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document no. ic-2913c (o. d. no. ic-8082d) date published january 1994 p printed in japan ? nec corporation 1991 the information in this document is subject to change without notice. description the m pd75308b is a 75x series 4-bit single-chip microcomputer capable of the same data processing as an 8-bit microcomputer. it is a low voltage operation version of the m pd75308 with on-chip lcd controller/driver. operation at an ultra-low voltage of 2.0 v is possible. an ultra small-sized plastic qfp (12 12 mm) is also provided and it is perfect for small-sized set that uses an lcd panel. functions, etc., are described in detail in the user's manual. please be sure to read this manual when carrying out design work. m pd75308 user's manual: iem-5016 features ultra-low-voltage operation possible: v dd = 2.0 to 6.0 v ? can be driven by two 1.5 v manganese batteries. on-chip memory ? program memory (rom) : 8064 8 bit ( m pd75308b) : 6016 8 bit ( m pd75306b) : 4096 8 bit ( m pd75304b) ? data memory (ram) : 512 4 bit instruction execution time adjustment function convenient in high-speed operation and power saving ? 0.95 m s, 1.91 m s, 15.3 m s (4.19 mhz operation) ? 122 m s (32.768 khz operation) built-in programmable lcd controller/driver ? lcd drive voltage: 2.0 v to v dd an ultra small-sized plastic qfp (12 12 mm) is provided. ? suitable for small-sized set, such as a camera. on-chip prom products available ? on-chip one-time prom products : m pd75p308, 75p316a ? on-chip eprom products : m pd75p308, 75p316b applications remote control, integrated camera type vcr, camera, gas meter, etc. unless there are any particular functional differences, the m pd75308b is described in this document as a representative product. the mark h shows major revised points. 4-bit single-chip microcomputer m pd75304b,75306b,75308b mos integrated circuit data sheet
2 m pd75304b,75306b,75308b ordering information ordering code package quality grade m pd75304bgc- -3b9 80-pin plastic qfp ( n n 14 mm) standard m pd75304bgf- -3b9 80-pin plastic qfp (14 20 mm) standard m pd75304bgk- -be9 80-pin plastic tqfp(fine pitch)( n n 12 mm) standard m pd75306bgc- -3b9 80-pin plastic qfp ( n n 14 mm) standard m pd75306bgf- -3b9 80-pin plastic qfp (14 20 mm) standard m pd75306bgk- -be9 80-pin plastic tqfp(fine pitch)( n n 12 mm)) standard m pd75308bgc- -3b9 80-pin plastic qfp ( n n 14 mm) standard m pd75308bgf- -3b9 80-pin plastic qfp (14 20 mm) standard m pd75308bgk- -be9 80-pin plastic tqfp(fine pitch)( n n 12 mm) standard remarks is the rom code number. please refer to quality grade on nec semiconductor devices (document number iei-1209) published by nec corporation to know the specification of quality grade on the devices and its recommended applications.
m pd75304b,75306b,75308b 3 function 41 0.95 m s, 1.91 m s, 15.3 m s (main system clock: 4.19 mhz operation) 122 m s (subsystem clock: 32.768 khz operation) 8064 8 bits ( m pd75308b), 6016 8 bits ( m pd75306b), 4096 8 bits ( m pd75304b) 512 4 bits ? 4-bit manipulation: 8 (b, c, d, e, h, l, x, a) ? 8-bit manipulation: 4 (bc, de, hl, xa) ? bit accumulator (cy) ? 4-bit accumulator (a) ? 8-bit accumulator (xa) ? various bit manipulation instructions ? efficient 4-bit data manipulation instructions ? 8-bit data transfer instructions ? geti instruction that can implement arbitrary 2-byte/3-byte instructions with 1 byte ? number of segments selection: 24/28/32 segments (4/8 can be switched at bit port output.) ? display mode selection: static, 1/2 duty, 1/3 duty (1/2 bias), 1/3 duty (1/3 bias), 1/4 duty ? lcd drive division resistor can be incorporated by mask option v dd = 2.0 to 6.0 v ? 8-bit timer/event counter ? clock source: 4 stages ? event count possible ? 8-bit basic interval timer ? standard clock generation: 1.95 ms, 7.82 ms, 31.3 ms, 250 ms (4.19 mhz operation) ? watchdog timer application possible function outline (1/2) item number of basic instructions instruction cycle on-chip memory general register accumulators instruction set i/o lines lcd controller/driver supply voltage range timer 8 cmos input pull-up by software possible : 23 16 cmos input/output 40 8 cmos output used with segment pin 8 10 v withstand voltage, pull-up by mask option possible : 8 3 channels rom ram n-ch open-drain input/output
4 m pd75304b,75306b,75308b function outline (2/2) function ? watch timer ? 0.5 seconds time interval generation ? count clock source: main system clock and subsystem clock switchable ? fast watch mode (3.9 ms time interval generation) ? buzzer output possible (2 khz) ? three modes application possible ? 3-wire serial i/o mode ? 2-wire serial i/o mode ? sbi mode ? lsb top/msb top switchable special bit manipulation memory: 16 bits ? perfect for remote control application timer/event counter output (pto0): arbitrary frequency square wave output clock output (pcl): f , 524, 262, 65.5 khz (4.19 mhz operation) buzzer output (buz): 2 khz (4.19 mhz or 32.768 khz operation) ? external: 3 ? internal: 3 ? external: 1 ? internal: 1 ? main system clock oscillation ceramic/crystal oscillation circuit: 4.194304 mhz ? subsystem clock oscillation crystal oscillation circuit: 32.768 khz stop/halt mode ? 80-pin plastic qfp (14 20 mm) ? 80-pin plastic qfp ( n n 14 mm) ? 80-pin plastic tqfp (fine pitch) ( n n 12 mm) item timer 8-bit serial interface bit sequential buffer clock output function vectored interrupt test input system clock oscillator standby package 3 channels
m pd75304b,75306b,75308b 5 contents 1. pin configuration (top view)............................................................................................... 6 2. block diagram............................................................................................................................ 8 3. pin functions .............................................................................................................................. 9 3.1 port pins .............................................................................................................................................. 9 3.2 non-port pins ..................................................................................................................................... 11 3.3 pin input/output circuits .............................................................................................................. 13 3.4 recommended connection of unused pins ............................................................................. 15 3.5 precautions concerning p00/int4 pin and reset pin ........................................................... 16 4. memory configuration .......................................................................................................... 16 5. peripheral hardware functions ........................................................................................ 21 5.1 ports ..................................................................................................................................................... 21 5.2 clock generator ............................................................................................................................... 22 5.3 clock output circuit ....................................................................................................................... 23 5.4 basic interval timer ........................................................................................................................ 24 5.5 watch timer ........................................................................................................................................ 25 5.6 timer/event counter ....................................................................................................................... 26 5.7 serial interface ................................................................................................................................. 28 5.8 lcd controller/driver .................................................................................................................... 30 5.9 bit sequential buffer ...................................................................................................................... 32 6. interrupt function ................................................................................................................. 32 7. standby function .................................................................................................................... 34 8. reset function .......................................................................................................................... 35 9. instruction set ......................................................................................................................... 37 10. mask option selection ............................................................................................................ 45 11. electrical specifications ...................................................................................................... 46 12. package information .............................................................................................................. 64 13. recommended soldering conditions ................................................................................ 67 appendix a. differences among series products .............................................................. 70 appendix b. development tools ............................................................................................... 72 appendix c. related documents .............................................................................................. 73
6 m pd75304b,75306b,75308b 1. pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 12 s27/bp3 s28/bp4 s29/bp5 s30/bp6 s31/bp7 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 48 47 46 45 44 43 42 41 49 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 s12 s13 s14 s15 s16 s17 s18 s19 s20 s21 s22 s23 s24/bp0 s25/bp1 s26/bp2 p60/kr0 x2 x1 nc xt2 xt1 v dd p33 p32 p31/sync p30/lcdcl p23/buz p22/pcl p21 p20/pto0 p13/ti0 p12/int2 p11/int1 p10/int0 p03/si/sb1 com0 com1 com2 com3 bias v lc0 v lc1 v lc2 p40 p41 p42 p43 v ss p50 p51 p52 p53 p00/int4 p01/sck p02/so/sb0 p71/kr5 p70/kr4 p63/kr3 p62/kr2 p61/kr1 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 reset p73/kr7 p72/kr6 m pd75304bgc- -3b9 m pd75304bgk- -be9 m pd75306bgc- -3b9 m pd75306bgk- -be9 m pd75308bgc- -3b9 m pd75308bgk- -be9
m pd75304b,75306b,75308b 7 p00 to 03 : port 0 p10 to 13 : port 1 p20 to 23 : port 2 p30 to 33 : port 3 p40 to 43 : port 4 p50 to 53 : port 5 p60 to 63 : port 6 p70 to 73 : port 7 bp0 to 7 : bit port kr0 to 7 : key return sck : serial clock si : serial input so : serial output sb0,1 : serial bus 0, 1 reset : reset input s27/bp3 s28/bp4 s29/bp5 s30/bp6 s31/bp7 s12 s13 s14 s15 s16 s17 s18 s19 s20 s21 s22 s23 s24/bp0 s25/bp1 s26/bp2 com0 com1 com2 com3 p23/buz p22/pcl p21 p20/pto0 p13/ti0 p70/kr4 p63/kr3 p62/kr2 p61/kr1 p60/kr0 x2 x1 nc xt2 xt1 v dd p33 p32 p31/sync p30/lcdcl p12/int2 p11/int1 p10/int0 p03/si/sb1 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 reset p73/kr7 p72/kr6 p71/kr5 bias v lc0 v lc1 v lc2 p40 p41 p42 p43 v ss p50 p51 p52 p53 p00/int4 p01/sck p02/so/sb0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 s0 to 31 : segment output 0 to 31 com0 to 3 : common output 0 to 3 v lc0-2 : lcd power supply 0 to 2 bias : lcd power supply bias control lcdcl : lcd clock sync : lcd synchronization ti0 : timer input 0 pto0 : programmable timer output 0 buz : buzzer clock pcl : programmable clock int0, 1, 4 : external vectored interrupt 0, 1, 4 int2 : external test input 2 x1, 2 : main system clock oscillation 1, 2 xt1, 2 : subsystem clock oscillation 1, 2 nc : no connection m pd75304bgf- -3b9 m pd75306bgf- -3b9 m pd75308bgf- -3b9
8 m pd75304b,75306b,75308b p ort 0 port 1 port 2 port 3 port 4 port 5 port 6 port 7 lcd control- ler /driver 4 4 4 4 4 4 4 4 24 8 4 3 p00-p03 p10-p13 p20-p23 p30-p33 p40-p43 p50-p53 p60-p63 p70-p73 s0-s23 s24/bp0 ?31/bp7 com0?om3 v lc0 ? lc2 bias lcdcl/p30 sync/p31 f lcd sp(8) bank general reg. data memory (ram) 512 4 bits decode and control cy alu program counter * reset v ss stand by control v dd cpu clock system clock generator sub main clock divider clock output control x2 x1 xt2 xt1 pcl/p22 f x / 2 n basic interval timer timer/event counter #0 watch timer clocked serial interface inter- rupt control bit seq. buffer (16) intcsi intw f lcd intbt intt0 kr0/p60 ?r7/p73 int4/p00 int2/p12 int1/p11 int0/p10 sck/p01 so/sb0/p02 si/sb1/p03 buz/p23 ti0/p13 pto0/p20 8 2. block diagram * 13bits : m pd75306b, 75308b 12bits : m pd75304b program memory (rom) 8064 8bits : m pd75308b 6016 8bits : m pd75306b 4096 8bits : m pd75304b
m pd75304b,75306b,75308b 9 3. pin functions 3.1 port pins (1/2) dual- function pin int4 sck so/sb0 si/sb1 int0 int1 int2 ti0 pto0 pcl buz lcdcl sync i/o circuit type *1 b f - a f - b m - c b - c e - b e - b m m *1. : schmitt trigger input 2. led direct drive possible with noise elimination function pin name p00 p01 p02 p03 p10 p11 p12 p13 p20 p21 p22 p23 p30 *2 p31 *2 p32 *2 p33 *2 p40 to p43 *2 p50 to p53 *2 input/output input input/output input/output input/output input input/output input/output input/output input/output function 4-bit input port (port 0) on-chip pull-up resistor can be specified for p01 to p03 as a 3-bit unit by software. 4-bit input port (port 1) on-chip pull-up resistor can be specified as a 4-bit unit by software. 4-bit input/output port (port 2) on-chip pull-up resistor can be specified as a 4-bit unit by software. programmable 4-bit input/output port (port 3) input/output can be specified bit-wise. on-chip pull-up resistor can be specified as a 4-bit unit by software. n-ch open-drain 4-bit input/output port (port 4) on-chip pull-up resistor can be specified bit- wise (mask option). open-drain: 10 v withstand voltage n-ch open-drain 4-bit input/output port (port 5) on-chip pull-up resistor can be specified bit- wise (mask option). open-drain: 10 v withstand voltage input input input input high level (on- chip pull-up resistor) or high- impedance high level (on- chip pull-up resistor) or high- impedance 8-bit i/o after reset
10 m pd75304b,75306b,75308b 3.1 port pins (2/2) dual- function pin kr0 kr1 kr2 kr3 kr4 kr5 kr6 kr7 s24 s25 s26 s27 s28 s29 s30 s31 *1. : schmitt trigger input 2. bp0 to bp7 select v lc1 as the input source. however, the output level depends on bp0 to bp7 and v lc1 external circuit. example bp0 to bp7 are connected mutually within the m pd75308b. therefore, the output level of bp0 to bp7 is determined by the value of r 1 , r 2 and r 3 . m pd75308b on on v lc1 r 1 r 3 bp0 bp1 r 2 v dd pin name p60 p61 p62 p63 p70 p71 p72 p73 bp0 bp1 bp2 bp3 bp4 bp5 bp6 bp7 input/output input/output input/output output output function programmable 4-bit input/output port (port 6) input/output can be specified bit-wise. on-chip pull-up resistor can be specified as a 4-bit unit by software. 4-bit input/output port (port 7) on-chip pull-up resistor can be specified as a 4-bit unit by software. 1-bit output port (bit port) also used as segment output pin. 8-bit i/o input input * 2 i/o circuit type *1 f - a f - a g - c after reset
m pd75304b,75306b,75308b 11 xt1 xt2 reset nc *5 v dd v ss function external event pulse input pin to timer/event counter timer/event counter output pin clock output pin fixed frequency output pin (for buzzer or system clock trimming) serial clock input/output pin serial data output pin serial bus input/output pin serial data input pin serial bus input/output pin edge detection vectored interrupt input pin (both rising edge and falling edge detection effective) edge detection vectored interrupt input pin (detection edge selectable) edge detection testable input pin (rising edge detection) parallel falling edge detection testable input pin parallel falling edge detection testable input pin segment signal output pin segment signal output pin common signal output pin lcd drive power supply pin on-chip split resistor (mask option) external split resistor cut output pin external expansion driver drive clock output pin external expansion driver synchronization clock output pin main system clock oscillation crystal/ceramic connection pin. for external clock, the external clock signal is input to x1 and its opposite phase is input to x2. subsystem clock oscillation crystal connection pin. for external clock, the external clock signal is input to xt1 and xt2 is opened. xt1 can be used as a 1-bit input (test) pin. system reset input pin no connection positive power supply pin gnd potential pin pin name ti0 pto0 pcl buz sck so/sb0 si/sb1 int4 int0 int1 int2 kr0 to kr3 kr4 to kr7 s0 to s23 s24 to s31 com0 to com3 v lc0 to v lc2 bias lcdcl *4 3.2 non-port pins dual- function pin p13 p20 p22 p23 p01 p02 p03 p00 p10 p11 p12 p60 to p63 p70 to p73 bp0 to bp7 p30 p31 clock synchronous system asynchronous asynchronous *1. : schmitt trigger input 2. display outputs are selected with v lcx shown below as the input source. s0 to s31: v lc1 , com0 to com2: v lc2 , com3: v lc0 however, the level of each display output depends on the display output and v lcx external circuit. input/output input input/output input/output input/output input/output input/output input/output input input input input/output input/output output output output output input/output input/output input input input input input input input input input input input input input input input *2 *2 *2 *3 input input sync *4 x1, x2 after reset i/o circuit type *1 b - c e - b e - b e - b f - a f - b m - c b b - c b - c f - a f - a g - a g - c g - b e - b e - b b
12 m pd75304b,75306b,75308b *3. on-chip split resistor ........ low level no on-chip split resistor ... high-impedance 4. pins provided for system expansion. currently, only used as p30 and p31. 5. if a printed wiring board is shared with the m pd75p316a/75p316b, the nc pin should be connected to v dd .
m pd75304b,75306b,75308b 13 3.3 pin input/output circuits the input/output circuits of each pin of the m pd75308b are shown by in abbreviated form. p-ch v dd out n-ch data output disable schmitt-trigger input with hysteresis characteristic p-ch v dd in n-ch p.u.r. p-ch in/out p.u.r. enable data output disable type d type a p.u.r. : pull-up resistor v dd p.u.r. p-ch in/out p.u.r. enable data output disable type d type b p.u.r. : pull-up resistor v dd cmos standard input buffer push-pull output that can be made high-impedance output (p-ch and n-ch off) type a (for type e-b) type d (for type e-b, f-a) type b type e-b type f-a type b-c in in p-ch p.u.r. p.u.r. enable v dd p.u.r. : pull-up resistor
14 m pd75304b,75306b,75308b p-ch v lc0 v lc1 v lc2 p-ch n-ch out seg data/bit port data n-ch v dd n-ch p-ch out seg data p-ch v lc0 v lc1 v lc2 n-ch v lc0 v lc1 v lc2 com data n-ch p-ch p-ch n-ch out n-ch p-ch type f-b type g-c type m type g-a type g-b type m-c p.u.r. enable p.u.r. : pull-up resistor v dd in/out n-ch data output disable (mask option) middle-high voltage input buffer (+10 v withstand voltage) p.u.r. enable in/out p-ch v dd n-ch data output disable p.u.r. : pull-up resistor p.u.r. p.u.r. in/out p.u.r. enable output disable (p) output disable data output disable (n) v dd v dd p-ch n-ch p-ch p.u.r. : pull-up resistor
m pd75304b,75306b,75308b 15 3.4 recpmmended connection of unused pins table 3-1 connection of unused pins pin recommended connection p00/int4 connect to v ss p01/sck p02/so/sb0 connect to v ss or v dd p03/si/sb1 p10/int0-p12/int2 p13/ti0 p20/pto0 p21 p22/pcl p23/buz p30/lcdcl p31/sync p32 p33 p40 to p43 p50 to p53 p60/kr0 to p63/kr3 p70/kr4 to p73/kr7 s0 to s23 s24/bp0 to s31/bp7 leave open com0 to com3 v lc0 to v lc2 connect to v ss bias connect to v ss only when v lc0 to v lc2 are all unused; otherwise leave open xt1 connect to v ss or v dd xt2 leave open connect to v ss h input state : connect to v ss or v dd outputstate : leave open
16 m pd75304b,75306b,75308b 3.5 precautions concerning p00/int4 pin and reset pin in addition to the functions shown in 3.1 and 3.2, the p00/int4 pin and reset pin are also used to set the test mode for testing internal m pd75308b operation (for ic testing). the test mode is set when a voltage greater than v dd is applied to either of these pins. consequently, if noise exceeding v dd is applied during normal operation, the test mode may be entered, making it impossible for normal operation to continue. for example, misoperation may result if inter-wiring noise is applied to the p00/int4 or reset pin due to the length of the wiring from these pins, and the pin voltage exceeds v dd . wiring should therefore be carried out so that inter-wiring noise is suppressed as far as possible. if it is completely impossible to suppress noise, noise prevention measures should be taken using an external compo- nent as shown below. o diode connected between p00/int4 or reset and v dd o capacitor connected between p00/int4 or reset and v dd diode with small v f v dd v dd v dd p00/int4, reset v dd p00/int4, reset 4. memory configuration program memory (rom) ... 8064 8 bits (0000h to 1f7fh): m pd75308b 6016 8 bits (0000h to 177fh): m pd75306b 4096 8 bits (0000h to 0fffh): m pd75304b ? 0000h to 0001h: vector table in which the program start address after a reset is written. ? 0002h to 000bh: vector table in which program start addresses in case of interrupts are written. ? 0020h to 007fh: table area referenced by the geti instruction. data memory ? data area ... 512 4 bits (000h to 1ffh) ? peripheral hardware area ... 128 4 bits (f80h to fffh) h
m pd75304b,75306b,75308b 17 fig. 4-1 program memory map (a) m pd75308b ? ? ? ? ? ? ? mbe 0 0 mbe 0 0 mbe 0 0 mbe 0 0 mbe 0 0 mbe 0 0 0000h 0002h 0004h 0006h 0008h 000ah 0020h 007fh 0080h 07ffh 0800h 0fffh 1000h 1f7fh 7 6 5 0 address internal reset start address (high-order 5 bits) internal reset start address (low-order 8 bits) intbt/int4 start address (high-order 5 bits) int0 start address (high-order 5 bits) intbt/int4 start address (low-order 8 bits) int0 start address (low-order 8 bits) int1 start address (high-order 5 bits) int1 start address (low-order 8 bits) intcsi start address (high-order 5 bits) intcsi start address (low-order 8 bits) intt0 start address (high-order 5 bits) intt0 start address (low-order 8 bits) geti instruction reference table callf ! faddr instruction entry address brcb ! caddr instruction branch address call !addr instruction subroutine entry address br !addr instruction branch address br $addr instruction relative branch address (-15 to -1, +2 to +16) branch destination address and subroutine entry address by geti instruction ? brcb ! caddr instruction branch address
18 m pd75304b,75306b,75308b (b) m pd75306b ? ? ? ? ? ? ? mbe 0 0 mbe 0 0 mbe 0 0 mbe 0 0 mbe 0 0 mbe 0 0 0000h 0002h 0004h 0006h 0008h 000ah 0020h 007fh 0080h 07ffh 0800h 0fffh 1000h 177fh 7 6 5 0 address internal reset start address (high-order 5 bits) internal reset start address (low-order 8 bits) intbt/int4 start address (high-order 5 bits) int0 start address (high-order 5 bits) intbt/int4 start address (low-order 8 bits) int0 start address (low-order 8 bits) int1 start address (high-order 5 bits) int1 start address (low-order 8 bits) intcsi start address (high-order 5 bits) intcsi start address (low-order 8 bits) intt0 start address (high-order 5 bits) intt0 start address (low-order 8 bits) geti instruction reference table callf ! faddr instruction entry address brcb ! caddr instruction branch address call !addr instruction subroutine entry address br !addr instruction branch address br $addr instruction relative branch address (-15 to -1, +2 to +16) branch destination address and subroutine entry address by geti instruction ? brcb ! caddr instruction branch address
m pd75304b,75306b,75308b 19 (c) m pd75304b ? ? ? ? ? mbe 0 0 mbe 0 0 mbe 0 0 mbe 0 0 mbe 0 0 mbe 0 0 0000h 0002h 0004h 0006h 0008h 000ah 0020h 007fh 0080h 07ffh 0800h 0fffh 7 6 5 0 address internal reset start address (high-order 4 bits) internal reset start address (low-order 8 bits) intbt/int4 start address (high-order 4 bits) int0 start address (high-order 4 bits) intbt/int4 start address (low-order 8 bits) int0 start address (low-order 8 bits) int1 start address (high-order 4 bits) int1 start address (low-order 8 bits) intcsi start address (high-order 4 bits) intcsi start address (low-order 8 bits) intt0 start address (high-order 4 bits) intt0 start address (low-order 8 bits) geti instruction reference table callf ! faddr instruction entry address call !addr instruction subroutine entry address br !caddr instruction branch address br $addr instruction relative branch address (-15 to -1, +2 to +16) branch destination address and subroutine entry address by geti instruction ?
20 m pd75304b,75306b,75308b fig. 4-2 data memory map (32 4) 256 4 (248 4) 256 4 (224 4) 128 4 (8 4) 0 1 15 000h 007h 008h 0ffh 100h 1dfh 1e0h 1ffh f80h fffh general register area stack area data area static ram (512 4) display data memory area peripheral hardware area data memory memory bank not on-chip
m pd75304b,75306b,75308b 21 5. peripheral hardware functions 5.1 ports there are four kinds of i/o ports, as follows. cmos input (port0, 1) : 8 cmos input/output (port2, 3, 6, 7) : 16 n-ch open drain (port4, 5) : 8 cmos output (bp0 to bp7) : 8 total 40 fig. 5-1 port functions port (symbol) function operation/features remarks dual function as int4, sck, so/ sb0 & si/sb1 pins dual function as pins int0 to int2 & ti0 dual function as pto0, pcl & buz pins dual function as pins kr4 to kr7 dual function as lcdcl & sync pins dual function as pins kr0 to kr3 incorporation of pull-up resistor can be specified bit-wise by mask option. small drive capability. for cmos load drive. port 0 port 1 port 2 port 7 port 3 * port 6 port 4 * port 5 * bp0 to bp7 4-bit input 4-bit input/output 4-bit input/output (n-ch open-drain 10 v withstand voltage) 1-bit output always readable or testable irrespective of dual-function pin operating mode. can be set to input or output mode as 4-bit unit. ports 6 & 7 can be paired for 8-bit data input/output. can be set to input or output mode bit-wise. can be set to input or output mode as 4-bit unit. ports 4 & 5 can be paired for 8-bit data input/output. outputs data bit-wise. switchable by software with lcd drive segment outputs s24 to s31. * direct led drive capability
22 m pd75304b,75306b,75308b 5.2 clock generator the operation of the clock generator is determined by the processor clock control register (pcc) and system clock control register (scc). there are two kinds of clock, the main system clock and subsystem clock, and the instruction execution time can be changed. 0.95 m s/1.91 m s/15.3 m s (4.19 mhz main system clock operation) 122 m s (32.768 khz subsystem clock operation) fig. 5-1 clock generator block diagram remarks 1. f x = main system clock frequency 2. f xt = subsystem clock frequency 3. pcc: processor clock control register 4. scc: system clock control register 5. * indicates instruction execution. 6. one f clock cycle (t cy ) is one machine cycle. see "ac characteristics" in 11. "electrical specifications" for details of t cy . h subsystem clock oscil- lation circuit xt1 xt2 x1 x2 v dd v dd f xt f x lcd controller/ driver watch timer ?basic interval timer (bt) ?timer/event counter ?serial interface ?watch timer ?lcd controller/driver ?int0 noise elimination circuit ?clock output circuit 1/8 to 1/4096 frequency divider 1/2 selector selector frequency divider 1/4 ?cpu ?int0 noise elimination circuit ?clock output circuit halt f/f wait release signal from bt reset signal standby release signal from interrupt control circuit stop f/f s r q pcc2, pcc3 clear oscil- lation stop wm. 3 scc pcc 4 internal bus main system clock oscil- lation circuit s r q pcc0 pcc1 pcc2 pcc3 scc3 scc0 halt * stop * f 1/16
m pd75304b,75306b,75308b 23 remarks consideration is given so that a low amplitude pulse is not output when switching between clock output enable and disable. 5.3 clock output circuit the clock output circuit is a circuit which outputs a clock pulse from p22/pcl pin and is used to supply clock pulses to remote control outputs or peripheral lsis. clock output (pcl) : f 524, 262, 65.5 khz (at 4.19 mhz operation) buzzer output (buz): 2 khz (at 4.19 mhz or 32.768 khz operation) the configuration of the clock output circuit is shown below. fig. 5-2 clock output circuit configuration clom3 clom1 clom0 0 f internal bus clom p22 output latch port2.2 bit 2 of pmgb bit specified in port 2 input/output mode output buffer pcl/p22 f x /2 3 f x /2 4 f x /2 6 4 selector from clock generator
24 m pd75304b,75306b,75308b 5.4 basic interval timer the basic interval timer includes the following functions. it operates as an interval timer which generates reference time interrupts. it can be applied as a watchdog timer which detects when a program is out of control. selects and counts wait times when the standby mode is released. it reads count contents. fig. 5-3 basic interval timer configuration remarks * indicates instruction execution. internal bus f x /2 5 f x /2 7 f x /2 12 from clock generator 4 btm3 btm2 btm1 btm0 btm mpx bt irqbt set bt interrupt request flag clear clear basic interval timer (8-bit frequency divider) wait release signal during standby release 8 3 vectored interrupt request signal f x /2 9 * set1
m pd75304b,75306b,75308b 25 5.5 watch timer the m pd75308b incorporates a single watch timer channel. the watch timer has the following functions. sets test flags (irqw) at 0.5 second intervals. the standby mode can be released with irqw. 0.5 sec. time intervals can be created in either the main system clock or the subsystem clock. in the fast watch mode, time intervals which are 128 times normal (3.91 ms) can be set, making this function convenient for program debugging and testing. a fixed frequency (2.048 khz) can be output to the p23/buz pin for use in generating buzzer sounds and trimming system clock oscillation frequencies. the frequency divider can be cleared, so this clock can be started at 0 second. fig. 5-4 watch timer block diagram remarks values in parentheses are when f x = 4.194304 mhz and f xt = 32.768 khz. 8 internal bus wm7 0 0 0 wm3 wm2 wm1 wm0 bit test instruction p23 output latch port 2 input/output mode port2.3 bit 2 of pmgb p23/buz output buffer selector frequency divider clear (2.048 khz) f lcd 2 14 f w 2 6 f w (512 hz : 1.95 ms) 2 7 f w (256 hz : 3.91 ms) f w (32.768 khz) selector wm from clock generator 16 f w 128 f w (32.768 khz) f xt (32.768 khz) intw irqw set signal 2hz 0.5 sec
26 m pd75304b,75306b,75308b 5.6 timer/event counter the m pd75308b incorporates a single timer/event counter channel. the timer/event counter has the following functions. operates as a programmable interval timer. outputs square waves in the desired frequency to the pto0 pin. operates as an event counter. divides the ti0 pin input into n divisions and outputs it to the pto0 pin (frequency divider operation). supplies a serial shift clock to the serial interface circuit. count status read function.
m pd75304b,75306b,75308b 27 fig. 5-5 timer/event counter block diagram *1 set1: instruction execution 2 for detail, see fig. 5-1. p13/ti0 port1.3 input buffer from clock generator *2 mpx tm06 tm05 tm04 tm03 tm02 set1 *1 tm0 timer operation start cp count register (8) clear 8 comparator (8) 8 8 modulo register (8) 8 8 internal bus tmod0 match reset tout f/f toe0 to enable flag p20 output latch port2.0 bit 2 of pgmb port 2 input/ output mode to serial interface p20/pto0 output buffer intt0 irqt0 set signal reset irqt0 clear signal t0
28 m pd75304b,75306b,75308b 5.7 serial interface the m pd75308b incorporates a clocked 8-bit serial interface. the serial interface has the following three modes. 3-wire serial i/o mode 2-wire serial i/o mode sbi mode (serial bus interface mode)
m pd75304b,75306b,75308b 29 fig. 5-6 serial interface block diagram f x /2 3 (from timer/ event counter) intcsi irqcsi set signal serial clock slector intcsi control circuit reld serial clock counter serial clock control circuit p01/sck p03/si/sb1 p02/so/sb0 selector 8/4 csim bit test 8 8 internal bus 8 slave address register (sva) addres comparator shift register (sio) match signal relt bit manipulation cmdt so latch set clr q d sbic bit test busy/ acknowledge output circuit ackt (8) (8) (8) cmdd ackd acke bsye bus release/ command/ acknowledge detection circuit selector f x /2 4 f x /2 6 tout f/f external sck p01 output latch ? ? ? ?
30 m pd75304b,75306b,75308b 5.8 lcd controller/driver the m pd75308b has an on-chip display controller which generates segment signals and common signals in accordance with data in display data memory as well as a segment driver and common driver capable of directly driving the lcd panel. the configuration of the lcd controller/driver is shown in fig. 5-7 the functions of the on-chip lcd controller/driver of the m pd75308b are as follows. display data memory are read automatically through dma operations and segment signals and common signals are generated. 5 different display modes can be selected. static 1/2 duty (1/2 bias) a 1/3 duty (1/2 bias) 1/3 duty (1/3 bias) ? 1/4 duty (1/3 bias) in each of the display modes, 4 types of frame frequency can be selected. the segment signal output is a maximum of 32 segments (s0 to s31) and 4 common outputs (com0 to com3). segment signal outputs (s24 to s27, s28 to s31) are in 4-segment units and they can be switched for use as output ports (bp0 to bp3, bp4 to bp7). split resistors can be built-in for the lcd driver power supply (mask option). conformity to various bias methods and lcd driver voltages is possible. when the display is off, the current flowing to the split resistors is cut. display data memory not used for the display can be used as ordinary data memory. operation by the subsystem clock is also possible. . 4
m pd75304b,75306b,75308b 31 fig. 5-7 lcd controller/driver block diagram 8 port mode register group a port 3 output latch display control register 4 4 0 1e0h 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 2 3 1e8h 1e9h 1feh 1ffh display data memory multi- plexer s30/pb6 s24/pb0 s23 s0 common driver com3 com2 com1 com0 v lc2 v lc1 v lc0 p31/ sync p30/ lcdcl f lcd 0 1 0 1 segment driver display mode register timing controller 8 4 1 selector lcd driver voltage control s31/pb7
32 m pd75304b,75306b,75308b 5.9 bit sequential buffer ..... 16 bits the bit sequential buffer is special data memory for bit manipulations and can be used easily particularly for bit manipulations where addresses and bit specifications are changed sequentially, so it is convenient for processing data with long bit lengths bit-wise. fig. 5-8 bit sequential buffer format remarks in pmem.@l addressing, the specified bit corresponding to the l register is moved. 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 l = 0 l = 3 l = 4 decs l l = 7 l = 8 incs l l = b l = c l = f fc3h fc2h fc1h fc0h symbol address bit l register bsb3 bsb2 bsb1 bsb0 6. interrupt function the m pd75218has 8 interrupt sources, and prioritized multiple interrupts are possible. there are also two test sources, of which int2 is an edge-detected testable input. the m pd75218 interrupt control circuit has the following functions hardware control vectored interrupt function that can control interrupt acceptance by interrupt flag (ie ) and interrupt master enable flag (ime). arbitrary setting of interrupt start address. multiple interrupt function with priority specifiable by the interrupt priority selection register (ips). interrupt request flag (irq ) test function (interrupt generation confirmation by software possible). standby mode release (selection of interrupt that releases the standby mode by interrupt enable flag possible).
m pd75304b,75306b,75308b 33 fig. 6-1 interrupt control circuit block diagram * noise elimination circuit 2 1 3 im2 im1 im0 irqbt int4 /p00 int0 /p10 int1 /p11 int2 /p12 kr0/p60 kr7/p73 irq4 irq0 irq1 irqcsi irqt0 irqw irq2 int bt intcsi intt0 intw im2 ime ist0 vrqn internal bus vector table address generator priority control circuit standby release signal interrupt enable flag (ie xxx ) rising edge detection circuit falling edge detection circuit edge detection circuit edge detection circuit both edges detection circuit decoder selector *
34 m pd75304b,75306b,75308b 7. standby function to reduce the power consumption during program wait, the m pd75308b has two standby modes: stop mode and halt mode. table 7-1 operation status at standby mode stop mode stop instruction only main system clock settable only main system clock oscillation stopped stopped operable only when external sck input selected as serial clock operable only when ti0 pin input specified as count clock operable only when f xt selected as count clock operable only when f xt selected as lcdcl int1, 2, 4: operable only int0 inoperable stopped interrupt request signal from operable hardware enabled by interrupt enable flag, or reset input setting instruction system clock at setting clock oscillator basic interval timer serial interface timer/event counter watch timer lcd controller external interrupt cpu release signal operation status halt mode halt instruction main system clock or subsystem clock settable only cpu clock f stopped (oscillation continued) operating (irqbt set at reference time intervals) * operable * operable * operable operable interrupt request signal from operable hardware enabled by interrupt enable flag, or reset input * in-operable only with main system clock oscillation stopped.
m pd75304b,75306b,75308b 35 8. reset function the m pd75308b is reset and the hardware is initialized as shown in table 8-1 by reset input. the reset operation timing is shown in fig. 8-1. fig. 8-1 reset operation by reset input wait (31.3 ms/4.19 mhz) halt mode operating mode internal reset operation operating mode or standby mode reset input table 8-1 status of each hardware after resetting (1/2) hardware program counter (pc) carry flag (cy) skip flag (sk0 to 2) psw interrupt status flag (ist0) bank enable flag (mbe) stack pointer (sp) data memory (ram) general register (x, a, h, l, d, e, b, c) bank selection register (mbs) *1. figures in parentheses apply to the m pd75304b. 2. data of data memory addresses 0f8h to 0fdh becomes undefined by reset input. reset input in standby mode low-order 5(4) *1 bits of program memory address 0000h are set in pc12(11) *1 to 8 and the contents of address 0001h are set in pc7 to 0. held 0 0 bit 7 of program memory address 0000h is set in mbe. undefined held *2 held 0 reset input during operation low-order 5(4) *1 bits of program memory address 0000h are set in pc12(11) *1 to 8 and the contents of address 0001h are set in pc7 to 0. undefined 0 0 bit 7 of program memory address 0000h is set in mbe. undefined undefined undefined 0
36 m pd75304b,75306b,75308b table 8-1 status of each hardware after resetting (2/2) reset input during operation hardware counter (bt) mode register (btm) counter (to) modulo register (tmod0) mode register (tm0) toe0, tout f/f mode register (wm) shift register (sio) operating mode register (csim) sbi control register (sbic) slave address register (sva) processor clock control register (pcc) system clock control register (scc) clock output mode register (clom) display mode register (lcdm) display control register (lcdc) interrupt request flag (irq ) interrupt enable flag (ie ) interrupt master enable flag (ime) int0, 1, 2 mode registers (im0, 1, 2) output buffer output latch i/o mode register (pmga, b) pull-up resistor specification register (poga) reset input in standby mode undefined 0 0 ffh 0 0,0 0 held 0 0 held 0 0 0 0 0 reset (0) 0 0 0, 0, 0 off clear (0) 0 0 held undefined 0 0 ffh 0 0,0 0 undefined 0 0 undefined 0 0 0 0 0 reset (0) 0 0 0, 0, 0 off clear (0) 0 0 undefined basic interval timer timer/event counter watch timer serial interface clock generator, clock output circuit lcd controller interrupt function digital port bit sequential buffer (bsb0 to 3)
m pd75304b,75306b,75308b 37 9. instruction set (1) operand identifier and description the operand is described in the operand field of each instruction in accordance with the description for the operand identifier of the instruction. (see the ra75x assembler package user's manual language volume (eeu-730) for details.) when there are multiple elements in the description, one of the elements is selected. upper case letters and symbols (+,C) are keywords and are described unchanged. for immediate data, a suitable value or label is described. various register or flag symbols can be used as a label instead of mem, fmem, pmem, bit, etc. (see the m pd75308 users manual (iem-5016) for details). however, there are restrictions on the labels for which fmem and pmem can be used (see the table on the previous page). identifier description reg x, a, b, c, d, e, h, l regl x, b, c, d, e, h, l rp xa, bc, de, hl rpl bc, de, hl rp2 bc, de rpa hl, de, dl rpal de, dl n4 4-bit immediate data or label n8 8-bit immediate data or label mem * 8-bit immediate data or label bit 2-bit immediate data or label fmem fb0h to fbfh, ff0h to fffh immediate data or label pmem fc0h to fffh immediate data or label m pd75304b 0000h to 0fffh immediate data or lebel addr m pd75306b 0000h to 177fh immediate data or lebel m pd75308b 0000h to 1f7fh immediate data or lebel caddr 12-bit immediate data or label faddr 11-bit immediate data or label taddr 20h to 7fh immediate data (however, bit0 = 0) or label portn port 0 to port 7 ie iebt, iecsi, iet0, ie0, ie1, ie2, ie4, iew mbn mb0, mb1, mb15 * only an even address can be written for mem in the case of 8-bit data processing.
38 m pd75304b,75306b,75308b (2) operation description legend a : a register; 4-bit accumulator b : b register; c : c register; d : d register; e : e register; h : h register; l : l register; x : x register; 4-bit accumulator xa : register pair (xa); 8-bit accumulator bc : register pair (bc) de : register pair (de) hl : register pair (hl) pc : program counter sp : stack pointer cy : carry flag; bit accumulator psw : program status word mbe : memory bank enable flag portn : portn (n = 0 to 7) ime : interrupt master enable flag ie : interrupt enable flag mbs : memory bank selection register pcc : processor clock control register ? : address, bit delimiter ( ) : contents addressed by h : hexadecimal data
m pd75304b,75306b,75308b 39 data memory addressing (3) description of addressing area field symbols remarks 1. mb indicates the accessible memory bank. 2. for * 2, mb = 0 without regard to mbe and mbs. 3. for * 4 and * 5, mb = 15 without regard to mbe and mbs. 4. * 6 to * 10 indicate the addressable area. (4) explanation of machine cycle field s shows the number of machine cycles required when skip is performed by an instruction with skip. the value of s changes as follows: ? no skip ....................................................................................................................................................................... s = 0 ? when instruction to be skipped is 1-byte or 2-byte instruction ......................................................................... s = 1 ? when instruction to be skipped is 3-byte instruction (br !addr, call !addr instruction) ............................. s = 2 note one machine cycle is required to skip a geti instruction. one machine cycle is equivalent to one cycle (=t cy ) of the cpu clock f . three times can be selected by pcc setting. program memory addressing mb = mbe ? mbs (mbs = 0, 1, 15) mb = 0 mbe = 0 : mb = 0 (00h to 7fh) mb = 15 (80h to ffh) mbe = 1 : mb = mbs (mbs = 0, 1, 15) mb = 15, fmem = fb0h to fbfh, ff0h to fffh mb = 15, pmem = fc0h to fffh m pd75304b addr=0000h to 0fffh m pd75306b addr=0000h to 177fh m pd75308b addr=0000h to 1f7fh addr = (current pc) C15 to (current pc) C1 (current pc) + 2 to (current pc) + 16 m pd75304b caddr= 0000h to 0fffh m pd75306b caddr= 0000h to 0fffh (pc 12 =0) or 1000h to 177fh (pc 12 =1) m pd75308b caddr=0000h to 0fffh (pc 12 =0) or 1000h to 1f7fh (pc 12 =1) faddr = 0000h to 07ffh taddr = 0020h to 007fh *1 *2 *3 *4 *5 *6 *7 *8 *9 *10
40 m pd75304b,75306b,75308b stack a stack a stack b carry carry borrow address- ing area operand skip condition a, #n4 regl, #n4 xa, #n8 hl, #n8 rp2, #n8 a, @hl a, @rpal xa, @hl @hl, a @hl, xa a, mem xa, mem mem, a mem, xa a, reg xa, rp regl, a rpl, xa a, @hl a, @rpal xa, @hl a, mem xa, mem a,regl xa, rp xa, @pcde xa, @pcxa a, #n4 a, @hl a, @hl a, @hl a, @hl *1 *2 *1 *1 *1 *3 *3 *3 *3 *1 *2 *1 *3 *3 *1 *1 *1 *1 note instruction group mne- monic mov xch movt adds addc subs subc operation table reference transfer note bytes machine cycles a ? n4 regl ? n4 xa ? n8 hl ? n8 rp2 ? n8 a ? (hl) a ? (rpal) xa ? (hl) (hl) ? a (hl) ? xa a ? (mem) xa ? (mem) (mem) ? a (mem) ? xa a ? reg xa ? rp regl ? a rpl ? xa a ? (hl) a ? (rpal) xa ? (hl) a ? (mem) xa ? (mem) a ? regl xa ? rp l m pd75304b xa ? (pc 11C8 + de) rom l m pd75306b, 75308b xa ? (pc 12C8 + de) rom l m pd75304b xa ? (pc 11C8 + xa) rom l m pd75306b, 75308b xa ? (pc 12C8 + xa) rom a ? a + n4 a ? a + (hl) a, cy ? a + (hl) + cy a ? a C (hl) a, cy ? a C (hl) C cy operation 1 2 2 2 2 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 2 2 2 1 2 1 1 1 1 1 1 1 1 2 2 2 2 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 2 2 2 1 2 3 3 1 + s 1 + s 1 1 + s 1
m pd75304b,75306b,75308b 41 operand operation address- ing area skip condition a, #n4 a, @hl a, #n4 a, @hl a, #n4 a, @hl a a reg @hl mem reg reg, #n4 @hl, #n4 a, @hl a, reg cy cy cy cy mem.bit fmem.bit pmem.@l @h + mem.bit mem.bit fmem.bit pmem.@l @h + mem.bit mem.bit fmem.bit pmem.@l @h + mem.bit mem.bit fmem.bit pmem.@l @h + mem.bit 2 1 2 1 2 1 1 2 1 2 2 1 2 2 1 2 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 *1 *1 *1 *1 *3 *1 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 reg = 0 (hl) = 0 (mem) = 0 reg = fh reg = n4 (hl) = n4 a = (hl) a = reg cy = 1 (mem.bit) = 1 (fmem.bit) = 1 (pmem.@l) = 1 (@h + mem.bit) = 1 (mem.bit) = 0 (fmem.bit) = 0 (pmem.@l) = 0 (@h + mem.bit) = 0 note 1. instruction group 2. accumulator operation 3. increment and decrement 4. carry flag operation mne- monic and or xor rorc not incs decs ske set1 clr1 skt not1 set1 clr1 skt skf bytes machine cycles 2 1 2 1 2 1 1 2 1 + s 2 + s 2 + s 1 + s 2 + s 2 + s 1 + s 2 + s 1 1 1 + s 1 2 2 2 2 2 2 2 2 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s a a ? n4 a a ? (hl) a a M n4 a a M (hl) a a M n4 a a M (hl) cy a 0 , a 3 cy, a nC1 a n a a reg reg + 1 (hl) (hl) + 1 (mem) (mem) + 1 reg reg C 1 skip if reg = n4 skip if (hl) = n4 skip if a = (hl) skip if a = reg cy 1 cy 0 skip if cy = 1 cy cy (mem.bit) 1 (fmem.bit) 1 (pmem 7C2 + l 3C2 .bit (l 1C0 )) 1 (h + mem 3C0 .bit) 1 (mem.bit) 0 (fmem.bit) 0 (pmem 7C2 + l 3C2 .bit (l 1C0 )) 0 (h + mem 3C0 .bit) 0 skip if (mem.bit) = 1 skip if (fmem.bit) = 1 skip if (pmem 7C2 + l 3C2 .bit (l 1C0 )) = 1 skip if (h + mem 3C0 .bit) = 1 skip if (mem.bit) = 0 skip if (fmem.bit) = 0 skip if (pmem 7C2 + l 3C2 .bit (l 1C0 )) = 0 skip if (h + mem 3C0 .bit) = 0 note 2 note 3 comparison note 4 memory bit manipulation operation note 1
42 m pd75304b,75306b,75308b operation skip condition operand mne- monic address- ing area *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *6 *6 *7 *8 *6 (fmem.bit) = 1 (pmem.@l) = 1 (@h + mem.bit) = 1 2 2 2 2 2 2 2 2 2 2 2 2 3 1 2 3 fmem.bit pmem.@l @h + mem.bit cy, fmem.bit cy, pmem.@l cy, @h + mem.bit cy, fmem.bit cy, pmem.@l cy, @h + mem.bit cy, fmem.bit cy, pmem.@l cy, @h + mem.bit addr !addr $addr !caddr !addr note instruction group note sktclr and1 or1 xor1 br brcb call bytes machine cycles 2 + s 2 + s 2 + s 2 2 2 2 2 2 2 2 2 3 2 2 3 subroutine stack control branch memory bit manipulation skip if (fmem.bit) = 1 and clear skip if (pmem 7C2 + l 3C2 .bit (l 1C0 )) = 1 and clear skip if (h + mem 3C0 .bit) = 1 and clear cy cy ? (fmem.bit) cy cy ? (pmem 7C2 + l 3C2 .bit (l 1C0 )) cy cy ? (h + mem 3-0 .bit) cy cy M (fmem.bit) cy cy M (pmem 7C2 + l 3C2 .bit (l 1C0 )) cy cy M (h + mem 3-0 .bit) cy cy M (fmem.bit) cy cy M (pmem 7C2 + l 3C2 .bit (l 1C0 )) cy cy M (h + mem 3-0 .bit) l m pd75304b pc 11e0 ? addr (the assembler selects the optimum instruction from among the brcb !caddr, and br $addr instructions.) l m pd75306b, 75308b pc 12e0 ? addr (the assembler selects the optimum instruction from among the br !addr, brcb !caddr, and br $addr instructions.) l m pd75306b, 75308b pc 12e0 ? addr l m pd75304b pc 11e0 ? addr l m pd75306b, 75308b pc 12e0 ? addr l m pd75304b pc 11e0 ? caddr 11e0 l m pd75306b, 75308b pc 12e0 ? pc 12 + caddr 11e0 l m pd75304b (sp e 4) (sp e 1) (sp e 2) ? pc 11e0 (sp e 3) ? mbe, 0, 0, 0 pc 11e0 ? addr, sp ? sp e 4 l m pd75306b, 75308b (sp e 4) (sp e 1) (sp e 2) ? pc 11e0 (sp e 3) ? mbe, 0, 0, pc 12 pc 12e0 ? addr, sp ? sp e 4
m pd75304b,75306b,75308b 43 operation skip condition operand mne- monic address- ing area l m pd75304b (sp e 4) (sp e 1) (sp e 2) ? pc 11e0 (sp e 3) ? mbe, 0, 0, 0 pc 11e0 ? 0, faddr, sp ? sp e 4 l m pd75306b, 75308b (sp e 4) (sp e 1) (sp e 2) ? pc 11e0 (sp e 3) ? mbe, 0, 0, pc 12 pc 12e0 ? 00, faddr, sp ? sp e 4 l m pd75304b mbe, , , ? (sp + 1) pc 11e0 ? (sp) (sp + 3) (sp + 2) sp ? sp + 4 l m pd75306b, 75308b mbe, , , pc 12 ? (sp + 1) pc 11e0 ? (sp) (sp + 3) (sp + 2) sp ? sp + 4 l m pd75304b mbe, , , ? (sp + 1) pc 11e0 ? (sp) (sp + 3) (sp + 2) sp ? sp + 4 the skip unconditionally l m pd75306b, 75308b mbe, , , pc 12 ? (sp + 1) pc 11e0 ? (sp) (sp + 3) (sp + 2) sp ? sp + 4 the skip unconditionally l m pd75304b mbe, , , ? (sp + 1) pc 11e0 ? (sp) (sp + 3) (sp + 2) psw ? (sp + 4) (sp + 5), sp ? sp + 6 l m pd75306b, 75308b mbe, , , pc 12 ? (sp + 1) pc 11e0 ? (sp) (sp + 3) (sp + 2) psw ? (sp + 4) (sp + 5), sp ? sp + 6 (sp e 1) (sp e 2) ? rp, sp ? sp e 2 (sp e 1) ? mbs, (sp e 2) ? 0, sp ? sp e 2 rp ? (sp + 1) (sp), sp ? sp + 2 mbs ? (sp + 1), sp ? sp + 2 ime ? 1 ie ? 1 ime ? 0 ie ? 0 !faddr *9 2 1 1 1 1 2 1 2 2 2 2 2 rp bs rp bs ie ie unconditional note 1. instruction group 2. interrupt control note 1 callf ret rets reti push pop ei di note 2 subroutine stack control bytes machine cycles 2 3 3+s 3 1 2 1 2 2 2 2 2
44 m pd75304b,75306b,75308b operation skip condition operand address- ing area a, portn xa, portn portn, a portn, xa mbn taddr 2 2 2 2 2 2 1 2 1 ----------------------------------------------------------------- ----------------------------------------------------------------- ----------------------------- conforms to referenced instruction. conforms to referenced instruction. ----------------------------------------------------------------- ----------------------------------------------------------------- ----------------------------- ----------------------------- * at in/out instruction execution, mbe = 0 or mbe = 1, mbs = 15 must be set in advance. *10 note 1. instruction group 2. cpu control remarks the tbr and tcall instructions are assembler pseudo-instructions for geti instruction table definition. note 1 mne- monic in * out * halt stop nop sel geti special input/output note 2 bytes machine cycles 2 2 2 2 2 2 1 2 3 a ? port n (n = 0C7) xa ? port n+1 , port n (n = 4, 6) port n ? a (n = 2C7) port n+1 , port n ? xa (n =4, 6) set halt mode (pcc.2 ? 1) set stop mode (pcc.3 ? 1) no operation mbs ? n (n = 0, 1, 15) l m pd75304b ? tbr instruction pc 11-0 ? (taddr) 3C0 + (taddr + 1) ? tcall instruction (sp C 4) (sp C 1) (sp C 2) ? pc 11C0 (sp C 3) ? mbe, 0, 0, 0 pc 11C0 ? (taddr) 3C0 ? (taddr + 1) sp ? sp C 4 ? other than tbr and tcall instruction execution of an instruction addressed at (taddr) and (taddr + 1) l m pd75306, 75308bb ? tbr instruction pc 12-0 ? (taddr) 4C0 + (taddr + 1) ? tcall instruction (sp C 4) (sp C 1) (sp C 2) ? pc 11C0 (sp C 3) ? mbe, 0, 0, pc 12 pc 12C0 ? (taddr) 4C0 ? (taddr + 1) sp ? sp C 4 ? other than tbr and tcall instruction execution of an instruction addressed at (taddr) and (taddr + 1) -----------------------------
m pd75304b,75306b,75308b 45 10. mask option selection the following pin mask options are available. pin functions mask options p40 to p43, l pull-up resistor incorporated (specifiable bit-wise) p50 to p53 l no pull-up resistor (specifiable bit-wise) v lc0 to v lc2 , l lcd drive power supply split resistor incorporated (specifiable as 4-bit unit) bias l no lcd drive power supply split resistor (specifiable as 4-bit unit)
46 m pd75304b,75306b,75308b 11. electrical specifications absolute maximum ratings (ta = 25 c) parameter symbol test conditions rating unit power supply voltage except ports 4 and 5 C0.3 to v dd +0.3 v input voltage on-chip pull-up resistor C0.3 to v dd +0.3 v ports 4 and 5 openCdrain C0.3 to +11 v output voltage C0.3 to v dd +0.3 v output current one pin C15 ma high all pins C30 ma peak value 30 ma one pin rms 15 ma peak value 100 ma output current low total of ports 0, 2, 3 and 5 rms 60 ma peak value 100 ma total of ports 4, 6, and 7 rms 60 ma operating temperature storage temperature * rms is calculated using the following expression: [rms] = [peak value] ? duty capacitance (ta = 25 c, v dd = 0 v) parameter symbol test conditions min. typ. max. unit input capacitance c in 15 pf output capacitance c out 15 pf i/o capacitance c io 15 pf v dd v i1 v 12 v o i oh i ol * t opt t stg C0.3 to +7.0 v C40 to +85 c C65 to +150 c f = 1 mhz unmeasured pins returned to 0 v.
m pd75304b,75306b,75308b 47 main system clock oscillator characteristics (ta = C40 to +85 c, v dd = 2.0 to 6.0 v) recommended test resonator parameter min. typ. max. unit constant conditions oscillator frequency (f x ) *1 after v dd reached the oscillation min. of the stabilization time *2 oscillation voltage range oscillator frequency (f x ) *1 v dd = 4.5 to 6.0 v oscillation stabilization time *2 30 ms x1 input frequency (f x ) *1 x1 input high-/low-level 100 500 ns width (t xh , t xl ) 4ms 1.0 5.0 *3 mhz 1.0 4.19 5.0 *3 mhz 1.0 5.0 *3 mhz *1. the oscillator frequency and x1 input frequency indicate only the oscillator characteristics. for the instruction execution time refer to the ac characteristics. 2. the oscillation stabilization time is necessary for oscillation to stabilize after applying v dd or releasing the stop mode. 3. when the oscillation frequency is 4.19 mhz < f x 5.0 mhz, pcc = 0011 should not be selected as the instruction execution time. if pcc = 0011 is selected, one machine cycle is less than 0.95 s, and the specification min. value of 0.95 m s will not be achieved. 10 ms ceramic resonator *3 crystal resonator *3 external clock h x1 x2 c2 c1 v dd x1 x2 m pd74hcu04 x1 x2 c2 c1 v dd
48 m pd75304b,75306b,75308b 32 32.768 35 khz 1.0 2 s xt1 xt2 leave open 10 s 515 m s external clock crystal resonator subsystem clock oscillator characteristics (ta = C40 to +85 c, v dd = 2.0 to 6.0 v) recommended test min. typ. max. unit resonator parameter constant conditions oscillator frequency (f xt ) v dd = 4.5 to 6.0 v oscillation stabilization time * xt1 input 32 100 khz frequency (f xt ) xt1 input high-/ low-level width (t xth ,t xtl ) * this is the time required for oscillation to stabilize after v dd reaches the min. value of the oscillation voltage range. note when the main system clock and subsystem clock oscillators are used, the following should be noted concerning wiring in the area in the figure enclosed by a dotted line to prevent the influence of wiring capacitance, etc. ? the wiring should be kept as short as possible. ? no other signal lines should be crossed. keep away from lines carrying a high fluctuating current. ? the oscillator capacitor grounding point should be at the same potential as v dd . do not ground to a ground pattern carrying a high current. ? a signal should not be taken from the oscillator. the subsystem clock oscillator is a low-amplitude circuit in order to achieve a low consumption current, and is more prone to misoperation due to noise than the main system clock oscillator. particu- lar care is therefore required with the wiring method when the subsystem clock is used. xt1 xt2 c4 c3 v dd r h
m pd75304b,75306b,75308b 49 1.0 v v oh1 v oh2 v dd C1.0 v v dd C2.0 v dc characteristics (ta = C40 to +85 c, v dd = 2.7 to 6.0 v) (1/2) parameter symbol test conditions min. typ. max. unit v ih1 ports 2 and 3 0.7 v dd v dd v v ih2 ports 0,1,6,7, reset 0.8 v dd v dd v on-chip pull-up resistor 0.7 v dd v dd v v ih3 ports 4 and 5 openCdrain 0.7 v dd 10 v v ih4 x1, x2, xt1 v dd C0.5 v dd v v il1 ports 2, 3, 4 and 5 0 0.3 v dd v v il2 ports 0, 1, 6, 7 reset 0 0.2 v dd v v il3 x1, x2, xt1 0 0.4 v v dd = 4.5 to 6.0 v ports 0, 2,3, 6, 7, i oh = C1 ma bias i oh = -100 m av dd C0.5 v v dd = 4.5 to 6.0 v bp0 to bp7 i oh = C100 m a (with 2 i oh outputs) i oh = C30 m av dd C1.0 v ports 3, 4 and 5 v dd = 4.5 to 6.0 v 0.5 2.0 v i ol = 15 ma ports 0, 2, 3, 4, 5, 6 and 7 v dd = 4.5 to 6.0 v v ol1 i ol = 1.6 ma i ol = 400 m a 0.5 v openCdrain pull-up resistor 3 1 k w v dd = 4.5 to 6.0 v bp0 to bp7 i ol = 100 m a (with 2 i ol outputs) i ol = 50 m a 1.0 v i l1h1 other than below 3 m a v in = v dd i lih2 x1, x2, xt1 20 m a ports 4 and 5 (when openCdrain) input leakage i lil1 other than below C3 m a current low v in = 0 v i lil2 x1, x2, xt1 C20 m a output leakage i loh1 v out = v dd other than below 3 m a current high ports 4 and 5 (when openCdrain) output leakage current low sb0, 1 0.2 v dd v 0.4 v i lih3 v in = 10 v 20 m a i loh2 v out = 10 v 20 m a v ol2 i lol v out = 0 v C3 m a input voltage low input voltage high output voltage high output voltage low input leakage current high
50 m pd75304b,75306b,75308b dc characteristics (ta = C40 to +85 c, v dd = 2.7 to 6.0 v) (2/2) ports 4 and 5 v out = v dd C2.0 v parameter symbol test conditions min. typ. max. unit ports 0, 1, 2, 3, 6 v dd = 5.0 v 10% 15 40 80 k w r l1 and 7 (except p00) v in = 0 v v dd = 3.0 v 10% 30 300 k w v dd = 5.0 v 10% 15 40 70 k w r l2 v dd = 3.0 v 10% 10 60 k w lcd drive voltage v lcd 2.0 v dd v lcd split resistor r lcd 60 100 150 k w lcd output voltage deviation *1 v odc i o = 5 m a0 0.2 v (common) lcd output voltage deviation v ods i o = 1 m a0 0.2 v (segment) v dd = 5 v 10% *4 3.0 9 ma i ddi 4.19 mhz *3 v dd = 3 v 10% *5 0.4 1.2 ma crystal oscillation c1 = c2 = 22 pf halt v dd = 5 v 10% 600 1800 m a i dd2 mode v dd = 3 v 10% 180 540 m a i dd3 v dd = 3 v 10% 40 120 m a 32 khz *6 crystal oscillation halt v dd = 3 v 10% mode v dd = 5 v 10% 1 25 m a i dd5 0.5 15 m a ta = 25 c 0.5 5 m a *1. the voltage deviation is the difference between the output voltage and the segment or common output desired value (v lcdn ; n= 0, 1, 2). 2. current which flows in the on-chip pull-up resistor or lcd split resistor is not included. 3. including oscillation of the subsystem clock. 4. when the processor clock control register (pcc) is set to 0011 and the device is operated in the high- speed mode. 5. when pcc is set to 0000 and the device is operated in the low-speed mode. 6. when the system clock control register (scc) is set to 1001 and the device is operated on the subsystem clock, with main system clock oscillation stopped. i dd4 12 36 m a v dd = 3 v 10% xt1 = 0 v stop mode v lcd0 = v lcd v lcd1 = v lcd 2/3 v lcd2 = v lcd 1/3 2.7 v v lcd v dd on-chip pull-up resistor supply current *2
m pd75304b,75306b,75308b 51 t cy t tih , t til t inth , t intl t cy vs v dd (operating on main system clock) cycle time t cy [ m s] supply voltage v dd [v] 0 1 2 3 4 5 6 0.5 1 2 3 4 5 30 64 70 6 guaranteed operation range cpu clock cycle time (minimum instruction execution time) *1 interrupt input width high/low ac characteristics (ta = C40 to +85 c, v dd = 2.7 to 6.0 v) parameter symbol test conditions min. typ. max. unit operating on main v dd = 4.5 to 6.0 v 0.95 64 m s system clock 3.8 64 m s operating on subsystem clock ti0 input v dd = 4.5 to 6.0 v 0 1 mhz frequency f ti 0 275 khz ti0 input width v dd = 4.5 to 6.0 v 0.48 m s high/low 1.8 m s int0 *2 m s int1, 2, 4 10 m s kr0 to kr7 10 m s reset width low t rsl 10 m s 114 122 125 m s *1. the cpu clock ( f ) cycle time (minimum instruction execution time) is determined by the oscillatior frequency of the connected resonator, the system clock control register (scc) and the processor clock control register (pcc). the figure at the right indicates the cycle time t cy versus supply voltage v dd characteristic with the main system clock operating. 2. 2t cy or 128/f x is set by setting the interrupt mode register (im0).
52 m pd75304b,75306b,75308b t sik2 100 ns serial transfer operation 2-wired and 3-wired serial i/o modes (sck ... internal clock output): (ta = C40 to +85 c, v dd = 2.7 to 6.0 v) parameter symbol test conditions min. typ. max. unit v dd = 4.5 to 6.0 v 1600 ns sck cycle time t kcy1 3800 ns sck width high/ v dd = 4.5 to 6.0 v t kcy1 /2-50 ns low t kcy1 /2-150 ns si setup time (to sck - ) si hold time (from sck - ) so output v dd = 4.5 to 6.0 v 250 ns delay time t kso1 from sck 1000 ns 2-wired and 3-wired serial i/o modes (sck ... external clock input): (ta = -40 to +85 c, v dd = 2.7 to 6.0 v) parameter symbol test conditions min. typ. max. unit sck cycle time v dd = 4.5 to 6.0 v 800 ns t kcy2 3200 ns sck width high/ v dd = 4.5 to 6.0 v 400 ns low 1600 ns si setup time (to sck - ) si hold time (from sck - ) so output v dd = 4.5 to 6.0 v 300 ns delay time t kso2 from sck 1000 ns * r l and c l are load resistor and load capacitance of the so output line. t sik1 150 ns t ksi1 400 ns t kl1 t kh1 r l = 1 k w , c l = 100 pf * t ksi2 400 ns t kl2 t kh2 r l = 1 k w , c l = 100 pf *
m pd75304b,75306b,75308b 53 sbi mode (sck ... internal clock output (master)): (ta = C40 to +85 c, v dd = 2.7 to 6.0 v) parameter symbol test conditions min. typ. max. unit sck cycle time v dd = 4.5 to 6.0 v 1600 ns t kcy3 3800 ns sck width high/ v dd = 4.5 to 6.0 v t kcy3 /2-50 ns low t kcy3 /2-150 ns sb0, 1 setup time (to sck - ) sb0, 1 hold time (from sck - ) sb0, 1 output v dd = 4.5 to 6.0 v 0 250 ns delay time from t kso3 sck 0 1000 ns sb0, 1 from sck - t ksb t kcy3 ns sck from sb0, 1 t sbk t kcy3 ns sb0, 1 width low t sbl t kcy3 ns sb0, 1 width high t sbh t kcy3 ns sbi mode (sck ... external clock input (slave)): (ta = C40 to +85 c, v dd = 2.7 to 6.0 v) parameter symbol test conditions min. typ. max. unit sck cycle time v dd = 4.5 to 6.0 v 800 ns t kcy4 3200 ns sck width high/ v dd = 4.5 to 6.0 v 400 ns low 1600 ns sb0, 1 setup time (to sck - ) sb0, 1 hold time (from sck - ) sb0, 1 output v dd = 4.5 to 6.0 v 0 300 ns delay time from t kso4 sck 0 1000 ns sb0, 1 from sck - t ksb t kcy4 ns sck from sb0, 1 t sbk t kcy4 ns sb0, 1 width low t sbl t kcy4 ns sb0, 1 width high t sbh t kcy4 ns * r l and c l are load resistor and load capacitance of the sb0, 1 output lines. t ksi4 t kcy4 /2 ns t sik3 150 ns t ksi3 t kcy3 /2 ns t kl3 t kh3 r l = 1 k w , c l = 100 pf * t sik4 100 ns t kl4 t kh4 r l = 1 k w , c l = 100 pf *
54 m pd75304b,75306b,75308b i ol = 400 m a 0.5 v v oh1 i oh = C100 m av dd C0.5 v dc characteristics (ta = C40 to +85 c, v dd = 2.0 to 6.0 v) (1/2) parameter symbol test conditions min. typ. max. unit v ih1 ports 2 and 3 0.8 v dd v dd v v ih2 ports 0, 1, 6, 7, reset 0.8 v dd v dd v on-chip pull-up resistor 0.8 v dd v dd v v ih3 ports 4 and 5 openCdrain 0.8 v dd 10 v v ih4 x1, x2, xt1 v dd C0.3 v dd v v il1 ports 2, 3, 4 and 5 0 0.2 v dd v v il2 ports 0, 1, 6, 7, reset 0 0.2 v dd v v il3 x1, x2, xt1 0 0.3 v ports 0, 2, 3, 6, 7, bias bp0 to bp7 (with 2 i oh outputs) ports 0, 2, 3, 4, 5 6, and 7 v ol1 openCdrain, pull-up resistor 3 1 k w bp0 to bp7 (with 2 i ol outputs) i lih1 other than below 3 m a v in = v dd i lih2 x1, x2, xt1 20 m a ports 4 and 5 (with openCdrain) input leakage i lil1 other than below C3 m a current low v in = 0 v i lil2 x1, x2, xt1 C20 m a output leakage i loh1 v out = v dd other than below 3 m a current high ports 4 and 5 (with openCdrain) output leakage current low v oh2 i oh = C10 m av dd C0.4 v sb0, 1 0.2 v dd v v ol2 i ol = 10 m a 0.4 v i lih3 v in = 10 v 20 m a i loh2 v out = 10 v 20 m a i lol v out = 0 v C3 m a input voltage high input voltage low output voltage high output voltage low input leakage current high
m pd75304b,75306b,75308b 55 dc characteristics (ta = C40 to +85 c, v dd = 2.0 to 6.0 v) (2/2) parameter symbol test conditions min. typ. max. unit ports 0, 1, 2, 3, 6 r l1 and 7 (except p00) v dd = 2.5 v 10% 50 600 k w v in = 0 v ports 4 and 5 v out = v dd C1.0 v lcd drive voltage v lcd 2.0 v dd v lcd split resistor r lcd 60 100 150 k w lcd output voltage deviation *1 v odc i o = 5 m a0 0.2 v (common) lcd output voltage deviation v ods i o = 1 m a0 0.2 v (segment) v dd = 3 v 10% *4 0.4 1.2 ma i ddi v dd = 2.5 v 10% *4 0.3 0.9 ma halt v dd = 3 v 10% 180 540 m a i dd2 mode v dd = 2.5 v 10% 120 360 m a v dd = 3 v 10% 40 120 m a i dd3 supply current *2 v dd = 2.5 v 10% 25 75 m a halt v dd = 3 v 10% 12 36 m a i dd4 mode v dd = 2.5 v 10% 9 27 m a 0.5 15 m a v dd = 3 v 10% ta = 25 c 0.5 5 m a i dd5 0.4 15 m a ta = 25 c 0.4 5 m a *1. the voltage deviation is the difference between the output voltage and the segment or common output desired value (v lcdn ; n = 0, 1, 2). 2. current which flows in the on-chip pull-up resistor or lcd split resistor is not included. 3. including oscillation of the subsystem clock. 4. when pcc is set to 0000 and the device is operated in the low-speed mode. 5. when the system clock control register (scc) is set to 1001 and the device is operated on the subsystem clock, with main system clock oscillation stopped. r l2 v dd = 2.5 v 10% 10 60 k w v lcdo = v lcd v lcd1 = v lcd 2/3 v lcd2 = v lcd 1/3 2.0 v v lcd v dd 4.19 mhz *3 crystal oscillation c1 = c2 = 22 pf low-speed mode 32 khz *5 crystal oscillation xt1 = 0 v stop mode v dd = 2.5 v 10% on-chip pull-up resistor
56 m pd75304b,75306b,75308b 3.4 64 m s ac characteristics (ta = C40 to +85 c, v dd = 2.0 to 6.0 v) parameter symbol test conditions min. typ. max. unit v dd = 2.7 to 6.0 v 3.8 64 m s operation on main v dd = 2.0 to 6.0 v 5 64 m s system clock t cy ta = C40 to + 60 c v dd = 2.2 to 6.0 v operation on subsystem clock ti0 input frequency ti0 input width t tih , high/low t til int0 *2 m s int1, 2, 4 10 m s kr0 to kr7 10 m s reset width low t rsl 10 m s 114 122 125 m s f ti 0 275 khz 1.8 m s t inth , t intl *1. the cpu clock ( f ) cycle time (minimum instruction execution time) is determined by the oscillatior frequency of the connected resonator, the system clock control register (scc) and the processor clock control register (pcc). the figure at the right indicates the cycle time t cy versus supply voltage v dd characteristic with the main system clock operating. 2. 2t cy or 128/f x is set by setting the interrupt mode register (im0). interrupt input width high/low t cy vs v dd (operating on main system clock) cycle time t cy [ m s] supply voltage v dd [v] 0 1 2 3 4 5 6 0.5 1 2 3 4 5 30 64 70 6 guaranteed operation range cpu clock cycle time (minimum instruction execution time) *1
m pd75304b,75306b,75308b 57 serial transfer operation 2-wired and 3-wired serial i/o mode (sck ... internal clock output): (ta = C40 to +85 c, v dd = 2.0 to 6.0 v) parameter symbol test conditions min. typ. max. unit sck cycle time v dd = 4.5 to 6.0 v 1600 ns t kcy1 3800 ns sck width high/ v dd = 4.5 to 6.0 v t kcy1 /2-50 ns low t kcy1 /2-150 ns si setup time (to sck - ) si hold time (from sck - ) so output v dd = 4.5 to 6.0 v 250 ns delay time t kso1 from sck 1000 ns 2-wired and 3-wired serial i/o mode (sck ... external clock input): (ta = C40 to +85 c, v dd = 2.0 to 6.0 v) parameter symbol test conditions min. typ. max. unit sck cycle time v dd = 4.5 to 6.0 v 800 ns t kcy2 3200 ns sck width high/ v dd = 4.5 to 6.0 v 400 ns low 1600 ns si setup time (to sck - ) si hold time (from sck - ) so output v dd = 4.5 to 6.0 v 300 ns delay time t kso2 from sck 1000 ns * r l and c l are load resistor and load capacitance of the so output line. t ksi2 400 ns t sik2 100 ns t kl1 t kh1 t ksi1 400 ns t sik1 250 ns r l = 1 k w , c l = 100 pf * t kl2 t kh2 r l = 1 k w , c l = 100 pf *
58 m pd75304b,75306b,75308b sbi mode (sck ... internal clock output (master)): (ta = C40 to +85 c, v dd = 2.0 to 6.0 v) parameter symbol test conditions min. typ. max. unit sck cycle time v dd = 4.5 to 6.0 v 1600 ns t kcy3 3800 ns sck width high/ v dd = 4.5 to 6.0 v t kcy3 /2-50 ns low t kcy3 /2-150 ns sb0, 1 setup time (to sck - ) sb0, 1 hold time (from sck - ) sb0, 1 output v dd = 4.5 to 6.0 v 0 250 ns delay time t kso3 from sck 0 1000 ns sb0, 1 from sck - t ksb t kcy3 ns sck from sb0, 1 t sbk t kcy3 ns sb0, 1 width low t sbl t kcy3 ns sb0, 1 width high t sbh t kcy3 ns sbi mode (sck ... external clock input (slave)): (ta = C40 to +85 c, v dd = 2.0 to 6.0 v) parameter symbol test conditions min. typ. max. unit sck cycle time v dd = 4.5 to 6.0 v 800 ns t kcy4 3200 ns sck width high/ v dd = 4.5 to 6.0 v 400 ns low 1600 ns sb0, 1 setup time (to sck - ) sb0, 1 hold time (from sck - ) sb0, 1 v dd = 4.5 to 6.0 v 0 300 ns output delay t kso4 time from sck 0 1000 ns sb0, 1 from sck - t ksb t kcy4 ns sck from sb0, 1 t sbk t kcy4 ns sb0, 1 width low t sbl t kcy4 ns sb0, 1 width high t sbh t kcy4 ns * r l and c l are load resistor and load capacitance of the sb0, 1 output lines. t ksi3 t kcy3 /2 ns t sik3 250 ns t sik4 100 ns t ksi4 t kcy4 /2 ns t kl4 t kh4 t kl3 t kh3 r l = 1 k w , c l = 100 pf * r l = 1 k w , c l = 100 pf *
m pd75304b,75306b,75308b 59 x1 input 1/f x t xl t xh v dd -0.5 v 0.4 v xt1 input 1/f xt t xtl t xth v dd -0.5 v 0.4 v ti0 1/f ti t til t tih ac timing test point (excluding x1 and xt1 inputs) clock timings ti0 timing 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd test points
60 m pd75304b,75306b,75308b sck t kcy1 t kh1 t kl1 input data output data t sik1 t ksi1 t kso1 si so serial transfer timing 3-wired serial i/o mode: 2-wired serial i/o mode: t kso2 t kl2 t kh2 t kcy2 sck sb0,1 t sik2 t ksi2
m pd75304b,75306b,75308b 61 t intl t inth int0,1,2,4 kr0-7 t rsl reset t ksb t kso3,4 t sik3,4 t ksi3,4 t kl3,4 t kh3,4 t kcy3,4 sck sb0,1 t sbk serial transfer timing bus release signal transfer: command signal transfer: interrupt input timing reset input timing t ksb t sbl t sbh t sbk t kso3,4 t sik3,4 t ksi3,4 t kl3,4 t kh3,4 t kcy3,4 sck sb0,1
62 m pd75304b,75306b,75308b data memory stop mode low supply voltage data retention characteristics (ta = C40 to 85 c) parameter symbol test conditions min. typ. max. unit data retention supply voltage v dddr 2.0 6.0 v data retention supply current *1 i dddr v dddr = 2.0 v 0.3 15 m a release signal setup time t srel 0 m s oscillation stabilization release by reset 2 17 /fx ms wait time *2 t wait release by interrupt request *3 ms *1. current which flows in the on-chip pull-up resistor is not included. 2. the oscillation stabilization wait time is the time during which the cpu operation is stopped to prevent unstable operation at the oscillation start. 3. depends on the basic interval timer mode register (btm) setting (table below). wait time btm3 btm2 btm1 btm0 (figures in parentheses are for operation at fx = 4.19 mhz) 0 00 2 20 /fx (approx. 250 ms) 0 11 2 17 /fx (approx. 31.3 ms) 1 01 2 15 /fx (approx. 7.82 ms) 1 11 2 13 /fx (approx. 1.95 ms)
m pd75304b,75306b,75308b 63 data retention timing (stop mode release by reset) data retention timing (standby release signal: stop mode release by interrupt signal) stop mode data retention mode stop instruction execution v dd halt mode operating mode v dddr t srel t wait standby release signal (interrupt request) stop mode data retention mode stop instruction execution reset v dd internal reset operation halt mode operating mode v dddr t srel t wait
64 m pd75304b,75306b,75308b 12. package information a m f b 60 61 40 k l 80 pin plastic qfp ( 14) 80 1 21 20 41 g d c detail of lead end s q p m i h j 55? n s80gc-65-3b9-3 item millimeters inches a b c d f g h i j k l 17.2 0.4 14.0 0.2 0.8 0.30 0.10 0.13 14.0 0.2 0.677 0.016 0.031 0.031 0.005 0.026 (t.p.) 0.551 note m n 0.10 0.15 1.6 0.2 0.65 (t.p.) 0.004 0.006 +0.004 ?.003 each lead centerline is located within 0.13 mm (0.005 inch) of its true position (t.p.) at maximum material condition. 0.063 0.008 0.012 0.551 0.8 0.2 0.031 p 2.7 0.106 0.677 0.016 17.2 0.4 0.8 +0.009 ?.008 q 0.1 0.1 0.004 0.004 s 3.0 max. 0.119 max. +0.10 ?.05 +0.009 ?.008 +0.004 ?.005 +0.009 ?.008
m pd75304b,75306b,75308b 65 n a m f b 64 65 40 k l 80 pin plastic qfp (14 20) 80 1 25 24 41 g d c p detail of lead end s q 55? m i h j p80gf-80-3b9-2 item millimeters inches a b c d f g h i j k l 23.6 0.4 14.0 0.2 0.8 0.35 0.10 0.15 20.0 0.2 0.929 0.016 0.039 0.031 0.006 0.031 (t.p.) 0.795 note m n 0.15 0.15 1.8 0.2 0.8 (t.p.) 0.006 0.006 +0.004 ?.003 each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. 0.071 0.014 0.551 0.8 0.2 0.031 p 2.7 0.106 0.693 0.016 17.6 0.4 1.0 +0.009 ?.008 q 0.1 0.1 0.004 0.004 s 3.0 max. 0.119 max. +0.10 ?.05 +0.009 ?.008 +0.004 ?.005 +0.009 ?.008 +0.008 ?.009
66 m pd75304b,75306b,75308b 80 pin plastic tqfp (fine pitch) ( 12) item millimeters inches i j 0.5 (t.p.) 0.10 0.004 0.020 (t.p.) a note each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. s a 14.0?.2 0.551 +0.009 ?.008 b 12.0?.2 0.472 +0.009 ?.008 c 12.0?.2 0.472 +0.009 ?.008 d 14.0?.2 0.551 +0.009 ?.008 f g 1.25 1.25 0.049 0.049 h 0.22 0.009?.002 p80gk-50-be9-4 s 1.27 max. 0.050 max. k 1.0?.2 0.039 +0.009 ?.008 l 0.5?.2 0.020 +0.008 ?.009 m 0.145 0.006?.002 n 0.10 0.004 p 1.05 0.041 q 0.05?.05 0.002?.002 r 55? 55? +0.05 ?.04 +0.055 ?.045 b c d j h i g f p n l k m q r detail of lead end m 61 60 41 40 21 20 1 80
m pd75304b,75306b,75308b 67 13. recommended soldering conditions these products should be soldered and mounted under the conditions recommended below. for details of recommended soldering conditions, refer to the information document "surface mount technology manual (iei 1207)" . for soldering methods and conditions other than those recommended, please contact our salesman. table 13-1 surface mount type soldering conditions h (1) m pd75304bgc- -3b9: 80-pin plastic qfp ( n n 14 mm) m pd75306bgc- -3b9: 80-pin plastic qfp ( n n 14 mm) m pd75308bgc- -3b9: 80-pin plastic qfp ( n n 14 mm) soldering method soldering conditionsrecommended condition symbol package peak temperature: 230 c duration: 30 sec. max. (210 c or above) infrared reflow number of applications: one time limit: 7 days * (thereafter 20 hours 125 c prebaking required) package peak temperature: 215 c duration: 40 sec. max. (200 c or above) vps number of applications: one time limit: 7 days* (thereafter 20 hours 125 c prebaking required) pin part heating pin part temperature: 300 c or less duration: 3 sec. max. (per side of device) ir30-207-1 vp15-207-1 * for the storage period after dry-pack decapsulation, storage conditions are max. 25 c, 65% rh. note use of more than one soldering method should be avoided (except in the case of pin part heating). ir30-00-1 vp15-00-1 ws60-00-1 soldering method soldering conditionsrecommended condition symbol infrared reflow package peak temperature: 230 c duration: 30 sec. max. (210 c or above) number of applications: one vps package peak temperature: 215 c duration: 40 sec. max. (200 c or above) number of applications: one solder bath temperature: 260 c or less duration: 10 sec. max. wave soldering number of applications: one preparatory heating temperature: 120 c max. (package surface temperature) pin part heating pin part temperature: 300 c or less duration: 3 sec. max. (per side of device) (2) m pd75304bgf- -3b9: 80-pin plastic qfp (14 20 mm) m pd75306bgf- -3b9: 80-pin plastic qfp (14 20 mm) m pd75308bgf- -3b9: 80-pin plastic qfp (14 20 mm)
68 m pd75304b,75306b,75308b (3) m pd75304bgk- -3b9: 80-pin plastic tqfp ( n n 12 mm) m pd75306bgk- -3b9: 80-pin plastic tqfp ( n n 12 mm) m pd75308bgk- -3b9: 80-pin plastic tqfp ( n n 12 mm) soldering method soldering conditionsrecommended condition symbol package peak temperature: 230 c duration: 30 sec. max. (210 c or above) infrared reflow number of applications: one time limit: 1 day * (thereafter 16 hours 125 c prebaking required) package peak temperature: 215 c duration: 40 sec. max. (200 c or above) vps number of applications: one time limit: 1 day * (thereafter 16 hours 125 c prebaking required) pin part heating pin part temperature: 300 c or less duration: 3 sec. max. (per side of device) ir30-161-1 vp15-161-1 * for the storage period after dry-pack decapsulation, storage conditions are max. 25 c, 65% rh. note use of more than one soldering method should be avoided (except in the case of pin part heating). notice recommended soldering conditions have been improved for some of these products. (improvements: relaxation of infrared reflow peak temperature (235 c, number of applications (two), time limit, etc.) please contact your nec sales representative for details.
m pd75304b,75306b,75308b 69 [memo]
70 m pd75304b,75306b,75308b appendix a. differences among series products h item supply voltage range rom configuration program memory (bytes) data memory ( 4 bits) instruction cycle cmos input cmos input/output input/output ports cmos output n-ch openCdrain input/output lcd controller/driver lcd drive voltage timer/counter serial interface vectored interrupt test input clock output (pcl) buzzer output (buz) package on-chip prom product 0.95 m s, 1.91 m s, 15.3 m s (main system clock: 4.19 mhz operation) 122 m s (subsystem clock: 32.768 khz operation) 8 pull-up resistor incorporation spesifiable by software: 23 16 40 8 used with segment pin 8 ? common output: static C 1/4 duty selected ? segment output: max. 32 lcd drive split resistor can be incorporated by no lcd drive split resistor. mask option. 2.0 to v dd ? 8-bit timer/event counter ? 8-bit basic interval timer ? watch timer ? nec standard serial bus interface (sbi) ? clock synchronous serial interface ? external: 3 ? internal: 3 ? external: 1 ? internal: 1 f , 524 khz, 262 khz, 65.5 khz (main system clock: 4.19 mhz operation) 2 khz (main system clock: in 4.19 mhz operation or subsystem clock: in 32.768 khz operation) m pd75p308 m pd75p316 m pd75p316a m pd75304/75306/75308 m pd75312/75316 m pd75p308 m pd75p316 2.0 to 6.0 v 5v 5% mask rom 4096/6016/8064 12160/16256 8064 16256 512 eprom/one- time one-time prom product name 10 v withstand voltage. pull-up resistor incorporation spesifiable by mask option. (without pull-up resistor) 10 v withstand voltage. pull-up resistor incorporation spesifiable by mask option 80-pin plastic qfp (14 20 mm) 80-pin plastic qfp (14 20 mm) 80-pin plastic qfp (14 20 mm) 80-pin ceramic wqfn (lcc with window)
m pd75304b,75306b,75308b 71 item supply voltage range rom configuration program memory (bytes) data memory ( 4 bits) instruction cycle cmos input cmos input/output input/output ports cmos output n-ch openCdrain input/output lcd controller/driver lcd drive voltage timer/counter serial interface vectored interrupt test input clock output (pcl) buzzer output (buz) package on-chip prom product 80-pin ceramic wqfn 80-pin plastic qfp (14 20 mm) 0.95 m s, 1.91 m s, 15.3 m s (main system clock: 4.19 mhz operation) 122 m s (subsystem clock: 32.768 khz operation) 8 pull-up resistor incorporation spesifiable by software: 23 16 40 8 used with segment pin 8 ? common output: static C 1/4 duty selected ? segment output: max. 32 lcd drive split resistor can be incorporat- no lcd drive split resistor. ed by mask option. 2.0 to v dd ? 8-bit timer/event counter ? 8-bit basic interval timer ? watch timer ? nec standard serial bus interface (sbi) ? clock synchronous serial interface ? external: 3 ? internal: 3 ? external: 1 ? internal: 1 f , 524 khz, 262 khz, 65.5 khz (main system clock: 4.19 mhz operation) 2 khz (main system clock: in 4.19 mhz operation or subsystem clock: in 32.768 khz operation) gf package: m pd75p316a m pd75p316b gc/gk package: m pd75p316b product name m pd75304b/75306b/75308b m pd75312b m pd75316b m pd75p316b * m pd75p316a 2.0 to 6.0 v mask rom 4096/6016/8064 12160 16256 512 1024 10 v withstand voltage. pull- up resistor incorporation spesifiable by mask option 10 v withstand voltage. pull-up resistor incorporation spesifiable by mask option. (without pull-up resistor) one-time prom eprom/one- time 80-pin plastic qfp ( n n 14mm) 80-pin plastic tqfp( n n 12mm) 80-pin plastic qfp ? (14 20 mm) ?( n n 14mm) 80-pin plastic tqfp( n n 12mm) * under development
72 m pd75304b,75306b,75308b appendix b. development tools the following development tools are available for system development using the m pd75304b/75306b/ 75308b. ie-75000-r *1 ie-75001-r ie-75000-r-em *2 ep-75308gf-r ev-9200g-80 ep-75308bgc-r ev-9200gc-80 ep-75308bgk-r ev-9500gk-80 pg-1500 pa-75p308gf pa-75p316bgc pa-75p316bgk ie control program pg-1500 controller ra75x relocatable assembler 75x series in-circuit emulator emulation board for the ie-75000-r or ie-75001-r emulation probe for the m pd75304bgf, 75306bgf and 75308bgf. an 80-pin conversion socket (ev-9200g-80) is also provided. emulation probe for the m pd75304bgc, 75306bgc and 75308bgc. an 80-pin conversion socket (ev-9200gc-80) is also provided. emulation probe for the m pd75304bgk, 75306bgk and 75308bgk. an 80-pin conversion adapter (ev-9200gk-80) is also provided. prom programmer prom programmer adapter for the m pd75p316agf, connected to the pg-1500. prom programmer adapter for the m pd75p316bgc, connected to the pg-1500. prom programmer adapter for the m pd75p316bgk, connected to the pg-1500. host machines pc-9800 series (ms-dos? ver. 3.30 to ver. 5.00a *3 ) ibm pc/at?(pc dos? ver. 3.1) *1. maintenance product 2. not incorporated in the ie-75001-r. 3. a task swapping function is provided in ver. 5.00/5.00a, but this function cannot be used with this software. remarks please refer to the 75x series selection guide (if-151) for third party development tools. hardware software
m pd75304b,75306b,75308b 73 appendix c. related documents device related documents document name document number user's manual iem-5016 instruction application table iem-994 application note iem-5035 iem-5041 75x series selection guide if-151 development tools documents document name document number ie-75000-r/ie-75001-r user's manual eeu-846 ie-75000-r-em user's manual eeu-673 ep-75308gf-r user's manual eeu-689 ep-75308bgc-r user's manual eeu-825 ep-75308bgk-r user's manual eeu-838 pg-1500 user's manual eeu-651 ra75x assembler package user's manual operation eeu-731 language eeu-730 pg-1500 controller user's manual eeu-704 hardware other documents document name document number package manual iei-635 surface mount technology manual iei-1207 quality grande on nec semiconductor device iei-1209 nec semiconductor device reliability & quality control iem-5068 electrostatic discharge(esd) test mem-539 semiconductor devices quality guarantee guide mei-603 microcomputer related products guide other manufacturers volume mei-604 * the contents of the above related documents are subject to change without notice. the latest documents should be used for design, etc. software
74 m pd75304b,75306b,75308b [memo]
m pd75304b,75306b,75308b 75
[memo] no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. the devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. if customers intend to use nec devices for above applications or they intend to use "standard" quality grade nec devices for applications not intended by nec, please contact our sales people in advance. application examples recommended by nec corporation standard : computer, office equipment, communication equipment, test and measurement equipment, machine tools, industrial robots, audio and visual equipment, other consumer products, etc. special : automotive and transportation equipment, traffic control systems, antidisaster systems, anticrime systems, etc. ms-dos is a trademark of microsoft corporation. pc dos, pc/at is a trademark of ibm corporation. m4 92.6 m pd75304b,75306b,75308b

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