ts3003 page 1 ? 2013 touchstone semiconductor, inc. all rights reserved. features ? ultra low supply current : 1.9 a at 25k hz ? supply voltage operation: 1.55v to 5.25v ? single resistor sets fout at 50% duty cycle ? programmable fout period: ? 10khz fout 300khz ? fout period accuracy: 3 % ? fout period drift: 0.02 % /oc ? single resistor set s output frequency ? separate pwm control and buffered output ? fout/pwmout output driver resistance: 160 applications portable and battery - powered equipment low - parts - count nanopower oscillator compact micropower replacement for crystal and ceramic oscillators micropower pulse - width modulation control micropower pulse - position modulation control micropower clock generation micropower sequential timing description the ts3003 is a single - supply , second - generation touchstone semi oscillator/timer fully specified to operate at a supply voltage range of 1.55v to 5.25v while consuming less than 2.4 a (max) supply current. requiring only a resistor to set the base output fr equency (or output period) at 25k h z (or 40 s) with a 50% duty cycle, the ts3003 timer/oscillator is compact, easy - to - use, and versatile. optimized for ultra - long life, low frequency, battery - powered/portable applications, ts3003 joins the ts3001, ts3002, ts3 004, and ts3006 in touchstones cmos timer family in its nanowatt analog? series of high - performance analog integrated circuits. t he ts3003 output frequency can be user - adjusted from 10khz to 300khz with a single resistor . in addition, the ts3003 repre sents a 25% reduction in pcb area and a factor - of - 10 lower power consumption over other cmos - based integrated circuit oscillators/timers. when compared against industry - standard 555 - timer - based products, the ts3003 offers up to 84% reduction in pcb area an d over three orders of magnitude lower power consumption. the ts3003 is fully specified over the - 40c to +85c temperature range and is available in a low - profile, 10 - pin 3x3mm tdfn package with an exposed back - side paddle. a 1.55v to 5 .25 v, 10khz to 300khz silicon timer typical application circuit t he touchstone semicondu c tor logo and nanowatt analog are registered trademark s of touchstone semiconductor, incorporated.
ts3003 page 2 ts3003ds r1p0 rtfds absolute maximum rat ings v dd to gnd ................................ ............................... - 0.3v to +5.5 v pwm_cntrl to gnd ................................ .............. - 0.3v to +5.5 v f out , pwmout to gnd ................................ ......... - 0.3v to +5.5v rset to gnd ................................ ........................... - 0.3v to +2 .5 v cpwm to gnd ................................ ......................... - 0.3v to + 5.5 v fdiv to gnd ................................ ............................ - 0.3v to +5.5 v continuous power dissipation (t a = +70c) 10 - pin tdfn (derate at 13.48mw/c above +70c) ... 1078mw operating temperature range ................................ - 40c to +85c storage temperature range ................................ . - 65c to +150c lead temperature (s oldering, 10s) ................................ ..... +300c electrical and thermal s tresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is not implied. exposure to any absolute maximum rating conditions for extended periods may affect device reliability and lifetime . package/ordering information order number part marking carrier quantity ts3003 itd1033 tp 3003 i tape & reel ----- ts3003 itd1033 t tape & reel 3000 lead - free program: touchstone semico nductor supplies only lead - free packaging. consult touchstone semiconductor for products specified with wider operating temperature ranges.
ts3003 ts3003ds r1p0 page 3 rtfds electrical character istics v dd = 3 v, v pwm_cntrl = v dd , r set = 4.32m?, r load(fout) = open circuit, c load(fout) = 0pf, c load(pwm) = 0pf , c pwm = 47 pf , unless otherwise noted. v alues are at t a = 25c unless otherwise noted. see note 1. parameter symbol conditions min typ max units supply voltage v dd 1.5 5 5.25 v supply current i dd cpwm = v dd 1.9 2.4 a - 40c t a 85c 2.7 3.3 3.6 - 40c t a 85c 4.5 fout period t fout 39 40.1 41.2 s - 40c t a 85c 38 42 fout period line regulation t fout /v 1 .5 5 v v dd 5 .25 v 0.17 %/v fout duty cycle 49 51 % fout period temperature coefficient t fout /t 0.02 %/c pwmout duty cycle dc(pwmout) 37 41.6 48 % v pwm_cntrl = 0v 15 24 pwmout duty cycle line regulation dc(pwmout)/v 1.55v < v dd < 5.25v, fdiv2:0 = 0 00 - 3 % c pwm sourcing current i cpwm 930 1050 na - 40c t a 85c 810 1150 uvlo hysteresis v uvlo (v dd =1.55v ) C (v dd _ shutdown voltage ) 150 250 mv fout, pwmout rise time t rise see note 2, c l = 15pf 10 ns fout, pwmout fall time t fall see note 2, c l = 15pf 10 ns fout jitter see note 3 0.001 % rset pin voltage v(rset) 0.3 v fd iv input current i f d iv 10 na - 40c t a 85c 20 maximum oscillator frequency fosc rset= 330k 300 k hz high level output voltage, fout and pwmout v dd - v oh i oh = 1ma 160 mv low l evel output voltage, fout and pwmout v ol i ol = 1ma 140 mv dead time t dt fout edge falling and pwmout edge rising 106 ns note 1: all devices are 100% production tested at t a = +25c and are guaranteed by characterization for t a = t min to t max , as specified. note 2: output rise and fall times are measured between the 10% and 90% of the v dd power - supply voltage levels. the specification is based on lab bench characterization and is not tested in production. note 3 : timing jitter is the ratio of the peak - to - peak variation of the period to the mean of the period. the specification is based on lab bench characterization and is not tested in production.
ts3003 page 4 ts3003ds r1p0 rtfds period - s supply current - a 20 40 4 0 supply current vs fout period 0 60 6 8 2 80 100 supply voltage - volt period - s 2.29 3.03 40.12 40.1 40.18 fout period vs supply voltage 1.55 3.77 40.14 40.16 4.51 c load - pf supply current - a 10 20 4 0 supply current vs c load(fout) 0 30 6 8 2 40 5.25 temperature - oc supply current - a 2.1 1.7 supply current vs temperature 2.3 2.5 1.9 - 15 10 - 40 35 60 85 supply voltage - volt start - up time - ms 6 5 9 start - up time vs supply voltage 7 8 10 temperature - oc period - s - 15 10 39.5 39 fout period vs temperature - 40 35 40 60 85 40.5 41 typical performance characteristics v dd = 3 v, v pwm_cntrl = v dd , r set = 4.32m?, r load(fout) = open circuit, c load(fout) = 0pf, c load(pwm) = 0pf , cpwm = v dd , unless otherwise noted. v alues are at t a = 25c unless otherwise noted. 10 12 14 40.2 2.29 3.03 1.55 3.77 4.51 5.25 11
ts3003 ts3003ds r1p0 page 5 rtfds typical performance characteristics v dd = 3 v, v pwm_cntrl = v dd , r set = 4.32m?, r load(fout) = open circuit, c load(fout) = 0pf, c load(pwm) = 0pf , cpwm = v dd , unless otherwise noted. v alues are at t a = 25c unless otherwise noted. r set - m period - s 2 4 40 0 100 period vs r set 0 6 60 80 20 8 10 percent of units - % supply current - a 0% supply current distribution 1.9 5 5% 10% 15% 20% 25% 30% 35% 1. 97 1. 99 2.0 1 fout and pwmout v dd = 3 v, c load = 15pf , v pwm_cntrl = v dd , c pwm = 47pf 5s/div fout 2v/div pwmout 2v/div fout and pwmout v dd = 5 v, c load = 15pf , v pwm_cntrl = v dd , c pwm = 47pf 5s/div fout 2v/div pwmout 2v/div fout v dd = 3v, c load = 15 pf 5s/div fout v dd = 5v, c load = 15 pf 5s/div fout 1v/div fout 1v/div 12
ts3003 page 6 ts3003ds r1p0 rtfds pin functions pin name function 1 fout fixed frequency output. a push - pull output stage with an output resistance of 160 . fout pin swings from gnd to vdd . for lowest power operation, capacitance loads should be minimized and resistive loads should be maximized. 2,3, nc non - connect. 5 pwmout pulse - width modulated output. a push - pull output stage with an output resistance of 160 , the pwmout pin is wired anti - phase with respect to fout and swings from gnd to vdd. for lowest power operation, capacitance loads should be minimized and resistive loads should be maximized . 6 pwm_cntrl pwm output pulse control pin. applying a voltage between gnd and v rset will reduce the duty cycle of the pwmout output that is set by the capacitor connected to the cpwm pin. connect pwm_cntrl to vdd for fixed pwm out output pulse time (determined only by capacitor at cpwm). 4, 7 gnd ground. connect this pin to the systems analog ground plane. 8 cpwm pwmout pulse width programming capacitance input. a target capacitance connected from this pin to gnd sets the duty cycle of the pmw output . minimize any stray capacitance on this pin. the voltage on this pin will swing from gnd to v rset . connect cpwm to vdd to disable pwm function (saves pwm current). 9 vdd power supply voltage input. the supply voltage range is 1.5 5v v dd 5.25 v. bypass this pin with a 0.1uf ceramic coupling capacitor in close proximity to the ts3003 . 10 rset fout programming resistor input. a 4.32mohm resistor connected from t his pin to ground sets the t3003 s internal oscillators output period to 40 s (25khz). for optimal performance, the composition of the rset resistor shall be consistent with a tolerance of 1% or lower. the rset pin voltage is approximately 0.3v.
ts3003 ts3003ds r1p0 page 7 rtfds block diagram theory of operation the ts3003 is a user - programmable oscillator where the period of the square wave at its f out terminal is generated by an external resistor connected to the rset pin . the output frequency is given by: o t 1 . 08 11 rs t equation 1. fout frequency calculation r set (m ? ) fout (khz) 1 108 2.49 43 4.32 25 6.81 16 9.76 11 table 1: fout vs r set
ts3003 page 8 ts3003ds r1p0 rtfds with an r set = 4.32m ? , the output frequency is approximately 25khz with a 50% duty cycle. as de sign aids, tables 1 lists ts3003 s typical o t for various standard values for r set . the output frequency can be user - adjusted from 10khz to 300khz with a single resistor . the ts3003 also provides a separate pwm output signal at its pwmout terminal that is anti - phase with respect to fout. a dead time of approximately 106ns exists between fout and pwmout. to adjust the pulse width of the pwmout output, a single capacitor can be placed at the cpwm pin. to determine the capacitan ce needed for a desired pulse width, the following equation is to be used: c wm = ulse width s x c wm v c wm 300 mv equation 2. cpwm capacit or calculation where i cpwm and v cpwm is the current supplied and voltage applied to the cpwm capacitor , respectively. the pulse width is determined based on the period of fout and should never be greater than the period at fout . make sure the pwm_cntrl pin is set to at least 400mv when calculating the pulse wid th of pwmout. note v cpwm is approximately 300mv, which is the rset voltage. also note that i cpwm is approximately 1 a. the pwmout output pulse width can be adjusted further after selecting a cpwm capacitor. this can be achieved by applying a voltage to the pwm_cntrl pin between v rset and gnd. with a voltage of at least v rset , the pulse width is set based on equation 2. for example, with a period of 40 s( 25khz) a 47pf capacitor at the cpwm pin generates a pulse wid th of approximately 16 s. this can be calculated using equation 2. by reducing the pwm_cntrl voltage from v rset 300mv to gnd, the pulse width is reduced from 16 s to approximately 8 s. this is a pulse width reduction of 50%. note that as the fout frequen cy increases, the amount of pulse width reduction reduces and vice versa. furthermore, if the pwmout output is half the frequency of the fout output, this means your cpwm capacitor is too large and as a result, the pulse width is greater than the fout peri od. in this case, use equation 2 and reduce the capacitor value to less than the period. connect cpwm to vdd to disable the pwm function and in turn, save power. connect pwm_cntrl to vdd for a fixed pwm out output pulse width, which is determined by the cpwm pin capacit or only. applications information minimizing power consumption to keep the ts3003 s power consumption low, resistive loads at the fout and pwmout terminals increase dc power consumption and therefore should be as large as possible. capacitive loads at the fout and pwmo ut terminals increase the ts3003 s transient power consumption and, as well, should be as small as possible. one ch allenge to minimizing the ts3003 s transient power consumption is the probe capacitance of oscilloscopes and frequency counter instruments. most instruments exhibit an input capacitance of 15pf or more. unless buffered, the increase in transient load current can be as much as 400na. to minimize capacitive loading, the technique shown in figure 1 can be used. in this circuit, the principle of series - connected capacitors can be used to reduce the effecti ve capacitive load at the ts3003 s o t and pwmout terminals. to determine the optimal value for c ext once the probe capacitance is known by simply solving for c ext using the following expression: or example, if the instruments input probe capacitance is 15pf and the desired effective load capacitance at either or both fout and pwmout terminals is to be 5p , then the value of c ext should be 7.5p . figure 1 : using an external capa citor in series with probes reduces effective capacitive load. c t = 1 1 c oa 1 c ro equation 3 : external capacitor calculation
ts3003 ts3003ds r1p0 page 9 rtfds ts3003 start - up time as the ts3003 is powered up, its fout terminal (and pwmout terminal, if enabled) is active on c e the applied vdd is higher than 1.55 v . once the applied vdd is higher than 1.55 v , the master oscillator achieves steady - state operation within 8 ms. divide the pwmout output frequency by t wo with the ts3003 using a single resistor and capacitor, the ts3003 can be configured to a divide by two circuit as shown in figure 2 . to achieve a divide by two function with the ts3003 , the pulse width of the pwmout output must be at least a factor of 2 greater than the period set at fout by resistor rset . the cpwm capacitor selected must meet this pulse width requirement and can be calculated using equat ion 2. in figure 3, a value of 4 .32m for rs t sets the o t output period to 40s. a cpwm capacitor of 265pf was chosen, which sets the pulse width of pwmout to approxim ately 80s. this is well above the required minimum pulse width of 40s. using the ts3003 and a potentiometer to dim an led t he ts3003 can be configured to dim an led by modulating the pulse width of the pwmout output. with an rset = 2 m, the o t output frequency is approximately 51k hz (or 1 9.5s period) . refer to figure 3 . the cpwm capacitor was calculated using equat ion 2 with a pulse width of 15 s. to reduce the pulse width from 15 s and in turn, dim the led, a 1m potentiometer is used. the potentiometer is connected to the pwm_cntrl pin in a voltage divider configuration. the supply voltage of the circuit is 5 v. . figure 2 : configuring the ts3003 into a divide by t wo frequency divider figure 3 : ts3003 configured to dim an led with a potentiometer
ts3003 touchstone semiconductor, inc. page 10 630 alder d rive, milpitas, ca 95035 ts300 3 ds r1p0 +1 (408) 215 - 1220 ? www.touchstonesemi.com rtfds p ackage outline drawing information furnished by touchstone semiconductor is believed to be accurate and reliable. however, touchstone semiconductor does not assume any responsibility for its use nor for any infringements of patents or other rights of third parties that may result f rom its use , and all information provided by touchstone semiconductor and its suppliers is provided on an as is basis, without warranty of any kind . touchstone semiconductor reserves the right to change product specifications and product descriptions at any time without any advance notice. no license is granted by implication or otherwise under any patent or pat ent rights of touchstone semiconductor. touchstone semiconductor assumes no liability for applications assistance or customer product design. customers are responsible for thei r products and applications using touchstone semiconductor components. to minimi ze the risk associated with customer products and applications, customers should provide adequate design and operating safeguards. trademarks and registered trademarks are the property of t heir respective owners. 10 - pin tdfn33 package outline drawing (n .b., drawings are not to scale) b o t t o m v i e w 3 . 0 0 0 . 0 5 3 . 0 0 0 . 0 5 t o p v i e w p i n 1 d o t b y m a r k i n g n o t e ! ? a l l d i m e n s i o n s i n m m . ? c o m p l i a n t w i t h j e d e c m o - 2 2 9 s i d e v i e w 0 . 2 5 0 . 0 5 0 . 5 0 b s c 2 . 3 0 0 . 1 0 1 . 6 0 0 . 1 0 c o . 3 5 d a p s i z e 2 . 6 5 x 1 . 9 0 m m 0 . 4 0 0 . 0 5 0 . 3 0 r e f 0 . 7 5 0 . 0 5 0 . 0 0 0 . 0 5
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