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sg543 i 2 c clock generator for 3 dimm, pentium , pentium ii & pro boards. approved product international microcircuits, inc. 525 los coches st. rev.1.7 8/14/98 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 1 of 15 product features ? supports pentium ,pentium ii, m2, & k6 cpus. ? designed to the 440lx specification ? supports synchronous and asynchronous pci. ? 4 cpu / agp clocks ? up to 12 sdram clocks for 3 dimms. ? 7 pci synchronous clocks. ? optional common or mixed supply mode: (vdd = vddc = vddp = vddsd = vddi = 3.3v) or (vdd = vddc = vddsd = vddp = 3.3v, vddi = vddc = 2.5) ? < 250 ps skew among cpu or sdram clocks. ? < 250 ps skew among pci clocks. ? i 2 c 2-wire serial interface ? programmable registers featuring: - jumperless frequency selection - enable/disable each output pin - mode as tri-state, test, or normal ? power management capability. ? ioapic clocks for multiprocessor support. ? 48 mhz for usb support ? internal crystal load capacitors. ? 48-pin ssop package ? spread spectrum technology for emi reduction block diagram frequency table (mhz) s2 s1 s0 cpu pci 0 0 0 50.11 25.06 0 0 1 75.17 30.07 0 1 0 83.52 41.76 0 1 1 69.80 34.90 1 0 0 83.52 33.41 1 0 1 75.17 37.59 1 1 0 60.14 30.07 1 1 1 66.82* 33.41* * supports spread spectrum connection diagram note : purchase of i 2 c components of international microcircuits, inc. or one of its sublicensed associated companies conveys a license under the phillips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by phillips. vdd 1 ref0 2 vss 3 xin 4 sdram11 17 sdram10 18 vddsd2 19 sdram9 20 xout 5 vddp 6 pci _ f/ s1 7 pci0 / s2 8 vss 9 pci1 10 pci2 11 pci3 12 pci4 13 vddp 14 pci5 / ps# 15 vss 16 sdram8 21 vss 22 sdata 23 sdclk 24 vddi 48 ioapic 47 ref1 / cs# 46 vss 45 cpu0 44 cpu1 43 vddc 42 cpu2 41 cpu3 40 vss 39 sdram0 38 sdram1 37 vddsd0 36 sdram2 35 sdram3 34 vss 33 sdram4 32 sdram5 31 vddsd1 30 sdram6 29 sdram7 28 vss 27 48 mhz / s0 26 24 mhz / mode 25 24 mhz pll2 48 mhz cs# ps# s2 s1 pll1 s0 mode b cpu (0:3) vddi vddc vddp vddsd [0:2] 4 pci (0:5) 6 dly pci_f b sdram(0:11) 12 sdata sdclk ref xin xout ref0 ref1 ioapic b
sg543 i 2 c clock generator for 3 dimm, pentium , pentium ii & pro boards. approved product international microcircuits, inc. 525 los coches st. rev.1.7 8/14/98 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 2 of 15 pin description pin number pin name pwr i/o description 4 xin vdd i these pins form an on-chip reference oscillator when connected to terminals of an external parallel resonant crystal (nominally 14.318 mhz). xin may also serve as input for an externally generated reference 5 xout vdd o signal. if the external input is used, pin 5 is left unconnected. 7 pci_f vddp o this is a bi-directional pin. during power up, this pin is an input for frequency selection s1 control bit (see page 1, and app note on page 12) and sets the bit to its initial state. after a fixed period of time (see s1 vdd i * fig.1, page 3), this pin becomes a low skew pci clock output that does not stop when ps# (pin 15 or i 2 c register bit) is asserted. 8 pci0 vddp o this is a bi-directional pin. during power up, this pin is an input for frequency selection s2 control bit (see page1,and app note on page 12) and sets the bit to its initial state. after a fixed period of time (see fig.1, s2 vdd i * page 3), this pin becomes a low skew pci clock output that stops when ps# (pin 15 or its i 2 c register bit) is asserted. 10, 11, 12, 13 pci (1:4) vddp o low skew (<250 ps) clock outputs for pci frequencies. 15 pci5 vddp o if mode=1 this pin becomes low skew (<250 ps) clock outputs for pci frequencies. ps# vdd i * if mode=0 then this pin controls whether the pci clock outputs (except for pci-f) are enabled (set to a logic 1) or disabled (set to a logic 0) 44, 43, 41, 40 cpu(0:3) vddc o low skew (<250 ps) clock outputs for host frequencies such as cpu, agp, chipset, cache. 38, 37, 35, 34, 32, 31, 29, 28, 21, 20, 18, 17 sdram(0:11) vddsd(0:2) o synchronous dram dim clocks. 47 ioapic vddi o buffered clock of the crystal oscillator (nominally 14.31818 mhz). 46 ref1 vdd o if mode=1 this pin becomes a buffered copy of the internal crystal oscillator (nominally 14.31818 mhz) cs# vdd i * if mode=0 then this pin controls whether the cpu clock outputs are enabled (set to a logic 1) or disabled (set to a logic 0). 2 ref0 vdd o this pin is a buffered output of the crystal reference frequency. 26 48 mhz vdd i/o this is a bi-directional pin. during power up, this pin is an input for frequency selection s0 control bit (see page1,and app note s0 vdd i * on page 12) and sets the bit to its initial state. after a fixed period of time (see fig.1, page 3), this pin becomes a 48 mhz frequency clock. 25 24 mhz vdd o this is a bi-directional pin. during power up, this pin is an input that enables (0) or disables (1) the power management shared pins (46 and 15) (see app note on page 12) and sets the bit to its initial state. after a fixed period of time (see fig.1, page 3), this pin becomes a 24 mhz mode vdd i * frequency clock. *a 10k ohm resistor to vdd or vss is required to insure that the devices internal storage registers are correctly set at power up.
sg543 i 2 c clock generator for 3 dimm, pentium , pentium ii & pro boards. approved product international microcircuits, inc. 525 los coches st. rev.1.7 8/14/98 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 3 of 15 pin description (cont.) pin number pin name pwr i/o description 23 sdata vdd i serial data for i 2 c 2-wire control interface. has internal pull-up. 24 sdclk vdd i serial clock of i 2 c 2-wire control interface. has internal pull-up. 3, 9, 16, 22, 27, 33, 39, 45 vss -p ground pins for the chip. 1 vdd -p power supply pins for analog circuit, core logic and reference clock buffers. 48 vddi -p power supply pin for ioapic clock. may be either 3.3 or 2.5 volts. 6, 14 vddp - p 3.3 volt power for pci clocks. 36, 30, 19 vddsd [0:2] - p 3.3 volt power for sdram clocks 42 vddc - p power suppl y pin for cpu clocks ma y be either 2.5 v or 3.3v a bypass capacitor (0.1 m m f) should be placed as close as possible to each vdd, vddsd, vddi, and vddp pin. if these bypass capacitors are not close to the pins their high frequency filtering characteristic will be canceled by the lead inductances of the traces. power supply vdd hi-z ( tristate ) , inputs toggle , outputs fig.1 pci_f / s1 pci0 / s2 48 mhz / s0 24 mhz / mode
sg543 i 2 c clock generator for 3 dimm, pentium , pentium ii & pro boards. approved product international microcircuits, inc. 525 los coches st. rev.1.7 8/14/98 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 4 of 15 power management functions when mode=0, pins 15 and 46 are inputs ps# (pci_stop#), and cs# (cpu_stop#), respectively (when mode=1, these functions are not available). a particular output is enabled only when both the serial interface and these pins indicate that it should be enabled. the imisg543 clocks may be disabled according to the following table in order to reduce power consumption. all clocks are stopped in the low state. all clocks maintain a valid high period on transitions from running to stopped. the cpu/agp and pci clocks transition between running and stopped by waiting for one positive edge on pciclk_f followed by a negative edge on the clock of interest, after which high levels of the output are either enabled or disabled. cpu_stop# pci_stop# cpu pci other clks xtal & vcos 0 0 low low running running 0 1 low running running running 1 0 running low running running 1 1 running running running running please note that all clocks can be individually asynchronously enabled or stopped via the 2-wire i2c control interface. in this case all clocks are stopped in the low state. power management timing pciclk_f pci_stop# pciclk(0:5) cpu_stop# cpuclk(0:3) fig. 2
sg543 i 2 c clock generator for 3 dimm, pentium , pentium ii & pro boards. approved product international microcircuits, inc. 525 los coches st. rev.1.7 8/14/98 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 5 of 15 2-wire i 2 c control interface the 2-wire control interface implements a write only slave interface. the imisg543 cannot be read back. sub-addressing is not supported, thus all preceding bytes must be sent in order to change one of the control bytes. the 2-wire control interface allows each clock output to be individually enabled or disabled. during normal data transfer, the sdata signal only changes when the sdclk signal is low, and is stable when sdclk is high. there are two exceptions to this. a high to low transition on sdata while sdclk is high is used to indicate the start of a data transfer cycle. a low to high transition on sdata while sdclk is high indicates the end of a data transfer cycle. data is always sent as complete 8-bit bytes, after which an acknowledge is generated. the first byte of a transfer cycle is a 7-bit address with a read/write bit as the lsb. data is transferred msb first. the imisg543 will respond to writes to 10 bytes (max) of data to address d2 by generating the acknowledge (low) signal on the sdata wire following reception of each byte. the imisg543 will not respond to any other control interface conditions. previously set control registers are retained. serial control registers note: the pin# column lists the affected pin number where applicable. the @pup column gives the state at true power up. bytes are set to the values shown only on true power up, and not when the pwr_dwn# pin is activated. following the acknowledge of the address byte (d2), two additional bytes must be sent: 1) command code byte, and 2) byte count byte. although the data (bits) in these two bytes are considered dont care, they must be sent and will be acknowledged. after the command code and the count bytes have been acknowledged, the below described sequence (byte 0, byte 1, byte2, ....) will be valid and acknowledged. byte 0: frequency, function select register ( 1 = enable, 0 = stopped) bit @pup pin# description 7 1 * reserved 61 * s2 (for frequency table selection by software via i2c) 51 * s1 (for frequency table selection by software via i2c) 41 * s0 (for frequency table selection by software via i2c) 3 0 * enables freq. selection by hardware (set to 0) or software i 2 c (set to 1) 2 1 * reserved 1 0 0 0 bit1 bit0 1 1 tri-state 1 0 spread-on normal operation 0 1 test mode 0 0 spread-off normal operation
sg543 i 2 c clock generator for 3 dimm, pentium , pentium ii & pro boards. approved product international microcircuits, inc. 525 los coches st. rev.1.7 8/14/98 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 6 of 15 serial control registers (cont.) function table function outputs description cpu pci sdram ref ioapic tri-state hi-z hi-z hi-z hi-z hi-z normal see table see table cpu 14.318 14.318 test mode 1 tclk/2 tclk/4 tclk/2 tclk tclk notes: 1. tclk is a test clock over driven on the xin input during test mode. byte 1: cpu, sio, usb clock register (1 = enable, 0 = stopped) bit @pup pin# description 7 1 26 48 mhz enable/stopped 6 1 25 24 mhz enable/stopped 5 1 - 0 = reserved for imi test. 1 = normal operation. 4 x - reserved 3 1 40 cpuclk3 enable/stopped 2 1 41 cpuclk2 enable/stopped 1 1 43 cpuclk1 enable/stopped 0 1 44 cpuclk0 enable/stopped byte 2: pci clock register (1 = enable, 0 = stopped) bit @pup pin# description 7x - reserved 6 1 7 pci_f enable/stopped 5 1 15 pci5 enable/stopped 4 1 13 pci4 enable/stopped 3 1 12 pci3 enable/stopped 2 1 11 pci2 enable/stopped 1 1 10 pci1 enable/stopped 0 1 8 pci0 enable/stopped
sg543 i 2 c clock generator for 3 dimm, pentium , pentium ii & pro boards. approved product international microcircuits, inc. 525 los coches st. rev.1.7 8/14/98 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 7 of 15 serial control registers (cont.) byte 3: sdram clock register ( 1 = enable, 0 = stopped ) bit @pup pin# description 7 1 28 sdram7 enable/stopped 6 1 29 sdram6 enable/stopped 5 1 31 sdram5 enable/stopped 4 1 32 sdram4 enable/stopped 3 1 34 sdram3 enable/stopped 2 1 35 sdram2 enable/stopped 1 1 37 sdram1 enable/stopped 0 1 38 sdram0 enable/stopped byte 4: additional sdram clock register (1 = enable, 0 = stopped) bit @pup pin# description 7 x - reserved 6 x - reserved 5 x - reserved 4 x - reserved 3 1 17 sdram11 enable/stopped 2 1 18 sdram10 enable/stopped 1 1 20 sdram9 enable/stopped 0 1 21 sdram8 enable/stopped byte 5: peripheral control (1 = enable, 0 = stopped) bit @pup pin# description 7 x - reserved 6 x - reserved 5 x - reserved 4 1 47 ioapic enable/stopped 3 x - reserved 2 x - reserved 1 x 46 ref1 / cs# enable/stopped 0 1 2 ref0 enable/stopped
sg543 i 2 c clock generator for 3 dimm, pentium , pentium ii & pro boards. approved product international microcircuits, inc. 525 los coches st. rev.1.7 8/14/98 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 8 of 15 spread spectrum clocking spectrum spreading selection table min (mhz) center (mhz) max (mhz) cpu frequency % of frequency spreading mode 65.98 66.82 67.66 66 mhz -/+ 1.25% center maximum ratings voltage relative to vss: -0.3v voltage relative to vdd: 0.3v storage temperature: -65oc to + 150oc operating temperature: 0oc to +70oc maximum power supply: 7v this device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. for proper operation, vin and vout should be constrained to the range: vss<(vin or vout) sg543 i 2 c clock generator for 3 dimm, pentium , pentium ii & pro boards. approved product international microcircuits, inc. 525 los coches st. rev.1.7 8/14/98 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 9 of 15 electrical characteristics characteristic symbol min typ max units conditions input low voltage vil - - 0.8 vdc - input high voltage vih 2.0 - - vdc - input low current iil -66 a input high current iih 5 a tri-state leakage current ioz - - 10 a dynamic supply current idd - - 220 ma cpu = 66.6 mhz, pci = 33.3 mhz static supply current isdd - - 35 ma - short circuit current isc 25 - - ma 1 output at a time - 30 seconds vdd = vddp = vddsd(0:2) =3.3v 5 %, vddc = vddi = 2.5 + 5%, ta = 0oc to +70oc switching characteristics characteristic symbol min typ max units conditions output duty cycle - 45 50 55 % measured at 1.5v cpu/sdram to pci offset toff 1 - 4 ns 15 pf load measured at 1.5v skew (cpu-cpu), (pci- pci), (sdram-sdram) tskew1 - - +250 ps 15 pf load measured at 1.5v skew (cpu-sdram) tskew2 - - +500 ps 15 pf load measured at 1.5v d period adjacent cycles d p - - +250 ps - jitter spectrum 20 db bandwidth from center bw j 500 khz overshoot/undershoot beyond power rails v over - - 1.5 v 22 ohms @ source of 8 inch pcb run to 15 pf load ring back exclusion v rbe 0.7 2.1 v note1 vdd = vddp = vddsd(0:2) =3.3v 5 %, vddc = vddi = 2.5 + 5%, ta = 0oc to +70oc note 1: ring back must not enter this range. jitter characteristics device maximum conditions cpu, sdram 250 ps 15 pf pci 500 ps 30 pf
sg543 i 2 c clock generator for 3 dimm, pentium , pentium ii & pro boards. approved product international microcircuits, inc. 525 los coches st. rev.1.7 8/14/98 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 10 of 15 tb40ax_v type buffer characteristics for cpu (0:3) characteristic symbol min typ max units conditions pull-up current min ioh min 22 - 31 ma vout = vdd -.5v pull-up current max ioh max 37 - 56 ma vout = 1.25v pull-down current min iol min 30 - 41 ma vout = 0.4v pull-down current max iol max 75 - 109 ma vout = 1.2v rise/fall time min between 0.4 v and 2.0 v trf min 0.4 - - ns 10 pf load rise/fall time max between 0.4 v and 2.0 v trf max - - 1.6 ns 20 pf load vdd = vddp = vddsd(0:2) =3.3v 5 %, vddc = 2.5 + 5%, ta = 0oc to +70oc tb40ax type buffer characteristics for ref0 and sdram(0:11) characteristic symbol min typ max units conditions pull-up current min ioh min 30 - 39 ma vout = vdd - .5v pull-up current max ioh max 44 - 64 ma vout = 1.5v pull-down current min iol min 30 - 40 ma vout = 0.4v pull-down current max iol max 75 - 103 ma vout = 1.2v rise/fall time min between 0.4 v and 2.4 v trf min 0.5 - - ns 20 pf load rise/fall time max between 0.4 v and 2.4 v trf max - - 1.3 ns 30 pf load vdd = vddp = vddsd(0:2) =3.3v 5 %, vddc = vddi = 2.5 + 5%, ta = 0oc to +70oc
sg543 i 2 c clock generator for 3 dimm, pentium , pentium ii & pro boards. approved product international microcircuits, inc. 525 los coches st. rev.1.7 8/14/98 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 11 of 15 bt4lp112c type buffer characteristics for pciclk(0:5,f) and ref1 characteristic symbol min typ max units conditions pull-up current min ioh min 18 - 23 ma vout = vdd - .5v pull-up current max ioh max 44 - 64 ma vout = 1.5v pull-down current min iol min 18 - 25 ma vout = 0.4v pull-down current max iol max 50 - 70 ma vout = 1.5v rise/fall time min between 0.4 v and 2.4 v trf min 0.5 - - ns 15 pf load rise/fall time max between 0.4 v and 2.4 v trf max - - 2.0 ns 30 pf load vdd = vddp = vddsd(0:2) =3.3v 5 %, vddc = vddi = 2.5 + 5%, ta = 0oc to +70oc tb4l1_v type buffer characteristics for ioapic characteristic symbol min typ max units conditions pull-up current min ioh min 13 - 20 ma vout = vdd - .5v pull-up current max ioh max 22 - 37 ma vout = 1.25v pull-down current min iol min 18 - 23 ma vout = 0.4v pull-down current max iol max 50 - 61 ma vout = 1.5v rise/fall time max between 0.4 v and 2.4 v trf 0.4 - 1.6 ns 20 pf load vdd = vddp = vddsd(0:2) =3.3v 5 %, vddc = vddi = 2.5 + 5%, ta = 0oc to +70oc bt5lp1 type buffer characteristics for 24m, 48m characteristic symbol min typ max units conditions pull-up current min ioh min 13 - 17 ma vout = vdd - .5v pull-up current max ioh max 30 - 44 ma vout = 1.5v pull-down current min iol min 13 - 19 ma vout = 0.4v pull-down current max iol max 32 - 44 ma vout = 1.5v rise/fall time max between 0.4 v and 2.4 v trf - - 2.0 ns 20 pf load vdd = vddp = vddsd(0:2) =3.3v 5 %, vddc = vddi = 2.5 + 5%, ta = 0oc to +70oc
sg543 i 2 c clock generator for 3 dimm, pentium , pentium ii & pro boards. approved product international microcircuits, inc. 525 los coches st. rev.1.7 8/14/98 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 12 of 15 crystal and reference oscillator parameters characteristic symbol min typ max units conditions frequency f o 12.00 14.31818 16.00 mhz tolerance tc - - +/-100 ppm calibration note 1 ts - - +/- 100 ppm stability (ta -10 to +60c) note 1 ta - - 5 ppm aging (first year @ 25c) note 1 mode om - - - parallel resonant pin capacitance cp 36 pf capacitance of xin and xout pins to g round (each) dc bias voltage v bias 0.3vdd vdd/2 0.7vdd v startup time ts - - 30 m s load capacitance cl - 20 - pf the crystals rated load. note 1 effective series resistance (esr) r1 - - 40 ohms power dissipation dl - - 0.10 mw note 1 shunt capacitance co - -- 8 pf crystals internal packa g e capacitance (total) for maximum accuracy, the total circuit loadin g capacitance should be equal to cl. this loadin g capacitance is the effective capacitance across the crystal pins and includes the device pin capacitance (cp) in parallel with any circuit traces, the clock g enerator and any onboard discrete load capacitors. bud g etin g calculations typical trace capacitance, (< half inch) is 4 pf, load to the crystal is therefore = 2.0 pf clock g enerator internal pin capacitance of 36 pf, load to the crystal is therefore = 18.0 pf the total parasitic capacitance would therefore be = 20.0 pf. note 1: it is recommended but not mandatory that a crystal meets these specifications.
sg543 i 2 c clock generator for 3 dimm, pentium , pentium ii & pro boards. approved product international microcircuits, inc. 525 los coches st. rev.1.7 8/14/98 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 13 of 15 application note for selection on bidirectional pins pins 7, 8, 25 and 26 are power up bidirectional pins and are used for selecting different functions in this device (see pin description, page 2). during power-up of the device, these pins are in input mode (see fig1, page4), therefore, they are considered input select pins internal to the ic, these pins have a large value pull-up each (250k w) , therefore, a selection 1 is the default. if the system uses a slow power supply (over 5ms settling time), then it is recommended to use an external pullup (rup) in order to insure a high selection. in this case, the designer may choose one of two configurations, see fig.3a and fig. 3b. fig 3a represents an additional pull up resistor 50k w connected from the pin to the power line, which allows a faster pull to a high level. if a selection 0 is desired, then a jumper is placed on jp1 to a 5k w resistor as implemented as shown in fig.3a. please note the selection resistors (rup, and rdn ) are placed before the damping resistor (rd) close to the pin. fig 3b represents a single resistor 10k w connected to a 3 way jumper, jp2. when a 1 selection is desired, a jumper is placed between leads 1 and 3. when a 0 selection is desired, a jumper is placed between leads 1 and 2. if the system power supply is fast (less than 5ms settling time), then fig3a only applies and pull up rup resistor is not necessary. load load fig.3a fig.3b vdd vdd rup 50k rd imisg543 bidirectional jp1 jumper jp2 3 way jumper rsel 10k rd imisg543 bidirectional rdn 5k
sg543 i 2 c clock generator for 3 dimm, pentium , pentium ii & pro boards. approved product international microcircuits, inc. 525 los coches st. rev.1.7 8/14/98 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 14 of 15 pcb layout suggestion via to vdd island via to gnd plane via to vcc plane imisg543 c36 fb2 c40 5 6 7 8 9 10 11 12 13 14 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 15 16 17 19 20 21 22 23 24 18 30 29 28 27 26 25 31 c37 c3 c39 vcc 1 fb1 c34 22 m f 22 m f 1 2 3 4 c35 c38 c4 vcc 2 c5 vcc 1 fb3 c41 22 m f
sg543 i 2 c clock generator for 3 dimm, pentium , pentium ii & pro boards. approved product international microcircuits, inc. 525 los coches st. rev.1.7 8/14/98 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 15 of 15 package drawing and dimensions 48 pin ssop outline dimensions inches millimeters symbol min nom max min nom max a 0.095 0.102 0.110 2.41 2.59 2.79 a 1 0.008 0.012 0.016 0.20 0.31 0.41 a2 0.085 0.090 0.095 2.16 2.29 2.41 b 0.008 0.010 0.0135 0.203 0.254 0.343 c 0.005 .008 0.010 0.127 0.20 0.254 d 0.620 0.625 0.637 15.75 15.88 16.18 e 0.291 0.295 0.299 7.39 7.49 7.59 e 0.0256 bsc 0.640 bsc h 0.395 0.408 0.420 10.03 10.36 10.67 l 0.024 0.030 0.040 0.61 0.76 1.02 a0o 4o8o 0o4o8o ordering information part number package type production flow IMISG543CYB 48 pin ssop commercial, 0oc to +70oc note: the ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. marking: example: imi sg543cyb date code, lot # IMISG543CYB flow b = commercial, 0oc to + 70oc package y = ssop revision imi device number b e a a 1 a 2 e h a l c d

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