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isolated switching regulator with quad-channel isolators data sheet adum4470/ adum4471/ adum4472/ adum4473/ adum4474 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2012 analog devices, inc. all rights reserved. technical support www.analog.com features isolated pwm feedback with built in compensation primary side transformer driver for up to 2.5 w output power with 5 v input voltage regulated adjustable output: 3.3 v to 24 v up to 80% efficiency quad dc-to-25 mbps (nrz) signal isolation channels 200 khz to 1 mhz adjustable oscillator soft start function at power-up pulse-by-pulse overcurrent protection thermal shutdown 5000 v rms isolation high common-mode transient immunity: >25 kv/s 20-lead soic package with 8.3 mm creepage high temperature operation: 105c applications power supply start-up bias and gate drives isolated sensor interfaces process controls rs-232/rs-422/rs-485 transceivers functional block diagram adum4470/ adum4471/ adum4472/ adum4473/ adum4474 primary controller/ driver secondary controller internal feedback v dd2 oc fb v reg v dd1 v dda gnd 1 gnd 2 reg rect 5v v iso cha chb chc chd secondary data i/o 4-channel primary data i/o 4-channel i/oa i/ob i/oc i/od i/oa i/ob i/oc i/od 10991-001 figure 1. general description the adum4470 / adum4471/ adum4472/ adum4473 / adum4474 1 are quad-channel, digital isolators with a regu- lated dc-to-dc isolated power supply controller and an internal mosfet driver. the dc-to-dc controller has an internal isolated pwm feedback from the secondary side, based on the i coupler? chip scale transformer technology and complete loop compensation. this eliminates the need to use an optocoupler for feedback and compensates the loop for stability. the adum447x isolators provide a more stable output voltage and higher efficiency compared to unregulated isolated dc- to-dc power supplies. the fully integrated feedback and loop compensation in a wide-body soic package provide a smaller form factor and 8.3 mm creepage distance solution. the regulated feedback provides a relatively flat efficiency curve over the full output power range. the adum447x enable a dc- to-dc converter with a 3.3 v to 24 v isolated output voltage range from either a 5.0 v or a 3.3 v input voltage, with an output power of up to 2.5 w. the adum447x isolators provide four independent isolation channels in a variety of channel configurations and data rates. (the x in adum447x throughout this data sheet stands for the adum4470/ adum4471 / adum4472 / adum4473 / adum4474 .) 1 protected by u.s. patents 5,952,849; 6,873, 065; and 7075 329 b2. other patents pending.
adum4470/adum4471/adum 4472/adum4473/adum4474 data sheet rev. 0 | page 2 of 36 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 block diagrams of i/o channels.................................................... 3 specifications ..................................................................................... 4 electrical characteristics5 v primary input supply/ 5 v secondary isolated supply ................................................... 4 electrical characteristics3.3 v primary input supply/ 3.3 v secondary isolated supply ................................................ 6 electrical characteristics5 v primary input supply/ 3.3 v secondary isolated supply ................................................ 8 electrical characteristics5 v primary input supply/ 15 v secondary isolated supply ............................................... 10 package characteristics ............................................................. 12 regulatory approvals (pending) .............................................. 12 insulation and safety-related specifications .......................... 12 din v vde v 0884-10 (vde v 0884-10) insulation characteristics ............................................................................ 13 recommended operating conditions .................................... 13 absolute maximum ratings .......................................................... 14 esd caution ................................................................................ 14 pin configurations and function descriptions ......................... 15 typical performance characteristics ........................................... 20 applications information .............................................................. 26 theory of operation .................................................................. 26 application schematics ............................................................. 26 transformer design ................................................................... 27 transformer turns ratio ........................................................... 27 transformer et constant ......................................................... 27 transformer primary inductance and resistance ................. 28 transformer isolation voltage .................................................. 28 switching frequency .................................................................. 28 transient response .................................................................... 28 component selection ................................................................ 29 printed circuit board (pcb) layout ....................................... 29 thermal analysis ....................................................................... 30 propagation delay-related parameters ................................... 30 dc correctness and magnetic field immunity ........................... 30 power consumption .................................................................. 31 power considerations ................................................................ 32 insulation lifetime ..................................................................... 33 outline dimensions ....................................................................... 34 ordering guide .......................................................................... 34 revision history 12/12revision 0: initial version
data sheet adum4470/adum4471/adum4472/adum4473/adum4474 rev. 0 | page 3 of 36 block diagrams of i/o chan ne ls adum4470 10991-002 figure 2. adum4470 adum4471 10991-003 figure 3. adum4471 adum4472 10991-004 figure 4. adum4472 adum4473 10991-005 figure 5. adum4473 adum4474 10991-006 figure 6. adum4474
adum4470/adum4471/adum4472/adum4473/adum4474 data sheet rev. 0 | page 4 of 36 specifications electrical characteristi cs 5 v primary input su pply/5 v secondary isolated s upply 4.5 v (v dd1 = v dda ) 5.5 v; v dd2 = v reg = v iso = 5.0 v; f sw = 500 khz; all voltages are relative to their respective grounds; see the application schematic in figure 48 . all minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. all typical specifications are at t a = 25c, v dd1 = v dda = 5.0 v, v dd2 = v reg = v iso = 5.0 v. table 1 . dc -to - dc converter static specifications parameter symbol min typ max unit test conditions/comments dc - to - dc converter supply isolated output voltage v iso 4.5 5.0 5.5 v i iso = 0 ma, v iso = v fb (r1 + r2)/r2 feedback voltage setpoint v fb 1.15 1.25 1.3 7 v i iso = 0 ma line regulation v iso (line) 1 10 mv/v i iso = 50 ma, v dd1 1 = v dda 2 = 4.5 v to 5.5 v load regulation v iso (load) 1 2 % i iso = 50 ma to 200 ma output ripple v iso (rip) 50 mv p - p 20 mhz bandwidth, c out = 0.1 f||47 f, i iso = 100 ma output noise v iso (noise) 100 mv p - p 20 mhz bandwidth, c out = 0.1 f||47 f, i iso = 100 ma switching frequency f sw 1000 khz r oc = 50 k 200 khz r oc = 270 k 192 318 515 khz v oc = v dd2 (open - loop) switch on - resistance r on 0.5 undervoltage lockout, v dda , v dd2 supplies positive going threshold v uv+ 2.8 v negative going threshold v uv ? 2.6 v hysteresis v u vh 0.2 v dc to 2 mbps data rate 3 maximum output supply current 4 i iso (max) 400 500 ma f 1 mhz, v iso = 5.0 v efficiency at max imum output current 5 7 2 % i iso = i iso (max) , f 1 mhz i coupler data channels dc to 2 mbps data rate i dd1 supply current, no v iso load i dd1 (q) i iso = 0 ma, f 1 mhz adum4470 14 30 ma adum4471 15 30 ma adum4472 16 30 ma adum4473 17 30 ma adum4474 18 30 ma 25 mbps data rate (criz grade only) i dd1 supply current, no v iso load i dd1 (d) adum4470 44 ma i iso = 0 ma, c l = 15 pf, f = 12.5 mhz adum4471 46 ma i iso = 0 ma, c l = 15 pf, f = 12.5 mhz adum4472 48 ma i iso = 0 ma, c l = 15 pf, f = 12.5 mhz adum4473 50 ma i iso = 0 ma, c l = 15 pf, f = 12.5 mhz adum4474 52 ma i iso = 0 ma, c l = 15 p f, f = 12.5 mhz available v iso supply current 6 i iso (load) f sw = 500 khz adum4470 390 ma c l = 15 pf, f = 12.5 mhz adum4471 388 ma c l = 15 pf, f = 1 2.5 mhz adum4472 386 ma c l = 15 pf, f = 12.5 mhz adum4473 384 ma c l = 15 pf, f = 12.5 mhz adum4474 382 ma c l = 15 pf, f = 12.5 mhz i dd1 supply current, full v iso load 550 ma c l = 0 pf, f = 0 mhz, v dd1 = v dda = 5 v, i iso = 400 ma i/o input currents i ia , i ib , i ic , i id ? 20 +0.01 +20 a logic high input threshold v ih 2.0 v logic low input threshold v il 0.8 v
data sheet adum4470/adum4471/adum4472/adum4473/adum4474 rev. 0 | page 5 of 36 parameter symbol min typ max unit test conditions/comments logic high output voltages v oah , v obh , v och , v odh v dda ? 0.3, v iso ? 0.3 5.0 v i ox = ? 20 a, v ix = v ixh v dda ? 0.5, v iso ? 0. 5 4.8 v i ox = ? 4 ma, v ix = v ixh logic low output voltages v oal , v obl , v ocl , v odl 0.0 0.1 v i ox = 20 a, v ix = v ixh 0.0 0.4 v i ox = 4 ma, v ix = v ixh ac specifications adum447xar iz minimum pulse width pw 1000 ns c l = 15 pf, cmos signal levels maximum data ra te 1 mbps c l = 15 pf, cmos signal l evels propagation delay t plh , t phl 55 100 ns c l = 15 pf, cmos signal l evels pulse width distortion, |t plh ? t phl | pwd 40 ns c l = 15 pf, cmos signal l evels propagation delay skew t psk 50 ns c l = 15 pf, cmos signal l evels channel - to - channel matching t pskcd /t pskod 50 ns c l = 15 pf, cmos signal l evels adum447xcr iz minimum pulse width pw 40 ns c l = 15 pf, cmos signal l evels maximum data rate 25 mbps c l = 15 pf, cmos signal l evels propagation delay t plh , t phl 30 45 60 ns c l = 15 pf, cmos signal l evels pulse width distortion, |t plh ? t phl | pwd 6 ns c l = 15 pf, cmos signal l evels change vs. temperature 5 p s/ c c l = 15 pf, cmos signal l evels propagation delay skew t psk 15 ns c l = 15 pf, cmos signal l evels channel - to - channel matching, t pskcd 6 ns c l = 15 pf, cmos signal l evels codirectional channels channel - to - channel matching, t pskcd 15 ns c l = 15 pf, cmos signal l evels o pposing directional channels output rise/fall time (10% to 90%) t r /t f 2.5 ns c l = 15 pf, cmos signal l evels common - mode transient immunity |cm h | 25 35 kv/ s v ix = v dda or v iso , v cm = 1000 v, at l ogic high output transient magnitude = 800 v common - mode transient immunity |cm l | 25 35 kv/ s v ix = 0 v or v iso , v cm = 1000 v, at logic low output transient magnitude = 800 v refresh rate f r 1.0 mbps 1 v dd1 is the power supply for the push - pu ll transformer. 2 v dda is the power supply of side 1 of the adum447x. 3 the contributions of supply current values for all four channels are combined at identical data rates. 4 the v iso supply current is available for external use when all data rates are b elow 2 mbps. at data rates above 2 mbps, the data i/o channels draw additional current proportional to the data rate. additional supply current associated with an individual channel operating at a given data rate can be calculated as described in the power consumption section. the dynamic i/o channel load must be treated as an external load and included in the v iso power budget. 5 the power demands of the quiescent operation of the data channels were not separated from the power su pply section. efficiency includes the quiescent power consumed by the i/o channels as part of the internal power consumption. 6 this current is available for driving external loads at the v iso output. all channels are simultaneously driven at a maximum da ta rate of 25 mbps with full capacitive load representing the maximum dynamic load conditions. refer to the power consumption section for calculation of available current at less than the maximum data rate.
adum4470/adum4471/adum4472/adum4473/adum4474 data sheet rev. 0 | page 6 of 36 electrical character istics 3.3 v pri mary input supply/3. 3 v secondary isolated s upply 3.0 v v dd1 = v dda 3.6 v; v dd2 = v reg = v iso = 3.3 v; f sw = 500 khz; all voltages are relative to their respective grounds; see the application schematic in figure 48. all minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. all typical specifications are at t a = 25c, v dd1 = v dda = 3.3 v, v dd2 = v reg = v iso = 3.3 v. table 2 . dc -to - dc converter static specifications parameter symbol min typ ma x unit test conditions/comments dc - to - dc converter supply isolated output voltage v iso 3.0 3.3 3.6 v i iso = 0 ma, v iso = v fb (r1 + r2)/r2 feedback voltage setpoint v fb 1.15 1.25 1.3 7 v i iso = 0 ma line regulation v iso (line) 1 10 mv/v i iso = 50 ma, v dd1 1 = v dda 2 = 4.5 v to 5.5 v load regulation v iso (load) 1 2 % i iso = 50 ma to 200 ma output ripple v iso (rip) 50 mv p - p 20 mhz bandwidth, c out = 0.1 f||47 f, i iso = 100 ma output noise v iso (noise) 100 mv p - p 20 mhz bandwidth, c out = 0.1 f||47 f, i iso = 100 ma switching frequency f sw 1000 khz r oc = 50 k 200 khz r oc = 270 k 192 318 515 khz v oc = v dd2 (open - loop) switch on - resistance r on 0. 6 undervoltage lockout, v dda , v dd2 supplies positive going threshold v uv+ 2.8 v negative going threshold v uv ? 2.6 v hysteresis v u vh 0.2 v dc to 2 mbps data rate 3 maximum output supply current 4 i iso (max) 250 ma f 1 mhz, v iso = 5.0 v efficiency at maximum output current 5 68 % i iso = i iso (max) , f 1 mhz i coupler data channels dc to 2 mbps data rate i dd1 supply current, no v iso load i dd1 (q) i iso = 0 ma, f 1mhz adum4470 9 20 ma adum4471 10 20 ma adum4472 11 20 ma adum4473 11 20 ma adum4474 12 20 ma 25 mbps data rate (criz grade only) i dd1 supply current, no v iso load i dd1 (d) adum4470 28 ma i iso = 0 ma, c l = 15 pf, f = 12.5 mhz adum4471 29 ma i iso = 0 ma, c l = 15 pf, f = 12.5 mhz adum4472 31 ma i iso = 0 ma, c l = 15 pf, f = 12.5 mhz adum4473 32 ma i iso = 0 ma, c l = 15 pf, f = 12.5 mhz adum4474 34 ma i iso = 0 ma, c l = 15 pf, f = 12.5 mhz available v iso supply current 6 i iso (load) f sw = 500 khz adum4470 244 ma c l = 15 pf, f = 12.5 mhz adum4471 243 ma c l = 15 pf, f = 12.5 m hz adum4472 241 ma c l = 15 pf, f = 12.5 mhz adum4473 240 ma c l = 15 pf, f = 12.5 mhz adum4474 238 ma c l = 15 pf, f = 12.5 mhz i dd1 supply current, full v iso load 350 ma c l = 0 pf, f = 0 mhz, v dd1 = v dda = 5 v, i iso = 400 ma i/o input currents i ia , i ib , i ic , i id ? 10 +0.01 +10 a logic high input threshold v ih 1.6 v logic low input threshold v il 0.4 v
data sheet adum4470/adum4471/adum4472/adum4473/adum4474 rev. 0 | page 7 of 36 parameter symbol min typ ma x unit test conditions/comments logic high output voltages v oah , v obh , v och , v odh v dda ? 0.3, v iso ? 0.3 3.3 v i ox = ? 20 a, v ix = v ixh v dda ? 0.5, v iso ? 0. 5 3.1 v i ox = ? 4 ma, v ix = v ixh logic low output voltages v oal , v obl , v ocl , v odl 0.0 0.1 v i ox = 20 a, v ix = v ixh 0.0 0.4 v i ox = 4 ma, v ix = v ixh ac specifications adum447xar iz minimum pulse width pw 1000 ns c l = 15 pf, cmos signal l evels maximum data ra te 1 mbps c l = 15 pf, cmos signal l evels propagation delay t plh , t phl 60 100 ns c l = 15 pf, cmos signal l evels pulse width distortion, |t plh ? t phl | pwd 40 ns c l = 15 pf, cmos signal l evels propagation delay skew t psk 50 ns c l = 15 pf, cmos signal l evels channel - to - channel matching t pskcd /t pskod 50 ns c l = 15 pf, cmos signal l evels adum447xcr iz minimum pulse width pw 40 ns c l = 15 pf, cmos signal l evels maximum data rate 25 mbps c l = 15 pf, cmos signal l evels propagation delay t plh , t phl 30 60 70 ns c l = 15 pf, cmos signal l evels pulse width distortion, |t plh ? t phl | pwd 8 ns c l = 15 pf, cmos signal l evels change vs. temperature 5 p s/ c c l = 15 pf, cmos signal l evels propagation delay skew t psk 45 ns c l = 15 pf, cmos signal l evels channel - to - channel matching, t pskcd 8 ns c l = 15 pf, cmos signal l evels codirectional channels channel - to - channel matching, t pskcd 15 ns c l = 15 pf, cmos signal l evels o pposing directional channels output rise/fall time (10% to 90%) t r /t f 2.5 ns c l = 15 pf, cmos signal l evels common - mode transient immunity |cm h | 25 35 kv/ s v ix = v dda or v iso , v cm = 1000 v, at l ogic high output transient magnitude = 800 v common - mode transient immunity |cm l | 25 35 kv/ s v ix = 0 v or v iso , v cm = 1000 v, at logic low output transient magnitude = 800 v refresh rate f r 1.0 mbps 1 v dd1 is the power supp ly for the push - pull transformer. 2 v dda is the power supply of side 1 of the adum447x. 3 the contributions of supply current values for all four channels are combined at identical data rates. 4 the v iso supply current is available for external use when al l data rates are below 2 mbps. at data rates above 2 mbps, the data i/o channels draw additional current proportional to the data rate. additional supply current associated with an individual channel operating at a given data rate can be calculated as desc ribed in the power consumption section. the dynamic i/o channel load must be treated as an external load and included in the v iso power budget. 5 the power demands of the quiescent operation of the data channels were not separated from the power supply section. efficiency includes the quiescent power consumed by the i/o channels as part of the internal power consumption. 6 this current is available for driving external loads at the v iso output. all channels are simultaneously driv en at a maximum data rate of 25 mbps with full capacitive load representing the maximum dynamic load conditions. refer to the power consumption section for calculation of available current at less than the maximum data rate.
adum4470/adum4471/adum4472/adum4473/adum4474 data sheet rev. 0 | page 8 of 36 electrical character istics 5 v pri mary input supply/3. 3 v secondary isolated s upply 4.5 v v dd1 = v dda 5.5 v; v dd2 = v reg = v iso = 3.3 v ; f sw = 500 khz; all voltages are relative to their respective grounds; see the application schematic in figure 48. all minimum/maximum specifications apply ove r the entire recommended operating range, unless otherwise noted. all typical specifications are at t a = 25c, v dd1 = v dda = 5.0 v, v dd2 = v reg = v iso = 3.3 v. table 3 . dc -to - dc converter static specifications parameter symbol min t yp max unit test conditions/comments dc - to - dc converter supply isolated output voltage v iso 3.0 3.3 3.6 v i iso = 0 ma, v iso = v fb (r1 + r2)/r2 feedback voltage setpoint v fb 1.15 1.25 1.3 7 v i iso = 0 ma line regulation v iso (line) 1 10 mv/v i iso = 50 ma, v dd1 1 = v dda 2 = 4.5 v to 5.5 v load regulation v iso (load) 1 2 % i iso = 50 ma to 200 ma output ripple v iso (rip) 50 mv p - p 20 mhz bandwidth, c out = 0.1 f||47 f, i iso = 100 ma output noise v iso (noise) 100 mv p - p 20 mhz bandwidth, c out = 0.1 f||47 f, i iso = 100 ma switching frequency f sw 1000 khz r oc = 50 k 200 khz r oc = 270 k 192 318 515 khz v oc = v dd2 (open - loop) switch on - resistance r on 0. 5 undervoltage lockout, v dda , v dd2 supplies positive going threshold v uv+ 2.8 v negative going threshold v uv ? 2.6 v hysteresis v u vh 0.2 v dc to 2 mbps data rate 3 maximum output supply current 4 i iso (max) 400 ma f 1 mhz, v iso = 5.0 v efficiency at maximum output current 5 70 % i iso = i iso (max) , f 1 mhz i coupler data channels dc to 2 mbps data rate i dd1 supply current, no v iso load i dd1 (q) i iso = 0 ma, f 1 mhz adum4470 9 30 ma adum4471 10 30 ma adum4472 11 30 ma adum4473 11 30 ma adum4474 12 30 ma 25 mbps data rate (criz grade only) i dd1 supply current, no v iso load i dd1 (d) adum4470 33 ma i iso = 0 ma, c l = 15 pf, f = 12.5 mhz adum4471 33 ma i iso = 0 ma, c l = 15 pf, f = 12.5 mhz adum4472 33 ma i iso = 0 ma, c l = 15 pf, f = 12.5 mhz adum4473 33 ma i iso = 0 ma, c l = 15 pf, f = 12.5 mhz adum4474 33 ma i iso = 0 ma, c l = 15 pf, f = 12.5 mhz available v iso supply current 6 i iso (load) f sw = 500 khz adum4470 393 ma c l = 15 pf, f = 12.5 mhz adum4471 392 ma c l = 15 pf, f = 12.5 mhz adum4472 390 ma c l = 15 pf, f = 12.5 mhz adum4473 389 ma c l = 15 pf, f = 12.5 mhz adum4474 375 m a c l = 15 pf, f = 12.5 mhz i dd1 supply current, full v iso load 350 ma c l = 0 pf, f = 0 mhz, v dd1 = v dda = 5 v, i iso = 400 ma i/o input currents i ia , i ib , i ic , i id ? 20 +0.01 +20 a logic high input threshold v ih 2.0 v logic low input threshold v il 0.8 v
data sheet adum4470/adum4471/adum4472/adum4473/adum4474 rev. 0 | page 9 of 36 parameter symbol min t yp max unit test conditions/comments logic high output voltages v oah , v obh , v och , v odh v dda ? 0.3, v iso ? 0.3 3.3 v i ox = ? 20 a, v ix = v ixh v dda ? 0.5, v iso ? 0. 5 3.1 v i ox = ? 4 ma, v ix = v ixh logic low output voltages v oal , v obl , v ocl , v odl 0.0 0.1 v i ox = 20 a, v ix = v ixh 0.0 0.4 v i ox = 4 ma, v ix = v ixh ac specifications adum447xar iz minimum pulse width pw 1000 ns c l = 15 pf, cmos signal l evels maximum data ra te 1 mbps c l = 15 pf, cmos signal l evels propagation delay t plh , t phl 55 100 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh ? t phl | pwd 40 ns c l = 15 pf, cmos signal l evels propagation delay skew t psk 50 ns c l = 15 pf, cmos signal l evels channel - to - channel matching t pskcd /t pskod 50 ns c l = 15 pf, cmos signal l evels adum447xcr iz minimum pulse width pw 40 ns c l = 15 pf, cmos signal l evels maximum data rate 25 mbps c l = 15 pf, cmos signal l evels propagation delay t plh , t phl 30 50 70 ns c l = 15 pf, cmos signal l evels pulse width distortion, |t plh ? t phl | pwd 8 ns c l = 15 pf, cmos signal l evels change vs. temperature 5 p s/ c c l = 15 pf, cmos signal l evels propagation delay skew t psk 15 ns c l = 15 pf, cmos signal l evels channel - to - channel matching, t pskcd 8 ns c l = 15 pf, cmos signal l evels codirectional channels channel - to - channel matching, t pskcd 15 ns c l = 15 pf, cmos signal l evels o pposing directional channels output rise/fall time (10% to 90%) t r /t f 2.5 ns c l = 15 pf, cmos signal l evels common - mode transient immunity |cm h | 25 35 kv/ s v ix = v dda or v iso , v cm = 1000 v, at l ogic high output transient magnitude = 800 v common - mode transient immunity |cm l | 25 35 kv/ s v ix = 0 v or v iso , v cm = 1000 v, at logic low output transient magnitude = 800 v refresh rate f r 1.0 mbps 1 v dd1 is the power supply for the push - pull transformer. 2 v dda is the power supply of side 1 of the adum447x. 3 the contributions of supply current values for all four channels are combined at identical data rates. 4 the v iso supply current is available for e xternal use when all data rates are below 2 mbps. at data rates above 2 mbps, the data i/o channels draw additional current proportional to the data rate. additional supply current associated with an individual channel operating at a given data rate can be calculated as described in the power consumption section. the dynamic i/o channel load must be treated as an external load and included in the v iso power budget. 5 the power demands of the quiescent operation of the data channels were not separated from the power supply section. efficiency includes the quiescent power consumed by the i/o channels as part of the internal power consumption. 6 this current is available for driving external loads at the v iso output. all channels are simultaneously driven at a maximum data rate of 25 mbps with full capacitive load representing the maximum dynamic load conditions. refer to the power consumption section for calculation of available current at less than the maximu m data rate.
adum4470/adum4471/adum4472/adum4473/adum4474 data sheet rev. 0 | page 10 of 36 electrical character istics 5 v pr imary input supply/1 5 v secondary isolated s upply 4.5 v v dd1 = v dda 5.5 v; v reg = v iso = 15 v; v dd2 = 5.0 v; f sw = 500 khz; all voltages are relative to their respective grounds; see the application schematic in figure 49 . all minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. all typical specifications are at t a = 25c, v dd1 = v dda = 5.0 v, v reg = v iso = 15 v, v dd2 = 5.0 v. table 4 . dc -to - dc converter static specifications parameter sym bol min typ max unit test conditions/comments dc - to - dc converter supply isolated output voltage v iso 13.8 15 16.2 v i iso = 0 ma, v iso = v fb (r1 + r2)/r2 feedback voltage setpoint v fb 1.15 1.25 1.3 7 v i iso = 0 ma v dd2 linear regulator r egulator voltage 4. 5 5.0 5. 5 v v reg = 7 v to 15 v, i dd2 = 0 ma to 50 ma dropout voltage 0.5 1.5 i dd2 = 50 ma line regulation v iso (line) 1 2 0 mv/v i iso = 50 ma, v dd1 1 = v dda 2 = 4.5 v to 5.5 v load regulation v iso (load) 1 3 % i iso = 2 0 ma to 80 ma output ripple v iso (rip) 200 mv p - p 20 mhz bandwidth, c out = 0.1 f||47 f, i iso = 100 ma output noise v iso (noise) 5 00 mv p - p 20 mhz bandwidth, c out = 0.1 f||47 f, i iso = 100 ma switching frequency f sw 1000 khz r oc = 50 k 200 khz r oc = 270 k 192 318 515 khz v oc = v dd2 (open - loop) switch on - resistance r on 0. 5 undervoltage lockout, v dda , v dd2 supplies positive going threshold v uv+ 2.8 v negative going threshold v uv ? 2.6 v hysteresis v u vh 0.2 v dc to 2 mbps data rate 3 maximum output supply current 4 i iso (max) 100 ma f 1 mhz, v iso = 5.0 v efficiency at maximum output current 5 7 8 % i iso = i iso (max) , f 1 mhz i coupler data channels dc to 2 mbps data rate i dd1 supply current, no v iso load i dd1 (q) i iso = 0 ma, f 1 mhz adum4470 25 45 ma adum4471 27 45 ma adum4472 29 45 ma adum4473 31 45 ma adum4474 33 45 ma 25 mbps data rate (criz grade only) i dd1 supply current, no v iso load i dd1 (d) adum4470 73 ma i iso = 0 ma, c l = 15 pf, f = 12.5 mhz adum4471 83 ma i iso = 0 ma, c l = 15 pf, f = 12.5 mhz adum4472 93 ma i iso = 0 ma, c l = 15 pf, f = 12.5 mhz adum4473 102 ma i iso = 0 ma, c l = 15 pf, f = 12.5 mhz adum4474 112 ma i iso = 0 ma, c l = 15 pf , f = 12.5 mhz available v iso supply current 6 i iso (load) f sw = 500 khz adum4470 91 ma c l = 15 pf, f = 12.5 mhz adum4471 89 ma c l = 15 pf, f = 12.5 mhz adum4472 86 ma c l = 15 pf, f = 12.5 mhz adum4473 83 ma c l = 15 pf, f = 12.5 mhz adum4474 80 ma c l = 15 pf, f = 12.5 mhz i dd1 supply current, full v iso load 425 ma c l = 0 pf, f = 0 mhz, v dd1 = v dda = 5 v, i iso = 400 ma
data sheet adum4470/adum4471/adum4472/adum4473/adum4474 rev. 0 | page 11 of 36 parameter sym bol min typ max unit test conditions/comments i/o input currents i ia , i ib , i ic , i id ? 20 +0.01 +20 a logic high input threshold v ih 2.0 v logic low input threshold v il 0.8 v logic high output voltages v oah , v obh , v och , v odh v dda ? 0.3, v iso ? 0.3 5.0 v i ox = ? 20 a, v ix = v ixh v dda ? 0 .5, v iso ? 0. 5 4.8 v i ox = ? 4 ma, v ix = v ixh logic low output voltages v oal , v obl , v ocl , v odl 0.0 0.1 v i ox = 20 a, v ix = v ixh 0.0 0.4 v i ox = 4 ma, v ix = v ixh ac specifications adum447xar iz minimum pulse width pw 1000 ns c l = 15 pf, cmos signal l evels maximum data ra te 1 mbps c l = 15 pf, cmos signal l evels propagation delay t plh , t phl 55 100 ns c l = 15 pf, cmos signal l evels pulse width distortion, |t plh ? t phl | pwd 40 ns c l = 15 pf, cmos signal l evels propagation delay skew t psk 50 ns c l = 15 pf, cmos signal l evels channel - to - channel matching t pskcd /t pskod 50 ns c l = 15 pf, cmos signal l evels adum447xcr iz minimum pulse width pw 40 ns c l = 15 pf, cmos signal l evels maximum data rate 25 mbps c l = 15 pf, cmos signal l evels propagation delay t plh , t phl 30 45 60 ns c l = 15 pf, cmos signal l evels pulse width distortion, |t plh ? t phl | pwd 6 ns c l = 15 pf, cmos signal l evels change vs. temperature 5 p s/ c c l = 15 pf, cmos signal l evels propagation delay skew t psk 15 ns c l = 15 pf, cmos signal l evels channel - to - channel matching, t pskcd 6 ns c l = 15 pf, cmos signal l evels codirectional channels channel - to - channel matching, t pskcd 15 ns c l = 15 pf, cmos signal l evels o pposing directional channels output rise/fall time (10% to 90%) t r /t f 2.5 ns c l = 15 pf, cmos signal l evels common - mode transient immunity |cm h | 25 35 kv/ s v ix = v dda or v iso , v cm = 1000 v, at l ogic high output transient magnitude = 800 v common - mode transient immunity |cm l | 25 35 kv/ s v ix = 0 v or v iso , v cm = 1000 v, at logic low output transient magnitude = 800 v refresh rate f r 1.0 mbps 1 v dd1 is the power supply for the push - pull transformer. 2 v dda is the power supply of side 1 of the adum447x. 3 the contributions of supply current values for all four channels are combined at identical data rates. 4 the v iso supply current is available for external use when all data rates are below 2 mbps. at data rates above 2 mbps, the data i/o c hannels draw additional current proportional to the data rate. additional supply current associated with an individual channel oper ating at a given data rate can be calculated as described in the power consumption section. the dynamic i/o channel load must be treated as an external load and included in the v iso power budget. 5 the power demands of the quiesce nt operation of the data channels were not separated from the power supply section. efficiency includes the quiescent power consumed by the i/o channels as part of the internal power consumption. 6 this current is available for driving external loads at t he v iso output. all channels are simultaneously driven at a maximum data rate of 25 mbps with full capacitive load representing the maximum dynamic load conditions. refer to the power consumption section for calculation of availabl e current at less than the maximum data rate.
adum4470/adum4471/adum4472/adum4473/adum4474 data sheet rev. 0 | page 12 of 36 package characterist ics table 5 . parameter symbol min typ max unit test conditions/comments resistance (input to output) 1 r i - o 10 12 capacitance (input to output) 1 c i - o 2.2 pf f = 1 mhz ic junction to ambient thermal resistance ja 45 c/w thermocouple located at center of package underside, test conducted on 4 - layer board with thin traces 2 t hermal shutdown thermal shutdown threshold ts sd 150 c t j rising thermal shutdown hysteresis ts sd - hys 20 c 1 the device is considered a 2 - terminal device: pin 1 to pin 10 are shorted together; and pin 11 to pin 20 are shorted together. 2 see the thermal analysis section for thermal model d efinitions. regulatory approvals (pending) table 6 . ul csa vde recognized under the ul 1577 component recognition p rogram 1 approved under csa component acceptance notice #5a certified according to din v vde v 0884 -10 (vde v 0884 - 10):2006 - 12 2 single protection, 5000 v rms isolation voltage basic insulation per csa 60950 -1 -03 and iec 60950 - 1, 600 v rms (848 v peak) max imum working voltage reinforced insulation per csa60950 - 1 - 03 and iec 60950- 1, 400 v rms (5 65 v peak) maximum working voltage reinforced insulation per iec 60601 - 1 250 v rms (353 v peak) maximum working voltage reinforced insulation, 84 9 v peak file e2141 00 file 205078 file 2471900 - 4880 - 0001 1 in accordance with ul 1577, each adum4 4 7x is proof tested by applying an insulation test voltage of 6000 v rms for 1 sec (current leakage detection limit = 10 a). 2 in accordance with din v vde v 0884 - 10 , each of the adum447x is proof tested by applying an insulation test voltage of 1050 v peak for 1 sec (partial discharge detection limit = 5 pc). the asterisk (*) marking branded on the component designates din v vde v 0884 - 10 approval. insulation and safet y - related specificatio ns table 7 . parameter symbol value unit test conditions/comments rated dielectric insulation voltage 5000 v rms 1 - minute duration minimum external air gap (clearance) l(i01) >8.0 mm measured from input terminals to output terminals, shortest distance through air minimum external tracking (creepage) l(i02) >8. 3 mm measured from input terminals to output terminals, shortest distance path along body minimum internal gap (internal clearance) 0.017 min mm distance through insulation tracking resistance (comparative tracking index) cti >400 v din iec 112/vde 0303 part 1 isolation group ii material group (din vde 0110, 1/89, table 1)
data sheet adum4470/adum4471/adum4472/adum4473/adum4474 rev. 0 | page 13 of 36 din v vde v 0 884 - 10 (vde v 0884 - 10) insulation character istics these isolators are suitable for reinforced electrical isolation only within the safety limit data. protective circuits ensure maintenance of the safety data . the asterisk (*) marking on packages denotes di n v vde v 0884 - 10 approval. table 8 . description test conditions/comments symbol characteristic unit installation classification per din vde 0110 for rated mains voltage 150 v rms i to iv for rated mains voltage 300 v rms i to iv for rated mains voltage 400 v rms i to ii i climatic classification 40/105/21 pollution degree per din vde 0110, table 1 2 maximum working insulation voltage v iorm 849 v peak input - to - output test voltage, method b 1 v iorm 1.875 = v pd (m) , 100% production test, t ini = t m = 1 sec, partial discharge < 5 pc v pd (m) 1 592 v peak input - to - output test voltage, method a v iorm 1. 5 = v pd (m) , t ini = 60 sec, t m = 1 0 sec, partia l discharge < 5 pc v pd (m) after environmental tests subgroup 1 1 2 7 3 v peak after input and/or safety test subgroup 2 and subgroup 3 v iorm 1.2 = v pd (m) , t ini = 60 sec, t m = 1 0 sec, partial discharge < 5 pc 1018 v peak highest allowable overvolta ge v iotm 6 000 v peak surge isolation voltage v peak = 10 kv, 1.2 s rise time, 50 s, 50% fall time v iosm 6 000 v peak safety limiting values maximum value allowed in the event of a failure (see figure 7 ) case temperature t s 150 c side 1 , side 2 p vdda , p vreg power dissipation p vdda , p vreg 2.78 w insulation resistance at t s v io = 500 v r s >10 9 0 100 200 300 400 500 600 0 50 100 150 200 ambient temperature (c) safe operating v dd1 current (ma) 10991-007 figure 7 . thermal derating curve, dependence of safety limiting values on case temperature, per din v vde v 0884 - 10 recommended operatin g conditions table 9 . parameter symbol min max unit temperature operating temperature t a ? 40 +105 c supply voltage v dd1 at v iso = 3.3 v v dd1 3.0 3.6 v v dd1 at v iso = 3.3 v v dd1 4.5 5.5 v v dd1 at v iso = 5.0 v v dd1 4.5 5.5 v load minimum load i iso (min) 10 ma
adum4470/adum4471/adum4472/adum4473/adum4474 data sheet rev. 0 | page 14 of 36 absolute maximum rat ings ambient tem perature = 25c, unless otherwise noted . table 10. parameter rating storage temperature range (t st ) ? 55c to +150c ambient operating temperature range (t a ) ? 40c to +105c supply voltages v dda , v dd2 1 , 2 ? 0.5 v to +7.0 v v reg , x1, x2 1 ? 0.5 v to +20.0 v input voltage (v ia , v ib , v ic , v id ) ? 0.5 v to + v ddi + 0.5 v output voltage (v oa , v ob , v oc , v od ) ? 0.5 v to v ddo + 0.5 v average output current per pin ? 10 ma to +10 ma common - mode transients 3 ? 10 0 kv/s to +100 kv/s 1 all voltage s are relative to their respective ground. 2 v dd1 is the power supply for the push - pull transformer, and v dda is the power supply of side 1 of t he adum447x. 3 refers to common - mode transients across the insulation barrier. common - mode transients exceeding the absolute maximum ratings may cause latch - up or permanent damage. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the oper ational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 11 . maximum continuous working volt age supporting 50- year minimum lifetim e 1 parameter max unit constraint ac voltage, bipolar waveform 848 v peak 50- year minimum lifetime ac voltage, unipolar waveform 848 v peak 50- year minimum lifetime dc voltage 848 v peak 50- year minimum lifetime 1 refers to the continuous voltage magni tude imposed across the isolation barrier. see the insulation lifetime section for more information. esd caution
data sheet adum4470/adum4471/adum 4472/adum4473/adum4474 rev. 0 | page 15 of 36 pin configurations and function descriptions x1 1 *gnd 1 2 nc 3 x2 4 v reg 20 gnd 2 * 19 v dd2 18 fb 17 v ia 5 v ib 6 v ic 7 v oa 16 v ob 15 v oc 14 v id 8 v od 13 v dda 9 oc 12 *gnd 1 10 gnd 2 * 11 top view (not to scale) adum4470 notes 1. the pin labeled nc can be allowed to float, but it is better to connect this pin to ground. avoid routing high speed signals through these pins because noise coupling may result. *pin 2 and pin 10 are internally connected, and connecting both to gnd 1 is recommended. pin 11 and pin 19 are internally connected, and connecting both to gnd 2 is recommended. 10991-008 figure 8. adum4470 pin configuration table 12. adum4470 pin function descriptions pin no. mnemonic description 1 x1 transformer driver output 1. 2, 10 gnd 1 ground reference for isolator primary. 3 nc this pin is not connected internally (see figure 8). 4 x2 transformer driver output 2. 5 v ia logic input a. 6 v ib logic input b. 7 v ic logic input c. 8 v id logic input d. 9 v dda primary supply voltage 3.0 v to 5.5 v. connect to v dd1 . connect a 0.1 f bypass capacitor from v dda to gnd 1 . 11, 19 gnd 2 ground reference for isolator side 2. 12 oc oscillator control pin. when oc = logic high = v dd2 , the secondary controller runs open-loop. to regulate the output voltage, connect a resistor between the oc pin and gnd 2 , and the secondary controller runs at a frequency of 200 khz to 1 mhz, as programmed by the resistor value. 13 v od logic output d. 14 v oc logic output c. 15 v ob logic output b. 16 v oa logic output a. 17 fb feedback input from the secondary output voltage, v iso . use a resistor divider from v iso to the fb pin to make the v fb voltage equal to the 1.25 v internal reference level using the v iso = v fb (r1 + r2)/r2 formula. the resistor divider is required even in open-loop mode to provide soft start. 18 v dd2 internal supply voltage pin for the secondary side. when a sufficient external voltage is supplied to v reg , the internal regulator regulates the v dd2 pin to 5.0 v. otherwise, v dd2 should be in the 3.0 v to 5.5 v range. connect a 0.1 f bypass capacitor from v dd2 to gnd 2 . 20 v reg input of the internal regulator to power the secondary side controller. v reg should be in the 5.5 v to 15 v range to regulate the v dd2 output to 5.0 v.
adum4470/adum4471/adum4472/adum4473/adum4474 data sheet rev. 0 | page 16 of 36 x1 1 *gnd 1 2 nc 3 x2 4 v reg 20 gnd 2 * 19 v dd2 18 fb 17 v ia 5 v ib 6 v ic 7 v oa 16 v ob 15 v oc 14 v od 8 v id 13 v dda 9 oc 12 *gnd 1 10 gnd 2 * 11 top view (not to scale) adum4471 notes 1. the pin labeled nc can be allowed to float, but it is better to connect this pin to ground. avoid routing high speed signals through these pins because noise coupling may result. * pin 2 and pin 10 are internally connected, and connecting both to gnd 1 is recommended. pin 11 and pin 19 are internally connected, and connecting both to gnd 2 is recommended. 10991-009 figure 9. adum4471 pin configuration table 13. adum4471 pin function descriptions pin no. mnemonic descri ption 1 x1 transformer driver output 1. 2, 10 gnd 1 ground reference for isolator primary. 3 nc this pin is not connected internally (see figure 9 ). 4 x2 transformer driver output 2. 5 v ia logic input a. 6 v ib logic input b. 7 v ic logic input c. 8 v od logic output d. 9 v dda primary supply voltage 3.0 v to 5.5 v . connect to v dd1 . connect a 0.1 f bypass capacitor from v dda to gnd 1 . 11, 1 9 gnd 2 ground reference for isolator side 2. 1 2 oc oscillator control pin. when oc = logic high = v dd2 , the secondary controller runs open - loop. to regulate the output voltage, connect a resistor between the oc pin and gnd 2 , and the secondary controller runs at a frequency of 200 khz to 1 mhz, as programmed by the resistor value. 13 v id logic input d . 14 v oc logic output c . 15 v ob logic output b . 16 v oa logic output a . 1 7 fb feedback input from the secondary output voltage , v iso . use a resistor divider from v iso to the fb pin to make the v fb voltage equal to the 1.25 v internal refere nce level using the v iso = v fb (r1 + r2)/r2 formula. the resistor divider is required even in open - loop mode to provide soft start. 1 8 v dd2 internal supply voltage pin for the secondary side. when a sufficient external voltage is supplied to v reg , the i nternal regulator regulates the v dd2 pin to 5.0 v. otherwise, v dd2 should be in the 3.0 v to 5.5 v range. connect a 0.1 f bypass capacitor from v dd2 to gnd 2 . 20 v reg input of the internal regulator to power the secondary side controller. v reg should be i n the 5.5 v to 15 v range to regulate the v dd2 output to 5.0 v.
data sheet adum4470/adum4471/adum4472/adum4473/adum4474 rev. 0 | page 17 of 36 x1 1 *gnd 1 2 nc 3 x2 4 v reg 20 gnd 2 * 19 v dd2 18 fb 17 v ia 5 v ib 6 v oc 7 v oa 16 v ob 15 v ic 14 v od 8 v id 13 v dda 9 oc 12 *gnd 1 10 gnd 2 * 11 top view (not to scale) adum4472 notes 1. the pin labeled nc can be allowed to float, but it is better to connect this pin to ground. avoid routing high speed signals through these pins because noise coupling may result. * pin 2 and pin 10 are internally connected, and connecting both to gnd 1 is recommended. pin 11 and pin 19 are internally connected, and connecting both to gnd 2 is recommended. 10991-010 figure 10 . adum4472 pin configuration table 14. adum4472 pin function descriptions pin no. mnemonic description 1 x1 transformer driver output 1. 2, 10 gnd 1 ground reference for isolator primary. 3 nc this pin is not connected internally (see figure 10). 4 x2 transfor mer driver output 2. 5 v ia logic input a. 6 v ib logic input b. 7 v oc logic output c. 8 v od logic output d. 9 v dda primary supply voltage 3.0 v to 5.5 v . connect to v dd1 . connect a 0.1 f bypass capacitor from v dda to gnd 1 . 11, 1 9 gnd 2 ground referenc e for isolator side 2. 1 2 oc oscillator control pin. when oc = logic high = v dd2 , the secondary controller runs open - loop. to regulate the output voltage, connect a resistor between the oc pin and gnd 2 , and the secondary controller runs at a frequency of 200 khz to 1 mhz, as programmed by the resistor value. 13 v id logic input d . 14 v ic logic input c . 15 v ob logic output b . 16 v oa logic output a . 1 7 fb feedback input from the secondary output voltage , v iso . use a resistor divider from v iso to the fb pin to make the v fb voltage equal to the 1.25 v internal reference level using the v iso = v fb (r1 + r2)/r2 formula. the resistor divider is required even in open - loop mode to provide soft start. 1 8 v dd2 internal supply voltage pin for the secondary sid e. when a sufficient external voltage is supplied to v reg , the internal regulator regulates the v dd2 pin to 5.0 v. otherwise, v dd2 should be in the 3.0 v to 5.5 v range. connect a 0.1 f bypass capacitor from v dd2 to gnd 2 . 20 v reg input of the internal re gulator to power the secondary side controller. v reg should be in the 5.5 v to 15 v range to regulate the v dd2 output to 5.0 v.
adum4470/adum4471/adum4472/adum4473/adum4474 data sheet rev. 0 | page 18 of 36 x1 1 *gnd 1 2 nc 3 x2 4 v reg 20 gnd 2 * 19 v dd2 18 fb 17 v ia 5 v ob 6 v oc 7 v oa 16 v ib 15 v ic 14 v od 8 v id 13 v dda 9 oc 12 *gnd 1 10 gnd 2 * 11 top view (not to scale) adum4473 notes 1. the pin labeled nc can be allowed to float, but it is better to connect this pin to ground. avoid routing high speed signals through these pins because noise coupling may result. * pin 2 and pin 10 are internally connected, and connecting both to gnd 1 is recommended. pin 11 and pin 19 are internally connected, and connecting both to gnd 2 is recommended. 10991-0 1 1 figure 11 . adum4473 pin configuration table 15. adum4473 pin function descriptions pin no. mnemonic description 1 x1 transformer driver output 1. 2, 10 gnd 1 ground reference for isolator primary. 3 nc this pin is not connected int ernally (see figure 11). 4 x2 transformer driver output 2. 5 v ia logic input a. 6 v ob logic output b. 7 v oc logic output c. 8 v od logic output d. 9 v dda primary supply voltage 3.0 v to 5.5 v . connect to v dd1 . connect a 0.1 f bypass capacitor from v dda to gnd 1 . 11, 1 9 gnd 2 ground reference for isolator side 2. 1 2 oc oscillator control pin. when oc = logic high = v dd2 , the secondary controller runs open - loop. to regulate the output voltage, connect a resistor between the oc pin and gnd 2 , and the secondary controller runs at a frequency of 200 khz to 1 mhz, as programmed by the resistor value. 13 v id logic input d . 14 v ic logic input c . 15 v ib logic input b . 16 v oa logic output a . 1 7 fb feedback input from the secondary output voltage , v iso . use a resistor divider from v iso to the fb pin to make the v fb voltage equal to the 1.25 v internal reference level using the v iso = v fb (r1 + r2)/r2 formula. the resistor divider is required even in open - loop mode to provide soft start. 1 8 v dd2 internal supply voltage pin for the secondary side. when a sufficient external voltage is supplied to v reg , the internal regulator regulates the v dd2 pin to 5.0 v. otherwise, v dd2 should be in the 3.0 v to 5.5 v range. connect a 0.1 f bypa ss capacitor from v dd2 to gnd 2 . 20 v reg input of the internal regulator to power the secondary side controller. v reg should be in the 5.5 v to 15 v range to regulate the v dd2 output to 5.0 v.
data sheet adum4470/adum4471/adum4472/adum4473/adum4474 rev. 0 | page 19 of 36 x1 1 *gnd 1 2 nc 3 x2 4 v reg 20 gnd 2 * 19 v dd2 18 fb 17 v oa 5 v ob 6 v oc 7 v ia 16 v ib 15 v ic 14 v od 8 v id 13 v dda 9 oc 12 *gnd 1 10 gnd 2 * 11 top view (not to scale) adum4474 notes 1. the pin labeled nc can be allowed to float, but it is better to connect this pin to ground. avoid routing high speed signals through these pins because noise coupling may result. * pin 2 and pin 10 are internally connected, and connecting both to gnd 1 is recommended. pin 11 and pin 19 are internally connected, and connecting both to gnd 2 is recommended. 10991-012 figure 12 . adum4474 pin configuration table 16. adum4474 pin function descriptions pin no. mnemonic description 1 x1 transformer driver output 1. 2, 10 gnd 1 ground ref erence for isolator primary. 3 nc this pin is not connected internally (see figure 12). 4 x2 transformer driver output 2. 5 v oa logic output a. 6 v ob logic output b. 7 v oc logic output c. 8 v od logic output d. 9 v dda prima ry supply voltage 3.0 v to 5.5 v. connect to v dd1 . connect a 0.1 f bypass capacitor from v dda to gnd 1 . 11, 1 9 gnd 2 ground reference for isolator side 2. 1 2 oc oscillator control pin. when oc = logic high = v dd2 , the secondary controller runs open - loop. to regulate the output voltage, connect a resistor between the oc pin and gnd 2 , and the secondary controller runs at a frequency of 200 khz to 1 mhz, as programmed by the resistor value. 13 v id logic input d . 14 v ic logic input c . 15 v ib logic input b . 16 v ia logic input a . 1 7 fb feedback input from the secondary output voltage , v iso . use a resistor divider from v iso to the fb pin to make the v fb voltage equal to the 1.25 v internal reference level using the v iso = v fb (r1 + r2)/r2 formula. the res istor divider is required even in open - loop mode to provide soft start. 1 8 v dd2 internal supply voltage pin for the secondary side. when a sufficient external voltage is supplied to v reg , the internal regulator regulates the v dd2 pin to 5.0 v. otherwise, v dd2 should be in the 3.0 v to 5.5 v range. connect a 0.1 f bypass capacitor from v dd2 to gnd 2 . 20 v reg input of the internal regulator to power the secondary side controller. v reg should be in the 5.5 v to 15 v range to regulate the v dd2 output to 5.0 v .
adum4470/adum4471/adum4472/adum4473/adum4474 data sheet rev. 0 | page 20 of 36 typical performance characteristics 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 0 50 100 150 200 250 300 350 400 450 500 f sw (khz) r oc (k?) 10991-013 figure 13 . switching frequency (f sw ) vs. r oc resistance 90 80 70 60 50 40 30 20 10 0 0 400 350 300 250 200 150 100 50 efficiency (%) load current (ma) f sw = 1mhz f sw = 700khz f sw = 500khz f sw = 200khz 10991-014 figure 14 . typical efficiency at 5 v in put to 5 v out put at various switching frequencies with 1: 2 coilcraft transformer (cr7983 - cl) 90 80 70 60 50 40 30 20 10 0 0 400 350 300 250 200 150 100 50 efficiency (%) load current (ma) f sw = 1mhz f sw = 700khz f sw = 500khz f sw = 200khz 10991-015 figure 15 . typical efficiency at 5 v in put to 5 v out put at various switching frequencies with 1:2 halo transformer (tgsad - 260v8lf) 90 80 70 60 50 40 30 20 10 0 0 400 350 300 250 200 150 100 50 efficiency (%) load current (ma) +25c ?40c +105c 10991-016 figure 16 . 5 v in put to 5 v out put efficiency over temperature with coilcraft transformer (cr7983 - cl) at 500 khz f sw 80 70 60 50 40 30 20 10 0 0 400 350 300 250 200 150 100 50 efficiency (%) load current (ma) 5v in to 5v out 5v in to 3.3v out 3.3v in to 3.3v out 10991-017 figure 17 . single - supply efficiency with coilcraft transformer (cr7983 - cl) at 500 khz f sw 70 60 50 40 30 20 10 0 0 200 150 100 50 efficiency (%) load current (ma) f sw = 1mhz f sw = 700khz f sw = 500khz f sw = 200khz 10991-018 figure 18 . typical eff iciency at 3.3 v in put to 5 v out put at various switching frequencies with 1:3 coilcraft transformer (cr7984 - cl )
data sheet adum4470/adum4471/adum4472/adum4473/adum4474 rev. 0 | page 21 of 36 70 60 50 40 30 20 10 0 0 200 175 150 125 100 75 50 25 efficiency (%) load current (ma) +25c ?40c +105c 10991-019 figure 19 . typical efficiency at 3.3 v in to 5 v o u t over temperature with 1:3 coilcraft transformer (cr7984 - cl) at 500 khz f sw 80 70 60 50 40 30 20 10 0 0 140 130 120 110 100 90 80 70 60 50 40 30 20 10 efficiency (%) load current (ma) f sw = 1mhz f sw = 700khz f sw = 500khz f sw = 200khz 10991-020 figure 20 . 5 v in put to 15 v out put efficiency at various switching frequencies with 1: 3 coilcraft transformer (cr7984 - cl) 90 80 70 60 50 40 30 20 10 0 0 140 130 120 110 100 90 80 70 60 50 40 30 20 10 efficiency (%) load current (ma) f sw = 1mhz f sw = 700khz f sw = 500khz f sw = 200khz 10991-021 figure 21 . 5 v in put to 15 v out put efficiency at various s witching frequencies with 1:3 halo transformer (tgsad - 290v8lf) 80 70 60 50 40 30 20 10 0 0 140 130 120 110 100 90 80 70 60 50 40 30 20 10 efficiency (%) load current (ma) +25c ?40c +105c 10991-022 figure 22 . 5 v in put to 1 5 v ou t put efficiency over temperature with coilcraft transformer (cr7984 - cl) at 500 khz f sw 80 70 60 50 40 30 20 10 0 0 70 65 60 55 50 45 40 35 30 25 20 15 10 5 efficiency (%) load current (ma) 5v in to 12v out 5v in to 15v out 10991-023 figure 23 . double - supply efficiency with coilcraft transformer (cr7985 - cl) at 500 khz f sw 1 5 1 0 5 0 0 2 5 2 0 1 5 1 0 5 da t a ra t e (mbps ) v cc = 5v, v iso = 5v v cc = 5v, v iso = 3.3v v cc = 3.3v, v iso = 3.3v i ch (ma) 10991-024 figure 24 . typical single - supply i ch supply current per forward data channel (15 pf output load)
adum4470/adum4471/adum4472/adum4473/adum4474 data sheet rev. 0 | page 22 of 36 15 10 5 0 0 25 20 15 10 5 data rate (mbps) i ch (ma) v cc = 5v, v iso = 5v v cc = 5v, v iso = 3.3v v cc = 3.3v, v iso = 3.3v 10991-025 figure 25 . typical single - su pply i ch supply current per reverse data channel (15 pf output load) 5 4 3 2 1 0 0 25 20 15 10 5 i iso(d) (ma) data rate (mbps) v cc = 5v, v iso = 5v v cc = 5v, v iso = 3.3v v cc = 3.3v, v iso = 3.3v 10991-026 figure 26 . typical single - supply i iso(d) dynamic supply current per output channel (15 pf output load) 5 4 3 2 1 0 0 25 20 15 10 5 i iso(d) (ma) data rate (mbps) v cc = 5v, v iso = 5v v cc = 5v, v iso = 3.3v v cc = 3.3v, v iso = 3.3v 10991-027 figure 27 . typical single - supply i iso(d) dynamic supply current per input channel (15 pf output load) 30 25 20 15 10 5 0 0 25 20 15 10 5 i ch (ma) data rate (mbps) v cc = 5v, v iso = 15v v cc = 5v, v iso = 12v 10991-028 figure 28 . typical double - supply current i ch per forward data channel (15 pf output load) 30 25 20 15 10 5 0 0 25 20 15 10 5 i ch (ma) data rate (mbps) v cc = 5v, v iso = 15v v cc = 5v, v iso = 12v 10991-029 figure 29 . typical double - suppl y i ch supply current per reverse data channel (15 pf output data) 5 4 3 2 1 0 0 25 20 15 10 5 i iso(d) (ma) data rate (mbps) v cc = 5v, v iso = 15v v cc = 5v, v iso = 12v 10991-030 figure 30 . typical double - supply i iso(d) dynamic supply current per output channel (15 pf output load)
data sheet adum4470/adum4471/adum4472/adum4473/adum4474 rev. 0 | page 23 of 36 5 4 3 2 1 0 0 25 20 15 10 5 i iso(d) (ma) data rate (mbps) v cc = 5v, v iso = 15v v cc = 5v, v iso = 12v 10991-031 figure 31 . typical double - sup ply i iso(d) dynamic supply current per input channel 6 5 4 3 2 1 0 0 5 10 15 20 25 30 v iso (v) time (ms) load = 10ma load = 50ma load = 400ma 10991-032 figure 32 . typical v iso startup 5 v in put to 5 v out put with 10 ma, 50 ma, and 400 ma output load 5 4 3 2 1 0 0 5 10 15 20 25 30 v iso (v) time (ms) load = 10ma load = 50ma load = 400ma 10991-033 figure 33 . typical v iso startup 5 v in put to 3. 3 v out put with 10 ma, 50 ma, and 400 ma output load 5 4 3 2 1 0 0 5 10 15 20 25 30 v iso (v) time (ms) load = 10ma load = 50ma load = 400ma 10991-034 figure 34 . typical v iso startup 3.3 v in put to 3.3 v out put with 10 ma, 50 ma, and 250 ma output load 5 4 3 2 1 0 0 5 10 15 20 25 30 v iso (v) time (ms) load = 10ma load = 50ma load = 400ma 10991-035 figure 35 . typical v iso startup 5 v in put t o 15 v out put with 10 ma, 20 ma, and 100 ma output load 0 1.0 0.5 ?2 0 2 4 6 8 14 10 12 v iso (v) i load (a) time (ms) 5.75 4.25 4.75 5.25 5.75 4.25 4.75 5.25 c out = 47f, l1 = 47h c out = 47f, l1 = 100h 90% load 10% load 10991-036 figure 36 . typical v iso load transient response 5 v in put to 5 v out put at 10% to 90% of 400 ma load at 500 khz f sw
adum4470/adum4471/adum4472/adum4473/adum4474 data sheet rev. 0 | page 24 of 36 0 1.0 0.5 ?2 0 2 4 6 8 14 10 12 v iso (v) i load (a) time (ms) 5.75 4.25 4.75 5.25 5.75 4.25 4.75 5.25 c out = 47f, l1 = 47h c out = 47f, l1 = 100h 90% load 10% load 10991-037 figure 37 . typical v iso lo ad transient response 5 v in put to 5 v out put at 10% to 90% of 400 ma load at 500 khz f sw with 0.1 f feedback capacitor 0 1.0 0.5 ?2 0 2 4 6 8 14 10 12 v iso (v) i load (a) time (ms) 4.0 2.5 3.0 3.5 4.0 2.5 3.0 3.5 c out = 47f, l1 = 47h c out = 47f, l1 = 100h 90% load 10% load 10991-038 figure 38 . typical v iso load transient response 5 v in put to 3.3 v out put at 10% to 90% of 40 0 ma load at 500 khz f sw 0 1.0 0.5 ?2 0 2 4 6 8 14 10 12 v iso (v) i load (a) time (ms) 4.0 2.5 3.0 3.5 4.0 2.5 3.0 3.5 c out = 47f, l1 = 47h c out = 47f, l1 = 100h 90% load 10% load 10991-039 figure 39 . typical v iso load transient response 5 v in put to 3.3 v out put at 10% to 90% of 400 ma load at 500 khz f sw with 0.1 f feedback capacitor 0 1.0 0.5 ?2 0 2 4 6 8 14 10 12 v iso (v) i load (a) time (ms) 4.0 2.5 3.0 3.5 4.0 2.5 3.0 3.5 c out = 47f, l1 = 47h c out = 47f, l1 = 100h 90% load 10% load 10991-040 figure 40 . typical v iso load transien t response 3.3 v in put to 3.3 v out put at 10% to 90% of 250 ma load at 500 khz f sw 0 1.0 0.5 ?2 0 2 4 6 8 14 10 12 v iso (v) i load (a) time (ms) 4.0 2.5 3.0 3.5 4.0 2.5 3.0 3.5 c out = 47f, l1 = 47h c out = 47f, l1 = 100h 90% load 10% load 10991-041 figure 41 . typical v iso load transient response 3.3 v in put to 3.3 v out put at 10% to 90% of 250 ma load at 500 khz f sw with 0.1 f feedback ca pacitor 0 0.2 0.1 ?2 0 2 4 6 8 14 10 12 v iso (v) i load (a) time (ms) 18 12 14 16 18 12 14 16 c out = 47f, l1 = 47h c out = 47f, l1 = 100h 90% load 10% load 10991-042 figure 42 . typical v iso load transient response 5 v in put to 15 v out put at 10% to 90% of 100 ma load at 500 khz f sw
data sheet adum4470/adum4471/adum4472/adum4473/adum4474 rev. 0 | page 25 of 36 0 0.2 0.1 ?2 0 2 4 6 8 14 10 12 v iso (v) i load (a) time (ms) 18 12 14 16 18 12 14 16 c out = 47f, l1 = 47h c out = 47f, l1 = 100h 90% load 10% load 10991-043 figure 43 . typical v iso load transient response 5 v in put to 15 v out put at 10% to 90% of 100 ma load at 500 khz f sw with 0.1 f feedback capacitor 0 20 10 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 2.0 1.0 1.5 v iso (v) x1 (v) time (ms) 5.06 4.94 4.98 5.02 10991-044 figure 44 . typical v iso output ripple, 5 v in put to 5 v out put at 4 00 ma load at 500 khz f sw 0 20 10 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 2.0 1.0 1.5 v iso (v) x1 (v) time (ms) 3.36 3.24 3.28 3.32 10991-045 figure 45 . typical v iso outpu t ripple, 5 v in put to 3.3 v out put at 4 00 ma load at 500 khz f sw 0 20 10 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 2.0 1.0 1.5 v iso (v) x1 (v) time (ms) 3.36 3.24 3.28 3.32 10991-046 figure 46 . typical v iso output ripple, 3.3 v in put to 3.3 v out put at 250 ma load at 500 khz f sw 0 20 10 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 2.0 1.0 1.5 v iso (v) x1 (v) time (ms) 15.08 14.94 14.96 14.98 15.00 15.02 15.04 15.06 10991-047 figure 47 . typical v iso output ri pple, 5 v in put to 15 v out put at 100 ma load at 500 khz f sw
adum4470/adum4471/adum4472/adum4473/adum4474 data sheet rev. 0 | page 26 of 36 applications informa tion theory of operation the dc - to - dc converter section of the adum4 4 7 x uses a secondary side controller architecture with isolated pulse - width modulation (pwm) feedba ck . v dd1 power is supplied to an oscillating circuit that switches current to the primary of an external power trans - former using internal push - pull switches at the x1 and x2 pins. power transferred to the secondary side of the transformer is full - wave rec tified with external schottky diodes (d1 and d2), filtered with the l1 inductor and c out capacitor, and regulated to the isolated power supply voltage from 3.3 v to 15 v. t h e secondary (v iso ) side controller regulates the output by using a feedback voltage , v fb , from a resistor divider on the output and creating a pwm control signal that is sent to the primary (v dd1 ) side by a dedicated i coupler data channel labeled v fb . the primary side pwm converter varies the duty cycle of the x1 and x2 switches to modul ate the oscillator circuit and control the power being sent to the secondary side. this feedback allows for significantly higher power and efficiency. the adum4 4 7 x implement s under voltage lockout (uvlo) with hysteresis on the v dd a and v dd2 power input s . t his feature ensures that the converter does not go into oscillation due to noisy input power or slow power - on ramp rates. a minimum load current of 10 ma is recommended to ensure optimum load regulation. smaller loads can generate excess noise on the outpu t because of short or erratic pwm pulses. excess noise generated this way can cause regulation problems in some circumstances. application schemati cs the adum4 4 7 x ha ve th ree main application schematics ( s ee figure 48 to figure 50) . figure 48 has a center - tapped secondary and two schottky diodes providing full wave rectification for a single output, typically for power supplies of 3. 3 v, 5 v, 12 v, and 15 v. for single supplies when v iso = 3.3 v or v iso = 5 v, see the note in figure 48 about connecting together v reg , v dd2 , and v iso . figure 49 is a volt age doubling circuit that can be used for a single supply whose output exceeds 15 v, which is the largest supply that ca n be connected to the regulator input , pin v reg , of the part . with figure 49, t he output volta ge can be as high as 24 v and the v reg pin only about 12 v. when using the circuit shown in figure 49 , to ob tain an output voltage lower than 10 v (for exam ple , v dd1 = 3.3 v, v iso = 5 v ), connect v reg to v iso directly . figure 50 , which also uses a voltage doubling secondary circuit, show s an example of a coarsely regulated, positive power supply and an unregulated, negative power supply for outputs of approximately 5 v, 1 2 v, and 15 v. for any circuit in figure 48 , figure 49 , or figure 50, the isolated output voltage (v iso ) can be set u sing the voltage dividers, r1 and r2 ( with values of 1 k? to 100 k? ), in the applicatio n schematics using the following equation: r2 r2 r1 v v fb iso + = where v fb is the internal feedback voltage, which is approximately 1.25 v. v iso = v fb (r1 + r2)/r2 for v iso = 3.3v or 5v connect v reg , v dd2 , and v iso . adum4470/ adum4471/ adum4472/ adum4473/ adum4474 1 x1 20 v reg 2 gnd 1 19 gnd 2 3 nc 18 v dd2 4 x2 17 fb 5 i/oa 16 i/oa 6 i/ob 15 i/ob 7 i/oc 14 i/oc 8 i/od 13 i/od 9 v dda 12 oc 10 gnd 1 11 gnd 2 d1 t1 l1 47h c out 47f d2 v dd1 v dd1 v dd1 0.1f c in 0.1f +5v r1 r2 r oc n? v fb c fb v iso = +3.3v to +15v 10991-048 figure 48 . single power sup ply v iso = v fb (r1 + r2)/r2 for v iso = 15v or less, v reg can connect to v iso . adum4470/ adum4471/ adum4472/ adum4473/ adum4474 1 x1 20 v reg 2 gnd 1 19 gnd 2 3 nc 18 v dd2 4 x2 17 fb 5 i/oa 16 i/oa 6 i/ob 15 i/ob 7 i/oc 14 i/oc 8 i/od 13 i/od 9 v dda 12 oc 10 gnd 1 11 gnd 2 d1 d3 t1 l1 47h l2 47h c out1 47f c out2 47f d4 d2 v dd1 v dd1 v dd1 0.1f c in 0.1f +5v r2 r oc n? v fb v iso = +12v to +24v unregulated +6v to +12v r1 c fb 10991-049 figure 49 . doubling power supply v iso = v fb (r1 + r2)/r2 adum4470/ adum4471/ adum4472/ adum4473/ adum4474 1 x1 20 v reg 2 gnd 1 19 gnd 2 3 nc 18 v dd2 4 x2 17 fb 5 i/oa 16 i/oa 6 i/ob 15 i/ob 7 i/oc 14 i/oc 8 i/od 13 i/od 9 v dda 12 oc 10 gnd 1 11 gnd 2 d1 d3 t1 l1 47h l2 47h c out1 47f c out2 47f d4 d2 v dd1 v dd1 v dd1 0.1f c in 0.1f +5v r2 r oc n? v fb v iso = coarsely regulated +5v to +15v unregulated ?5v to ?15v r1 c fb 10991-050 figure 50 . positive and unregulated negative supply
data sheet adum4470/adum4471/adum4472/adum4473/adum4474 rev. 0 | page 27 of 36 transformer design transformers that have been designed for use in the circuits shown in figure 48, figure 49 , and figure 50 are listed in table 17. the design of a transformer for the adum4 4 7 x can differ from some is olated dc - to - dc converter designs that do not regulate the output voltage. the output voltage is regulated by a pwm controller in the adum4 7x that varies the duty cycle of the primary side switches in response to a secondary side feedback voltage, v fb , rec eived through an isolated digital channel. the internal controller has a limit of 40% maximum duty cycle. transformer turns ra tio to determine the transformer turns ratio, and taking into account the losses for the primary switches and the losses for the secondary diodes and inductors, the external transformer turns ratio for the adum4 4 7 x can be calculated by 2 ) ( + = d v v v n n min dd1 d iso p s (1) where: n s / n p is the primary to secondary turns ratio. v iso is the isolated output supply voltage. v d is the schottky diod e voltage drop (0.5 v maximum). v dd1 (min) is the minimum input supply voltage. d is the duty cycle = 0.30 for a 30% typical duty cycle, 40% is maximum, and a multiplier factor of 2 is used for the push - pull switching cycle. for example, using the circuit in figure 48 and the 5 v to 5 v reference design in table 17, with v dd1 (min) = 4.5 v, the turns ratio is n s /n p = 2. for a similar 3.3 v input to 3.3 v output, isolated single power sup ply , and with v dd1 (min) = 3.0 v, the turns ratio is also n s /n p = 2. therefore, the same transformer turns ratio n s /n p = 2 can be used for the three single power applications (5 v to 5 v, 5 v to 3.3 v, and 3.3 v to 3.3 v). in figure 49 , the circuit uses double windings and diode pairs to create a doubler circuit; therefore, half the output voltage, v iso /2, is used in the equation: 2 2 ) ( + = d v v v n n min dd1 d iso p s (2) n s / n p is the primary to secondary turns ratio. v iso /2 is used in the equatio n because the circuit uses two pairs of diodes creating a doubler circuit. v d is the schottky diode voltage drop (0.5 v maximum). v dd1 (min) is the minimum input supply voltage. d is duty cycle , which equals 0.30 for a 30% typical duty cycle, 40% is maximum , and a multiplier factor of 2 is used for the push - pull switching cycle. for example, using the circuit in figure 49 and the 5 v to 15 v reference design in table 17, with v dd1 (min) = 4. 5 v, the turns ratio is n s /n p = 3. in figure 50 , the circuit also uses double windings and diode pairs to create a doubler circuit; however, because a positive and negative output voltage is created, v iso is used i n the equation : 2 ) ( + = d v v v n n min dd1 d iso p s (3) where: n s /n p is the primary to secondary turns ratio. v iso is the isolated output supply voltage and is used in the equation because the circuit uses two pairs of diodes , creating a doubler circuit with a positive and negative output. v d is the schottky diode voltage drop (0.5 v maximum). v dd1 (min) is the minimum input supply voltage, and a multiplier factor of 2 is used for the push - pull switching cycle. d is the duty cycle; in this case, a higher duty cycle of d = 0.35 for a 35% typical duty cycle (40% is maximum) was used in the figure 50 circuit to reduce the maximum voltages seen by the diodes for a 15 v supply. for example, using the circuit in figure 50 and the +5 v to 15 v reference design in table 17 , with v dd1 (min) = 4.5 v, the turns ratio is n s /n p = 5. transformer et constant the next transformer design factor to consider is the et constant . this constant determines the minimum v s constant of the transformer over the operating temperature. et value s of 14 v s and 18 v s were selected for the adum4 4 7 x designs listed in table 17 using the following equation: 2 ) ( ) ( ) ( = min sw max dd1 f v min et (4) w here: v dd1 (max) is the maximum input supply voltage. f sw(min) is the minimum primary switching frequency = 300 khz in startup, and a multiplier factor of 2 is used for the push - pull switching cycle.
adum4470/adum4471/adum 4472/adum4473/adum4474 data sheet rev. 0 | page 28 of 36 transformer primary inductance and resistance another important characteristic of the transformer for designs with the adum447x is the primary inductance. transformers for the adum447x are recommended to have between 60 h to 100 h of inductance per primary winding. values of primary inductance in this range are needed for smooth operation of the adum447x pulse-by-pulse current-limit circuit, which can help protect against buildup of saturation currents in the transformer. if the inductance is specified for the total of both primary windings, for example, as 400 h, the inductance of one winding is ? of two equal windings, or 100 h. another important characteristic of the transformer for designs with the adum447x is primary resistance. primary resistance as low as is practical (less than 1 ) helps reduce losses and improves efficiency. the dc primary resistance can be measured and specified, and is shown for the transformers in table 17. transformer isolation voltage isolation voltage and isolation type should be determined for the requirements of the application and then specified. the transformers in table 17 have been specified for 2500 v rms for supplemental or basic isolation and for 1500 v rms functional isolation. other isolation levels and isolation voltages can be specified and requested from the manufacturers in table 17 or from other manufacturers. switching frequency the adum447x switching frequency can be adjusted from 200 khz to 1 mhz by changing the value of the r oc resistor shown in figure 48, figure 49, and figure 50. the value of the r oc resistor needed for the desired switching frequency can be determined from the switching frequency vs. the r oc resistance curve shown in figure 13. the output filter inductor value and output capacitor value for the adum447x application schematics have been designed to be stable over the switching frequency range from 500 khz to 1 mhz, when loaded from 10% to 90% of the maximum load. the adum447x also has an open-loop mode where the output voltage is not regulated and is dependent on the transformer turns ratio, n s /n p , and the conditions of the output, including output load current and the losses in the dc-to-dc converter circuit. this open-loop mode is selected when the oc pin is connected high to the v dd2 pin. in open-loop mode, the switching frequency is 318 khz. transient response the load transient response of the output voltage of the adum447x for 10% to 90% of the full load is shown in figure 36 to figure 43 for the application schematics in figure 48 to figure 50. the response shown is slow but stable and can have more output change than desired for some applications. the output voltage change with load transient has been reduced, and the output has been shown to remain stable by adding more inductance to the output circuits, as shown in the second v iso output waveform in figure 36 to figure 43. for additional improvement in transient response, add a 0.1 f ceramic capacitor (c fb ) in parallel with the high feed- back resistor. as shown in figure 36 to figure 43, this value helps reduce the overshoot and undershoot during load transients. table 17. transformer reference designs part no. manufacturer turns ratio, pri:sec et constant (v s min) total primary inductance (h) total primary resistance () isolation voltage (rms) isolation type reference cr7983-cl coilcraft 1ct:2ct 18 256 0.2 5000 reinforced figure 48 cr7984-cl coilcraft 1ct:3ct 18 256 0.2 5000 reinforced figure 49 cr7985-cl coilcraft 1ct:5ct 18 256 0.2 5000 reinforced figure 50 tgrad-560v8lf halo electronics 1ct:2ct 14 398 0.8 5 000 supplemental figure 48 tgrad-590v8lf halo electronics 1ct:3ct 14 398 0.8 5 000 supplemental figure 49
data sheet adum4470/adum4471/adum4472/adum4473/adum4474 rev. 0 | page 29 of 36 component selection power supply bypassing is required at the input and output supply pins. note that a low esr ceramic b ypass capacitor of 0.1 f is required on side 1 between pin 9 and pin 10 , and on side 2 between pin 1 8 and pin 1 9 , as close to the chip pads as possible. the power supply section of the adum4 4 7 x uses a high oscillator frequency to efficiently pass power th rough the external power transformer. bypass capacitors are required for several operat - ing frequencies. noise suppression requires a low inductance, high frequency capacitor; ripple suppression and proper regulation require a large value capacitor. to sup press noise and reduce ripple, large - valued ceramic capacitors of x5r or x7r dielectric type are recommended. the recommended capacitor value is 10 f for v dd1 and 47 f for v iso . these capacitors have a low esr and are available in moderate 1206 or 1210 s izes for voltages up to 10 v. for output voltages larger than 10 v, two 22 f ceramic capacitors can be used in parallel. see table 18 for suggested components. inductors must be selected based on the value and s upply current needed. most applications with switching frequencies between 500 khz and 1 mhz and load transients between 10% and 90% of full load are stable with the 47 h inductor value listed in table 18 . values as large as 200 h can be used for power supply applications with a switching frequency as low as 200 khz to help stabilize the output voltage or for improved load transient response (see figure 36 to figure 39 ). inductors in a small 1212 or 1210 size are listed in table 18 with a 47 h value and a 0.4 1 a current rating to handle the majority of applications below a 400 ma load, and with a 100 h value and a 0.34 a current rating to handle a load to 300 ma. schottky diodes are recommended for their low forward voltage to reduce losses and their high reverse voltage of up to 40 v to withstand the peak voltages available in the doubling circuit shown in figure 49 and figure 50 . table 18. suggested components part number manufacturer value grm32er71a476ke15l murata 47 f, 10 v, x7 r, 1210 grm32er71c226kea8l murata 22 f, 16 v, x7r, 1210 grm31cr71a106ka01l murata 10 f, 10 v, x7r, 1206 mbr0540t1 - d on semiconductor 0.5 a, 40 v, schottky, sod - 123 lqh3npn470mm0 murata 47 h, 0.41 a, 1212 me3220 - 104kl coilcraft 100 h, 0.34 a, 1210 lqh6ppn470m43 murata 47 h, 1.10 a, 2424 l qh6 pp n101m43 murata 100 h, 0.80 a, 2424 printed circuit boar d (pcb) layout note that the total lead length between the ends of the low esr capacitor and the v ddx and gnd x pins must not exceed 2 mm . see figure 51 for the recommended pcb layout. x1 gnd 1 nc x2 v ia /v oa v ib /v ob v ic /v oc v id /v od v dda gnd 1 v reg gnd 2 v dd2 fb v oa /v ia v ob /v ib v oc /v ic v od /v id oc gnd 2 10991-051 figure 51 . recommended pcb layout in applications involving high common - mode transients, ensure that board coupling across the isolation barrier is minimized. furth ermore, design the board layout such that any coupling that does occur equally affects all pins on a given component side. failure to ensure this can cause voltage differentials between pins, exceeding the absolute m aximum ratings specified in table 10 , thereby leading to latch - up and/or permanent damage. the adum4 4 7 x are power device s that dissipate about 1 w of power when fully loaded and running at maximum speed. because it is not possible to apply a heat sink to an isolation de vice, the devices primarily depend on heat dissipation into the pcb through the gnd x pins. if the devices are used at high ambient temperatures, take care to provide a thermal path from the gnd x pins to the pcb ground plane. the board layout shows enlarged pads for the gnd x pins (pin 2 and pin 10 on side 1 and pin 11 and pin 1 9 ) on side 2 ) . large diameter vias should be implemented from the pad to the ground planes and power planes to increase thermal conductivity and to reduce inductance. multiple vias in the thermal pads can significantly reduce temperatures inside the chip. the dimensions of the expanded pads are left to the discretion of the designer and the available board space.
adum4470/adum4471/adum4472/adum4473/adum4474 data sheet rev. 0 | page 30 of 36 thermal analysis the adum4 4 7x consist of two internal die attached to a split lead frame with two die attach paddles. for the purposes of thermal analysis, the die are treated as a thermal unit, with the highest junction temperature reflected in the ja from table 5 . the value of ja is based on measurements taken with the parts mounted on a jedec standard, 4 - layer board with fine width traces and still air. under normal operating conditions, the adum4 4 7x operate at a full load across the full temperature range without derating the output current. however, following the recom - mendations in the printed circuit board (pcb) layout section decreases thermal resistance to the pcb, allowing increased thermal mar gins in high ambient temperatures. the adum4 4 7x has an thermal shutdown circuit that shuts down the dc - to - dc converter and the outputs of the adum4 4 7x when a die tempe rature of about 160c is reached. when the die cools below about 140c, the adum4 4 7x dc - to - dc converter and outputs turn on again. propagation delay - related parameters propagation delay is a parameter that describes the time it takes a logic signal to pro pagate through a component (see figure 52 ). the propagation delay to a logic low output may differ from the propagation delay to a logic high output. input (v ix ) output (v ox ) t plh t phl 50% 50% 10991-052 figure 52 . propagation delay paramete rs p ulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the input signal timing is preserved. channel - to - channel matching refers to the maximum amount the propagation delay diff ers between channels within a single adum4 4 7x component. propagation delay skew refers to the maximum amount the propagation delay differs between multiple adum4 4 7x components operating under the same conditions. dc correctness and m agnetic field immuni ty positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. the decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. in t he absence of logic transitions at the input for more than 1 s, periodic sets of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. if the decoder receives no internal pulses of more than approximately 5 s, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see table 17 ) by the watchdog timer circuit. this situation should occur in the adum4 4 7x devices only during power - up and power - down operations. the limitation on the adum4 4 7x magnetic field immunity is set by the condition in which induced voltage in the transformer receiving coil is suffi ciently large to either falsely set or reset the d ecoder. the following analysis defines the conditions under which this can occur. the 3.3 v operating condition of the adum4 4 7x is examined because it represents the most susceptible mode of operation. the pulses at the transformer output have an amplitud e of >1.0 v. the decoder has a sensing threshold of about 0.5 v, thus estab - lishing a 0.5 v margin in which induced voltages can be tolerated. the voltage induced across the receiving coil is given by v = ( ? d /dt )? r n 2 ; n = 1, 2, , n where: is magnetic flux density (gauss). n is the number of turns in the receiving coil. r n is the radius of the n th turn in the receiving coil (cm). given the geometry of the receiving coil in the adum4 4 7x and an imposed require ment that the induced voltage be, at most, 50% of the 0.5 v margin at the decoder, a maximum allowable magnetic field is calculated as shown in figure 53. magnetic field frequency (hz) 100 maximum allowable magnetic flux density (kgauss) 0.001 1m 10 0.01 1k 10k 10m 0.1 1 100m 100k 10991-053 figure 53 . maximum allowable external m agnetic flux density for example, at a magnetic field frequency of 1 mhz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 v at the receiving coil. this is about 50% of the sensing threshold and does not cause a faulty output tr ansition. similarly, if such an event occurs during a transmitted pulse (and is of the worst - case polarity), it reduces the received pulse from >1.0 v to 0.75 v, which is still well above the 0.5 v sensing threshold of the decoder.
data sheet adum4470/adum4471/adum4472/adum4473/adum4474 rev. 0 | page 31 of 36 the preceding magnetic f lux density values correspond to specific current magnitudes at given distances from the adum4 4 7x transformers. figure 54 expresses these allowable current magnitudes as a function of frequency for selected dist ances. as shown in figure 54 , the adum4 4 7x are extremely immune and can be affected only by extremely large currents operated at a high fre - quency that is very close to the component. for the 1 mhz example, a 0 .5 ka current needs to be placed 5 mm away from the adum4 4 7x to affect component operation. magnetic field frequency (hz) maximum allowable current (ka) 1k 100 10 1 0.1 0.01 1k 10k 100m 100k 1m 10m distance = 5mm distance = 1m distance = 100mm 10991-054 figure 54 . maximum allowable current for various current - to- adum4 47x spacings in combinations of strong magnetic field and high frequenc y, any loops formed by pcb traces c an induce error voltages that are sufficiently large to trigger the thresholds of succeeding cir - cuitr y. t ake care in the layout of such traces to avoid this possibility. power consumption the v dda power supply input prov ides power to the i coupler data channels, as well as to the power converter. for this reason, the quiescent currents drawn by the data converter and the primary and secondary i/o channels cannot be determined separately. all of these quiescent power demand s have been combined into the i dda (q) current, as shown in figure 55 . the total i dd supply current is equal to the sum of the quiescent operating current; the dynamic current, i dda (d) , demanded by the i/o channel s; and any external i iso load. converter primary converter secondary feedback secondary data i/o 4-channel primary data i/o 4-channel i ddp (d) i iso (d) i iso i dda (q) i dda (d) 10991-055 figure 55 . power consumption within the adum4 47x dynamic i/o current is consumed only when operating a channel at speeds higher than the refresh rate of f r . the dynamic current of each channel is d etermined by its data rate. figure 24 and figure 28 show the current for a channel in the forward direction, meaning that the input is on the v dda and v dd2 side of the part . figure 25 and figure 29 show the current for a channel in the r everse direction, meaning that the input is on the v iso side of the part. figure 24, figure 25, figure 28 , or figure 29 assume a typical 15 pf output load. the following relationship allows the t otal i dd1 current to be i dd1 = ( i iso v iso ) /( e v dd1 ) + i chn ; n = 1 to 4 (5 ) where: i dd1 is the total supply input current. i iso is the current drawn by the secondary side external load. e is the power supply efficiency at the given output l oad from figure 17 or figure 23 at the v iso , v dda , and v dd2 condition of interest. i chn is the current drawn by a single channel dete rmined from figure 24, figure 25, figure 28 , or figure 29 , depending on channel direction. the maximum external load can be calculated by subtracting the dynamic output load from the maximum al lowable load. i iso (load) = i iso (max) ? i iso (d)n ; n = 1 to 4 ( 6 ) where: i iso (load) is the current available to supply an external secondary side load. i iso (max) is the maximum external secondary side load current available at v iso . i iso (d)n is th e dynamic load current drawn from v iso by an output or input channel, as shown for a single supply in figure 26 or figure 27 or for a double supply in figure 30 or figure 31. the preceding analysis assumes a 15 pf capacitive load on each data output. if the capacitive load is larger than 15 pf, the additional current must be included in the a nalysis of i dd1 and i iso (load) .
adum4470/adum4471/adum4472/adum4473/adum4474 data sheet rev. 0 | page 3 2 of 36 power considerations soft start mode and current - limit protection when the adum4 4 7x first receives power from v dda , it is in soft start mode, and the output voltage , v iso , is increased gradually while it is below the star t - up threshold. in soft start mode, the width of the pwm signal is increased gradually by the primary converter to limit the peak current during v iso power - up. when the output voltage is larger than the start - up threshold, the pwm signal can be transferre d from the secondary controller to the primary converter, and the dc - to - dc converter switch es from soft start mode to the normal pwm control mode. if a short circuit occurs, the push - pull converter shut s down for about 2 ms and then enter s soft start mod e. if , at the end of soft start, a short circuit still exists, the process is repeated, which is called hiccup mode. if the short circuit is cleared, the adum4 4 7x enters normal operation. the adum4 4 7x also ha ve a pulse - by - pulse current limit, which is acti ve in startup and normal operation and protects the primary switches, x1 and x2, from exceeding approximately 1.2 a peak . this current limit also protects the transformer windings. data channel power cycle the adum4 4 7x data input channels on the primary si de and the data input channels on the secondary side are protected from premature operation by uvlo circuitry. below the minimum operating voltage, the power converter holds its oscillator inactive, and all input channel drivers and refresh circuits are i dle. outputs are held in a low state. this is to prevent transmission of undefined states during power - up and power - down operations. during the application of power to v dda , the primary side circuitry is held idle until the uvlo preset voltage is reached. at that time, the data channels are initialized to their default low output state until they receive data pulses from the secondary side. the primary side input channels sample the input and send a pulse to the inactive secondary output. the secondary s ide converter begins to accept power from the primary, and the v iso voltage starts to rise. when the secondary side uvlo is reached, the secondary side outputs are initialized to their default low state until data, either a transition or a dc refresh pulse , is received from the corresponding primary side input. it can take up to 1 s after the secondary side is initialized for the state of the output to correlate with the primary side input. secondary side inputs sample their state and transmit it to the pr imary side. outputs are valid one propagation delay after the secondary side becomes active. because the rate of charge of the secondary side is dependent on the soft start cycle, loading conditions, input voltage, and output voltage level sel ected, take c are in the design to allow the converter to stabilize before valid data is required. when power is removed from v dda , the primary side converter and coupler shut down when the uvlo level is reached. the secondary side stops receiving power and starts to di scharge. the outputs on the secondary side hold the last state that they received from the primary until either the uvlo level is reached and the outputs are placed in their default low state, or the outputs detect a lack of activity from the inputs and th e outputs are set to their default value before the secondary power reaches uvlo.
data sheet adum4470/adum4471/adum4472/adum4473/adum4474 rev. 0 | page 33 of 36 insulation lifetime all insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. the rate of insu - lation degradation is d ependent on the characteristics of the voltage waveform applied across the insulation. analog devices , inc. , conducts an extensive set of evaluations to determine the lifetime of the insulation structure within the adum4 4 7x. accelerated life testing is per formed using voltage levels higher than the rated continuous working voltage. acceleration factors for several operating conditions are determined, allowing calculation of the time to failure at the working voltage of interest. the values shown in table 11 sum marize the peak voltages for 50 years of service life in several operating condi - tions. in many cases, the working voltage approved by agency testing is higher than the 50- year service life voltage. operation at working voltages that are higher than the service life voltage listed leads to premature insulation failure. the insulation lifetime of the adum4 4 7 x depends on the voltage waveform type imposed across the isolation barrier. the i coupler insulation stru cture degrades at different rates, depending on whether the waveform is dc , bipolar ac, or unipolar ac. figure 56 , figure 57 , and figure 58 illustrate these different isolation voltage waveforms. bipolar ac voltage is the most stringent environment. a 50 - year operating lifetime under the bipolar ac condition determines the analog devices recommended maximum working voltage. in the case of dc or unipolar ac voltage, the stress on the insulation is significantly lower. this allows operation at higher working voltages while still achieving a 50 - year service life. the working voltages listed in table 11 can be applied while maintaining the 50- yea r minimum lifetime, provided that the voltage conforms to either the dc or unipolar ac voltage cases. treat a ny cross - insulation voltage waveform that does not conform to figure 57 or figure 58 as a bipolar ac waveform, and limit its peak voltage to the 50 - year lifetime voltage value listed in table 11. 0v rated peak voltage 10991-056 figure 56 . bipolar ac waveform 0v rated peak voltage 10991-057 figure 57 . dc waveform 0v rated peak voltage notes 1. the voltage is shown sinusoidal for illustration purposes only. it is meant to represent any voltage waveform varying between 0 and some limiting value. the limiting value can be positive or negative, but the voltage cannot cross 0v. 10991-058 figure 58 . unipolar ac waveform
adum4470/adum4471/adum4472/adum4473/adum4474 data sheet rev. 0 | page 34 of 36 outline dimensions 1 1-15-20 1 1- a 20 1 1 10 1 se a ting plane coplanarit y 0.1 1.27 bsc 15.40 15.30 15.20 7.60 7.50 7.40 2.64 2.54 2.44 1.01 0.76 0.51 0.30 0.20 0.10 10.51 10.31 10. 1 1 0.46 0.36 2.44 2.24 pin 1 mark 1.93 ref 8 0 0.32 0.23 0.71 0.50 0.31 45 0.25 bsc gage plane compliant t o jedec s t andards ms-013 figure 59 . 20 - lead standard small outline package, with increased creepage [soic_i c ] wide body (ri - 20 - 1) dimension s shown in mil limeters ordering guide model 1 number of inputs, v dd1 side number of inputs, v iso side maximum data rate (mbps) temperature range package description package option ordering quantity adum4 4 70ariz 4 0 1 ? 40 c to +105 c 20- lead soic_ic wide body ri - 20- 1 adum4 4 70ariz - rl 4 0 1 ? 40 c to +105 c 20- lead soic_ic wide body 13 tape and reel ri - 20- 1 1,000 adum4 4 70criz 4 0 25 ? 40 c to +105 c 20- lead soic_ic wide body ri - 20- 1 adum4 4 70criz - rl 4 0 25 ? 40 c to +105 c 20- lead soic_ic wide body 13 tape and reel ri - 20- 1 1,000 adum4 4 71ariz 3 1 1 ? 40 c to +105 c 20 - lead soic_ic wide body ri - 20 - 1 adum4 4 71ariz - rl 3 1 1 ? 40 c to +105 c 20 - lead soic_ic wide body 13 tape and reel ri - 20 - 1 1,000 adum4 4 71criz 3 1 25 ? 40 c to +105 c 20- lead soic_ic wide body ri - 20- 1 a dum4 4 71criz - rl 3 1 25 ? 40 c to +105 c 20- lead soic_ic wide body 13 tape and reel ri - 20- 1 1,000 adum4 4 72ariz 2 2 1 ? 40 c to +105 c 20- lead soic_ic wide body ri - 20- 1 adum4 4 72ariz - rl 2 2 1 ? 40 c to +105 c 20- lead soic_ic wide body 13 tape and reel ri - 20- 1 1,000 adum4 4 72criz 2 2 25 ? 40 c to +105 c 20- lead soic_ic wide body ri - 20- 1 adum4 4 72criz - rl 2 2 25 ? 40 c to +105 c 20- lead soic_ic wide body 13 tape and reel ri - 20- 1 1,000 adum4 4 7 3 ariz 1 3 1 ? 40 c to +105 c 20- lead soic_ic wide body ri - 20- 1 adum4 4 7 3 ariz - rl 1 3 1 ? 40 c to +105 c 20- lead soic_ic wide body 13 tape and reel ri - 20- 1 1,000 adum4 4 7 3 criz 1 3 25 ? 40 c to +105 c 20- lead soic_ic wide body ri - 20- 1 adum4 4 7 3 criz - rl 1 3 25 ? 40 c to +105 c 20- lead soic_ic wide body 13 tape and reel ri - 20- 1 1, 000 adum4 4 7 4 ariz 0 4 1 ? 40 c to +105 c 20 - lead soic_ic wide body ri - 20 - 1 adum4 4 7 4 ariz - rl 0 4 1 ? 40 c to +105 c 20- lead soic_ic wide body 13 tape and reel ri - 20- 1 1,000 adum4 4 7 4 criz 0 4 25 ? 40 c to +105 c 20- lead soic_ic wide body ri - 20- 1 adum4 4 7 4 cri z - rl 0 4 25 ? 40 c to +105 c 20- lead soic_ic wide body 13 tape and reel ri - 20- 1 1,000 1 z = rohs compli ant part.
data sheet adum4470/adum4471/adum4472/adum4473/adum4474 rev. 0 | page 35 of 36 notes
adum4470/adum4471/adum 4472/adum4473/adum4474 data sheet rev. 0 | page 36 of 36 notes ?2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d10991-0-12/12(0)

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