low noise, matched dual monolithic transistor preliminary technical data MAT12 rev. pra information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2010 analog devices, inc. all rights reserved. features pin configuration low offset voltage (v os ): 50 v max very low voltage noise: 1nv/ hz max @ 100hz high gain (h fe ): 500 min at i c = 1ma 300 min at i c = 1a excellent log conformance: r be = 0.3 low offset voltage drift: 0.1 v/oc max high gain bandwidth product: 200mhz note: substrate is connected to ca se on to-78 package. substrate is normally connected to the most negative circuit potential, but can be floated general description the design of the MAT12 series of npn dual monolithic transistors is optimized for very low noise, low drift and low r be . exceptional characteristics of the MAT12 include offset voltage of 50 v max and high current gain (h fe ) which is maintained over a wide range of collector current. device performance is specified over the full temperature range as well as at 25 c. input protection diodes are provided across the emitter-b ase junctions to prevent degradation of the device characteristics due to reverse-biased emitter current. the s ubstrate is clamped to the most negative emitter by the parasitic isolation junction created by the protection di odes. this results in complete isolation between the transistors. the MAT12 is ideal for applications where low noise is a priority. the MAT12 can be used as an input stage to make an amplifier with noise voltage of less than 1.0 nv/ hz at 100 hz. other applications, such as log/antilog circuits, may use the excellent logging conformity of the MAT12. typical bulk resistance is only 0.3 to 0.4 . the MAT12 electrical characteristics approach those of an ideal transistor when operated over a collector current range of 1 a to 10 ma.
MAT12 preliminary technical data rev. pra | page 2 of 4 specifications electrical characteristics; v cb = 15v v cb = 15 v, i o = 10a, t a = 25c, unless otherwise specified. table 1. parameter symbol conditions min typ max unit current gain h fe i c = 1ma (note 1) -25oct a +85oc i c = 100a -25oct a +85oc i c = 10a -25oct a +85oc i c = 1a -25oct a +85oc 500 325 500 275 400 225 300 200 605 590 550 485 current gain match h fe 10a i c 1ma (note 2) 0.5 2 % noise voltage density e n i c = 1ma, v cb = 0 (note 3) f o = 10hz f o = 100hz f o = 1khz f o = 10khz 1.6 0.9 0.85 0.85 2 1 1 1 nv/hz nv/hz nv/hz nv/hz offset voltage v os v cb = 0, 1a i c 1ma -25oct a +85oc 10 50 70 v uv offset voltage change vs. v cb v os /v cb 0 v cb v max (note 4) 1a i c 1ma (note 5) 10 25 v offset voltage change vs. i c offset voltage drift breakdown voltage v os /i c v os /t bv ceo 1a i c 1ma (note 5), v cb =0 -25oct a +85oc -25oct a +85oc, v os trimmed to zero 40 5 0.08 0.03 25 0.3 0.3 v v/ oc v/ oc v gain-bandwidth product f t i c = 100ma, v ce = 10v 200 mhz collector-base leakage current i cbo v cb =v max -25oct a +85oc 25 2 200 pa na collector-collector leakage current i cc v cc =v max (notes 6,7) -25oct a +85oc 35 3 200 pa na collector-emitter leakage current i ces v be =0 (notes 6,7) -25oct a +85oc 35 3 200 pa na
preliminary technical data MAT12 rev. pra | page 3 of 4 input bias current i b i c = 10a -25oct a +85oc 25 45 na na input offset current i os i c = 10a -25oct a +85oc 0.6 8 na na input offset current drift i os /t i c =10a (note 6) -25oct a +85oc 40 90 pa/oc offset current change vs. v cb i os /v cb 0 v cb v max (note 4) 30 70 pa/v collector saturation voltage v ce(sat) i c = 1ma, i b =100a 0.05 0.1 v output capacitance c ob v cb =15v, i e =0 23 pf bulk resistance r be 10ai c 10ma (note6) 0.3 0.5 collector-collector capacitance c cc v cc = 0 35 pf notes: 1. current gain is guaranteed with collector-base voltage (v cb ) swept from 0 to v max at the indicated collector currents. 2. current gain match (h fe ) defined as: h fe = (100(i b )( h fe min )/i c ) 3. noise voltage density is guar anteed, but not 100% tested 4. this is the maximum change in v os as v cb is swept from 0v to 40v. 5. measured at i c =10a and guaranteed by design over the specified range of i c 6. guaranteed by design 7. i cc and i ces are verified by measurement of i cbo
MAT12 preliminary technical data rev. pra | page 4 of 4 absolute maximum ratings table 2. parameter rating collector-base voltage (bv cbo ) collector-emitter voltage (bv ceo ) collector-collector voltage (bv cc ) emitter-emitter voltage (bv ee ) 40 v 40v 40v 40v collector current (i c ) 20 ma emitter current (i e ) 20 ma storage temperature range h packages ?65c to +150c operating temperature range ?25c to +85c junction temperature range rm, cp packages ?65c to +150c lead temperature (soldering, 60 sec) 300c 1 differential input voltage is limited to 5 v or the supply vo ltage, whichever is less. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 3. thermal resistance package type ja jc unit to-78 (h) tbd tbd oc/w esd caution ?2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. pr09044-0-4/10(pra)
|
