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| 1/18 october 2000 hardware features s/t isdn interface n supports osi level 1 in confor- mance with uit-t i.430 for basic access at s and t interfaces (etsi 300012/ansi t1.605) n line interface transformer direct drive n full-duplex transmission at 192kbps on separate transmit and receive twisted pairs using alternate mark inversion (ami) line coding n 2 b channels at 64kbps each plus 1 d channel at 16kbps n all i.430 wiring configurations supported including passive bus for te's distributed point to point and point to multipoint n multiframe support n analog part: included with adaptive detection threshold and equalizer usb interface n usb 1.0 specification full compli- ance, 1.1 specification compati- bility (1.1 power management com- pliance), 12 mbps full speed n on-chip usb transceiver with digital pll n 6 isochronous endpoints for b1, b2, d channels data.interrupt endpoint for i430 n isdn protocol and data.control endpoint for usb standard plus vendor specific request n communication device class and vendor requests n bus or self powered application (pin programmable) n onnow power management (d0,d2,d3) suspend mode compliance n pin programmable high/low power usb device registration, wake-up capability, usb device identification general C usb hot plug and play interface. C control access and interrupt handling provided through the usb interface. C all fifos and fifos management needed in- cluded for usb/isdn data processing. C internal pll to generate the usb 48mhz clock from a 15.36mhz crystal. C internal regulator for 3.3v generation from usb bus 5v. C 48 pin tqfp package. C 0.35 micron hcmos 6 process. description ST5481 combines isdn link access and an usb interface to allow a very simple usb/isdn modem design with all isdn protocols and upper applications processed into the host pc. tqfp48 ordering number: ST5481 tqf7 ST5481 product preview l.o.u.i.s - lo w cost u sb i sdn s olution this is advance information on a new product now in development or undergoing evaluation. details are subject to change without notice.
ST5481 2/18 1 - general purpose the ST5481 is a single chip isdn -bri with usb interface low cost controller. the purpose is a low cost isdn modem for applications like internet acces and fax capabilities when the pc is on (full operating mode). the bonus is to offer an easy and lowcost access to internet at a rate of 128kbits/sec. easy access due to plug and play features via usb bus and lowcost due to host processing concept and remote powering via usb bus features. 2 - main functions the device controls the s0 isdn basic rate access (itu normalization i430) and manages the b1, b2, d channels through the usb bus. b1, b2, d channels data flow is regulated through fifo memories of respectively 32, 32, 16 bytes in each direction. on d, b1, b2 channels, all upper protocols than basic hdlc framing protocol are host processed from upper-datalink protocol (i440 normalization), network protocol up to applications drivers. link activation, deactivation protocols (i430) is managed by the device. but the full handling of the command and indicate primitives is done by the host processor accessing to dedicated registers. call setup signalling frames through d channel are managed by the host processor. internal regulators can be enabled to feed the device (and external devices) via the gndbus, vbus usb powering lines. they convert the usb 5 volts to 3.3 volts. the device respects the usb release 1.0 power management recommendations. when entered in suspend mode on usb side the device drop into a low power mode. an internal oscillator and a pll provide from an external 15.36mhz crystal a 48mhz clock for usb data rate recovering and 15.36mhz clock for s interface. the device offers one operating mode called closed mode plus several test modes. in closed mode the device presents the usb interface, the s interface and 8 gpio pins. 3 - pin-out figure 1 : pin-out synoptic 10987654321 12 11 48 47 46 45 44 43 42 41 40 39 38 37 27 28 29 30 31 32 33 34 35 36 25 26 13 14 15 16 17 18 19 20 21 22 23 24 mode3 mode2 mode1 mod0 rpsm gnda vrega vbus vregd1 gndbus dp dm dr_test5 fs_test4 clk_test3 id3_test2 id2_test1 id1_test14 id0_test15 nreset vregd2 gndd2 cfg0/test0 gpio7 gpio6 gpio5 gpio4 gndd1 gpio3 gpio2 gpio1 gpio0 xtalin xtalout fltpll lip lin iref lon lop test13 test12 ncs_test11 sdi_test10 cfg1_test9 sdo_test8 sck_test7 ST5481 dx_test6 ST5481 3/18 3.1 - pin list pin name type function 1 dm i/o negative usb differential data line 2 dp i/o positive usb differential data line 3 gndbus i usb remote ground 4 vregd1 i/o digital input/ output regulated supply, is an input when rpsm is tied to a logic zero value 5 vbus i usb remote positive supply 5 volts. 6 vrega i/o 3.3v input/ output analog regulated supply, is an input when rpsm is tied to a logic zero value 7 gnda i analog ground 8 rpsm i remote power supply mode: when tied to a logic zero value the device is self powered 9 mode0 i static configuration pin. used for working modes and test modes programming 10 mode1 i static configuration pin. used for working modes and test modes programming 11 mode2 i static configuration pin. used for working modes and test modes programming 12 mode3 i static configuration pin. used for working modes and test modes programming 13 lip in analog receive ami signal differential positive inputs from the s line 14 lin in analog receive ami signal differential negative input from the s line 15 iref in analog external current reference (connected to an external resistor) 16 lon out analog transmit ami signal differential negative output to the s line 17 lop out analog transmit ami signal differential positive output to the s line 18 test13 out analog analog test pin: aoptest1 19 test12 out analog analog test pin: aoptest2 20 test11 i/o test pin 21 test10 i/o test pin 22 test9 i/o test pin 23 test8 i/o test pin 24 test7 i/o test pin 25 test6 i/o test pin 26 test5 i/o test pin 27 test4 i/o test pin 28 test3 i/o test pin 29 id3_test2 i/o either id product bit 2 for usb descriptor either test pin 30 id2_test1 i/o either id product bit 3 for usb descriptor either test pin 31 id1_test14 i either id product bit 1 for usb descriptor either test pin 32 id0_test15 i either id product bit 0 for usb descriptor either test pin 33 nreset i initialisation input pin, zero active. 34 vregd2 i digital input supply, must be connected to vregd1 ST5481 4/18 3.2 - pll an internal oscillator provides a 15.36mhz clock for s interface from an external 15.36mhz crystal. from this clock, the analog block pll provides a 48mhz clock for usb data rate recovering. 35 gndd2 i digital ground 36 cfg0_test0 i/o cfg0 input for configuration when closed or open mode else test9 37 fltpll in analog used to adjust the internal pll filter 38 xtalout o tied to 15.36mhz external crystal 39 xtalin i tied to 15.36mhz external crystal 40 gpio0 i/o general purpose input-output pin 2ma 41 gpio1 i/o general purpose input-output pin 2ma 42 gpio2 i/o general purpose input-output pin 2ma 43 gpio3 i/o general purpose input-output pin 2ma 44 gndd1 i digital ground 45 gpio4 i/o general purpose input-output pin 4ma 46 gpio5 i/o general purpose input-output pin 4ma 47 gpio6 i/o general purpose input-output pin 4ma 48 gpio7 i/o general purpose input-output pin 4ma pin name type function ST5481 5/18 4 - synoptic figure 2 : global synoptic i430 macrocell mclk stop_osc s0 interface txck_o iref vref nreset nint den dreq nlsd sdo sdi sck ncs rxck_o txfs_o rxfs_o txdata rxdata b1_w b2_w d_w test vref-gen channel b1, b2, d fifos for rom descriptor access and controller endpoint 1 microwire interface controller endpoint 0 test interface ck48 usb macrocell usb driver ck12 control_data_in(7-0) control_data_out(7-0) test2-0 usb bus 4 power management and regulators 8 power pins rpsm mode(3-0) te s t p i ns 15.36mhz fltpll pll 15.36 48mhz 4 s0 ck48 isochonous endpoints 256 bytes framing ST5481 6/18 5 - isdn access the device is directly connected to the isdn line at s0 interface point. 4 pins are dedicated to this access: lip, lin: receive ami differential signals inputs connected to the appropriate transformer lop, lon: transmit ami differential signals outputs connected to the appropriate transformer. the s interface access sub-function is clock- feeded by a 15.36mhz clock signal from the on-chip oscillator. i431 recommendation protocols are fully imple- mented. the activation / deactivation command manage- ment is done by the device. 5.1 - isdn s interface synoptic see figure 3. 6 - usb access the device is directly connected to the usb bus. 4 pins are dedicated to this access: dp, dm for data exchange. vbus, gndbus as power lines. the data transfer rate is 12 mbits. the clock is extracted from the differential lines dp, dm by a digital pll from a 48mhz internal clock. this 48mhz clock is created from the 15.36mhz clock. the usb protocol is fully implemented following the 1.0 usb specification. 6.1 - usb normalization this specification refers to usb normalization documents: C universal serial bus specification revision 1.0 C universal serial bus common class specifica- tion revision 1.0 C ST5481 belongs to the vendor specific device class and to a vendor specific subclass defined as isdn modem device subclass. it presents one interface belonging to the vendor specific interface class and a vendor specific interface subclass defined as isdn soft modem interface subclass. it satisfies to a vendor specific control protocol called isdn soft modem protocol. figure 3 : s-interface block diagram line signal rx slicers rxnum control txnum - tx multiframe control - d channel monitoring - loopbacks - frame construction - ami code generation detector - c/i control - activation state machine - master clocks generation - d & e channel processing - auto threshold controller - auto equalizer controller - digital pll, line synchronization - ami decoder - frame synchronization & polarity check - signal id - multiframe control. pre filter & equalizer 2x6 bits dacs line driver ST5481 7/18 7 - power management the device can be supplied by the usb bus power lines vbus (5 volts) and gndbus (ground). this is enabled when rpsm (remote power supply mode) is at logic one. then on-chip regulators bring 3.3 volts to internal analog and digital blocks. when rpsm is high, a supply is brought to external devices through pins gndd1, vregd1, gndd2, vregd2, gnda, vrega. the power budgeting is done by the host when initializing the pipe: the needed information (maximum power consumption) is adjusted through pins cfg0, cfg1 and as well as rpsm for remote wake up ability information. the following mechanism is used to do "a get description device". figure 4 : bus-powered mode (rpsm=1) st 5481 vbus rpsm gndbus vregd1 gndd1 vregd2 gndd2 vrega gnda from to other to other 8 5 3 4 44 34 35 6 7 digital analog device device usb bus figure 5 : self powered mode (rpsm=0) st 5481 vbus rpsm gndbus vregd1 gndd1 vregd2 gndd2 vrega gnda from 8 5 3 4 44 34 35 6 7 from 3.3v externally regulated supplies usb bus ST5481 8/18 the host gets back the configuration of the device either a low power device, either a high power device (max power parameter higher than 100ma). being a high power device allows to set on a wake up ability because looking for a line signal detection consume more than 500ua allowed for a low power device when in a suspend state. to adjust the maximum power consumption parameter into the configuration descriptor, the logical values present on pins cfg0, cfg1, rpsm are used (see table 1). at power on, the digital regulator is immediately on and after 100 m s the analog regulator is authorized to feed the internal oscillator. C initialization and clocks management. C a hardware pin reset is done through pin nreset (active low). C a delay of 4.5ms is introduced before distribut- ing the clocks to the internal functions. C a usb hardware reset is done through dp, dm pins. this reset affects the usb inter- face, resetting the usb core state machines. it does not affect the application (s interface, reg- isters, fifos). a usb software reset is done through usb bmrequest set_default. it brings the s interface, application registers, application state machines and fifos pointers to default state. when the device goes out of suspend_clock state, a delay of 4.5ms is introduced before distributing the clocks to the internal functions. when the device enters into a suspend mode due to inactivity on usb bus, the oscillator is stopped in order to save power except if fconf(3) is equal to 1. table 1 : maximum power current and wake up ability coding max power current high/low power wake up ability cfg1 cfg0 rpsm bm attributes rom add 27 max power rom add 28 100 ma lo no 0 0 1 80 32 150 ma hi no 0 1 1 80 96 150 ma hi yes 1 0 1 a0 96 250 ma hi yes 1 1 1 a0 f9 100 ma lo no 0 0 0 c0 32 150 ma hi no 0 1 0 c0 96 150 ma hi yes 1 0 0 e0 96 250 ma hi yes 1 1 0 e0 f9 ST5481 9/18 8 - device states the device complies with usb rev 1.1 power management requirements. it complies with i430 power management requirements. due to inactivity on the usb bus for more than 3 ms, the device may enter into the suspend mode even if reset signalling is not done yet. the ST5481 recovers activity within the 15ms of the resume signalling issued by the host or hub. if wake up is enabled and occurs, the ST5481 recovers activity within the 15ms when it initiates the resume (k state) and about the same time the host or hub initiates a reset (seo for 10 ms). wake up ability concerns wake up of the usb bus (resume event when the bus is in a suspend state) from the s line through a line signal detection done by the s interface. interface s states and relationship with device versus usb states. m1: quiet mode (initial mode if cfg1 = 0). it means that s interface cannot be activated neither by the host nor by a detection of signal on line. this signal detection is disabled. the 15mhz oscillator is not addressed to macro-s m2: active mode. when the device is in s6,s7,s8,s9 states from usb point of view, the s interface may be in this state, then it can be deactivated by a pdn primitive (from host) or a hardware power down which is generated by a suspend event on usb bus m3: inactive mode (initial mode if cfg1 = 1). the line signal detection is enabled. then it can be activated (go to state active) by a line signal detection. when usb is suspended, the s interface will really be in the active mode once a resume signalling has been done on usb bus after the nlsd signal became active. when usb is configured, a transition from this mode to active mode is obtained with a pup primitive (from host). figure 6 : s interface states - cfg1=0 pon reset / usb request/ pin reset m3 m2 stt(5)=0 stt(5)=1 pdn or pdwn=1 pup or nlsd=0 stt(5)=1 m1 off s line activation active inactive s line activation possible not possible ST5481 10/18 if pin cfg1 is 1, when reset (pon,usb,pin) is active the initial state is inactive. 9 - endpoints configuration and dedication these endpoints are organized as one interface (interface 0), one configuration (configuration 1). the interface being composed of four alternate settings. hereafter in the document rx data direction is from s line to pc and is considered as in by usb protocol. the endpoints are: C 4 isochronous endpoints for b1 and b2 channels (fifo 32 bytes in each direction) ? ep3 input endpoint for b1 channel in(rx) on s line - associated to in(rx) fifo 32 bytes ? ep2 output endpoint for b1 channel out(tx) on s line - associated to out(tx) fifo 32 bytes ? ep5 input endpoint for b2 channel in(rx) on s line - associated to in(rx) fifo 32 bytes ? ep4 output endpoint for b2 channel out(tx) on s line - associated to out(tx) fifo 32 bytes C 2 isochronous endpoints for d channels (fifo 16 bytes in each direction) ? ep7 input endpoint for d channel in(rx) on s line - associated to in(rx) fifo 16 bytes ? ep6 output endpoint for d channel out(tx) on s line - associated to out(tx) fifo 16 bytes C 1 control endpoint means management of usb standards, communication device class (cdc) standards (unused), and vendor requests (s in- terface application dedicated): ? ep0 - internal configuration and control registers - d, b1, b2 channels transmit commands - ci primitives to be transmitted C 1 interrupt endpoint used for vendor interrupts ? ep1 - channels reception or transmission indications - ci primitives in receive direction - d, b1, b2 channel reception indications - s line status - gpio input changes the alternate settings are: ? alternate setting 0: ep0, ep1. - initialisation configuration ? alternate setting 1: ep0, ep1, ep2, ep3, p6, ep7 - connection 64kbits through b1 channel ? alternate setting 2: ep0, ep1, ep4, ep5, ep6, ep7 - connection 64kbits through b2 channel ? alternate setting 3: ep0, ep1, ep2, ep3, ep4, ep5, ep6, ep7 - connection 128kbps (144kbits/sec) through b1 + b2 + (data into d) channels figure 7 : s interface states - cfg1=1 off pon reset / usb request/ pin reset m3 m2 stt(5)=0 stt(5)=1 pdn or pdwn=1 pup or nlsd=0 stt(5)=1 m1 off s line activation not possible active inactive s line activation possible ST5481 11/18 usb descriptors during the usb request get descriptor, the device returns these values from an internal 256 byte rom. notes 1. this word represents the hardware-software association. the value is programmable through 4 of the 16 bits. the lower b its values are defined by pins id3 to id0. 2. this word represents the silicon hardware. the lower 8-bit value is defined at metal layer. the other 8 bits are written int o the rom at diffusion layer. note 1. theses words are defined by a transcoding of the pins cfg0, cfg1, rpsm : see power management section for coding of thes e pins. table 2 : device descriptor rom addr offset field size value description 08 0 blengh 1 12h size of this descriptor in bytes 09 1 bdescriptortype 1 01h device descriptor type 0a 2 bcdusb 2 0101h usb spec release number 1.1 0c 4 bdeviceclass 1 ffh vendor specific class code 0d 5 bdevicesubclass 1 01h vendor specific isdn modem subclass 0e 6 bdeviceprotocol 1 01h vendor specific isdn soft modem control protocol 0f 7 bmaxpacketsize0 1 08h max packet size for ep0 10 8 idvendor 2 0483h st id vendor 12 10 idproduct 2 481xh application id product 1 14 12 bcddevice 2 01xxh device release 2 16 14 imanufacturer 1 00h no specific manufacturer registred 17 15 iproduct 1 01h product id string descriptor index 1 18 16 iserialnumber 1 00h no specific serial number registred 19 17 bnumconfigurations 1 01h number of possible configurations table 3 : interface 0 as 0 descriptor rom addr offset field size value description 20 0 blengh 1 09h size of this descriptor in bytes 21 1 bdescriptortype 1 02h configuration descriptor type 22 2 wtotallengh 2 00cfh total length of data byte returned for this configuration 24 4 bnuminterface 1 01h number of interfaces supported by this configuration 25 5 bconfigurationvalue 1 01h value used to select this conf. 26 6 iconfiguration 1 00h no specific string descriptor for this configuration 27 7 bmattributes 1 xxh self powered and remote wake-up abilities programmable 1 28 8 maxpower 1 xxh max consumption programmable 1 ST5481 12/18 10 - electrical specifications unless otherwise stated, electrical characteristics are specified over the operating range. typical values are given for vbus = +5v, vrega = 3.3v, vregd1 = vregd2 = 3.3v, tamb = 25 c 10.1 - absolute maximum rating notes gnda = gndd1 = gndd2 = gndbus = 0v warning : operation beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at the se extremes. 1. in remote power supply mode (rpsm=0) 2. for the isdn s side access lop,lon,lip,lin pins the voltage level can temporary exceed the maximum rating due to the phone line conditions. to prevent any damage to the circuit, an external protection circuit must be implemented according to the appl ication schematics. 10.2 - nominal dc characteristics (ta = 0 to 70 c unless otherwise specified) note 1. vregd2 is always an analog power input, to be connected to vregd1 table 4 : absolute maximum ratings symbol parameter value unit vbus 5v power supply voltage 5.5v v vregd1 3.3v power supply voltage 1 -0.3v to 3.6v v vregd2 3.3v power supply voltage 1 -0.3v to 3.6v v vrega 3.3v power supply voltage 1 -0.3v to 3.6v v v ia analog input voltage 2 -0.3 to v rega + 0.3v v v id digital input voltage -0.3 to v regdx + 0.3v v v id digital input voltage on rpsm -0.5 to vbus + 0.3v v t oper operating temperature 0, +70 c t stg storage temperature -55, +125 c c table 5 : nominal dc characteristics symbol parameter minimum typical maximum unit vbus supply voltage 4 5 5.25 v ivdd supply current (rpsm=1) tbd tbd ma ivdds supply current in suspended mode (rpsm=1) tbd ma vrega analog regulated output power supply (rpsm=1) analog regulated input power supply (rpsm=0) 3.3-5% 3.3 3.3+5% v vregd1 digital regulated output power supply (rpsm=1) digital regulated input power supply (rpsm=0) 3.3-5% 3.3 3.3+5% v vregd2 digital regulated input power supply 1 3.3-5% 3.3 3.3+5% v i vrega analog regulated output current (rpsm=1) analog regulated input current (rpsm=0) tbd 40 ma i vregd1 digital regulated output current (rpsm=1) digital regulated input current (rpsm=0) tbd 40 ma i vregd2 digital regulated input current 1 tbd ma p dlp low power mode (suspended mode) tbd mw p d operating power tbd mw ST5481 13/18 a 2.2 m f decoupling polarized capacitor (tantal or chemical) is necessary as between vrega and gnda. a 1 m f decoupling polarized capacitor (tantal or chemical) is necessary as between vregd1 and gndd1. a 1 m f decoupling polarized capacitor (tantal or chemical) is necessary as between vregd2 and gndd2. note a 10ms time constant will be used (ex: 470 nf, 20 w ) to generate an adequate pulse on nreset pin. table 6 : digital pins (except gpio4 to gpio7,xtalin, xtalout, rpsm, nr eset) symbol parameter minimum typical maximum unit v il low level input voltage 0.2v regd1 v v ih high level input voltage 0.8v regd1 v v ol low level input voltage (iload = 2ma) 0.4 v v oh high level output voltage (iload = -2ma) 0.85v regd1 v i leak input leakage current 1 ua i ol low level input current (0 ST5481 16/18 11.2 - application schematic figure 9 : schematic u3 dalc208sc6 36 35 34 33 32 31 30 29 28 27 26 25 dx/test6 dr/test5 fs/test4 clk/test3 id2/test2 id3/test1 id1/test14 id0/test15 nreset vregd2 gndd2 cfg0/test0 13 14 15 16 17 18 19 20 21 22 23 24 gpio7 lip lin iref lon lop test12 test13 ncs/test11 sdi/test10 cfg1/test9 sd0/test8 sck/test7 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 mode3 mode2 mode1 mode0 rpsm gnda vrega vbus vregd1 gndbus dp dm u1 ST5481 gpio6 gpio5 gpio4 gndd1 gpio3 gpio2 gpio1 gpio0 xtalin xtalout fltpll c1 47pf r7 c2 33pf c3 33pf y1 15.36mhz c4 100nf r2 220k w vcc r1 d1 gnd.d1/d2 gnda c8 100nf c10 2.2 m f 6 5 u2 usbuf01w6 r19 1 2 3 4 16 15 14 13 2:1 2fold-choke 2x5mh t60407 2:1 2fold-choke 2x5mh 5 6 7 8 12 11 10 9 t1 r20 1 2 3 4 5 6 7 8 rj45 r21 d2 led led 510 w 510 w 1k w c9 4.7 m f r15 1m w + 4.7 w 4.7 w r23 10k w 1% c11 100nf r22 10k w 1% l526x010 3 2 1 i/02 ref2 i/01 4 5 6 i/03 ref1 i/04 12 d3 smltv3/3 vcc + r17 120k w r18 4.7m w c7 10 m f + 4 d+out vcc d-out 1 2 3 d+in gnd d-in vcc r16 0 w d+ d- l1 4.7 m h 1 2 3 4 usb-b 5 6 j1 j2 ST5481 17/18 tqfp48 package mechanical data figure 10 : 48 pins - full plastic dimension millimeter inch minimum typical maximum minimum typical maximum a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.17 0.22 0.27 0.007 0.009 0.011 c 0.09 0.20 0.004 0.008 d 9.00 0.354 d1 7.00 0.276 d3 5.50 0.216 e 0.50 0.0197 e 9.00 0.354 e1 7.00 0.276 e3 5.50 0.216 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 k 0 (minimum), 7 (maximum) 48 37 d3 e 13 24 1 12 25 36 c a1 a2 a d1 d e3 e1 e l k l1 0,25 mm .010 inch gage plane 0,10 mm .004 inch seating plane b 18/18 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2000 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com ST5481.ref |
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