1 of 2:8 differential clock/data fanout buffe r fastedge? series cy2pp318 cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-07501 rev.*e revised july 27, 2004 features ? eight ecl/pecl differential outputs ? two ecl/pecl differential inputs ? hot-swappable/-insertable ? 50 ps output-to-output skew ? 150 ps device-to-device skew ? 500 ps propagation delay (typical) ? 1.5 ghz operation (2.2 ghz max. toggle frequency) ? 1.2 ps rms period jitter (typ.) ? pecl mode supply range: v cc = 2.5v 5% to 3.3v5% with v ee = 0v ? ecl mode supply range: v e e = ?2.5v 5% to ?3.3v5% with v cc = 0v ? industrial temperature range: ?40c to 85c ? 28-pin plcc package ? temperature compensation like 100k ecl functional description the cy2pp318 is a low-skew, low propagation delay 1-to-8 differential fanout buffer targeted to meet the requirements of high-performance clock and data distribution applications. the device is implemented on sige technology and has a fully differential internal architecture that is optimized to achieve low signal skews at operating frequencies of up to 1.5 ghz. the device features two differential input paths that are multi- plexed internally. this mux is controlled by the clk_sel pin. the cy2pp318 may function not only as a differential clock buffer but also as a signal-level translator and fanout on ecl/pecl signal to eight ecl/pecl differential loads. an ex- ternal bias pin, vbb, is provided for this purpose. in such an application, the vbb pin should be connected to either one of the clka# or clkb# inputs and bypassed to ground via a 0.01- f capacitor. since the cy2pp318 introduces negligible jitter to the timing budget, it is the ideal choice for distributing high frequency, high precision clocks across back-planes and boards in communication system s. furthermore, advanced circuit design schemes, such as internal temperature compensation, ensure that the cy2pp318 delivers consistent performance over various platforms. block diagram pin configuration q0 q0# q1 q1# q2 q2# q3 q3# q4 q4# q5 q5# q6 q6# q7 q7# vbb vee vee vcc clka clka# clkb clkb# clk_sel vee vcc q3 q4 q3# vcc q4# q5 q5# q0 q1 q0# vcc q1# q2 q2# nc clkb# q7# vcc q7 q6# q6 vee clka clk_sel vcc clka# vbb clkb 18 17 16 15 14 13 12 19 20 21 22 23 24 25 11 10 9 8 7 6 5 26 27 28 1 2 3 4 cy2pp318 top view
fastedge? series cy2pp318 document #: 38-07501 rev.*e page 2 of 8 governing agencies the following agencies provide specifications that apply to the cy2pp318. the agency name and relevant specification is listed below in ta ble 2 . pin definitions [1, 2, 3] pin name i/o type description 3 vbb o bias reference voltage output 26 vee ?pwr power negative supply 1, 8, 15, 22 vcc +pwr power positive supply 28 clka i, pd ecl/pecl ecl/pecl differential input clocks 2 clka# i, pd/pu ecl/pecl ecl/pecl differential input clocks 4 clkb i, pd ecl/pecl ecl/pecl differential input clocks 5 clkb# i, pd/pu ecl/pecl ecl/pecl differential input clocks 27 clk_sel i, pd ecl/pecl ecl/pecl input clock select 6nc no connect 25,23,20,18,16,13,11,9 q(0:7) o ecl/pecl ecl/pecl differential output clocks 24,21,19,17,14,12,10,7 q(0;7)# o ecl/pecl ecl/pecl differential output clocks table 1. control operation clk_sel 0 clka, clka# input pair is active (d efault condition with no connection to pin) clka can be driven with ecl- or pecl-compatible signals with respective power configurations 1 clkb, clkb# input pair is active. clkb can be driven with ecl- or pecl-compatible signals with respective power configurations table 2. agency name specification jedec jesd 020b (msl) jesd 51 (theta ja) jesd 8?2 (ecl) jesd 65?b (skew,jitter) mil-spec 883e method 1012.1 (thermal theta jc) notes: 1. in the i/o column, the following notation is used: i for input, o for output, pd for pull-down, pu for pull-up, and pwr for p ower 2. in ecl mode (negative power supply mode), v ee is either ?3.3v or ?2.5v and v cc is connected to gnd (0v). in pecl mode (positive power supply mode), v ee is connected to gnd (0v) and v cc is either +3.3v or +2.5v. in both modes, the input and ou tput levels are referenced to the most positive supply (v cc ) and are between v cc and v ee . 3. v bb is available for use for single-ended bias mode for |3.3v| supplies (not |2.5v|).
fastedge? series cy2pp318 document #: 38-07501 rev.*e page 3 of 8 absolute maximum ratings parameter description condition min. max. unit v cc positive supply voltage non-functional ?0.3 4.6 v v ee negative supply voltage non-functional -4.6 0.3 v t s temperature, storage non-functional ?65 +150 c t j temperature, junction non-functional 150 c esd h esd protection human body model 2000 v m sl moisture sensitivity level 3 n.a. gate count total number of used gates assembled die 28 gates multiple supplies: the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supp ly sequencing is not required. operating conditions parameter description condition min. max. unit i bb output reference current relative to v bb |200| ua lu i latch up immunity functional, typical 100 ma t a temperature, operating am bient functional ?40 +85 c ? jc dissipation, junction to case functional 39 [4] c/w ? ja dissipation, junction to ambient functional 60 [4] c/w i ee maximum quiescent supply current v ee pin 100 [5] ma c in input pin capacitance 3pf l in pin inductance 1nh v in input voltage relative to v cc [6] ?0.3 v cc + 0.3 v v tt output termination voltage relative to v cc [6] v cc ? 2 v v out output voltage relative to v cc [6] ?0.3 v cc + 0.3 v i in input current [7] v in = v il , or v in = v ih l150l ua pecl dc electrical specifications parameter description c ondition min. max. unit v cc operating voltage 2.5v 5%, v ee = 0.0v 3.3v 5%, v ee = 0.0v 2.375 3.135 2.625 3.465 v v v cmr differential cross point voltage [8] differential operation 1.2 v cc v v oh output high voltage i oh = ?30 ma [9] v cc ? 1.25 v cc ? 0.7 v v ol output low voltage v cc = 3.3v 5% v cc = 2.5v 5% i ol = ?5 ma [9] v cc ? 1.995 v cc ?1.995 v cc ? 1.5 v cc ? 1.3 v v v ih input voltage, high single-ended operation v cc ? 1.165 v cc ? 0.880 [10] v v il input voltage, low single-ended operation v cc ? 1.945 [10] v cc ? 1.625 v v bb [3] output reference voltage relative to v cc [6] v cc ? 1.620 v cc ? 1.220 v notes: 4. theta ja eia jedec 51 test board conditions (typical value); theta jc 883e method 1012.1 5. power calculation: v cc * i ee +0.5 (i oh + i ol ) (v oh ? v ol ) (number of differential outputs used); i ee does not include current going off chip. 6. where v cc is 3.3v5% or 2.5v5% 7. inputs have internal pull-up/pull-down or biasing resistors which affect the input current. 8. refer to figure 1 9. equivalent to a termination of 50 ? to vtt. i ohmin =(v ohmin -v tt )/50; i ohmax =(v ohmax -v tt )/50; i olmin =(v olmin -v tt )/50; i olmax =(v olmax -v tt )/50; 10. v il will operate down to v ee ; v ih will operate up to v cc
fastedge? series cy2pp318 document #: 38-07501 rev.*e page 4 of 8 ecl dc electrical specifications parameter description c ondition min. max. unit v ee negative power supply ?2.5v 5%, v cc = 0.0v ?3.3v 5%, v cc = 0.0v ?2.625 ?3.465 ?2.375 ?3.135 v v cmr differential cross point voltage [8] differential operation v ee + 1.2 0v v v oh output high voltage i oh = ?30 ma [9] ?1.25 ?0.7 v v ol output low voltage v ee = ?3.3v 5% v ee = ?2.5v 5% i ol = ?5 ma [9] ?1.995 ?1.995 ?1.5 ?1.3 v v ih input voltage, high single -ended operation ?1.165 ?0.880 [10] v v il input voltage, low single-ended operation ?1.945 [10] ?1.625 v v bb [3] output reference voltage ? 1.620 ? 1.220 v ac electrical specifications parameter description condition min. max. unit v pp differential input voltage [8] differential operation 0.1 1.3 v f clk input frequency 50% duty cycle standard load 1.5 ghz t pd propagation delay clka or clkb to output pair 660 mhz [11] 400 680 ps vo output voltage (peak-to-peak; see fig- ure 2) < 1 ghz 0.375 ? v v cmro output common voltage range (typ.) v cc ? 1.425 v tsk (0) output-to-output skew 660 mhz [11] , see figure 3 ? 50 ps tsk (pp) part-to-part output skew 660 mhz [11] ?150ps t per output period jitter (rms) [12] 660 mhz [11] ?1.6ps tsk (p) output pulse skew [13] 660 mhz [11] , see figure 3 ? 35 ps t r ,t f output rise/fall time (see figure 2) 660 mhz 50% duty cycle differential 20% to 80% 0.08 0.3 ns notes: 11. 50% duty cycle; standard load; differential operation 12. for 3.3v supplies. jitter measured differentially using an ag ilent 8133a pulse generator with an 8500a lecroy wavemaster osc illoscope using at least 10,000 data points 13. output pulse skew is the absolute diff erence of the propagation delay times: | t plh ? t phl |
fastedge? series cy2pp318 document #: 38-07501 rev.*e page 5 of 8 timing definitions . vih vil vcmr vpp vcmr min = vee + 1.2 vpp range 0.1v - 1.3v vcmr max = vcc vcc vee figure 1. pecl/ecl input waveform definitions tr, tf, 20-80% vo figure 2. ecl/lvpecl output figure 3. propagation delay (t pd ), output pulse skew (|t plh -t phl |), and output-to-output skew (t sk(o) ) for both clka or clkb to output pair, pecl/ecl to pecl/ecl vo vpp tpd in p u t clock o utput clock another o utput clock tplh, tphl ts k (o )
fastedge? series cy2pp318 document #: 38-07501 rev.*e page 6 of 8 test configuration standard test load using a di fferential pulse generator and differential measurement instrument. applications information termination examples pulse generator z = 50 ohm zo = 50 ohm vtt vtt r t = 50 ohm zo = 50 ohm vtt 5" 5" vtt r t = 50 ohm dut cy2pp318 r t = 50 ohm r t = 50 ohm figure 4. cy2pp318 ac test reference vtt zo = 50 ohm vtt 5" 5" cy2pp318 r t = 50 ohm r t = 50 ohm vcc vee figure 5. standard lvpecl ? pecl output termination vtt zo = 50 ohm vtt 5" 5" cy2pp318 r t = 50 ohm r t = 50 ohm vcc vee vbb (3.3v) figure 6. driving a pecl/ecl single-ended input
fastedge? series cy2pp318 document #: 38-07501 rev.*e page 7 of 8 ? cypress semiconductor corporation, 2004. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. package drawing and dimensions fastedge is a trademark of cypress semi conductor. all product and company name s mentioned in this document are the trademarks of their respective holders. ordering information part number package type product flow CY2PP318JI 28-pin plcc industrial, ?40 to 85 c CY2PP318JIt 28-pin plcc ? tape and reel industrial, ?40 to 85 c 3.3v zo = 50 ohm 3.3v 5" 5" cy2pp318 120 ohm 120 ohm vcc =3.3v vee = 0v lvds 51 ohm (2 places) 33 ohm (2 places) lvpecl to lvds figure 7. low-vo ltage positive emitter-couple d logic (lvpecl) to a low-vo ltage different ial signaling (lvds) interface 28-lead plastic leaded chip carrier j64 51-85001-*a
fastedge? series cy2pp318 document #: 38-07501 rev.*e page 8 of 8 document history page document title: cy2pp318 fastedge? series 1 of 2:8 differential clock/data fanout buffer document number: 38-07501 rev. ecn no. issue date orig. of change description of change ** 122041 02/13/03 rgl new data sheet *a 125923 06/11/03 rgl shifted the pin location changed the title (comlink to fastedge) corrected specs that does not match eros/iros *b 204240 see ecn rgl change pin 1 from vcc to vcco *c 222602 see ecn rgl changed the ecl and pecl mode ranges in the features section specified tsk max value to 150ps replaced i cc calculation with power calculation in the footnote. reformatted datasheet revised jitter spec as period jitter (rms) max operating frequency 1.5 ghz *d 229352 see ecn rgl added jedec spec for msl *e 247624 see ecn rgl/ggk changed v oh and v ol to match with the char data
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