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i 2 c-compatible, wide bandwidth, quad, 2:1 multiplexer ADG791A/adg791g rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features bandwidth: 325 mhz low insertion loss and on resistance: 2.6 typical on resistance flatness: 0.3 typical single 3 v/5 v supply operation 3.3 v analog signal range (5 v supply, 75 load) low quiescent supply cu rrent: 1 na typical fast switching times: t on = 186 ns, t off = 177 ns i 2 c?-compatible interface compact 24-lead lfcsp esd protection 4 kv human body model (hbm) 200 v machine model (mm) 1 kv field-induced charged device model (ficdm) applications s-video rgb/ypbpr video switches hdtvs projection tvs dvd-r/rw av receivers functional block diagram s1a s1b d1 s2a s2b d2 s3a s3b d3 s4a s4b d4 gpo1 adg791g i 2 c serial interface sclsda a2a1a0 v dd gnd 06033-001 s 1a s 1b d1 s 2a s 2b d2 s 3a s 3b d3 s 4a s 4b d4 ADG791A i 2 c serial interface sclsda a2a1a0 v dd gnd figure 1. general description the ADG791A/adg791g are monolithic cmos devices comprising four 2:1 multiplexers/demultiplexers controllable via a standard i 2 c serial interface. the cmos process provides ultralow power dissipation yet gives high switching speed and low on resistance. the on-resistance profile is very flat over the full analog input range and wide bandwidth ensures excellent linearity and low distortion. these features, combined with a wide input signal range make the ADG791A/adg791g the ideal switching solution for a wide range of tv applications including s-video, rgb, and ypbpr video switches. the switches conduct equally well in both directions when on. in the off condition, signal levels up to the supplies are blocked. the ADG791A/adg791g switches exhibit break-before-make switching action. the adg791g has one general-purpose logic output pin controlled by the i 2 c interface that can also be used to control other non-i 2 c-compatible devices such as video filters. the integrated i 2 c interface provides a large degree of flexibility in the system design. it has three configurable i 2 c address pins that allow up to eight devices on the same bus. this allows the user to expand the capability of the device by increasing the size of the switching array. the ADG791A/adg791g operate from a single 3 v or 5 v supply voltage and is available in a compact 4 mm 4 mm body, 24-lead lfcsp . product highlights 1. wide bandwidth: 325 mhz. 2. ultralow power dissipation. 3. extended input signal range. 4. integrated i 2 c serial interface. 5. compact 4 mm 4 mm, 24-lead, pb-free lfcsp. 6. esd protection tested as per esd association standards: 4 kv hbm (ansi/esd stm5.1-2001) 200 v mm (ansi/esd stm5.2-1999) 1 kv ficdm (ansi/esdstm5.3.1-1999)
ADG791A/adg791g rev. 0 | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 i 2 c timing specifications ............................................................ 7 timing diagram ........................................................................... 8 absolute maximum ratings ............................................................ 9 esd caution .................................................................................. 9 pin configurations and function descriptions ......................... 10 typical performance characteristics ........................................... 11 test circ u its ..................................................................................... 14 ter mi nolo g y .................................................................................... 16 theory of operation ...................................................................... 17 i 2 c serial interface ..................................................................... 17 i 2 c address .................................................................................. 17 write operation .......................................................................... 17 ldsw bit ..................................................................................... 19 power on/software reset .......................................................... 19 read operation ........................................................................... 19 evaluation board ............................................................................ 20 using the adg791g evaluation board .................................. 20 outline dimensions ....................................................................... 23 ordering guide .......................................................................... 23 revision history 7/06revision 0: initial version
ADG791A/adg791g rev. 0 | page 3 of 24 specifications v dd = 5 v 10%, gnd = 0 v, t a = ?40c to +85c, unless otherwise noted. table 1. parameter conditions min typ 1 max unit analog switch analog signal range 2 v s = v dd , r l = 1 m 0 4 v v s = v dd , r l = 75 0 3.3 v on resistance, r on v d = 0 v, i ds = ?10 ma, see figure 22 2.6 3.5 v d = 0 v to 1 v, i ds = ?10 ma, see figure 22 4 on-resistance matching between channels, ?r on v d = 0 v, i ds = ?10 ma 0.15 0.5 v d = 1 v, i ds = ?10 ma 0.6 on-resistance flatness, r flat (on) v d = 0 v to 1 v, i ds = ?10 ma 0.3 0.55 leakage currents source off leakage (i s (off) ) v d = 4 v/1 v, v s = 1 v/4 v, see figure 23 0.25 na drain off leakage (i d (off) ) v d = 4 v/1 v, v s = 1 v/4 v, see figure 23 0.25 na channel on leakage (i d (on) , i s (on) ) v d = v s = 4 v/1 v, see figure 24 0.25 na dynamic characteristics 3 t on , t enable c l = 35 pf, r l = 50 , v s = 2 v, see figure 28 186 250 ns t off , t disable c l = 35 pf, r l = 50 , v s = 2 v, see figure 28 177 240 ns break-before-make time delay, t d c l = 35 pf, r l = 50 , v s1 = v s2 = 2 v, see figure 29 1 3 ns i 2 c to gpo propagation delay, t h , t l (adg791g only) 130 ns off isolation f = 10 mhz, r l = 50 , see figure 26 ?60 db channel-to-channel crosstalk f = 10 mhz, r l = 50 , see figure 27 same multiplexer ?55 db different multiplexer ?70 db ?3 db bandwidth r l = 50 , see figure 25 325 mhz thd + n r l = 100 0.14 % charge injection c l = 1 nf, v s = 0 v, see figure 30 5 pc c s (off) 10 pf c d (off) 13 pf c d (on) , c s (on) 27 pf power supply rejection ratio, psrr f = 20 khz 70 db differential gain error ccir330 test signal 0.32 % differential phase error ccir330 test signal 0.44 degrees logic inputs 3 a0, a1, a2 input high voltage, v inh 2.0 v input low voltage, v inl 0.8 v input current, i inl or i inh v in = 0 v to v dd 0.005 1 a input capacitance, c in 3 pf scl, sda input high voltage, v inh 0.7 v dd v dd + 0.3 v input low voltage, v inl ?0.3 +0.3 v dd v input leakage current, i in v in = 0 v to v dd 0.005 1 a input hysteresis 0.05 v dd v input capacitance, c in 3 pf
ADG791A/adg791g rev. 0 | page 4 of 24 parameter conditions min typ 1 max unit logic outputs 3 sda pin output low voltage, v ol i sink = 3 ma 0.4 v i sink = 6 ma 0.6 v floating-state leakage current 1 a floating-state output capacitance 10 pf gpo1 pin and gpo2 pin output low voltage, v ol i load = +2 ma 0.4 v output high voltage, v oh i load = ?2 ma 2.0 v power requirements i dd digital inputs = 0 v or v dd , i 2 c interface inactive 0.001 1 a i 2 c interface active, f scl = 400 khz 0.2 ma i 2 c interface active, f scl = 3.4 mhz 0.7 ma 1 all typical values are at t a = 25c, unless otherwise stated. 2 guaranteed by initial characterization, not subject to production test. 3 guaranteed by design, not subject to production test.
ADG791A/adg791g rev. 0 | page 5 of 24 v dd = 3 v 10%, gnd = 0 v, t a = ?40c to +85c, unless otherwise noted. table 2. parameter conditions min typ 1 max unit analog switch analog signal range 2 v s = v dd , r l = 1 m 0 2.2 v v s = v dd , r l = 75 0 1.7 v on resistance, r on v d = 0 v, i ds = ?10 ma, see figure 22 3 4 v d = 0 v to 1 v, i ds = ?10 ma, see figure 22 6 on-resistance matching between channels, ?r on v d = 0 v, i ds = ?10 ma 0.15 0.6 v d = 1 v, i ds = ?10 ma 1.1 on-resistance flatness, r flat (on) v d = 0 v to 1 v, i ds = ?10 ma 0.8 2.8 leakage currents source off leakage (i s (off) ) v d = 2 v/1 v, v s = 1 v/2 v, see figure 23 0.25 na drain off leakage (i d (off) ) v d = 2 v/1 v, v s = 1 v/2 v, see figure 23 0.25 na channel on leakage (i d (on) , i s (on) ) v d = v s = 2 v/1 v, see figure 24 0.25 na dynamic characteristics 3 t on , t enable c l = 35 pf, r l = 50 , v s = 2 v, see figure 28 198 270 ns t off , t disable c l = 35 pf, r l = 50 , v s = 2 v, see figure 28 195 260 ns break-before-make time delay, t d c l = 35 pf, r l = 50 , v s1 = v s2 = 2 v, see figure 29 1 3 ns i 2 c to gpo propagation delay, t h , t l (adg791g only) 121 ns off isolation f = 10 mhz, r l = 50 , see figure 26 ?60 db channel-to-channel crosstalk f = 10 mhz, r l = 50 , see figure 27 same multiplexer ?55 db different multiplexer ?70 db ?3 db bandwidth r l = 50 , see figure 25 310 mhz thd + n r l = 100 0.14 % charge injection c l = 1 nf, v s = 0 v, see figure 30 2.5 pc c s (off) 10 pf c d (off) 13 pf c d (on) , c s (on) 27 pf power supply rejection ratio, psrr f = 20 khz 70 db differential gain error ccir330 test signal 0.28 % differential phase error ccir330 test signal 0.28 degrees logic inputs 3 a0, a1, a2 input high voltage, v inh 2.0 v input low voltage, v inl 0.8 v input current, i inl or i inh v in = 0 v to v dd 0.005 1 a input capacitance, c in 3 pf scl, sda input high voltage, v inh 0.7 v dd v dd + 0.3 v input low voltage, v inl ?0.3 +0.3 v dd v input leakage current, i in v in = 0 v to v dd 0.005 1 a input hysteresis 0.05 v dd v input capacitance, c in 3 pf
ADG791A/adg791g rev. 0 | page 6 of 24 parameter conditions min typ 1 max unit logic outputs 3 sda pin output low voltage, v ol i sink = 3 ma 0.4 v i sink = 6 ma 0.6 v floating-state leakage current 1 a floating-state output capacitance 3 pf gpo1 pin and gpo2 pin output low voltage, v ol i load = +2 ma 0.4 v output high voltage, v oh i load = ?2 ma 2.0 v power requirements i dd digital inputs = 0 v or v dd , i 2 c interface inactive 0.001 1 a i 2 c interface active, f scl = 400 khz 0.1 ma i 2 c interface active, f scl = 3.4 mhz 0.2 ma 1 all typical values are at t a = 25c, unless otherwise stated. 2 guaranteed by initial characterization, not subject to production test. 3 guaranteed by design, not subject to production test.
ADG791A/adg791g rev. 0 | page 7 of 24 i 2 c timing specifications v dd = 2.7 v to 5.5 v; gnd = 0 v; t a = ?40c to +85c, unless otherwise noted. see figure 2 for timing diagram. table 3. parameter 1 conditions min max unit description f scl standard mode 100 khz serial clock frequency fast mode 400 khz high speed mode c b = 100 pf max 3.4 mhz c b = 400 pf max 1.7 mhz t 1 standard mode 4 s t high , scl high time fast mode 0.6 s high speed mode c b = 100 pf max 60 ns c b = 400 pf max 120 ns t 2 standard mode 4.7 s t low , scl low time fast mode 1.3 s high speed mode c b = 100 pf max 160 ns c b = 400 pf max 320 ns t 3 standard mode 250 ns t su;dat , data setup time fast mode 100 ns high speed mode 10 ns t 4 2 standard mode 0 3.45 s t hd;dat , data hold time fast mode 0 0.9 s high speed mode c b = 100 pf max 0 703 ns c b = 400 pf max 0 150 ns t 5 standard mode 4.7 s t su;sta , setup time for a repeated start condition fast mode 0.6 s high speed mode 160 ns t 6 standard mode 4 s t hd;sta , hold time (repeated) start condition fast mode 0.6 s high speed mode 160 ns t 7 standard mode 4.7 s t buf , bus free time between a stop and a start condition fast mode 1.3 s t 8 standard mode 4 s t su;sto , setup time for stop condition fast mode 0.6 s high speed mode 160 ns t 9 standard mode 1000 ns t rda , rise time of sda signal fast mode 20 + 0.1 c b b 300 ns high speed mode c b = 100 pf max 10 80 ns c b = 400 pf max 20 160 ns t 10 standard mode 300 ns t fda , fall time of sda signal fast mode 20 + 0.1 c b b 300 ns high speed mode c b = 100 pf max 10 80 ns c b = 400 pf max 20 160 ns t 11 standard mode 1000 ns t rcl , rise time of scl signal fast mode 20 + 0.1 c b b 300 ns high speed mode c b = 100 pf max 10 40 ns c b = 400 pf max 20 80 ns
ADG791A/adg791g rev. 0 | page 8 of 24 parameter 1 conditions min max unit description t 11a standard mode 1000 ns t rcl1 , rise time of scl signal after a repeated start condition and after an acknowledge bit. fast mode 20 + 0.1 c b b 300 ns high speed mode c b = 100 pf max 10 80 ns c b = 400 pf max 20 160 ns t 12 standard mode 300 ns t fcl , fall time of scl signal fast mode 20 + 0.1 c b b 300 ns high speed mode c b = 100 pf max 10 40 ns c b = 400 pf max 20 80 ns t sp fast mode 0 50 ns pulse width of suppressed spike high speed mode 0 10 ns 1 guaranteed by initial characterization. c b refers to capacitive load on the bus line, t r and t f measured between 0.3 v dd and 0.7 v dd . 2 a device must provide a data hold time for sda to bridge the undefined region of the scl falling edge. timing diagram scl s da ps s p t 8 t 6 t 5 t 3 t 10 t 9 t 4 t 6 t 1 t 7 t 2 t 11 t 12 0 6033-002 figure 2. timing diagram for 2-wire serial interface
ADG791A/adg791g rev. 0 | page 9 of 24 absolute maximum ratings t a = 25c, unless otherwise noted. table 4. parameter ratings v dd to gnd ?0.3 v to +6 v analog, digital inputs ?0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first continuous current, s or d 100 ma peak current, s or d 300 ma (pulsed at 1 ms, 10% duty cycle max) operating temperature range industrial (b version) ?40c to +85c storage temperature range ?65c to +150c junction temperature 150c ja thermal impedance 24-lead lfcsp 30c/w lead temperature, soldering (10 sec) 300c ir reflow, peak temperature (<20 sec) 260c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd pr ecautions are recommended to avoid performance degradation or loss of functionality.
ADG791A/adg791g rev. 0 | page 10 of 24 pin configurations and function descriptions pin 1 indicator 1 s1a 2 s1b 3 d1 4 d2 5 s2b 6 s2a 15 nc 16 nc 17 nc 18 a2 14 nc 13 nc 7 s 3 a 8 s 3 b 9 d 3 1 1 s 4 b 1 2 s 4 a 1 0 d 4 2 1 s c l 2 2 s d a 2 3 v d d 2 4 g n d 2 0 a 0 1 9 a 1 ADG791A top view (not to scale) notes 1. nc = no connect. 2. the exposed pad must be tied to gnd. 06033-004 pin 1 indicator 1 s1a 2 s1b 3 d1 4 d2 5 s2b 6 s2a 15 nc 16 gpo1 17 nc 18 a2 14 nc 13 nc 7 s 3 a 8 s 3 b 9 d 3 1 1 s 4 b 1 2 s 4 a 1 0 d 4 2 1 s c l 2 2 s d a 2 3 v d d 2 4 g n d 2 0 a 0 1 9 a 1 adg791g top view (not to scale) notes 1. nc = no connect. 2. the exposed pad must be tied to gnd. 06033-003 figure 3. adg791g pin configuration figure 4. ADG791A pin configuration table 5. ADG791A/adg791g pi n function descriptions pin no. mnemonic description 1 s1a a-side source terminal for mux 1. can be an input or output. 2 s1b b-side source terminal for mu x 1. can be an input or output. 3 d1 drain terminal for mux 1. can be an input or output. 4 d2 drain terminal for mux 2. can be an input or output. 5 s2b b-side source terminal for mu x 2. can be an input or output. 6 s2a a-side source terminal for mu x 2. can be an input or output. 7 s3a a-side source terminal for mu x 3. can be an input or output. 8 s3b b-side source terminal for mu x 3. can be an input or output. 9 d3 drain terminal for mux 3. can be an input or output. 10 d4 drain terminal for mux 4. can be an input or output. 11 s4b b-side source terminal for mux 4. can be an input or output. 12 s4a a-side source terminal for mu x 4. can be an input or output. 13 nc not internally connected. 14 nc not internally connected. 15 nc not internally connected. 16 nc/gpo1 not internally connected for ADG791A/general-purpose logic output 1 for adg791g. 17 nc not internally connected. 18 a2 logic input. sets bit a2 from the leas t significant bit of the 7-bit slave address. 19 a1 logic input. sets bit a1 from the leas t significant bit of the 7-bit slave address. 20 a0 logic input. sets bit a0 from the leas t significant bit of the 7-bit slave address. 21 scl digital input, serial clock line. open -drain input that is used in conjun ction with sda to clock data into the device. external pull-up resistor required. 22 sda digital i/o. bidirectional, open-drain data line. external pull-up resistor required. 23 v dd positive power supply input. 24 gnd ground (0 v) reference.
ADG791A/adg791g rev. 0 | page 11 of 24 input signal (v) output signal (v) typical performance characteristics 3.0 0 03 . 5 2.5 2.0 1.5 1.0 0.5 0.5 1.0 1.5 2.0 2.5 3.0 t a =25c 1 channel v dd =2.7v,r l =75 ? v dd =3v,r l =75 ? v dd =3.3v,r l =75 ? v dd =2.7v,r l =1m ? v dd =3v,r l =1m ? v dd =3.3v,r l =1m ? 06033-005 figure 5. analog signal range, 3 v supply 06033-006 5.0 0 06 input signal (v) output signal (v) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 12345 t a =25c 1channel v dd =5.5v,r l =1m ? v dd =4.5v,r l =1m ? v dd =4.5v,r l =75 ? v dd =5v,r l =75 ? v dd =5.5v,r l =75 ? v dd =5v,r l =1m ? figure 6. analog signal range, 5 v supply 6 0 01 . 8 06033-007 4.0 0 03 . 0 v d (v s )(v) r on t a = 25c 1 channel v dd =5.0v 3.5 3.0 2.5 2.0 1.5 1.0 0.5 v dd =4.5v v dd =5.5v ( ? ) 0.5 1.0 1.5 2.0 2.5 06033-008 . 6 v d (v s )(v) r on ( ? ) 5 4 3 2 1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 t a = 25c 1 channel v dd =2.7v v dd =3.3v v dd =3.0v figure 7. on resistance vs. v d (v s ), 3 v supply figure 8. on resistance vs. v d (v s ), 5 v supply 7 0 01 v d (v s )(v) r on ( ? ) 6 5 4 3 2 1 0.20.40.60.81.01.21.4 t a = 25c 1 channel v dd =3v t a = +25c t a =+85c t a =?40c 0 6033-009 figure 9. on resistance vs. v d (v s ) for various temperatures, 3 v supply 4.5 0 03 . 0 v d (v s )(v) r on t a =+25c 1 channel v dd =5v t a = +85c ( ? ) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 t a = +25c t a = ?40c 0.51.01.52.02.5 06033-010 figure 10. on resistance vs. v d (v s ) for various temperatures, 5 v supply
ADG791A/adg791g rev. 0 | page 12 of 24 source voltage (v) charge injection (pc) 0 ?5.0 04 . 0 0 ?120 0.01 1000 frequency (mhz) crosstalk (db) ?0.5 ?1.0 ?1.5 ?2.0 ?2.5 ?3.0 ?3.5 ?4.0 ?4.5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 v dd =5v v dd =3v t a =25c v dd =3v/5v t a =25c 06033-011 figure 11. charge injection vs. source voltage 220 160 ?40?200 20406080 temperature (c) t on / t off (ns) 210 200 190 180 170 t on (3v) t off (3v) t off (5v) t on (5v) 06033-012 figure 12. t on /t off vs. temperature 0 ?120 0.01 1000 frequency (mhz) off isolation (db) 0.1 1 10 100 ?20 ?40 ?60 ?80 ?100 t a = 25c v dd =3v/5v 06033-013 figure 13. off isolation vs. frequency 0.1 1 10 100 ?20 ?40 ?60 ?80 ?100 same multiplexer different multiplexer 06033-014 figure 14. crosstalk vs. frequency ?15 ?13 ?11 ?9 ?7 ?5 ?3 ?1 0.01 1000 frequency (mhz) attenuation (db) 0.1 1 10 100 t a =25c v dd =5v 06033-015 figure 15. bandwidth 0 ?100 0.0001 1000 frequency (mhz) psrr (db) ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 0.001 0.01 0.1 1 10 100 0 6033-016 t a = 25c 1 channel v dd =3v/5v no decoupling capacitors used figure 16. psrr vs. frequency
ADG791A/adg791g rev. 0 | page 13 of 24 0.40 0 0.1 3.1 f clk frequency (mhz) i dd (ma) 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.6 1.1 1.6 2.1 2.6 t a = 25c v dd =3v v dd =5v 06033-017 figure 17. i dd vs. f clk frequency 1.4 ?0.2 06 i 2 c logic input voltage (v) i dd (ma) 1.2 1.0 0.8 0.6 0.4 0.2 0 12345 t a = 25c v dd =3v v dd =5v 06033-018 figure 18. i dd vs. i 2 c logic input voltage (sda, scl) 120 95 ?40?200 20406080 temperature (c) propagation delay (ns) 115 110 105 100 t plh (5v) t phl (3v) t plh (3v) t phl (5v) 06033-019 figure 19. i 2 c to gpo propagation delay vs. temperature (adg791g only) 6 0 ?20 0 load current (ma) gpo voltage (v) 5 4 3 2 1 ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 t a = 25c v dd =3v v dd =5v 06033-020 figure 20. gpo v oh vs. load current 2.5 0 03 load current (ma) gpo voltage (v) 5 2.0 1.5 1.0 0.5 5 1015202530 t a = 25c v dd =3v v dd =5v 06033-021 figure 21. gpo v ol vs. load current
ADG791A/adg791g rev. 0 | page 14 of 24 test circuits sd r on =v1/i ds v1 i ds v s 06033-022 figure 22. on resistance sd a a i s (off) v s v d i d (off) 0 6033-023 figure 23. off leakage sd a v d i d (on) nc nc = no connect 06033-024 figure 24. on leakage d v dd 0.1f v s v out 50 ? 50? 50? 50? network analyzer gnd sa sb 06033-027 figure 25. bandwidth s d v dd 0.1f v s v out 50? 50 ? 50? 50 ? 50 ? network analyzer gnd 06033-028 figure 26. off isolation sy dy dx sx v dd 0.1f v s v out 50? 50 ? 50 ? r l 50 ? network analyzer gnd 50? 50 ? 06033-029 figure 27. channel-to-channel crosstalk
ADG791A/adg791g rev. 0 | page 15 of 24 i 2 c interface scl gnd sda c l 35pf r l 50? v s v out v dd 5v 0.1f sd scl v out 50% 90% 10% 50% t off t on clock pulses corresponding to the ldsw bits scl v gpo 50% 90% 10% 50% t l t h clock pulses corresponding to the ldsw bits 0 6033-025 figure 28. switching time i 2 c interface scl gnd sda c l 35pf r l 50? v s v out v dd 5 v 0.1f sa d sb scl v s t d v out 80% clock pulse corresponding to the ldsw bit 06033-026 figure 29. break-before-make time delay v out q inj =c l v out switch on switch off v s v out gnd v dd r s 5 v c l 1nf sd 06033-030 figure 30. charge injection
ADG791A/adg791g rev. 0 | page 16 of 24 terminology on resistance (r on ) the series on-channel resistance measured between the s and d pins. on resistance match (r on ) the channel-to-channel matching of on resistance when channels are operated under identical conditions. on resistance flatness (r flat(on) ) the variation of on resistance over the specified range produced by the specified analog input voltage change with a constant load current. channel off leakage (i off ) the sum of leakage currents into or out of an off channel input. channel on leakage (i on ) the current loss/gain through an on-channel resistance, creating a voltage offset across the device. input leakage current (i in , i inl , i inh ) the current flowing into a digital input when a specified low level or high level voltage is applied to that input. input/output off capacitance (c off ) the capacitance between an analog input and ground when the switch channel is off. input/output on capacitance (c on ) the capacitance between the inputs or outputs and ground when the switch channel is on. digital input capacitance (c in ) the capacitance between a digital input and ground. output on switching time (t on ) the time required for the switch channel to close. the time is measured from 50% of the falling edge of the ldsw bit to the time the output reaches 90% of the final value. output off switching time (t off ) the time required for the switch to open. the time is measured from 50% of the falling edge of the ldsw bit to the time the output reaches 10% of the final value. i 2 c to gpo propagation delay (t h , t l ) the time required for the logic value at the gpo pin to settle after loading a gpo command. the time is measured from 50% of the falling edge of the ldsw bit to the time the output reaches 90% of the final value for high and 10% for low. total harmonic distortion + noise (thd + n) the ratio of the harmonic amplitudes plus noise of a signal to the fundamental. ?3 db bandwidth the frequency at which the output is attenuated by 3 db. off isolation the measure of unwanted signal coupling through an off switch. crosstalk the measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. charge injection the measure of the glitch impulse transferred from the digital input to the analog output during on/off switching. differential gain error the measure of how much color saturation shift occurs when the luminance level changes. both attenuation and amplifica- tion can occur; therefore, the largest amplitude change between any two levels is specified and expressed in %. differential phase error the measure of how much hue shift occurs when the luminance level changes. it can be a negative or positive value and is expressed in degrees of subcarrier phase. input high voltage (v inh ) the minimum input voltage for logic 1. input low voltage (v inl ) the maximum input voltage for logic 0. output high voltage (v oh ) the minimum output voltage for logic 1. output low voltage (v ol ) the maximum output voltage for logic 0. i dd positive supply current.
ADG791A/adg791g rev. 0 | page 17 of 24 theory of operation the ADG791A/adg791g are monolithic cmos devices comprising four 2:1 multiplexers controllable via a standard i 2 c serial interface. the cmos process provides ultralow power dissipation, yet offers high switching speed and low on resistance. the on resistance profile is very flat over the full analog input range, and wide bandwidth ensures excellent linearity and low distortion. these features, combined with a wide input signal range, make the ADG791A/adg791g an ideal switching solution for a wide range of tv applications. the switches conduct equally well in both directions when on. in the off condition, signal levels up to the supplies are blocked. the integrated serial i 2 c interface controls the operation of the switches (ADG791A/adg791g) and general-purpose logic pins (adg791g only). the ADG791A/adg791g have many attractive features, such as the ability to individually control each multiplexer, the option of reading back the status of any switch. the adg791g has one general-purpose logic output pin controllable through the i 2 c interface. the following sections describe these features in detail. i 2 c serial interface the ADG791A/adg791g are controlled via an i 2 c-compatible serial bus interface (refer to the i 2 c-bus specification available from philips semiconductor) that allows the part to operate as a slave device (no clock is generated by the ADG791A/adg791g). the communication protocol between the i 2 c master and the device operates as follows: 1. the master initiates data transfer by establishing a start condition (defined as a high-to-low transition on the sda line while scl is high). this indicates that an address/data stream follows. all slave devices connected to the bus respond to the start condition and shift in the next eight bits, consisting of a 7-bit address (msb first) plus an r/ w bit. this bit determines the direction of the data flow during the communication between the master and the addressed slave device. 2. the slave device whose address corresponds to the transmitted address responds by pulling the sda line low during the ninth clock pulse (this is known as the acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to, or read from, its serial register. if the r/ w bit is set high, the master reads from the slave device. however, if the r/ w bit is set low, the master writes to the slave device. 3. data transmits over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). the transitions on the sda line must occur during the low period of the clock signal, scl, and remain stable during the high period of scl. otherwise, a low-to-high transition when the clock signal is high can be interpreted as a stop event that ends the communication between the master and the addressed slave device. 4. after transferring all data bytes, the master establishes a stop condition, defined as a low-to-high transition on the sda line while scl is high. in write mode, the master pulls the sda line high during the 10 th clock pulse to establish a stop condition. in read mode, the master issues a no acknowledge for the ninth clock pulse (the sda line remains high). the master then brings the sda line low before the 10 th clock pulse, and then high during the 10 th clock pulse to establish a stop condition. i 2 c address the ADG791A/adg791g has a 7-bit i 2 c address. the four most significant bits are internally hardwired while the last three bits (a0, a1, and a2) are user-adjustable. this allows the user to connect up to eight ADG791As/adg791gs to the same bus. the i 2 c bit map shows the configuration of the address. 7-bit i 2 c address configuration msb l sb 1 0 1 0 a2 a1 a0 write operation when writing to the ADG791A/adg791g, the user must begin with an address byte and r/ w bit, after which time the switch acknowledges that it is prepared to receive data by pulling sda low. data is loaded into the device as a 16-bit word under the control of a serial clock input, scl. figure 31 illustrates the entire write sequence for the ADG791A/ adg791g. the first data byte (ax7 to ax0) controls the status of the switches while the ldsw and resetb bits from the second byte control the operation mode of the device. table 6 shows a list of all commands supported by the ADG791A/adg791g with the corresponding byte that needs to be loaded during a write operation. to achieve the desired configuration, one or more commands can be loaded into the device. any combination of the commands listed in table 6 can be used with these restrictions: ? only one switch from a given multiplexer can be on at any given time ? when a sequence of successive commands affect the same element (that is, the switch or gpo pin), only the last command is executed.
ADG791A/adg791g rev. 0 | page 18 of 24 scl sda a2 a1 a0 ax6 ax7 r/w ax5 ax4 ax3 ax2 ax1 ax0 x x x x x x resetb ldsw start condition by master stop condition by master address byte acknowledge by switch acknowledge by switch acknowledge by switch 06033-031 figure 31. write operation table 6. ADG791A/adg791g command list a7 a6 a5 a4 a3 a2 a1 a0 addressed switch 0 0 0 0 0 0 0 0 s1a/d1, s2a/d2, s3a/d3, s4a/d4 off 1 0 0 0 0 0 0 0 s1a/d1, s2a/d2, s3a/d3, s4a/d4 on 0 0 0 0 0 0 0 1 s1b/d1, s2b/d2, s3b/d3, s4b/d4 off 1 0 0 0 0 0 0 1 s1b/d1, s2b/d2, s3b/d3, s4b/d4 on 0 0 0 0 0 0 1 0 s1a/d1 off 1 0 0 0 0 0 1 0 s1a/d1 on 0 0 0 0 0 0 1 1 s1b/d1 off 1 0 0 0 0 0 1 1 s1b/d1 on 0 0 0 0 0 1 0 0 s2a/d2 off 1 0 0 0 0 1 0 0 s2a/d2 on 0 0 0 0 0 1 0 1 s2b/d2 off 1 0 0 0 0 1 0 1 s2b/d2 on 0 0 0 0 0 1 1 0 s3a/d3 off 1 0 0 0 0 1 1 0 s3a/d3 on 0 0 0 0 0 1 1 1 s3b/d3 off 1 0 0 0 0 1 1 1 s3b/d3 on 0 0 0 0 1 0 0 0 s4a/d4 off 1 0 0 0 1 0 0 0 s4a/d4 on 0 0 0 0 1 0 0 1 s4b/d4 off 1 0 0 0 1 0 0 1 s4b/d4 on x 1 0 0 0 1 0 1 0 reserved x 1 0 0 0 1 0 1 1 reserved x 1 0 0 0 1 1 0 0 reserved x 1 0 0 0 1 1 0 1 reserved x 1 0 0 0 1 1 1 0 mux 1 disabled (all switches connected to d1 are off ) x 1 0 0 0 1 1 1 1 mux 2 disabled (all switches connected to d2 are off ) x 1 0 0 1 0 0 0 0 mux 3 disabled (all switches connected to d3 are off ) x 1 0 0 1 0 0 0 1 mux 4 disabled (all switches connected to d4 are off ) x 1 0 0 1 0 0 1 0 reserved x 1 0 0 1 0 0 1 1 reserved 1 0 0 1 0 1 0 0 gpo1 high for adg791g/reserved for ADG791A 0 0 0 1 0 1 0 0 gpo1 low for adg791g/reserved for ADG791A 0 0 0 1 1 1 1 1 all muxes disabled 1 0 0 1 1 1 1 1 reserved 1 x = logic state does not matter.
ADG791A/adg791g rev. 0 | page 19 of 24 ldsw bit the ldsw bit allows the user to control the way the device executes the commands loaded during the write operations. the ADG791A/adg791g executes all the commands loaded between two successive write operations that have set the ldsw bit high. setting the ldsw high for every write cycle ensures that the device executes the command right after the ldsw bit was loaded into the device. this setting can be used when the desired configuration can be achieved by sending a single command or when the switches and/or gpo pin are not required to be updated at the same time. when the desired configuration requires multiple commands with simultaneous update, the ldsw bit should be set low while loading the commands except the last one when the ldsw bit should be set high. once the last command with ldsw = high is loaded, the device executes all commands received since the last update simultaneously. power on/software reset the ADG791A/adg791g has a software reset function implemented by the resetb bit from the second data byte written to the device. for normal operation of the multiplexers and gpo pin, this bit should be set high. when resetb = low or after power-up, the switches from all multiplexers are turned off (open) and the gpo pin is set low. read operation when reading data back from the ADG791A/adg791g, the user must begin with an address byte and r/ w bit. the switch then acknowledges that it is prepared to transmit data by pulling sda low. following this acknowledgement, the ADG791A/adg791g transmits two bytes on the next clock edges. these bytes contain the status of the switches, and each byte is followed by an acknowledge bit. a logic high bit represents a switch in the on (close) state while a low represents a switch in the off (open) state. for the gpo pin (adg791g only), the bit represents the logic value of the pin. figure 32 illustrates the entire read sequence. the bit maps accompanying figure 32 show the relationship between the elements of the ADG791A and adg791g (that it, the switches and gpo pins) and the bits that represent their status after a completed read operation. ADG791A bit map rb15 rb14 rb13 rb12 rb11 rb 10 rb9 rb8 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 s1a/d1 s1b/d1 s2a/d2 s2b/d2 s3a/d3 s3b/d3 s4a/d4 s4b/d4 - - - - - - - - adg791g bit map rb15 rb14 rb13 rb12 rb11 rb 10 rb9 rb8 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 s1a/d1 s1b/d1 s2a/d2 s2b/d2 s3a/d3 s3 b/d3 s4a/d4 s4b/d4 - - - - gpo1 - - - scl sda a2 a1 a0 rb14 rb15 r/w rb13 rb12 rb11 rb10 rb9 rb8 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 start condition by master stop condition by master address byte acknowledge by switch acknowledge by switch acknowledge by switch 06033-032 figure 32. ADG791A/adg791g read operation
ADG791A/adg791g rev. 0 | page 20 of 24 evaluation board the adg791g evaluation kit allows designers to evaluate the high performance of the device with a minimum of effort. the evaluation kit includes a printed circuit board populated with the adg791g. the evaluation board can be used to evaluate the performance of both the ADG791A and adg791g. it interfaces to the usb port of a pc, or it can be used as a standalone evaluation board. software is available with the evaluation board that allows the user to easily program the adg791g through the usb port. schematics of the evaluation board are shown in figure 33 and figure 34 . the software runs on any pc that has microsoft? windows? 2000 or windows xp installed. using the adg791g evaluation board the adg791g evaluation kit is a test system designed to simplify the evaluation of the device. each input/output of the part comes with a socket specifically chosen for easy audio/video evaluation. a data sheet is also available and gives full information on operating the evaluation board.
ADG791A/adg791g rev. 0 | page 21 of 24 j2-1 j2-2 t1 t4 r5 75? r6 75? r1 2.2k ? r2 2.2k ? r7 0 ? c4 10f c9 0.1f c18 0.1f c23 2.2f 3.3v 3.3v 3.3v shield 1 2 3 4 5 j1 usb-mini-b vbus d? d+ io gnd 42 44 54 9 8 33 34 35 36 37 38 39 40 1 2 13 14 pa0/int0 *wakeup clkout d? d+ pa1/int1 pa2/*sloe pa3/*wu2 pa4/fifoadr0 pa5/fifoadr1 pa6/*pktend pa7/*fld/slcs reset rdy0/*slrd rdy1/*slwr ifclk rsvd 18 pb0/fd0 19 pb1/fd1 20 pb2/fd2 21 pb3/fd3 22 pb4/fd4 23 pb5/fd5 24 pb6/fd6 25 pb7/fd7 45 pd0/fd8 46 pd1/fd9 47 pd2/fd10 48 pd3/fd11 49 pd4/fd12 50 pd5/fd13 51 pd6/fd14 52 29 30 31 16 15 4 5 pd7/fd15 3.3v 3.3v 3.3v 3.3v 3.3v 7 3 43 55 32 27 17 11 avcc vcc vcc vcc vcc vcc vcc vcc r31 10k ? r32 10k? r12 2.2k ? r9 2.2k ? r10 10k? scl_en ctl0/*flaga ctl1/*flagb ctl2/*flagc sda scl xtalout xtalin xtal1 24mhz agnd gnd gnd gnd gnd gnd gnd gnd 6 10 12 26 28 41 53 56 3.3v t27 t28 c21 0.1f c20 0.1f c19 0.1f c8 0.1f c7 0.1f c5 0.1f c6 0.1f j5 ab vdd c3 0.1f c13 10f 8 7 5 1 2 6 3 4 in1 in2 sd out1 out2 error nr u5 gnd adp3303-3.3 c16 0.1f c14 10f c15 0.1f t26 3.3v r11 1k ? c10 22pf c17 22pf 3.3v d4 24lc64 a0 a1 a2 vss vcc wp scl sda u2 c22 0.1f c2 0.1f u3 cy7c68013-cs p q1 q2 g g sd sd scl_en vdd sda scl u4 adg821 8 7 6 5 1 2 3 4 s1 d1 in2 gnd vdd in1 d2 s2 1 2 3 4 8 7 6 5 06033-033 *denotes programmable polarity. figure 33. eval-adg791geb schematic, usb controller section
ADG791A/adg791g rev. 0 | page 22 of 24 1 5 4 2 3 k4 phono_dual bottom top gnd case case 1 5 4 2 3 k5 phono_dual bottom top gnd case case 1 5 4 2 3 k6 phono_dual bottom top gnd case case r19 r20 r21 r22 r23 r24 t10 t11 t12 t13 t14 t15 a t2 t3 t22 t23 t24 t25 t7 t8 t9 t5 t6 12 7 8 9 10 11 23 24 22 21 20 19 u1 adg791g 25 paddle 13 14 15 16 17 18 1 2 3 4 5 6 r36 0 ? gpo1 vdd a 1 5 4 2 3 k7 phono_dual bottom top gnd case case 1 5 4 2 3 k8 phono_dual bottom top gnd case case 1 5 4 2 3 k9 phono_dual bottom top gnd case case gpo2 r25 r26 r28 r29 r30 r27 t16 t17 t18 t19 t20 t21 1 5 4 2 3 k3 phono_dual bottom top gnd case case 1 5 4 2 3 k2 phono_dual bottom top gnd case case 1 5 4 2 3 k1 phono_dual bottom top gnd case case r13 r14 r15 r16 r17 r3 10k ? r4 10k ? r8 10k ? r34 0 ? r35 0 ? r18 j3 j7 j8 j6-1 j6-2 j6-3 j4-1 j4-3 j4-2 gpo1 gpo2 c1 0.1f scl scl sda scl sda sda 06033-034 figure 34. eval-adg791geb schematic, chip section
ADG791A/adg791g rev. 0 | page 23 of 24 outline dimensions * compliant to jedec standards mo-220-vggd-2 except for exposed pad dimension 1 24 6 7 13 19 18 12 * 2.45 2.30 sq 2.15 0.60 max 0.50 0.40 0.30 0.30 0.23 0.18 2.50 ref 0.50 bsc 12 max 0.80 max 0.65 typ 0.05 max 0.02 nom 1.00 0.85 0.80 seating plane pin 1 indicator top view 3.75 bsc sq 4.00 bsc sq pin 1 indicator 0.60 max coplanarity 0.08 0.20 ref 0.23 min exposed pa d (bottomview) figure 35. 24-lead lead frame chip scale package [lfcsp_vq] 4 mm x 4 mm body, very thin quad (cp-24-2) dimensions shown in millimeters ordering guide model temperature range i 2 c speed package description package option ADG791Abcpz-reel 1 ?40c to +85c 100 khz, 400 khz 24-lead lfcsp_vq cp-24-2 ADG791Abcpz-500rl7 1 ?40c to +85c 100 khz, 400 khz 24-lead lfcsp_vq cp-24-2 ADG791Accpz-reel 1 ?40c to +85c 100 khz, 400 khz, 3.4 mhz 24-lead lfcsp_vq cp-24-2 ADG791Accpz-500rl7 1 ?40c to +85c 100 khz, 400 khz, 3.4 mhz 24-lead lfcsp_vq cp-24-2 adg791gbcpz-reel 1 ?40c to +85c 100 khz, 400 khz 24-lead lfcsp_vq cp-24-2 adg791gbcpz-500rl7 1 ?40c to +85c 100 khz, 400 khz 24-lead lfcsp_vq cp-24-2 adg791gccpz-reel 1 ?40c to +85c 100 khz, 400 khz, 3.4 mhz 24-lead lfcsp_vq cp-24-2 adg791gccpz-500rl7 1 ?40c to +85c 100 khz, 400 khz, 3.4 mhz 24-lead lfcsp_vq cp-24-2 eval-adg791geb 2 evaluation board 1 z = pb-free part. 2 evaluation board is rohs compliant.
ADG791A/adg791g rev. 0 | page 24 of 24 notes purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the phi lips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06033-0-7/06(0)

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