sg577c low emi clock generator for pentium ii systems with power management approved product international microcircuits, inc. 525 los coches st. rev 1.8 2/19/98 milpitas, ca 95035 tel: 408-263-6300 ext. 275 fax 408-263-6571 page 1 of 10 product features ? supports pentium . pentium ii & pro cpus. ? designed to meet intel chipset specification ? 4 cpu and 8 pci clocks ? two 48 mhz fixed clocks for usb and super io. ? separate supply pins for mixed cpu, ioapic, and fixed/pci clocks ? < 175 ps max. skew among cpu clocks. ? < 250 ps max. skew among pci clocks. ? controlled current output buffers ? power management feature ? 2 ioapic clocks for multiprocessor support. ? 48-pin ssop package ? spread spectrum emi reduction mode block diagram ref osc xin xout ref[1:3] ioapic[1:2} fs[0:2] cpu[1:4] pcif pci[1:7] pll2 48m[1:2] pstop #ssm cstop pll1 vddf vddp vddp vddc vddi vddr frequency table fs2 fs1 fs0 cpu pci 0 0 0 tri-state tri-state 0 1 1 66 (66.58)* 33.3* 1 0 0 ref/2 ref/4 1 1 1 100 (99.7)** 33.2** note: *down spread 1.25% (total) **down spread .5% (total) connection diagram 5() 5() 966 ;,1 ;287 966 3&,b) 3&, 9''3 3&, 966 3&, 3&, 3&, 3&, 3&, 9''3 966 9'' 9'') 0 0 966 )6 )6 )6 660 3' 36723 &6723 9'' &38 &38 966 &38 9''& 1& 966 966 9''& &38 966 ,2$3,& ,2$3,& 9'', 5() 9''5 966 ,0,6*
sg577c low emi clock generator for pentium ii systems with power management approved product international microcircuits, inc. 525 los coches st. rev 1.8 2/19/98 milpitas, ca 95035 tel: 408-263-6300 ext. 275 fax 408-263-6571 page 2 of 10 pin description pin no. pin name pwr i/o type description 4 xin vdd i osc1 on-chip reference oscillator input pin. re q uires either an external parallel resonant cr y stal ( nominall y 14.318 mhz ) or externall y g enerated reference si g nal 5 xout vdd o osc1 o-chip reference oscillator output pin. drives an external parallel resonant cr y stal when an externall y g enerated reference si g nal is used, is left unconnected 25, 26, 27 fs(0:2) - i pad pu fre q uenc y select input pins. see fre q uenc y select table on pa g e 1. these pin has an internal pull-up 40, 39, 36, 35 cpu(1:4) vddc o buf1 clock outputs. cpu fre q uenc y table specified on pa g e 1. 45, 44 ioapic(1:2) vddi o buf2 ioapic clock for multi processor support. fixed fre q uenc y at 14.31818 mhz. ( 2.5 or 3.3 suppl y = vddi ) 8, 10, 11, 13, 14, 16, 17 pci(1:7) vddp o buf4 pci bus clocks. see fre q uenc y select table on pa g e 1. 7 pci_f vddp o buf4 pci clock that ceases onl y when pd ( pin 29 ) is ascerted. see fre q uenc y select table on pa g e 1. 3, 6, 12, 18, 20, 24, 32, 34, 38, 43 vss - p - ground pins for the device. 46 vddi - p - 3.3 or 2.5 volt power suppl y pins for ioapic clock output buffers. 9, 15 vddp - p - 3.3 volt power suppl y pins for pci and pci_f clock output buffers. 21 vddf - p - 3.3 volt power suppl y pins for 48 mhz clock output buffers. 48 vddr - p 3.3 volt power suppl y pins for reference clock output buffers. 37, 41 vddc - p - 3.3 or 2.5 volt power suppl y pins for cpu clock output buffers. 19, 33 vdd power suppl y pins for analo g circuits and core lo g ic 1, 2, 47 ref(1:3) vddr o buf3 buffered outputs of on-chip reference oscillator. 22, 23 48m(1:2) vddf o buf3 fixed 48 mhz fre q uenc y clock outputs. 31 pstop - i pad pu when driven to a lo g ic low level, this pin will s y nchronousl y stop all pci clocks ( except pci_f ) at a lo g ic low level. 30 cstop - i pad pu when driven to a lo g ic low level, this pin will s y nchronousl y stop all cpu clocks at a lo g ic low level. 28 #ssm - i pad pu when driven to a lo g ic low level this pin enables emi reducin g spread spectrum mode ( affects onl y cpu and pci clocks ) . 29 pd - i pad pu when this pin is driven to a lo g ic low the ic will enter shutdown mode and all internal circuitry is turned off.
sg577c low emi clock generator for pentium ii systems with power management approved product international microcircuits, inc. 525 los coches st. rev 1.8 2/19/98 milpitas, ca 95035 tel: 408-263-6300 ext. 275 fax 408-263-6571 page 3 of 10 outputs descriptions cpu pci, pcif 48 mhz ref1:3 ioapic tri-state hi-z hi-z hi-z hi-z hi-z test mode tclk/2 tclk/4 tclk/2 tclk tclk note: tclk is a test clock that is driven into the xtal_in input during test mode. power management functions all pci (excluding pci_f) and cpu clocks can be enabled or stopped via the pstop and cstop input pins. all clocks are stopped in the low state. all clocks maintain a valid high period on transitions from running to stopped and on transitions from stopped to running when the chip was not powered down. on power up, (after bring pd from a low to high state) the vcos will stabilize to the correct pulse widths within about 0.2 ms. the cpu, and pci clocks transition between running and stopped by waiting for one positive edge on pci_f followed by a negative edge on the clock of interest, after which high levels of the output are either enabled or disabled. cstop pstop pd cpuclk pciclk other clks xtal & vcos x x 0 low low low off 0 0 1 low low running running 0 1 1 low running running running 1 0 1 running low running running 1 1 1 running running running running power management timing pciclk_f pstop pciclk(0:5) cstop cpuclk(0:3)
sg577c low emi clock generator for pentium ii systems with power management approved product international microcircuits, inc. 525 los coches st. rev 1.8 2/19/98 milpitas, ca 95035 tel: 408-263-6300 ext. 275 fax 408-263-6571 page 4 of 10 power management timing latency signal signal state no. of rising edges of free running pciclk (pcif) cstop 0 (disabled) 1 1 (enabled) 1 pstop 0 (disabled) 1 1 (enabled) 1 pd 1 (normal operation) 3 ms 0 (power down) 2 ms max. notes: 1. clock on/off latency is defined in the number of rising edges of free running pciclks between the clock disable goes low/high to the first valid clock comes out of the device. 2. power up latency is when pwr_dwn# goes inactive (high) to when the first valid clocks are driven from the device. spectrum spread clocking spectrum analysis center frequency(mhz) amplitude (db) without spectrum spread with spectrum spread down spread
sg577c low emi clock generator for pentium ii systems with power management approved product international microcircuits, inc. 525 los coches st. rev 1.8 2/19/98 milpitas, ca 95035 tel: 408-263-6300 ext. 275 fax 408-263-6571 page 5 of 10 spectrum spreading selection table min (mhz) center (mhz) max (mhz) cpu frequency % of frequency spreading mode 99.50 99.75 99.7 100 .5% (-.5% + 0%) down spread 65.4 66.4 67.39 66 1.25% (-1.25% + 0%) down spread maximum ratings voltage relative to vss: -0.3v voltage relative to vdd: 0.3v storage temperature: 0oc to + 125oc operating temperature: 0oc to +70oc maximum power supply: 7v this device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. for proper operation, vin and vout should be constrained to the range: vss<(vin or vout) sg577c low emi clock generator for pentium ii systems with power management approved product international microcircuits, inc. 525 los coches st. rev 1.8 2/19/98 milpitas, ca 95035 tel: 408-263-6300 ext. 275 fax 408-263-6571 page 6 of 10 switching characteristics characteristic symbol min typ max units conditions output duty cycle - 45 50 55 % measured at 1.5v cpu to pci offset toff 1.5 - 4 ns cpu load = 20 pf, pci load = 30 pf measured at 1.5v pci and 1.25v cpu buffer out skew all cpu buffer outputs tskew 1 - - 175 ps 20 pf load measured at 1.5v buffer out skew all pci buffer outputs tskew 2 - - 250 ps 30 pf load measured at 1.5v d period adjacent cycles d p - - +250 ps - jitter spectrum 20 db bandwidth from center bw j 500 khz vdd = vddp=vddf =vddr =3.3v 5 %, vddc, & vddi = 2.5v 5 %, ta = 0oc to +70oc buffer 1 characteristics for cpuclk(1:4) characteristic symbol min typ max units conditions pull-up current min ioh min -27 - - ma vout = 1.0 v pull-up current max ioh max - - -27 ma vout = 2.375 v pull-down current min iol min 27 - - ma vout = 1.2 v pull-down current max iol max - - 30 ma vout = 0.3 v rise/fall time min/max between 0.4 v and 2.0 v trf 0.4 - 1.6 ns 20 pf load vdd = vddp=vddf =vddr =3.3v 5 %, vddc, & vddi =2.5v 5 %,, ta = 0oc to +70oc
sg577c low emi clock generator for pentium ii systems with power management approved product international microcircuits, inc. 525 los coches st. rev 1.8 2/19/98 milpitas, ca 95035 tel: 408-263-6300 ext. 275 fax 408-263-6571 page 7 of 10 buffer 2 characteristics for ioapic (1:2) characteristic symbol min typ max units conditions pull-up current min ioh min -36 - - ma vout = 1.4 v pull-up current max ioh max - - -21 ma vout = 2.5 v pull-down current min iol min 36 - - ma vout = 1.0 v pull-down current max iol max - - 31 ma vout = 0.2 v rise/fall time min/max between 0.4 v and 2.0 v trf max 0.4 - 1.6 ns 20 pf load vdd = vddp=vddf =vddr =3.3v 5 %, vddc, & vddi =2.5v 5 %,, ta = 0oc to +70oc buffer 3 characteristics for ref(1:3) and 48(1:2) mhz characteristic symbol min typ max units conditions pull-up current min ioh min -29 - - ma vout = 1.0 v pull-up current max ioh max - - -23 ma vout = 3.135 v pull-down current min iol min 29 - - ma vout = 1.95 v pull-down current max iol max - - 27 ma vout = 0.4 v rise/fall time min/max between 0.4 v and 2.4 v trf 0.5 - 2.0 ns 20 pf load vdd = vddp=vddf =vddr =3.3v 5 %, vddc, & vddi =2.5v 5 %,, ta = 0oc to +70oc buffer 4 characteristics for pciclk(1:8,f) characteristic symbol min typ max units conditions pull-up current min ioh min -33 - - ma vout = 1.0 v pull-up current max ioh max - - -33 ma vout = 3.135 v pull-down current min iol min 30 - - ma vout = 1.95 v pull-down current max iol max - - 38 ma vout = 0.4 v rise/fall time min/max between 0.4 v and 2.4 v trf 0.5 - 2.0 ns 30 pf load vdd = vddp=vddf =vddr =3.3v 5 %, vddc, & vddi =2.5v 5 %,, ta = 0oc to +70oc
sg577c low emi clock generator for pentium ii systems with power management approved product international microcircuits, inc. 525 los coches st. rev 1.8 2/19/98 milpitas, ca 95035 tel: 408-263-6300 ext. 275 fax 408-263-6571 page 8 of 10 crystal and reference oscillator parameters characteristic symbol min typ max units conditions frequency f o 12.00 14.31818 16.00 mhz tolerence tc - - +/-100 ppm calibration note 1 ts - - +/- 100 ppm stability (ta -10 to +60c) note 1 ta - - 5 ppm aging (first year @ 25c) note 1 mode om - - - parallell resonant pin capacitance cp 5 pf capacitance of xin and xout pins dc bias voltage v bias 0.3vdd vdd/2 0.7vdd v startup time ts - - 30 m s load capacitance cl - 20 - pf note 1 effective series resonant resistance r1 - - 40 ohms power dissipation dl - - 0.10 mw note 1 shunt capacitance co - -- 7 pf x1 and x2 load cl 17 pf internal cr y stal loadin g g apacitors on each pin (to ground) for maximum accurac y ,the total circuit loadin g capacitance should be e q ual to cl. this loadin g capacitance is the effective capacitance across the cr y stal pins and includes the device pin capacitance ( cp ) in parallel with an y circuit traces, the clock generator and any onboard discrete load capacitors. budgeting calculations typical trace capacitance, (< half inch) is 4 pf, load to the crystal is therefore 2.0 pf clock generator internal pin capacitance of 36 pf, load to the crystal is therefore 18.0 pf the total parasitic capacitance would therefore be = 20.0 pf.(matching cl ) note 1: it is recommended but not mandatory that a crystal meets these specifications.
sg577c low emi clock generator for pentium ii systems with power management approved product international microcircuits, inc. 525 los coches st. rev 1.8 2/19/98 milpitas, ca 95035 tel: 408-263-6300 ext. 275 fax 408-263-6571 page 9 of 10 pcb layout suggestion via to vdd plane via to gnd plane void (cut) in power plane 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 v cc v cc (c p u) c 1 fb2 fb1 22uf 22uf c 11 c10 c9 c8 c 7 c6 c3 c4 c5 this is only a layout recommendation for best performance and lower emi. the designer may choose a different approach but c2, c3, c4, c5, c6, c7, c8, c9, and c10 (all are 0.1 uf) should always be used and placed as close to their vdd pins as is physically possible. the topological hookup of c4 with respect to its power and ground vias is especially important. c 2
sg577c low emi clock generator for pentium ii systems with power management approved product international microcircuits, inc. 525 los coches st. rev 1.8 2/19/98 milpitas, ca 95035 tel: 408-263-6300 ext. 275 fax 408-263-6571 page 10 of 10 package drawing and dimensions 48 pin ssop outline dimensions inches millimeters symbol min nom max min nom max a 0.095 0.102 0.110 2.41 2.59 2.79 a 1 0.008 0.012 0.016 0.20 0.31 0.41 a2 0.088 0.090 0.092 2.24 2.29 2.34 b 0.008 0.010 0.0135 0.203 0.254 0.343 c 0.005 - 0.010 0.127 - 0.254 d 0.620 0.625 0.630 15.75 15.88 16.00 e 0.292 0.296 0.299 7.42 7.52 7.59 e 0.025 bsc 0.635 bsc h 0.400 0.406 0.410 10.16 10.31 10.41 l 0.024 0.032 0.040 0.61 0.81 1.02 a0o 5o8o 0o5o8o x 0.085 0.093 0.100 2.16 2.36 2.54 ordering information part number package type production flow IMISG577CYB 48 pin ssop commercial, 0oc to +70oc note: the ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. marking: example: imi sg577cyb date code, lot # IMISG577CYB flow b = commercial, 0oc to + 70oc package y = ssop revision imi device number b e a a 1 a 2 e a l c d h
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