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vcc c bypass 100 nf v supply gnd vout pwmout sensitivity, qvo, and temperature compensation chopper switches r pullup signal recovery pwm frequency trim mismatch compensation pwm carrier generation signal conditioning low-pass filter amp A1359-ds features and benefits ? dual tracking outputs: analog voltage output and pulse width modulated (pwm) output ? matched analog and pwm outputs enable user to detect various output error conditions ? factory-programmed offset, sensitivity, and polarity ? sensitivity temperature coefficient (tc) and qvo/qd temperature coefficient programmed at allegro ? for improved accuracy ? high speed chopping scheme minimizes quiescent voltage output (qvo) drift across temperature ? temperature-stable qvo and sensitivity ? output voltage clamps provide short circuit diagnostic capabilities ? wide ambient temperature range: ?40c to 150c ? immune to mechanical stress ? enhanced emc performance for stringent automotive applications factory-programmed dual output linear hall effect sensor ic with analog and pulse width modulated outputs continued on the next page? package: 8-pin tssop (suffix le) surface mount functional block diagram not to scale A1359 description new applications for linear output hall effect sensors, such as displacement and angular position, require high accuracy in conjunction with redundant outputs. the allegro A1359 programmable, linear, hall effect sensor ic has been designed specifically to achieve both goals. the features associated with this linear device make it ideal for use in automotive and industrial applications requiring high accuracy, and this temperature-stable device operates across an extended temperature range: ?40c to 150c. the accuracy of the device is enhanced via programmability at the allegro factory for optimization of device sensitivity, the quiescent voltage output (qvo: output with no magnetic field), and quiescent duty cycle (qd) for a given application or circuit. the A1359 also allows optimized performance across the entire operating temperature range via programming the temperature coefficients for both sensitivity and qvo/qd at allegro end-of-line test. this ratiometric hall effect sensor ic provides a analog voltage, and a pwm signal with duty cycle, that are proportional to the applied magnetic field. each bicmos monolithic circuit integrates a hall element, temperature-compensating circuitry to reduce the intrinsic sensitivity drift of the hall element, a small-signal high-gain http://www..net/ datasheet pdf - http://www..net/
factory-programmed dual output linear hall effect sensor ic with analog and pulse width modulated outputs A1359 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com absolute maximum ratings characteristic symbol notes rating unit forward supply voltage v cc refer to power derating section 6 v reverse supply voltage v rcc ?0.1 v forward output voltage v out refer to power derating section 7 v reverse output voltage v rout ?0.1 v forward pwm output voltage v pwm refer to power derating section 7 v reverse pwm output voltage v rpwm ?0.1 v output source current i out(source) vout to gnd 2 ma output sink current i out(sink) vcc to vout 10 ma pwm output source current i pwm(source) v pwm > ?0.5 v, t a = 25c ?50 ma pwm output sink current i pwm(sink) internal current limiting is intended to protect the device from momentary short circuits and not intended for continuous operation 25 ma operating ambient temperature t a temperature range l ?40 to 150 oc storage temperature t stg ?65 to 170 oc maximum junction temperature t j (max) 165 oc description (continued) selection guide part number factory programmed output polarity packing* A1359lletr-t forward: output voltage increases with increasing positive (south) applied magnetic field 4000 units / reel A1359lletr-rp-t reverse: output voltage increases with increasing negative (north) applied magnetic field 4000 units / reel *contact allegro for additional packing options amplifier, a clamped low-impedance output stage and a proprietary dynamic offset cancellation technique. the A1359 is provided in an 8-contact surface mount tssop (suffix le) which is lead (pb) free, with 100% matte tin leadframe plating. http://www..net/ datasheet pdf - http://www..net/
factory-programmed dual output linear hall effect sensor ic with analog and pulse width modulated outputs A1359 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com thermal characteristics may require derating at maximum conditions, see application information characteristic symbol test conditions* value unit package thermal resistance r ja on 4-layer pcb based on jedec standard 145 oc/w *additional thermal information available on the allegro website pin-out diagram pwmout vcc nc vout nc gnd nc nc 1 2 3 4 8 7 6 5 terminal list table number name function 1 pwmout open drain pwm output 2 vcc input power supply; tie to gnd with bypass capacitor 3 nc no connect, tie to either gnd or vcc 4 vout output signal 5 nc no connect, tie to either gnd or vcc 6 nc no connect, tie to either gnd or vcc 7 gnd device ground 8 nc no connect, tie to either gnd or vcc 20 40 60 80 100 120 140 160 180 temperature, t a (c) power dissipation, p d (mw) 0 300 400 200 100 600 500 800 700 900 1000 power dissipation versus ambient temperature (r q ja = 145 oc/w) http://www..net/ datasheet pdf - http://www..net/
operating characteristics valid over full operating temperature range, t a , c bypass = 0.1 f , v cc = 5 v, unless otherwise noted characteristics symbol test conditions min. typ. max. unit 1 electrical characteristics supply voltage v cc 4.5 5.0 5.5 v undervoltage threshold 2 v uvlohi t a = 25c (device powers on) ? ? 3 v v uvlolow t a = 25c (device powers off) 2.5 ? ? v supply current i cc v cc = 5 v ? 10 12 ma supply zener clamp voltage v z t a = 25c, i cc = 20 ma 6 8.3 ? v internal bandwidth 3 bw i small signal, ?3 db ? 2 ? khz chopping frequency 3,4 f c t a = 25c ? 400 ? khz analog output characteristics output referred noise 3 v n t a = 25c, c bypass = 0.1 f, sens = 5 mv/g, no load on vout ? 6 ? mv(p-p) input referred rms noise density 3 v nrms t = 25c, c bypass = open, no load on vout, f << bw i ? 1.9 ? mg/ hz dc output resistance 3 r out ?< 1? output load resistance 3 r l vout to gnd 4.7 ? ? k output load capacitance 3 c l vout to gnd ? ? 10 nf analog output current limit i limit(alg) r pullup = 0 10 ? 80 ma output voltage clamp 5 v clph t a = 25c, b = +350 g, r l = 10 k (vout to gnd) 4.25 4.5 4.65 v v clpl t a = 25c, b = ?350 g, r l = 10 k (vout to vcc) 0.40 0.5 0.70 v response time 3 t response_ vout impulse magnetic field of 300 g ? ? 500 s settling time 3 t settlevout t a = 25c, primary overload > 5000 g ? ? 750 s power-on time for analog 3 t povout t a = 25c, c l (probe) = 10 pf, on vout ? 250 ? s delay to clamp for analog 3 t clpvout t a = 25c, c l = 10 nf, on vout ? 30 ? s pwm output characteristics pwmout saturation voltage v sat i pwmout(sink) 20 ma, pwmout transistor on ? ? 0.6 v i pwmout(sink) 10 ma, pwmout transistor on ? ? 0.5 v pwmout current limit i limit r pullup = 0 30 60 110 ma pwmout leakage current i leak vcc = gnd, 0 v v pwmout 5 v, pwmout transistor off ? 0.1 10 a pwmout zener clamp voltage v zout i pwmout(sink) = 10 ma, t a = 25oc 28 ? ? v pwmout rise time 3 t r t a = 25c, r pullup = 2 k , c l = 20 pf ? 3 ? s pwmout fall time 3 t f t a = 25c, r pullup = 2 k , c l = 20 pf ? 3 ? s power-on time for pwm 3 t popwm t a = 25c, c l (probe) = 10 pf, on pwmout ? 500 ? s delay to clamp for pwm 3 t clppwm t a = 25c, c l = 10 nf, on pwmout ? 250 ? s response time 3 t response_ pwm t a = 25c, impulse magnetic field of 300 g ? ? 1.5 ms settling time 3 t settlepwm t a = 25c, primary overload > 5000 g ? ? 2.25 ms factory-programmed dual output linear hall effect sensor ic with analog and pulse width modulated outputs A1359 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com continued on the next page? http://www..net/ datasheet pdf - http://www..net/
pwm output characteristics (continued) load resistance 3,6 r pullup pwmout to vcc 2000 ? ? load capacitance 3,6 c l pwmout to gnd ? ? 10 nf duty cycle jitter 3 jitter pwm measured over 1000 pwm output clock periods, 3 sigma values, sens = 9 mv/g ? 0.18 ? %d quiescent voltage output (qvo) quiescent voltage output v out(q) t a = 25c 2.45 2.5 2.55 v quiescent voltage output equivalent pwm d (q) t a = 25c, v cc = 4.5 to 5.5 v 49 50 51 %d pwm carrier frequency carrier frequency f pwm t a = 25c 3.6 4 4.4 khz sensitivity sensitivity temperature coefficient tc sens programmed at t a = 150c, calculated relative to sens at 25c 0.08 0.12 0.16 %/c analog sensitivity 7 sen A1359lletr-t b = 125 g, t a = 25c 8.73 9.0 9.27 mv/g A1359lletr-rp-t b = 125 g, t a = 25c ?9.27 ?9.0 ?8.73 mv/g error components pwm to analog output mismatch 8 v outerr 1.75 v < v out < 3.25 v ?57.4 ? +57.4 mv v out = 1.25 v, v out = 3.75 v ?85 ? +85 mv linearity sensitivity error 9 lin err ? 0.5 ? % symmetry sensitivity error 9 sym err ? 0.5 ? % ratiometry quiescent voltage output error 10 rat vout(q) across supply voltage range, (relative to v cc = 5 v) ? 0.5 ? % ratiometry sensitivity error 9 rat sens across supply voltage range, (relative to v cc = 5 v) ? 0.5 ? % ratiometry clamp error 10 rat voutclp t a = 25c, across supply voltage range, (relative to v cc = 5 v) ? 0.5 ? % quiescent voltage output drift through temperature range ? v out(q) t a =150c ?17 ? +17 mv sensitivity drift due to package hysteresis ? sens pkg t a = 25c, after temperature cycling ? 2 ? % 1 1 g (gauss) = 0.1 mt (millitesla). 2 at power-up, the output is held low until v cc exceeds v uvlohi . when the device reaches the operational power level, the output remains valid until v cc drops below v uvlolo , when the output is pulled low. 3 determined by design and characterization, not evaluated at final test. 4 f c varies as much as approximately 20% across the full operating ambient temperature range and process. 5 v clpl and v clph scale with v cc , due to ratiometry. 6 load capacitance and resistance directly effects the rise time of the pwm output by t r = 0.35 2 r l c l . 7 room temperature sensitivity can drift, sens life , by an additional 3% (typical worst case) over the life of the product. 8 see characteristic definitions section. 9 applicable to both analog and pwm channels. tested at allegro factory for only the analog channel, and determined by design and characterization for the pwm channel. 10 applies only to the analog channel. operating characteristics (continued) valid over full operating temperature range, t a , c bypass = 0.1 f , v cc = 5 v, unless otherwise noted characteristics symbol test conditions min. typ. max. unit 1 factory-programmed dual output linear hall effect sensor ic with analog and pulse width modulated outputs A1359 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com http://www..net/ datasheet pdf - http://www..net/
factory-programmed dual output linear hall effect sensor ic with analog and pulse width modulated outputs A1359 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com characteristic definitions figure 1. definition of analog power-on time, t povout figure 2. definition of pwm power-on time, t popwm figure 3. definition of response time for pwm output v +t v cc v cc (min) v out 90% v out 0 t 1 = time at which power supply reaches minimum specified operating voltage t 2 = time at which output voltage settles within 10% of its steady state value under an applied magnetic field t 1 t 2 t povout v cc (typ) time time v cc (min) t popwm first valid duty cycle v cc v pwmout time b-field pwmout propagation delay 1ms a b adc bdc adc ? dc corresponds to the a field bdc ? dc corresponds to the b field c response time 0.9 c cdc cdc ? dc corresponds to the 0 .9 c field power-on time when the supply is ramped to its operating voltage, the device requires a finite time to power its internal components before supplying a valid pwm output duty-cycle. power-on time for analog output, t povout , is defined as the time it takes for the output voltage to settle within 10% of its steady state value after the power supply has reached its minimum speci- fied operating voltage, v cc(min) . (see figure 1.) power-on time is specified in a different way for the pwm out- put than the analog output. for the pwm output, the power-on time, t popwm , is defined as the time it takes for the duty cycle to settle within 10% of the target steady state value from the time the power supply has reached the minimum specified operating voltage, v cc(min) . (see figure 2.) response time the time interval, t responsepwm or t responsevout , between: a) when the applied magnetic field reaches 90% of its final value, and b) when the sensor ic reaches 90% of its output corresponding to the applied magnetic field (pwm duty cycle or analog v out ). figure 3 illustrates an example with the pwm output. response time is conceptually the same for the analog output. http://www..net/ datasheet pdf - http://www..net/
factory-programmed dual output linear hall effect sensor ic with analog and pulse width modulated outputs A1359 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com delay to clamp a large magnetic input step may cause the clamp to overshoot its steady state value. the delay to clamp, t clpvout , is defined as the time it takes for the output voltage to settle within 1% of its steady state value after initially passing through its steady state voltage. this is conceptually the same for the pwm output duty cycle settling to the steady state value. (see figure 4.) quiescent voltage output in the quiescent state (no signifi- cant magnetic field: b = 0 g), the analog output, v out , is ratio- metric to the supply voltage, v cc , throughout the entire operating range of v cc . the pwm output, v pwmout , by virtue of being a % duty-cycle will remain at 50% nominal throughout the entire v cc operating range (4.5 to 5.5 v). quiescent output drift through temperature range due to internal component tolerances and thermal considerations, the quiescent voltage output, v out(q) , may drift from its nominal value across the operating ambient temperature, t a . for purposes of specification, the quiescent voltage output drift through temperature range, ? v out(q) (mv), is defined as: v out(q)(ta) ? v out(q)(25c) ? v out(q) = (1) sensitivity assuming the sensitivity of the device is positive (positive polarity: A1359lletr-t), the presence of a south- polarity magnetic field perpendicular to the branded surface of the package face increases the output voltage from its quiescent value toward the supply voltage rail. the amount of the output voltage increase is proportional to the magnitude of the magnetic field applied. conversely, the application of a north polarity field decreases the output voltage from its quiescent value. for the case of the reverse polarity device (A1359lletr-rp-t), the presence of a south-polarity magnetic field perpendicular to the branded surface of the package face decreases the output volt- age from its quiescent value toward the ground rail. the amount of the output voltage decrease is proportional to the magnitude of the magnetic field applied. conversely, the application of a north polarity field increases the output voltage from its quiescent value. this proportionality is specified as the magnetic sensitiv- ity, sens (mv/g), of the device and is defined as: v out(bpos) ? v out(bneg) bpos ? bneg sens = (2) where bpos and bneg are two magnetic fields with opposite polarities. sensitivity temperature coefficient device sensitivity changes as temperature changes, with respect to its programmed sensitivity temperature coefficient, tc sens . tc sens is pro- grammed at 150c, and calculated relative to the nominal sensitivity programming temperature of 25c. tc sens (%/c) is defined as: sens t2 ? sens t1 sens t1 t2?t1 1 tc sens = 100% ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (3) where t1 is the nominal sens programming temperature of 25c, and t2 is the tc sens programming temperature of 150c. the ideal value of sens through the full ambient temperature range, sens ideal(ta) , is defined as: sens t1 [100% +tc sens ( t a ? t1 )] sens ideal(ta) = (4) sensitivity drift due to package hysteresis package stress and relaxation can cause the device sensitivity at t a = 25c to change during and after temperature cycling. this change in sensitivity follows a hysteresis curve. for purposes of specifica- tion, the sensitivity drift due to package hysteresis, ? sens pkg , is defined as: sens (25c)2 ? sens (25c)1 sens (25c)1 ? sens pkg = 100 (%) (5) figure 4. definition of delay to clamp time ( s) magnetic input signal magnetic input signal t 1 = time at which output voltage initially reaches steady state clamp voltage t 2 = time at which output voltage settles to within 1% of steady state clamp voltage v clp(high) t 1 t 2 t clppwm or t clpvout v pwmout or v out device output, v pwmout or v out (v) http://www..net/ datasheet pdf - http://www..net/
factory-programmed dual output linear hall effect sensor ic with analog and pulse width modulated outputs A1359 8 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com where sens (25c)1 is the programmed value of sensitivity at t a = 25c, and sens (25c)2 is the value of sensitivity at t a = 25c, after temperature cycling t a up to 150c, down to ?40c, and back to up 25c. linearity sensitivity error the A1359 is designed to provide linear output in response to a ramping applied magnetic field. consider two magnetic fields, b1 and b2. ideally, the sensitivity of a device is the same for both fields, for a given supply voltage and temperature. linearity error is present when there is a differ- ence between the sensitivities measured at b1 and b2. linearity sensitivity error is calculated separately for the positive (lin errpos ) and negative (lin errneg ) applied magnetic fields. linearity error (%) is measured and defined as: sens bpos2 sens bpos1 sens bneg2 sens bneg1 1? lin errpos = 100 (%) 100 (%) ? ? ? ? ? ? ? ? 1? lin errneg = ? ? ? ? ? ? ? ? (6) where: |v out(b x ) ? v out(q) | b x sens b x = (7) and bposx and bnegx are positive and negative magnetic fields, with respect to the quiescent voltage output such that b pos2 > b pos1 and b neg2 > b neg1 . then: lin err max( | lin errpos | , |lin errneg |) = (8) clamping range the output voltage clamps, v clph and v clpl , limit the operating magnetic range of the applied field in which the device provides a linear output. the maximum posi- tive and negative applied magnetic fields in the operating range can be calculated: v clp(high) ? v out(q) sens |bpos(max)| = v out(q) ? v clp(low) sens |bneg(max)| = (9) symmetry sensitivity error the magnetic sensitivity of the A1359 device is constant for any two applied magnetic fields of equal magnitude and opposite polarities. symmetry sensitivity error, sym err (%), is measured and defined as: sens bpos sens bneg 1? sym err = 100 (%) ? ? ? ? ? ? ? ? (10) where sens bx is as defined in equation 7, and bpos and bneg are positive and negative magnetic fields such that |b pos | = |b neg |. ratiometry error the A1359 provides a ratiometric output. this means that the quiescent voltage output, v out(q) , mag- netic sensitivity, sens, and clamp voltage, v clph and v clpl , are proportional to the supply voltage, v cc . in other words, when the supply voltage increases or decreases by a certain percent- age, each characteristic also increases or decreases by the same percentage. error is the difference between the measured change in the supply voltage relative to 5 v, and the measured change in each characteristic. the ratiometric error in quiescent voltage output, rat vout(q) (%), for a given supply voltage, v cc , is defined as: v out(q)(vcc) / v out(q)(5v) v cc / 5 v 1? rat errvout(q) = 100 (%) ? ? ? ? ? ? ? ? (11) the ratiometric error in magnetic sensitivity, rat sens (%), for a given supply voltage, v cc , is defined as: sens (vcc) / sens (5v) v cc / 5 v 1? rat errsens = 100 (%) (12) the ratiometric error in the clamp voltages, rat voutclp (%), for a given supply voltage, v cc , is defined as: v clp(vcc) / v clp(5v) v cc / 5 v 1? rat voutclp = 100 (%) (13) where v clp is either v clph or v clpl . note: equations 11 and 13 apply to the analog channel (v out ), only. recall that for the pwm output, the 0 g output is 50% from 4.5 to 5.5 v. however, as sensitivity is ratiometric with v cc for both analog and pwm channels, equation 12 applies to both the analog and the pwm channels. http://www..net/ datasheet pdf - http://www..net/
factory-programmed dual output linear hall effect sensor ic with analog and pulse width modulated outputs A1359 9 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com duty cycle jitter the duty cycle of the pwm output may vary slightly over time despite the presence of a constant applied mag- netic field and a constant carrier frequency, f pwm , for the pwm signal. this phenomenon is known as jitter, jitter pwm (%) , and is defined as: jitter pwm = d b (max) ? d b (min) 2 (14) where d b (max) and d b (min) are the maximum and minimum duty cycles, measured in 1000 pwm clock periods, in a constant applied magnetic field. undervoltage lockout the A1359 features an undervolt- age lockout function that ensures that the device will output a valid signal when v cc is above a certain threshold, v uvlohi , and remains valid until v cc falls below a lower threshold, v uvlolow . the undervoltage lockout feature provides a hyster- esis of operation to eliminate indeterminate output states. the output of the A1359 is held low (gnd) until v cc exceeds v uvlohi . when v cc exceeds v uvlohi , the device powers-up and the output provides a ratiometric output voltage proportional to the input magnetic signal, and v cc . if v cc should drop back down below v uvlolow for more than t uvlo after the device is powered-up, the output would be pulled low. (see figure 5.) pwm to analog output mismatch when comparing the pwm output to the analog output for channel mismatch, the following equation is used to convert pwm (% d, duty cycle) to voltage (v): v pwmout = d (q) + d (field) = v out(q) 20.0 % d / v + v out(b) 21.0% d / v (15) where: d (q) is the quiescent pwm signal with no input field (b = 0 g), and d (field) is the pwm signal in response to the input magnetic field. in other words, the product of pwm sensitivity (%d/g) and input magnetic field (g). (see figure 6.) figure 5. uvlo operation v pwmout or v out t uvlo v cc v uvlohi v uvlolo time figure 6. definition of pwm to analog output mismatch, v outerr +v out (v) +v pwmout (v) digital channel analog channel v outerr = 85 mv v outerr = 85 mv 1.25 1.25 1.75 1.75 3.75 3.25 3.25 3.75 v outerr = 57.4 mv http://www..net/ datasheet pdf - http://www..net/
factory-programmed dual output linear hall effect sensor ic with analog and pulse width modulated outputs A1359 10 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com typical application circuit chopper stabilization technique A1359 vout gnd 0.1 5 v f r l c l pwmout vcc 4.7 nf r pullup optional: recommended for emc robustness amp regulator clock/logic hall element tuned filter anti-aliasing lp filter when using hall-effect technology, a limiting factor for switchpoint accuracy is the small signal voltage developed across the hall element. this voltage is disproportionally small relative to the offset that can be produced at the output of the hall sensor ic. this makes it difficult to process the signal while maintain- ing an accurate, reliable output over the specified operating temperature and voltage ranges. chopper stabilization is a unique approach used to minimize hall offset on the chip. allegro employs a patented technique to remove key sources of the out- put drift induced by thermal and mechanical stresses. this offset reduction technique is based on a signal modulation-demodula- tion process. the undesired offset signal is separated from the magnetic field-induced signal in the frequency domain, through modulation. the subsequent demodulation acts as a modulation process for the offset, causing the magnetic field-induced signal to recover its original spectrum at base band, while the dc offset becomes a high-frequency signal. the magnetic-sourced signal then can pass through a low-pass filter, while the modulated dc offset is suppressed. in addition to the removal of the thermal and stress related offset, this novel technique also reduces the amount of thermal noise in the hall sensor while completely removing the modulated residue resulting from the chopper operation. the chopper stabilization technique uses a high frequency sampling clock. for demodulation process, a sample-and-hold technique is used. this high-frequency operation allows a greater sampling rate, which results in higher accuracy and faster signal-processing capability. this approach desensitizes the chip to the effects of thermal and mechanical stresses, and produces devices that have extremely stable quiescent hall output voltages and precise recoverability after temperature cycling. this technique is made possible through the use of a bicmos process, which allows the use of low-offset, low-noise amplifiers in combination with high- density logic integration and sample-and-hold circuits. figure 7. typical application circuit figure 8. concept of chopper stabilization technique http://www..net/ datasheet pdf - http://www..net/
factory-programmed dual output linear hall effect sensor ic with analog and pulse width modulated outputs A1359 11 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package le, 8-pin tssop a 1.10 max 0.15 0.05 0.30 0.19 0.20 0.09 8o 0o 0.60 1.00 ref c seating plane A1359lletr-t A1359lletr-rp-t c 0.10 8x 0.65 bsc 0.25 bsc +0.15 ?0.10 2 1 8 3.000.10 4.400.10 6.40 bsc gauge plane seating plane a terminal #1 mark area b for reference only; not for tooling use (reference mo-153 aa) dimensions in millimeters dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown 6.10 0.65 0.45 1.70 8 2 1 reference land pattern layout (reference ipc7351 sop65p640x110-8m); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias can improve thermal dissipation (reference eia/jedec standard jesd51-5) pcb layout reference view b 1.50 2.20 d d d d branding scale and appearance at supplier discretion hall element, not to scale branded face e active area depth 0.36 mm ref 359 1 yyww 59r 1 yyww c branding reference view top line is device designator = supplier emblem y = last two digits of year of manufacture w = week of manufacture e http://www..net/ datasheet pdf - http://www..net/
factory-programmed dual output linear hall effect sensor ic with analog and pulse width modulated outputs A1359 12 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com for the latest version of this document, visit our website: www.allegromicro.com copyright ?2011-2013, allegro microsystems, inc. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes n o re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. http://www..net/ datasheet pdf - http://www..net/

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