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ltc2410 1 the ltc ? 2410 is a 2.7v to 5.5v micropower 24-bit differential ds analog to digital converter with an inte- grated oscillator, 2ppm inl and 0.16ppm rms noise. it uses delta-sigma technology and provides single cycle settling time for multiplexed applications. through a single pin, the ltc2410 can be configured for better than 110db input differential mode rejection at 50hz or 60hz 2%, or it can be driven by an external oscillator for a user defined rejection frequency. the internal oscillator re- quires no external frequency setting components. the converter accepts any external differential reference voltage from 0.1v to v cc for flexible ratiometric and remote sensing measurement configurations. the full- scale differential input range is from C 0.5v ref to 0.5v ref . the reference common mode voltage, v refcm , and the input common mode voltage, v incm , may be indepen- dently set anywhere within the gnd to v cc range of the ltc2410. the dc common mode input rejection is better than 140db. the ltc2410 communicates through a flexible 3-wire digital interface which is compatible with spi and microwire tm protocols. n direct sensor digitizer n weight scales n direct temperature measurement n gas analyzers n strain-gage transducers n instrumentation n data acquisition n industrial process control n 6-digit dvms , ltc and lt are registered trademarks of linear technology corporation. n differential input and differential reference with gnd to v cc common mode range n 2ppm inl, no missing codes n 2.5ppm full-scale error n 0.1ppm offset n 0.16ppm noise n single conversion settling time for multiplexed applications n internal oscillatorno external components required n 110db min, 50hz or 60hz notch filter n 24-bit adc in narrow ssop-16 package (so-8 footprint) n single supply 2.7v to 5.5v operation n low supply current (200 m a) and auto shutdown n fully differential version of ltc2400 24-bit no latency ds tm adc with differential input and differential reference no latency ds is a trademark of linear technology corporation. microwire is a trademark of national semiconductor corporation. v cc f o ref + ref sck in + in sdo gnd cs 214 3 4 13 5 6 12 1, 7, 8, 9, 10, 15, 16 11 reference voltage 0.1v to v cc analog input range 0.5v ref to 0.5v ref = internal osc/50hz rejection = external clock source = internal osc/60hz rejection 3-wire spi interface 1 f 2.7v to 5.5v ltc2410 2410 ta01 v cc ltc2410 in + ref + v cc ref v cc gnd f o in 1 f sdo 3-wire spi interface sck 2410 ta02 cs 12 3 2 1, 7, 8 9, 10, 15, 16 14 5 6 4 13 11 bridge impedance 100 to 10k applicatio s u features descriptio u typical applicatio s u
ltc2410 2 absolute axi u rati gs w ww u package/order i for atio uu w electrical characteristics (notes 1, 2) order part number consult factory for parts specified with wider operating temperature ranges. supply voltage (v cc ) to gnd .......................C 0.3v to 7v analog input pins voltage to gnd .................................... C 0.3v to (v cc + 0.3v) reference input pins voltage to gnd .................................... C 0.3v to (v cc + 0.3v) digital input voltage to gnd ........ C 0.3v to (v cc + 0.3v) digital output voltage to gnd ..... C 0.3v to (v cc + 0.3v) operating temperature range ltc2410c ............................................... 0 c to 70 c ltc2410i ............................................ C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c t jmax = 125 c, q ja = 110 c/w ltc2410cgn LTC2410IGN parameter conditions min typ max units resolution (no missing codes) 0.1v v ref v cc , C0.5 ? v ref v in 0.5 ? v ref , (note 5) l 24 bits integral nonlinearity 5v v cc 5.5v, ref + = 2.5v, ref C = gnd, v incm = 1.25v, (note 6) 1 ppm of v ref 5v v cc 5.5v, ref + = 5v, ref C = gnd, v incm = 2.5v, (note 6) l 2 14 ppm of v ref ref + = 2.5v, ref C = gnd, v incm = 1.25v, (note 6) 5 ppm of v ref offset error 2.5v ref + v cc , ref C = gnd, l 0.5 2.5 m v gnd in + = in C v cc , (note 14) offset error drift 2.5v ref + v cc , ref C = gnd, 10 nv/ c gnd in + = in C v cc positive full-scale error 2.5v ref + v cc , ref C = gnd, l 2.5 12 ppm of v ref in + = 0.75ref + , in C = 0.25 ? ref + positive full-scale error drift 2.5v ref + v cc , ref C = gnd, 0.03 ppm of v ref / c in + = 0.75ref + , in C = 0.25 ? ref + negative full-scale error 2.5v ref + v cc , ref C = gnd, l 2.5 12 ppm of v ref in + = 0.25 ? ref + , in C = 0.75 ? ref + negative full-scale error drift 2.5v ref + v cc , ref C = gnd, 0.03 ppm of v ref / c in + = 0.25 ? ref + , in C = 0.75 ? ref + total unadjusted error 5v v cc 5.5v, ref + = 2.5v, ref C = gnd, v incm = 1.25v 3 ppm of v ref 5v v cc 5.5v, ref + = 5v, ref C = gnd, v incm = 2.5v 3 ppm of v ref ref + = 2.5v, ref C = gnd, v incm = 1.25v, (note 6) 4 ppm of v ref output noise 5v v cc 5.5v, ref + = 5v, ref C = gnd, 0.8 m v rms gnd in C = in + v cc , (note 13) the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (notes 3, 4) gn part marking 2410 2410i top view gn package 16-lead plastic ssop 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 gnd v cc ref + ref in + in gnd gnd gnd gnd f o sck sdo cs gnd gnd
ltc2410 3 symbol parameter conditions min typ max units in + absolute/common mode in + voltage l gnd C 0.3v v cc + 0.3v v in C absolute/common mode in C voltage l gnd C 0.3v v cc + 0.3v v v in input differential voltage range l Cv ref /2 v ref /2 v (in + C in C ) ref + absolute/common mode ref + voltage l 0.1 v cc v ref C absolute/common mode ref C voltage l gnd v cc C 0.1v v v ref reference differential voltage range l 0.1 v cc v (ref + C ref C ) c s (in + )in + sampling capacitance 18 pf c s (in C )in C sampling capacitance 18 pf c s (ref + )ref + sampling capacitance 18 pf c s (ref C )ref C sampling capacitance 18 pf i dc_leak (in + )in + dc leakage current cs = v cc , in + = gnd l C10 1 10 na i dc_leak (in C )in C dc leakage current cs = v cc , in C = gnd l C10 1 10 na i dc_leak (ref + )ref + dc leakage current cs = v cc , ref + = 5v l C10 1 10 na i dc_leak (ref C )ref C dc leakage current cs = v cc , ref C = gnd l C10 1 10 na the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (notes 3, 4) parameter conditions min typ max units input common mode rejection dc 2.5v ref + v cc , ref C = gnd, l 130 140 db gnd in C = in + v cc input common mode rejection 2.5v ref + v cc , ref C = gnd, l 140 db 60hz 2% gnd in C = in + v cc , (note 7) input common mode rejection 2.5v ref + v cc , ref C = gnd, l 140 db 50hz 2% gnd in C = in + v cc , (note 8) input normal mode rejection (note 7) l 110 140 db 60hz 2% input normal mode rejection (note 8) l 110 140 db 50hz 2% reference common mode 2.5v ref + v cc , gnd ref C 2.5v, l 130 140 db rejection dc v ref = 2.5v, in C = in + = gnd power supply rejection, dc ref + = 2.5v, ref C = gnd, in C = in + = gnd 120 db power supply rejection, 60hz 2% ref + = 2.5v, ref C = gnd, in C = in + = gnd, (note 7) 120 db power supply rejection, 50hz 2% ref + = 2.5v, ref C = gnd, in C = in + = gnd, (note 8) 120 db co verter characteristics u a alog i put a u d refere ce uu u
ltc2410 4 symbol parameter conditions min typ max units v cc supply voltage l 2.7 5.5 v i cc supply current conversion mode cs = 0v (note 12) l 200 300 m a sleep mode cs = v cc (note 12) l 20 30 m a the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) symbol parameter conditions min typ max units v ih high level input voltage 2.7v v cc 5.5v l 2.5 v cs, f o 2.7v v cc 3.3v 2.0 v v il low level input voltage 4.5v v cc 5.5v l 0.8 v cs, f o 2.7v v cc 5.5v 0.6 v v ih high level input voltage 2.7v v cc 5.5v (note 9) l 2.5 v sck 2.7v v cc 3.3v (note 9) 2.0 v v il low level input voltage 4.5v v cc 5.5v (note 9) l 0.8 v sck 2.7v v cc 5.5v (note 9) 0.6 v i in digital input current 0v v in v cc l C10 10 m a cs, f o i in digital input current 0v v in v cc (note 9) l C10 10 m a sck c in digital input capacitance 10 pf cs, f o c in digital input capacitance (note 9) 10 pf sck v oh high level output voltage i o = C800 m a l v cc C 0.5v v sdo v ol low level output voltage i o = 1.6ma l 0.4v v sdo v oh high level output voltage i o = C800 m a (note 10) l v cc C 0.5v v sck v ol low level output voltage i o = 1.6ma (note 10) l 0.4v v sck i oz hi-z output leakage l C10 10 m a sdo digital i puts a d digital outputs uu power require e ts w u
ltc2410 5 note 1: absolute maximum ratings are those values beyond which the life of the device may be impaired. note 2: all voltage values are with respect to gnd. note 3: v cc = 2.7 to 5.5v unless otherwise specified. v ref = ref + C ref C , v refcm = (ref + + ref C )/2; v in = in + C in C , v incm = (in + + in C )/2. note 4: f o pin tied to gnd or to v cc or to external conversion clock source with f eosc = 153600hz unless otherwise specified. note 5: guaranteed by design, not subject to test. note 6: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 7: f o = 0v (internal oscillator) or f eosc = 153600hz 2% (external oscillator). note 8: f o = v cc (internal oscillator) or f eosc = 128000hz 2% (external oscillator). note 9: the converter is in external sck mode of operation such that the sck pin is used as digital input. the frequency of the clock signal driving sck during the data output is f esck and is expressed in khz. note 10: the converter is in internal sck mode of operation such that the sck pin is used as digital output. in this mode of operation the sck pin has a total equivalent load capacitance c load = 20pf. note 11: the external oscillator is connected to the f o pin. the external oscillator frequency, f eosc , is expressed in khz. note 12: the converter uses the internal oscillator. f o = 0v or f o = v cc . note 13: the output noise includes the contribution of the internal calibration operations. note 14: guaranteed by design and test correlation. symbol parameter conditions min typ max units f eosc external oscillator frequency range l 2.56 2000 khz t heo external oscillator high period l 0.25 390 m s t leo external oscillator low period l 0.25 390 m s t conv conversion time f o = 0v l 130.86 133.53 136.20 ms f o = v cc l 157.03 160.23 163.44 ms external oscillator (note 11) l 20510/f eosc (in khz) ms f isck internal sck frequency internal oscillator (note 10) 19.2 khz external oscillator (notes 10, 11) f eosc /8 khz d isck internal sck duty cycle (note 10) l 45 55 % f esck external sck frequency range (note 9) l 2000 khz t lesck external sck low period (note 9) l 250 ns t hesck external sck high period (note 9) l 250 ns t dout_isck internal sck 32-bit data output time internal oscillator (notes 10, 12) l 1.64 1.67 1.70 ms external oscillator (notes 10, 11) l 256/f eosc (in khz) ms t dout_esck external sck 32-bit data output time (note 9) l 32/f esck (in khz) ms t 1 cs to sdo low z l 0 200 ns t2 cs - to sdo high z l 0 200 ns t3 cs to sck (note 10) l 0 200 ns t4 cs to sck - (note 9) l 50 ns t kqmax sck to sdo valid l 220 ns t kqmin sdo hold after sck (note 5) l 15 ns t 5 sck set-up before cs l 50 ns t 6 sck hold after cs l 50 ns the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) ti i g characteristics w u
ltc2410 6 typical perfor a ce characteristics uw total unadjusted error vs temperature (v cc = 2.7v, v ref = 2.5v) total unadjusted error vs temperature (v cc = 5v, v ref = 2.5v) total unadjusted error vs temperature (v cc = 5v, v ref = 5v) integral nonlinearity vs temperature (v cc = 2.7v, v ref = 2.5v) integral nonlinearity vs temperature (v cc = 5v, v ref = 2.5v) integral nonlinearity vs temperature (v cc = 5v, v ref = 5v) noise histogram (output rate = 52.5hz, v cc = 5v, v ref = 5v) noise histogram (output rate = 22.5hz, v cc = 5v, v ref = 5v) noise histogram (output rate = 7.5hz, v cc = 5v, v ref = 5v) v in (v) 2.5 2 1.5 1 0.5 0 0.5 1 1.5 2 2.5 tue (ppm of v ref ) 2410 g01 1.5 1.0 0.5 0 0.5 1.0 1.5 v cc = 5v ref + = 5v ref = gnd v ref = 5v v incm = 2.5v f o = gnd t a = 90 c t a = 25 c t a = 45 c v in (v) ? 0.5 0 0.5 1 tue (ppm of v ref ) 2410 g02 1.5 1.0 0.5 0 0.5 1.0 1.5 v cc = 5v ref + = 2.5v ref = gnd v ref = 2.5v v incm = 1.25v f o = gnd t a = 90 c t a = 25 c t a = 45 c v in (v) ? 0.5 0 0.5 1 tue (ppm of v ref ) 2410 g03 10 8 6 4 2 0 ? ? ? ? ?0 v cc = 2.7v ref + = 2.5v ref = gnd v ref = 2.5v v incm = 1.25v f o = gnd t a = 90 c t a = 25 c t a = 45 c v in (v) 2.5 2 1.5 1 0.5 0 0.5 1 1.5 2 2.5 inl error (ppm of v ref ) 2410 g04 1.5 1.0 0.5 0 0.5 1.0 1.5 v cc = 5v ref + = 5v ref = gnd v ref = 5v v incm = 2.5v f o = gnd t a = 45 c t a = 25 c t a = 90 c v in (v) ? 0.5 0 0.5 1 inl error (ppm of v ref ) 2410 g05 1.5 1.0 0.5 0 0.5 1.0 1.5 v cc = 5v ref + = 2.5v ref = gnd v ref = 2.5v v incm = 1.25v f o = gnd t a = 25 c t a = 45 c t a = 90 c v in (v) ? 0.5 0 0.5 1 inl error (ppm of v ref ) 2410 g06 10 8 6 4 2 0 ? ? ? ? ?0 v ref = 2.5v v incm = 1.25v f o = gnd v cc = 2.7v ref + = 2.5v ref = gnd t a = 25 c t a = 45 c t a = 90 c output code (ppm of v ref ) ?.8 ?.6 ?.4 ?.2 0 0.2 0.4 0.6 0.8 number of readings (%) 2410 g07 12 10 8 6 4 2 0 10,000 consecutive readings v cc = 5v v ref = 5v v in = 0v ref + = 5v ref = gnd in + = 2.5v in = 2.5v f o = gnd t a = 25 c gaussian distribution m = 0.105ppm s = 0.153ppm output code (ppm of v ref ) ?.8 ?.6 ?.4 ?.2 0 0.2 0.4 0.6 0.8 number of readings (%) 2410 g08 12 10 8 6 4 2 0 10,000 consecutive readings v cc = 5v v ref = 5v v in = 0v ref + = 5v ref = gnd in + = 2.5v in = 2.5v f o = 460800hz t a = 25 c gaussian distribution m = 0.067ppm s = 0.151ppm output code (ppm of v ref ) 9.8 9.4 ? 8.6 8.2 7.8 7.4 7 6.6 number of readings (%) 2410 g09 12 10 8 6 4 2 0 10,000 consecutive readings v cc = 5v v ref = 5v v in = 0v ref + = 5v ref = gnd in + = 2.5v in = 2.5v f o = 1075200hz t a = 25 c gaussian distribution m = 8.285ppm s = 0.311ppm
ltc2410 7 typical perfor a ce characteristics uw output code (ppm of v ref ) 1.6 0.8 0 0.8 1.6 number of readings (%) 2410 g10 12 10 8 6 4 2 0 10,000 consecutive readings v cc = 5v v ref = 2.5v v in = 0v ref + = 2.5v ref = gnd in + = 1.25v in = 1.25v f o = gnd t a = 25 c gaussian distribution m = 0.033ppm s = 0.293ppm output code (ppm of v ref ) 1.6 1.2 0.8 0.4 0 0.4 0.8 1.2 1.6 number of readings (%) 2410 g11 12 10 8 6 4 2 0 10,000 consecutive readings v cc = 5v v ref = 2.5v v in = 0v ref + = 2.5v ref = gnd in + = 1.25v in = 1.25v f o = 460800hz t a = 25 c gaussian distribution m = 0.014ppm s = 0.292ppm output code (ppm of v ref ) 5.5 5.1 4.7 4.3 3.9 3.5 3.1 2.7 2.3 number of readings (%) 2410 g12 12 10 8 6 4 2 0 10,000 consecutive readings v cc = 5v v ref = 2.5v v in = 0v ref + = 2.5v ref = gnd in + = 1.25v in = 1.25v f o = 1075200hz t a = 25 c gaussian distribution m = 3.852ppm s = 0.326ppm output code (ppm of v ref ) 1.6 1.2 0.8 0.4 0 0.4 0.8 1.2 1.6 number of readings (%) 2410 g13 12 10 8 6 4 2 0 10,000 consecutive readings v cc = 2.7v v ref = 2.5v v in = 0v ref + = 2.5v ref = gnd in + = 1.25v in = 1.25v f o = gnd t a = 25 c gaussian distribution m = 0.079ppm s = 0.298ppm output code (ppm of v ref ) 1.6 1.2 0.8 0.4 0 0.4 0.8 1.2 1.6 number of readings (%) 2410 g14 12 10 8 6 4 2 0 10,000 consecutive readings v cc = 2.7v v ref = 2.5v v in = 0v ref + = 2.5v ref = gnd in + = 1.25v in = 1.25v f o = 460800hz t a = 25 c gaussian distribution m = 0.177ppm s = 0.297ppm output code (ppm of v ref ) ?0 8.5 ? 5.5 ? 2.5 1 0.5 2 number of readings (%) 2410 g15 10 9 8 7 6 5 4 3 2 1 0 10,000 consecutive readings v cc = 2.7v v ref = 2.5v v in = 0v ref + = 2.5v ref = gnd in + = 1.25v in = 1.25v f o = 1075200hz t a = 25 c gaussian distribution m = 3.714ppm s = 1.295ppm output code (ppm of v ref ) ?.8 ?.6 ?.4 ?.2 0 0.2 0.4 0.6 0.8 number of readings (%) 2410 g16 12 10 8 6 4 2 0 adc consecutive readings v cc = 5v v ref = 5v v in = 0v ref + = 5v ref = gnd in + = 2.5v in = 2.5v f o = gnd t a = 25 c gaussian distribution m = 0.101837ppm s = 0.154515ppm time (hours) 0 5 10 15 20 25 30 35 40 45 50 55 60 adc reading (ppm of v ref ) 2410 g17 1.0 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 1.0 v cc = 5v v ref = 5v v in = 0v f o = gnd t a = 25 c ref + = 5v ref = gnd in + = 2.5v in = 2.5v input differential voltage (v) 2.5 2 1.5 1 0.5 0 0.5 1 1.5 2 2.5 rms noise (ppm of v ref ) 2410 g18 0.5 0.4 0.3 0.2 0.1 0 v cc = 5v v ref = 5v ref + = 5v ref = gnd v incm = 2.5v f o = gnd t a = 25 c noise histogram (output rate = 52.5hz, v cc = 5v, v ref = 2.5v) noise histogram (output rate = 22.5hz, v cc = 5v, v ref = 2.5v) noise histogram (output rate = 7.5hz, v cc = 5v, v ref = 2.5v) noise histogram (output rate = 52.5hz, v cc = 2.7v, v ref = 2.5v) noise histogram (output rate = 22.5hz, v cc = 2.7v, v ref = 2.5v) noise histogram (output rate = 7.5hz, v cc = 2.7v, v ref = 2.5v) rms noise vs input differential voltage consecutive adc readings vs time long-term noise histogram (time = 60 hrs, v cc = 5v, v ref = 5v)
ltc2410 8 typical perfor a ce characteristics uw rms noise vs v cc rms noise vs temperature (t a ) rms noise vs v incm offset error vs temperature (t a ) offset error vs v incm rms noise vs v ref + full-scale error vs temperature (t a ) offset error vs v ref offset error vs v cc v incm (v) ?.5 0 1 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 rms noise (nv) 2410 g19 850 825 800 775 750 725 700 675 650 v cc = 5v ref + = 5v ref = gnd v ref = 5v in + = v incm in = v incm v in = 0v f o = gnd t a = 25 c temperature ( c) rms noise (nv) 2410 g20 850 825 800 775 750 725 700 675 650 ?0 ?5 0 25 50 75 100 v cc = 5v ref + = 5v ref = gnd in + = 2.5v in = 2.5v v in = 0v f o = gnd v cc (v) 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 rms noise (nv) 2410 g21 850 825 800 775 750 725 700 675 650 ref + = 2.5v ref = gnd v ref = 2.5v in + = gnd in = gnd f o = gnd t a = 25 c v ref (v) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 rms noise (nv) 2410 g22 850 825 800 775 750 725 700 675 650 v cc = 5v ref = gnd in + = gnd in = gnd f o = gnd t a = 25 c v incm (v) ?.5 0 1 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 offset error (ppm of v ref ) 2410 g23 0.3 0.2 0.1 0 0.1 0.2 0.3 v cc = 5v ref + = 5v ref = gnd v ref = 5v in + = v incm in = v incm v in = 0v f o = gnd t a = 25 c temperature ( c) ?0 ?5 0 25 50 75 100 offset error (ppm of v ref ) 2410 g24 0.3 0.2 0.1 0 0.1 0.2 0.3 v cc = 5v ref + = 5v ref = gnd in + = 2.5v in = 2.5v v in = 0v f o = gnd v cc (v) offset error (ppm of v ref ) 2410 g25 0.3 0.2 0.1 0 0.1 0.2 0.3 ref + = 2.5v ref = gnd v ref = 2.5v in + = gnd in = gnd f o = gnd t a = 25 c 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 v ref (v) offset error (ppm of v ref ) 2410 g26 0.3 0.2 0.1 0 0.1 0.2 0.3 v cc = 5v ref = gnd in + = gnd in = gnd f o = gnd t a = 25 c 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 temperature ( c) +full-scale error (ppm of v ref ) 2410 g27 3 2 1 0 ? ? ? ?5 ?0 ?5 0 15 30 45 60 75 90 v cc = 5v ref + = 5v ref = gnd in + = 2.5v in = gnd f o = gnd
ltc2410 9 typical perfor a ce characteristics uw C full-scale error vs temperature (t a ) + full-scale error vs v ref + full-scale error vs v cc psrr vs frequency at v cc C full-scale error vs v ref C full-scale error vs v cc psrr vs frequency at v cc psrr vs frequency at v cc psrr vs frequency at v cc v cc (v) +full-scale error (ppm of v ref ) 2410 g28 3 2 1 0 ? ? ? ref + = 2.5v ref = gnd v ref = 2.5v in + = 1.25v in = gnd f o = gnd t a = 25 c 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 v ref (v) +full-scale error (ppm of v ref ) 2410 g29 3 2 1 0 ? ? ? v cc = 5v ref + = v ref ref = gnd in + = 0.5 ?ref + in = gnd f o = gnd t a = 25 c 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 temperature ( c) full-scale error (ppm of v ref ) 2410 g30 3 2 1 0 ? ? ? ?5 ?0 ?5 0 15 30 45 60 75 90 v cc = 5v ref + = 5v ref = gnd in + = gnd in = 2.5v f o = gnd v cc (v) full-scale error (ppm of v ref ) 2410 g31 3 2 1 0 ? ? ? ref + = 2.5v ref = gnd v ref = 2.5v in + = gnd in = 1.25v f o = gnd t a = 25 c 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 v ref (v) full-scale error (ppm of v ref ) 2410 g32 3 2 1 0 ? ? ? v cc = 5v ref + = v ref ref = gnd in + = gnd in = 0.5 ?ref + f o = gnd t a = 25 c 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 frequency at v cc (hz) rejection (db) 2410 g33 0 ?0 ?0 ?0 ?0 100 120 140 0.01 0.1 1 10 100 v cc = 4.1v dc 1.4v ref + = 2.5v ref = gnd in + = gnd in = gnd f o = gnd t a = 25 c frequency at v cc (hz) rejection (db) 2410 g34 0 ?0 ?0 ?0 ?0 100 120 140 0 30 60 90 120 150 180 210 240 v cc = 4.1v dc 1.4v ref + = 2.5v ref = gnd in + = gnd in = gnd f o = gnd t a = 25 c frequency at v cc (hz) rejection (db) 2410 g35 0 ?0 ?0 ?0 ?0 100 120 140 1 10 100 1k 10k 100k 1m ref + = 2.5v ref = gnd in + = gnd in = gnd f o = gnd t a = 25 c frequency at v cc (hz) rejection (db) 2410 g36 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 7600 7620 7640 7660 7680 7700 7720 7740 v cc = 4.1v dc 0.7v ref + = 2.5v ref = gnd in + = gnd in = gnd f o = gnd t a = 25 c
ltc2410 10 gnd (pins 1, 7, 8, 9, 10, 15, 16): ground. multiple ground pins internally connected for optimum ground current flow and v cc decoupling. connect each one of these pins to a ground plane through a low impedance connection. all seven pins must be connected to ground for proper operation. v cc (pin 2): positive supply voltage. bypass to gnd (pin 1) with a 10 m f tantalum capacitor in parallel with 0.1 m f ceramic capacitor as close to the part as possible. ref + (pin 3), ref C (pin 4): differential reference input. the voltage on these pins can have any value between gnd and v cc as long as the reference positive input, ref + , is maintained more positive than the reference negative input, ref C , by at least 0.1v. in + (pin 5), in C (pin 6): differential analog input. the voltage on these pins can have any value between gnd C 0.3v and v cc + 0.3v. within these limits the converter bipolar input range (v in = in + C in C ) extends from C 0.5 ? (v ref ) to 0.5 ? (v ref ). outside this input range the converter produces unique overrange and underrange output codes. cs (pin 11): active low digital input. a low on this pin enables the sdo digital output and wakes up the adc. following each conversion the adc automatically enters the sleep mode and remains in this low power state as long as cs is high. a low-to-high transition on cs during the data output transfer aborts the data transfer and starts a new conversion. sdo (pin 12): three-state digital output. during the data output period, this pin is used as serial data output. when the chip select cs is high (cs = v cc ) the sdo pin is in a high impedance state. during the conversion and sleep periods, this pin is used as the conversion status output. the conversion status can be observed by pulling cs low. sck (pin 13): bidirectional digital clock pin. in internal serial clock operation mode, sck is used as digital output for the internal serial interface clock during the data output period. in external serial clock operation mode, sck is used as digital input for the external serial interface clock during the data output period. a weak internal pull- up is automatically activated in internal serial clock op- eration mode. the serial clock operation mode is deter- mined by the logic level applied to the sck pin at power up or during the most recent falling edge of cs. f o (pin 14): frequency control pin. digital input that controls the adcs notch frequencies and conversion time. when the f o pin is connected to v cc (f o = v cc ), the converter uses its internal oscillator and the digital filter first null is located at 50hz. when the f o pin is connected to gnd (f o = ov), the converter uses its internal oscillator and the digital filter first null is located at 60hz. when f o is driven by an external clock signal with a frequency f eosc , the converter uses this signal as its system clock and the digital filter first null is located at a frequency f eosc /2560. pi fu ctio s uuu typical perfor a ce characteristics uw temperature ( c) supply current ( a) 2410 g39 23 22 21 20 19 18 17 16 ?5 ?0 ?5 0 15 30 45 60 75 90 f o = gnd cs = v cc sck = nc sdo = nc v cc = 5.5v v cc = 2.7v v cc = 4.1v sleep current vs temperature (t a ) output data rate (readings/sec) supply current ( a) 2410 g38 1100 1000 900 800 700 600 500 400 300 200 100 010 20 30 40 50 60 70 80 90 100 v cc = 5v ref + = 5v ref = gnd in + = gnd in = gnd t a = 25 c f o = external osc cs = gnd sck = nc sdo = nc temperature ( c) supply current ( a) 2410 g37 220 210 200 190 180 170 160 ?5 ?0 ?5 0 15 30 45 60 75 90 f o = gnd cs = gnd sck = nc sdo = nc v cc = 5.5v v cc = 4.1v v cc = 2.7v conversion current vs output data rate conversion current vs temperature (t a )
ltc2410 11 test circuits applicatio s i for atio wu u u fu ctio al block diagra uu w figure 2. ltc2410 state transition diagram converter operation converter operation cycle the ltc2410 is a low power, delta-sigma analog-to- digital converter with an easy to use 3-wire serial interface (see figure 1). its operation is made up of three states. the converter operating cycle begins with the conversion, followed by the low power sleep state and ends with the data output (see figure 2). the 3-wire interface consists of serial data output (sdo), serial clock (sck) and chip select (cs). initially, the ltc2410 performs a conversion. once the conversion is complete, the device enters the sleep state. while in this sleep state, power consumption is reduced by an order of magnitude. the part remains in the sleep state autocalibration and control dac decimating fir internal oscillator serial interface adc gnd v cc in + in sdo sck ref + ref cs f o (int/ext) 2410 fd ? + 1.69k sdo 2410 ta04 hi-z to v ol v oh to v ol v ol to hi-z c load = 20pf v cc 1.69k sdo 2410 ta03 hi-z to v oh v ol to v oh v oh to hi-z c load = 20pf convert sleep data output 2410 f02 true false cs = low and sck figure 1. functional block diagram as long as cs is high. the conversion result is held indefinitely in a static shift register while the converter is in the sleep state.
ltc2410 12 once cs is pulled low, the device begins outputting the conversion result. there is no latency in the conversion result. the data output corresponds to the conversion just performed. this result is shifted out on the serial data out pin (sdo) under the control of the serial clock (sck). data is updated on the falling edge of sck allowing the user to reliably latch data on the rising edge of sck (see figure 3). the data output state is concluded once 32 bits are read out of the adc or when cs is brought high. the device automatically initiates a new conversion and the cycle repeats. through timing control of the cs and sck pins, the ltc2410 offers several flexible modes of operation (internal or external sck and free-running conversion modes). these various modes do not require program- ming configuration registers; moreover, they do not dis- turb the cyclic operation described above. these modes of operation are described in detail in the serial interface timing modes section. conversion clock a major advantage the delta-sigma converter offers over conventional type converters is an on-chip digital filter (commonly implemented as a sinc or comb filter). for high resolution, low frequency applications, this filter is typically designed to reject line frequencies of 50 or 60hz plus their harmonics. the filter rejection performance is directly related to the accuracy of the converter system clock. the ltc2410 incorporates a highly accurate on- chip oscillator. this eliminates the need for external fre- quency setting components such as crystals or oscilla- tors. clocked by the on-chip oscillator, the ltc2410 achieves a minimum of 110db rejection at the line fre- quency (50hz or 60hz 2%). ease of use the ltc2410 data output has no latency, filter settling delay or redundant data associated with the conversion cycle. there is a one-to-one correspondence between the conversion and the output data. therefore, multiplexing multiple analog voltages is easy. the ltc2410 performs offset and full-scale calibrations every conversion cycle. this calibration is transparent to the user and has no effect on the cyclic operation de- scribed above. the advantage of continuous calibration is extreme stability of offset and full-scale readings with re- spect to time, supply voltage change and temperature drift. power-up sequence the ltc2410 automatically enters an internal reset state when the power supply voltage v cc drops below approxi- mately 2.2v. this feature guarantees the integrity of the conversion result and of the serial interface mode selec- tion. (see the 2-wire i/o sections in the serial interface timing modes section.) when the v cc voltage rises above this critical threshold, the converter creates an internal power-on-reset (por) signal with a duration of approximately 0.5ms. the por signal clears all internal registers. following the por signal, the ltc2410 starts a normal conversion cycle and follows the succession of states described above. the first conversion result following por is accurate within the specifications of the device if the power supply voltage is restored within the operating range (2.7v to 5.5v) before the end of the por time interval. reference voltage range this converter accepts a truly differential external refer- ence voltage. the absolute/common mode voltage speci- fication for the ref + and ref C pins covers the entire range from gnd to v cc . for correct converter operation, the ref + pin must always be more positive than the ref C pin. the ltc2410 can accept a differential reference voltage from 0.1v to v cc . the converter output noise is deter- mined by the thermal noise of the front-end circuits, and as such, its value in nanovolts is nearly constant with reference voltage. a decrease in reference voltage will not significantly improve the converters effective resolution. on the other hand, a reduced reference voltage will im- prove the converters overall inl performance. a reduced reference voltage will also improve the converter perfor- mance when operated with an external conversion clock (external f o signal) at substantially higher output data rates (see the output data rate section). applicatio s i for atio wu u u
ltc2410 13 input voltage range the analog input is truly differential with an absolute/ common mode range for the in + and in C input pins extending from gnd C 0.3v to v cc + 0.3v. outside these limits, the esd protection devices begin to turn on and the errors due to input leakage current increase rapidly. within these limits, the ltc2410 converts the bipolar differential input signal, v in = in + C in C , from C fs = C 0.5 ? v ref to +fs = 0.5 ? v ref where v ref = ref + C ref C . outside this range, the converter indicates the overrange or the underrange condition using distinct output codes. input signals applied to in + and in C pins may extend by 300mv below ground and above v cc . in order to limit any fault current, resistors of up to 5k may be added in series with the in + and in C pins without affecting the perfor- mance of the device. in the physical layout, it is important to maintain the parasitic capacitance of the connection between these series resistors and the corresponding pins as low as possible; therefore, the resistors should be located as close as practical to the pins. the effect of the series resistance on the converter accuracy can be evalu- ated from the curves presented in the input current/ reference current sections. in addition, series resistors will introduce a temperature dependent offset error due to the input leakage current. a 1na input leakage current will develop a 1ppm offset error on a 5k resistor if v ref = 5v. this error has a very strong temperature dependency. output data format the ltc2410 serial output data stream is 32 bits long. the first 3 bits represent status information indicating the sign and conversion state. the next 24 bits are the conversion result, msb first. the remaining 5 bits are sub lsbs beyond the 24-bit level that may be included in averaging or discarded without loss of resolution. the third and fourth bit together are also used to indicate an underrange condition (the differential input voltage is below Cfs) or an overrange condition (the differential input voltage is above +fs). bit 31 (first output bit) is the end of conversion (eoc) indicator. this bit is available at the sdo pin during the conversion and sleep states whenever the cs pin is low. this bit is high during the conversion and goes low when the conversion is complete. bit 30 (second output bit) is a dummy bit (dmy) and is always low. bit 29 (third output bit) is the conversion result sign indi- cator (sig). if v in is >0, this bit is high. if v in is <0, this bit is low. bit 28 (fourth output bit) is the most significant bit (msb) of the result. this bit in conjunction with bit 29 also provides the underrange or overrange indication. if both bit 29 and bit 28 are high, the differential input voltage is above +fs. if both bit 29 and bit 28 are low, the differential input voltage is below Cfs. the function of these bits is summarized in table 1. table 1. ltc2410 status bits bit 31 bit 30 bit 29 bit 28 input range eoc dmy sig msb v in 3 0.5 ? v ref 0011 0v v in < 0.5 ? v ref 0010 C0.5 ? v ref v in < 0v 0 0 0 1 v in < C 0.5 ? v ref 0000 bits 28-5 are the 24-bit conversion result msb first. bit 5 is the least significant bit (lsb). bits 4-0 are sub lsbs below the 24-bit level. bits 4-0 may be included in averaging or discarded without loss of resolution. data is shifted out of the sdo pin under control of the serial clock (sck), see figure 3. whenever cs is high, sdo remains high impedance and any externally generated sck clock pulses are ignored by the internal data out shift register. in order to shift the conversion result out of the device, cs must first be driven low. eoc is seen at the sdo pin of the device once cs is pulled low. eoc changes real time from high to low at the completion of a conversion. this signal may be used as an interrupt for an external microcontroller. bit 31 (eoc) can be captured on the first rising edge of sck. bit 30 is shifted out of the device on the first falling edge of sck. the final data bit (bit 0) is shifted out on the falling edge of the 31st sck and may be latched applicatio s i for atio wu u u
ltc2410 14 on the rising edge of the 32nd sck pulse. on the falling edge of the 32nd sck pulse, sdo goes high indicating the initiation of a new conversion cycle. this bit serves as eoc (bit 31) for the next conversion cycle. table 2 summarizes the output data format. as long as the voltage on the in + and in C pins is maintained within the C 0.3v to (v cc + 0.3v) absolute maximum operating range, a conversion result is generated for any differential input voltage v in from Cfs = C0.5 ? v ref to +fs = 0.5 ? v ref . for differential input voltages greater than +fs, the conversion result is clamped to the value corre- sponding to the +fs + 1lsb. for differential input voltages below Cfs, the conversion result is clamped to the value corresponding to Cfs C 1lsb. frequency rejection selection (f o ) the ltc2410 internal oscillator provides better than 110db normal mode rejection at the line frequency and all its harmonics for 50hz 2% or 60hz 2%. for 60hz rejec- tion, f o should be connected to gnd while for 50hz rejection the f o pin should be connected to v cc . the selection of 50hz or 60hz rejection can also be made by driving f o to an appropriate logic level. a selection change during the sleep or data output states will not disturb the converter operation. if the selection is made during the conversion state, the result of the conversion in progress may be outside specifications but the following conversions will not be affected. when a fundamental rejection frequency different from 50hz or 60hz is required or when the converter must be table 2. ltc2410 output data format differential input voltage bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 0 v in * eoc dmy sig msb v in * 3 0.5 ? v ref ** 0 0110 0 00 0.5 ? v ref ** C 1lsb 0 0101 1 11 0.25 ? v ref ** 0 0101 0 00 0.25 ? v ref ** C 1lsb 0 0100 1 11 0 0 0100 0 00 C1lsb 0 0011 1 11 C 0.25 ? v ref ** 0 0011 0 00 C 0.25 ? v ref ** C 1lsb 0 0010 1 11 C 0.5 ? v ref ** 0 0010 0 00 v in * < C0.5 ? v ref ** 0 0001 1 11 *the differential input voltage v in = in + C in C . **the differential reference voltage v ref = ref + C ref C . figure 3. output data timing applicatio s i for atio wu u u msb sig ? 12345 262732 bit 0 bit 27 bit 5 lsb 24 bit 28 bit 29 bit 30 sdo sck cs eoc bit 31 sleep data output conversion 2410 f03 hi-z
ltc2410 15 synchronized with an outside source, the ltc2410 can operate with an external conversion clock. the converter automatically detects the presence of an external clock signal at the f o pin and turns off the internal oscillator. the frequency f eosc of the external signal must be at least 2560hz (1hz notch frequency) to be detected. the exter- nal clock signal duty cycle is not significant as long as the minimum and maximum specifications for the high and low periods t heo and t leo are observed. while operating with an external conversion clock of a frequency f eosc , the ltc2410 provides better than 110db normal mode rejection in a frequency range f eosc /2560 4% and its harmonics. the normal mode rejection as a function of the input frequency deviation from f eosc /2560 is shown in figure 4. whenever an external clock is not present at the f o pin, the converter automatically activates its internal oscillator and enters the internal conversion clock mode. the ltc2410 operation will not be disturbed if the change of conversion clock source occurs during the sleep state or during the data output state while the converter uses an external serial clock. if the change occurs during the conversion state, the result of the conversion in progress may be outside specifications but the following conversions will not be affected. if the change occurs during the data output state and the converter is in the internal sck mode, the serial clock duty cycle may be affected but the serial data stream will remain valid. table 3 summarizes the duration of each state and the achievable output data rate as a function of f o . serial interface pins the ltc2410 transmits the conversion results and re- ceives the start of conversion command through a syn- chronous 3-wire interface. during the conversion and sleep states, this interface can be used to assess the converter status and during the data output state it is used to read the conversion result. table 3. ltc2410 state duration state operating mode duration convert internal oscillator f o = low 133ms, output data rate 7.5 readings/s (60hz rejection) f o = high 160ms, output data rate 6.2 readings/s (50hz rejection) external oscillator f o = external oscillator 20510/f eosc s, output data rate f eosc /20510 readings/s with frequency f eosc khz (f eosc /2560 rejection) sleep as long as cs = high until cs = low and sck data output internal serial clock f o = low/high as long as cs = low but not longer than 1.67ms (internal oscillator) (32 sck cycles) f o = external oscillator with as long as cs = low but not longer than 256/f eosc ms frequency f eosc khz (32 sck cycles) external serial clock with as long as cs = low but not longer than 32/f sck ms frequency f sck khz (32 sck cycles) figure 4. ltc2410 normal mode rejection when using an external oscillator of frequency f eosc applicatio s i for atio wu u u differential input signal frequency deviation from notch frequency f eosc /2560(%) 128404812 normal mode rejection (db) 2410 f04 ?0 ?5 ?0 ?5 100 105 110 115 120 125 130 135 140
ltc2410 16 applicatio s i for atio wu u u serial clock input/output (sck) the serial clock signal present on sck (pin 13) is used to synchronize the data transfer. each bit of data is shifted out the sdo pin on the falling edge of the serial clock. in the internal sck mode of operation, the sck pin is an output and the ltc2410 creates its own serial clock by dividing the internal conversion clock by 8. in the external sck mode of operation, the sck pin is used as input. the internal or external sck mode is selected on power-up and then reselected every time a high-to-low transition is detected at the cs pin. if sck is high or floating at power- up or during this transition, the converter enters the inter- nal sck mode. if sck is low at power-up or during this transition, the converter enters the external sck mode. serial data output (sdo) the serial data output pin, sdo (pin 12), provides the result of the last conversion as a serial bit stream (msb first) during the data output state. in addition, the sdo pin is used as an end of conversion indicator during the conversion and sleep states. when cs (pin 11) is high, the sdo driver is switched to a high impedance state. this allows sharing the serial interface with other devices. if cs is low during the convert or sleep state, sdo will output eoc. if cs is low during the conversion phase, the eoc bit appears high on the sdo pin. once the conversion is complete, eoc goes low. the device remains in the sleep state until the first rising edge of sck occurs while cs = low. chip select input (cs) the active low chip select, cs (pin 11), is used to test the conversion status and to enable the data output transfer as described in the previous sections. in addition, the cs signal can be used to trigger a new conversion cycle before the entire serial data transfer has been completed. the ltc2410 will abort any serial data transfer in progress and start a new conversion cycle anytime a low-to-high transition is detected at the cs pin after the converter has entered the data output state (i.e., after the first rising edge of sck occurs with cs=low). finally, cs can be used to control the free-running modes of operation, see serial interface timing modes section. grounding cs will force the adc to continuously convert at the maximum output rate selected by f o . tying a capacitor to cs will reduce the output rate and power dissipation by a factor proportional to the capacitors value, see figures 12 to 14. serial interface timing modes the ltc2410s 3-wire interface is spi and microwire compatible. this interface offers several flexible modes of operation. these include internal/external serial clock, 2- or 3-wire i/o, single cycle conversion and autostart. the following sections describe each of these serial interface timing modes in detail. in all these cases, the converter can use the internal oscillator (f o = low or f o = high) or an external oscillator connected to the f o pin. refer to table 4 for a summary. external serial clock, single cycle operation (spi/microwire compatible) this timing mode uses an external serial clock to shift out the conversion result and a cs signal to monitor and control the state of the conversion cycle, see figure 5. table 4. ltc2410 interface timing modes conversion data connection sck cycle output and configuration source control control waveforms external sck, single cycle conversion external cs and sck cs and sck figures 5, 6 external sck, 2-wire i/o external sck sck figure 7 internal sck, single cycle conversion internal cs cs figures 8, 9 internal sck, 2-wire i/o, continuous conversion internal continuous internal figure 10 internal sck, autostart conversion internal c ext internal figure 11
ltc2410 17 applicatio s i for atio wu u u the serial clock mode is selected on the falling edge of cs. to select the external serial clock mode, the serial clock pin (sck) must be low during each cs falling edge. the serial data output pin (sdo) is hi-z as long as cs is high. at any time during the conversion cycle, cs may be pulled low in order to monitor the state of the converter. while cs is pulled low, eoc is output to the sdo pin. eoc = 1 while a conversion is in progress and eoc = 0 if the device is in the sleep state. independent of cs, the device automatically enters the low power sleep state once the conversion is complete. when the device is in the sleep state (eoc = 0), its conversion result is held in an internal static shift regis- ter. the device remains in the sleep state until the first rising edge of sck is seen while cs is low. data is shifted out the sdo pin on each falling edge of sck. this enables external circuitry to latch the output on the rising edge of sck. eoc can be latched on the first rising edge of sck and the last bit of the conversion result can be latched on the 32nd rising edge of sck. on the 32nd falling edge of sck, the device begins a new conversion. sdo goes high (eoc = 1) indicating a conversion is in progress. at the conclusion of the data cycle, cs may remain low and eoc monitored as an end-of-conversion interrupt. alternatively, cs may be driven high setting sdo to hi-z. as described above, cs may be pulled low at any time in order to monitor the conversion status. typically, cs remains low during the data output state. however, the data output state may be aborted by pulling cs high anytime between the first rising edge and the 32nd falling edge of sck, see figure 6. on the rising edge of cs, the device aborts the data output state and imme- diately initiates a new conversion. this is useful for sys- tems not requiring all 32 bits of output data, aborting an invalid conversion cycle or synchronizing the start of a conversion. external serial clock, 2-wire i/o this timing mode utilizes a 2-wire serial i/o interface. the conversion result is shifted out of the device by an exter- nally generated serial clock (sck) signal, see figure 7. cs may be permanently tied to ground, simplifying the user interface or isolation barrier. the external serial clock mode is selected at the end of the power-on reset (por) cycle. the por cycle is concluded approximately 0.5ms after v cc exceeds 2.2v. the level applied to sck at this time determines if sck is internal or external. sck must be driven low prior to the end of por in order to enter the external serial clock timing mode. figure 5. external serial clock, single cycle operation eoc bit 31 sdo sck (external) cs test eoc sub lsb msb sig bit 0 lsb bit 5 bit 27 bit 26 bit 28 bit 29 bit 30 sleep data output conversion 2410 f05 conversion = 50hz rejection = external oscillator = 60hz rejection hi-z hi-z hi-z v cc test eoc test eoc v cc f o ref + ref sck in + in sdo gnd cs 214 3 4 13 5 6 12 1, 7, 8, 9, 10, 15, 16 11 reference voltage 0.1v to v cc analog input range 0.5v ref to 0.5v ref 1 f 2.7v to 5.5v ltc2410 3-wire spi interface
ltc2410 18 applicatio s i for atio wu u u since cs is tied low, the end-of-conversion (eoc) can be continuously monitored at the sdo pin during the convert and sleep states. eoc may be used as an interrupt to an external controller indicating the conversion result is ready. eoc = 1 while the conversion is in progress and eoc = 0 once the conversion enters the low power sleep state. on the falling edge of eoc, the conversion result is loaded into an internal static shift register. the device remains in the sleep state until the first rising edge of sck. data is shifted out the sdo pin on each falling edge of sck enabling external circuitry to latch data on the rising edge of sck. eoc can be latched on the first rising edge of sck. on the 32nd falling edge of sck, sdo goes high (eoc = 1) indicating a new conversion has begun. internal serial clock, single cycle operation this timing mode uses an internal serial clock to shift out the conversion result and a cs signal to monitor and control the state of the conversion cycle, see figure 8. in order to select the internal serial clock timing mode, the serial clock pin (sck) must be floating (hi-z) or pulled high prior to the falling edge of cs. the device will not enter the internal serial clock mode if sck is driven low on the falling edge of cs. an internal weak pull-up resistor is active on the sck pin during the falling edge of cs; therefore, the internal serial clock timing mode is auto- matically selected if sck is not externally driven. the serial data output pin (sdo) is hi-z as long as cs is high. at any time during the conversion cycle, cs may be pulled low in order to monitor the state of the converter. once cs is pulled low, sck goes low and eoc is output to the sdo pin. eoc = 1 while a conversion is in progress and eoc = 0 if the device is in the sleep state. when testing eoc, if the conversion is complete (eoc = 0), the device will exit the sleep state and enter the data output state if cs remains low. in order to prevent the device from exiting the low power sleep state, cs must be pulled high before the first rising edge of sck. in the internal sck timing mode, sck goes high and the device begins outputting data at time t eoctest after the falling edge of cs (if eoc = 0) or t eoctest after eoc goes low (if cs is low during the falling edge of eoc). the value of t eoctest is 23 m s if the device is using its internal oscillator (f 0 = logic low or high). if f o is driven by an external oscillator of figure 6. external serial clock, reduced data output length = 50hz rejection = external oscillator = 60hz rejection sdo sck (external) cs data output conversion sleep sleep test eoc test eoc data output hi-z hi-z hi-z conversion 2410 f06 msb sig bit 8 bit 27 bit 9 bit 28 bit 29 bit 30 eoc bit 31 bit 0 eoc hi-z v cc test eoc v cc f o ref + ref sck in + in sdo gnd cs 214 3 4 13 5 6 12 1, 7, 8, 9, 10, 15, 16 11 reference voltage 0.1v to v cc analog input range 0.5v ref to 0.5v ref 3-wire spi interface 1 f 2.7v to 5.5v ltc2410
ltc2410 19 applicatio s i for atio wu u u figure 7. external serial clock, cs = 0 operation (2-wire) figure 8. internal serial clock, single cycle operation eoc bit 31 sdo sck (external) cs msb sig bit 0 lsb 24 bit 5 bit 27 bit 26 bit 28 bit 29 bit 30 sleep data output conversion 2410 f07 conversion = 50hz rejection = external oscillator = 60hz rejection v cc v cc f o ref + ref sck in + in sdo gnd cs 214 3 4 13 5 6 12 1, 7, 8, 9, 10, 15, 16 11 reference voltage 0.1v to v cc analog input range 0.5v ref to 0.5v ref 2-wire interface 1 f 2.7v to 5.5v ltc2410 sdo sck (internal) cs msb sig bit 0 lsb 24 bit 5 test eoc bit 27 bit 26 bit 28 bit 29 bit 30 eoc bit 31 sleep data output conversion conversion 2410 f08 ltc2410 20 applicatio s i for atio wu u u frequency f eosc , then t eoctest is 3.6/f eosc . if cs is pulled high before time t eoctest , the device remains in the sleep state. the conversion result is held in the internal static shift register. if cs remains low longer than t eoctest , the first rising edge of sck will occur and the conversion result is serially shifted out of the sdo pin. the data output cycle begins on this first rising edge of sck and concludes after the 32nd rising edge. data is shifted out the sdo pin on each falling edge of sck. the internally generated serial clock is output to the sck pin. this signal may be used to shift the conversion result into external circuitry. eoc can be latched on the first rising edge of sck and the last bit of the conversion result on the 32nd rising edge of sck. after the 32nd rising edge, sdo goes high (eoc = 1), sck stays high and a new conversion starts. typically, cs remains low during the data output state. however, the data output state may be aborted by pulling cs high anytime between the first and 32nd rising edge of sck, see figure 9. on the rising edge of cs, the device aborts the data output state and immediately initiates a new conversion. this is useful for systems not requiring all 32 bits of output data, aborting an invalid conversion cycle, or synchronizing the start of a conversion. if cs is pulled high while the converter is driving sck low, the internal pull-up is not available to restore sck to a logic high state. this will cause the device to exit the internal serial clock mode on the next falling edge of cs. this can be avoided by adding an external 10k pull-up resistor to the sck pin or by never pulling cs high when sck is low. whenever sck is low, the ltc2410s internal pull-up at pin sck is disabled. normally, sck is not externally driven if the device is in the internal sck timing mode. however, certain applications may require an external driver on sck. if this driver goes hi-z after outputting a low signal, the ltc2410s internal pull-up remains disabled. hence, sck remains low. on the next falling edge of cs, the device is switched to the external sck timing mode. by adding an external 10k pull-up resistor to sck, this pin goes high once the external driver goes hi-z. on the next cs falling edge, the device will remain in the internal sck timing mode. figure 9. internal serial clock, reduced data output length sdo sck (internal) cs >t eoctest msb sig bit 8 test eoc test eoc bit 27 bit 26 bit 28 bit 29 bit 30 eoc bit 31 eoc bit 0 sleep data output hi-z hi-z hi-z hi-z hi-z data output conversion conversion sleep 2410 f09 ltc2410 21 applicatio s i for atio wu u u a similar situation may occur during the sleep state when cs is pulsed high-low-high in order to test the conver- sion status. if the device is in the sleep state (eoc = 0), sck will go low. once cs goes high (within the time period defined above as t eoctest ), the internal pull-up is activated. for a heavy capacitive load on the sck pin, the internal pull-up may not be adequate to return sck to a high level before cs goes low again. this is not a concern under normal conditions where cs remains low after detecting eoc = 0. this situation is easily overcome by adding an external 10k pull-up resistor to the sck pin. internal serial clock, 2-wire i/o, continuous conversion this timing mode uses a 2-wire, all output (sck and sdo) interface. the conversion result is shifted out of the device by an internally generated serial clock (sck) signal, see figure 10. cs may be permanently tied to ground, simpli- fying the user interface or isolation barrier. the internal serial clock mode is selected at the end of the power-on reset (por) cycle. the por cycle is concluded approximately 0.5ms after v cc exceeds 2.2v. an internal weak pull-up is active during the por cycle; therefore, the internal serial clock timing mode is automatically selected if sck is not externally driven low (if sck is loaded such that the internal pull-up cannot pull the pin high, the external sck mode will be selected). during the conversion, the sck and the serial data output pin (sdo) are high (eoc = 1). once the conversion is complete, sck and sdo go low (eoc = 0) indicating the conversion has finished and the device has entered the low power sleep state. the part remains in the sleep state a minimum amount of time (1/2 the internal sck period) then immediately begins outputting data. the data output cycle begins on the first rising edge of sck and ends after the 32nd rising edge. data is shifted out the sdo pin on each falling edge of sck. the internally generated serial clock is output to the sck pin. this signal may be used to shift the conversion result into external circuitry. eoc can be latched on the first rising edge of sck and the last bit of the conversion result can be latched on the 32nd rising edge of sck. after the 32nd rising edge, sdo goes high (eoc = 1) indicating a new conversion is in progress. sck remains high during the conversion. figure 10. internal serial clock, continuous operation sdo sck (internal) cs lsb 24 msb sig bit 5 bit 0 bit 27 bit 26 bit 28 bit 29 bit 30 eoc bit 31 sleep data output conversion conversion 2410 f10 = 50hz rejection = external oscillator = 60hz rejection v cc v cc f o ref + ref sck in + in sdo gnd cs 214 3 4 13 5 6 12 1, 7, 8, 9, 10, 15, 16 11 reference voltage 0.1v to v cc analog input range 0.5v ref to 0.5v ref 2-wire interface 1 f 2.7v to 5.5v ltc2410
ltc2410 22 applicatio s i for atio wu u u internal serial clock, autostart conversion this timing mode is identical to the internal serial clock, 2-wire i/o described above with one additional feature. instead of grounding cs, an external timing capacitor is tied to cs. while the conversion is in progress, the cs pin is held high by an internal weak pull-up. once the conversion is complete, the device enters the low power sleep state and an internal 25na current source begins discharging the capacitor tied to cs, see figure 11. the time the converter spends in the sleep state is determined by the value of the external timing capacitor, see figures 12 and 13. once the voltage at cs falls below an internal threshold ( ? 1.4v), the device automatically begins outputting data. the data output cycle begins on the first rising edge of sck and ends on the 32nd rising edge. data is shifted out the sdo pin on each falling edge of sck. the internally generated serial clock is output to the sck pin. this signal may be used to shift the conversion result into external circuitry. after the 32nd rising edge, cs is pulled high and a new conversion is immediately started. this is useful in appli- cations requiring periodic monitoring and ultralow power. figure 14 shows the average supply current as a function of capacitance on cs. it should be noticed that the external capacitor discharge current is kept very small in order to decrease the con- verter power dissipation in the sleep state. in the autostart mode, the analog voltage on the cs pin cannot be ob- served without disturbing the converter operation using a regular oscilloscope probe. when using this configura- tion, it is important to minimize the external leakage current at the cs pin by using a low leakage external capacitor and properly cleaning the pcb surface. the internal serial clock mode is selected every time the voltage on the cs pin crosses an internal threshold volt- age. an internal weak pull-up at the sck pin is active while figure 11. internal serial clock, autostart operation sdo hi-z hi-z sck (internal) cs v cc gnd 2410 f11 bit 0 sig bit 29 bit 30 sleep data output conversion conversion eoc bit 31 = 50hz rejection = external oscillator = 60hz rejection v cc v cc f o ref + ref sck in + in sdo gnd cs 214 3 4 13 5 6 12 1, 7, 8, 9, 10, 15, 16 11 reference voltage 0.1v to v cc analog input range 0.5v ref to 0.5v ref 2-wire interface 1 f 2.7v to 5.5v ltc2410 c ext
ltc2410 23 applicatio s i for atio wu u u cs is discharging; therefore, the internal serial clock timing mode is automatically selected if sck is floating. it is important to ensure there are no external drivers pulling sck low while cs is discharging. preserving the converter accuracy the ltc2410 is designed to reduce as much as possible the conversion result sensitivity to device decoupling, pcb layout, antialiasing circuits, line frequency perturba- tions and so on. nevertheless, in order to preserve the extreme accuracy capability of this part, some simple precautions are desirable. digital signal levels the ltc2410s digital interface is easy to use. its digital inputs (f o , cs and sck in external sck mode of operation) accept standard ttl/cmos logic levels and the internal hysteresis receivers can tolerate edge rates as slow as 100 m s. however, some considerations are required to take advantage of the exceptional accuracy and low supply current of this converter. the digital output signals (sdo and sck in internal sck mode of operation) are less of a concern because they are not generally active during the conversion state. while a digital input signal is in the range 0.5v to (v cc C 0.5v), the cmos input receiver draws additional current from the power supply. it should be noted that, when any one of the digital input signals (f o , cs and sck in external sck mode of operation) is within this range, the ltc2410 power supply current may increase even if the signal in question is at a valid logic level. for micropower operation, it is recommended to drive all digital input signals to full cmos levels [v il < 0.4v and v oh > (v cc C 0.4v)]. during the conversion period, the undershoot and/or overshoot of a fast digital signal connected to the ltc2410 pins may severely disturb the analog to digital conversion process. undershoot and overshoot can occur because of the impedance mismatch at the converter pin when the transition time of an external control signal is less than twice the propagation delay from the driver to ltc2410. for reference, on a regular fr-4 board, signal propagation figure 12. cs capacitance vs t sample figure 13. cs capacitance vs output rate figure 14. cs capacitance vs supply current capacitance on cs (pf) 1 5 6 7 1000 10000 2400 f12 4 3 10 100 100000 2 1 0 t sample (sec) v cc = 5v v cc = 3v capacitance on cs (pf) 0 sample rate (hz) 3 4 5 1000 100000 2400 f13 2 1 0 10 100 10000 6 7 8 v cc = 5v v cc = 3v capacitance on cs (pf) 1 0 supply current ( a rms ) 50 100 150 200 250 300 10 100 1000 10000 2400 f14 100000 v cc = 5v v cc = 3v
ltc2410 24 applicatio s i for atio wu u u velocity is approximately 183ps/inch for internal traces and 170ps/inch for surface traces. thus, a driver gener- ating a control signal with a minimum transition time of 1ns must be connected to the converter pin through a trace shorter than 2.5 inches. this problem becomes particularly difficult when shared control lines are used and multiple reflections may occur. the solution is to carefully terminate all transmission lines close to their characteristic impedance. parallel termination near the ltc2410 pin will eliminate this problem but will increase the driver power dissipation. a series resistor between 27 w and 56 w placed near the driver or near the ltc2410 pin will also eliminate this problem without additional power dissipation. the actual resistor value depends upon the trace impedance and connection topology. an alternate solution is to reduce the edge rate of the control signals. it should be noted that using very slow edges will increase the converter power supply current during the transition time. the multiple ground pins used in this package configuration, as well as the differential input and reference architecture, reduce substantially the converters sensitivity to ground currents. particular attention must be given to the connection of the f o signal when the ltc2410 is used with an external conversion clock. this clock is active during the conver- sion time and the normal mode rejection provided by the internal digital filter is not very high at this frequency. a normal mode signal of this frequency at the converter reference terminals may result into dc gain and inl errors. a normal mode signal of this frequency at the converter input terminals may result into a dc offset error. such perturbations may occur due to asymmetric capaci- tive coupling between the f o signal trace and the converter input and/or reference connection traces. an immediate solution is to maintain maximum possible separation between the f o signal trace and the input/reference sig- nals. when the f o signal is parallel terminated near the converter, substantial ac current is flowing in the loop formed by the f o connection trace, the termination and the ground return path. thus, perturbation signals may be inductively coupled into the converter input and/or refer- ence. in this situation, the user must reduce to a minimum the loop area for the f o signal as well as the loop area for the differential input and reference connections. driving the input and reference the input and reference pins of the ltc2410 converter are directly connected to a network of sampling capacitors. depending upon the relation between the differential input voltage and the differential reference voltage, these ca- pacitors are switching between these four pins transfering small amounts of charge in the process. a simplified equivalent circuit is shown in figure 15. for a simple approximation, the source impedance r s driving an analog input pin (in + , in C , ref + or ref C ) can be considered to form, together with r sw and c eq (see figure 15), a first order passive network with a time constant t = (r s + r sw ) ? c eq . the converter is able to sample the input signal with better than 1ppm accuracy if the sampling period is at least 14 times greater than the input circuit time constant t . the sampling process on the four input analog pins is quasi-independent so each time constant should be considered by itself and, under worst- case circumstances, the errors may add. when using the internal oscillator (f o = low or high), the ltc2410s front-end switched-capacitor network is clocked at 76800hz corresponding to a 13 m s sampling period. thus, for settling errors of less than 1ppm, the driving source impedance should be chosen such that t 13 m s/14 = 920ns. when an external oscillator of frequency f eosc is used, the sampling period is 2/f eosc and, for a settling error of less than 1ppm, t 0.14/f eosc . input current if complete settling occurs on the input, conversion re- sults will be unaffected by the dynamic input current. an incomplete settling of the input signal sampling process may result in gain and offset errors, but it will not degrade the inl performance of the converter. figure 15 shows the mathematical expressions for the average bias currents flowing through the in + and in C pins as a result of the sampling charge transfers when integrated over a sub- stantial time period (longer than 64 internal clock cycles).
ltc2410 25 applicatio s i for atio wu u u the effect of this input dynamic current can be analyzed using the test circuit of figure 16. the c par capacitor includes the ltc2410 pin capacitance (5pf typical) plus the capacitance of the test fixture used to obtain the results shown in figures 17 and 18. a careful implementation can bring the total input capacitance (c in + c par ) closer to 5pf thus achieving better performance than the one predicted by figures 17 and 18. for simplicity, two distinct situa- tions can be considered. figure 15. ltc2410 equivalent analog input circuit figure 16. an rc network at in + and in C figure 18. Cfs error vs r source at in + or in C (small c in ) figure 17. +fs error vs r source at in + or in C (small c in ) iin vv v r iin vv v r iref vv v r v vr iref vv v r v vr where avg in incm refcm eq avg in incm refcm eq avg ref incm refcm eq in ref eq avg ref incm refcm eq in ref eq + - + - () = +- () = -+ - () = - + - () = - - + + 05 05 15 05 15 05 2 2 . . . . . . :: . . ./ v ref ref v ref ref vinin v in in r m internal oscillator hz notch f low r m internal oscillator hz notch f high r f external oscillator ref refcm in incm eq o eq o eq eosc =- = + ? ? ? ? =- = - ? ? ? ? == () == () = () +- +- +- +- 2 2 361 60 432 50 0 555 10 12 w w v ref + v in + v cc r sw (typ) 20k i leak i leak v cc i leak i leak v cc r sw (typ) 20k c eq 18pf (typ) r sw (typ) 20k i leak i in + v in i in i ref + i ref 2410 f15 i leak v cc i leak i leak switching frequency f sw = 76800hz internal oscillator (f o = low or high) f sw = 0.5 ?f eosc external oscillator v ref r sw (typ) 20k c in 2410 f16 v incm + 0.5v in r source in + ltc2410 c par @ 20pf c in v incm ?0.5v in r source in c par @ 20pf r source ( ) 1 10 100 1k 10k 100k +fs error (ppm of v ref ) 2410 f17 50 40 30 20 10 0 v cc = 5v ref + = 5v ref = gnd in + = 5v in = 2.5v f o = gnd t a = 25 c c in = 0.01 f c in = 0.001 f c in = 100pf c in = 0pf r source ( ) 1 10 100 1k 10k 100k fs error (ppm of v ref ) 2410 f18 0 ?0 ?0 ?0 ?0 ?0 v cc = 5v ref + = 5v ref = gnd in + = gnd in = 2.5v f o = gnd t a = 25 c c in = 0.01 f c in = 0.001 f c in = 100pf c in = 0pf
ltc2410 26 applicatio s i for atio wu u u for relatively small values of input capacitance (c in < 0.01 m f), the voltage on the sampling capacitor settles almost completely and relatively large values for the source impedance result in only small errors. such values for c in will deteriorate the converter offset and gain performance without significant benefits of signal filtering and the user is advised to avoid them. nevertheless, when small values of c in are unavoidably present as parasitics of input multiplexers, wires, connectors or sensors, the ltc2410 can maintain its exceptional accuracy while operating with relative large values of source resistance as shown in figures 17 and 18. these measured results may be slightly different from the first order approximation suggested earlier because they include the effect of the actual second order input network together with the non- linear settling process of the input amplifiers. for small c in values, the settling on in + and in C occurs almost indepen- dently and there is little benefit in trying to match the source impedance for the two pins. larger values of input capacitors (c in > 0.01 m f) may be required in certain configurations for antialiasing or gen- eral input signal filtering. such capacitors will average the input sampling charge and the external source resistance will see a quasi constant input differential impedance. when f o = low (internal oscillator and 60hz notch), the typical differential input resistance is 1.8m w which will generate a gain error of approximately 0.28ppm for each ohm of source resistance driving in + or in C . when f o = high (internal oscillator and 50hz notch), the typical differential input resistance is 2.16m w which will generate a gain error of approximately 0.23ppm for each ohm of source resistance driving in + or in C . when f o is driven by an external oscillator with a frequency f eosc (external conversion clock operation), the typical differential input resistance is 0.28 ? 10 12 /f eosc w and each ohm of source resistance driving in + or in C will result in 1.78 ? 10 C6 ? f eosc ppm gain error. the effect of the source resistance on the two input pins is additive with respect to this gain error. the typical +fs and Cfs errors as a function of the sum of the source resistance seen by in + and in C for large values of c in are shown in figures 19 and 20. in addition to this gain error, an offset error term may also appear. the offset error is proportional with the mismatch between the source impedance driving the two input pins in + and in C and with the difference between the input and reference common mode voltages. while the input drive circuit nonzero source impedance combined with the converter average input current will not degrade the inl performance, indirect distortion may result from the modu- lation of the offset error by the common mode component of the input signal. thus, when using large c in capacitor values, it is advisable to carefully match the source imped- ance seen by the in + and in C pins. when f o = low (internal oscillator and 60hz notch), every 1 w mismatch in source impedance transforms a full-scale common mode input signal into a differential mode input signal of 0.28ppm. when f o = high (internal oscillator and 50hz notch), every 1 w mismatch in source impedance trans- forms a full-scale common mode input signal into a differential mode input signal of 0.23ppm. when f o is driven by an external oscillator with a frequency f eosc , every 1 w mismatch in source impedance transforms a full-scale common mode input signal into a differential mode input signal of 1.78 ? 10 C6 ? f eosc ppm. figure 21 shows the typical offset error due to input common mode voltage for various values of source resistance imbalance between the in + and in C pins when large c in values are used. if possible, it is desirable to operate with the input signal common mode voltage very close to the reference signal common mode voltage as is the case in the ratiometric measurement of a symmetric bridge. this configuration eliminates the offset error caused by mismatched source impedances. the magnitude of the dynamic input current depends upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling clock. the accuracy of the internal clock over the entire temperature and power supply range is typical better than 0.5%. such a specification can also be easily achieved by an external clock. when relatively stable resistors (50ppm/ c) are used for the external source impedance seen by in + and in C , the expected drift of the dynamic current, offset and gain errors will be insignificant (about 1% of their respec- tive values over the entire temperature and voltage range). even for the most stringent applications, a one-time calibration operation may be sufficient.
ltc2410 27 applicatio s i for atio wu u u in addition to the input sampling charge, the input esd protection diodes have a temperature dependent leakage current. this current, nominally 1na ( 10na max), results in a small offset shift. a 100 w source resistance will create a 0.1 m v typical and 1 m v maximum offset voltage. reference current in a similar fashion, the ltc2410 samples the differential reference pins ref + and ref C transfering small amount of charge to and from the external driving circuits thus producing a dynamic reference current. this current does not change the converter offset, but it may degrade the gain and inl performance. the effect of this current can be analyzed in the same two distinct situations. for relatively small values of the external reference capaci- tors (c ref < 0.01 m f), the voltage on the sampling capacitor settles almost completely and relatively large values for the source impedance result in only small errors. such values for c ref will deteriorate the converter offset and gain performance without significant benefits of reference filtering and the user is advised to avoid them. larger values of reference capacitors (c ref > 0.01 m f) may be required as reference filters in certain configurations. such capacitors will average the reference sampling charge and the external source resistance will see a quasi con- stant reference differential impedance. when f o = low (internal oscillator and 60hz notch), the typical differential reference resistance is 1.3m w which will generate a gain error of approximately 0.38ppm for each ohm of source resistance driving ref + or ref C . when f o = high (internal oscillator and 50hz notch), the typical differential refer- ence resistance is 1.56m w which will generate a gain error of approximately 0.32ppm for each ohm of source resis- tance driving ref + or ref C . when f o is driven by an external oscillator with a frequency f eosc (external conver- sion clock operation), the typical differential reference resistance is 0.20 ? 10 12 /f eosc w and each ohm of source resistance drving ref + or ref C will result in 2.47 ? 10 C6 ? f eosc ppm gain error. the effect of the source resistance on the two reference pins is additive with respect to this gain error. the typical +fs and Cfs errors for various combinations of source resistance seen by the figure 19. +fs error vs r source at in + or in C (large c in ) figure 20. Cfs error vs r source at in + or in C (large c in ) figure 21. offset error vs common mode voltage (v incm = in + = in C ) and input source resistance imbalance ( d r in = r sourcein + C r sourcein C) for large c in values (c in 3 1 m f) r source ( ) 0 100 200 300 400 500 600 700 800 900 1000 +fs error (ppm of v ref ) 2410 f19 300 240 180 120 60 0 v cc = 5v ref + = 5v ref = gnd in + = 3.75v in = 1.25v f o = gnd t a = 25 c c in = 0.01 f c in = 0.1 f c in = 1 f, 10 f r source ( ) 0 100 200 300 400 500 600 700 800 900 1000 fs error (ppm of v ref ) 2410 f20 0 ?0 120 180 240 300 v cc = 5v ref + = 5v ref = gnd in + = 1.25v in = 3.75v f o = gnd t a = 25 c c in = 0.01 f c in = 0.1 f c in = 1 f, 10 f v incm (v) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 offset error (ppm of v ref ) 2410 f21 120 100 80 60 40 20 0 ?0 ?0 ?0 ?0 100 120 f o = gnd t a = 25 c r sourcein ?= 500 c in = 10 f v cc = 5v ref + = 5v ref = gnd in + = in = v incm a: ? r in = +400 b: ? r in = +200 c: ? r in = +100 d: ? r in = 0 e: ? r in = 100 f: ? r in = 200 g: ? r in = 400 a b c d e f g
ltc2410 28 applicatio s i for atio wu u u ref + and ref C pins and external capacitance c ref con- nected to these pins are shown in figures 22, 23, 24 and 25. in addition to this gain error, the converter inl perfor- mance is degraded by the reference source impedance. when f o = low (internal oscillator and 60hz notch), every 100 w of source resistance driving ref + or ref C translates into about 1.34ppm additional inl error. when f o = high (internal oscillator and 50hz notch), every 100 w of source resistance driving ref + or ref C translates into about 1.1ppm additional inl error. when f o is driven by an external oscillator with a frequency f eosc , every 100 w of source resistance driving ref + or ref C translates into about 8.73 ? 10 C6 ? f eosc ppm additional inl error. figure 26 shows the typical inl error due to the source resistance driving the ref + or ref C pins when large c ref values are used. the effect of the source resistance on the two reference pins is additive with respect to this inl error. in general, matching of source impedance for the ref + and ref C pins does not help the gain or the inl error. the user is thus advised to minimize the combined source impedance driving the ref + and ref C pins rather than to try to match it. figure 22. +fs error vs r source at ref + or ref C (small c in ) figure 23. Cfs error vs r source at ref + or ref C (small c in ) figure 24. +fs error vs r source at ref + and ref C (large c ref ) figure 25. Cfs error vs r source at ref + and ref C (large c ref ) r source ( ) 1 10 100 1k 10k 100k +fs error (ppm of v ref ) 2410 f22 0 ?0 ?0 ?0 ?0 ?0 v cc = 5v ref + = 5v ref = gnd in + = 5v in = 2.5v f o = gnd t a = 25 c c ref = 0.01 f c ref = 0.001 f c ref = 100pf c ref = 0pf r source ( ) 1 10 100 1k 10k 100k fs error (ppm of v ref ) 2410 f23 50 40 30 20 10 0 v cc = 5v ref + = 5v ref = gnd in + = gnd in = 2.5v f o = gnd t a = 25 c c ref = 0.01 f c ref = 0.001 f c ref = 100pf c ref = 0pf r source ( ) 0 100 200 300 400 500 600 700 800 900 1000 +fs error (ppm of v ref ) 2410 f24 0 ?0 180 270 360 450 v cc = 5v ref + = 5v ref = gnd in + = 3.75v in = 1.25v f o = gnd t a = 25 c c ref = 0.01 f c ref = 0.1 f c ref = 1 f, 10 f r source ( ) 0 100 200 300 400 500 600 700 800 900 1000 fs error (ppm of v ref ) 2410 f25 450 360 270 180 90 0 v cc = 5v ref + = 5v ref = gnd in + = 1.25v in = 3.75v f o = gnd t a = 25 c c ref = 0.01 f c ref = 0.1 f c ref = 1 f, 10 f
ltc2410 29 applicatio s i for atio wu u u the magnitude of the dynamic reference current depends upon the size of the very stable internal sampling capaci- tors and upon the accuracy of the converter sampling clock. the accuracy of the internal clock over the entire temperature and power supply range is typical better than 0.5%. such a specification can also be easily achieved by an external clock. when relatively stable resistors (50ppm/ c) are used for the external source impedance seen by ref + and ref C , the expected drift of the dynamic current gain error will be insignificant (about 1% of its value over the entire temperature and voltage range). even for the most stringent applications a one-time calibration operation may be sufficient. in addition to the reference sampling charge, the reference pins esd protection diodes have a temperature dependent leakage current. this leakage current, nominally 1na ( 10na max), results in a small gain error. a 100 w source resistance will create a 0.05 m v typical and 0.5 m v maxi- mum full-scale error. output data rate when using its internal oscillator, the ltc2410 can pro- duce up to 7.5 readings per second with a notch frequency of 60hz (f o = low) and 6.25 readings per second with a notch frequency of 50hz (f o = high). the actual output data rate will depend upon the length of the sleep and data output phases which are controlled by the user and which can be made insignificantly short. when operated with an external conversion clock (f o connected to an external oscillator), the ltc2410 output data rate can be increased as desired. the duration of the conversion phase is 20510/ f eosc . if f eosc = 153600hz, the converter behaves as if the internal oscillator is used and the notch is set at 60hz. there is no significant difference in the ltc2410 perfor- mance between these two operation modes. an increase in f eosc over the nominal 153600hz will translate into a proportional increase in the maximum output data rate. this substantial advantage is neverthe- less accompanied by three potential effects, which must be carefully considered. first, a change in f eosc will result in a proportional change in the internal notch position and in a reduction of the converter differential mode rejection at the power line frequency. in many applications, the subsequent perfor- mance degradation can be substantially reduced by rely- ing upon the ltc2410s exceptional common mode rejec- tion and by carefully eliminating common mode to differ- ential mode conversion sources in the input circuit. the user should avoid single-ended input filters and should maintain a very high degree of matching and symmetry in the circuits driving the in + and in C pins. second, the increase in clock frequency will increase proportionally the amount of sampling charge transferred through the input and the reference pins. if large external input and/or reference capacitors (c in , c ref ) are used, the previous section provides formulae for evaluating the effect of the source resistance upon the converter perfor- mance for any value of f eosc . if small external input and/ or reference capacitors (c in , c ref ) are used, the effect of the external source resistance upon the ltc2410 typical performance can be inferred from figures 17, 18, 22 and 23 in which the horizontal axis is scaled by 153600/f eosc . third, an increase in the frequency of the external oscilla- tor above 460800hz (a more than 3 increase in the output data rate) will start to decrease the effectiveness of the internal autocalibration circuits. this will result in a pro- gressive degradation in the converter accuracy and linear- figure 26. inl vs differential input voltage (v in = in + C in C ) and reference source resistance (r source at ref + and ref C for large c ref values (c ref 3 1 m f) v indif /v refdif ?.5 0.40.30.20.1 0 0.1 0.2 0.3 0.4 0.5 inl (ppm of v ref ) 15 12 9 6 3 0 ? ? ? ?2 ?5 v cc = 5v ref+ = 5v ref?= gnd v incm = 0.5 ?(in + + in ) = 2.5v f o = gnd c ref = 10 f t a = 25 c r source = 1000 r source = 500 r source = 100 2410 f26
ltc2410 30 applicatio s i for atio wu u u ity. typical measured performance curves for output data rates up to 100 readings per second are shown in fig- ures 27, 28, 29, 30, 31, 32, 33 and 34. in order to obtain the highest possible level of accuracy from this converter at output data rates above 20 readings per second, the user is advised to maximize the power supply voltage used and to limit the maximum ambient operating temperature. in certain circumstances, a reduction of the differential reference voltage may be beneficial. input bandwidth the combined effect of the internal sinc 4 digital filter and of the analog and digital autocalibration circuits deter- mines the ltc2410 input bandwidth. when the internal oscillator is used with the notch set at 60hz (f o = low), the 3db input bandwidth is 3.63hz. when the internal oscillator is used with the notch set at 50hz (f o = high), the 3db input bandwidth is 3.02hz. if an external conver- sion clock generator of frequency f eosc is connected to the f o pin, the 3db input bandwidth is 0.236 ? 10 C6 ? f eosc . due to the complex filtering and calibration algorithms utilized, the converter input bandwidth is not modeled very accurately by a first order filter with the pole located at the 3db frequency. when the internal oscillator is used, the shape of the ltc2410 input bandwidth is shown in fig- ure 35 for f o = low and f o = high. when an external oscillator of frequency f eosc is used, the shape of the ltc2410 input bandwidth can be derived from figure 35, f o = low curve in which the horizontal axis is scaled by f eosc /153600. the conversion noise (800nv rms typical for v ref = 5v) can be modeled by a white noise source connected to a noise free converter. the noise spectral density is 62.75nv ? hz for an infinite bandwidth source and 86.1nv ? hz for a single 0.5mhz pole source. from these numbers, it is clear that particular attention must be given to the design of external amplification circuits. such circuits face the simultaneous requirements of very low bandwidth (just a few hz) in order to reduce the output referred noise and relatively high bandwidth (at least 500khz) necessary to drive the input switched-capacitor network. a possible solution is a high gain, low bandwidth amplifier stage followed by a high bandwidth unity-gain buffer. figure 27. offset error vs output data rate and temperature figure 28. +fs error vs output data rate and temperature figure 29. Cfs error vs output data rate and temperature output data rate (readings/sec) 0 102030405060708090100 offset error (ppm of v ref ) 2410 f27 500 450 400 350 300 250 200 150 100 50 0 t a = 85 c v cc = 5v ref + = 5v ref = gnd v incm = 2.5v v in = 0v f o = external oscillator t a = 25 c output data rate (readings/sec) 0 102030405060708090100 +fs error (ppm of v ref ) 2410 f28 7000 6000 5000 4000 3000 2000 1000 0 t a = 85 c v cc = 5v ref + = 5v ref = gnd in + = 3.75v in = 1.25v f o = external oscillator t a = 25 c output data rate (readings/sec) 0 102030405060708090100 ?s error (ppm of v ref ) 2410 f29 0 1000 2000 3000 4000 5000 6000 7000 t a = 85 c v cc = 5v ref + = 5v ref = gnd in + = 1.25v in = 3.75v f o = external oscillator t a = 25 c
ltc2410 31 applicatio s i for atio wu u u figure 30. resolution (noise rms 1lsb) vs output data rate and temperature figure 31. resolution (inl rms 1lsb) vs output data rate and temperature figure 32. offset error vs output data rate and reference voltage figure 33. resolution (noise rms 1lsb) vs output data rate and reference voltage figure 34. resolution (inl max 1lsb) vs output data rate and reference voltage output data rate (readings/sec) 0 102030405060708090100 resolution (bits) 2410 f30 24 23 22 21 20 19 18 17 16 15 14 13 12 t a = 85 c v cc = 5v ref + = 5v ref = gnd v incm = 2.5v v in = 0v f o = external oscillator resolution = log 2 (v ref /noise rms ) t a = 25 c output data rate (readings/sec) 0 102030405060708090100 resolution (bits) 2410 f31 22 20 18 16 14 12 10 8 t a = 85 c v cc = 5v ref + = 5v ref = gnd v incm = 2.5v ?.5v < v in < 2.5v f o = external oscillator resolution = log 2 (v ref /inl max ) t a = 25 c output data rate (readings/sec) 0 102030405060708090100 offset error (ppm of v ref ) 2410 f32 250 225 200 175 150 125 100 75 50 25 0 v ref = 5v v cc = 5v ref + = gnd v incm = 2.5v v in = 0v f o = external oscillator t a = 25 c v ref = 2.5v output data rate (readings/sec) 0 102030405060708090100 resolution (bits) 2410 f33 24 23 22 21 20 19 18 17 16 15 14 13 12 v ref = 5v v cc = 5v ref = gnd v incm = 2.5v v in = 0v f o = external oscillator t a = 25 c resolution = log 2 (v ref /noise rms ) v ref = 2.5v output data rate (readings/sec) 0 102030405060708090100 resolution (bits) 2410 f34 22 20 18 16 14 12 10 8 t a = 25 c v cc = 5v ref = gnd v incm = 0.5 ?ref + 0.5v ?v ref < v in < 0.5 ?v ref f o = external oscillator v ref = 2.5v v ref = 5v resolution = log 2 (v ref /inl max ) figure 35. input signal bandwidth using the internal oscillator differential input signal frequency (hz) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 input signal attenuation (db) 2410 f35 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 f o = high f o = low
ltc2410 32 applicatio s i for atio wu u u when external amplifiers are driving the ltc2410, the adc input referred system noise calculation can be simpli- fied by figure 36. the noise of an amplifier driving the ltc2410 input pin can be modeled as a band limited white noise source. its bandwidth can be approximated by the bandwidth of a single pole lowpass filter with a corner frequency f i . the amplifier noise spectral density is n i . from figure 36, using f i as the x-axis selector, we can find on the y-axis the noise equivalent bandwidth freq i of the input driving amplifier. this bandwidth includes the band limiting effects of the adc internal calibration and filtering. the noise of the driving amplifier referred to the converter input and including all these effects can be calculated as n = n i ? ? freq i . the total system noise (referred to the ltc2410 input) can now be obtained by summing as square root of sum of squares the three adc input referred noise sources: the ltc2410 internal noise (800nv), the noise of the in + driving amplifier and the noise of the in C driving amplifier. if the f o pin is driven by an external oscillator of frequency f eosc , figure 36 can still be used for noise calculation if the x-axis is scaled by f eosc /153600. for large values of the ratio f eosc /153600, the figure 36 plot accuracy begins to decrease, but in the same time the ltc2410 noise floor rises and the noise contribution of the driving amplifiers lose significance. normal mode rejection and antialiasing one of the advantages delta-sigma adcs offer over con- ventional adcs is on-chip digital filtering. combined with a large oversampling ratio, the ltc2410 significantly simplifies antialiasing filter requirements. the sinc 4 digital filter provides greater than 120db normal mode rejection at all frequencies except dc and integer multiples of the modulator sampling frequency (f s ). the ltc2410s autocalibration circuits further simplify the antialiasing requirements by additional normal mode sig- nal filtering both in the analog and digital domain. inde- pendent of the operating mode, f s = 256 ? f n = 2048 ? f outmax where f n in the notch frequency and f outmax is the maximum output data rate. in the internal oscillator mode with a 50hz notch setting, f s = 12800hz and with a 60hz notch setting f s = 15360hz. in the external oscillator mode, f s = f eosc /10. figure 37. input normal mode rejection, internal oscillator and 50hz notch figure 38. input normal mode rejection, internal oscillator and 60hz notch or external oscillator differential input signal frequency (hz) 0f s 2f s 3f s 4f s 5f s 6f s 7f s 8f s 9f s 10f s 11f s 12f s input normal mode rejection (db) 2410 f37 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 110 120 f o = high f o = low or f o = external oscillator, f eosc = 10 ?f s differential input signal frequency (hz) 0f s input normal mode rejection (db) 2410 f38 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 110 120 2f s 3f s 4f s 5f s 6f s 7f s 8f s 9f s 10f s figure 36. input referred noise equivalent bandwidth of an input connected white noise source input noise source single pole equivalent bandwidth (hz) 1 input referred noise equivalent bandwidth (hz) 10 0.1 1 10 100 1k 10k 100k 1m 2410 f36 0.1 100 f o = high f o = low
ltc2410 33 applicatio s i for atio wu u u figure 39. input normal mode rejection figure 40. input normal mode rejection figure 41. input normal mode rejection vs input frequency with input perturbation of 100% full scale (60hz notch) figure 42. input normal mode rejection vs input frequency with input perturbation of 100% full scale (50hz notch) input signal frequency (hz) input normal mode rejection (db) 2410 f39 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 110 120 f n 0 2f n 3f n 4f n 5f n 6f n 7f n 8f n input signal frequency (hz) 250f n 252f n 254f n 256f n 258f n 260f n 262f n input normal mode rejection (db) 2410 f40 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 110 120 input frequency (hz) 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 normal mode rejection (db) 2410 f41 0 ?0 ?0 ?0 ?0 100 120 v cc = 5v ref + = 5v ref = gnd v incm = 2.5v v in(p-p) = 5v f o = gnd t a = 25 c measured data calculated data input frequency (hz) 0 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200 normal mode rejection (db) 2410 f42 0 ?0 ?0 ?0 ?0 100 120 v cc = 5v ref + = 5v ref = gnd v incm = 2.5v v in(p-p) = 5v f o = 5v t a = 25 c measured data calculated data the combined normal mode rejection performance is shown in figure 37 for the internal oscillator with 50hz notch setting (f o = high) and in figure 38 for the internal oscillator with 60hz notch setting (f o = low) and for the external oscillator mode. the regions of low rejection occurring at integer multiples of f s have a very narrow bandwidth. magnified details of the normal mode rejection curves are shown in figure 39 (rejection near dc) and figure 40 (rejection at f s = 256f n ) where f n represents the notch frequency. these curves have been derived for the external oscillator mode but they can be used in all operating modes by appropriately selecting the f n value. the user can expect to achieve in practice this level of performance using the internal oscillator as it is demon- strated by figures 41 and 42. typical measured values of the normal mode rejection of the ltc2410 operating with an internal oscillator and a 60hz notch setting are shown in figure 41 superimposed over the theoretical calculated curve. similarly, typical measured values of the normal mode rejection of the ltc2410 operating with an internal oscillator and a 50hz notch setting are shown in figure 42 superimposed over the theoretical calculated curve. as a result of these remarkable normal mode specifica- tions, minimal (if any) antialias filtering is required in front of the ltc2410. if passive rc components are placed in front of the ltc2410, the input dynamic current should be considered (see input current section). in cases where large effective rc time constants are used, an external buffer amplifier may be required to minimize the effects of dynamic input current.
ltc2410 34 applicatio s i for atio wu u u traditional high order delta-sigma modulators, while pro- viding very good linearity and resolution, suffer from po- tential instabilities at large input signal levels. the propri- etary architecture used for the ltc2410 third order modu- lator resolves this problem and guarantees a predictable stable behavior at input signal levels of up to 150% of full scale. in many industrial applications, it is not uncommon to have to measure microvolt level signals superimposed over volt level perturbations and ltc2410 is eminently suited for such tasks. when the perturbation is differential, the specification of interest is the normal mode rejection for large input signal levels. with a reference voltage v ref = 5v, the ltc2410 has a full-scale differential input range of 5v peak-to-peak. figures 43 and 44 show mea- surement results for the ltc2410 normal mode rejection ratio with a 7.5v peak-to-peak (150% of full scale) input signal superimposed over the more traditional normal mode rejection ratio results obtained with a 5v peak-to-peak (full scale) input signal. in figure 43, the ltc2410 uses the internal oscillator with the notch set at 60hz (f o = low) and in figure 44 it uses the internal oscillator with the notch set at 50hz (f o = high). it is clear that the ltc2410 rejection performance is maintained with no compromises in this extreme situation. when operating with large input signal levels, the user must observe that such signals do not violate the device absolute maximum ratings. synchronization of multiple ltc2410s since the ltc2410s absolute accuracy (total unadjusted error) is 5ppm, applications utilizing multiple synchro- nized adcs are possible. figure 43. measured input normal mode rejection vs input frequency with input perturbation of 150% full scale (60hz notch) figure 44. measured input normal mode rejection vs input frequency with input perturbation of 150% full scale (50hz notch) input frequency (hz) 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 normal mode rejection (db) 2410 f43 0 ?0 ?0 ?0 ?0 100 120 v cc = 5v ref + = 5v ref = gnd v incm = 2.5v f o = gnd t a = 25 c v in(p-p) = 5v v in(p-p) = 7.5v (150% of full scale) input frequency (hz) 0 normal mode rejection (db) 2410 f44 0 ?0 ?0 ?0 ?0 100 120 v cc = 5v ref + = 5v ref = gnd v incm = 2.5v f o = 5v t a = 25 c v in(p-p) = 5v v in(p-p) = 7.5v (150% of full scale) 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
ltc2410 35 applicatio s i for atio wu u u simultaneous sampling with two ltc2410s one such application is synchronizing multiple ltc2410s, see figure 45. the start of conversion is synchronized to the rising edge of cs. in order to synchronize multiple ltc2410s, cs is a common input to all the adcs. to prevent the converters from autostarting a new con- version at the end of data output read, 31 or fewer sck clock signals are applied to the ltc2410 instead of 32 (the 32nd falling edge would start a conversion). the exact timing and frequency for the sck signal is not critical since it is only shifting out the data. in this case, two ltc2410s simultaneously start and end their conversion cycles under the external control of cs. increasing the output rate using mulitple ltc2410s a second application uses multiple ltc2410s to increase the effective output rate by 4 , see figure 46. in this case, four ltc2410s are interleaved under the control of sepa- rate cs signals. this increases the effective output rate from 7.5hz to 30hz (up to a maximum of 60hz). addition- ally, the one-shot output spectrum is unfolded allowing further digital signal processing of the conversion results. sck and sdo may be common to all four ltc2410s. the four cs rising edges equally divide one ltc2410 conver- sion cycle (7.5hz for 60hz notch frequency). in order to synchronize the start of conversion to cs, 31 or less sck clock pulses must be applied to each adc. both the synchronous and 4 output rate applications use the external serial clock and single cycle operation with reduced data output length (see serial interface timing modes section and figure 6). an external oscillator clock is applied commonly to the f o pin of each ltc2410 in order to synchronize the sampling times. both circuits may be extended to include more ltc2410s. figure 45. synchronous conversionextendable 31 or less clock cycles cs sck1 sck2 2410 f45 sdo1 sdo2 31 or less clock cycles ltc2410 #1 v cc ref + ref in + in gnd f o sck sdo cs sck2 sck1 cs sdo1 sdo2 ltc2410 #2 v cc ref + ref in + in gnd f o sck sdo cs controller external oscillator (153,600hz) v ref + v ref
ltc2410 36 applicatio s i for atio wu u u bridge applications typical strain gauge based bridges deliver only 2mv/volt of excitation. as the maximum reference voltage of the ltc2410 is 5v, remote sensing of applied excitation without additional circuitry requires that excitation be limited to 5v. this gives only 10mv full scale input signal, which can be resolved to 1 part in 10000 without averag- ing. for many solid state sensors, this is still better than the sensor. averaging 64 samples however reduces the noise level by a factor of eight, bringing the resolving power to 1 part in 80000, comparable to better weighing systems. hysteresis and creep effects in the load cells are typically much greater than this. most applications that require strain measurements to this level of accuracy are measuring slowly changing phenomena, hence the time required to average a large number of readings is usually not an issue. for those systems that require accurate measurement of a small incremental change on a signifi- cant tare weight, the lack of history effects in the ltc2400 family is of great benefit. for those applications that cannot be fulfilled by the ltc2410 alone, compensating for error in external ampli- fication can be done effectively due to the no latency feature of the ltc2410. no latency operation allows samples of the amplifier offset and gain to be interleaved with weighing measurements. the use of correlated double sampling allows suppression of 1/f noise, offset and thermocouple effects within the bridge. correlated double sampling involves alternating the polarity of excitation and dealing with the reversal of input polarity mathematically. alternatively, bridge excitation can be increased to as much as 10v, if one of several precision attenuation figure 46. using multiple ltc2410s to increase output data rate cs1 cs2 cs3 2410 f46 cs4 sck 31 or less clock pulses sdo ltc2410 #1 sck sdo cs1 cs2 cs3 cs4 ltc2410 #2 ltc2410 #3 ltc2410 #4 controller external oscillator (153,600hz) v ref + v ref v cc ref + ref in + in gnd f o sck sdo cs v cc ref + ref in + in gnd f o sck sdo cs v cc ref + ref in + in gnd f o sck sdo cs v cc ref + ref in + in gnd f o sck sdo cs
ltc2410 37 applicatio s i for atio wu u u techniques is used to produce a precision divide operation on the reference signal. another option is the use of a reference within the 5v input range of the ltc2410 and developing excitation via fixed gain, or ltc1043 based voltage multiplication, along with remote feedback in the excitation amplifiers, as shown in figures 52 and 53. figure 47 shows an example of a simple bridge connec- tion. note that it is suitable for any bridge application where measurement speed is not of the utmost impor- tance. for many applications where large vessels are weighed, the average weight over an extended period of time is of concern and short term weight is not readily determined due to movement of contents, or mechanical resonance. often, large weighing applications involve load cells located at each load bearing point, the output of which can be summed passively prior to the signal pro- cessing circuitry, actively with amplification prior to the adc, or can be digitized via multiple adc channels and summed mathematically. the mathematical summation of the output of multiple ltc2410s provides the benefit of a root square reduction in noise. the low power consump- tion of the ltc2410 makes it attractive for multidrop communication schemes where the adc is located within the load-cell housing. a direct connection to a load cell is perhaps best incorpo- rated into the load-cell body, as minimizing the distance to the sensor largely eliminates the need for protection devices, rfi suppression and wiring. the ltc2410 exhib- its extremely low temperature dependent drift. as a result, exposure to external ambient temperature ranges does not compromise performance. the incorporation of any amplification considerably complicates thermal stability, as input offset voltages and currents, temperature coeffi- cient of gain settling resistors all become factors. the circuit in figure 48 shows an example of a simple amplification scheme. this example produces a differen- tial output with a common mode voltage of 2.5v, as determined by the bridge. the use of a true three amplifier instrumentation amplifier is not necessary, as the ltc2410 has common mode rejection far beyond that of most amplifiers. the ltc1051 is a dual autozero amplifier that can be used to produce a gain of 15 before its input referred noise dominates the ltc2410 noise. this ex- ample shows a gain of 34, that is determined by a feedback network built using a resistor array containing 8 individual resistors. the resistors are organized to optimize tem- perature tracking in the presence of thermal gradients. the second ltc1051 buffers the low noise input stage from the transient load steps produced during conversion. the gain stability and accuracy of this approach is very good, due to a statistical improvement in resistor match- ing. a gain of 34 may seem low, when compared to common practice in earlier generations of load-cell inter- faces, however the accuracy of the ltc2410 changes the rationale. achieving high gain accuracy and linearity at higher gains may prove difficult, while providing little benefit in terms of noise reduction. at a gain of 100, the gain error that could result from typical open-loop gain of 160db is C1ppm, however, worst-case is at the minimum gain of 116db, giving a gain error of C158ppm. worst-case gain error at a gain of 34, is C54ppm. the use of the ltc1051a reduces the worst- case gain error to C33ppm. the advantage of gain higher than 34, then becomes dubious, as the input referred noise sees little improvement 1 and gain accuracy is poten- tially compromised. note that this 4-amplifier topology has advantages over the typical integrated 3-amplifier instrumentation ampli- fier in that it does not have the high noise level common in the output stage that usually dominates when an instru- figure 47. simple bridge connection ref + ref sdo sck in + in cs gnd v ref f o 3 r1 12 4 350 bridge 13 5 6 2410 f47 11 1, 7, 8, 9, 10, 15, 16 2 14 ltc2410 + r2 r1 and r2 can be used to increase tolerable ac component on ref signals lt1019
ltc2410 38 applicatio s i for atio wu u u mentation amplifier is used at low gain. if this amplifier is used at a gain of 10, the gain error is only 10ppm and input referred noise is reduced to 0.1 m v rms . the buffer stages can also be configured to provide gain of up to 50 with high gain stability and linearity. figure 49 shows an example of a single amplifier used to produce single-ended gain. this topology is best used in applications where the gain setting resistor can be made to match the temperature coefficient of the strain gauges. if the bridge is composed of precision resistors, with only one or two variable elements, the reference arm of the bridge can be made to act in conjunction with the feedback resistor to determine the gain. if the feedback resistor is incorporated into the design of the load cell, using resis- tors which match the temperature coefficient of the load- cell elements, good results can be achieved without the need for resistors with a high degree of absolute accuracy. the common mode voltage in this case, is again a function of the bridge output. differential gain as used with a 350 w bridge is a v = (r1+ r2)/(r1+175 w ). common mode gain is half the differential gain. the maximum differential signal that can be used is 1/4 v ref , as opposed to 1/2 v ref in the 2-amplifier topology above. remote half bridge interface as opposed to full bridge applications, typical half bridge applications must contend with nonlinearity in the bridge output, as signal swing is often much greater. applications include rtds, thermistors and other resistive elements that undergo significant changes over their span. for single variable element bridges, the nonlinearity of the half bridge output can be eliminated completely; if the refer- ence arm of the bridge is used as the reference to the adc, as shown in figure 50. the ltc2410 can accept inputs up to 1/2 v ref . hence, the reference resistor r1 must be at least 2x the highest value of the variable resistor. in the case of 100 w platinum rtds, this would suggest a value of 800 w for r1. such a low value for r1 is not advisable due to self-heating effects. a value of 25.5k is shown for r1, reducing self-heating effects to acceptable levels for most sensors. the basic circuit shown in figure 50 shows connections for a full 4-wire connection to the sensor, which may be located remotely. the differential input connections will reject induced or coupled 60hz interference, however, the 1 input referred noise for a v = 34 for approximately 0.05 m v rms , whereas at a gain of 50, it would be 0.048 m v rms . figure 48. using autozero amplifiers to reduce input referred noise 0.1 f 8 0.1 f 0.1 f ref + ref sdo sck in + in cs gnd v cc f o 312 5v ref 4 350 bridge 13 5 6 2410 f48 11 1, 7, 8, 9, 10, 15, 16 2 14 ltc2410 rn1 = 5k 8 resistor array u1a, u1b, u2a, u2b = 1/2 ltc1051 + 3 2 8 4 u1a 4 5v + 6 5 rn1 1 16 15 2 611 7 1 14 3 710 4 13 89 512 u1b + 2 3 u2a 5v 1 + 6 5 u2b 7
ltc2410 39 applicatio s i for atio wu u u reference inputs do not have the same rejection. if 60hz or other noise is present on the reference input, a low pass filter is recommended as shown in figure 51. note that you cannot place a large capacitor directly at the junction of r1 and r2, as it will store charge from the sampling process. a better approach is to produce a low pass filter decoupled from the input lines with a high value resistor (r3). the use of a third resistor in the half bridge, between the variable and fixed elements gives essentially the same result as the two resistor version, but has a few benefits. if, for example, a 25k reference resistor is used to set the excitation current with a 100 w rtd, the negative refer- ence input is sampling the same external node as the positive input and may result in errors if used with a long cable. for short cable applications, the errors may be acceptalby low. if instead the single 25k resistor is re- placed with a 10k 5% and a 10k 0.1% reference resistor, the noise level introduced at the reference, at least at higher frequencies, will be reduced. a filter can be intro- duced into the network, in the form of one or more capacitors, or ferrite beads, as long as the sampling pulses are not translated into an error. the reference voltage is also reduced, but this is not undesirable, as it will decrease the value of the lsb, although, not the input referred noise level. the circuit shown in figure 51 shows a more rigorous example of figure 50, with increased noise suppression and more protection for remote applications. figure 52 shows an example of gain in the excitation circuit and remote feedback from the bridge. the ltc1043s provide voltage multiplication, providing 10v from a 5v reference with only 1ppm error. the amplifiers are used at unity gain and introduce very little error due to gain error or due to offset voltages. a 1 m v/ c offset voltage drift translates into 0.05ppm/ c gain error. simpler alterna- tives, with the amplifiers providing gain using resistor arrays for feedback, can produce results that are similar to bridge sensing schemes via attenuators. note that the amplifiers must have high open-loop gain or gain error will be a source of error. the fact that input offset voltage has relatively little effect on overall error may lead one to use low performance amplifiers for this application. note that the gain of a device such as an lf156, (25v/mv over temperature) will produce a worst-case error of C180ppm at a noise gain of 3, such as would be encountered in an inverting gain of 2, to produce C10v from a 5v reference. figure 49. bridge amplification using a single amplifier 0.1 f 5v ref + ref in + in gnd v cc 3 3 2 4 6 7 4 350 bridge 5 6 2410 f49 1, 7, 8, 9, 10, 15, 16 2 ltc2410 + ltc1050s8 5v 0.1 v r2 46.4k 20k 20k 175 1 f 10 f r1 4.99k () a v = 9.95 = r1 + r2 r1 + 175 + + 1 f +
ltc2410 40 applicatio s i for atio wu u u the error associated with the 10v excitation would be C80ppm. hence, overall reference error could be as high as 130ppm, the average of the two. figure 53 shows a similar scheme to provide excitation using resistor arrays to produce precise gain. the circuit is configured to provide 10v and C5v excitation to the bridge, producing a common mode voltage at the input to the ltc2410 of 2.5v, maximizing the ac input range for applications where induced 60hz could reach amplitudes up to 2v rms . the last two example circuits could be used where mul- tiple bridge circuits are involved and bridge output can be multiplexed onto a single ltc2410, via an inexpensive multiplexer such as the 74hc4052. figure 54 shows the use of an ltc2410 with a differential multiplexer. this is an inexpensive multiplexer that will contribute some error due to leakage if used directly with the output from the bridge, or if resistors are inserted as a protection mechanism from overvoltage. although the bridge output may be within the input range of the a/d and multiplexer in normal operation, some thought should be given to fault conditions that could result in full excitation voltage at the inputs to the multiplexer or adc. the use of amplification prior to the multiplexer will largely eliminate errors associated with channel leakage developing error voltages in the source impedance. figure 51. remote half bridge sensing with noise suppression on reference figure 50. remote half bridge interface 2410 f50 ref + ref in + in gnd v cc v s 2.7v to 5.5v 3 4 5 6 platinum 100 rtd r1 25.5k 0.1% 1, 7, 8, 9, 10, 15, 16 2 ltc2410 ref + ref in gnd v cc 5v 3 4 6 2410 f51 1, 7, 8, 9, 10, 15, 16 2 ltc2410 + ltc1050 5v platinum 100 rtd 560 r3 10k 5% r1 10k, 5% r2 10k 0.1% 1 f in + 5 10k 10k
ltc2410 41 applicatio s i for atio wu u u figure 52. ltc1043 provides precise 4x reference for excitation voltages 350 bridge 0.1 f 1 f 15v 15v 15v 38 14 7 4 13 12 11 10v 5v 15v u1 ltc1043 6 2 7 4 7 4 + ref + ref in + in gnd v cc 3 4 5 6 1, 7, 8, 9, 10, 15, 16 2410 f52 2 5v ltc2410 47 f 0.1 f 10v + + 17 5 15 6 18 3 2 u2 ltc1043 1 f film 8 14 7 4 13 12 11 * * * 5v u2 ltc1043 17 10v 10v lt1236-5 1k 33 q1 2n3904 0.1 f 15v 15v 15v 3 6 2 + 1k 33 10v 10v q2 2n3906 *flying capacitors are 1 f film (mkp or equivalent) see ltc1043 data sheet for details on unused half of u1 ltc1150 ltc1150 20 200 20 200 0.1 f 10 f +
ltc2410 42 applicatio s i for atio wu u u figure 53. use resistor arrays to provide precise matching in excitation amplifier figure 54. use a differential multiplexer to expand channel capability c1 0.1 f 15v 3 1 2 3 2 1 6 5 4 + ref + ref in + in gnd v cc 3 4 5 6 1, 7, 8, 9, 10, 15, 16 2410 f53 2 ltc2410 lt1236-5 rn1 10k 22 10v 350 bridge two elements varying rn1 10k q1 2n3904 1/2 lt1112 c2 0.1 f 15v ?v ?5v 15v 6 7 5 8 7 + rn1 10k rn1 is caddock t914 10k-010-02 q2, q3 2n3906 2 1/2 lt1112 rn1 10k 33 2 c3 47 f c1 0.1 f 5v 5v 8 4 20 20 + 2410 f54 ref + ref in + in 1, 7, 8, 9, 10, 15, 16 2 a0 a1 ltc2410 v cc gnd 13 3 6 12 47 f 14 1 5 10 16 5v 15 11 2 to other devices 4 9 8 5v + 74hc4052 3 4 5 6
ltc2410 43 typical applicatio s u sample driver for ltc2410 spi interface the ltc2410 has a very simple serial interface that makes interfacing to microprocessors and microcontrollers very easy. the listing in figure 56 is a simple assembler routine for the 68hc11 microcontroller. it uses port d, configuring it for spi data transfer between the controller and the ltc2410. figure 55 shows the simple 3-wire spi connection. the code begins by declaring variables and allocating four memory locations to store the 32-bit conversion result. this is followed by initializing port ds spi configuration. the program then enters the main sequence. it activates the ltc2410s serial interface by setting the ss output low, sending a logic low to cs. it next waits in a loop for a logic low on the data line, signifying end-of-conversion. after the loop is satisfied, four spi transfers are com- pleted, retrieving the conversion. the main sequence ends by setting ss high. this places the ltc2410s serial interface in a high impedance state and initiates another conversion. figure 55. connecting the ltc2410 to a 68hc11 mcu using the spi serial interface the performance of the ltc2410 can be verified using the demonstration board dc291a, see figure 57 for the schematic. this circuit uses the computers serial port to generate power and the spi digital signals necessary for starting a conversion and reading the result. it includes a labview application software program (see figure 58) which graphically captures the conversion results. it can be used to determine noise performance, stability and with an external source, linearity. as exemplified in the schematic, the ltc2410 is extremely easy to use. this demonstration board and associated software is available by contacting linear technology. ltc2410 sck sdo cs 13 12 11 sck (pd4) miso (pd2) ss (pd5) 68hc11 2410 f55
ltc2410 44 typical applicatio s u ***************************************************** * this example program transfers the ltc2410's 32-bit output * * conversion result into four consecutive 8-bit memory locations. * ***************************************************** *68hc11 register definition portd equ $1008 port d data register * " C , C , ss* ,csk ;mosi,miso,txd ,rxd" ddrd equ $1009 port d data direction register spsr equ $1028 spi control register * "spie,spe ,dwom,mstr;spol,cpha,spr1,spr0" spsr equ $1029 spi status register * "spif,wcol, C ,modf; C , C , C , C " spdr equ $102a spi data register; read-buffer; write-shifter * * ram variables to hold the ltc2410's 32 conversion result * din1 equ $00 this memory location holds the ltc2410's bits 31 - 24 din2 equ $01 this memory location holds the ltc2410's bits 23 - 16 din3 equ $02 this memory location holds the ltc2410's bits 15 - 08 din4 equ $03 this memory location holds the ltc2410's bits 07 - 00 * ********************** * start getdata routine * ********************** * org $c000 program start location init1 lds #$cfff top of c page ram, beginning location of stack ldaa #$2f C,C,1,0;1,1,1,1 * C, C, ss*-hi, sck-lo, mosi-hi, miso-hi, x, x staa portd keeps ss* a logic high when ddrd, bit 5 is set ldaa #$38 C,C,1,1;1,0,0,0 staa ddrd ss*, sck, mosi are configured as outputs * miso, txd, rxd are configured as inputs *ddrd's bit 5 is a 1 so that port d's ss* pin is a general output ldaa #$50 staa spcr the spi is configured as master, cpha = 0, cpol = 0 * and the clock rate is e/2 * (this assumes an e-clock frequency of 4mhz. for higher e- * clock frequencies, change the above value of $50 to a value * that ensures the sck frequency is 2mhz or less.) getdata pshx pshy psha ldx #$0 the x register is used as a pointer to the memory locations * that hold the conversion data ldy #$1000 bclr portd, y %00100000 this sets the ss* output bit to a logic * low, selecting the ltc2410 *
ltc2410 45 typical applicatio s u ********************************** * the next short loop waits for the * * ltc2410's conversion to finish before * * starting the spi data transfer * ********************************** * convend ldaa portd retrieve the contents of port d anda #%00000100 look at bit 2 * bit 2 = hi; the ltc2410's conversion is not * complete * bit 2 = lo; the ltc2410's conversion is complete bne convend branch to the loop's beginning while bit 2 remains high * * ******************** * the spi data transfer * ******************** * trflp1 ldaa #$0 load accumulator a with a null byte for spi transfer staa spdr this writes the byte in the spi data register and starts * the transfer wait1 ldaa spsr this loop waits for the spi to complete a serial transfer/exchange by reading the spi status register bpl wait1 the spif (spi transfer complete flag) bit is the spsr's msb * and is set to one at the end of an spi transfer. the branch * will occur while spif is a zero. ldaa spdr load accumulator a with the current byte of ltc2410 data that was just received staa 0,x transfer the ltc2410's data to memory inx increment the pointer cpx #din4+1 has the last byte been transferred/exchanged? bne trflp1 if the last byte has not been reached, then proceed to the * next byte for transfer/exchange bset portd,y %00100000 this sets the ss* output bit to a logic high, * de-selecting the ltc2410 pula restore the a register puly restore the y register pulx restore the x register rts figure 56. this is an example of 68hc11 code that captures the ltc2410s conversion results over the spi serial interface shown in figure 55
ltc2410 46 typical applicatio s u figure 57. 24-bit a/d demo board schematic figure 58. display graphic jp4 jumper 2 3 1 1 p1 db9 6 9 2 7 3 8 4 5 + 2410 f57 r1 10 w j1 v ext d1 bav74lt1 c4 100 f 16v v out v in gnd u2 lt1236acn8-5 u3e 74hc14 62 11 10 14 3 13 4 12 5 16 6 15 10 9 8 7 1 11 2 3 21 1 1 4 u3f 74hc14 13 12 u3b 74hc14 3 4 u3a 74hc14 1 2 u3c 74hc14 6 5 u3d 74hc14 8 3 2 1 9 + c3 10 f 35v v out v in gnd u1 lt1460acn8-2.5 62 4 + c1 10 f 35v + c2 22 f 25v c6 0.1 f + c5 10 f 35v v cc v cc v cc j2 gnd j3 v cc 1 1 j5 gnd 1 j7 ref banana jack 1 j6 ref + banana jack 1 j4 v ext banana jack 1 j8 v in + banana jack 1 j9 v in banana jack 1 j10 gnd banana jack r3 51k r4 51k r6 3k q1 mmbt3904lt1 r5 49.9 r7 22k r8 51k ref + f o ref sck v in + sdo v in gnd gnd gnd cs v cc gnd gnd gnd gnd jp3 jumper 2 3 1 c7 0.1 f bypass cap for u3 notes: install jumber jp1 at pin 1 and pin 2 install jumber jp2 at pin 1 and pin 2 install jumber jp3 at pin 1 and pin 2 v cc jp5 jumper 1 2 jp1 jumper 2 3 1 jp2 jumper 2 1 r2 3 u4 ltc2410cgn
ltc2410 47 package descriptio u dimensions in inches (millimeters) unless otherwise noted. pcb layout a d fil uw silkscreen top top layer gn package 16-lead plastic ssop (narrow 0.150) (ltc dwg # 05-08-1641) gn16 (ssop) 1098 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side 0.016 ?0.050 (0.406 ?1.270) 0.015 0.004 (0.38 0.10) 45 0 ?8 typ 0.007 ?0.0098 (0.178 ?0.249) 0.053 ?0.068 (1.351 ?1.727) 0.008 ?0.012 (0.203 ?0.305) 0.004 ?0.0098 (0.102 ?0.249) 0.0250 (0.635) bsc 12 3 4 5 6 7 8 0.229 ?0.244 (5.817 ?6.198) 0.150 ?0.157** (3.810 ?3.988) 16 15 14 13 0.189 ?0.196* (4.801 ?4.978) 12 11 10 9 0.009 (0.229) ref information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
ltc2410 48 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com ? linear technology corporation 2000 sn2410 2410fs lt/tp 1100 4k ? printed in usa related parts pcb layout a d fil uw part number description comments lt1019 precision bandgap reference, 2.5v, 5v 3ppm/ c drift, 0.05% max lt1025 micropower thermocouple cold junction compensator 80 m a supply current, 0.5 c initial accuracy ltc1043 dual precision instrumentation switched capacitor precise charge, balanced switching, low power building block ltc1050 precision chopper stabilized op amp no external components 5 m v offset, 1.6 m v p-p noise lt1236a-5 precision bandgap reference, 5v 0.05% max, 5ppm/ c drift lt1460 micropower series reference 0.075% max, 10ppm/ c max drift, 2.5v, 5v and 10v versions ltc2400 24-bit, no latency ds adc in so-8 0.3ppm noise, 4ppm inl, 10ppm total unadjusted error, 200 m a ltc2401/ltc2402 1-/2-channel, 24-bit, no latency ds adc in msop 0.6ppm noise, 4ppm inl, 10ppm total unadjusted error, 200 m a ltc2404/ltc2408 4-/8-channel, 24-bit, no latency ds adc 0.3ppm noise, 4ppm inl, 10ppm total unadjusted error, 200 m a ltc2411 24-bit, no latency ds adc in msop 1.45 m v rms noise, 4ppm inl ltc2413 24-bit, no latency ds adc simultaneous 50hz/60hz rejection, 800nv rms noise ltc2420 20-bit, no latency ds adc in so-8 1.2ppm noise, 8ppm inl, pin compatible with ltc2400 ltc2424/ltc2428 4-/8-channel, 20-bit, no latency ds adcs 1.2ppm noise, 8ppm inl, pin compatible with ltc2404/ltc2408 bottom layer

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