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rev. 0.9 6/12 copyright ? 2012 by silicon laboratories si4770/77-a20 this information applies to a product under dev elopment. its characteristics and specifications are s ubject to change without n otice. si4770/77-a20 h igh -p erformance c onsumer e lectronics b roadcast r adio r eceiver and hd r adio t uner features applications description the si4770/77-a20 broadcast receiver and hd radio tuner (si4777 only) employs an advanced, proven digital low-if architecture to bring outstanding receiver performance to high-performance consumer electronics. ? worldwide fm band support (64?108 mhz) ? worldwide am band support (520?1710 khz) ? am/fm hd radio support (si4777 only) ? comprehensive signal quality metrics: rssi, snr, multipath interference, frequency offset, adjacent channel rssi, frequency deviation, and image rssi ? advanced patented rds soft- decision decoder ? advanced, patented fm channel equalizer for multipath interference ? dynamic am/fm channel bandwidth control ? programmable am/fm soft mute ? fm stereo-mono blend ? fm hi-blend control ? am/fm hi-cut control ? am lo-cut filter ? l/r analog and digital (i 2 s) audio outputs ? digital low-if architecture ? frequency synthesizer with fully integrated pll-vco ? fully integrated am/fm front-end including high performance lna, agc with integrated resistor and capacitor banks, and rf and if peak detectors ? integrated crystal oscillator ? digital (i 2 s) zero-if am/fm i/q outputs (si4777 only) ? 1.2 to 5 v power supplies ? qfn 40-pin, 6x6x0.85 mm ?? pb-free/rohs compliant ? audio/video receivers ? consumer electronics ? boom boxes ? home theater systems patents pending ordering information: see page 49. pin assignments si4770/77-a20 nc/iqclk 23 nc/iqfs 24 nc/iout 25 nc/qout 26 dout 27 dfs 28 dclk 29 nc/blend 30 nc 8 fmi 7 fmo 6 rfreg 5 rfgnd 4 fmxin 3 fmxip 2 nc 1 ami 10 nc 9 vio1 19 vd 20 a0 11 a1/intb 12 nc/dclk2 13 nc/dout2 14 rstb 15 sda 16 scl 17 intb/dfs2 18 fmagc1 40 fmagc2 39 gpio1 38 gpio2 37 dacref 36 xtal1 35 rclk/ xtal2 34 rout 33 lout/ mpxout 32 va 31 dbyp 21 vio2 22 gnd pad
si4770/77-a20 2 rev. 0.9 functional block diagram ami lna xtal1 fmxip fmi clk gen xtal2/ rclk dsp fmo fmagc1 fmagc2 cntrl iout rf pkd qout iqfs iqclk dout dfs dclk rstb fmxin a1 sda a0 lout/ mpxout rout if pkd rds adc adc dac dac si4770/77 0/90 vio2 rf pkd scl lna rf pkd reg rfreg vio1 intb r l rfgnd
si4770/77-a20 rev. 0.9 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3. bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 4.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 4.2. clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.3. tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.4. fm receiver fr ont-end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.5. am receiver front-end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.6. received signal qualifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.7. digital audio interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.8. channel equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.9. digital zif i/q interfac e (si4777 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.10. iboc blend mode for hd radio (s i4777 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.11. stereo audio processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.12. de-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.13. analog audio and fm mpx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.14. soft mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 4.15. am/fm dynamic bandwidth control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.16. seek and valid st ation qualification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.17. am hi-cut control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.18. fm hi-cut control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.19. fm hi-blend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 4.20. am lo-cut . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5. rds/rbds advanced processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6. programming section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7. i 2 c control bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 7.1. i 2 c device address selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 7.2. i 2 c standard operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8. reset, powerup, and powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9. pin descriptions: si4770/77-a20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11. package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 12. pcb land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13. top marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 13.1. si4770/77-a20 top marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 13.2. top marking explana tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
si4770/77-a20 4 rev. 0.9 1. electrical specifications table 1. recommended operation conditions* parameter symbol test condition min typ max unit analog supply voltage v a ?4.555.5v digital supply voltage v d ?2.73.33.6v interface supply voltage v io1 ?1.73.33.6v v io2 ?1.23.33.6v *note: all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typical values apply at v d =3.3v, v io1 =3.3v, v io2 =3.3v, v a = 5 v, and 25 c unless otherwise stated. parameters are tested in production unless otherwise stated. table 2. dc characteristics (t amb = ?40 to 85 c, v a = 4.5 to 5.5 v, v d = 2.7 to 3.6 v, v io1 = 1.7 to 3.6 v, v io2 = 1.2 to 3.6 v) parameter symbol test condition min typ max unit fm mode total supply power 671 850 1049 mw v a supply current i va 121 130 139 ma v d supply current i vd 47 60 79 ma v a supply power down current i va 20 90 170 a v d supply power down current i vd 52050a am mode total supply power 707 900 1100 mw v a supply current i va 129 140 147 ma v d supply current i vd 47 60 81 ma v a supply power down current i va 20 90 170 a v d supply power down current i vd 52050a *note: see "7. i2c control bus" on page 44.
si4770/77-a20 rev. 0.9 5 interface supplies v io1 supply current i vio1 0.1 0.5 0.82 ma v io2 supply current i vio2 0.1 0.2 0.5 ma v io1 supply power down current* i pd 150 250 420 a v io2 supply power down current* i pd 520150a inputs pins scl, sda, rstb, a0, a1 high level input voltage v ih 0.7 x v io1 ?? v low level input voltage v il ? ? 0.3xv io1 v high level input current i ih v in =v i01 = 3.6 v ?10 ? 10 a low level input current i il v in =0=v, v i01 =3.6v ?10 ? 10 a input pins dclk, dfs high level input voltage v ih 0.7 x v io2 ?? v low level input voltage v il ? ? 0.3 x v io2 v high level input current i ih v in =v i02 =3.6v ?10 ? 10 a low level input current i il v in =0v, v i02 =3.6v ?10 ? 10 a input pins gpio1, gpio2 high level input voltage v ih gpio1 and gpio2 are internally regu- lated at 3.6 v 2.52 ? ? v low level input voltage v il ??1.08v high level input current i ih v in =3.6v ?10 ? 10 a low level input current i il v in =0v ?10 ? 10 a output pins intb high level output voltage v oh output is common drain output with internal 10 k ? pull- up to v io1 0.8xv io1 ?? v low level output voltage v ol i out = ?500 a? ?0.2xv io1 v table 2. dc characteristics (continued) (t amb = ?40 to 85 c, v a = 4.5 to 5.5 v, v d = 2.7 to 3.6 v, v io1 = 1.7 to 3.6 v, v io2 = 1.2 to 3.6 v) parameter symbol test condition min typ max unit *note: see "7. i2c control bus" on page 44.
si4770/77-a20 6 rev. 0.9 output pins sda high level output voltage v oh output is common drain output with external 4.7 k ? pull-up to v io1 0.8xv io1 ?? v low level output voltage v ol i out = ?500 a? ?0.2xv io1 v output pins gpio1, gpio2 high level output voltage v oh gpio1 and gpio2 are internally regu- lated at 3.6 v, iout = +500 a 2.88 ? ? v low level output voltage v ol i out = ?500 a? ? 0.72 v output pins iqclk, iqfs, iout, qout, dfs, dclk, dout high level output voltage v oh i out = 500 a 0.8 x v io2 ?? v low level output voltage v ol i out = ?500 a ? ? 0.2 x v io2 v table 2. dc characteristics (continued) (t amb = ?40 to 85 c, v a = 4.5 to 5.5 v, v d = 2.7 to 3.6 v, v io1 = 1.7 to 3.6 v, v io2 = 1.2 to 3.6 v) parameter symbol test condition min typ max unit *note: see "7. i2c control bus" on page 44.
si4770/77-a20 rev. 0.9 7 figure 1. digital audio table 3. digital audio interface characteristics* (t amb = ?40 to 85 c, v a = 4.5 to 5.5 v, v d = 2.7 to 3.6 v, v io1 = 1.7 to 3.6 v, v io2 = 1.2 to 3.6 v) parameter symbol test condition min typ max unit dclk input cycle time t cyc: dclk 70 ? ? ns dclk input pulse width high t hi: dclk 0.4 x t cyc:dclk ? 0.6 x t cyc:dclk ns dclk input pulse width low t lo: dclk 0.4 x t cyc:dclk ? 0.6 x t cyc:dclk ns dfs setup time t su:dfs 10 ? ? ns dfs hold time t hd:dfs 5? ? ns dout output delay t pd:dout 0 ? 35 ns capacitive loading c b vio 2 < 1.33 v ? ? 10 pf vio 2 > 1.33 v ? ? 15 *note: guaranteed by characterization. dclk in dfs in dout out t cyc:dclk t hi:dclk t lo:dclk t hd:dfs t pd:dout t su:dfs
si4770/77-a20 8 rev. 0.9 figure 2. digital zero-if i/q table 4. digital zero-if i/q interface characteristics (si4777 only) 1 (t amb = ?40 to 85 c, v a = 4.5 to 5.5 v, v d = 2.7 to 3.6 v, v io1 = 1.7 to 3.6 v, v io2 = 1.2 to 3.6 v) parameter symbol test condition min typ max unit iqclk output cycle time t cyc:iqclk 0.8 x per per 2 1.2 x per ns iqclk output pulse width high t hi:iqclk 0.22 x per ? 0.59 x per ns iqclk output pulse width low t lo:iqclk 0.41 x per ? 0.78 x per ns iqfs output delay t pd:iqfs 0 ? (0.5 x per) + 18 ns iqfs output se tup to iqclk rise 3 t su:iqfs (0.5 x per) ? 18 ? ? ns iout output delay t pd:iout 0 ? (0.5 x per) + 18 ns qout output delay t pd:qout 0 ? (0.5 x per) + 18 ns iout output setup to iqclk rise 3 t su:iout (0.5 x per) ? 18 ? ? ns qout output setup to iqclk rise 3 t su:qout (0.5 x per) ? 18 ? ? ns notes: 1. guaranteed by characterization. 2. per is the iqclk i/q bit clock period. refer to table 15 on page 35 for iqclk bit clock frequencies. 3. minimum time the si4770/77-a20 will produce betwe en valid output and the next rising edge of iqclk iqclk out iqfs out t cyc:iqclk max t cyc:iqclk min t hi:iqclk min t lo:iqclk max t hi:iqclk max t lo:iqclk min t pd:iqfs max t pd:iqfs min t su:iqfs iout out t pd:iout max t pd:iout min t su:iout qout out t pd:qout max t pd:qout min t su:qout
si4770/77-a20 rev. 0.9 9 table 5. reference clock and crystal characteristics parameter symbol test condition min typ max unit reference clock, pin rclk rclk supported frequencies ? 36.4 37.8 37.209375 ?mhz rclk frequency to l e r a n c e ?100 ? 100 ppm rclk = 36.4 mhz, 37.8 mhz, 37.209375 mhz phase noise 100 hz offset ? ? ?86 dbc/hz 1 khz offset ? ? ?101 dbc/hz 10 khz offset ? ? ?108 dbc/hz 100 khz offset ? ? ?122 dbc/hz input capacitance ? 7 ? pf input voltage ac coupling capacitor = 1 f square wave input 400 mv pp ac coupling capacitor = 1 f sine wave input 300 ? 900 mv pp crystal oscillator, pins xtal1, xtal2 crystal frequency ? 36.4 37.8 37.209375 ?mhz crystal frequency to l e r a n c e ?100 ? 100 ppm load capacitance, pro- grammable, each pin to gnd 5 ? 21.8 pf
si4770/77-a20 10 rev. 0.9 table 6. i 2 c control interface characteristics (t amb = ?40 to 85 c, v a = 4.5 to 5.5 v, v d = 2.7 to 3.6 v, v io1 = 1.7 to 3.6 v, v io2 = 1.2 to 3.6 v) parameter symbol test condition min typ max unit pins scl, sda scl frequency f scl 0 ? 400 khz scl low time t low 1.3 ? ? s scl high time t high 0.6 ? ? s scl input to sda ? setup (start) t su:sta 0.6 ? ? s scl input from sda ? hold (start) t hd:sta 0.6 ? ? s sda input to scl ? setup t su:dat 100 ? ? ns sda input from scl ?? hold t hd:dat 0 ? 900 ns sda output delay t pd:dat 300 ? 900 ns scl input to sda ?? setup (stop) t su:sto 0.6 ? ? s stop to start time t buf 1.3 ? ? s sda output fall time t f:out ? 250 ns sda input, scl rise/fall time t f:in, t r:in ? 300 ns capacitive loading c b ? ? 50 pf pulse width rejected by input filter t sp ? ? 50 ns 20 0.1 c b 1pf ---------- - + 20 0.1 c b 1pf ---------- - +
si4770/77-a20 rev. 0.9 11 figure 3. i 2 c control interface read and write timing parameters figure 4. i 2 c control interface read and write timing diagram scl 70% 30% sda 70% 30% start start stop t f:in t r:in t low t high t hd:sta t su:sta t su:sto t sp t buf t su:dat t r:in t hd:dat t f:in, t f:out t pd:dat scl sda (write) start stop address + r/w ack data ack data ack a6-a0, 0 command 7-0 arg1 7-0 sda (read) start stop address + r/w ack data ack data ack a6-a0, 1 status 7-0 response 7-0
si4770/77-a20 12 rev. 0.9 table 7. fm receiver characteristics (t amb = ?40 to 85 c, v a = 4.5 to 5.5 v, v d = 2.7 to 3.6 v, v io1 = 1.7 to 3.6 v, v io2 = 1.2 to 3.6 v. typical values measured at t amb = 25 c, fm modulation (l = r), f mod = 1 khz, f dev = 22.5 khz, deemphasis = 75 sec, rf level = 60 dbv, and f rf = 98 mhz in application circuit unless otherwise specified) parameter test condition min typ max unit input frequency 64 ? 108 mhz frequency step resolution 10 ? 200 khz powerup time 1,2 rclk or crystal = 36.4 mhz, 37.8 mhz, 37.209375 mhz ??100 ms tune time 1 ?1.5 ? ms seek time/channel 1 at lout and rout pins ? 20 ? ms max frequency deviation 1 audio thd <1%, over-deviation handling enabled ?150 ? khz rf agc range ? 40 ? db agc gain resolution 3 ?2? db rf agc threshold accuracy 3 2? db if agc threshold accuracy 3 1? db following fm receiver specifications refer to si4770/77-a20 application circuit input ip3 6 blockers at 400/800 khz offset agc disabled (max rf gain) 115 117 ? dbv sensitivity 6 audio sinad = 26 db agc disabled (max rf gain) ? ?3.5 ?2 dbv image rejection 1 deviation = 22.5 khz 65 70 ? db adjacent channel rejection 1,6 audio sinad = 26 db desired = 40dbv, f mod = 1 khz, f dev = 22.5 khz undesired at 100 khz offset, f mod =400hz, f dev = 22.5 khz 63 65 ? db notes: 1. guaranteed by characterization. 2. measured at t amb =25c. 3. guaranteed by design. 4. ip3 measured at the fmxip and fmxin pins reflects ip 3 for mixer stage and all subsequent downstream blocks. 5. refer to fm test circuit in figure 5. 6. no a-weighting. noise integrated from 30 hz to 15 khz for audio sinad and snr measurements. 7. input resistance is software configurable. 8. ip3 measured at the fmi input pin reflects ip3 for fmi lna stage. 9. rds synchronization persistence is the minimum rf level at which the tuner loses synchronization to the rds pi code as the rf level decreases from high to low levels. 10. rds synchronization stability is the minimum rf level at wh ich the tuner achieves synchronization to the rds pi code as the rf level increases from low to high levels. 11. noise integrated from 30 hz to 120 khz for audio sinad and snr measurements.
si4770/77-a20 rev. 0.9 13 alternate channel rejection 6 audio sinad = 26 db desired = 40 dbv, f mod = 1 khz, f dev = 22.5 khz undesired at 200 khz offset, f mod =400hz, f dev = 22.5 khz 65 72 ? db thd f dev =75khz ? 0.05 0.1 % mono (s+n)/n 6 66 75 ? db stereo (s+n)/n 6 stereo modulation (l = 1, r = 0), deviation = 67.5 khz, pilot deviation = 6.75 khz 64 70 ? db am suppression 1 am: m = 0.3/fmod = 1 khz, rf level = 60 dbv 50 55 ? db de-emphasis time constant 3 70 75 80 sec 45 50 54 sec l/r imbalance deviation = 75 khz ?1 ? 1 db stereo separation stereo modulation (l = 1, r = 0), deviation = 67.5 khz, pilot deviation = 6.75 khz 40 43 ? db stereo thd stereo modulation (l = 1, r = 0), deviation = 67.5 khz, pilot deviation = 6.75 khz ?0.10.2 % pilot signal rejection 1 stereo modulation (l = 1, r = 0), deviation = 67.5 khz, pilot deviation = 6.75 khz ?55? db rds sensitivity 1 ? f = 2 khz, rds bler < 5% ? 13 14.5 dbv rds synchronization time 1 ? f=2khz rf input = 60 dbv ?70? ms rds pi lock time 1 ? f=2khz rf input = 60 dbv ?85? ms table 7. fm receiver characteristics (continued) (t amb = ?40 to 85 c, v a = 4.5 to 5.5 v, v d = 2.7 to 3.6 v, v io1 = 1.7 to 3.6 v, v io2 = 1.2 to 3.6 v. typical values measured at t amb = 25 c, fm modulation (l = r), f mod = 1 khz, f dev = 22.5 khz, deemphasis = 75 sec, rf level = 60 dbv, and f rf = 98 mhz in application circuit unless otherwise specified) parameter test condition min typ max unit notes: 1. guaranteed by characterization. 2. measured at t amb =25c. 3. guaranteed by design. 4. ip3 measured at the fmxip and fmxin pins reflects ip 3 for mixer stage and all subsequent downstream blocks. 5. refer to fm test circuit in figure 5. 6. no a-weighting. noise integrated from 30 hz to 15 khz for audio sinad and snr measurements. 7. input resistance is software configurable. 8. ip3 measured at the fmi input pin reflects ip3 for fmi lna stage. 9. rds synchronization persistence is the minimum rf level at which the tuner loses synchronization to the rds pi code as the rf level decreases from high to low levels. 10. rds synchronization stability is the minimum rf level at wh ich the tuner achieves synchronization to the rds pi code as the rf level increases from low to high levels. 11. noise integrated from 30 hz to 120 khz for audio sinad and snr measurements.
si4770/77-a20 14 rev. 0.9 fm mixer inputs: pins fmxip, fmxin maximum rf input voltage 3 1 db compression point of mixer ? 112 ? dbv mixer input resistance 3 ?8? k ? mixer input capacitance 3 ?6? pf ip3 4,5,6 blockers at 400/800 khz offset, max gain (agc disabled) ?123 ? dbv sensitivity 5,6 audio sinad = 26 db max gain (agc disabled) ?3.5 ?dbv fm resistor banks: fmagc1, fmagc2 fmagc1 min ? 2.5 ? ? fmagc1 max ? 800 ? ? fmagc1 step size maximum parallel resistance change ? 800 ? ? fmagc2 min ? 2.5 ? ? fmagc2 max ? 800 ? ? fmagc2 step size maximum parallel resistance change ? 800 ? ? fm lna: pins fmi, fmo single receiver mode fmi input resistance 3,7 ?50? ? fmi input capacitance 3 ?2? pf fmi return loss 3 64 mhz < f < 108 mhz ? 15 ? db fmi input referred noise 3 ?0.73? fmi lna ip3 3,8 blockers at 400/800 khz offset, max gain ? 128 ? dbv table 7. fm receiver characteristics (continued) (t amb = ?40 to 85 c, v a = 4.5 to 5.5 v, v d = 2.7 to 3.6 v, v io1 = 1.7 to 3.6 v, v io2 = 1.2 to 3.6 v. typical values measured at t amb = 25 c, fm modulation (l = r), f mod = 1 khz, f dev = 22.5 khz, deemphasis = 75 sec, rf level = 60 dbv, and f rf = 98 mhz in application circuit unless otherwise specified) parameter test condition min typ max unit notes: 1. guaranteed by characterization. 2. measured at t amb =25c. 3. guaranteed by design. 4. ip3 measured at the fmxip and fmxin pins reflects ip 3 for mixer stage and all subsequent downstream blocks. 5. refer to fm test circuit in figure 5. 6. no a-weighting. noise integrated from 30 hz to 15 khz for audio sinad and snr measurements. 7. input resistance is software configurable. 8. ip3 measured at the fmi input pin reflects ip3 for fmi lna stage. 9. rds synchronization persistence is the minimum rf level at which the tuner loses synchronization to the rds pi code as the rf level decreases from high to low levels. 10. rds synchronization stability is the minimum rf level at wh ich the tuner achieves synchronization to the rds pi code as the rf level increases from low to high levels. 11. noise integrated from 30 hz to 120 khz for audio sinad and snr measurements. nv/ hz
si4770/77-a20 rev. 0.9 15 fmo output resistance 3 nominal fmi to fmo gain = 8 db, source load = 50 ? ?125 ? ? fmo output capacitance 3 ?2? pf dual receiver mode fmi input resistance 7,3 ?100 ? ? fmi input capacitance 3 ?1.5 ? pf fmi return loss 3 64 mhz < f < 108 mhz ? 15 ? db fmi input referred noise 3 ?1.20? fmi lna ip3 3,8 blockers at 400/800 khz offset, max gain ? 126 ? dbv fmo output resistance 3 nominal fmi to fmo gain = 8db, source load = 50 ? ?250 ? ? fmo output capacitance 3 ?2? pf audio outputs: pins lout and rout audio frequency response low 1,2 3 db ? ? 30 hz audio frequency response high 1,2 3 db 15 ? ? khz output load resistance 3 at lout and rout pins 10 k ? ? ? output load capacitance 3 at lout and rout pins ? ? 50 pf output voltage deviation = 22.5 khz 99 112 125 mvrms power supply rejection ratio (psrr) 3 100 hz ripple on power supply lines. ripple voltage = 100 mv pp of power supply voltage ?45? db table 7. fm receiver characteristics (continued) (t amb = ?40 to 85 c, v a = 4.5 to 5.5 v, v d = 2.7 to 3.6 v, v io1 = 1.7 to 3.6 v, v io2 = 1.2 to 3.6 v. typical values measured at t amb = 25 c, fm modulation (l = r), f mod = 1 khz, f dev = 22.5 khz, deemphasis = 75 sec, rf level = 60 dbv, and f rf = 98 mhz in application circuit unless otherwise specified) parameter test condition min typ max unit notes: 1. guaranteed by characterization. 2. measured at t amb =25c. 3. guaranteed by design. 4. ip3 measured at the fmxip and fmxin pins reflects ip 3 for mixer stage and all subsequent downstream blocks. 5. refer to fm test circuit in figure 5. 6. no a-weighting. noise integrated from 30 hz to 15 khz for audio sinad and snr measurements. 7. input resistance is software configurable. 8. ip3 measured at the fmi input pin reflects ip3 for fmi lna stage. 9. rds synchronization persistence is the minimum rf level at which the tuner loses synchronization to the rds pi code as the rf level decreases from high to low levels. 10. rds synchronization stability is the minimum rf level at wh ich the tuner achieves synchronization to the rds pi code as the rf level increases from low to high levels. 11. noise integrated from 30 hz to 120 khz for audio sinad and snr measurements. nv/ hz
si4770/77-a20 16 rev. 0.9 fm mpx output: pins mpxout output voltage 1 f rf = 83 mhz, rf level = 65 dbv, f dev = 3 khz, f mod =76khz unless otherwise noted 14 16 ? mvrms output load resistance 3 ?10? k ? output load capacitance 3 ?50? pf psrr 3 100 hz ripple on power supply lines. ripple voltage = 100 mv pp of power supply volt- age ?45? db bandwidth 1 110 ? ? khz following fm mpx specifications refer to si4770/77-a20 application circuit (s+n)/n 1,11 f rf = 83 mhz, rf level = 65 dbv, f dev = 3 khz, f mod =76khz unless otherwise noted 25 30 ? db sensitivity 1,11 f rf =83mhz, f dev = 3 khz, f mod =76khz unless otherwise noted, sinad = 5 db ?1925dbv table 7. fm receiver characteristics (continued) (t amb = ?40 to 85 c, v a = 4.5 to 5.5 v, v d = 2.7 to 3.6 v, v io1 = 1.7 to 3.6 v, v io2 = 1.2 to 3.6 v. typical values measured at t amb = 25 c, fm modulation (l = r), f mod = 1 khz, f dev = 22.5 khz, deemphasis = 75 sec, rf level = 60 dbv, and f rf = 98 mhz in application circuit unless otherwise specified) parameter test condition min typ max unit notes: 1. guaranteed by characterization. 2. measured at t amb =25c. 3. guaranteed by design. 4. ip3 measured at the fmxip and fmxin pins reflects ip 3 for mixer stage and all subsequent downstream blocks. 5. refer to fm test circuit in figure 5. 6. no a-weighting. noise integrated from 30 hz to 15 khz for audio sinad and snr measurements. 7. input resistance is software configurable. 8. ip3 measured at the fmi input pin reflects ip3 for fmi lna stage. 9. rds synchronization persistence is the minimum rf level at which the tuner loses synchronization to the rds pi code as the rf level decreases from high to low levels. 10. rds synchronization stability is the minimum rf level at wh ich the tuner achieves synchronization to the rds pi code as the rf level increases from low to high levels. 11. noise integrated from 30 hz to 120 khz for audio sinad and snr measurements.
si4770/77-a20 rev. 0.9 17 figure 5. fm test circuit for mixer input ip3 and sensitivity measurement table 8. am receiver characteristics (t amb = ?40 to 85 c, v a = 4.5 to 5.5 v, v d = 2.7 to 3.6 v, v io1 = 1.7 to 3.6 v, v io2 = 1.2 to 3.6 v. typical values measured at t amb = 25 c, am modulation = 30%, f mod = 1 khz, rf level = 74 dbv, and f rf = 1 mhz unless otherwise specified) parameter test cond ition min typ max unit input frequency 520 ? 1710 khz frequency step resolution 1 ? 10 khz powerup time 1,2 rclk or crystal = 36.4 mhz, 37.8 mhz, 37.209375 mhz ? ? 100 ms tune time 1 ?15 ? ms seek time/channel 1 at lout and rout pins ? 55 ? ms maximum rf input voltage 1,2 mod = 90%, fmod = 1 khz, sinad = 57 db ? 93 ? dbv image rejection 1,3 68 72 ? db adjacent channel rejection 1,3 sinad = 20 db desired = 40 dbv, f mod = 1 khz, mod = 30% undesired at 9 khz offset, f mod =400hz, mod = 30% 57 62 ? db alternate channel rejection 1,3 sinad = 20 db desired = 40dbv, f mod = 1 khz, mod = 30% undesired at 18 khz offset, f mod =400hz, mod = 30% 59 62 ? db ip3 1,3 blockers at 40/80 khz, agc disabled (max gain) 110 120 ? dbv notes: 1. guaranteed by characterization. 2. measured at t amb =25c. 3. no a-weighting. noise integrated from 30 hz to 15 khz for audio sinad and snr measurements. 4. guaranteed by design. 50 ? signal generator fmxip fmxin si477x
si4770/77-a20 18 rev. 0.9 ip2 1,3 desired=700khz, undesired = 1000 khz, 1700 khz agc disabled (max gain) 142 146 ? dbv rf agc range ? 50 ? db agc step resolution 2 db rf agc threshold accuracy 4 ?2 ? db if agc threshold accuracy 4 ?2 ? db sensitivity 1,3 sinad = 20 db, agc disabled (max rf gain) ? 14 17 dbv emf thd 1,3 mod = 30% ? 0.1 ? % mod = 90% ? 0.2 ? % audio snr 1,3 mod = 30% 60 65 ? db antenna inductance 3 180 ? 540 h audio outputs: pins lout and rout audio output resistance load 4 10k ? ? ? audio output capacitance load 4 single ended ? ? 50 pf audio output voltage 96 108 121 mvrms psrr at audio output pins 4 ripple test should be for 100 hz ripple on power supply lines ripple voltage = 100 mv pp of power supply voltage ?45 ? db table 8. am receiver characteristics (continued) (t amb = ?40 to 85 c, v a = 4.5 to 5.5 v, v d = 2.7 to 3.6 v, v io1 = 1.7 to 3.6 v, v io2 = 1.2 to 3.6 v. typical values measured at t amb = 25 c, am modulation = 30%, f mod = 1 khz, rf level = 74 dbv, and f rf = 1 mhz unless otherwise specified) parameter test cond ition min typ max unit notes: 1. guaranteed by characterization. 2. measured at t amb =25c. 3. no a-weighting. noise integrated from 30 hz to 15 khz for audio sinad and snr measurements. 4. guaranteed by design.
si4770/77-a20 rev. 0.9 19 table 9. thermal conditions parameter symbol test conditions min typ max unit ambient temperature t amb ? ?40 25 85 c junction temperature t j ???115c delta from junction to ambient * ja ??27?c/w *note: the ja is layout-dependent, and, theref ore, pcb layout must provide adequate heat-sink capability. the ja is specified assuming adequate ground plane. table 10. absolute maximum ratings 1 parameter symbol min max unit analog supply voltage v a ?0.5 5.9 v digital supply voltage v d ?0.5 3.9 v i/o 1 supply voltage v io1 ?0.5 3.9 v i/o 2 supply voltage v io2 ?0.5 3.9 v i/o 1 input current 2 i in1 ?10 10 a i/o 1 input voltage 2 v in1 ?0.3 v i01 + 0.3 v i/o 2 input current 3 i in2 ?10 10 a i/o 2 input voltage 3 v in2 ?0.3 v i02 + 0.3 v operating temperature t op ?40 95 c storage temperature t stg ?55 150 c am rf input level 4 v rfin ?1 v a + 1 v am rf input current 4 i rfin ?100 100 ma fm rf input level 5 v rfin ?1 1 v fm rf input current 5 i rfin ?100 100 ma hbm esd v hbm ?2 2 kv mm esd v mm ?200 200 v cdm esd 6 v cdm ?500 500 v cdm esd 7 v cdm ?750 750 v notes: 1. permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as specified in the operationa l sections of this data sheet. exposure beyond recommended operating conditions for extended per iods may affect device reliability. 2. for input pins scl, sda, rstb, a0, a1, gpio1, gpio2. 3. for input pins dclk and dfs. 4. at rf input pins am1. 5. at rf input pins fmxin, fm xip, fmi, fmagc1, fmagc2. 6. all pins. 7. corner pins.
si4770/77-a20 20 rev. 0.9 2. typical application schematic figure 6 shows the proposed application schematic. rf rf rf rf x1 3.2x2.5 c7 2.2nf rf t1 4 2 3 16 1:1 rf c8 1nf c9 62pf l1 220nh l3 150nh j1 sma_edge rf u1 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 fmxip fmxin gndrf rfreg fmo fmi nc ami a0 a1 rstb sda scl intb vio1 vd dbyp vio2 iqclk iqfs iout qout dout dfs dclk va lout rout xtal2 xtal1 dacref gpio2 gpio1 fmagc2 fmagc1 gnd_pad nc nc nc nc nc si4770/77 t2 5 4 3 1 sl755tf01 silabs l2 47nh c10 18pf c5 2.2nf jp1 100pf c1 c2 2.2nf c3 2.2nf c20 10uf c4 2.2nf d1 esd_diode 10uf c6 10nh l9 0.1uf c21 d3 esd_diode rf rf 0.1uf c13 vd gnd va iqclk lout vio2 dclk qout vio1 dout dfs rout iout iqfs intb_1 scl rstb_1 sda analog audio/ mpx /mpx digital audio digital iq/zif (si4777 only) host mcu airloop ant fm ant figure 6. application circuit
si4770/77-a20 rev. 0.9 21 3. bill of materials table 11. si4770/77-a20 bill of materials item qty ref package value mfr part number 1 1 t2 transformer, thru-hole silicon laboratories sl755tf01 2 1 t1 balun, 1:1, toko toko 458pt1566 3 2 c13, c21 cap, sm, 0402 0.1 f murata grm155r71a204ka01d 5 1 c1 cap, sm, 0402 100 pf murata grm1555c1h101jz01 6 1 c10 cap, sm, 0402 18 pf murata grm1555c1h180jz01 7 1 c8 cap, sm, 0402 1 nf murata grm155r61h102ka01 8 5 c2, c3, c4, c5, c7 cap, sm, 0402 2.2 nf murata grm155r71h222ka01 9 1 c9 cap, sm, 0402 62 pf murata grm1555c1h620jd01 10 2 c6, c20 cap, sm, 0603 10 f digikey 490-3896-2-nd 11 1 j1 conn, sma, edgemount aep connectors 12 1 jp1 conn, th, header, .100 pitch,1x2 samtec htsw-101-07-g-d 13 2 d1, d3 esd protector, sm te connectivity pesd0402-140 14 1 u1 ic, sm, si4770/77-a20, qfn40 silicon laboratories si4770/77 15 1 l9 ind, sm, 0603 10 nh murata 16 1 l3 ind, sm, 0603 150 nh murata lqw18anr15g00 17 1 l1 ind, sm, 0603 220 nh murata lqw18anr22g00 18 1 l2 ind, sm, 0603 47 nh murata lqw18an47ng00 21 1 x1 xtal, sm, 3.2 x 2.5 mm see table 12 see table 12 see table 12
si4770/77-a20 22 rev. 0.9 table 12. crystal options frequency (mhz) mfr series p/n 36.400000 ndk nx3225 sa exs00a-cs02420 37.800000 ndk nx3225 sa exs00a-cs02421 37.209375 ndk nx3225 sa exs00a-cs02422 36.400000 taisaw smd 3.2x2.5 36.4 mhz crystal unit tz1514a 37.800000 taisaw smd 3.2x2.5 37.8 mhz crystal unit tz1517a 37.209375 taisaw smd 3.2x2.5 37.209375 mhz crystal unit tz1522a 36.400000 jauch jxe115 q36,40-jas32p4-12-10/20- t1-lf 37.800000 jauch jxe115 q37,80-jas32p4-12-10/20- t1-lf 37.209375 jauch jxe115 q37,209375-jas32p4-12-10/ 20-t1-lf 36.400000 epson toyocom tsx-3225 outd-2b-0541 37.800000 epson toyocom tsx-3225 outd-2b-0541 37.209375 epson toyocom tsx-3225 outd-2b-0541
si4770/77-a20 rev. 0.9 23 4. functional description 4.1. overview figure 7. si4770/77-a20 block diagram the si4770/77-a20 radio receiver family employs 100% rf cmos technology to bring outstanding receiver performance to the consumer electronics industry. the si4770/77-a20 receiver family supports worldwide radio reception. the si4770/77-a20 incorporates a digital pre- processor for the european radio data system (rds) and the north american radio broadcast data system (rbds) including all required symbol decoding, block synchronization, error detection, and error correction functions. the si4777 supports am/fm hd radio channel reception with digital (i 2 s) zero-if (zif) i/q outputs for interface to an hd radio processor. the family leverages silicon laboratories? patented low- if digital architecture, delivering superior rf performance and interference rejection. the low-if architecture delivers superior performance while integrating the great majority of external components required by competing solutions. the proven digital techniques provide excellent sensitivity in weak signal environments and superb selectivity and intermodulation immunity in strong signal environments. the solution offers dynamic am/fm channel bandwidth control, auto-calibrated digital tuning, and proven am/fm seek functionality based on multiple signal quality and band parameters. the family offers highly flexible and advanced audio processing including programmable softmute, fm stereo-mono blend, dynamic am/fm channel bandwidth, am/fm hi- cut, fm hi-blend, and am lo-cut filters. in addition, the si4770/77-a20 provides an in tegrated clock oscillator or accepts a reference clock and an i 2 c-compatible, 2-wire control interface. the si 4770/77-a20 receiver system specifies a minimal bill of mate rials, resulting in a small board space requirement and making the solution ideal for any consumer electronics application from single tuner radios to multiple tuner radios. ami lna xtal1 fmxip fmi clk gen xtal2/ rclk dsp fmo fmagc1 fmagc2 cntrl iout rf pkd qout iqfs iqclk dout dfs dclk rstb fmxin a1 sda a0 lout/ mpxout rout if pkd rds adc adc dac dac si4770/77 0/90 vio2 rf pkd scl lna rf pkd reg rfreg vio1 intb r l rfgnd
si4770/77-a20 24 rev. 0.9 table 13. part number descriptions part number description fm (64?108 mhz) mw (520?1710 khz) rds analog mpx (vics/darc) iboc blend digital zif (hd/drm) channel eq ir cal si4770 am/fm rds, vics ???? ?? si4777 am/fm rds, vics, hd tuner ????????
si4770/77-a20 rev. 0.9 25 4.2. clocking the si4770/77-a20 generates all internal clocking from an external crystal using an on-chip oscillator or an external programmable reference clock. the reference clock of si4770/77-a20 is a sinusoidal or rectangular clock provided by an external source on pin rclk. the supported crystal and external clock source frequencies are selected frequencies in the 36?38 mhz range. the power up command enables the selection of an external crystal or reference clock. the reference clock and/or crystal accuracy should be 100 ppm. in a multi- receiver system, a single crystal can be shared between all si4770/77-a20 receivers. the si4770/77-a20 family features programmable loading capacitors for the on- chip crystal oscillator, e liminating external loading capacitors. figure 8. xtal share between two tuners 4.3. tuning the si4770/77-a20 includes a complete on-chip pll- vco frequency synthesizer to generate the quadrature lo input to the image-reject am and fm mixers. the si4770/77-a20 employs a single-conversion mix (down conversion) to a fixed low if center frequency. an innovative high-performan ce image reject mixer architecture allows for if center frequencies below 300 khz, thereby eliminating ceramic filters required in 10.7 mhz if tuner architectures. the tune command automatically programs the lo frequency to the center of the desired channel plus (minus) the output center if frequency when using a high-side (low-side) mix. the si4770/77-a20 supports 50, 100, or 200 khz channel spacing for fm, 9 or 10 khz for am. si477x audio receiver 1 xtal1 xtal2 si477x audio receiver 2 xtal1 xtal2 clk clk
si4770/77-a20 26 rev. 0.9 4.4. fm receiver front-end the si4770/77-a20 provides a very flexible front-end interface to accommodate a wide range of applications from cost-sensitive to high-performance. an advanced agc on the si4770/77-a20 is implemented with the use of internal rf peak and if peak detectors with programmable thresholds (trip points). the agc adjusts the resistor values automatically. attack and re lease rates for the agc are programmable, providing flexible fast attack and slow release agc performance. for cost-effective performance and superior fm sensitivity, the antenna output can be received on the fmi pin (figure 9). the fm band can be received on the fmi pin via an input coupling network. this input coupling network isolates the fm band for best performance. an internal lna provides gain for the signal. the lna output is ro uted externally to the fm mixer input pins. the lna gain is regulated with an internal voltage regulator supply via an internal resistor bank, r l . the agc circuit automatically controls the lna gain, resistor banks fmagc1, fmagc2, and r l to optimize sensitivity and strong signal handling. figure 9. conceptual illustration of the use of the fmi lna for cost-optimized and superior fm sensitivity performance cost can be further reduced by eliminating the 1:1 balun and directly interfacing the signal to the fm mixer by programming the mixer for single-ended input mode (figure 10). the trade-off is a drop in linearity of 6 dbv in ip3. figure 10. conceptual illustration of the lowest-cost configuration 4.4.1. fmi lna for fm loop-through usage in dual receiver applications, two receivers (figure 11) can be attached to a single antenna. the dual receiver solution allows for independent radio station listening in different rooms. the fmi lna input impedance is software-configurable and provides two options: 50 ? and 100 ? . configuring the input impedance for 100 ? facilitates a si4770/77- a20 receiver 1 and the si4770/77-a20 receiver 2 to be interfaced to the antenna output in parallel, providing a matched 50 ? input impedance. agc is coordinated between both receivers whereby the resistor banks, fmagc1, fmagc2, and r l , from one receiver are used to optimize sensitivit y and strong signal handling. reg lna rf pkd si477x fmxip fmxin rfreg fmo fmi rf pkd r l 50 fmagc1 fmagc2 ? ?
si4770/77-a20 rev. 0.9 27 figure 11. conceptual illustration of si4770/77- a20 receivers interfaced to a single antenna using the fmi lna in loop-through mode 4.5. am receiver front-end the si4770/77-a20 contains an integrated lna, providing an am receive chain from antenna to audio out. there are few external components and no manual alignment required. the am signal is received on the ami pin. an advanced agc on the si4770/77-a20 is implemented with the use of internal rf peak and if peak detectors with programmable thresholds (trip points). attack and release rates for the agc are programmable providing flexible fast attack and slow release agc performance. the si4770/77-a20 provides highly-accurate digital am tuning without factory adjustments. to offer maximum flexibility, the receiver suppo rts a wide range of ferrite loop sticks from 180~688 h. an air loop antenna is supported by using a transformer to increase the effective inductance of the air loop. using a 1:5 turn ratio inductor, the inductance is increased by 25 times and easily supports all typical am air loop antennas which generally vary between 10 and 20 h. reg lna reg lna si477x si477x rf pkd rf pkd fmxip rfreg fmo fmi fmxip fmxin rfreg fmo fmi rf pkd rf pkd r l r l fmxin 50 ? 100 ? 100 ? fmagc1 fmagc2
si4770/77-a20 28 rev. 0.9 4.6. received signal qualifiers a tuned signal's quality can va ry with the environmental conditions, time of day, and geographical location among many other factors. to adequately manage the audio output and avoid unpleasant audible effects to the end-user, the si4770/77-a20 monitors and provides indicators of signal quality, allowing the on-chip dsp and host processor (if required) to perform signal processing. the si4770/77-a20 monitors and reports a set of industry-standard sig nal quality metrics including on-channel rssi, adjacent channel rssi (100 khz and 200 khz), image rssi, snr, multi-path in terference on fm signal, ultra-sonic noise, and fm pilot detection. as with other si4770/77-a20 features, how these variables are used to improve audio performance can be left to the silicon labs on-chip algorithms (recommended), or they can be brought out for host-processor instructions. 4.7. digital audio interface the digital audio 3-pin interface consists of data serial lines containing audio data, a bit clock, and a word frame for left and right channel data. the digital audio interface operates in slav e mode and supports five different audio data formats: ? i 2 s audio ? left-justified audio ? right-justified audio ? dsp audio ? dsp left-justified audio 4.7.1. audio data formats in i 2 s format, by default the msb is captured on the second rising edge of dclk following each dfs transition. the remaining bits of the word are sent in order, down to the lsb. the left channel is transferred first when the dfs is low, and the right channel is transferred when the dfs is high. in left-justified format, by default, the msb is captured on the first rising edge of dclk following each dfs transition. the remaining bits of the word are sent in order, down to the lsb. the left channel is transferred first when the dfs is high, and the right channel is transferred when the dfs is low. in right-justified format, by default, the lsb is captured on the last rising edge of dclk in each valid dfs interval. the left channel is transferred fi rst when the dfs is high, and the right channel is transferred when the dfs is low. in dsp format, the dfs becomes a pulse with a width of one dclk period. the left channel is transferred first, followed right away by the right channel. there are two options in transferring the digital audio data in dsp format; the msb of the left channel can be transferred on the first rising edge of dclk following the dfs pulse (left-justified dsp format) or on the second rising edge. in all audio formats, depending on the word size, dclk frequency, and sample rates, there may be unused dclk cycles after the lsb of each word before the next dfs transition and msb of the next word. in addition, if preferred, the user can configure the msb to be captured on the falling edg e of dclk via properties. the number of audio bits can be configured for 8, 16, 20, or 24 bits. 4.7.2. audio sample rates the device supports a number of industry-standard sampling rates including 32, 40, 44.1, and 48 khz.
si4770/77-a20 rev. 0.9 29 figure 12. i 2 s audio format figure 13. left-justified audio format figure 14. right-justified audio format left channel right channel 1 dclk 1 dclk 13 2n n-1 n-2 13 2n n-1 n-2 lsb msb lsb msb dclk dout dfs i 2 s left channel right channel 13 2n n-1 n-2 13 2 n n-1 n-2 lsb msb lsb msb dclk dout dfs left channel right channel 13 2n n-1 n-2 13 2 n n-1 n-2 lsb msb lsb msb dclk dout dfs
si4770/77-a20 30 rev. 0.9 figure 15. dsp audio format figure 16. dsp left-justified audio format dclk dfs 1 dclk 13 2n n-1 n-2 n n-1 n-2 lsb msb lsb msb 13 2 left channel right channel dout (msb at 2 nd rising edge) 13 2n n-1 n-2 n n-1 n-2 lsb msb lsb msb dclk dout (msb at 1 st rising edge) dfs 13 2 left channel right channel
si4770/77-a20 rev. 0.9 31 4.8. channel equalizer the si4770/77-a20 supports advanced fm multi-path channel equalization. multi-pa th interference results in fading of the fm signal at the receiver. frequency selective fading causes different frequencies of an input signal to be attenuated and phase shifted differently in a channel. frequency selective fading gives rise to notches in the frequency response of the channel. the si4770/77-a20 channel equalizer performs blind equalization utilizing propri etary constant modulus algorithm (cma) to restore the flat response of the channel. 4.9. digital zif i/q interface (si4777 only) the digital zif i/q output can provide the down converted channelized am/fm signal at baseband to a third-party processor for am/fm hd radio processor for iboc signal processing. the si4777 provide a 500 khz bw signal for fm iboc signal processing and a 30 khz bw signal for am iboc signal processing. the zif i/q 4-pin interface consists of two data serial lines containing i and q data, a bit clock, and a word frame for each data sample. the interface operates in master mode and supports five different data formats: ? i 2 s zif ? left-justified zif ? right-justified zif ? dsp zif ? dsp left-justified zif 4.9.1. zif i/q data formats in i 2 s format, by default, the msb is captured on the second rising edge of iqclk following each iqfs transition. the remaining bits of the word are sent in order, down to the lsb. in left-justified format, by default, the msb is captured on the first rising edge of iqclk following each iqfs transition. the remaining bits of the word are sent in order, down to the lsb. in right-justified format, by default, the lsb is captured on the last rising edge of iqclk in each valid iqfs interval. in dsp format, the iqfs becomes a pulse with a width of 1 iqclk period. there are two options in transferring the digital baseband i/q data in dsp format: the msb of i and q data can be transferred on the first rising edge of iqclk following the iqfs pulse (left-justified dsp format) or on the second rising edge. in all data formats, depending on the word size, iqclk frequency, and sample rates, there may be unused iqclk cycles after the lsb of each word before the next iqfs transition and msb of the next word. in addition, if preferred, the user can configure the msb to be captured on the falling ed ge of iqclk via properties. the number of baseband i/q bits is configured for 16 bits. table 14. zif i/q interface description pin description iout 16-bit baseband i word qout 16-bit baseband q word iqfs word frame sync for i and q words iqclk bit clock for i and q data
si4770/77-a20 32 rev. 0.9 figure 17. i 2 s zif format figure 18. left-justified zif format sample n sample n+1 1 iqclk 1 iqclk 13 2n n-1 n-2 13 2n n-1 n-2 lsb msb lsb msb iqclk iout iqfs 13 2n n-1 n-2 13 2n n-1 n-2 qout lsb msb lsb msb sample n sample n+1 13 2n n-1 n-2 13 2 n n-1 n-2 lsb msb lsb msb iqclk iout iqfs 13 2n n-1 n-2 13 2 n n-1 n-2 lsb msb lsb msb qout
si4770/77-a20 rev. 0.9 33 figure 19. right-justified zif format figure 20. dsp zif format sample n sample n+1 13 2n n-1 n-2 13 2 n n-1 n-2 lsb msb lsb msb iqclk iout iqfs 13 2n n-1 n-2 13 2 n n-1 n-2 qout lsb msb lsb msb iqclk iqfs 1 iqclk 13 2n n-1 n-2 n n-1 n-2 lsb msb lsb msb 13 2 sample n sample n+1 iout (msb at 2 nd rising edge) 1 iqclk 13 2n n-1 n-2 n n-1 n-2 lsb msb lsb msb 13 2 sample n sample n+1 qout (msb at 2 nd rising edge)
si4770/77-a20 34 rev. 0.9 figure 21. dsp left-justified zif format 13 2n n-1 n-2 n n-1 n-2 lsb msb lsb msb iqclk iout (msb at 1 st rising edge) iqfs 13 2 sample n sample n+1 13 2n n-1 n-2 n n-1 n-2 lsb msb lsb qout (msb at 1 st rising edge) 13 2 sample n+1 sample n msb
si4770/77-a20 rev. 0.9 35 4.9.2. zif i/q sample rates and clocking requirements the device supports a number of industry-standard sampling rates including 650, 675, and 744.1875 khz. the external crystal and/or reference clock frequency must be the following to support the following zif i/q samples rates for interface to an hd radio demodulator/decoder or dsp. table 15. crystal/reference clock frequency requirements for the zif i/q sample rates and bit clock rates supported rclk/xtal frequency (mhz) iqfs zif i/q sample rate (khz) iqclk i/q bit clock (mhz) broadcast reception modes 36.4000 650.0000 10.4000 am/fm hd-radio 325.0000 5.2000 fm analog 40.6250 2.2750 am analog/hd-radio 37.8000 675.0000 10.8000 am/fm hd-radio 337.5000 5.4000 fm analog 42.1875 2.3625 am analog/hd-radio 37.209375 744.1875 14.88375 am/fm hd-radio 372.0938 7.4419 fm analog 46.5117 1.8605 am analog/hd-radio
si4770/77-a20 36 rev. 0.9 4.10. iboc blend mode for hd radio (si4777 only) for hd-radio reception iboc blend is supported on the si4777. this feat ure supports the ability to blend between analog and digital audio. when the bit error rate (ber) of the hd-radio digital signal falls below a predefined threshold (set by the hd-radio demodulator) and the digital audio fades out, the analog audio is blended in. this prevents the received audio from muting when the digital signal is lost. the audio will "blend to digital" upon reacquisition of the digital signal. figure 22 illustrates the syst em implementation with a third party hd-radio demodulator. zif i/q data is output to the hd-radio demodulator. the hd-radio demodulator demodulates and decodes the received hd-radio signal. it outputs digital audio (i 2 s three-wire mode) to the si4777 where the iboc blend is performed. an on-chip asynchronous resampling converter (asrc) allows the si4777 to be slaved to the hd-radio demodulator digital audio output at any sample rate from 32 khz to 48 khz. the hd-r demodulator sends a 1-bit "blend" signal to the silicon labs tuner. when this signal is "1", the si4777 initiates a crossover from full am/fm analog audio into full hd-r audio following a time ramp at a programmable ramp rate. this process continues until hd-r audio is fully blended to analog or until the blend bit becomes a "0". when the blend bit is "0", the reverse crossover occurs (crossover from hd-r to am/fm analog following a programmable ramp rate). this process continues until am/fm is fully blended or until blend becomes "1". the blended audio can be output on the analog output pins, lout and rout and/or a digital audio port to a third party audio dsp. an on-chip asynchronous re-sampling converter (asrc) allows the si4777 to be slaved to the audio dsp?s digital frame sync and bit clock from 32 khz to 48 khz. audio level alignment and calibration is implemented in the si4777 by multiplying the input hd-r audio signal by a scaling constant (determined at manufacturing time in the factory) and a dynamic constant that is hd-r station-dependent. the dynamic constant is determined by the hd-r demodulator during reception and is relayed to the si4777 by the host controller for the blend. 4.10.1. iboc blend and i 2 c device address selection in applications not requiring hd-radio reception and iboc blend, with the si4777, two i 2 c device addresses, a0 and a1 (pins 11 and 12), are available, allowing up to four si4777 receivers to share the same i 2 c bus (see "7. i2c control bus" on page 44). however in utilizing iboc blend for hd-radio reception on the si4777, only one device address a0 (pin 11) is available. pin 12 is repurposed for the interrupt output intb, whilst pin 18 is repurposed for the digital audio clock input dfs2. the 7-bit device address consists of a fixed part (6 msbs), followed by a programmable 1-bit part. the lsb of the device address signals whether a read or write i 2 c operation occurs. the voltage on the a0 pin is used to set the programmable 1-bit part of the device address. the a0 pin is tied to ground and or is left to float for address selection. the various i 2 c device addresses can be selected as summarized in table 16. table 16. i 2 c device address selection in iboc blend mode for si4777 device address [6?1] device address [0] a0 voltage (pin connection) 110001 1 vio1 110001 0 gnd
si4770/77-a20 rev. 0.9 37 figure 22. system implementation of hd-radio reception with iboc blend on the si4777 dsp hd radio demod audio processing demod audio /data decoders pll x si4777 digital i/q zif (i 2 s) iboc blend blend flag blended audio am/fm analog demodulation weak signal processing qout (pin 26) iout (pin 25) iqfs (pin24) iqclk (pin 23) master digital frame sync digital bit clock hd audio (mp1) dout2 (pin 14) master am/fm audio 4-wire mode 3-wire mode master dclk2 (pin 13) blend (pin 30) dclk (pin 29) dfs (pin 28) din (pin 27) dfs2 (pin 18) digital frame sync digital bit clock asrc asrc blended audio
si4770/77-a20 38 rev. 0.9 figure 23. si4777 pin descriptions for iboc blend mode table 17. pin descriptions for si4777 for iboc blend mode pin number name i/o description 1 nc i no connect: leave floating 2 fmxip i balanced input to fm mixer (positive) 3 fmxin i balanced input to fm mixer (negative) 4 rfgnd rf ground 5 rfreg o fm lna regulator 6 fmo o fm lna output 7 fmi i fm lna input 8 nc no connect: leave floating 9 nc no connect: leave floating 10 ami i am single-ended input 11 a0 i i 2 c address 0 12 intb o interrupt active low (si4777 for iboc blend mode) 13 dclk2 i digital audio bit clock input (si4777 for iboc blend mode) 14 dout2 o digital audio output (si4777 for iboc blend mode) iqclk 23 iqfs 24 iout 25 qout 26 din 27 dfs 28 dclk 29 blend 30 nc 8 fmi 7 fmo 6 rfreg 5 rfgnd 4 fmxin 3 fmxip 2 nc 1 ami 10 nc 9 vio1 19 vd 20 a0 11 intb 12 dclk2 13 dout2 14 rstb 15 sda 16 scl 17 dfs2 18 fmagc1 40 fmagc2 39 gpio1 38 gpio2 37 dacref 36 xtal1 35 rclk/ xtal2 34 rout 33 lout/ mpxout 32 va 31 dbyp 21 vio2 22 gnd pad
si4770/77-a20 rev. 0.9 39 15 rstb i global chip reset 16 sda i/o i 2 c data input/output 17 scl i i 2 c clock 18 dfs2 i digital audio bit clock input (si4777 for iboc blend mode) 19 vio1 s host i/o supply voltage (all pads except digital audio and i/q) 20 vd s digital voltage supply 21 dbyp i digital bypass to ground 22 vio2 s digital audio and i/q interface supply voltage 23 iqclk o zif i/q bit clock output (si4777) 24 iqfs o zif i/q frame sync output (si4777) 25 iout o zif i data output (si4777) 26 qout o zif q data output (si4777) 27 din i digital audio data input (si4777 for iboc blend mode) 28 dfs i digital audio frame sync input 29 dclk i digital audio bit clock input 30 blend i blend flag control 31 va s analog voltage supply 32 lout/ mpxout o left audio line out / fm mpx output 33 rout o right audio line out 34 xtal2/rclk i crystal oscillator input/reference clock input 35 xtal1 o crystal oscillator output 36 dacref i voltage reference for analog outputs 37 gpio2 i/o general-purpose input/output 38 gpio1 i/o general-purpose input/output 39 fmagc2 i fm automatic gain control 2 40 fmagc1 i fm automatic gain control 1 pdl gnd pad i ground. reference ground table 17. pin descriptions for si4777 for iboc blend mode (continued) pin number name i/o description
si4770/77-a20 40 rev. 0.9 4.11. stereo audio processing the output of the fm demodulator is a stereo multiplexed (mpx) signal. the mpx standard was developed in 1961, and is used worldwide. today's mpx signal format consists of left + right (l+r) audio, left ? right (l?r) audio, a 19 khz pilot tone, and rds/ rbds data as shown in figure 24. figure 24. mpx signal spectrum 4.11.1. stereo decoder the si4770/77-a20's integrated stereo decoder automatically decodes the mpx signal using dsp techniques. the 0 to 15 khz (l+r) signal is the mono output of the fm tuner. stereo is generated from the (l+r), (l?r), and a 19 khz pilot tone. the pilot tone is used as a reference to recover the (l?r) signal. output left and right channels are obtained by adding and subtracting the (l+r) and (l?r) signals respectively. 4.11.2. stereo-mono blending adaptive noise suppression is employed to gradually combine the stereo left and right audio channels to a mono (l+r) audio signal as the signal quality degrades to maintain optimum sound fidelity under varying reception conditions. signal metrics such as on-channel rssi, ultra-sonic noise (usn), and multi-path interference are monitored simultaneously in forcing a blend from stereo to mono. the metric, reflecting the poorest signal quality, takes priority and the stereo signal is blended appropriately. the thresholds for activating stereo-mono blend are programmable, as are the levels for a fully blended state. the attack and decay rates for each metric are programmable. the pilot detection metric is additionally available for read-out. figure 25. conceptual illustration of stereo-mono blend 057 53 38 23 19 15 frequency (khz) modulation level stereo audio left - right rds/ rbds mono audio left + right stereo pilot stereo thld mono thld stereo thld mono thld mono thld stereo thld snr (db) rssi (dbuv) multi-path % stereo mono blend level t< t release
si4770/77-a20 rev. 0.9 41 4.12. de-emphasis pre-emphasis and de-emphasis is a technique used by fm broadcasters to improve the signal-to-noise ratio of fm receivers by reducing the effects of high-frequency interference and noise. when the fm signal is transmitted, a pre-emphasis filter is applied to accentuate the high audio frequencies. the si4770/77- a20 incorporate a de-emphasis filter which attenuates high frequencies to restore a flat frequency response. two time constants are used in various regions. the de- emphasis time constant is programmable to 50 or 75 s. 4.13. analog audio and fm mpx high-fidelity digital-to-analog converters (dacs) drive analog audio signals or the fm mpx signal onto the lout/mpxout and rout pins . at powerup time the user can configure the analog outputs for either audio or mpx output. in applications where mpx and audio outputs are required simultaneously, the analog mpx signal can be driven onto the mpxout pin and the audio signals can be sourced from the digital audio interface. the audio output may be muted. volume is adjusted digitally. it is necessary th at the volume be maintained at maximum levels to ensure the highest dynamic range audio outputs to the external audio processing stage in a car radio. 4.14. soft mute the soft mute feature is available to attenuate the audio outputs and minimize audible noise in compromised signal conditions. the si4770/77-a20 triggers soft mute by monitoring signal metrics such as on-channel rssi or snr. the thresholds fo r activating soft mute are programmable, as are soft mute attenuation levels and attack and decay rates. the si4770/77-a20 provides the soft mute feature in fm and am bands. 4.15. am/fm dynami c bandwidth control the am/fm if channel bandwidth is dynamically optimized according to on-channel rssi, and with the aid of the adjacent and alternate channel rssi metric. 4.16. seek and valid station qualification the seek function will search up or down the selected frequency band for a valid channel. a valid channel is qualified according to a series of programmable signal indicators and thresholds. the seek function can be made to stop at the band edge and provide an interrupt, or wrap the band and continue seeking until arriving at the original departure frequency. the device sets interrupts with found valid statio ns or, if the seek results in zero found valid stations , the device indicates failure and again sets an interrupt. the si4770/77-a20 seek f unctionality is performed completely on-chip or can be brought out to a companion processor. the si4770/77-a20 can provide base values for signal quality variables to a companion processor for qualification or can further process the base values to qualify va lid or invalid stations. the si4770/77-a20 uses rssi, snr, and frequency offset to qualify stations. these variables have programmable thresholds to tailor the seek function to the subjective tast es of customers. rssi is employed first to screen all possible candidate stations. snr and frequency offset are subsequently used in screening the rssi qualified stations. the more thresholds the system engages, the higher the confidence that an y found stations will indeed be valid broadcast stations; however, the more challenging levels the thresholds are set to, the longer the overall seek time as more stations and more qualifiers will be assessed. it is recommended that rssi be set to a midlevel threshold in conjunction with an snr threshold set to a level delivering acceptable audio performance. this trade-off will eliminate very low rssi stations whilst keeping the seek time to ac ceptable levels. generally, the time to auto-scan and store valid channels for an entire am or fm band with all thresholds engaged is very short depending on the band content. seek is initiated using the am and fm seek commands. the rssi and snr threshold settings are adjustable using properties.
si4770/77-a20 42 rev. 0.9 4.17. am hi-cut control am hi-cut control is employed on am audio outputs with degradation of signal quality. signal metrics such as snr or on-channel rssi acti vate the hi-cut filter. programmable minimum and maximum thresholds are available for all metrics. attack and release rates for hi- cut are programmable for all metrics. the level of hi-cut applied can be monitored with the received signal quality command. hi-cut can be disabled by setting the hi-cut filter setting to the default audio bandwidth for am. further information is provided in the programming guide. 4.18. fm hi-cut control fm hi-cut control applies a lo w-pass filter on the (l+r) audio upon degradation of received signal quality. signal metrics, such as usn, on-channel rssi, and multipath interference, activate the hi-cut filter. programmable minimum and maximum thresholds are available for all metrics. attack and release rates are also programmable for all metrics. the level of hi-cut applied can be monitored with the received signal quality command. further inform ation is provided in the programming guide. 4.19. fm hi-blend fm hi-blend control applies a low-pass filter on the (l-r) audio upon degradation of received signal quality. signal metrics, such as usn, on-channel rssi, and multipath interference, activate the hi-blend filter. programmable minimum and maximum thresholds are available for all metrics. attack and release rates for are also programmable for all metrics. the level of hi-blend applied can be monitored with the received signal quality command. further information is provided in the programming guide. 4.20. am lo-cut am lo-cut is employed on audio outputs for rejection of power-supply 50/60 hz interfer ence. am lo-cut is a high pass filter. lo-cut is enabled by default and can be disabled by programming the filter to being switched off.
si4770/77-a20 rev. 0.9 43 5. rds/rbds advanced processor the si4770/77-a20 implements an advanced, patented, high-performance rds proc essor for demodulation, symbol decoding, block synchronization, error detection, and error correction. the rds decoder applies advanced decoding and statistical decision techniques to provide high-performance synchronization at very noisy signal levels, and excellent sensitivity at industry-standard block error rate (bler) levels (5%). the si4770/77-a20?s strong synchronization performance in very noisy/low snr environments minimizes the number of instances of lost synchronization. other less robust tuners must attempt to resynchronize in low s nr environments, resulting in lost data and lengthy delays in reestablishing data reception. the si4770/77-a20 maintains synchronization to the rds transmission, despite high bler. this results in fewer dropped connections, minimal resynchronization time, and greater data reliability in low snr environments. the si4770/77-a20 reports rds decoder synchronization status and detailed bit errors for each rds block. the range of reportable bit errors detected and corrected are 0, 1-2, 3-5, and ?not correctable.? more than five errors indi cate that the corresponding block information word is non-correctable. the si4770/77-a20 also provides highly configurable interrupts based on rds-driven events and conditions. the default settings provide an interrupt when rds is synchronized and when rds group data has been received. the configurable interrupts can be set to provide frequent interrupts down to a single received block with bler. the configurable interrupts also can be set to provide very infrequent interrupts, buffering up to 25 complete rds groups (100 blocks) with bler information by block in the on-chip fifo. the si4770/ 77-a20 also provides configurable interrupts on changes or receipt of the ke y rds blocks a and b. this flexibility allows adopters to either conduct extensive rds data processing on the host or reserve the host processor in power-saving modes with minimal rds interrupts, allowing the si4770/77-a20 to perform rds processing on-chip. 6. programming section to ease development time and offer maximum customization, the si4770/77-a20 provides a simple and powerful software command protocol in addition to the 2-wire i 2 c serial interface to communicate with the host processor.the device is programmed using commands, arguments, properties, and responses. to perform an action, the user writes a command byte and associated arguments, causi ng the chip to execute the given command. commands control actions such as powerup, powerdown, or tune to a station. arguments are specific to a given command and are used to modify the command. properties are a special command + argument used to modify the default chip operation and are generally configured immediately after powerup. examples of properties are de-emphasis level, rssi seek threshold, and soft mute attenuation threshold. responses provide information and are echoed after a command + argument is issued and processed. all commands provide a one-byte status update indicating interrupt and clear-to-send status information.
si4770/77-a20 44 rev. 0.9 7. i 2 c control bus a serial port slave interface is provided, which allo ws an external controller to send commands and receive responses from the si4770/77-a20. 7.1. i 2 c device address selection two device i 2 c addresses are available, allowing up to four si4770/77-a20 receivers to share the same i 2 c bus. the 7-bit device address consists of a fixed part (5 m sbs), followed by a programmable 2-bit part. the lsb of the device address signals whether a read or write i 2 c operation occurs. the voltage on the a0 and a1 pins are used to set the programmable 2-bit part of the device address. the a0 and a1 pins are tied to ground and are left to float for address selection. the various i 2 c device addresses can be sele cted as summarized in table 18. 7.2. i 2 c standard operation the i 2 c bus interface is provided for configuration and mo nitoring of all internal registers. the si4770/77-a20 supports a 7-bit device addressing procedure and is capabl e of operating at clock rate s up to 400 khz. individual data transfers to and from the device are eight bits. the i 2 c bus consists of two wires: a serial clock line (scl) and a serial data line (sda). the device always operates as a bus slave. in order to be active, the i 2 c block requires that vio1 and vd supplies be turned on. a transaction begins with the start condition, which occu rs when sda falls while scl is high. next, the user drives an 8-bit control byte serially on sda, which is captured by the device on rising edges of scl. the control byte consists of a 7-bit device address followed by a read/write bit (read = 1, write = 0). the si4770/77-a20 acknowledges the control word by driving sda low on the next falling edge of scl. read and write operations are performed in accordance with the i 2 c bus specification. for write operations, the host sends an 8-bit data byte on sda, which is captured by the device on rising edges of scl. the si4770/77-a20 acknowledges each data byte by driv ing sda low for one cycle, after the next falling edge of scl. the host may write any number of data bytes in a single two-wire transa ction. the first byte is a command, and the next bytes are arguments. for read operations, after the si4770/77-a20 has acknow ledged the control byte, it drives an 8-bit data byte on sda, changing the state of sda after the falling edge of scl. the host acknowledges ea ch data byte by driving sda low for one cycle, after the next falling edge of scl. if a data byte is not acknowledged, the transaction ends. the host may read any number of data bytes in a single two-wire transaction. these bytes contain the response data from the si4770/77-a20. a 2-wire transaction ends with the stop condition, which occurs when sda rises while scl is high. table 18. i 2 c device address selection device address [6?2] device address [1:0] a1 voltage (pin connection) a0 voltage (pin connection) 11000 11 floating floating 11000 10 floating gnd 11000 01 gnd floating 11000 00 gnd gnd
si4770/77-a20 rev. 0.9 45 figure 26. i 2 c command/response protocol s device addr w a command arg 1 a a arg 2 a ... ... a p s device addr r a status response 1 a a response 2 a ... ... a p write operation read operation master slave a= acknowledge r = read w = write s = start condition p = stop condition
si4770/77-a20 46 rev. 0.9 8. reset, powerup, and powerdown setting the rstb pin low will disable analog and digital ci rcuitry, reset the registers to their default settings, and disable the bus. setting the rstb pin high will bring the device out of reset. the powerup mode powers up the device and provides m ode selection. mode select ions include the following: ? am, fm reception (si4770/77-a20 only). ? crystal oscillator or reference clock input a powerdown mode is available to reduce power cons umption when the part is idle. putting the device in powerdown mode will disable ana log and digital circuitry wh ile keeping the bus active. figure 27. startup timing vio 1 vio 2 vd va rstb scl sda power_up command 100 sec min 100 sec min
si4770/77-a20 rev. 0.9 47 9. pin descriptions: si4770/77-a20 figure 28. si4770/77 pin descriptions table 19. pin descriptions for si4770/77 pin number name i/o description 1 nc i no connect: leave floating 2 fmxip i balanced input to fm mixer (positive) 3 fmxin i balanced input to fm mixer (negative) 4 rfgnd rf ground 5 rfreg o fm lna regulator 6 fmo o fm lna output 7 fmi i fm lna input 8 nc no connect: leave floating 9 nc no connect: leave floating 10 ami i am single-ended input 11 a0 i i 2 c address 0 12 a1 i i 2 c address 1 13 nc no connect: leave floating nc/iqclk 23 nc/iqfs 24 nc/iout 25 nc/qout 26 dout 27 dfs 28 dclk 29 nc 30 nc 8 fmi 7 fmo 6 rfreg 5 rfgnd 4 fmxin 3 fmxip 2 nc 1 ami 10 nc 9 vio1 19 vd 20 a0 11 a1 12 nc 13 nc 14 rstb 15 sda 16 scl 17 intb 18 fmagc1 40 fmagc2 39 gpio1 38 gpio2 37 dacref 36 xtal1 35 rclk/ xtal2 34 rout 33 lout/ mpxout 32 va 31 dbyp 21 vio2 22 gnd pad
si4770/77-a20 48 rev. 0.9 14 nc no connect: leave floating 15 rstb i global chip reset 16 sda i/o i 2 c data input/output 17 scl i i 2 c clock 18 intb o interrupt, active low 19 vio1 s host i/o supply voltage (all pads except digital audio and i/q) 20 vd s digital voltage supply 21 dbyp i digital bypass to ground 22 vio2 s digital audio and i/q interface supply voltage 23 nc/iqclk o no connect: leave floating (si4770); zif i/q bit clock output (si4777) 24 nc/iqfs o no connect: leave floating (si4770); zif i/q frame sync output (si4777) 25 nc/iout o no connect: leave floating (si 4770); zif i data output (si4777) 26 nc/qout o no connect: leave floating (si 4770); zif q data output (si4777) 27 dout o digital audio data output 28 dfs i digital audio frame sync input 29 dclk i digital audio bit clock input 30 nc no connect: leave floating 31 va s analog voltage supply 32 lout/ mpxout o left audio line out / fm mpx output 33 rout o right audio line out 34 xtal2/rclk i crystal oscillator input/reference clock input 35 xtal1 o crystal oscillator output 36 dacref i voltage reference for analog outputs 37 gpio2 i/o general-purpose input/output 38 gpio1 i/o general-purpose input/output 39 fmagc2 i fm automatic gain control 2 40 fmagc1 i fm automatic gain control 1 pdl gnd pad i ground. reference ground table 19. pin descriptions for si4770/77 (continued) pin number name i/o description
si4770/77-a20 rev. 0.9 49 10. ordering guide part number , * description package type operating temperature SI4770-A20-GM am/fm rds broadcas t radio receiver 6 x 6 40-pin qfn pb-free ?40 to 85 c si4777-a20-gm am/fm rds broadcast radio receiver and hd radio tuner 6 x 6 40-pin qfn pb-free ?40 to 85 c *note: add an ?(r)? at the end of the device part number to denote tape and reel option.
si4770/77-a20 50 rev. 0.9 11. package outline figure 29. 40-pin quad flat no-lead (qfn) table 20. package dimensions dimensions min nom max a 0.80 0.85 0.90 a1 0.00 0.02 0.05 b 0.18 0.25 0.30 d 6.00 bsc. d2 3.95 4.10 4.25 e 0.50 bsc. e 6.00 bsc. e2 3.95 4.10 4.25 l 0.30 0.40 0.50 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.10 eee 0.05 notes: 1. all dimensions shown are in milli meters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jedec outline mo-220, variation vjjd-2. 4. recommended card reflow profile is per the jedec/ipc j-std-020c specification for small body components.
si4770/77-a20 rev. 0.9 51 12. pcb land pattern figure 30. pcb land pattern
si4770/77-a20 52 rev. 0.9 table 21. pcb land pattern dimensions dimensions min max e 0.50 bsc. e5.42 ref. d5.42 ref. e2 4.00 4.20 d2 4.00 4.20 ge 4.53 ? gd 4.53 ? x?0.28 y0.89 ref. ze ? 6.31 zd ? 6.31 notes: general 1. all dimensions shown are in milli meters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per th e ansi y14.5m-1994 specification. 3. this land pattern design is based on ipc-sm-782 guidelines. 4. all dimensions shown are at maximum material condition (mmc). least material condition (lmc) is calculat ed based on a fabrication allowance of 0.05 mm. solder mask design 5. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 6. a stainless steel, laser-cut and electr o-polished stencil with trapezoidal walls should be used to assure good solder paste release. 7. the stencil thickness should be 0.125 mm (5 mils). 8. the ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 9. a 4 x4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the center ground pad. card assembly 10. a no-clean, type-3 solder paste is recommended. 11. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components.
si4770/77-a20 rev. 0.9 53 13. top marking 13.1. si4770/77-a20 top marking 13.2. top marking explanation mark method: laser pin 1 mark: circle = 0.90 mm diameter (bottom-left-justified) font size: 0.70 mm right-justified line 1 mark format: device number 4770 = si4770 4777 = si4777 a = part revision a 20 = firmware revision 2.0 line 2 mark format: tttttt = mfg code manufacturing code from the assembly purchase order form. line 3 mark format: yy = year ww = work week assigned by the assembly house. corresponds to the year and work week of the assembly date.
si4770/77-a20 54 rev. 0.9 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: fminfo@silabs.com internet: www.silabs.com silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon labor atories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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