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| AM53C974A pc scsi tm ii technical manual revision 1.0 a d v a n c e d m i c r o d e v i c e s
? 1994 advanced micro devices, inc. advanced micro devices reserves the right to make changes in its products without notice in order to improve design or performance characteristics. this publication neither states nor implies any warranty of any kind, including but not limited to implied warrants of merchantability or fitness for a particular application. amd a assumes no responsibility for the use of any circuitry other than the circuitry in an amd product. the information in this publication is believed to be accurate in all respects at the time of publication, but is subject to change without notice. amd assumes no responsibility for any errors or omissions, and disclaims responsibility for any consequences resulting from the use of the information included herein. additionally, amd assumes no responsibility for the functioning of undescribed features or parameters. trademarks amd is a registered trademark of advanced micro devices, inc. pc scsi and glitch eater are trademarks of advanced micro devices, inc. microsoft is a registered trademark of microsoft corporation. windows nt miniport is a trademark of microsoft corporation. product names used in this publication are for identification purposes only and may be trademarks of their respective companies. iii table of contents table of contents chapter 1 general information 1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 introduction 1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 hardware 1-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.1 fast scsi block 1-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.1.1 features 1-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.1.1.1 access fifo command 1-3 . . . . . . . . . . . . . . . . . . . 1.2.1.1.2 reduced power mode 1-3 . . . . . . . . . . . . . . . . . . . . 1.2.1.1.3 programmable glitch eater circuitry 1-3 . . . . . . 1.2.1.1.4 programmable active negation 1-4 . . . . . . . . . . . . . 1.2.2 dma engine 1-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 software 1-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.1 amds pc scsi software solution 1-5 . . . . . . . . . . . . . . . . . . . . . . chapter 2 signal descriptions 2-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 logic symbol 2-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 quick reference pin descriptions 2-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 signal descriptions 2-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 address and data pins 2-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.2 pci interface control pins 2-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.3 arbitration pins 2-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.4 system pins 2-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.5 error reporting pins 2-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.6 interrupt request pins 2-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.7 scsi interface signals 2-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.8 power management signals 2-7 . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.9 boot rom support pins 2-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.10 miscellaneous signals 2-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.11 power supply pins 2-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 connection diagram tables 2-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.1 listed by pin number 2-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.2 listed by pin name 2-11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 pin out map 2-12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 nand tree testing 2-13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 AM53C974A register map 2-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . chapter 3 power management features 3-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 introduction 3-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 scsi activity indicators 3-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 reduced power mode 3-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 power down pin (pwdn pin) 3-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 software disk spin-down 3-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . amd table of contents iv chapter 4 the pci bus interface unit 4-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 introduction 4-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 addressing 4-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 bus acquisition 4-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 bus cycle definition 4-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 bus cycle diagrams 4-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.1 slave i/o read 4-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.2 slave i/o write 4-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.3 master memory read 4-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.4 slave memory read 4-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.5 master memory write 4-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.6 slave configuration read 4-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.7 slave configuration write 4-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.8 master memory read line 4-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 transaction termination 4-11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.1 target initiated termination 4-11 . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.1.1 disconnect with data transfer 4-11 . . . . . . . . . . . . . . . . 4.6.1.2 disconnect without data transfer 4-12 . . . . . . . . . . . . . . 4.6.1.3 target abort 4-13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.2 master initiated termination 4-14 . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.2.1 preemption 4-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.2.2 master abort 4-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 configuration registers 4-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7.1 predefined header register description 4-17 . . . . . . . . . . . . . . . . . 4.7.1.1 vendor id register 4-17 . . . . . . . . . . . . . . . . . . . . . . . . . 4.7.1.2 device id register 4-17 . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7.1.3 command register 4-17 . . . . . . . . . . . . . . . . . . . . . . . . . 4.7.1.4 status register 4-19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7.1.5 revision id register 4-20 . . . . . . . . . . . . . . . . . . . . . . . . 4.7.1.6 programming interface register 4-20 . . . . . . . . . . . . . . . 4.7.1.7 sub-class register 4-20 . . . . . . . . . . . . . . . . . . . . . . . . . 4.7.1.8 base class register 4-20 . . . . . . . . . . . . . . . . . . . . . . . . 4.7.1.9 latency timer register 4-20 . . . . . . . . . . . . . . . . . . . . . . 4.7.1.10 header type register 4-21 . . . . . . . . . . . . . . . . . . . . . . . 4.7.1.11 base address register 4-21 . . . . . . . . . . . . . . . . . . . . . . 4.7.1.12 expansion rom base address register 4-22 . . . . . . . . . 4.7.1.13 interrupt line register 4-23 . . . . . . . . . . . . . . . . . . . . . . . 4.7.1.14 interrupt pin register 4-23 . . . . . . . . . . . . . . . . . . . . . . . . 4.7.1.15 min_gnt register 4-23 . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7.1.16 max_lat register 4-23 . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7.2 device dependent register description 4-24 . . . . . . . . . . . . . . . . . 4.7.3 amds scratch register usage 4-24 . . . . . . . . . . . . . . . . . . . . . . . . 4.7.3.1 target device configuration register definition 4-24 . . . 4.7.3.2 host configuration register definition 4-26 . . . . . . . . . . . amd v table of contents chapter 5 the fast scsi block 5-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 functional overview 5-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.1 part-unique id 5-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.2 scsi fifo threshold 5-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.3 data transmission 5-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.4 req/ack control 5-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.5 parity 5-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.5.1 parity from the scsi bus 5-3 . . . . . . . . . . . . . . . . . . . . . 5.1.6 reset levels 5-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.6.1 hard resets: (h) 5-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.6.2 soft reset: (s) 5-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.6.3 disconnected reset: (d) 5-5 . . . . . . . . . . . . . . . . . . . . . 5.2 register description 5-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1 register bit map: read 5-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.2 register bit map: write 5-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.3 register descriptions 5-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.3.1 current transfer count register 5-9 . . . . . . . . . . . . . . . 5.2.3.2 start transfer count register 5-10 . . . . . . . . . . . . . . . . . 5.2.3.3 scsi fifo register 5-10 . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.3.4 scsi command register 5-11 . . . . . . . . . . . . . . . . . . . . 5.2.3.5 scsi status register 5-12 . . . . . . . . . . . . . . . . . . . . . . . . 5.2.3.6 scsi destination id register 5-14 . . . . . . . . . . . . . . . . . 5.2.3.7 interrupt status register 5-14 . . . . . . . . . . . . . . . . . . . . . 5.2.3.8 scsi timeout register 5-15 . . . . . . . . . . . . . . . . . . . . . . 5.2.3.9 internal state register 5-16 . . . . . . . . . . . . . . . . . . . . . . . 5.2.3.10 synchronous transfer period register 5-20 . . . . . . . . . . 5.2.3.11 current fifo/internal state register 5-22 . . . . . . . . . . . . 5.2.3.12 synchronous offset register 5-23 . . . . . . . . . . . . . . . . . . 5.2.3.13 control register one 5-24 . . . . . . . . . . . . . . . . . . . . . . . . 5.2.3.14 clock factor register 5-25 . . . . . . . . . . . . . . . . . . . . . . . 5.2.3.15 reserved 5-25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.3.16 control register two 5-26 . . . . . . . . . . . . . . . . . . . . . . . . 5.2.3.17 control register three 5-27 . . . . . . . . . . . . . . . . . . . . . . 5.2.3.18 control register four 5-28 . . . . . . . . . . . . . . . . . . . . . . . 5.2.3.19 reserved 5-29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.3.20 part-unique id register 5-29 . . . . . . . . . . . . . . . . . . . . . . 5.3 device commands 5-30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1 command stacking 5-32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2 invalid commands 5-32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.3 command window 5-32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.4 initiator commands 5-32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.4.1 information transfer command 5-33 . . . . . . . . . . . . . . . . 5.3.4.2 initiator command complete steps 5-34 . . . . . . . . . . . . . 5.3.4.3 message accepted command 5-34 . . . . . . . . . . . . . . . . . 5.3.4.4 transfer pad bytes command 5-34 . . . . . . . . . . . . . . . . . 5.3.4.5 set atn command 5-35 . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.4.6 reset atn command 5-35 . . . . . . . . . . . . . . . . . . . . . . . 5.3.5 target commands 5-35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.5.1 send message command 5-36 . . . . . . . . . . . . . . . . . . . . 5.3.5.2 send status command 5-36 . . . . . . . . . . . . . . . . . . . . . . 5.3.5.3 send data command 5-36 . . . . . . . . . . . . . . . . . . . . . . . 5.3.5.4 disconnect steps command 5-36 . . . . . . . . . . . . . . . . . . 5.3.5.5 terminate steps command 5-36 . . . . . . . . . . . . . . . . . . . 5.3.5.6 target command complete steps command 5-37 . . . . . 5.3.5.7 disconnect command 5-37 . . . . . . . . . . . . . . . . . . . . . . 5.3.5.8 receive message steps command 5-37 . . . . . . . . . . . . . 5.3.5.9 receive commands command 5-37 . . . . . . . . . . . . . . . . amd table of contents vi 5.3.5.10 receive data command 5-37 . . . . . . . . . . . . . . . . . . . . . 5.3.5.11 receive command steps command 5-38 . . . . . . . . . . . . 5.3.5.12 dma stop command 5-38 . . . . . . . . . . . . . . . . . . . . . . . . 5.3.5.13 access fifo command 5-39 . . . . . . . . . . . . . . . . . . . . . 5.3.6 idle state commands 5-39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.6.1 reselect steps command 5-39 . . . . . . . . . . . . . . . . . . . 5.3.6.2 select without atn steps command 5-40 . . . . . . . . . . . . 5.3.6.3 select with atn steps command 5-40 . . . . . . . . . . . . . 5.3.6.4 select with atn and stop steps command 5-40 . . . . . . 5.3.6.5 enable selection/reselection command 5-40 . . . . . . . . 5.3.6.6 disable selection/reselection command 5-40 . . . . . . . . 5.3.6.7 select with atn3 steps command 5-41 . . . . . . . . . . . . . 5.3.6.8 reselect with atn3 steps command 5-41 . . . . . . . . . . . 5.3.7 general commands 5-42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.7.1 no operation command 5-42 . . . . . . . . . . . . . . . . . . . . . 5.3.7.2 clear fifo command 5-42 . . . . . . . . . . . . . . . . . . . . . . 5.3.7.3 reset device command 5-42 . . . . . . . . . . . . . . . . . . . . . 5.3.7.4 reset scsi bus command 5-42 . . . . . . . . . . . . . . . . . . chapter 6 dma engine 6-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 introduction 6-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 data path unit 6-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 dma fifo 6-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.1 dma blast command 6-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 funneling logic 6-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 scsi dma programming sequence 6-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6 mdl based dma programming 6-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7 dma registers 6-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7.1 command register 6-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7.2 starting transfer count 6-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7.3 starting physical address 6-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7.4 working byte counter 6-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7.5 working address counter 6-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7.6 status register 6-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7.7 starting memory descriptor list address (smdla) 6-10 . . . . . . . . 6.7.8 working mdl address counter (wmac) 6-10 . . . . . . . . . . . . . . . . 6.7.9 scsi bus and control (sbac) 6-11 . . . . . . . . . . . . . . . . . . . . . . . . 6.8 dma scatter-gather mechanism 6-13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.1 memory descriptor list (mdl) 6-14 . . . . . . . . . . . . . . . . . . . . . . . . 6.8.2 dma scatter C gather operation (4k aligned elements) 6-14 . . . . . 6.8.3 dma scatter C gather operation (non-4k aligned elements mdl not set) 6-17 . . . . . . . . . . . . . . . . . 6.9 interrupts 6-17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . chapter 7 expansion rom support 7-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 introduction 7-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 rom base address register 7-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 sample implementation 7-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4 rom access cycle 7-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 expansion rom mapping 7-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . amd vii table of contents chapter 8 scam tutorial 8-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 introduction 8-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 requirements 8-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3 scam terminology 8-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 normal scsi and scam selections 8-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.1 normal scsi selection 8-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.2 level 1 scam selection 8-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5 scam protocol 8-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5.1 scam master device operation 8-5 . . . . . . . . . . . . . . . . . . . . . . . 8.5.2 scam slave device operation 8-6 . . . . . . . . . . . . . . . . . . . . . . . . 8.6 scam examples 8-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.7 id assignment 8-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.7.1 protocol initialization 8-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.7.2 function codes 8-11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.7.3 identification string 8-11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.7.4 assigning ids 8-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.7.5 default id and id assignment 8-15 . . . . . . . . . . . . . . . . . . . . . . . . . chapter 9 design considerations for motherboards and adapter cards 9-1 . . . . . . . . . 9.1 introduction 9-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 signal routing and scsi placement 9-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.1 the motherboard 9-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.1.1 layout #1 9-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.1.2 layout #2 9-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.2 the adapter card 9-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3 noise considerations 9-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.1 electromagnetic interference (emi) 9-6 . . . . . . . . . . . . . . . . . . . . . 9.3.2 decoupling methods 9-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4 termination considerations 9-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.1 termination 9-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.1.1 scheme #1 9-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.1.2 scheme #2 9-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.1.3 scheme #3 9-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5 other considerations 9-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . chapter 10 amd's pc scsi software 10-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1 introduction 10-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2 pc scsi software architecture 10-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 operating system support 10-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.1 dos 10-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.2 netware 10-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.3 os/2 10-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.4 windows 10-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.5 windows nt 10-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.6 sco unix 10-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.7 scsi rom bios 10-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4 peripheral support 10-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . appendix a AM53C974A literature/tool support a-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . amd table of contents viii AM53C974A pc scsi ii technical manual ix scsi technology overview introduction this chapter is included in the technical specification for the pci family of amd scsi solutions because of the nature of these devices. each scsi chip is effectively a complete solution for integrating scsi on a pci adapter card or onto the motherboard of a pci based system. all of the logic required for a scsi port is included in the pci scsi device. because amd also furnishes the software solution for pc operating systems, users are (for the first time) looking at scsi as a standard i/o solution, but may have little experience in the basics of the standard. this introduction will provide a basic understanding of the relevant information so that users can quickly integrate and use the scsi interface. before the scsi standard was defined, in the 1979 time frame, the typical introduction of new peripheral technology required 18 to 24 months. the tasks consisted of: 1. designing a disk controller board 2. designing a host adapter board 3. changing system software to accommodate new device characteristics 4. testing the new configuration disk drive manufacturers were faced with a delay that severely impacted business. if disk development required 18 months, and integration took another 18 months, the total time to revenue was three years. clearly, this technology bottleneck caused problems for the disk industry. consequently, vendors began to define logical interfaces that could survive beyond each model, and allow integrators to preserve the majority of their development investment. scsi was one of these definitions that survived. origi- nally defined by shugart associates, sasi (shugart associates systems interface) was offered as a public document by shugart in hopes that other system vendors would use it and establish it as a defacto standard. within a short time, an ansi standards group was formed, the name was changed to s mall c omputer s ystems i nterface, and the standardization efforts began. with support from peripheral vendors, the document defined a logical interface to a wide variety of peripherals. this interface would allow system vendors to attach peripherals easily and quickly to new systems, in order to meet a fast moving market window. the standard defined a physical level (mechanical and electrical) as well as a logical level (commands and messages). the actual command passing protocol and the set of peripheral command sets were defined by the standard. using logical addressing mechanisms, rather than physical addressing (sector 347 vs. cylinder 13, head 2, sector 3), the standard allowed the physical details of the peripheral to be hidden from the system software. therefore, after the standard was defined, a typical integration cycle was reduced to three months, and consisted of: 1. replacing the current scsi disk with a new model 2. testing the new configuration for compliance amd AM53C974A pc scsi ii technical manual x the process was complicated because new peripherals offered features that were enabled through the system software, and because vendors did not offer devices that were compatible with other vendors. but in general, the process was much simpler and faster than before. since 1979, the scsi standard passed through several key stages as it matured into todays standard. these stages are: sasi (1979 C 1982) this was a dtc/shugart collaboration that was a controller board shipped with shugart drives. although limited in function, it highlighted the advantages of a high level logical interface for disk drives. scsi-1 (1982 C 1986) a group of companies (shugart, adaptec, ncr, & omti) banded together and approached ansi for permission to develop a scsi standard. the effort generated industry wide interest and was quickly written because of the participants common interest (i.e. everyone desired quick time to market for their products). the ansi specification (x3.131C1986) won final approval in may of 1986. ccs (1985 C 1986) upon finalization of the scsi-1 specification, the participants barely had time to congratulate each other before the weakness of the document began to emerge. the number of options allowed vendors were to develop disks that worked fine, but which were not compatible with each other. thus system vendors could not easily integrate disk drives from all vendors into their system. so, disk vendors met to define an extended subset of scsi that would (if followed closely) permit vendors to produce compatible disk products. this document (common com- mand set) became a defacto standard and allowed further standardization of the scsi market. scsi-2 (1986 C 199x) as soon as the ccs specification was written, the complete scsi community realized the benefit of these extensions and restarted the scsi effort to bring the benefits of ccs into the complete scsi standard document. the original goal was to quickly fold ccs into the disk section and expand other com- mand sets to include ccs features. unfortunately, the door of improvement, once open, allowed a flood of improvements to come in. updates were cut off by 1990 and the specification has been finalized as of august 1990. scsi-3 (1990 C 199x) the stated goal of the first two scsi specifications was downward compatibility, but with scsi-3, backward compatibility was sacrificed. the goal was to define a protocol that accommodated the new serial interfaces and solved some of the problems of the parallel interface. the result is a family of docu- ments being written for scsi-3. basic scsi the standard scsi parallel bus allows connection for 8 or 16 devices (computers or peripherals). each has a unique identifier that allows selection and communication between any two devices on the scsi bus. an initiator is an entity on the bus that issues a command to a target. note that any device on the bus, peripheral or computer system, can initiate a command sequence. the initiator arbitrates for and wins the scsi bus, selects the desired target, and sends a command to that target. at this point, the target controls the bus and directs the remainder of the command sequence. the initiator can always regain control by use of the attention line that signals the target that something is coming. but in general, the target remains in control. there are nine control signals on the scsi bus that allow the complete handshake to happen. target or initiator controls the bus depending on the phase of the command sequence. there are 8, 16, or 32 data lines with each 8 bit set having a parity line. the data width can be negotiated for, with 8 being the default, and 16 or 32 being amd AM53C974A pc scsi ii technical manual xi options. sixteen-bit scsi devices are available but are not in widespread use, while 32-bit devices are not yet available. there is considerable inertia resisting going beyond 8-bit cables because of the physical sizes involved. there is a fast scsi option that allows scsi to transfer data at 10 mega transfers per second, thus allowing 10 mb/sec on 8-bit cables. this configuration is the clear winner in todays market, because it allows faster transfers with no change in the physical environment. single ended scsi is by far the most popular implementation and the specification allows 6 meter cables in this environment. fast scsi is not defined for single-ended cables, however, vendors are providing silicon that will allow data to be transferred at the higher speeds. the scsi protocol defines the phases required to complete a scsi i/o. the message phase allows short transfers of protocol related information to be sent across the bus to establish and control the logical connection between an initiator and a target. the command phase allows the initiator to tell the target what action must be performed. read, write, rewind, etc. are all scsi commands. user data is transferred during the data phase, allowing the data to be sent into or out from the initiator. this data can be written to the media, or it can be control information that is used to communicate operating modes or sensed information to(from) the peripheral. status information (one byte only) is sent to the initiator from the target at the end of the complete scsi command sequence. if an error occurred, the initiator must request the details of the problem with a subsequent scsi command. the basic scsi command sequence follows: bus is free and any device is allowed to arbitrate for ownership an initiator arbitrates for the bus and selects a target device the target, after sensing selection, goes to message out phase and receives a one byte id message from the initiator that establishes which physical device the initiator wants to communicate with after switching to command phase, the target receives the scsi command. changing to the appropriate data phase (in/out) the target handshakes the data across the bus a single status byte is sent to the initiator a command complete message is sent to the initiator to signal completion of the scsi i/o the target then physically disconnects from the scsi bus, and it is free for the next device to use any time after the id message is sent, the target controls the sequence and directs the initiators next step. the target is allowed to disconnect, temporarily get off the bus and reselect later. in this manner, data can be multiplexed from various peripherals to the host computer, in support of overlapped physical actions at the peripheral and multi- threaded i/o in the operating system. scsi-1 provided the basic protocol functionality that supported the original goals of device connectability, allowing 8 bit buses and a limited protocol flexibility. as noted above, the plug and play aspects of the specification were not quickly realized because of the large set of options. the ccs specification defined the extended subset of the scsi-1 document that allowed multiple disk vendors to work in one system environment without compatibility issues in the host software. the main scsi-2 features were: compatibility CC there must be an evolutionary growth, and mixed environments were permitted. requirements in scsi-2 were popular options in scsi-1. amd AM53C974A pc scsi ii technical manual xii high performance CC the original 5 mb/sec limit was pushed to 40 mb/sec using a combination of 32-bit buses and 10 mega transfers per second. the maximum cable limits were still set at 6 (single ended) and 25 (differential) meters. eight devices were allowed on the bus, but a working paper described how sixteen devices could be attached. hardware requirements CC parity on the bus is required for data integrity, and dis- connect/reconnect is required for multiplexing the scsi bus. scsi-1 had no require- ment for messages (all were optional) because of compatibility with sasi, but scsi-2 required certain messages to make scsi more usable in a complex systems environment. logical interface improvements CC a group of features were defined to generally improve scsi. features included were queueing of 256 commands at the peripheral, more detailed definition for all control data used to change device characteristics (or report information about the device), cache support for direct access devices, and tape partition support. new command sets CC new device command sets were for scanners, optical memory devices, medium changers, and communication devices. these changes dramatically increased the size of the scsi-2 specification, and moved the definition into a more high performance system environment. scsi-3 has given scsi a totally new set of capabilities. the basic desire was to increase the functionality to cover all the physical interfaces and allow the architecture to be extended to the future requirements with few restrictions for compatibility. the standard was divided into multiple documents to ease the pain of an editor. there are four transport layers: standard parallel interface for 8- and 16-bit cables fiber channel for 100 mb/sec, full duplex transfers serial storage architecture in support of high performance (20 mb/sec) disks p1394 allows 400 mb/sec isochronous transfers five protocols: interlocked fiber channel ssa serial bus generic packetized five command sets: primary block stream graphics medium changer the target release date for these set of documents is 1994, but if the past is any indication, scsi-3 will require many years of work before being ready for official release. the delay will not stop products from emerging however, because products with the new interfaces and features are already appearing in the marketplace. amd AM53C974A pc scsi ii technical manual xiii before scsi could penetrate the pc market, a critical piece of technology was required: i/o software drivers to support the scsi capabilities in the pc operating system environments. as the first vendors introduced host adapter boards that connected scsi devices to the pc, the user quickly learned the importance of software. consider the following scenario: user buys a scsi disk with host adapter a tape drive is required to back up the disk user buys a tape drive the tape can be connected, but there is no software to drive the device user buys a host adapter to drive the tape the tape works now, but there is no software to move data to/from the disk point solutions became available, but general solutions were not available until 1991. although the hardware was available and certain systems vendors were able to make scsi work, there was no guarantee that a user could find an off-the-shelf solution for the dos/windows environment. host adapter companies quickly began to offer limited software capabilities that allowed several devices to be used in the pc. several defacto interfaces were available and in the interest of standardization, a common access method (cam) committee was formed to standardize access to the scsi interface for each pc operating system environment. unfortunately, once software was running, users were reluctant to change. therefore, the cam specification, although technically sound, has never been widely accepted as a standard. the advanced scsi programming interface (aspi) instead became a defacto standard interface for i/o application software such as cd-rom and tape backup utilities. consequently, aspi seems to be entrenched as the interface of choice for dos/ windows. however, more sophisticated operating systems already have a logical i/o interface defined and do not share the same limitations as dos. as the new operating systems become more widely used in pcs and dos i/o gradually becomes buried in an emulation mode, the critical driver issues for the pc will disappear. until then (as yogi berra says, tomorrow isnt here yet), highly integrated scsi chips must be supplied with scsi i/o drivers for the operating systems that execute on a pc. the drivers must be architected carefully so as to require minimal change when the scsi device changes. known as a two layer software interface, a good architecture will isolate changes in the operating system from changes in the scsi interface. software technol- ogy like this allows scsi to be commonly available in the pc environment. another key element in the i/o performance saga is the availability of bus mastering in the pc environment. rather inexpensive 32 bit bus mastering scsi chips with fifos in the chip have taken high performance i/o to new levels. the combination of bus mastering on the chip, extremely high performance system processors and increasing levels of silicon integration have combined recently to result in high performance low cost solutions in a single chip. performance that was once only available as a host adapter board (with a separate processor, scsi chip, ram, and system interface) is now achieved using a single chip. system processors offer a level of mips on the motherboard that can easily support i/o silicon on the motherboard, thus simplifying the scsi port dramatically. this new level of cost effective silicon, combined with a complete software solution will no doubt enable scsi in a new environment and drive the industry to another level of capability. amd AM53C974A pc scsi ii technical manual xiv 1-1 general information general information 1 1.1 introduction the AM53C974A from advanced micro devices was developed in response to the pc industrys need for a hardware solution which harnessed the speed and flexibility of high bandwidth local and i/o buses. combining the performance of the pci local bus with the intelligence of the scsi i/o bus, advanced micro devices offers this bus mastering scsi controller for pci systems. the AM53C974A is one member of a family of amds plug compatible pci products which share a common software solution. these products are compliant with pci specification rev 2.0; the AM53C974A also complies with ansi standards x3.131C1986 (scsi-1) and x3.131C199x (scsi-2). the AM53C974A offers a glueless interface to the pci bus, making it an ideal choice for motherboard as well as adapter card designs. the on-chip state machine which controls scsi sequences in hardware is coupled with a bus-mastering dma engine to eliminate the need for an additional risc processor. the result is a pci-scsi controller with a superior price/performance advantage. furthermore, amds value-added proposition for the AM53C974A offering is a complete, licensable solution to minimize your time to market. distinctive features: pci bus interface unit pci specification rev 2.0 compliant interface 32-bit address/data bus master dma host interface glueless interface to 33 mhz 32-bit pci bus 96-byte dma fifo for low bus latency scsi controller features single chip pci to scsi interface boot rom support level 1 scam support scsi-2 compliant, 8-bit fast scsi interface supports single-ended scsi bus 48 ma scsi drivers performance 10 mbyte/s synchronous and 7 mbyte/s asynchronous transfer rates on the scsi bus 132 mbyte/s burst dma transfer rate supports scatter-gather data transfers power management sleep mode capability for fast scsi block CC power down for scsi receivers amd 1-2 general information scsi activity monitoring pin and status bit fully static design for low frequency operation scsi clock disconnect capability scsi bus reliability amds patented programmable glitch eater ? circuitry on req and ack inputs programmable active negation on req , ack and data lines other features 132-pin pqfp uses state of the art advanced cmos technology the AM53C974A hardware solution is complemented by an extensive software package for all major operating systems. the software solution incorporates amds portable scsi software which is based in part on the microsoft windows nt miniport ? model. 1.2 hardware the AM53C974A is a high performance pci local bus-scsi controller. it is comprised of the pci bus interface unit (biu), a fast scsi block, and a bus master dma engine. the pci biu consists of configuration space and a pci master/slave interface as defined in rev 2.0 of the pci specification. figure 1-1 shows the basic interface block diagram of the AM53C974A. figure 1-1 pci-dma-scsi interface block diagram 19113a-1 fast scsi block data cntl dreq dack dma engine pci bus interface unit data cntl pci^req pci^gnt addr cntl amd 1-3 general information 1.2.1 fast scsi block the AM53C974As fast scsi block supports scsi transfer rates of up to 10 mbytes/s synchronously, and up to 7 mbyte/s asynchronously. the AM53C974A combines this functionality with features such as programmable active negation, and a 24-bit transfer counter. amds proprietary features such as power-down mode for scsi receivers and programmable glitch eater circuitry are also included for improved product performance. the AM53C974A has an 8-bit scsi data interface and can operate as either an initiator or a target to support all scsi applications. the scsi block is designed to minimize host intervention by implementing common scsi sequences in hardware. selection, reselection, information transfer and disconnection commands are directly supported. for example, functions such as target selection/initiator reselection, command, message, and data transfers between the scsi bus and the scsi fifo are internal processes that the AM53C974A handles without microprocessor intervention. an on-chip state machine reduces protocol overhead by performing the required sequences in response to a single command from the host. additionally, a 16-byte scsi fifo further assists in minimizing host involvement. the fifo provides a temporary storage for all command, data, status and message bytes as they are transferred between the 32-bit host data bus and the 8-bit scsi data bus. parity checking on data received from the scsi bus is optional. parity is generated in the scsi block as data is loaded into the scsi fifo. data transfers between the scsi bus and the scsi fifo are internal processes that the AM53C974A also handles without microprocessor intervention. 1.2.1.1 features key features in the AM53C974A fast scsi block are highlighted below: 1.2.1.1.1 access fifo command the target command set for the AM53C974A includes the access fifo command. this command allows the host or dma controller to remove remaining fifo data following the hosts issuance of a target abort dma command, or following an abort due to parity error. this command facilitates data recovery and thereby minimizes the need to re-transmit data. for more details, refer to the target command set. 1.2.1.1.2 reduced power mode amds exclusive power-down feature can be enabled to help reduce power consump- tion. the receivers on the scsi bus may be turned off to eliminate current flow due to termination power (~3 v) near the trip point of the input buffers. additionally, the clock to the scsi core can be disconnected for further power reduction. 1.2.1.1.3 programmable glitch eater circuitry the patented glitch eater circuitry in the AM53C974A pc scsi ii controller can be programmed to filter glitches with widths up to 35 ns. it is designed to dramatically increase system reliability by detecting and removing glitches that may cause system failure. the glitch eater circuitry is implemented on the req and ack inputs since these lines are most susceptible to electrical anomalies such as reflections and voltage spikes. such signal inconsistencies can trigger false req / ack handshaking, false data transfers, addition of random data, and double clocking. amds glitch eater circuitry therefore maintains system performance and improves reliability. the following diagram illustrates this circuits operation. amd 1-4 general information figure 1-2 glitch eater circuitry operation scsi environment valid signal glitches >15 ns <15 ns glitches pass through as valid signals ack or req input device without the glitch eater circuit glitches filtered amds device with the glitch eater circuit valid signal passes ack or req input 19113a-2 by default, this feature is enabled and will filter glitches with widths up to 12 ns. when this feature is implemented, the setup and hold times for the following parameters are modified. however, they are still compliant with the scsi-2 specification and have no effect on the AM53C974As ability to meet fast scsi timings. 0 ns 12 ns window window data to req or ack setup time: fast scsi ansi requirement: 25 ns normal scsi ansi requirement: 55 ns data to req setup time (async initiator receive mode): 0 ns 12 ns data to ack setup time (async target receive mode): 0 ns 12 ns data to req or ack setup time (sync initiator/target receive mode): 5 ns 12 ns 1.2.1.1.4 programmable active negation amd offers programmable active negation, a feature which, when implemented, will actively drive the req , ack and scsi data lines to a high state. this feature is especially helpful for reducing scsi bus noise and improving data reliability. by actively driving these signals to their high state, active negation eliminates unwanted signal transitions and associated data double-clocking. this feature is controlled by bits 3:2 in the scsi control register four ((b)+34h), and may be implemented on req and ack , or on req , ack , and data lines during all scsi bus phases except arbitration and selection. for more information on programming options, refer to control register four ((b)+34h) bit level descriptions. amd 1-5 general information 1.2.2 dma engine the AM53C974A bridges the pci and scsi buses by providing a buffer for these buses. a 96-byte dma fifo (24 double words) internally interfaces with the 16-byte scsi fifo to provide temporary storage for command, data, status, and message bytes as they are transferred between the two buses. the dma engine is also capable of handling block type transfers (4 kb pages) during scatter-gather operations. odd/even boundary conditions are handled through hardware to minimize software overhead. 1.3 software to minimize your time to market, amd offers a complete software solution for the AM53C974A. this combination represents a powerful pci systems solution which enhances the flexibility of your system. 1.3.1 amd's pc scsi ii software solution amds pc scsi ii software maximizes reusability and portability of scsi protocol chip and device driver source code across multiple operating system platforms. the software architecture was based in part on the microsoft windows nt scsi miniport driver model. amds scsi software architecture supports the following features: device level overlapped/multithreaded operation tagged-queuing automatic request sense scatter-gather operations synchronous transfers (including fast scsi) amd 1-6 general information 2-1 signal descriptions signal descriptions 2 2.1 logic symbol figure 2-1 AM53C974A logic symbol bd [7:0] ad [31:0] c/ be [3:0] par frame trdy irdy stop devsel idsel pci^req pci^gnt clk pci^rst inta lock perr serr sd [7:0] sd p msg c /d i /o atn bsy sel scsi^rst req ack scsi clk1 res_dnc pwdn busy pc scsi (AM53C974A) scsi bus miscellaneous power management signals pci interface v dd v ss 19113a-3 ba [7:0] oe lck boot boot rom support amd signal descriptions 2-2 2.2 quick reference pin descriptions pin name pin type description pci ad [31:00] in/out address/data bus c/ be [3:0] in/out command/byte enable signals par in/out parity signal frame in/out cycle frame trdy in/out target ready irdy in/out initiator ready stop in/out stop lock in/out lock idsel in initialization device select devsel in/out device select pci^req out pci request pci^gnt in pci grant clk in pci clock pci^rst in pci reset perr in/out parity error serr out system error inta out interrupt scsi interface sd [7:0] in/out scsi data sd p in/out scsi data parity msg in/out message c /d in/out command/data i /o in/out input/output atn in/out attention bsy in/out busy sel in/out select scsi^rst in/out scsi bus reset req in/out request ack in/out acknowledge boot rom interface boot in boot rom enable ba [7:0] out boot rom address bd [7:0] in boot rom data oe out rom output enable lck out high address byte latch clock miscellaneous scsi clk1 in scsi core clock res_dnc in reserved, do not connect power management pwdn in power down indicator busy out scsi bus activity pin power supply v dd +5 v v ss gnd v ddb +5 v (buffer) v ssb gnd (buffer) v dd3b +5 v (pci) v ss3b gnd (5 v pci) amd 2-3 signal descriptions 2.3 signal descriptions 2.3.1 address and data pins ad (31:00) address/data (input/output, active high) address and data are multiplexed on the same pci pins. during the first clock of a transaction the ad (31:00) contains the physical address (32 bits). during subsequent clocks ad (31:00) may contain data. little-endian byte ordering is used. ad (07:00) is defined as least significant byte and ad (31:24) is defined as the most significant byte. when pci^rst is active, ad(31:00) are inputs for nand tree testing. c/ be (3:0) bus command/byte enable (input/output, active low) command and byte enables are multiplexed on the same pci pins. during the address phase of the transaction, c/ be (3:0) define the bus command. during the data phase c/ be (3:0) are used as byte enables. the byte enables define which byte lanes carry meaningful data. c/ be (0) applies to the least significant byte (byte 0) and c/ be (3) applies to the most significant byte (byte 3). when pci^rst is active, c/ be (3:0) are inputs for nand tree testing. par parity (input/output, active high) parity is even across ad(31:00) and c/ be (3:0). parity is generated and driven during master address cycle, memory write, i/o read, and configuration read cycles. parity is checked during slave address cycle, memory read, i/o write, and configuration write cycles. when pci^rst is active, par is an input for nand tree testing. 2.3.2 pci interface control pins frame cycle frame (input/output, active low) this signal is driven by the AM53C974A when it is the bus master to indicate the beginning and duration of the access. frame is asserted to indicate that bus transaction is beginning. frame is asserted while data transfers continue. frame is driven high when the transaction is in the final data phase. when pci^rst is active, frame is an input for nand tree testing. trdy target ready (input/output, active low) when the AM53C974A is selected as a slave, it will drive(low) this signal to indicate its ability to complete the current data phase of the transaction. as a master, this signal is an input to the AM53C974A from the selected (slave) device. trdy is used in conjunction with irdy to indicate completion of the data phase. the data phase is complete (on any clock) when both trdy and irdy are sampled asserted. during a read transaction, trdy is asserted when valid data is present on ad (31:00), while during a write transaction, trdy asserted indicates the target is prepared to accept data. wait cycles are inserted until both irdy and trdy are asserted together. when pci^rst is active, trdy is an input for nand tree testing. amd signal descriptions 2-4 irdy initiator ready (input/output, active low) when the AM53C974A is the initiator (master), it will drive (low) this signal to indicate its ability to complete the current data phase of the transaction. as a slave, this signal is an input to the AM53C974A from the initiating (master) device. irdy is used in conjunction with trdy to indicate completion of the data phase. the data phase is complete (on any clock) when both irdy and trdy are sampled asserted. during a read transaction, irdy asserted indicates the master is prepared to accept data, while during a write transaction, irdy is asserted to indicate that valid data is present on ad (31:00). wait cycles are inserted until both irdy and trdy are asserted together. when pci^rst is active, irdy is an input for nand tree testing. stop stop (input/output, active low) in the slave role the AM53C974A drives the stop signal to indicate to the bus master to stop the current transaction. in the bus master role the AM53C974A receives the stop signal and stops the current transaction. when pci^rst is active, stop is an input for nand tree testing. lock lock (input/output, active low) in the master role the AM53C974A drives the lock signal to indicate to the slave device that multiple transactions may be necessary to complete an operation. when lock is asserted, non-exclusive transactions may proceed. control of lock is obtained under its own protocol in conjunction with pci^gnt . in the slave role the AM53C974A receives the lock signal from the master. when pci^rst is active, lock is an input for nand tree testing. note : in the current implementation, the AM53C974A as a master will never generate a lock . however in slave role, the chip will respond to a lock asserted by a master. idsel initialization device select (input, active high) this signal is used as a chip select for the AM53C974A in lieu of the 24 address lines during configuration read and write transaction. when pci^rst is active, idsel is an input for nand tree testing. devsel device select (input/output, active low) this signal when actively driven by the AM53C974A as a slave device signals to the master device that it has decoded its address as the target of the current access. as an input it indicates whether any device on the bus has been selected. when pci^rst is active, devsel is an input for nand tree testing. amd 2-5 signal descriptions 2.3.3 arbitration pins pci^req pci request (output, active low, tristate) this signal indicates to the arbiter that the AM53C974A desires use of the bus. this is a point to point signal. every master has its own equivalent of pci^req , which will be tristated after a power-up or a chip reset. when pci^rst is active, pci^req is an input for nand tree testing. pci^gnt pci grant (input, active low) this signal indicates that the access to the bus has been granted to the AM53C974A. this is a point to point signal. every master has its own equivalent of pci^gnt . when pci^rst is active, pci^gnt is an input for nand tree testing. 2.3.4 system pins clk clock (input) this signal provides timing for all the transactions on the pci bus and all pci devices on the bus including the AM53C974A. all signals are sampled on the rising edge of clk and all parameters are defined with respect to this edge. the AM53C974A operates up to 33 mhz. when pci^rst is active, clk is an input for nand tree testing. pci^rst pci reset (input, active low) this signal forces the AM53C974A sequencer to a known state. all three-state bi-directional signals are forced to a high impedance state and all sustained open drain signals are allowed to float high. the AM53C974A will tristate pci^req , and completely reset the AM53C974A. pci^rst may be asynchronous to the clk when asserted or driven low. it is recommended that the deassertion be synchronous to guarantee a clean and bounce free edge. when pci^rst is active, nand tree testing is enabled. all pci interface pins are input mode. the result of the nand tree testing can be observed on the busy output (pin 62). 2.3.5 error reporting pins perr parity error (input/output, active low) this signal may be pulsed by the AM53C974A when it detects a parity error during any data phase when its ad (31:00) and c/ be (3:0) lines are inputs. the AM53C974A monitors the perr input during a bus master write cycle. it will assert the data parity reported bit in the status register of the pci configuration space when a parity error is reported by the target device. when pci^rst is active, perr is an input for nand tree testing. amd signal descriptions 2-6 serr system error (output, active low, open drain) this signal may be pulsed by the AM53C974A for reporting address parity errors when ad(31:00) are inputs. when pci^rst is active, serr is an input for nand tree testing. 2.3.6 interrupt request pins inta interrupt request (output, active low, open drain) this signal combines the interrupt request from both the dma engine and the scsi block. the interrupt source can be determined by reading the dma status register ((b)+70). interrupts caused by the dma engine may be cleared in two ways. when the write erase feature is not set in the sbac register ((b)+54), the inta signal will be cleared when the status register ((b)+54) is read. when the write erase feature is set, the inta signal will only be cleared when a 1 is written to the bit associated with the interrupting condition. for those interrupts generated by the scsi block, the scsi interrupt register must be serviced in order to clear the interrupt. when pci^rst is active, inta is an input for nand tree testing. 2.3.7 scsi interface signals sd (7:0) scsi data (input/output, active low, schmitt trigger, open drain/active negation) these pins are defined as bi-directional scsi data bus. sdp scsi data parity (input/output, active low, schmitt trigger, open drain/active negation) this pin is defined as bi-directional scsi data parity. msg message (input/output, active low, schmitt trigger, open drain) msg is a bi-directional signal which is asserted during a message phase. it is a schmitt triggered input in the initiator role and an output with a 48 ma driver in the target role. c /d command/data (input/output, active low, schmitt trigger, open drain) c /d is a bi-directional signal which is used to indicate whether control or data information is on the scsi data bus. it is a schmitt trigger input in the initiator role and an output with a 48 ma driver in the target role. i /o input/output (input/output, active low, schmitt trigger, open drain) i /o is a bi-directional signal which controls the direction of data movement on the scsi data bus with respect to the initiator. it is a schmitt triggered input in the initiator role and an output with a 48 ma driver in the target role. amd 2-7 signal descriptions atn attention (input/output, active low, schmitt trigger, open drain) atn is a bi-directional signal which is used to indicate the attention condition. it is a schmitt triggered input in the target role and an output with a 48 ma driver in the initiator role. bsy busy (input/output, active low, schmitt trigger, open drain) bsy is a bi-directional signal which is asserted when the AM53C974A is arbitrating for the scsi bus or when it is connected as a target. as an input it has a schmitt trigger and as an output it has a 48 ma driver. sel select (input/output, active low, schmitt trigger, open drain) sel is a bi-directional signal which is asserted when the AM53C974A is attempting to select or reselect another scsi device. as an input it has a schmitt trigger and as an output it has a 48 ma driver. scsi rst reset (input/output, active low, schmitt trigger, open drain) scsi rst is a bi-directional scsi bus reset signal. as a schmitt triggered input to the AM53C974A, this signal when asserted will reset portions of the scsi logic (see soft reset). as a 48 ma output driver, this signal when asserted will cause all other devices on the scsi bus to be reset. the reset scsi command will also cause the scsi rst pin to be driven active for 25C40 ms, depending on the scsi clock frequency and conversion factor. req request (input/output, active low, schmitt trigger, open drain) req is a bi-directional scsi bus signal which indicates a request for a req/ack data transfer. it is a schmitt triggered input in the initiator role and an output with a 48 ma driver in the target role. ack acknowledge (input /output, active low, schmitt trigger/open drain) ack is a bi-directional scsi bus signal which is used to indicate an acknowledgment for a req/ack data transfer handshake. it is a schmitt triggered input in the target role and a output with a 48 ma driver in the initiator role. 2.3.8 power management signals pwdn power down indicator (input, active high) this signal, when asserted, sets the pwdn status bit in the dma status register and sends an interrupt to the host. when pci^rst is active, pwdn is an input for nand tree testing. busy scsi devices busy (output, active low) this signal is the logical equivalent of the scsi bus bsy ored with sel signals. it is duplicated so that external logic can be connected to monitor scsi bus activity. amd signal descriptions 2-8 when pci^rst is active, the results of the nand tree testing can be observed on busy . when pci^rst is driven low, busy will function as described above. 2.3.9 boot rom support pins boot boot rom present (input) the state of this pin determines whether or not the boot rom interface on the AM53C974A is enabled. when this pin is connected to v cc , the interface is enabled to support the boot rom feature. when this pin is connected to ground, all input buffers on bd (7:0) are disabled, and ba (7:0), oe , and lck pins are tri-stated. since this pin was v ss on the am53c974, the boot rom interface on the AM53C974A is automatically disabled in existing am53c974 designs. bd (7:0) boot rom data (input) when the AM53C974A is configured for boot rom support (pin 100 tied to v cc ), bd (7:0) carries data from the rom to the AM53C974A. when not configured to support a boot rom (pin 100 tied to ground), the input buffers on these pins are disabled. ba (7:0) rom address (output) when the AM53C974A is configured for boot rom support (pin 100 tied to v cc ), ba (7:0) carries the boot rom address from the AM53C974A. when boot rom support is disabled (pin 100 tied to ground), these pins are tri-stated. oe rom output enable (output) when the AM53C974A is configured for boot rom support (pin 100 tied to v cc ), this pin is used as the output enable for the rom. when boot rom support is disabled (pin 100 tied to ground), this pin is tri-stated. lck latch clock (output) when the AM53C974A is configured for boot rom support (pin 100 tied to v cc ), this pin is used as a clock to latch the high byte of the rom address. when boot rom support is disabled (pin 100 tied to ground), this pin is tri-stated. 2.3.10 miscellaneous signals scsi clk1 scsi clock (input) the scsi clock signal is used to generate all internal device timings. the maximum frequency of this input is 40 mhz, while the minimum is 10 mhz to maintain scsi bus timing requirements. to achieve fast scsi timings, a 40 mhz clock must be supplied to this input. res_dnc reserved _do not connect (input) this pin (#116) is reserved for factory testing. to ensure proper chip operation, it must not be connected. amd 2-9 signal descriptions 2.3.11 power supply pins v dd +5 v power (input) these inputs provide power necessary to operate the AM53C974A. all v dd pins must be connected to a +5 v source. v ddb +5 v power (input) these inputs are for scsi buffers. these pins can be connected to the v dd pins. v dd3b +5 v power (input) these inputs provide power for the pci interface block. these pins must be connected to a +5 v source. v ss /v ssb /v ss3b ground (input) these inputs provide the necessary grounds to operate the AM53C974A. the v ssb and v ss3b can be connected to v ss provided there is a decoupling capacitor between v ssb and v ddb and v ss3b and v dd3b . amd signal descriptions 2-10 2.4 connection diagram tables 2.4.1 listed by pin number pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1v dd3b 34 par 67 v ssb 100 boot 2 ad27 35 c/ be 168 sd 0 101 bd0 3 ad26 36 ad15 69 sd 1 102 nc 4v ss3b 37 v ss3b 70 sd 2 103 v dd 5 ad25 38 ad14 71 sd 3 104 oe 6 ad24 39 ad13 72 v ssb 105 lck 7c/ be 3 40 ad12 73 sd 4 106 ba0 8v dd 41 ad11 74 sd 5 107 nc 9 idsel 42 ad10 75 sd 6 108 v dd 10 nc 43 v ss3b 76 v ddb 109 v dd 11 v ss 44 ad9 77 sd 7 110 nc 12 ad23 45 ad8 78 sd p 111 ba1 13 ad22 46 v dd3b 79 v ss 112 ba2 14 v ss3b 47 c/ be 080 sel 113 v ss 15 ad21 48 ad7 81 req 114 ba3 16 ad20 49 ad6 82 v ssb 115 ba4 17 v dd3b 50 v ss3b 83 ack 116 res_dnc 18 ad19 51 ad5 84 v dd 117 inta 19 ad18 52 ad4 85 msg 118 ba5 20 v ss3b 53 ad3 86 c /d 119 v ss 21 ad17 54 ad2 87 i /o 120 pci^rst 22 ad16 55 v ss3b 88 v ss 121 clk 23 c/ be 2 56 ad1 89 bd7 122 v dd 24 frame 57 ad0 90 bd6 123 ba6 25 irdy 58 pwdn 91 v dd 124 pci^gnt 26 trdy 59 v dd 92 nc 125 v ss 27 devsel 60 scsiclk1 93 bd5 126 ba7 28 stop 61 v ss 94 bd4 127 pci^req 29 lock 62 busy 95 bd3 128 ad31 30 v ss 63 v ss 96 v dd 129 ad30 31 perr 64 bsy 97 bd2 130 v ss3b 32 serr 65 atn 98 v ss 131 ad29 33 v dd3b 66 scsi^rst 99 bd1 132 ad28 nc = no connect res_dnc = reserved_do not connect. amd 2-11 signal descriptions 2.4.2 listed by pin name pin name pin no. ack 83 ad0 57 ad1 56 ad2 54 ad3 53 ad4 52 ad5 51 ad6 49 ad7 48 ad8 45 ad9 44 ad10 42 ad11 41 ad12 40 ad13 39 ad14 38 ad15 36 ad16 22 ad17 21 ad18 19 ad19 18 ad20 16 ad21 15 ad22 13 ad23 12 ad24 6 ad25 5 ad26 3 ad27 2 ad28 132 ad29 131 ad30 129 ad31 128 pin name pin no. atn 65 ba0 106 ba1 111 ba2 112 ba3 114 ba4 115 ba5 118 ba6 123 ba7 126 bd0 101 bd1 99 bd2 97 bd3 95 bd4 94 bd5 93 bd6 90 bd7 89 boot 100 bsy 64 busy 62 c/ be 047 c/ be 135 c/ be 223 c/ be 37 c /d 86 clk 121 devsel 27 frame 24 i /o 87 idsel 9 inta 117 irdy 25 lck 105 pin name pin no. lock 29 msg 85 nc 10 nc 92 nc 102 nc 107 nc 110 oe 104 par 34 pci^gnt 124 pci^req 127 pci^rst 120 perr 31 pwdn 58 req 81 res_dnc 116 scsi^rst 66 scsiclk1 60 sd 068 sd 169 sd 270 sd 371 sd 473 sd 574 sd 675 sd 777 sd p78 sel 80 serr 32 stop 28 trdy 26 v dd 8 v dd 59 pin name pin no. v dd 84 v dd 91 v dd 96 v dd 103 v dd 108 v dd 109 v dd 122 v dd3b 1 v dd3b 17 v dd3b 33 v dd3b 46 v ddb 76 v ss 11 v ss 30 v ss 61 v ss 63 v ss 79 v ss 88 v ss 98 v ss 113 v ss 119 v ss 125 v ss3b 4 v ss3b 14 v ss3b 20 v ss3b 37 v ss3b 43 v ss3b 50 v ss3b 55 v ss3b 130 v ssb 67 v ssb 72 v ssb 82 nc = no connect res_dnc = reserved_do not connect. amd signal descriptions 2-12 2.5 pin out map 19113a-4 132 1 ad28 ad29 131 v ss3b 130 ad30 129 ad31 128 pci^req 127 ba7 126 v ss 125 pci^gnt 124 ba6 123 v dd 122 clk 121 pci^rst 120 v ss 119 ba5 118 inta 117 res_dnc 116 ba4 115 ba3 114 v ss 113 ba2 112 ba1 111 nc 110 v dd 109 v dd 108 nc 107 ba0 106 lck 105 oe 104 v dd 103 nc 102 bd0 101 boot 100 bd1 99 v ss 98 bd2 97 v dd 96 bd3 95 bd4 94 bd5 93 nc 92 v dd 91 bd6 90 bd7 89 v ss 88 i /o 87 c /d 86 msg 85 v dd 84 ack 83 v ssb 82 req 81 sel 80 v ss 79 sd p 78 sd 7 77 v ddb 76 sd 6 75 sd 5 74 sd 4 73 v ssb 72 sd 3 71 sd 2 70 sd 1 69 sd 0 68 v ssb 67 34 par 35 c/ be 1 36 ad15 37 v ss3b 38 ad14 39 ad13 40 ad12 41 ad11 42 ad10 43 v ss3b 44 ad9 45 ad8 46 v dd3b 47 c/ be 0 48 ad7 49 ad6 50 v ss3b 51 ad5 52 ad4 53 ad3 54 ad2 55 v ss3b 56 ad1 57 ad0 58 59 v dd 60 scsiclk1 61 v ss 62 busy 63 v ss 64 bsy 65 atn 66 scsi^rst v dd3b 2 ad27 3 ad26 4 v ss3b 5 ad25 6 ad24 7 c/ be 3 8 v dd 9 idsel 10 nc 11 v ss 12 ad23 13 ad22 14 v ss3b 15 ad21 16 ad20 17 v dd3b 18 ad19 19 ad18 20 v ss3b 21 ad17 22 ad16 23 c/ be 2 24 frame 25 irdy 26 trdy 27 devsel 28 stop 29 lock 30 v ss 31 perr 32 serr 33 v dd3b pwdn pc scsi ii (AM53C974A) amd 2-13 signal descriptions 2.6 nand tree testing the AM53C974A pc scsi ii controller provides a nand tree test mode to allow conne- ctivity checking to the device on a printed circuit board. the nand tree is built on all pci bus signals. the nand tree test is enabled by asserting pci^rst . all pci signals will become inputs when pci^rst is asserted. the result of the nand tree test can be observed on the busy pin. figure 2-2 nand tree 19113a-5 pci^rst (pin 120) inta (pin 117) v dd clk (pin 121) pwdn (pin 58) busy (pin 62) a b s mux o busy pc scsi ii amd signal descriptions 2-14 pin 120 ( pci^rst ) is the first input to the nand tree. pin 117 ( inta ) is the second input to the nand tree, followed by pin 121 (clk). all other pci bus signals follow, counter- clockwise, with pin 58 (pwdn) being the last. pins labeled nc and power supply pins are not part of the nand tree. the table below shows the complete list of pins con- nected to the nand tree. nand nand nand tree tree tree input # pin # name input # pin # name input # pin # name 1 120 pci^rst 19 16 ad20 37 39 ad13 2 117 inta 20 18 ad19 38 40 ad12 3 121 clk 21 19 ad18 39 41 ad11 4 124 pci^gnt 22 21 ad17 40 42 ad10 5 127 pci^req 23 22 ad16 41 44 ad9 6 128 ad31 24 23 c/ be 2 42 45 ad8 7 129 ad30 25 24 frame 43 47 c/ be 0 8 131 ad29 26 25 irdy 44 48 ad7 9 132 ad28 27 26 trdy 45 49 ad6 10 2 ad27 28 27 devsel 46 51 ad5 11 3 ad26 29 28 stop 47 52 ad4 12 5 ad25 30 29 lock 48 53 ad3 13 6 ad24 31 31 perr 49 54 ad2 14 7 c/ be 332 32 serr 50 56 ad1 15 9 idsel 33 34 par 51 57 ad0 16 12 ad23 34 35 c/ be 1 52 58 pwdn 17 13 ad22 35 36 ad15 18 15 ad21 36 38 ad14 pci^rst must be asserted (logic low) to start a nand tree test sequence. initially, all nand tree inputs except pci^rst should be driven high. this will result in a low output at the busy pin. if the nand tree inputs are driven low in the same order as they are connected to build the nand tree, busy will toggle every time an additional input is driven low. busy will change to a one, when inta is driven low and all other nand tree inputs stay high. busy will toggle back to low, when clk is additionally driven low. the square wave will continue until all nand tree inputs are driven low. busy will be high when all nand tree inputs are driven low. when testing is complete, deassert pci^rst to exit this test mode. note: some of the pins connected to the nand tree are outputs in normal mode of operation. they must not be driven from an external source until the pc scsi controller is configured for nand tree testing. amd 2-15 signal descriptions figure 2-3 nand tree waveform 19113a-6 pcirst inta clk pcignt pcireq ad[31:0] c/ be [3:0] idsel frame irdy trdy devsel stop lock perr serr ffffffff 31 0000ffff f 7 par pwdn 0 busy amd signal descriptions 2-16 2.7 AM53C974A register map configuration register map 31 16 15 0 device id vendor id 00h status command 04h base class sub class prog. if. revision id 08h bist* header type* latency timer cache line size* 0ch base address 10h reserved* 14h C 38h expansion rom base address 30h reserved* 34h C 38h max_lat min_gnt interrupt pin interrupt line 3ch reserved for reserved for reserved for reserved for 40h C scsi software scsi software scsi software scsi software 4ch** * not implemented on AM53C974A. writes to these locations will have no effect; reads from these locations will return 00h. ** reserved for scsi software. scsi register map register acronym address (hex.) register description type ctcreg (b)+00 current transfer count register low r stcreg (b)+00 start transfer count register low w ctcreg (b)+04 current transfer count register middle r stcreg (b)+04 start transfer count register middle w ffreg (b)+08 scsi fifo register r/w cmdreg (b)+0c scsi command register r/w statreg (b)+10 scsi status register r sdidreg (b)+10 scsi destination id register w instreg (b)+14 interrupt status register r stimreg (b)+14 scsi timeout register w isreg (b)+18 internal state register r stpreg (b)+18 synchronous transfer period register w cfireg (b)+1c current fifo/internal state register r sofreg1 (b)+1c synchronous offset register w cntlreg1 (b)+20 control register one r/w clkfreg (b)+24 clock factor register w res (b)+28 reserved w cntlreg2 (b)+2c control register two r/w cntlreg3 (b)+30 control register three r/w cntlreg4 (b)+34 control register four r/w ctcreg (b)+38 current transfer count register high/part-unique id code r stcreg (b)+38 start current transfer count register high w res (b)+3c reserved w amd 2-17 signal descriptions dma register map register acronym address (hex.) register description type cmd (b)+40 command r/w stc (b)+44 starting transfer count r/w spa (b)+48 starting physical address r/w wbc (b)+4c working byte counter r wac (b)+50 working address counter r status (b)+54 status register r smdla (b)+58 starting memory descriptor list (mdl) address r/w wmac (b)+5c working mdl counter r sbac (b)+70 scsi bus and control * *certain bits are read/write, certain bits are read only. refer to the sbac (scsi bus and control) register for more detail. amd signal descriptions 2-18 3-1 power management features power management features 3 3.1 introduction as a leader in low-voltage technology, amd has incorporated power-saving features into the AM53C974A. through hardware and software or just software alone, the AM53C974A can be powered down to reduce consumption during chip inactivity. this significantly reduces overall power usage, as the system and associated peripherals can benefit from these features. 3.2 scsi activity indicators the scsi bus activity can be monitored through hardware or software. through the hardware, the scsi bus activity is reflected by the busy output pin. this pin, when active, indicates that the scsi bus is in use and therefore the AM53C974A should not be powered down. similarly, the scsi activity can also be monitored through software by polling the sbsy bit (bit 20) in the sbac register ((b)+70). both these indicators are the logical equivalent to the scsi bus signal bsy ored with sel . however, they are not physically connected to the bsy signal on the scsi bus. to correctly identify the bus free state on the scsi bus, either the busy pin or the sbsy bit must be inactive for at least 250 ms (selection timeout period). once this condition is valid, the scsi software can safely commence the power down sequence. note that if the busy pin is used to detect scsi bus free condition, then external logic on the host must drive the pwdn pin to notify the scsi software to commence the power down sequence. 3.2.1 reduced power mode when the scsi bus is free and there are no pending commands, the AM53C974A may be powered down by turning off the input buffers on the scsi bus lines. this is done by setting bit 5 in control register four (b)+34h. additionally, for further power reduction, the internal registers may be programmed to a predetermined state, and the clock to the scsi core disconnected via the pwd bit (bit 21) in the sbac register ((b)+70). however before disconnecting the clock from the scsi core, the state of the scsi bus should first be saved. this can be done through use of the scratch registers in the pci configuration space starting at address 40h. 3.3 power down pin (pwdn pin) when the pwdn pin is driven active, it sets the pwdn bit in the status register (bit 0, dma status register (b)+54h), signaling the AM53C974A that the host would like to power down the scsi interface. an interrupt is generated when this bit is set. 3.3.1 software disk spin-down incorporated into the scsi rom bios and certain device drivers of amds software solution is a module which physically spins down scsi fixed disks when the host system elects to enact power management on the scsi system. the software module is activated upon the rom bios and/or other device drivers receipt of an interrupt caused by the pwdn pin being driven active. upon receipt of this interrupt, the current software process is suspended and software control is given to the power management module. amd power management features 3-2 when the power management module is activated, it checks the status of all scsi fixed disks on the system under its control. the scsi fixed disks that are idle are issued a command to spin down their media. all fixed disks that are active at the time will be scheduled for spin down upon completion of their pending commands. once the bios and/or drivers have detected the completion of each fixed disks final pending com- mands, they are issued the command to spin down as well. to spin down the disk drives, the power management module issues a scsi command (1bC start/stop unit). when the command is received by the drive, it spins down and waits in an idle state. for multiple drives on the scsi bus, the power management driver spins down each drive individually. the drives remain in the idle state until the bios and/or driver receives a command for the particular fixed disk. once this occurs, the drive is issued the command to spin up. when the drive has completely spun up and is ready, the pending command is issued to the drive. only the particular fixed disk issued the command is instructed to spin up. all other drives will remain in the spun down state until a command is issued to them. note: this sequence does not turn off the scsi input buffers as described in the previ- ous section. 4-1 the pci bus interface unit the pci bus interface unit 4 4.1 introduction the AM53C974A handles all pci bus accesses through its pci bus interface unit (biu). the pci biu interprets and generates all pci bus signals in accordance with the pci specification rev 2.0. in addition to interfacing the AM53C974A with the pci bus, the pci biu also contains a 256 byte pci configuration register which is accessible via configuration read/write cycles from the pci bus. this chapter covers the pci block of the AM53C974A pci scsi ii controller. the AM53C974As i/o address map, pci bus cycles and modes supported are described in detailed as well as the function and contents of its pci configuration registers. for more information on the pci bus protocol, refer to the pci local bus specification . 4.2 addressing pci defines three physical address spaces: memory, i/o, and configuration. the memory and i/o address space are customary while configuration has been defined to support pci hardware. AM53C974A accesses to the memory space requires a memory read/write command to the desired memory location while host cpu accesses to the i/o space requires an i/o read/write command to the location specified by the base address register of the devices configuration space. that is, the value written to the base address register of the configuration space defines the base i/o location of the AM53C974A. configuration accesses to the AM53C974A are done by issuing a configuration read/write command with the AM53C974A idsel line asserted. 4.3 bus acquisition the first step in any AM53C974A bus master transfer is to acquire ownership of the bus. this task is handled by synchronous logic within the pci biu. bus ownership is requested with the pci^req signal and ownership is granted by the arbiter through the pci^gnt signal. figure 4-1 shows the AM53C974As bus acquisition timing. in this figure, although bus ownership is granted on clock 3 with the assertion of pci^gnt , the AM53C974A will not assert frame (indicating the start of bus cycle) until clock 5. note, however, that although the AM53C974A will begin driving ad[31:0] and c/ be [3:0] prior to clock 4, these lines will not be valid until frame is asserted. adstep (bit 7) in the pci command register is set to one to indicate that the AM53C974A uses address stepping. however, address stepping is only used for the first address phase of a bus master period. amd the pci bus interface unit 4-2 figure 4-1 bus acquisition timing 19113a-7 12 3456 clk frame ad c/ be pci^gnt pci^req addr cmd 4.4 bus cycle definition the AM53C974A supports only the relevant pci bus cycles (eight of the sixteen cycles). these cycles are defined by the c/ be [3:0] command lines during the address phase of each pci bus cycle. table 4-1 shows these bus cycles and the mode supported by the AM53C974A. note that bus cycles with an asterisk (*) are ignored by the AM53C974A, while those with double asterisks (**) are aliased to the slave memory read cycle. table 4-1 pci bus cycles supported by the AM53C974A c/ be [3:0] bus cycle type mode supported 0000 interrupt ack * 0001 special cycle * 0010 i/o read slave 0011 i/o write slave 0100 reserved * 0101 reserved * 0110 memory read master, slave 0111 memory write master, slave*** 1000 reserved * 1001 reserved * 1010 config. read slave 1011 config. write slave 1100 mem read multiple **slave 1101 dual address cycle * 1110 mem read line master, **slave 1111 mem write & invalidate * * these cycles are ignored by the AM53C974A. ** both the slave memory read line and slave memory read multiple cycles are aliased to the slave memory read cycle. *** slave memory write commands to the AM53C974A will complete normally but the data is ignored by the device. amd 4-3 the pci bus interface unit 4.5 bus cycle diagrams the following are samples of the AM53C974As bus cycles in table 4-1. each cycle shows an example timing diagram along with a brief description of the cycle. note that the cycles shown are only typical pci bus cycles; each cycle can be distinct because of various factors such as bus latency, irdy and trdy timing, etc. 4.5.1 slave i/o read the slave i/o read command is used by the processor to read internal registers in the AM53C974A. it is a single cycle, non_burst 8-bit, 16-bit, or 32-bit transfer which is initiated by the host cpu. the AM53C974A will not produce slave i/o read commands while a bus master. slave i/o read cycles are fixed length cycles, i.e. the AM53C974A will return trdy on the 10th bus cycle of the transfer. figure 4-2 shows the timing for a slave i/o read bus cycle. figure 4-2 slave i/o read timing 19113a-8 123 4 5 6 7 8 9 10 11 12 clk frame ad c/ be par serr perr irdy trdy devsel addr data 0010 be par par serr perr amd the pci bus interface unit 4-4 4.5.2 slave i/o write the slave i/o write command is used by the processor to write the internal registers in the AM53C974A. it is a single cycle, non-burst 8-bit, 16-bit, or 32-bit transfer which is initiated by the host cpu. the AM53C974A will not produce slave i/o write commands while a bus master. slave i/o write cycles are fixed length cycles, i.e. the AM53C974A will return trdy on the 10th bus cycle of the transfer. figure 4-3 shows the timing for a slave i/o write bus cycle. figure 4-3 slave i/o write timing 19113a-9 1 23 4567 89101112 clk frame ad c/ be par serr perr irdy trdy devsel addr data 0011 be par par serr perr amd 4-5 the pci bus interface unit 4.5.3 master memory read the master memory read command is used by the AM53C974A when it will be reading 2 or less 32-bit locations of memory. if the device needs to read more than 2 double- words (dwords) of memory, the master memory read line command is used. fig- ure 4-4 shows an example timing diagram for a master memory read command. in this figure, the device issues a request for the bus, is granted access, and then reads a 32-bit dword from system memory before releasing the bus. the data phase in this diagram takes two clock cycles, this being determined by the timing of trdy . note that during a master memory read, the AM53C974A will always activate all byte enables, even though some byte lanes may not contain valid data. in such instances, the AM53C974A will internally discard unnecessary bytes. figure 4-4 master memory read timing 19113a-10 1 23 4567 8 clk frame ad c/ be par serr perr irdy trdy devsel addr data 0110 be par serr par perr pci^req pci^gnt 910 amd the pci bus interface unit 4-6 4.5.4 slave memory read the slave memory read command is used by the processor to read data from the AM53C974As expansion rom. this is a single cycle, non-burst 8-bit,16-bit, or 32-bit transfer which is initiated by the host cpu. the AM53C974A will always respond to this cycle by returning valid data on all byte lanes. thus, it is the responsibility of the host to discard any unneccessary bytes via the c/ be [3:0] lines. the AM53C974A will not produce slave memory read commands while a bus master. slave memory read cycles are fixed length cycles, i.e. the AM53C974A will return trdy on the 54th bus cycle of the transfer. figure 4-5 shows the timing for a slave memory read bus cycle. note that the slave memory read multiple and the slave memory read line commands are aliased to the slave memory read command. figure 4-5 slave memory read timing 19113a-11 12345 5354 clk frame ad c/ be par serr perr irdy trdy devsel addr 0110 be par serr par perr stop data amd 4-7 the pci bus interface unit 4.5.5 master memory write the master memory write command is used by the AM53C974A when it will be writing to memory. figure 4-6 shows an example timing diagram for a master memory write command. in this figure, the device issues a request for the bus, is granted access, and then writes a 32-bit dword into system memory before releasing the bus. note that in this example, the data phase transfer takes 2 clock cycles. the timing of this transfer, in this case, was controlled by trdy . figure 4-6 master memory write timing 1 23 4567 8 clk frame ad c/ be par serr perr irdy trdy devsel addr data 0111 be par serr par perr pci^req pci^gnt 910 19113a-12 amd the pci bus interface unit 4-8 4.5.6 slave configuration read the slave configuration read command is used by the host cpu to read the pci configuration space in the AM53C974A. this provides the host cpu with information concerning the device and its capabilities. this is a single cycle, non-burst 8-bit, 16-bit, or 32-bit transfer. slave configuration read cycles are fixed length cycles, i.e. the AM53C974A will return trdy on the 5th bus cycle of the transfer. figure 4-7 shows the configuration read cycle timing. figure 4-7 slave configuration read timing 1 2 3 4567 8 clk frame ad c/ be par serr perr irdy trdy idsel addr data 1010 be serr perr par par devsel 19113a-13 amd 4-9 the pci bus interface unit 4.5.7 slave configuration write the slave configuration write command is used by the host cpu to write the configura- tion space in the AM53C974A. this allows the host cpu to control basic activity of the device, such as enable/disable, change i/o location, etc. this is a single cycle, non- burst 8-bit, 16-bit, or 32-bit transfer. slave configuration write cycles are fixed length cycles, i.e. the AM53C974A will return trdy on the 5th bus cycle of the transfer. figure 4-8 shows the configuration write cycle timing. figure 4-8 slave configuration write timing 1 2345678 clk frame ad c/ be par serr perr irdy trdy idsel addr data 1011 be serr perr par par devsel 19113a-14 amd the pci bus interface unit 4-10 4.5.8 master memory read line the master memory read line command is used by the AM53C974A when it will be reading more than two 32-bit locations of memory. if the device needs to read less than 2 dwords of memory the master memory read command is used. figure 4-9 shows an example timing diagram for a master memory read line command. in this figure, the device issues a request for the bus, is granted access, and then reads four 32-bit dwords from system memory before releasing the bus. note that all data phases in this example take 2 clock cycles, this being determined by the timing of trdy . figure 4-9 master memory read line timing 1 2 3 4 5 6 7 8 9 10 11 12 clk frame ad c/be par serr perr irdy trdy devsel addr data 1110 be par serr perr data par par perr pci^req pci^gnt data data par par perr perr 13 14 19113a-15 amd 4-11 the pci bus interface unit 4.6 transaction termination termination of a pci transaction may be initiated by either the master or the target. during termination, the master remains in control to bring all pci transactions to an orderly and systematic conclusion regardless of what caused the termination. all transactions are concluded when frame and irdy are both deasserted, indicating an idle cycle. 4.6.1 target initiated termination when the AM53C974A is a bus master, the cycles it produces on the pci bus may be terminated by the target in one of three different ways: disconnect with data transfer, disconnect without data transfer, and target abort. 4.6.1.1 disconnect with data transfer figure 4-10 shows a disconnection in which one last data transfer occurs after the target asserted stop . stop is asserted on clock 4 to start the termination sequence. data is still transferred during this cycle, since both irdy and trdy are asserted. the AM53C974A terminates the current transfer with the deassertion of frame on clock 5 and then one clock cycle later with the deassertion irdy . it finally releases the bus on clock 6. the AM53C974A will re-request the bus after 2 clock cycles, if it wants to transfer more data. the starting address of the new transfer will be the address of the next untransferred data. figure 4-10 disconnect with data transfer 19113a-16 frame clk ad irdy trdy c/ be devsel pci^req pci^gnt 1234567 8 data data 0000 0111 10 9 par par par par devsel is sampled by the AM53C974A stop 0111 11 addr +8 i addr i amd the pci bus interface unit 4-12 4.6.1.2 disconnect without data transfer figure 4-11 shows a target disconnect sequence during which no data is transferred. stop is asserted on clock 4 without trdy being asserted at the same time. the AM53C974A terminates the current transfer with the deassertion of frame on clock 5 and one clock cycle later with the deassertion of irdy . it finally releases the bus on clock 6. the AM53C974A will re-request the bus after 2 clock cycles to retry the last transfer. the starting address of the new transfer will be the same address as the last untransferred data. figure 4-11 disconnect without data transfer 19113a-17 frame clk ad irdy trdy c/ be devsel pci^req pci^gnt 1234567 8 data 0000 0111 10 9 par par par devsel is sampled by the AM53C974A stop 0111 11 addr i addr i amd 4-13 the pci bus interface unit 4.6.1.3 target abort figure 4-12 shows a target abort sequence. the target asserts devsel for one clock. it then deasserts devsel and asserts stop on clock 4. a target can use the target abort sequence to indicate that it cannot service the data transfer and that it does not want the transaction to be retried. additionally, the AM53C974A cannot make any assumption about the success of the previous data transfers in the current transaction. the AM53C974A terminates the current transfer with the deassertion of frame on clock 5 and one clock cycle later with the deassertion of irdy . it finally releases the bus on clock 6. since data integrity is not guaranteed, the AM53C974A cannot recover from a target abort event. any on-going scsi activity will be stopped immediately and an interrupt will be generated. the abort and error bits will be set in the dma status register. the pci configuration registers will not be cleared. rtabort (bit 12) in the pci configura- tion space status register will be set to indicate that the AM53C974A has received a target abort. figure 4-12 target abort 19113a-18 frame clk ad irdy trdy c/ be devsel pci^req pci^gnt 123456 data 0000 0111 par par par devsel is sampled by the AM53C974A stop addr amd the pci bus interface unit 4-14 4.6.2 master initiated termination there are two scenarios besides normal completion of a transaction where the AM53C974A will terminate the cycles it produces on the pci bus. these are preemption and master abort. 4.6.2.1 preemption the central arbiter can take pci^gnt to the AM53C974A away if the current bus operation takes too long. this may happen during dma bursts. when pci^gnt is removed and the value in the latency timer register has counted to zero, the AM53C974A will finish the current transfer and then immediately release the bus. the latency timer in pci configuration space of the AM53C974A is programmable. the AM53C974A will keep pci^req asserted to regain bus ownership as soon as possible. figure 4-13 preemption 19113a-19 frame clk ad irdy trdy c/ be devsel pci^req pci^gnt 12345678 addr data data data 0000 0111 9 par par par par devsel is sampled by the AM53C974A amd 4-15 the pci bus interface unit 4.6.2.2 master abort the AM53C974A will terminate its cycle with a master abort sequence if devsel is not asserted within 4 clocks after frame is asserted. master abort is treated as a fatal error by the AM53C974A. any on-going scsi activity will be stopped immediately and an interrupt will be generated. the abort and error bits will be set in the dma status register. the pci configuration registers will not be cleared. rmabort (bit 13) in the pci configuration space status register will be set to indicate that the AM53C974A has terminated its transaction with a master abort. figure 4-14 master abort 19113a-20 frame clk ad irdy trdy c/ be devsel pci^req pci^gnt 12345678 addr data 0000 0111 10 9 par par par devsel is sampled by the AM53C974A amd the pci bus interface unit 4-16 4.7 configuration registers pci configuration registers are used to determine which devices are in the system as well as to configure those devices. configuration registers can be accessed any time but only by pci configuration read/write cycles. this space is divided into two regions: a predefined header region and a device dependent region. the predefined header region contains 64 bytes organized as 4 dwords while the device dependent region may contain up to 192 bytes also organized as 4 dwords. the AM53C974A supports the full 64 byte predefined header and only 16 bytes of the device dependent region. table 4-2 shows the configuration register map for both these regions. in table 4-2, the first 64 bytes (00h C 3fh) are the predefined header and the last 16 reserved bytes (40h C 4fh) belong to the device dependent space. table 4-2 configuration register map 31 16 15 0 address offset device id vendor id 00h status command 04h base class sub class prog. if. revision id 08h reserved* header type latency timer reserved* 0ch base address 10h reserved* 14h reserved* 18h reserved* 1ch reserved* 20h reserved* 24h reserved* 28h reserved* 2ch expansion rom base address 30h reserved* 34h reserved* 38h max_lat min_gnt interrupt pin interrupt line 3ch reserved for reserved for reserved for reserved for 40h** scsi software scsi software scsi software scsi software reserved for reserved for reserved for reserved for scsi software scsi software scsi software scsi software 44h** reserved for reserved for reserved for reserved for scsi software scsi software scsi software scsi software 48h** reserved for reserved for reserved for reserved for scsi software scsi software scsi software scsi software 4ch** * not implemented on AM53C974A. writes to these locations will have no effect; reads from these locations will return 00h. ** reserved for scsi software. all pci compliant devices, including the AM53C974A, must support the vendor id, device id, command and status register in the header portion. implementation of the other registers in this header is optional depending on device functionality. in table 4-2, an asterisk (*) means the location is not implemented on the AM53C974A while a double asterisk (**) specifies that the location is reserved for use by the scsi software. write operations to unimplemented registers in the configuration space are treated as no-ops. that is, the access will be completed normally on the bus and the data dis- carded. read accesses to unimplemented registers are completed normally and a data value of 00h is returned. amd 4-17 the pci bus interface unit 4.7.1 predefined header register description the following only describes the functions of the registers that are supported by the AM53C974A. refer to the pci local bus specification for more detailed information on pci registers. 4.7.1.1 vendor id register address 00h read only this register identifies the manufacturer of this device as advanced micro devices, inc. (amd) the vendor id is 1022h. 4.7.1.2 device id register address 02h read only this register uniquely identifies this device within amds product line. the AM53C974A device id is 2020h. 4.7.1.3 command register address 04h read/write the command register is used to control the gross functionality of the device. it controls a devices ability to generate and respond to pci bus cycles. to logically disconnect the AM53C974A from all pci bus cycles except configuration cycles, a value of zero should be written to this register. the command register is cleared by a pci reset. reserved reserved reserved reserved reserved reserved fbtben serren 00000000 15 14 13 12 11 10 9 8 adstep perren vgasnoop mwien scycen bmen memen ioen 10000000 76543210 bit 15:10 C reserved these 6 bits are reserved by the pci specification. write operations to these locations have no affect on the device. read operations from these locations will return 0s. bit 9 C fbtben C fast back-to-back enable this bit is hardwired to a value of 0 since AM53C974A back-to-back transactions are only allowed to the same agent. amd the pci bus interface unit 4-18 bit 8 C serren - serr enable this read/write bit is an enable bit for the serr driver. when this bit is set to 1, the serr driver is enabled. when this bit is reset to 0, the serr driver is disabled. this bit and bit 6 (parity error response) must be set to 1 to report address parity errors. this bits state is zero after a device reset. bit 7 C adstep C wait cycle control this bit is hardwired to a value of 1 since the AM53C974A always does address stepping. the AM53C974A uses address stepping for the first address phase of each bus master period. frame will be asserted on the second clock following the assertion of pci^gnt , indicating a valid address on the ad bus. bit 6 C perren C parity error response enable this read/write bit controls the AM53C974As response to parity errors. when perren is 0 and the AM53C974A detects a parity error, it only sets the detected parity error bit in the pci configuration space status register. when perren is 1, the AM53C974A asserts perr on the detection of a data parity error. it also sets the dataperr bit (bit 8 in the pci configuration space status register) when the data parity error occurred during a master cycle. perren also enables reporting address parity errors through the serr pin and the serr bit in the pci configuration space status register. this bit must be reset to 0 after pci^rst . parity is still generated by the device even if this bit is disabled (0). bit 5 C vgasnoop C vga palette snoop this bit is hardwired to a value of 0 since the AM53C974A is not a graphics device. bit 4 C mwien C memory write & invalidate enable this bit is hardwired to a value of 0 since the AM53C974A does not generate memory write & invalidate commands. instead, the memory write command must be used. bit 3 C scycen C special cycles enable the AM53C974A will ignore all special cycle operations since this bit is hardwired to a value of 0. bit 2 C bmen C bus master enable this read/write bit controls the AM53C974As ability to act as a master on the pci bus. when this bit is 0, the device is disabled from generating pci accesses. when this bit is 1, the device is allowed to behave as a bus master. bit 1 C memen C memory space enable this bit is programmable to allow support for expansion rom accesses. this bit must be set to 1 before the expansion rom can be accessed. when this bit is 0, access to the boot rom is disabled. bit 0 C ioen C i/o space enable this read/write bit controls the AM53C974As response to i/o space accesses. when this bit is 0, the device will not respond to i/o space accesses. when this bit is 1, the device is allowed to respond to i/o space accesses. the host must set ioen before the first i/o access to the device. the base address register at address (10h) must be programmed with a valid i/o address before setting ioen. amd 4-19 the pci bus interface unit 4.7.1.4 status register address 06h read/write the status register is used to record status information for pci bus related activities. reads from this register function normally, however writes function differently. on a write of 1, bits will be reset (from 1 to 0), not set. for example, to reset bit 15 and not affect any other bits, a value of 1000_0000_0000_0000 should be written to the status register. perr serr rmabort rtabort stabort devsel1 devsel0 dataperr xxxxx01x 15 14 13 12 11 10 9 8 fbbok reserved reserved reserved reserved reserved reserved reserved 00000000 76543210 bit 15 C perr C detected parity error this bit is used by the AM53C974A to report parity errors. this bit is set to 1 whenever the device detects a parity error. this bit is cleared by writing a 1 to this location. the value of this bit is undefined after a device reset. the AM53C974A samples the ad(31:00), c/ be (3:0) and the par lines for a parity error at the following times: in slave mode, during the address phase of any pci bus command. in slave mode, during the data phase of all i/o and configuration write commands that select the AM53C974A. in master mode, during the data phase of all memory read and memory read line commands. during the data phase of the memory write command, the AM53C974A sets the perr bit if the target reports a data parity error by asserting the perr signal. perr is not affected by the state of the parity error response enable bit (bit 6 in the pci configura- tion space command register). bit 14 C serr C signaled system error this bit is set to 1 when the serr pin is asserted. this bit is cleared by writing a 1 to this location. bit 13 C rmabort C received master abort as a bus master, the AM53C974A will set this bit to 1 whenever its transaction is terminated with a master-abort. this bit is cleared by writing a 1 to this location. bit 12 C rtabort C received target abort as a bus master, the AM53C974A will set this bit to 1 whenever its transaction is terminated with a target-abort. this bit is cleared by writing a 1 to this location. bit 11 C stabort C signaled target abort as a target device, this bit is set to 1 by the AM53C974A whenever it terminates a transaction with a target-abort. this bit is cleared by writing a 1 to this location. amd the pci bus interface unit 4-20 bit 10:9 C devsel1:0 C devsel timing these bits encode the timing of the devsel signal. these bits are hardwired to a value of 0 and 1 (for bits 10 and 9 respectively) since the AM53C974A uses medium assertion timing for the devsel signal. that is, devsel is asserted two clocks after frame is asserted. these bits are read-only and indicate the time that the AM53C974A asserts devsel for any bus command. bit 8 C dataperr C data parity detected dataperr is set when the AM53C974A detects a data parity error during master mode and the parity error response enable bit (bit 6 in the pci configuration space command register) is set. during the data phase of all memory read and memory read line commands, the AM53C974A checks for parity errors by sampling the ad(31:00), c/ be (3:0) and the par lines. during the data phase of all memory write commands, the AM53C974A checks the perr input to detect whether the target has reported a parity error. dataperr is set by the AM53C974A and is cleared by writing a 1 to this location. writing a 0 has no effect. bit 7 C fbbok C fast back-to-back capable this bit is hardwired to a value of 0 since the AM53C974A is not capable of accepting fast back-to-back transactions when the transactions are not to the same agent. bit 6C0 C reserved these 7 bits are reserved by the pci specification. write operations to these locations have no affect on the device. read operations from these locations will return 0s. 4.7.1.5 revision id register address 08h read only this register specifies the device specific revision number. on the AM53C974A, the value of this register is 10h. 4.7.1.6 programming interface register address 09h read only this register identifies the programming interface of this device. the value in this register is 00h. 4.7.1.7 sub-class register address 0ah read only this register identifies this device as a scsi controller as defined by the pci specifica- tion. the value in this register is 00h. 4.7.1.8 base class register address 0bh read only this register identifies this device as a mass storage controller as defined by the pci specification. the value in this register is 01h. 4.7.1.9 latency timer register address 0dh read/write this register specifies the maximum time the AM53C974A can continue with bus master transfers after the system arbiter has removed pci^gnt . the time is measured in clk amd 4-21 the pci bus interface unit cycles. the working copy of the timer will start counting down when the AM53C974A asserts frame for the first time during a bus mastership period. the counter will freeze at zero. when the counter is zero and pci^gnt is deasserted by the system arbiter, the AM53C974A will finish the current data phase and then immediately release the bus. the value for the AM53C974A latency timer register is programmable. 4.7.1.10 header type register address 0eh read only funct layout6 layout5 layout4 layout3 layout2 layout1 layout0 00000000 76543210 this is an 8-bit register that describes the format of the pci configuration space locations 10h to 3ch and that identifies a device to be single or multi-function. this register is located at address 0eh in the pci configuration space and is read only. the value contained in this register is 00h. 4.7.1.11 base address register address 10h read/write this read/write register defines the base address for the AM53C974A. bit 0 is hard- wired to a value of 1 to indicate that the base address is mapped into the i/o space while bit 1 is reserved and will always return a 0 when read. that is, a value of 01 for bits 1 and 0 respectively will be returned on reads. iobase26 iobase25 iobase24 iobase23 iobase22 iobase21 iobase20 iobase19 xxxxxxxx 31 30 29 28 27 26 25 24 iobase18 iobase17 iobase16 iobase15 iobase14 iobase13 iobase12 iobase11 xxxxxxxx 23 22 21 20 19 18 17 16 iobase10 iobase9 iobase8 iobase7 iobase6 iobase5 iobase4 iobase3 xxxxxxxx 15 14 13 12 11 10 9 8 iobase2 iobase1 iobase0 iosize2 iosize1 iosize0 reserved iospace x0000001 76543210 amd the pci bus interface unit 4-22 bit 31:5 C iobase 26:0 C i/o base address these bits are written by the host to specify the location of the AM53C974A in all of i/o space. iobase 26:0 must be written with a valid address before the AM53C974A slave i/o mode is turned on with the setting of the ioen bit (bit 0 in the pci configuration space command register). when the AM53C974A is enabled for i/o mode (ioen is set), it monitors the pci bus for a valid i/o command. if the value on ad(31:05) during the address phase of the cycles matches the value of iobase, the AM53C974A will drive devsel indicating it will respond to the access. iobase 26:2 is read and written by the host. iobase 1:0 is hardwired to 0. bit 4:2 C iosize 2:0 C i/o size requirements iosize 2:0 together with iobase 1:0 and bits 1 and 0 indicate the size of the i/o space the AM53C974A requires. when the host writes a value of ffff_ffff to the base address register, it will read back a value of 0 in bits 6C1. this indicates an AM53C974A i/o space requirement of 128 bytes. bit 1 C reserved this bit is reserved. writes to this location have no effect. reads from this location will return a 0. bit 0 C iospace C i/o space indicator this bit indicates that the base address register describes an i/o base address. writes to this location have no effect. read from this location will return a 1. 4.7.1.12 expansion rom base address register address 30h read/write this is a 32-bit read/write register which is used to hold the expansion rom base address. it is used to specify the size and alignment of the expansion rom for the AM53C974A. it supports expansion roms of up to 64k. rom31 rom30 rom29 rom28 rom27 rom26 rom25 rom24 xxxxxxxx 31 30 29 28 27 26 25 24 rom23 rom22 rom21 rom20 rom19 rom18 rom17 rom16 xxxxxxxx 23 22 21 20 19 18 17 16 rom15 rom14 rom13 rom12 rom11 rom10 rom9 rom8 00000000 15 14 13 12 11 10 9 8 rom7 rom6 rom5 rom4 rom3 rom2 rom1 rom0 00000000 76543210 amd 4-23 the pci bus interface unit bit 31:16 C rom31:16 C rom base address these bits are programmable for storing the expansion rom base address. the values in these bits are unknown after power-on or reset. bit 15:11 C rom15:11 C rom alignment these bits are hardwired to 0, specifying a 64k alignment rom support. bit 10:1 C rom10:1 C reserved these bits are reserved as defined by the pci specification, rev 2.0. these bits will return a value of 0 when read. bit 0 C rom0 C rom address decodeenable this bit is used to enable/disable the rom address space decoding. when this bit is 0, the expansion rom address space is disabled. when this bit is 1, address decoding is enabled using the value programmed into bits 31:16 of this register. this bit will default to 0 after power-on or reset. 4.7.1.13 interrupt line register address 3ch read/write the interrupt line register is used to communicate the routing of the interrupt. this read/write register is written by the post (power-on self test) software as it initializes the pci devices in the system. the value in this register tells which input of the system interrupt controller(s) the AM53C974As interrupt pin is connected to. device drivers and operating systems can use this information to determine priority and vector information. values in the register are system architecture specific. for example, in x86 based pcs, the values in this register correspond to irq numbers (0C15) of the standard dual 8259 configuration. values between 15 and 255 are reserved. value 255 is defined as unknown or no connection to the interrupt controller. 4.7.1.14 interrupt pin register address 3dh read only this register indicates which interrupt pin the device is using. this register is hard wired with a value of 1 because the AM53C974A only uses inta . 4.7.1.15 min_gnt register address 3eh read only the min_gnt register is an 8-bit read only register. it is hardwired to a value of 04h. this value equals a burst period of 1 m s calculated at a 33 mhz clock rate. the register value specifies the time in units of 1/4 microseconds. the host should use the value of this register to determine the setting of the AM53C974As latency timer register. 4.7.1.16 max_lat register address 3fh read only the max_lat register is an 8-bit read only register. it is hardwired to a value of 28h. this value equals a pci bus latency of 10 m s calculated at a 33 mhz clock rate. the register value specifies the time in units of 1/4 microseconds. the host should use the value of this register to determine the setting of the AM53C974As latency timer register. amd the pci bus interface unit 4-24 4.7.2 device dependent register description the AM53C974A implements 16 bytes (4 dwords located at locations 40h, 44h, 48h, and 4ch) of the 192 byte device dependent registers. these 16 bytes are scratch data registers provided for use by scsi device drivers. developers of scsi device drivers for the AM53C974A can use these register for their own needs provided that amds scsi drivers are not used. if amd scsi drivers are used, these registers must not be modified. note that since these are scratch registers, they may be used to contain any data. for example, amds scsi drivers for the AM53C974A uses these registers to hold specific information concerning the state of the scsi bus and each target device connected. examples of information contained in these registers as used by amds drivers are current scsi bus status for each device, synchronous parameters, pro- tected/real mode driver initialization flags, etc. the next section describes how amds scsi device drivers take advantage of these registers. 4.7.3 amd's scratch register usage the registers located at locations 40h, 44h, 48h, and 4ch (table 4-1) are four 32-bit registers (16 bytes total) which are used by amds scsi device drivers to hold informa- tion about the state of the scsi bus and the target devices connected. table 4-3 illustrates how amds scsi software defines and uses these registers. in table 4-3, seven of the eight registers are used for target devices and one is used for the host. that is, there is one target configuration register for each scsi target and one host configuration register for the host. table 4-3 scratch register definition for amd's pc scsi software scsi configuration pci configuration register byte bits 15:0 0 41h, 40h scsi configuration register 0 1 43h, 42h scsi configuration register 1 2 45h, 44h scsi configuration register 2 3 47h, 46h scsi configuration register 3 4 49h, 48h scsi configuration register 4 5 4bh, 4ah scsi configuration register 5 6 4dh, 4ch scsi configuration register 6 7 4fh, 4eh scsi configuration register 7 the following define the scsi configuration registers for target devices and host adapters for the AM53C974A scsi software drivers. 4.7.3.1 target device configuration register definition read/write the target device configuration register layout is shown below. bit placements follow little endian ordering. reserved reserved fscsi spd4 spd3 spd2 spd1 spd0 00 0 xxxxx 15 14 13 12 11 10 9 8 amd 4-25 the pci bus interface unit soff3 soff2 soff1 soff0 status2 status1 status0 pres xxxxxxxx 76543210 bits 15:14 C reserved these 2 bits are reserved by amds scsi software driver. bit 13 C fscsi C fast scsi drive present this bit identifies the target as a fast scsi drive. a value of 1 indicates that a fast drive is present, while a 0 indicates either that a drive is not present, or that the drive is not capable of sustaining fast synchronous scsi transfers rates of 10 mbytes/s. this bit will default to a value of 0. note: this register is defined by amds pc scsi software and does not represent a change in the chips functionality. bits 12:8 C spd4:0 C synchronous period these bits define the synchronous period negotiated for the scsi target device. bits 7C4 C soff3:0 C synchronous offset these bits define the synchronous offset negotiated for the scsi target device in number of bytes. a value of 0 indicates asynchronous transfers. valid values are from 1 to 15 (bytes). bits 3:1 C status2:0 C scsi bus status these bits define the current state of the scsi target device relating to the scsi bus. valid values for the scsi bus status are as follows: bits 3:1 scsi bus status 000 data out phase 001 data in phase 010 command phase 011 status phase 100 idle 101 active and disconnected 110 message out phase 111 message in phase bit 0 C pres C present this bit is used to indicate that the target device is present and active. if this bit is set to 1, then the target device is present on the scsi bus and all other bits are considered valid. if this bit is reset to 0, then the target device is assumed to be not present on the scsi bus and all other bits must be reset to 0. the exception to this case is if the target present bit is reset to 0 and the scsi bus status bits are set to 1xx (where x is a dont care). in this case, the configuration register definition indicates the host adapter target id. amd the pci bus interface unit 4-26 4.7.3.2 host configuration register definition read/write the host adapter device configuration register layout is shown below. bit placements follow little endian ordering. reserved reserved reserved reserved reserved reserved reserved reset 00000000 15 14 13 12 11 10 9 8 sbnv sbn2 sbn1 sbn0 host protect rm tp 00001xx0 76543210 bits 15:9 C reserved these 7 bits are reserved by amds scsi software driver. bit 8 C reset C scsi bus reset has taken place if this bit is set to 1, it indicates that a scsi bus reset has occurred. this is useful for protected mode/real mode driver scsi controller sharing. if device configuration parameters, such as mode select information or synchronous negotiation, have been issued to the scsi devices, these parameters may no longer be valid upon the scsi bus reset. when this bit is set, it indicates to the non-controlling driver that a bus reset has occurred and that appropriate action should be taken. bit 7 C sbnv C starting bios number valid when set to 1, this bit indicates that the starting bios number (sbn2:0, bits 6C4) is valid. when reset to 0, the starting bios number is invalid. bit 6:4 C sbn2:0 C starting bios number these bits are valid if the starting bios number valid bit (bit 7) is set to 1. this value ranges from 0 to 7 and indicates the starting bios unit number of the scsi bios. for example, if the value is 1, this indicates that the scsi bios starts controlling fixed disks at bios unit 81h. if the value is 3, scsi bios fixed disks start at bios unit 83h and so on. bit 3 C host C host this bit is set to 1 to indicate that the device associated with this register is a host device. bit 2 C protect C protected mode driver initialized this bit is set to 1 when a protected mode device driver initializes the scsi controller. a real mode driver that regains control due to a mode change (i.e. windows to dos or netware 3.x to dos, etc.) will reset this bit to 0 to indicate that once the protected mode driver regains control of the scsi controller, it must re-initialize itself in order to continue proper operation. upon re-initialization of the scsi controller by the protected mode driver, this bit will once again be set to 1. bit 1 C rm C real mode driver initialized this bit is set to 1 when a real mode device driver initializes the scsi controller. a protected mode driver that loads and initializes will reset this bit to 0 to indicate that if and when the real mode driver regains control of the scsi controller, it must re-initialize amd 4-27 the pci bus interface unit itself in order to operate. upon re-initialization of the scsi controller by the real mode driver, this bit will once again be set to 1. bit 0 C tp C target present bit this bit is set to 0 and is used in conjunction with bit 3, which is set to 1, to indicate that this configuration register defines the host configuration. amd the pci bus interface unit 4-28 5-1 the fast scsi block the fast scsi block 5 5.1 functional overview the functionality of the scsi block is described in the following section. topics to be covered are: part-unique id scsi fifo threshold data transmission req / ack control parity reset levels 5.1.1 part-unique id the AM53C974A contains a part-unique id code which is stored in the msb of the current transfer count register. the code reflects the chips revision level and family code. this 8-bit code may be read when the following conditions are true. after power up or a chip reset has occurred before the current transfer counter ((b)+38h) is loaded the part-unique id code in register ((b)+38h) will read as follows: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00010010 5.1.2 scsi fifo threshold the threshold value for the scsi fifo is two bytes (one word). when this threshold is reached, the scsi block will indicate to the dma engine that it is capable of receiving or sending data bytes. 5.1.3 data transmission data transmission rates will vary from system to system, depending on the number of devices configured on the scsi bus, as well as the transfer rates that each individual device is capable of sustaining. transfer rates for the AM53C974A are controlled by the fastscsi and fastclk bits in control register three, as well as by the extended timing feature in control register one. the chart below shows the effects of different bit configurations on minimum asynchronous and synchronous cycle times. amd the fast scsi block 5-2 ext. timing min min min fastclk fastscsi mode cycles per cycles per cycles per cntl reg 3 cntl reg 3 cntl reg 1 data setup data setup period bit3 bit4 bit 7 asynch xfer synch xfer synch xfer 0x0225 0x1336 100338 101538 110324 111524 to achieve 10 mb/sec transmission rates, the following requirements must be true: a 40 mhz clock (50% duty cycle) must be supplied to scsiclk1. the target must be able to sustain fast scsi timings bits 3 and 4 in control register three must be set to 1 the lower three bits of register ((b)+24h), the clock conversion factor register must be programmed to 000 the lower 5 bits of the synchronous transfer period register ((b)+18h) must be set to a value of 04h. control register three contains two bits which modify the scsi state machine to produce both fast and normal scsi timings. synchronous data transmission rates are dependent on the input clock frequency selected, as well as the transfer period. the registers listed above should be programmed consistently. bits 4:0 in the synchronous transfer period register ((b)+18h) specify the timing between the leading edges of consecutive req and ack pulses during synchronous transfers. for programming information, refer to the register level descriptions. 5.1.4 req/ack control the assertion and deassertion time for the req and ack signals may be controlled via the synchronous offset register ((b)+1ch). bits 7:6 control req / ack deassertion delay, while bits 5:4 control req / ack assertion delay. the deassertion for req / ack may be moved ahead 0.5 clock cycles, or it may be delayed for up to 1.5 clock cycles. deassertion delay options depend on the status of the fastclk bit in control register three. assertion delay for req / ack can vary from 0 to 1.5 clock cycles. for programming information, refer to the register level descriptions. the following drawings illustrate the req / ack assertion/deassertion feature: amd 5-3 the fast scsi block fastclk enabled 19113a-21 req / ack synch offset reg binary value: 0123 01 23 clk fastclk disabled req/ack clk synch offset reg binary value: 01 23 0 12 3 19113a-22 note: care must be taken in programming this feature, as it is possible to violate scsi-2 timing specifications. 5.1.5 parity parity on the scsi bus is such that the total number of logical ones on the data bus including the parity bit must be odd. parity checking features are implemented via two bits in the status register and control register one. parity checking can be imple- mented on data flowing in from the scsi bus. parity is always generated internally by the AM53C974A for data moving onto the scsi bus. feature bit name bit # register parity from scsi parity error reporting 4 control reg one ((b)+20h) parity status parity error 5 status register ((b)+10h) 5.1.5.1 parity from the scsi bus the parity error reporting bit (bit 4, control register one) applies parity checking on all incoming bytes from the scsi bus. this feature is cleared to 0 by a hardware reset. when this feature is enabled, the AM53C974A will check parity on all data received from the scsi bus. any detected error will be flagged by setting bit 5 in the scsi status register, and atn will be asserted on the scsi bus. however, no interrupt will be generated. when this feature is disabled (bit 4 set to 0), no parity check is done on incoming bytes; rather, the AM53C974A generates parity internally for each byte. note that the parity on the pci bus is generated internally and is distinct from the parity received from the scsi bus. amd the fast scsi block 5-4 5.1.6 reset levels the AM53C974A has two reset pins and two reset commands that affect the scsi block. the pci^rst pin resets the whole chip including the scsi controller and the pci interface. the reset device command causes almost the same effect on the scsi controller that the pci^rst pin does. however, the reset device command has no effect on the pci interface. also, after the reset device command has been issued, the user must issue a nop command before another command can be executed. the action of the pci^rst signal or the reset device command is called hard reset. the scsi^rst pin is a bidirectional signal on the scsi bus that resets a portion of the scsi logic when it is asserted by a device on the scsi bus. similarly, the AM53C974A can assert the scsi^rst signal to cause all of the other devices on the scsi bus to reset. the reset scsi command causes the same effect on the scsi controller that the scsi^rst pin does, except that this command also causes the scsi^rst pin to be asserted so that all other (external) devices on the scsi bus are also reset. once a scsi reset command has been executed, the scsi^rst signal will remain asserted until a hard reset has occurred. the action of the scsi^rst signal and the reset scsi command is called soft reset. in addition there is a third type of reset, called disconnected reset, that is caused by certain sequences on the scsi bus. these three types of reset are described in the following sections. 5.1.6.1 hard resets: (h) this reset occurs at power up, when the pci^rst pin is asserted through external hardware, or when the reset device command is issued by writing 02h to the scsi command register at ((b)+0ch). hard reset causes all chip functions to halt and resets all internal state machines. it leaves the scsi block in the disconnected state. it leaves all scsi registers in their default states. in addition, if the hard reset is caused by the assertion of the pci^rst pin, the following actions occur. the command register in the pci configuration space is cleared to zero. (no other register in the configuration space is affected.) the dma ccb registers are set to their default values. 5.1.6.2 soft reset: (s) this reset occurs either when the scsi^rst pin on the scsi bus is asserted or when the reset scsi bus command is issued (by writing 03h to the scsi command register at ((b)+0ch). soft reset causes the following actions to occur: all scsi bus signals except scsi^rst are released. the chip is returned to the disconnected state. an interrupt is generated if bit 6 in control register one is enabled. amd 5-5 the fast scsi block 5.1.6.3 disconnected reset: (d) this reset is caused by various commands or situations which cause the AM53C974A to disconnect from the scsi bus. disconnected reset occurs when any of the following conditions occur: target disconnect, disconnect steps, and terminate steps the AM53C974A is the initiator and the scsi bus moves to a bus free state. the selection or reselection command terminates due to selection timeout. disconnected reset causes the following actions to occur: all scsi signals except scsi^rst are deasserted. the scsi command register is initialized to empty. the is1 and is0 bits in the internal state register, ((b)+18h), are cleared to 0. resets bit 6:4 in the command register. the table below describes chip operations and features which are affected by the various reset levels. chip operation/feature reset level deassert all scsi signals except scsirst * * scsirst cleared by hard reset only hsd reset bits 6:4 in the command register hsd command register fifo initialized to empty hsd reset internal state bits in registers (b)+18h and (b)+1ch hs clear internal state register bits: enable select (is2 = 0) hs target (is 0 = 0) hsd initiator (is 1:0 = 00) hsd reset command sequence module hs reset dma interface hs reset bus-initiated selection/reselection module hs clear scsi status register (b)+10h h clear interrupt status register (b)+14h h release int pin h deassert scsirst signal h synchronous offset register = 0 h synchronous transfer period register = 5 h initialize scsi fifo to empty condition h clear all control registers h set clock conversion factor = 2 h h = hard reset s = soft reset d = disconnected reset amd the fast scsi block 5-6 5.2 register description the AM53C974A scsi registers are mapped to a double word address space as shown in the table below. however, the actual register data occupies only the least significant byte of the address. the register addresses are represented by the pci configuration base address (b) and its corresponding offset value. the base address for the AM53C974A is stored at register address (10h) in the pci configuration space. register acronym address (hex.) register description type ctcreg (b)+00 current transfer count register low read stcreg (b)+00 start transfer count register low write ctcreg (b)+04 current transfer count register middle read stcreg (b)+04 start transfer count register middle write ffreg (b)+08 scsi fifo register read/write cmdreg (b)+0c scsi command register read/write statreg (b)+10 scsi status register read sdidreg (b)+10 scsi destination id register write instreg (b)+14 interrupt status register read stimreg (b)+14 scsi timeout register write isreg (b)+18 internal state register read stpreg (b)+18 synchronous transfer period register write cfireg (b)+1c current fifo/internal state register read sofreg1 (b)+1c synchronous offset register write cntlreg1 (b)+20 control register one read/write clkfreg (b)+24 clock factor register write res (b)+28 reserved write cntlreg2 (b)+2c control register two read/write cntlreg3 (b)+30 control register three read/write cntlreg4 (b)+34 control register four read/write ctcreg (b)+38 current transfer count register high/part-unique id code read stcreg (b)+38 start current transfer count register high write res (b)+3c reserved write amd 5-7 the fast scsi block 5.2.1 register bit map: read register address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 xfer cntr xfer cnt xfer cnt xfer cnt xfer cnt xfer cnt xfer cnt xfer cnt xfer cnt (b)+00h (07) (06) (05) (04) (03) (02) (01) (00) xfer cntr xfer cnt xfer cnt xfer cnt xfer cnt xfer cnt xfer cnt xfer cnt xfer cnt (b)+04h (15) (14) (13) (12) (11) (10) (09) (08) xfer cntr xfer cnt xfer cnt xfer cnt xfer cnt xfer cnt xfer cnt xfer cnt xfer cnt (b)+38h (23) (22) (21) (20) (19) (18) (17) (16) fifo fif0 fifo fifo fifo fifo fifo fifo fifo (b)+08h (07) (06) (05) (04) (03) (02) (01) (00) command dma cmd cmd cmd cmd cmd cmd cmd (b)+0ch (06) (05) (04) (03) (02) (01) (00) status int illegal parity ctz gcv phase phase phase (b)+10h op error msg c/d i/o interrupt scsi invalid disc svc success resel sel sel (b)+14h rst cmd req op w/atn internal state res res res res synch internal internal internal (b)+18h offset flag state state state current fifo/ internal internal internal current current current current current int state state state state fifo fifo fifo fifo fifo (b)+1ch control 1 xtend disable res par error res id id id (b)+20h timing int report (02) (01) (00) clk factor res res res res res clk clk clk (b)+24h factor factor factor reserved res res res res res res res res (b)+28h control 2 res enable res res scsi-2 res res res (b)+2ch features features control 3 addl qtag group2 fast fast res res res (b)+30h id chk en cmd scsi clock control 4 glitch glitch power res res active res res (b)+34h eater eater down neg reserved res res res res res res res res (b)+3ch amd the fast scsi block 5-8 5.2.2 register bit map: write register address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 xfer cntr xfer cnt xfer cnt xfer cnt xfer cnt xfer cnt xfer cnt xfer cnt xfer cnt (b)+00h (07) (06) (05) (04) (03) (02) (01) (00) xfer cntr xfer cnt xfer cnt xfer cnt xfer cnt xfer cnt xfer cnt xfer cnt xfer cnt (b)+04h (15) (14) (13) (12) (11) (10) (09) (08) xfer cntr xfer cnt xfer cnt xfer cnt xfer cnt xfer cnt xfer cnt xfer cnt xfer cnt (b)+38h (23) (22) (21) (20) (19) (18) (17) (16) fifo fif0 fifo fifo fifo fifo fifo fifo fifo (b)+08h (07) (06) (05) (04) (03) (02) (01) (00) command dma cmd cmd cmd cmd cmd cmd cmd (b)+0ch (06) (05) (04) (03) (02) (01) (00) destination id res res res res res dest dest dest (b)+10h id id id time out time time time time time time time time (b)+14h (07) (06) (05) (04) (03) (02) (01) (00) synch xfer pd res res res synch synch synch synch synch (b)+18h period period period period period synch offset req / ack req / ack req / ack req / ack synch synch synch synch (b)+1ch deassert deassert assert assert offset offset offset offset control 1 xtend disable res par error res id id id (b)+20h timing int report (02) (01) (00) clk factor res res res res res clk clk clk (b)+24h factor factor factor reserved res res res res res res res res (b)+28h control 2 res enable res res res res res res (b)+2ch features control 3 addl res res fast fast res res res (b)+30h id chk scsi clock control 4 glitch glitch power res active active res res (b)+34h eater eater down neg neg reserved res res res res res res res res (b)+3ch amd 5-9 the fast scsi block 5.2.3 register descriptions the values shown below each bit reflect register reset values. the register shall default to these values following a power-up or chip reset. bit level descriptions are valid for the lsb at each address location. remaining bytes at each address location are reserved. 5.2.3.1 current transfer count register (ctcreg) address [(b)+00h, (b)+04h, (b)+38h] read only address (b)+38h 76543210 crvl23 crvl22 crvl21 crvl20 crlv19 crvl18 crvl17 crvl16 xxxxxxxx address (b)+04h 76543210 crvl15 crvl14 crvl13 crvl12 crlv11 crvl10 crvl9 crvl8 xxxxxxxx address (b)+00h 76543210 crvl7 crvl6 crvl5 crvl4 crlv3 crvl2 crvl1 crvl0 xxxxxxxx bit 23:0 C crvl 23:0 C current value this is a three-byte register which decrements to keep track of the number of bytes transferred during a dma transfer. reading these registers returns the current value of the counter. the counter will decrement by one for every byte and by two for every word transferred. the transaction is complete when the count reaches zero, and bit 4 of the scsi status register ((b)+10h) is set. should the sequence terminate early, the sum of the values in the current fifo ((b)+1ch) and the current transfer count register reflect the number of bytes remaining. the least significant byte is located at address ((b)+00h), the middle byte is located at address ((b)+04h), and the most significant byte is located at address ((b)+38h). register ((b)+38h) extends the total width of the register from 16 to 24 bits, and is only enabled when the enable features bit (bit 6) of control register two is set to a value of 1. these registers are automatically loaded with the values in the start transfer count register every time a dma command is issued. however, following a chip or power on reset, up until the time register ((b)+38h) is loaded, the AM53C974As part-unique id can be obtained by reading register ((b)+38h). the value in the current transfer count register will be decremented as follows: asynch data in: active edge of ack synch data in: active edge of dack data out: active edge of dack amd the fast scsi block 5-10 5.2.3.2 start transfer count register (stcreg) address [(b)+00h, (b)+04h, (b)+38h] write address (b)+38h 76543210 stvl23 stvl22 stvl21 stvl20 stvl19 stvl18 stvl17 stvl16 xxxxxxxx address (b)+04h 76543210 stvl15 stvl14 stvl13 stvl12 stvl11 stvl10 stvl9 stvl8 xxxxxxxx address (b)+00h 76543210 stvl7 stvl6 stvl5 stvl4 stvl3 stvl2 stvl1 stvl0 xxxxxxxx bit 23:0 C stvl 23:0 C start value this is a three-byte register which contains the number of bytes to be transferred during a dma operation. the value in the start transfer count register must be programmed prior to command execution. the value programmed in this register should be the same as the value programmed in the dma starting transfer counter ((b)+44h). the least significant byte is located at address ((b)+00h), the middle byte is located at address ((b)+04h), and the most significant byte is located at address ((b)+38h). register ((b)+38h) extends the total width of the register from 16 to 24 bits, and is only enabled when the enable features bit (bit 6) of control register two is set to a value of 1. this sets the maximum transfer count to 16 mbytes. when a value of 0 is written to these registers, the transfer count will be set to the maximum. these registers retain their value until overwritten, and are therefore unaffected by a hardware or software reset. this reduces programming redundancy since it is no longer necessary to reprogram the count for subsequent dma transfers of the same size. 5.2.3.3 scsi fifo register (ffreg) address (b)+08h read/write 76543210 ff7 ff6 ff5 ff4 ff3 ff2 ff1 ff0 00000000 bit 7:0 C ff 7:0 C fifo the fifo on the AM53C974A is 16 bytes deep and is used to transfer scsi data to and from the AM53C974A. the fifo may be accessed via a read or write to this register. this is the only register that can be accessed with req or ack . this register is reset to zero by hardware or software reset or if the clear fifo command is issued. amd 5-11 the fast scsi block 5.2.3.4 scsi command register (cmdreg) address (b)+0ch read/write 76543210 dma cmd6 cmd5 cmd4 cmd3 cmd2 cmd1 cmd0 xxxxxxxx commands to the AM53C974A are issued by writing to this register which is two bytes deep. commands may be queued, and will be read from the bottom of the queue. at the completion of the bottom command, the top command, if present, will drop to the bottom of the register to begin execution. all commands are executed within six clock cycles of dropping to the bottom of the scsi command register, with the exception of the reset scsi bus, reset device, and dma stop commands. these commands are not queued and are executed within four clock cycles of being loaded into the top this register. interrupts are generated upon completion of some commands. should back-to-back commands generate interrupts, and the first interrupt has not been serviced, the interrupt from the second (top) command will be stacked behind the first. the scsi status register ((b)+10h), interrupt register ((b)+14h), and internal state register ((b)+18h) will be updated to reflect the second interrupt after the microprocessor services the first interrupt. reading this register will return the command currently being executed (or the last command executed if there are no pending commands). when this register is cleared, existing commands will be terminated and any queued commands will be ignored. however, clearing this register does not reset the bits to 00h. under the following conditions, the scsi command register will be cleared and maintained in a reset state (00h) until the host services the interrupt status register ((b)+18h). illegal command scsi bus reset or disconnect completion of bus-initiated selection or reselection select command reselect command (if atn is asserted) target disconnect or terminate command selection or reselection timeout bad parity received in target mode atn asserted in target mode receiving a message while in target mode and atn is deasserted before completion not in message in phase for the second byte of the initiator command complete steps unexpected phase change during an information transfer or transfer pad bytes command bit 7 C dma C direct memory access when set, this bit notifies the device that the command is a dma instruction, when reset it is a non-dma instruction. amd the fast scsi block 5-12 for dma instructions the current transfer count register (ctcreg) will be loaded with the contents of the start transfer count register (stcreg). the data is then transferred and the ctcreg is decremented for each byte until it reaches zero. data is transferred between system memory and the scsi bus via the bus-mastering dma engine. non-dma instructions do not modify the transfer count registers ((b)+00h, (b)+04h, and (b)+38h), since the number of bytes transferred is a function of the operation rather than the transfer count. these type of instructions move data between the scsi fifo and the scsi bus, and requires host processor intervention to handle data transmission between the scsi fifo and memory. bits 6:0 C cmd 6:0 C command 6:0 these command bits decode the commands that the device needs to perform. there are a total of 31 commands grouped into four categories. the groups are initiator commands, target commands, selection/reselection commands and general purpose commands. see section 5.3 for descriptions of these commands. 5.2.3.5 scsi status register (statreg) address (b)+10h read only 76543210 int ioe pe ctz gcv msg c/d i/o 0000xxxx this read-only register contains flags which indicate the status of the chip and the current phase of the scsi bus. these bits are read in conjunction with the interrupt status register ((b)+14h) to determine the reason for the interrupt. this register should always be read prior to servicing the interrupt status register (instreg) since bits 7:3 will be reset to 0 once the interrupt status register is read. if command stacking is used, the phase bits may be latched by setting the enf bit (control register two, bit 6). with this feature enabled, the scsi bus phase of the last complete command (preced- ing the interrupt) will be latched by bits 2:0. bits 7:3 are reset to 0 during a hardware reset. bit 7 C int C interrupt the int bit is set when the scsi block detects an interrupt condition. this bit will be cleared by a hardware or software reset. reading the interrupt status register ((b)+14h) will deassert the interrupt output and also clear this bit. note: scsi interrupt conditions will also be flagged in the dma status register ((b)+54h, bit 4). bit 6 C ioe C illegal operation error the ioe bit is set when an illegal operation is attempted. this condition will not cause an interrupt, and will therefore be detected by reading the status register ((b)+10h) while servicing another interrupt. the following conditions will cause the ioe bit to be set: dma and scsi transfer directions are opposite. fifo overflows or data is overwritten. in initiator mode and unexpected phase change detected during synchronous data transfer. amd 5-13 the fast scsi block command register overwritten. this bit is cleared by reading the interrupt status register ((b)+14h) or by a hard or soft reset. bit 5 C pe C parity error the pe bit is set if any of the parity checking options are enabled and the device detects a parity error on bytes sent or received on the scsi bus. parity options are controlled by bit 4 in control register one ((b)+20h), and by bit 2 in control register two ((b)+2ch). detection of a parity error condition will not cause an interrupt but will be reported with other interrupt causing conditions. this bit will be cleared by reading the interrupt status register ((b)+14h) or by a hard or soft reset. bit 4 C ctz C count to zero the ctz bit is set when the current transfer count register ((b)+00h, (b)+04h, (b)+38h) has decremented to zero. this bit is reset when the current transfer count register is re-loaded. reading the interrupt status register ((b)+14h) will not affect this bit. this bit will however be cleared by a hard or soft reset. note: a non-dma nop will not reset the ctz bit since it does not load the current transfer count register. however, a dma nop will reset this bit since it loads the cur- rent transfer count register. bit 3 C gcv C group code valid the gcv bit is set if the group code field in the command descriptor block (cdb) is one that is defined by the ansi committee in their document x3.131 C 1986. if the scsi-2 features enable (s2fe) bit in the control register 2 ((b)+2ch) is set, group 2 com- mands will be treated as 10-byte commands and the gcv bit will be set. if s2fe is reset then group 2 commands will be treated as reserved commands. group 3 and 4 commands will always be considered reserved commands. the device will treat all reserved commands as 6-byte commands. group 6 commands will always be treated as vendor unique 6-byte commands and group 7 commands will always be treated as vendor unique 10-byte commands. the gcv bit is cleared by reading the interrupt status register (instreg at (b)+14h) or by a hard or soft reset. bit 2 C msg C message bit 1 C c/d C command/data bit 0 C i/o C input/output the msg, c/d and i/o bits together are referred to as the scsi phase bits. they indicate the phase of the scsi bus. these bits may be latched or unlatched depending on whether or not the enf bit in control register two is set. in the latched mode the scsi phase bits are latched at the end of a command and the latch is opened when the interrupt status register ((b)+14h) is read. in the unlatched mode, they indicate the real-time phase of the scsi bus. amd the fast scsi block 5-14 bit 2 bit 1 bit 0 msg c/d i/o scsi phase 1 1 1 message in 1 1 0 message out 1 0 1 reserved 1 0 0 reserved 0 1 1 status 0 1 0 command 0 0 1 data in 0 0 0 data out 5.2.3.6 scsi destination id register (sdidreg) address (b)+10h write 76543210 reserved reserved reserved reserved reserved did2 did1 did0 00000xxx bit 7:3 C reserved bit 2:0 C did 2:0 C destination id the did 2:0 bits are the encoded scsi id of the device on the scsi bus which needs to be selected or reselected. at power-up the state of these bits is undefined. the did 2:0 bits are not affected by reset. did2 did1 did0 scsi id 11 1 7 11 0 6 10 1 5 10 0 4 01 1 3 01 0 2 00 1 1 00 0 0 5.2.3.7 interrupt status register (instreg) address (b)+14h read only 76543210 srst icmd dis sr so resel sela sel 000000xx the interrupt status register (instreg) indicates the reason for the interrupt. this register is used with the scsi status register ((b)+10h) and internal state register ((b)+18h) to determine the reason for the interrupt. reading the interrupt status register will clear all three registers. therefore the scsi status register ((b)+10h) and internal state register ((b)+18h) should be examined prior to reading this register. this register should only be read when an interrupt is pending. all bits will be cleared to 0 by a hardware reset. amd 5-15 the fast scsi block bit 7 C srst C scsi reset the srst bit will be set if a scsi reset is detected and scsi reset reporting is enabled via the disr (bit 6) of control register one ((b)+20h). bit 6 C icmd C invalid command the icmd bit will be set if the device detects an illegal command code. this bit is also set if a command code is detected from a mode that is different from the mode the device is currently in. once set, an invalid command interrupt will be generated. bit 5 C dis C disconnected the dis bit can be set in the target or the initiator mode when the device disconnects from the scsi bus. in the target mode this bit will be set if a terminate or a command complete steps causes the device to disconnect from the scsi bus. in the initiator mode this bit will be set if the target disconnects; while in idle mode, this bit will be set if a selection or reselection timeout occurs. bit 4 C sr C service request the sr bit can be set in the target or the initiator mode when another device on the scsi bus has a service request. in the target mode, this bit will be set when the initiator asserts the atn signal. in the initiator mode, this bit is set when a command steps successfully completed command is issued. bit 3 C so C successful operation the so bit can be set in the target or the initiator mode when an operation has successfully completed. in the target mode this bit will be set when any target or idle state command is completed. in the initiator mode this bit is set after a target has been successfully selected, after a command has successfully completed and after an information transfer command when the target requests a message in phase. bit 2 C resel C reselected the resel bit is set at the end of the reselection phase indicating that the device has been reselected as an initiator. bit 1 C sela C selected with attention the sela bit is set at the end of the selection phase indicating that the device has been selected as a target by the initiator and that the atn signal was active during selection. bit 0 C sel C selected the sel bit is set at the end of the selection phase indicating that the device has been selected as a target by the initiator and that the atn signal was inactive during selection. 5.2.3.8 scsi timeout register (stimreg) address (b)+14h write 76543210 stim7 stim6 stim5 stim4 stim3 stim2 stim1 stim0 xxxxxxxx this register determines how long the initiator will wait for a response to a selection before timing out. it should be set to yield 250 ms to comply with ansi standards for amd the fast scsi block 5-16 scsi. the maximum time out period may be calculated using the following formulas. a hardware reset will clear this register. bit 7:0 C stim 7:0 C scsi timer the value loaded in stim 7:0 can be calculated as shown below: stim 7:0 = [(scsi time out) (clock frequency) / (8192 (clock factor))] example: scsi time out (in seconds): 250 ms. (recommended by the ansi standard) = 250 x 10 C3 s. clock frequency: 40 mhz. (assume) = 40 x 10 6 hz. clock factor: 8 (see clock factor register) stim 7:0 = (250 x 10C3) x (40 x 106) / (8192 (8)) = 152.59 decimal the decimal value of 152.59 must be rounded up to 153 (the next integer value), and its hexadecimal value of 99h should be written to this register. 5.2.3.9 internal state register (isreg) address (b)+18h read only 76543210 reserved reserved reserved reserved sof is2 is1 is0 xxxx0 000 the lower four bits of this register track the progress of a sequence-type command. it is updated after each successful completion of an intermediate operation. if an error occurs, the host can read this register to determine the point where the command failed and take the necessary procedure for recovery. reading the interrupt status register ((b)+14h) while an interrupt is pending will clear this register. a hard or soft reset will also clear this register. bit 7:4 C reserved bit 3 C sof C synchronous offset flag the sof is reset when the synchronous offset register ((b)+1ch) has reached its maximum value of 15. note: the sof bit is active low. bit 2:0 C is 2:0 C internal state the is 2:0 bits along with the interrupt status register ((b)+14h) indicate the completion status of certain device commands. certain commands cause the contents of the 3-bit internal state register to be changed at several steps in the execution process. the value left in this register when the command terminates along with the contents of the interrupt status register indicate how far the execution had proceeded prior to the command termination. the following status decode tables show how to interpret the internal state register after these commands have terminated. amd 5-17 the fast scsi block status decode: initiator select without atn steps internal state interrupt status register ((b)+18h) register ((b)+14h) explanation bits 2:0 (hex) bits 7:0 (hex) 0 20 arbitration steps completed. selection time-out occurred, then disconnected 4 18 selection without atn steps fully executed 3 18 sequence halted during command transfer due to premature phase change (target) 2 18 arbitration and selection completed; sequence halted because target failed to assert command phase initiator select with atn steps internal state interrupt status register ((b)+18h) register ((b)+14h) explanation bits 2:0 (hex) bits 7:0 (hex) 0 20 arbitration steps completed; selection timeCout occurred then disconnected 4 18 selection with atn steps fully executed 3 18 sequence halted during command transfer due to premature phase change; some cdb bytes may not have been sent; check fifo flags 2 18 message out completed; sent one message byte with atn true, then released atn ; sequence halted because target failed to assert command phase after message byte was sent 0 18 arbitration and selection completed; sequence halted because target did not assert message out phase; atn still driven by the AM53C974A initiator select with atn3 steps internal state interrupt status register ((b)+18h) register ((b)+14h) explanation bits 2:0 (hex) bits 7:0 (hex) 0 20 arbitration steps completed; selection time-out occurred then disconnected 4 18 selection with atn3 steps fully executed 3 18 sequence halted during command transfer due to premature phase change; some cdb bytes may not have been sent; check fifo flags 2 18 one, two, or three message bytes sent; sequence halted because target failed to assert command phase after third message byte or prematurely released message out phase; atn released only if third message byte was sent 0 18 arbitration and selection completed; sequence halted because target did not assert message out phase; atn still driven by the AM53C974A amd the fast scsi block 5-18 status decode (continued): initiator select with atn and stop steps internal state interrupt status register ((b)+18h) register ((b)+14h) explanation bits 2:0 (hex) bits 7:0 (hex) 0 20 arbitration steps completed; selection time-out occurred then disconnected 0 18 arbitration and selection completed; sequence halted because target did not assert message out phase; atn still driven by the AM53C974A 1 18 message out completed; one message byte sent; atn on target selected without atn steps internal state interrupt status register ((b)+18h) register ((b)+14h) explanation bits 2:0 (hex) bits 7:0 (hex) 2 11 selected; received entire cdb; check group code valid bit; initiator asserted atn in command phase 1 11 sequence halted in command phase due to parity error; some cdb bytes may not have been received; check fifo flags; initiator asserted atn in command phase 2 01 selected; received entire cdb; check group code valid bit 1 01 sequence halted in command phase because of parity error; some cdb bytes may not have been received; check fifo flags 0 01 selected; loaded bus id into fifo; null-byte message loaded into fifo target select with atn steps, scsi-2 bit not set internal state interrupt status register ((b)+18h) register ((b)+14h) explanation bits 2:0 (hex) bits 7:0 (hex) 2 12 selection complete; received one message byte and entire cdb; initiator asserted atn during command phase 1 12 halted in command phase; parity error and atn true 0 12 selected with atn ; stored bus id and one message byte; sequence halted because atn remained true after first message byte 2 02 selection completed; received one message byte and the entire cdb 1 02 sequence halted in command phase because of parity error; some cdb bytes not received; check group code valid bit and fifo flags 0 02 selected with atn ; stored bus id and one message byte; sequence halted because of parity error or invalid id message amd 5-19 the fast scsi block status decode (continued): target select with atn steps, scsi-2 bit set internal state interrupt status register ((b)+18h) register ((b)+14h) explanation bits 2:0 (hex) bits 7:0 (hex) 6 12 selection completed; received three message bytes and entire cdb. atn is true 5 12 halted in command phase; parity error and atn true 412 atn remained true after third message byte 2 12 selection completed; initiator deasserts atn after receipt of one message byte; entire cdb received. atn asserted during command phase 1 12 sequence halted during command phase; initiator deasserts atn after receipt of one message byte; parity error and atn true 0 12 selected with atn ; stored bus id and one message byte; sequence halted because of parity error or invalid id message; atn is true 6 02 selection completed; received three message bytes and the entire cdb 5 02 received three message bytes then halted in command phase because of parity error; some cdb bytes not received; check group code valid bit and fifo flags 4 02 parity error during second or third message byte 2 02 selection completed; initiator deasserts atn after receipt of one message byte; entire cdb received 1 02 sequence halted during command phase because of parity error; initiator deasserts atn after receipt of one message byte; some bytes of cdb not received; check fifo flags and group code valid bit 0 02 selected with atn ; stored bus id and one message byte; sequence halted because of parity error or invalid id message target receive command steps internal state interrupt status register ((b)+18h) register ((b)+14h) explanation bits 2:0 (hex) bits 7:0 (hex) 2 18 received entire cdb; initiator asserted atn 1 18 sequence halted during command transfer due to parity error; atn asserted by initiator 2 08 received entire cdb 1 08 sequence halted during command transfer due to parity error; check fifo flags amd the fast scsi block 5-20 status decode (continued): target disconnect steps internal state interrupt status register ((b)+18h) register ((b)+14h) explanation bits 2:0 (hex) bits 7:0 (hex) 2 28 disconnect steps fully executed; disconnected; bus is free 1 18 two message bytes sent; sequence halted because initiator asserted atn 0 18 one message byte sent; sequence halted because initiator asserted atn target terminate steps internal state interrupt status register ((b)+18h) register ((b)+14h) explanation bits 2:0 (hex) bits 7:0 (hex) 2 28 terminate steps fully executed; disconnected; bus is free 1 18 status and message bytes sent; sequence halted because initiator asserted atn 0 18 status byte sent; sequence halted because initiator asserted atn target command complete steps internal state interrupt status register ((b)+18h) register ((b)+14h) explanation bits 2:0 (hex) bits 7:0 (hex) 0 18 status byte sent; sequence halted because initiator set atn 2 08 command complete steps fully executed 5.2.3.10 synchronous transfer period register (stpreg) address (b)+18h write 76543210 reserved reserved reserved stp4 stp3 stp2 stp1 stp0 xx x 0 0 1 01 the synchronous transfer period register (stpreg) contains a 5-bit value indicating the number of clock cycles each byte will take to be transferred over the scsi bus in synchronous mode. the stpreg defaults to 5 clocks/byte after a hard or soft reset. bits 7:5 C reserved bits 4:0 C stp 4:0 C synchronous transfer period the stp 4:0 bits are programmed to specify the synchronous transfer period or the number of clock cycles for each byte transferred in the synchronous mode. the minimum value for stp 4:0 is 4 clocks/byte. amd 5-21 the fast scsi block the following tables list synchronous transfer period options for both fast and normal scsi modes. table entries follow the binary code, and may be extrapolated if neces- sary. the synchronous transfer requirements as defined by the ansi specification are listed for each instance. setup hold assert/negate normal synchronous 55 ns 100 ns 90 ns fast synchronous 25 ns 35 ns 30 ns fastscsi enabled fastclk enabled, 40 mhz clock frequency: data hold: 2 cycles assert: 2 cycles stp4-0 clocks per data setup negate transfer rate (hex) cycle (cycles) (cycles) (mbytes/sec) 4 4 2 2 10.0 55 338.0 66 446.6 77 555.7 88 665.0 99 774.4 a 10 8 8 4.0 b 11 9 9 3.6 c 12 10 10 3.3 d 13 11 11 3.0 fastscsi disabled fastclk enabled, 40 mhz clock frequency: data hold: 5 cycles assert: 4 cycles stp4-0 clocks per data setup negate transfer rate (hex) cycle (cycles) (cycles) (mbytes/sec) 78 345.0 89 454.4 9 10 5 6 4.0 a 11 6 7 3.6 b 12 7 8 3.3 c 13 8 9 3.0 d 14 9 10 2.8 e 15 10 11 2.6 f 16 11 12 2.5 10 17 12 13 2.3 11 18 13 14 2.2 12 19 14 15 2.1 13 20 15 16 2.0 amd the fast scsi block 5-22 fastscsi disabled fastclk disabled, 25 mhz clock frequency: data hold: 3 cycles assert: 2.5 cycles stp4-0 clocks per data setup negate transfer rate (hex) cycle (cycles) (cycles) (mbytes/sec) 5 5 2 2.5 5.0 6 6 3 3.5 4.2 7 7 4 4.5 3.6 8 8 5 5.5 3.1 9 9 6 6.5 2.8 a 10 7 7.5 2.5 b 11 8 8.5 2.3 c 12 9 9.5 2.1 d 13 10 10.5 1.9 5.2.3.11 current fifo/internal state register (cfisreg) address (b)+1ch read only 76543210 is2 is1 is0 cf4 cf3 cf2 cf1 cf0 00000000 this register has two fields, the current fifo field and the internal state field. bits 7:5 C is 2:0 C internal state the internal state register (isreg) tracks the progress of a sequence-type command. these bits is 2:0 are duplicated from the is 2:0 field in the internal state register ((b)+18h). bits 4:0 C cf 4:0 C current fifo the cf 4:0 bits are the binary coded value of the number of bytes in the scsi fifo. these bits should not be read when the device is transferring data since this count may not be stable. the maximum value read from this register is 10h or 16 decimal due to the size of the scsi fifo. when the AM53C974A is the initiator and the phase changes to synchronous data in from either message out or command phase, cf4:0 will latch the number of message or command bytes that were not transmitted to the scsi bus. this value will be held until the next command begins. all bytes in the scsi fifo will be flushed, and only incoming data bytes will be retained. amd 5-23 the fast scsi block 5.2.3.12 synchronous offset register (sofreg) address (b)+1ch write 76543210 rad1 rad0 raa1 raa0 so3 so2 so1 so0 00000000 the synchronous offset register (sofreg) controls req / ack deassertion/assertion delay and stores a 4-bit count of the number of bytes that can be sent to (or received from) the scsi bus during synchronous transfers without a req (or ack ). bytes exceeding the threshold will be sent one byte at a time (asynchronously). that is, each byte will require an req / ack handshake. to set up an asynchronous transfer, the sofreg is set to zero. the sofreg is set to zero after a hard or soft reset. bits 7:6 C rad 1:0 C req/ack deassertion these bits may be programmed to control the deassertion delay of the req and ack signals during synchronous transfers. deassertion delay is expressed in input clock cycles, and depends on the implementation of fastclk. (see control register three, bit 3) deassertion delay sofreg fastclk req / ack bits 7:6 ctrl 3, bit 3 input clock cycles 00 0 default C 0 cycles 01 0 1/2 cycle early 10 0 1 cycle delay 11 0 1/2 cycle delay 00 1 default C 0 cycles 01 1 1/2 cycle delay 10 1 1 cycle delay 11 1 1 1/2 cycles delay bits 5:4 C raa 1:0 C req/ack assertion these bits may be programmed to control the assertion delay of the req and ack signals during synchronous transfers. unlike deassertion delay, assertion delay is independent of the fastclk setting. assertion delay sofreg req / ack bits 5:4 input clock cycles 00 default C 0 cycles 01 1/2 cycle delay 10 1 cycle delay 11 1 1/2 cycles delay note: exercise caution when programming bits 7:4 in the synchronous offset register as it is possible to violate the scsi-2 timing specifications. bits 3:0 C so 3:0 C synchronous offset 3:0 the so 3:0 bits are the binary coded value of the number of bytes that can be sent to (or received from) the scsi bus without an ack (or req ) signal. a zero value desig- nates asynchronous transfers, while a non-zero value designates the byte offset for synchronous transfers. the AM53C974A supports a maximum synchronous offset of 15 bytes. amd the fast scsi block 5-24 5.2.3.13 control register one (cntlreg1) address (b)+20h read/write 76543210 etm disr reserved pere reserved sid2 sid1 sid0 00000xxx the control register one (cntlreg1) programs the operating parameters for the AM53C974A. bit 7 C etm C extended timing mode enabling this feature will increase the minimum setup time for data being transmitted on the scsi bus. this bit should only be set if the external cabling conditions produce scsi timing violations. fastclk operation is unaffected by this feature. bit 6 C disr C disable interrupt on scsi reset the disr bit masks the reporting of the scsi reset. when the disr bit is set and a scsi reset is asserted, the device will disconnect from the scsi bus and remain idle without interrupting the host processor. when the disr bit is reset and a scsi reset is asserted the device will respond by interrupting the host processor. the disr bit is reset to zero by a hard or soft reset. bit 5 C reserved this bit is reserved and must always be programmed to 0. bit 4 C pere C parity error reporting enable the pere bit enables the checking and reporting of parity errors on incoming scsi bytes during the information transfer phase. when the pere bit set and bad parity is detected, the pe bit in the scsi status register will be set but an interrupt will not be generated. in the initiator mode the atn signal will also be asserted on the scsi bus. when the pere bit is reset and bad parity occurs, the error is not detected and no action is taken. bit 3 C reserved this bit is reserved and must always be programmed to 0. bit 2:0 C sid 2:0 C scsi id 2:0 the chip id 2:0 bits specify the binary coded value of the device id on the scsi bus. the device will arbitrate with this id and will respond to reselection with this id. at power-up the state of these bits are undefined. these bits are not affected by hard or soft reset. amd 5-25 the fast scsi block 5.2.3.14 clock factor register (clkfreg) address (b)+24h write 76543210 reserved reserved reserved reserved reserved clkf2 clkf1 clkf0 00000010 the clock factor register (clkfreg) must be set to indicate the input frequency range of the device. this value is crucial for controlling various timings to meet the scsi specification. the value of bits clkf 2:0 can be calculated by rounding off the quotient of (input clock frequency in mhz)/(5 mhz). the device has a frequency range of 10 to 40 mhz. bits 7:3 C reserved these bits are reserved and must always be programmed to 0. bits 2:0 C clkf 2:0 C clock factor 2:0 the clkf 2:0 bits specify the binary coded value of the clock factor. the clkf 2:0 bits will default to a value of 2 by a hard or soft reset. these bits encode the decimal value to be used in calculating the scsi timeout register value. clkf2 clkf1 clkf0 input clk freq (mhz) 01 010 0 1 1 10.01 to 15 1 0 0 15.01 to 20 1 0 1 20.01 to 25 1 1 0 25.01 to 30 1 1 1 30.01 to 35 0 0 0 35.01 to 40 note: clkf2:0 must be set to 000 (binary) and a 40 mhz clock must be used to gen- erate the clk signal in order to achieve 10 mb/sec synchronous transfer rates. for this case, a value of 8 should be used to calculate the scsi timeout register value. see the scsi timeout register. 5.2.3.15 reserved address (b)+28h write 76543210 reserved reserved reserved reserved reserved reserved reserved reserved 00000000 bits 7:0 C reserved these bits are reserved and must always be programmed to 00h. amd the fast scsi block 5-26 5.2.3.16 control register two (cntlreg2) address (b)+2ch read/write 76543210 reserved enf reserved reserved scsi-2 reserved reserved reserved 00000000 control register two (cntlreg2) programs various operating parameters for the AM53C974A. bit 7 C reserved this bit is reserved and must always be programmed to 0. bit 6 C enf C enable features when set to a value of 1, this bit activates the following product enhancements: 1) the current transfer count register high ((b)+38h) will be enabled, extending the transfer counter from 16 to 24 bits to allow for larger transfers. 2) following a chip or power on reset, up until the point where the current transfer count register high ((b)+38h) is loaded with a value, reading this register will return the AM53C974As part-unique id. 3) the scsi phase will be latched at the completion of each command by bits 2:0 in the scsi status register ((b)+10h). when this bit is 0, the scsi status register will re- flect real-time scsi phases. a software or hardware reset will clear this bit to its default value of 0; a scsi reset will leave this bit unaffected. bit 5:4 C reserved (read only) this bit is reserved and will always return a value of 0 when read. bit 3 C s2fe C scsiC2 features enable the s2fe bit allows the device to recognize two scsi-2 features: the extended message feature and the group 2 command recognition. (these features can also be controlled independently by bits 6:5 in cntlreg3). extended message feature: when the s2fe bit is set and the device is selected with attention, the device will monitor the atn signal at the end of the first message byte. if the atn signal is active, the device will request two more message bytes before switching to the command phase. if the atn signal is inactive the device will switch to the command phase. when the s2fe bit is reset as a target the device will request a single message byte. group 2 command recognition: when the s2fe bit is set, group 2 commands are recognized as 10-byte commands. when the s2fe bit is reset, the device will interpret group 2 commands as reserved commands. thus the AM53C974A will only request 6-byte commands when the s2fe bit is reset. bit 2:0 C reserved these bits are reserved and must always be programmed to 0. amd 5-27 the fast scsi block 5.2.3.17 control register three (cntlreg3) address (b)+30h read/write 76543210 adidchk qtag g2cb fastscsi fastclk reserved reserved reserved 00000000 bit 7 C adidchk C additional id check this bit enables additional check on id message during bus-initiated select with atn . the AM53C974A will check bits 7, and bits 5:3 in the first byte of the id message during selection. an interrupt will be generated if bit 7 is 0, or if bits 5, 4, or 3 are 1. bit 6 C qtag C qtag control this bit controls the queue tag feature in the AM53C974A. when enabled, the AM53C974A is capable of receiving 3-byte messages during bus-initiated select/ reselect with atn. the 3-byte message consists of one byte identify message and two bytes of queue tag message. the AM53C974A will check the second byte for values of 20h, 21h, and 22h. if this condition is not satisfied, the sequence halts and the AM53C974A generates an interrupt. when the qtag feature is not enabled, the AM53C974A halts the selected with atn sequence following the receipt of one id message byte if atn is still true. bit 3, control register two also enables this feature. bit 5 C g2cb C group 2 command block when this bit is set, the AM53C974A is capable of recognizing 10-byte group 2 commands as valid cdbs (command descriptor blocks). (this feature is also con- trolled by bit 3 of cntlreg2). when this feature is enabled, the target receives 10 bytes of group 2 commands, and sets the group code valid bit (bit 3) in the status register (statreg). when this feature is disabled, the target receives only 6 bytes of command code, and does not set bit 3 in the status register ((b)+10h). this bit may be programmed in conjunction with bit 6 (described above) to send 1 or 3 byte messages with 6 or 10 byte cdbs. the following table illustrates the transmission options: cntlreg3 cntlreg3 cntlreg2 bit 6 bit 5 bit 3 enabled features qtag g2cb s2fe x x 1 10-byte cdb, 3-byte message 1 0 0 3-byte message 0 1 0 10-byte cdb 1 1 0 10-byte cdb, 3-byte message 0 0 0 features disabled x is dont care amd the fast scsi block 5-28 bit 4 C fastscsi C fast scsi bit 3 C fastclk C fast scsi clocking these bits configure the AM53C974As state machine to support both fast scsi timings and scsi-1 timings. these bits affect the scsi transfer rate, and must be considered in conjunction with the AM53C974As clock frequency and mode of operation. fastscsi fastclk clock bit 4 bit 3 frequency mode of operation 1 1 25 mhz C 40 mhz 10 mbytes/sec, fast scsi 0 1 25 mhz C 40 mhz 5 mbytes/sec, scsi-1 CC 0 <=25 mhz 5 mbytes/sec, scsi-1 CC = dont care cntlreg3 bit 2 C reserved this bit is reserved and must always be programmed to 0. bit 1 C reserved (read only) this bit is reserved and will always return a value of 0 when read. bit 0 C reserved this bit is reserved and must always be programmed to 0. 5.2.3.18 control register four (cntlreg4) address (b)+34h read/write 76543210 ge1 ge0 pwd reserved res (r) rade reserved reserved 00000000 rae (w) this register is used to control several features implemented in the scsi block. at power up, this register will contain a 0 value on all bits except bit 4. bit 7:6 C ge1:0 C glitch eater the glitch eater circuitry has been implemented on req and ack lines and are controlled by bits 7and 6. the valid signal window may be adjusted by setting the bits according to the combinations listed below. bit 7 bit 6 valid signal ge1 ge0 window 0 0 12 ns 1 0 25 ns 0 1 35 ns 1 1 0 ns cntlreg4 note: changes in the valid signal window will affect data setup and hold times for fast scsi timings. amd 5-29 the fast scsi block bit 5 C pwd C reduced power feature setting this bit to 1 enables amds reduced power feature. this feature turns off the input buffers on all the scsi bus signal lines to reduce power consumption. for further power savings, the clock input may be removed using bit 21 in the sbac register ((b)+ 70h). bit 4 C reserved this bit is reserved for internal use. bit 3 (read only) C res C reserved this bit is reserved for internal use. bit 3 (write only) C rae C active negation control bit 2 C rade C active negation control bits 2 and 3 control the active negation drivers which may be enabled on req , ack , or data lines. the following table shows the programming options for this feature: bit 3 bit 2 rae rade function selected 0 0 active negation disabled 1 0 active negation on req and ack only 1 active negation on req , ack and data = dont care cntlreg4 bit 1:0 C reserved this bit is reserved for internal use. 5.2.3.19 reserved address (b)+3ch write 76543210 reserved reserved reserved reserved reserved reserved reserved reserved 00000000 bit 7:0 C reserved these bits are reserved and must always be programmed to 00h. 5.2.3.20 part-unique id register (ctcreg) address (b)+38h read only this register extends the transfer counter from 16 to 24 bits and is only enabled when the enf bit is set (bit 6, control register two). the descriptions accompanying the start transfer count registers and the current transfer count registers should be refer- enced for more information regarding the transfer counter. this register is also used to store the part-unique id code for the AM53C974A. this information may be accessed when all of the following are true: a power up or chip reset has taken place a value has not been loaded into this register the id value in this register is 12h. amd the fast scsi block 5-30 5.3 device commands the device commands can be broadly divided into two categories, dma commands and non-dma commands. dma commands are those which cause data movement between the host memory and the scsi bus while non-dma commands are those that cause data movement between the scsi fifo and the scsi bus. the most significant bit of the command byte differentiate the dma from the non-dma commands. when a dma command is issued, the contents of the start transfer count register will be loaded into the current transfer count register. data transmission will continue until the current transfer count register decrements to zero. before a dma device command is issued, the software must initialize the dma starting transfer count and starting physical address registers. then it must issue a dma start command. once this is done, it can issue the device command. non-dma commands do not modify the current transfer count register and are unaffected by the value in the current transfer count register. for non-dma com- mands, the number of bytes transmitted depends solely on the operation in progress. some of the non-dma commands are output commands that transfer data from the scsi fifo to the scsi bus. before these commands are executed, the scsi fifo must be loaded with the bytes to be sent. other non-dma commands are input commands that transfer data from the scsi bus to the scsi fifo. after these commands are executed, the data received can be accessed by reading one byte at a time from the scsi fifo. amd 5-31 the fast scsi block initiator commands information transfer 10 90 initiator command complete steps 11 91 message accepted 12 C transfer pad bytes 18 98 set atn *1aC reset atn *1bC target commands send message 20 a0 send status 21 a1 send data 22 a2 disconnect steps 23 a3 terminate steps 24 a4 target command complete steps 25 a5 disconnect 27 C receive message steps 28 a8 receive commands 29 a9 receive data 2a aa receive command steps 2b ab dma stop 04 C access fifo C 85 idle state commands reselect steps 40 c0 select without atn steps 41 c1 select with atn steps 42 c2 select with atn and stop steps 43 c3 enable selection/reselection* 44 c4 disable selection/reselection 45 C select with atn3 steps 46 c6 reselect with atn3 steps 47 c7 general commands no operation* 00 80 clear fifo* 01 81 reset device* 02 82 reset scsi bus** 03 83 * these commands do not generate interrupt. ** an interrupt is generated when scsi bus reset interrupt reporting is not disabled (see control register1/disr bit 6). non- dma mode dma mode code (hex.) command amd the fast scsi block 5-32 5.3.1 command stacking the microprocessor may stack commands in the command register ((b)+0ch) since it functions as a two-byte deep fifo. non-dma commands may not be stacked, and commands which transfer data in opposing directions should not be stacked together. if dma commands are queued together, the start transfer count must be written before the associated command is loaded into the command register. since multiple interrupts can occur when commands are stacked, it is recommended that the enf bit in control register two (bit 6) be set in order to latch the scsi phase bits in the scsi status register ((b)+10h) at the completion of a command. this allows the host to determine the phase of the interrupting command without having to consider phase changes that occurred after the stacked command began execution. note: command stacking and queuing should only be used during scsi data in or data out transfers. 5.3.2 invalid commands when an illegal command is written to the AM53C974A, the invalid command bit (bit 6, register (b)+14h) will be set to 1, and an interrupt will be generated to the host. when this happens, the interrupt must be serviced before another command may be written to the command register. an invalid command is defined as a command written to the AM53C974A that is either not supported, not allowed in the specified mode, or a command that has an unsup- ported command mode. the following conditions will also cause an invalid command interrupt to occur: an initiator information transfer, transfer pad, or command complete is issued when ack is still asserted. a selection or reselection command is issued with the dma bit enabled, if the selection/reselection command was previously issued with the dma enabled. 5.3.3 command window the window at the point where the disable selection/reselection command (45h/c5h) has been loaded into the command register ((b)+0ch), and before bus-initiated selection or reselection begins, has been eliminated. this prevents a false successful operation interrupt from being generated when the selection/reselection sequence continues to completion after the disable command has been loaded. 5.3.4 initiator commands initiator commands are executed by the device when it is in the initiator mode. if the device is not in the initiator mode and an initiator command is received the device will ignore the command, generate an invalid command interrupt and clear the command register. should the target disconnect from the scsi bus by deasserting the bsy signal line while the AM53C974A (initiator) is waiting for the target to assert req , a disconnected interrupt will be issued 1.5 to 3.5 clock cycles following bsy going false. upon receipt of the last byte during message in phase, ack will remain asserted to prevent the target from issuing any additional bytes, while the initiator decides to accept/reject the message. if non-dma commands are used, the last byte signals the scsi fifo is empty. if dma commands are used, the current transfer count signals the last byte. amd 5-33 the fast scsi block a reset scsi bus command (03h/83h) will force the AM53C974A to abort the current operation and disconnect from the bus. if the disr bit is reset (bit 6, control register one (b)+20h)), the host processor will be interrupted with a scsi reset interrupt before the AM53C974A proceeds to disconnect. if parity checking is enabled in the initiator mode during the data-in phase and an error is detected, atn will be asserted for the erroneous byte before deasserting ack . 5.3.4.1 information transfer command (command code 10h/90h) the information transfer command is used to transfer information bytes over the scsi bus. this command may be issued during any scsi information transfer phase. synchronous data transmission requires use of the dma mode. the device will continue to transfer information until it is terminated by any one of the following conditions: the target changes the scsi bus phase before the expected number of bytes are transferred. the AM53C974A clears the command register (cmdreg), and gener- ates a service request interrupt when the target asserts req . transfer has successfully completed. if the phase is message out, the AM53C974A deasserts atn before asserting ack for the last byte of the message. when the tar- get asserts req , a service request interrupt is generated. in the message in phase when the device receives the last byte. the AM53C974A keeps the ack signal asserted and generates a successful operation interrupt. during synchronous data transfers the target may send up to the maximum synchro- nous threshold number of req pulses to the initiator. if it is the synchronous data-in phase then the target sends the data and the req pulses. these bytes are stored by the initiator in the fifo as they are received. the information transfer command, when issued during the following scsi phases and terminated in synchronous data phases, is handled as described below: message in/status phase C when a phase change to synchronous data-in or syn- chronous data-out is detected by the device, the command register is cleared and the dma interface is disabled to prevent any transfer of data (phase) bytes. if the phase change is to synchronous data-in and bad parity is detected on the data bytes coming in, it is not reported since the status register will report the status of the command just completed. the parity error flag and the atn signal will be as- serted when the next information transfer command begins execution. message out/command phase C when a phase change to synchronous data-in or synchronous data-out is detected by the device, the command register is cleared and the dma interface is disabled to prevent any transfer of data (phase) bytes. if the phase change is to synchronous data-in and bad parity is detected on the data bytes coming in, it is not reported since the status register will report the status of the command just completed. the parity error flag and the atn signal will be as- serted when the next information transfer command begins execution. the scsi fifo register will be latched and will remain in that condition until the next command begins execution. the value in the scsi fifo register indicates the num- ber of non-data bytes in the scsi fifo when the phase changed to synchronous data-in. these bytes are cleared from the fifo, and only incoming data bytes are retained. amd the fast scsi block 5-34 in the synchronous data-out phase, the threshold counter is incremented as req pulses are received. the transfer is completed when the fifo is empty and the cur- rent transfer count register is 0. the threshold counter will not be 0. in the synchronous data-in phase, the current transfer count register is decre- mented as bytes are read from the scsi fifo rather than when the bytes are being written to the scsi fifo. the transfer is completed when current transfer count register is 0. however, the scsi fifo may not be empty. 5.3.4.2 initiator command complete steps (command code 11h/91h) the initiator command complete steps command is normally issued when the scsi bus is in the status in phase. one status byte followed by one message byte is transferred if this command completes normally. after receiving the message byte the device will keep the ack signal asserted to allow the initiator to examine the message and assert the atn signal if it is unacceptable. the command terminates early if the target does not switch to the message in phase or if the target disconnects from the scsi bus. this command does not utilize the internal state register ((b)+18h). 5.3.4.3 message accepted command (command code 12h) the message accepted command is used to release the ack signal. this command is normally used to complete a message in handshake. upon execution of this command the device generates a service request interrupt after req is asserted by the target. after the device has received the last byte of message, it keeps the ack signal as- serted. this allows the device to either accept or reject the message. to accept the message, message accepted command is issued. to reject the message the atn signal must be asserted (with the help of the set atn command) before issuing the message accepted command. in either case, the message accepted command has to be issued to release the ack signal. 5.3.4.4 transfer pad bytes command (command code 18h/98h) the transfer pad bytes command is used to recover from an error condition. this command is similar to the information transfer command, only the information bytes consists of null data. it is used when the target expects more data bytes than the initiator has to send. it is also used when the initiator receives more information than expected from the target. when sending data to the scsi bus, the scsi fifo is loaded with null bytes which are sent out to the scsi bus. although an actual dma request is not made, dma interface must be enabled when pad bytes are transmitted since the AM53C974A uses the current transfer count register to terminate transmission. this command terminates under the same conditions as the information transfer command, but the device does not keep the ack signal asserted during the last byte of the message in phase. should this command terminate prematurely due to a discon- nect or a phase change before the current transfer count register decrements to zero, the scsi fifo may contain residual pad bytes. amd 5-35 the fast scsi block 5.3.4.5 set atn command (command code 1ah) the set atn command is used to drive the atn signal active on the scsi bus. an interrupt is not generated at the end of this command. the atn signal is deasserted before asserting the ack signal during the last byte of the message out phase. note: the atn signal is asserted by the device without this command in the following cases: if any select with atn command is issued and the arbitration is won. an initiator needs the targets attention to send a message. the atn signal is asserted before deasserting the ack signal. 5.3.4.6 reset atn command (command code 1bh) the reset atn command is used to deassert the atn signal on the scsi bus. an interrupt is not generated at the end of this command. this command is used only when interfacing with devices that do not support the common command set (ccs). these older devices do not deassert their atn signal automatically on the last byte of the message out phase. this device does deassert its atn signal automatically on the last byte of the message out phase. 5.3.5 target commands target commands are executed by the device when it is in the target mode. if the device is not in the target mode and a target command is received the device will ignore the command, generate an invalid command interrupt and clear the command register (cmdreg). a scsi bus reset during any target command will cause the device to abort the command sequence, flag a scsi bus reset interrupt (if the interrupt is enabled) and disconnect from the scsi bus. normal or successful completion of a target command will cause a successful operation interrupt to be generated. if the atn signal is asserted during a target command sequence, the service request bit is asserted in the interrupt status register (instreg). if the atn signal is asserted when the device is in an idle state, a service request interrupt will be generated, the successful operation bit in the interrupt status register (instreg) will be reset, and the command register (cmdreg) cleared. during a command sequence, the AM53C974A decodes bits 7C5 of the 1st byte received during the command phase to determine the group code and cdb length. the following table shows group codes and their corresponding block lengths. amd the fast scsi block 5-36 group code bits 7C5 cdb length command group status 000 6 valid 001 10 valid 010 6 reserved (scsi-2 mode or g2cb disabled) 010 10 reserved (scsi-2 mode or g2cb enabled) 011 6 reserved 100 6 reserved 101 12 valid 110 6 valid 111 10 valid 5.3.5.1 send message command (command code 20h/a0h) the send message command is used by the target to inform the initiator to receive a message. the scsi bus phase lines are set to the message in phase and message bytes are transferred from the scsi fifo to the scsi bus. 5.3.5.2 send status command (command code 21h/a1h) the send status command is used by the target to inform the initiator to receive status information. the scsi bus phase lines are set to the status phase and status bytes are transferred from the scsi fifo to the scsi bus. 5.3.5.3 send data command (command code 22h/a2h) the send data command is used by the target to inform the initiator to receive data bytes. the scsi bus phase lines are set to the data-in phase and data bytes are transferred from the scsi fifo to the scsi bus. 5.3.5.4 disconnect steps command (command code 23h/a3h) the disconnect steps command is used by the target to disconnect from the scsi bus. this command is executed in two steps. in the message in phase, the target sends two bytes of the save data pointers commands. following transmission, the target disconnects from the scsi bus. successful operation and disconnected bits are set in the interrupt status register (instreg) upon command completion. if atn signal is asserted by the initiator then successful operation and service request bits are set in the instreg, the command register (cmdreg) is cleared and disconnect steps command terminates without disconnecting. 5.3.5.5 terminate steps command (command code 24h/a4h) the terminate steps command is used by the target to disconnect from the scsi bus. this command is executed in three steps. while in status phase, the target first sends a 1 byte status message. following the status phase the target moves to the message in phase and sends another 1 byte message. lastly, the target disconnects from the scsi bus. the disconnected bit is set in the interrupt status register (instreg) upon command completion. if atn signal is asserted by the initiator, then the successful operation and service request bits are set in the instreg, an interrupt is generated and the command register (cmdreg) is cleared and terminate steps command terminates without disconnecting. amd 5-37 the fast scsi block 5.3.5.6 target command complete steps command (command code 25h/a5h) the target command complete steps command is used by the target to inform the initiator of a linked command completion. this command consists of two steps. in the first step, the target sends one status byte to the initiator in the status phase. the target then sends one message byte to the initiator in the message in phase. the successful operation bit is set in the interrupt status register (instreg) upon command completion. if atn signal is asserted by the initiator, then the successful operation and service request bits are set in the instreg, the command register (cmdreg) is cleared and target command complete steps command terminates prematurely. 5.3.5.7 disconnect command (command code 27h) the disconnect command is used by the target to disconnect from the scsi bus. all scsi bus signals except scsirst are released and the device returns to the discon- nected state. the scsirst signal is driven active for about 25 ms (depending on clock frequency and clock factor). interrupt is not generated to the microprocessor. 5.3.5.8 receive message steps command (command code 28h/a8h) the receive message steps command is used by the target to request message bytes from the initiator. the target receives the message bytes from the initiator while the scsi bus is in the message out phase. the successful operation bit is set in the interrupt status register (instreg) upon command completion. if atn is asserted by the initiator, the successful operation and service request bits are set in the instreg, and the command register (cmdreg) is cleared. but if a parity error is detected, the AM53C974A ignores the received message bytes until the atn signal is deasserted. then the successful operation bit is set in the instreg, and the cmdreg is cleared. 5.3.5.9 receive commands command (command code 29h/a9h) the receive commands command is used by the target to request command bytes from the initiator. the target receives the command bytes from the initiator while the scsi bus is in the command phase. the successful operation bit is set in the interrupt status register (instreg) upon command completion. if the atn signal is asserted by the initiator, then the successful operation and service request bits are set in the instreg, the command register (cmdreg) is cleared, and the command terminates prematurely. if a parity error is detected, the device continues to receive command bytes until the transfer is complete. however, if the abort on command data/parity error (acdpe) bit in control register two (cntlreg2) bit is set, the command is terminated immediately. the parity error (pe) bit in the status register (statreg) is set and cmdreg is cleared. 5.3.5.10 receive data command (command code 2ah/aah) the receive data command is used by the target to request data bytes from the initiator. during this command the target receives the data bytes from the initiator while the scsi bus is in the data-out phase. the successful operation bit is set in the interrupt status register (instreg) upon command completion. if atn signal is asserted by the initiator then successful operation and service request bits are set in the instreg, the command register (cmdreg) is cleared and the command terminates prematurely. if a parity error is detected, the device continues to receive data bytes until the transfer is complete (abort on command/data parity error (acdpe) bit in control register two (cntlreg2) is reset). if the acdpe bit is set, the command is terminated immediately. the parity error (pe) bit in the status register (statreg) is set and cmdreg is cleared. amd the fast scsi block 5-38 5.3.5.11 receive command steps command (command code 2bh/abh) the receive command steps command is used by the target to request command information bytes from the initiator. during this command the target receives the command information bytes from the initiator while the scsi bus is in the command phase. the target device determines the command block length from the first byte. if an unknown length is received, the start transfer count register (stcreg) is loaded with five and the group code valid (gcv) bit in the status register (statreg) is reset. if a valid length is received, the stcreg is loaded with the appropriate value and the gcv bit in the statreg is set. if atn signal is asserted by the initiator then the service request bit is set in the interrupt status register (instreg), and the command register (cmdreg) is cleared. if a parity error is detected, the command is terminated prematurely and the cmdreg is cleared. 5.3.5.12 dma stop command (command code 04h) the dma stop command is used by the target to allow the microprocessor to terminate a target data transfer due to a lack of activity on the dma channel. this command is executed from the top of the command queue. if there is a queued command waiting execution, it will be overwritten and the illegal operation error (ioe) bit in the status register (statreg) will be set. this command is cleared from the command queue once it is decoded. caution must be exercised when using this command since the removal of dreq by this command may confuse the system dma controller. verify this condition before proceeding further. the dma stop command may be executed when all of the following conditions are satisfied: dma target send data command or dma target receive data command is in exe- cution. in both cases the dma controller and the AM53C974A must be in a steady state. during a dma target send data command: the fifo is empty or the current fifo (cf 4:0) bits in the current fifo/internal state register (cfisreg) are zero. during a dma synchronous target receive data command: the current transfer count register (ctcreg) is zero, (indicated by the count to zero (ctz) bit of the status register (statreg)), or the synchronous offset register (sofreg) has reached its maximum value (indicated by the synchronous offset flag (sof) bit of the internal state register (isreg)). during a dma asynchronous target receive data command: the fifo is full (cf 4:0 set to 1 in the current fifo/internal state register (cfisreg)), or current transfer count register (ctcreg) is zero (indicated by the count to zero (ctz) bit of the status register (statreg)). when these conditions are satisfied, the AM53C974A halts, asserts a dma request to its internal dma engine, and then waits for the dma channel. if the AM53C974A halted during synchronous transfer, the ack pulses not received from the scsi bus remain outstanding. amd 5-39 the fast scsi block upon receipt of the dma stop command, the AM53C974A resets the dma interface to its internal dma engine and then terminates the command in progress. ongoing scsi sequences are completed as follows: synch data send: completes when ctz bit in status register is 1. synch data receive: when all outstanding acks received, command completes asynchronous data send: immediately completes asynchronous data receive: immediately completes. remaining data in fifo should be removed by host. the host is interrupted only by the command that was in progress. other bits in the interrupt and status registers are left untouched, and the command register is cleared. 5.3.5.13 access fifo command (command code 85h) the host may issue the access fifo command following a target abort dma or abort due to parity error. this command will give the dma controller access to the data remaining in the scsi fifo. 5.3.6 idle state commands the idle state commands can be issued to the device only when the device is discon- nected from the scsi bus. if these commands are issued to the device when it is logically connected to the scsi bus, the commands are ignored, an invalid command interrupt is generated, and the command register (cmdreg) is cleared. 5.3.6.1 reselect steps command (command code 40h/c0h) the reselect steps command is used by the target device to reselect an initiator device. when this command is issued, the device arbitrates for the control of the scsi bus. if the device wins arbitration, it reselects the initiator device and transfers a single byte identify message. before issuing this command the scsi timeout register (stimreg), control register one (cntlreg1), and the scsi destination id register (sdidreg) must be set to the proper values. if dma is enabled, the start transfer count register (stcreg) must be set to one. if dma is not enabled, the single byte identify message must be loaded into the fifo before issuing this command. this command will be terminated early if the scsi timeout register times out. if the sequence terminates normally, a successful operation interrupt will be issued. this command also resets the internal state register (isreg). 5.3.6.2 select without atn steps command (command code 41h/c1h) the select without atn steps command is used by the initiator to select a target. when this command is issued, the device arbitrates for the control of the scsi bus. when the device wins arbitration, it selects the target device and transfers the com- mand descriptor block (cdb). before issuing this command the scsi timeout register (stimreg), control register one (cntlreg1), and the scsi destination id register (sdidreg) must be set to the proper values. if dma is enabled, the start transfer count register (stcreg) must be set to the total length of the command. if dma is not enabled, the data must be loaded into the fifo before issuing this command. this command will be terminated early if the scsi timeout register times out, if the target does not go to the command phase following the selection phase, or if the target exits the command phase prematurely. a successful operation interrupt will be generated following normal command execution. amd the fast scsi block 5-40 5.3.6.3 select with atn steps command (command code 42h/c2h) the select with atn steps command is used by the initiator to select a target. when this command is issued, the device arbitrates for the control of the scsi bus. when the device wins arbitration, it selects the target device with the atn signal asserted and transfers a 1-byte message followed by the command descriptor block (cdb). before issuing this command the scsi timeout register (stimreg), control register one (cntlreg1) and the scsi destination id register (sdidreg) must be set to the proper values. if dma is enabled, the start transfer count register (stcreg) must be set to the total length of the command and message. if dma is not enabled, the data must be loaded into the fifo before issuing this command. this command will be terminated early in the following situations: the scsi timeout register times out the target does not go to the message out phase following the selection phase the target exits the message phase early the target does not go to the command phase following the message out phase the target exits the command phase early a successful operation/service request interrupt is generated when this command is completed successfully. 5.3.6.4 select with atn and stop steps command (command code 43h/c3h) the select with atn and stop steps command is used by the initiator to send mes- sages with lengths other than 1 or 3 bytes. when this command is issued, the device executes the selection process, transfers the first message byte, then stops the sequence and interrupts the host processor. atn is not deasserted at this time, allowing the initiator to send additional message bytes after the id message. to send these additional bytes, the initiator must write the transfer counter with the number of bytes which will follow, then issue a transfer information command. (note: the target is still in the message out phase when this command is issued). atn will remain asserted until the current transfer count register decrements to zero. the scsi timeout register (stimreg), control register one (cntlreg1), and the scsi destination id register (sdidreg) must be set to the proper values before the initiator issues this command. this command will be terminated early if the stimreg times out or if the target does not go to the message out phase following the selection phase. 5.3.6.5 enable selection/reselection command (command code 44h/c4h) the enable selection/reselection command is used to respond to a bus-initiated selection or reselection. upon disconnecting from the bus the selection/reselection circuit is automatically disabled by the device. this circuit must be enabled for the AM53C974A to respond to subsequent reselection attempts and the enable selection/ reselection command is issued to do that. this command is normally issued within 250 ms (select/reselect timeout) after the device disconnects from the bus. if dma is enabled, the device loads the received data to the buffer memory. if the dma is disabled, the received data stays in the fifo. 5.3.6.6 disable selection/reselection command (command code 45h) the disable selection/reselection command is used by the target to disable response to a bus-initiated reselection. when this command is issued before a bus-initiated selection or reselection is in progress, it resets the internal state bits previously set by the enable selection/reselection command. the device also generates a successful amd 5-41 the fast scsi block operation interrupt to the processor. if however, this command is issued after a bus-initiated selection/reselection has begun, this command and all incoming com- mands are ignored since the command register (cmdreg) is held reset. the AM53C974A also generates a selected or reselected interrupt when the sequence is complete. 5.3.6.7 select with atn 3 steps command (command code 46h/c6h) the select with atn 3 steps command is used by the initiator to select a target. this command is similar to the select with atn steps command, except that it sends exactly three message bytes. when this command is issued the AM53C974A arbitrates for control of the scsi bus. when the device wins arbitration, it selects the target device with the atn signal asserted and transfers three message bytes followed by the command descriptor block (cdb). before issuing this command the scsi timeout register (stimreg), control register one (cntlreg1), and the scsi destination id register (sdidreg) must be set to the proper values. if dma is enabled, the start transfer count register (stcreg) must be set to the total length of the command. if dma is not enabled, the data must be loaded into the fifo before issuing this com- mand. this command will be terminated early in the following situations: the scsi timeout register times out the target does not go to the message out phase following the selection phase the target removes command phase early the target does not go to the command phase following the message out phase the target exits the command out phase early a successful operation/service request interrupt is generated when this command is executed successfully. 5.3.6.8 reselect with atn3 steps command (command code 47h/c7h) the queue tag feature of the select with atn3 command has been implemented in the reselection command. therefore, a target reselecting an initiator can use the qtag feature of atn3. following reselection, one message byte and 2 qtag bytes will be sent. the three message bytes must be loaded into the fifo before this command is issued if dma is not enabled. amd the fast scsi block 5-42 5.3.7 general commands 5.3.7.1 no operation command (command code 00h/80h) the no operation command administers no operation, therefore an interrupt is not generated upon completion. this command is issued following the reset device command to clear the command register (cmdreg). a no operation command in the dma mode may be used to verify the contents of the start transfer count register (stcreg). after the stcreg is loaded with the transfer count and a dma no opera- tion command is issued, reading the current transfer count register (ctcreg) returns the transfer count value. 5.3.7.2 clear fifo command (command code 01h) the clear fifo command is used to initialize the scsi fifo to the empty condition. the current fifo register (cfisreg) reflects the empty fifo status and the bottom of the fifo is set to zero. no interrupt is generated at the end of this command. 5.3.7.3 reset device command (command code 02h) the reset device command immediately stops any device operation and resets all the functions of the device. additionally, it returns the device to the disconnected state and it generates a hard reset. the reset device command remains on the top of the com- mand register fifo holding the device in the reset state until the no operation command is loaded. once loaded, the no operation command serves to re-enable the command register. 5.3.7.4 reset scsi bus command (command code 03h) the reset scsi bus command forces the scsirst signal active for a period of 25 ms, and drives the chip to the disconnected state. an interrupt is not generated upon command completion, however, if bit 6 is set to 0 in control register one (cntlreg1), a scsi reset interrupt will be issued. 6-1 dma engine dma engine 6 6.1 introduction the dma engine in the AM53C974A provides bus-mastering capabilities to allow flexibility and performance advantages over slave pci-scsi devices. built into the engine is a 96-byte (24 dw) fifo and additional logic to handle the transition between the 32 bit pci bus and the 8-bit scsi bus. figure 6-1 illustrates the dma engine in relation to the pci interface and the scsi block. as its most basic function, the dma engine acts as the dma controller in a bus master capacity on the pci bus, transferring data between memory and the scsi block. all command, data, status, and message bytes pass through the dma fifo on their way to or from the scsi bus. however, for pio accesses to the scsi registers, the dma fifo is bypassed as data moves directly from the scsi block to the pci interface. since pio operations do not pass through the funneling logic and dma fifo, data is transferred one byte at a time from the scsi block to the pci interface via the least significant byte lane. (the three most significant byte lanes will contain null data.) figure 6-1 pci biu C dma engine C scsi block 19113a-23 pci bus interface unit funnel/alignment logic scsi fifo (16x9) dreq dack scsi block dma cntl full empty data path unit pci^gnt ad(3:0) cs rd wr ad(4:0), cs wr , rd 32 16 32 data data data pci config space ad (4:0) c/ be (3:0) pci^req dma reg scsi reg dma engine 8 data dma fifo (24x32) amd dma engine 6-2 since the pci bus is 4 bytes wide and the scsi bus is only 1 byte wide, funneling logic is included in this engine to handle byte alignment and to ensure that data is properly transferred between the scsi bus and the wider pci bus. all boundary conditions are handled through hardware by the dma engine. the dma engine is also designed for block type (4 kbyte page) transfers to support scatter-gather operations. implementation of this feature is described further in section 6.8. 6.2 data path unit the data path unit receives address ad(6:0) and c/ be (3:0) inputs from the pci bus through the pci bus interface unit, and routes appropriate addresses, rd , wr , and cs control lines to either the dma engine or the scsi block, depending on the state of the ad6 address line. if ad6 is 0, then register accesses are to the scsi registers. however, if ad6 is 1, then register accesses are routed to the dma registers. 6.3 dma fifo data transfers from the scsi fifo to the dma fifo take place each time the threshold of two bytes is reached on the scsi side. the transfer is initiated by the scsi block when dreq is asserted, and continues with the dack handshaking which typically takes place in dma accesses. data is accumulated in the dma fifo until a threshold of 16 dw (64 bytes) is reached. data is then burst across the pci bus to memory. residue data which is less than the threshold in each fifo is sent in non-contiguous bursts. for memory read operations, data is sent in burst mode to the dma fifo and continues through to the scsi fifo and onto the scsi bus. 6.3.1 dma blast command this command is used to retrieve the contents of the dma fifo when the target disconnects during a dma write operation. users are cautioned against using this command for recovery during a dma read operation. if the current dma write operation is interrupted by a target disconnect ( inta asserted, and scsi transfer counter 1 0), the dma blast command may be used to retrieve any data bytes within the dma fifo. the following procedure outlines its use: 1. read the dma status register. it should indicate that a scsi interrupt is pending. 2. read the scsi fifo flags register. if the value 1 0, wait for the scsi fifo to empty its contents into the dma fifo. when the value = 0, execute the dma blast com- mand. note: in some odd byte conditions, one residual byte will be left in the scsi fifo, and the fifo flags will never count to 0. when this happens, the residual byte should be retrieved via pio following completion of the blast operation 3. the dma blast command is executed by writing 01 to bits 1:0 in the dma com- mand register. when issued, this command will move the dma fifo contents into the system memory. 4. completion of the blast operation is signaled when bit 5 in the dma status regis- ter is set to 1. 5. set the dma engine to idle when all data bytes have been moved to memory. note: an interrupt is not generated upon completion of this command. amd 6?3 dma engine 6.4 funneling logic figure 6-4 shows the internal dma logic interface with the scsi block. the dma fifo interfaces to the funnel logic block via a 32-bit data bus, and the funnel logic properly reduces this stream of data to a 16-bit stream to properly interface with the scsi fifo. figure 6-4 dma fifo to scsi fifo interface 19113a-24 96-byte dma fifo funnel logic 16-byte scsi fifo 32 16 6.5 scsi dma programming sequence the following section outlines the procedure for executing scsi dma operations: 1. program the dma engine to the idle state 2. program the scsi block registers (e.g. synchronous operation, offset values, etc.) 3. program the dma registers 4. start the dma engine 5. at the end of the dma transaction, set the dma engine back to the idle state 6.6 mdl based dma programming the following section outlines the procedure for executing mdl based dma operation: 1. set up the mdl list 2. use the programming sequence defined earlier for initiating a scsi dma transfer 6.7 dma registers the following is a description of the dma register set or the dma channel context block (dma ccb). these registers control the specifics for dma operations such as transfer length and scatter-gather options. the three read-only working counter registers allow the system software and driver to monitor the dma transaction. the register addresses are represented by the pci configuration base address (b) and its corresponding offset value. the base address for the AM53C974A is stored at register address (10h) in the pci configuration space. register acronym address (hex.) register description type cmd (b)+40 command r/w stc (b)+44 starting transfer count r/w spa (b)+48 starting physical address r/w wbc (b)+4c working byte counter r wac (b)+50 working address counter r status (b)+54 status register r smdla (b)+58 starting memory descriptor list (mdl) address r/w wmac (b)+5c working mdl counter r sbac (b)+70 scsi bus and control * *certain bits are read/write; certain bits are read only. refer to the sbac register description for more details. amd dma engine 6-4 6.7.1 command register (cmd) address (b)+40h read/write the upper 3 bytes of the command register are reserved while the remaining (lsb) byte is used to control different features of the dma engine. this register must be written twice to ensure proper operation. the first pci i/o write to this register must issue an idle command (cmd1:0 = 00) and set bits 7:4 for the dma operation. the following pci i/o write should then issue a start command (cmd1:0 = 11) to begin the dma operation. during this second register write cycle, bits 7 through 4 must be programmed as they were during the first pci i/o write cycle, and must be preserved throughout the operation. at the completion of the dma operation, the dma engine should be restored to the idle state. the power up/reset state is shown in the register map that follows. reserved reserved reserved reserved reserved reserved reserved reserved xxxxxxxx 31 30 29 28 27 26 25 24 reserved reserved reserved reserved reserved reserved reserved reserved xxxxxxxx 23 22 21 20 19 18 17 16 reserved reserved reserved reserved reserved reserved reserved reserved xxxxxxxx 15 14 13 12 11 10 9 8 dir inte_d inte_p mdl reserved diag cmd1 cmd0 00000000 76543210 bit 31:8 C reserved these bits are reserved for future implementation and should always be programmed to 0. bit 7 C dir C direction of transfer this bit, active logic 1 true, indicates a read data transfer (i.e., read from device C dma write to memory). a logic 0 false value implies a write data transfer (dma read from memory C write to device). this bit is cleared by a hard reset. bit 6 C inte_d C dma transfer interrupt enable this bit active logic 1 true, enables the channel to cause an active interrupt upon completion of a dma transfer (done condition), or receipt of an error condition during a dma transfer. this bit is cleared by a hard reset. bit 5 C reserved this bit is reserved and should be programmed to 0. amd 6-5 dma engine bit 4 C mdl C map to memory descriptor list this bit, active logic 1 true, enables the mapping of physical memory addresses into the memory descriptor list (mdl). in this mode, the spa register (bits 11:0), will contain the offset for the first of the translated mdl entries. when this bit is 0, the AM53C974A will operate in non-mdl mode, in which case the spa register will contain actual 32-bit physical memory addresses. this bit is cleared by a hard reset. bit 3 C reserved this bit is reserved for future implementation and should be programmed to 0. bit 2 C diag C diagnostic this bit is reserved for diagnostics only. it will be reset to 0 and shall remain zero. when this bit is set with the blast command, the AM53C974A will fill the memory buffer with random data and set the done bit in the dma status register, regardless of the scsi bus activities. bit 1:0 C cmd1:0 C command code bits these bits are encoded to represent commands for the dma engine. they will be cleared by a hard reset condition. command codes are described as follows: cmd1 cmd0 command description 0 0 idle the dma channel is inactive. writes of this value are considered nops if there are no dma operations in progress. issuing this command while a dma transaction is in progress will reset the dma engine to the idle state and halt the current transfer, inta will not be asserted. 0 1 blast empties all data bytes in dma fifo to memory during a dma write operation. upon completion, the bcmplt bit will be set in the dma status register. this command should not be used during a dma read operation. 1 0 abort terminates the current dma transfer. the dma engine should be restored to the idle state following execution of this command. note: this is only valid after a start command is issued. 1 1 start initiates a new dma transfer. these bits must remain set throughout the dma operation until the done bit in the dma status register is set. note: this command should be issued only after all other control bits have been initialized. x= dont care 6.7.2 starting transfer count (stc) address (b)+44h read/write the stc register contains a 24-bit read/write value which represents the number of bytes to be transferred. the value programmed in this register should be identical to the value programmed in the scsi start transfer count register ((b+00h, (b)+04h, (b)+38h). this register is not modified by the dma transfer logic, and can be read by the software at any time. the system software may modify this register only after the dma transfer has completed. for each transfer, this register must be reloaded. amd dma engine 6-6 reserved reserved reserved reserved reserved reserved reserved reserved xxxxxxxx 31 30 29 28 27 26 25 24 stc23 stc22 stc21 stc20 stc19 stc18 stc17 stc16 xxxxxxxx 23 22 21 20 19 18 17 16 stc15 stc14 stc13 stc12 stc11 stc10 stc9 stc8 xxxxxxxx 15 14 13 12 11 10 9 8 stc7 stc6 stc5 stc4 stc3 stc2 stc1 stc0 76543210 xxxxxxxx bit 31:24 C reserved these bits are reserved for future implementation and should always be programmed to 0. bit 23:0 C stc23:0 C starting transfer count this 24-bit count represents the number of bytes to be transferred during the current dma operation. these bits are cleared to an indeterminate state following a hard reset. 6.7.3 starting physical address (spa) address (b)+48h read/write the spa register is a 32-bit read/write address that is used as the starting address value for the dma transfer. this register is not modified by the dma transfer logic, and can be read by the software at any time. this register may be modified only after the dma transfer has completed. spa31 spa30 spa29 spa28 spa27 spa26 spa25 spa24 xxxxxxxx 31 30 29 28 27 26 25 24 spa23 spa22 spa21 spa20 spa19 spa18 spa17 spa16 xxxxxxxx 23 22 21 20 19 18 17 16 spa15 spa14 spa13 spa12 spa11 spa10 spa9 spa8 xxxxxxxx 15 14 13 12 11 10 9 8 spa7 spa6 spa5 spa4 spa3 spa2 spa1 spa0 76543210 xxxxxxxx amd 6-7 dma engine bit 31:0 C spa31:0 C starting physical address this value represents the starting memory address for the dma transfer. during a scatter-gather operation, bits 31:12 will be programmed through hardware with the mdl entries. therefore, bits 11:0 should be programmed with the starting page offset. 6.7.4 working byte counter (wbc) address (b)+4ch read only the wbc register contains a 24-bit read-only counter that is initialized to the value in the stc register when the transfer begins. the counter occupies the 3 lower bytes of this address, and reflects the number of bytes transferred during a dma operation. when the dma transfer stops, a non zero value in this register indicates that the operation aborted earlier than expected (i.e. an error occurred). this registers intermediate value may be read by software between dma burst transactions. reserved reserved reserved reserved reserved reserved reserved reserved xxxxxxxx 31 30 29 28 27 26 25 24 wbc23 wbc22 wbc21 wbc20 wbc19 wbc18 wbc17 wbc16 xxxxxxxx 23 22 21 20 19 18 17 16 wbc15 wbc14 wbc13 wbc12 wbc11 wbc10 wbc9 wbc8 15 14 13 12 11 10 9 8 00000000 76543210 wbc7 wbc6 wbc5 wbc4 wbc3 wbc2 wbc1 wbc0 00000000 bit 31C24 C reserved these bits are reserved for future implementation and should always be programmed to 0. bit 23:0 C wbc23:0 C working byte counter these bits are loaded with the value in the starting transfer counter (stc, register (b)+44h) when the dma transfer begins. it is decremented by 1, 2, or 4, as data is sent to the pci bus. this count will be decremented to 0 at the completion of a dma transfer (reflected by the done bit in the dma status register). this register will be set to 0 with a hard reset. 6.7.5 working address counter (wac) address (b)+50h read only the wac register is a 32-bit read-only address that increments the memory address during a dma transfer. this registers intermediate values can be read by software in between dma burst transactions. amd dma engine 6-8 wac31 wac30 wac29 wac28 wac27 wac26 wac25 wac24 11111111 31 30 29 28 27 26 25 24 wac23 wac22 wac21 wac20 wac19 wac18 wac17 wac16 11111111 23 22 21 20 19 18 17 16 wac15 wac14 wac13 wac12 wac11 wac10 wac9 wac8 11111111 15 14 13 12 11 10 9 8 wac7 wac6 wac5 wac4 wac3 wac2 wac1 wac0 11111111 76543210 bit 31:0 C wac31:0 C working address counter this register is initialized to the value in the starting physical address register (spa, register (b)+48) and is incremented to the next double word (dword) boundary when the dma transfer begins. as data is processed by the dma channel, the contents of this register will be incremented by dword addresses. when the current transfer termi- nates, this register will reflect the address for the next access. upon hard reset, this register is set to 1. 6.7.6 status register (status) address (b)+54h read only the upper 3 bytes of the status register are reserved. the state of the lower six bits report the state of the dma channel and any termination conditions. these flags are automatically set to logic 0 when a new dma transfer is started. reading this register will clear it and its associated interrupt. reserved reserved reserved reserved reserved reserved reserved reserved xxxxxxxx 31 30 29 28 27 26 25 24 reserved reserved reserved reserved reserved reserved reserved reserved xxxxxxxx 23 22 21 20 19 18 17 16 reserved reserved reserved reserved reserved reserved reserved reserved xxxxxxxx 15 14 13 12 11 10 9 8 reserved pabort bcmblt scsint done abort error pwdn 0000000x 76543210 amd 6-9 dma engine bit 31:8 C reserved these bits are reserved for future implementation. bit 7 C reserved this bit is reserved and read as zero. bit 6 C pabort C pci master/target abort this bit is used in conjunction with bit 25 in register (b)+70h to indicate that a pci master or target abort condition was detected. when bit 25 is set to 1 and a pci abort condition is detected, this bit will be set to 1. when bit 25 is reset to 0, detection of an abort condition will not be reported by this bit. pabort is read-only and is cleared when read if bit 24 (dma status write erase control) in register (b)+70h is reset to 0. if the write erase feature is set, pabort is cleared when a 1 is written to this location. bit 5 C bcmplt C blast complete this bit, when set to 1 (true) indicates that the blast command has completed, and the dma f ifo is empty. this bit is only valid when the blast command is issued for a scsi disconnect and reselect operation. bit 4 C scsiint C scsi interrupt this bit when set to 1 (true) indicates that an interrupt condition has occurred in the scsi block. this read-only bit is cleared only when the appropriate scsi registers are serviced. the scsi registers must be cleared by servicing the scsi status register, internal state register and the interrupt status register in the order mentioned above bit 3 C done C dma transfer terminated this bit, active logic 1 true, indicates that the dma transfer request has successfully completed. when this bit is set in conjunction with bit 6 (inte_d) in the dma command register ((b)+40h), and the working byte count (wbc23:0) is zero, an interrupt is generated. reading this bit will clear it and its associated interrupt. refer to the section on interrupts. bit 2 C abort C dma transfer aborted this bit, active logic 1 true, indicates that the dma transfer request was aborted for one of the following reasons: the abort command was issued pci master abort pci target abort when this register is read, this bit will be cleared. bit 1 C error C dma transfer error this bit, active logic 1 true, indicates that the dma transfer request terminated with one of the error conditions present on the pci bus. if the inte_d bit is set in the cmd register, an interrupt will be generated. reading this bit will clear it and its associated interrupt. bit 0 C pwdn C power down indicator this bit, active logic 1 true, reflects the state of the pwdn input pin. when first set, an interrupt is generated. this bit will be cleared when the pwdn pin is deasserted, amd dma engine 6-10 however, the interrupt caused when this bit is set will be cleared when this register is read. 6.7.7 starting memory descriptor list address (smdla) address (b)+58h read/write the smdla register is a 32-bit read/write address that is used as the starting address of the scatter-gather memory descriptor list. this register is not modified by the dma transfer logic, and may be read by the software at any time. the system software can modify this register after the dma transfer has been started. smdla31 smdla30 smdla29 smdla28 smdla27 smdla26 smdla25 smdla24 xxxxxxxx 31 30 29 28 27 26 25 24 smdla23 smdla22 smdla21 smdla20 smdla19 smdla18 smdla17 smdla16 xxxxxxxx 23 22 21 20 19 18 17 16 smdla15 smdla14 smdla13 smdla12 smdla11 smdla10 smdla9 smdla8 xxxxxxxx 15 14 13 12 11 10 9 8 smdla7 smdla6 smdla5 smdla4 smdla3 smdla2 smdla1 smdla0 76543210 xxxxxxxx bit 31:0 C smdla31:0 C starting memory descriptor list address these bits reflect the starting address in the memory descriptor list used for scatter- gather operations. the mdl start address must be double word aligned since the hardware ignores non-zero values written to the two low address bits. upon hard reset, this register is set to an indeterminate value. 6.7.8 working mdl address counter (wmac) address (b)+5ch read only the wmac register is a 32-bit read-only address that is initialized to the value in the smdla register when the transfer begins. its value is incremented by 4 as successive page entries in the mdl are fetched. this register will contain the address of the last mdl entry read when the transfer terminates. this registers intermediate values may be read by software between dma burst transactions. wmac31 wmac30 wmac29 wmac28 wmac27 wmac26 wmac25 wmac24 11111111 31 30 29 28 27 26 25 24 wmac23 wmac22 wmac21 wmac20 wmac19 wmac18 wmac17 wmac16 11111111 23 22 21 20 19 18 17 16 amd 6-11 dma engine wmac15 wmac14 wmac13 wmac12 wmac11 wmac10 wmac9 wmac8 11111111 15 14 13 12 11 10 9 8 wmac7 wmac6 wmac5 wmac4 wmac3 wmac2 wmac1 wmac0 11111100 76543210 bit 31:0 C wmac31:0 C working mdl address counter bits 31:2 are set to 1 following a hard reset, while bits 1:0 are set to 0. 6.7.9 scsi bus and control (sbac) address (b)+70h read only control (cntrl) address (b)+70 this is a 32-bit register which is used to control the enhancements in the AM53C974A. these enhancements inclued the write erase feature for the dma status register, the scsi powerdown and clock selection feature, and the scam support. reserved reserved reserved reserved reserved reserved pabten status 31 30 29 28 27 26 25 24 00000000 reserved reserved pwd sbsy sclk scam req ack 23 22 21 20 19 18 17 16 00000000 rst bsy sel ant msg c/d i/o sdp 15 14 13 12 11 10 9 8 00000000 sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 76543210 00000000 bit 31:26 C reserved these bits are reserved and will return undefined values when read. bit 25 C pabten C enable interrupt on pci abort this bit controls the interrupt and status bit for the pci abort condition (master or target). when this bit is set to 1 and a pci abort condition is detected, an interrupt will be generated, and bit 6 of the dma status register ((b)+54h) will be set to 1. when this bit is reset to 0 and a pci abort condition is detected, an interrupt will not be generated and bit 6 in the dma status register will be 0. amd dma engine 6-12 bit 24 C status C write erase control this bit controls the write erase feature on bits 3:1 and bit 6 of the dma status register ((b)+54h). when this bit is programmed to 1, the state of bits 3:1 are preserved when read. bits 3:1 are only cleared when a 1 is written to the corresponding bit location. for example, to clear bit 1, the value of 0000_0010b should be written to the register. when the dma status preserve bit is 0, bits 3:1 are cleared when read. bit 23:22 C reserved these bits are reserved for internal testing and must always be set to 0. bit 21 C pwd C power down scsi core this bit is used to remove the scsi clock input to the AM53C974A during power-down sequencing. when this bit is 1, the scsi clock input is disconnected from the scsi core to save power. when this bit is 0, the clock is connected for scsi operation. bit 20 C sbsy C scsi busy this is a read only bit which monitors the bus free condition on the scsi bus. when this bit is 1 , the scsi bus is in use. when this bit is 0, the scsi bus is free. this bit is used in conjunction with the pwd bit for power-down mode. bit 19 C sclk C select clock this bit is read-only and indicates whether the scsi core is connected to the pci clock, or if it is connected to an external scsi clock source. when an external scsi clock is not provided on pin 60 (scsiclk1), the AM53C974A will automatically use the pci clock pin to drive the scsi logic. under this condition, this bit will be read as 0. when an external scsi clock is present, the scsi logic will automatically be driven by the scsi clock and this bit will be read as 1. note: for fast synchronous (10 mbytes/sec) operation, the scsi core must be driven by a 40 mhz source. this requires an external scsi clock source since the pci clock operates at 33 mhz or less. bit 18 C scam C scsi configure automagically mode this bit is used to enable or disable scam mode. when this bit is set to 1, bits 17:0 may be programmed to support scam protocol. when in scam mode, bits 17:0 are read/write and directly affect the logical state of the scsi bus. for example, if scam is enabled and bit 17 (req) is set to 1, the req line on the scsi bus will go low. when bit 18 is reset to 0, bits 17:0 are read-only and represent the logical state of the scsi bus. bit 17 C req C request when the scam bit is enabled (bit 18 set to 1), this bit is read/write and logically affects the state of the req line on the scsi bus. when scam is disabled (bit 18 reset to 0), this bit is read-only and represents the logical state of the req line. bit 16 C ack C acknowledge when the scam bit is enabled (bit 18 set to 1), this bit is read/write and logically affects the state of the ack line on the scsi bus. when scam is disabled (bit 18 reset to 0), this bit is read-only and represents the logical state of the ack line. amd 6-13 dma engine bit 15 C rst C reset when the scam bit is enabled (bit 18 set to 1), this bit is read/write and logically affects the state of the rst line on the scsi bus. when scam is disabled (bit 18 reset to 0), this bit is read-only and represents the logical state of the rst line. bit 14 C bsy C busy when the scam bit is enabled (bit 18 set to 1), this bit is read/write and logically affects the state of the bsy line on the scsi bus. when scam is disabled (bit 18 reset to 0), this bit is read-only and represents the logical state of the bsy line. bit 13 C sel C select when the scam bit is enabled (bit 18 set to 1), this bit is read/write and logically affects the state of the sel line on the scsi bus. when scam is disabled (bit 18 reset to 0), this bit is read-only and represents the logical state of the sel line. bit 12 C atn C attention when the scam bit is enabled (bit 18 set to 1), this bit is read/write and logically affects the state of the atn line on the scsi bus. when scam is disabled (bit 18 reset to 0), this bit is read-only and represents the logical state of the sel line. bit 11 C msg C message when the scam bit is enabled (bit 18 set to 1), this bit is read/write and logically affects the state of the msg line on the scsi bus. when scam is disabled (bit 18 reset to 0), this bit is read-only and represents the logical state of the msg line. bit 10 C c/d C command/data when the scam bit is enabled (bit 18 set to 1), this bit is read/write and logically affects the state of the c /d line on the scsi bus. when scam is disabled (bit 18 reset to 0), this bit is read-only and represents the logical state of the c /d line. bit 9 C i/o C input/output when the scam bit is enabled (bit 18 set to 1), this bit is read/write and logically affects the state of the i /o line on the scsi bus. when scam is disabled (bit 18 reset to 0), this bit is read-only and represents the logical state of the i /o line. bit 8 C sdp C scsi data parity when the scam bit is enabled (bit 18 set to 1), this bit is read/write and logically affects the state of the sdp line on the scsi bus. when scam is disabled (bit 18 reset to 0), this bit is read-only and represents the logical state of the sdp line. bit 7:0 C sd7:0 C scsi data when the scam bit is enabled (bit 18 set to 1), these bits are read/write and logically affect the state of the sd 7:0 lines on the scsi bus. when scam is disabled (bit 18 reset to 0), this bit is read-only and represents the logical state of the sd 7:0 lines. 6.8 dma scatter-gather mechanism the AM53C974A contains a scatter-gather translation mechanism which facilitates faster data transfers. this feature uses a memory descriptor list (a list of contiguous physical memory addresses) which is stored in system memory. use of the memory descriptor list allows a single scsi transfer to be read from (or written to) non- contiguous physical memory locations. this mechanism avoids copying the transfer data and mdl list, which was previously required for conventional dma operations. amd dma engine 6-14 6.8.1 memory descriptor list (mdl) the mdl is a non-terminated (no end of file marker) list of 32-bit page frame addresses, which is always aligned on a double word boundary. the format is shown below: 31 12 11 0 page frame address ignored 6.8.2 dma scatter C gather operation (4k aligned elements) the scatter-gather mechanism described below assumes 4k page alignment and size for all mdl entries except the first and last entry. this feature is enabled by setting the mdl bit in the dma command register (bit 4, address (b)+40h). 1. a) prepare the memory descriptor list (mdl) through software and store it in system memory. b) load the address of the starting entry in the memory descriptor list (mdl) into the start memory descriptor list address (smdla) register. c) program the starting transfer count (stc) register with the total transfer length (i.e., # of bytes). also program the starting physical address (spa) register (bits 11:0) with the starting offset of the first entry. d) when the start dma command is written to the dma command register, the value in the smdla register is loaded into the working mdl address counter (wmac) register which points to the appropriate entry in the mdl list as shown below. note: the value in the smdla register is double word aligned. therefore, read/write transactions will always begin on a double word boundary. smdla wmac page frame address #1 page frame address #2 page frame address #3 page frame address #4 page frame address #n ignored ignored ignored ignored ignored 31 0 31 0 31 0 12 19113a-25 in this example, the contents of the wmac register is pointing to page frame address #1. when the first entry in the mdl is read, the wmac register is incremented to point to the next page entry (page frame address #2). 2. the AM53C974A reads only the page frame address (bits 31:12) from the mdl entry and combines it with the first page offset value in the starting physical address (spa) register (bits 11:0). this 32-bit value is loaded into the working address counter (wac) register and becomes the physical address for page#1, as shown below. amd 6-15 dma engine starting offset xxxxx page frame address #1 starting offset spa wac 31 12 0 31 12 0 programmed by the software 4k page#1 data from the mdl 19113a-26 when the wac register (bits 11:0) reaches the end of the first page, the AM53C974A reads the next mdl entry, and increments the wmac register. 3. the chip reads the page frame address (bits 31:12) from the second entry of the mdl and combines it with the wac register (bits 11:0). this becomes the physical address for page#2. the wac register (bits 11:0) are 000h since it now points to the beginning of page# 2 as shown below. page frame address #2 0 wac 31 12 0 4k page#2 data from the mdl 19113a-27 again when wac (bits 11:0) reaches the maximum page length count, the AM53C974A resets it to 000h and increments the wmac register to the next mdl entry. the operation continues in this way until wmac register reaches the last mdl entry (page frame address #n in this example). 4. the wac register points to the beginning of the last page#n and the dma operation continues until the byte count is exhausted in the working byte counter (wbc) register. when wbc=0, the chip stops incrementing the wac register. this is shown below. amd dma engine 6-16 0 12 31 0 12 31 spa wac 4k page #n page frame address #n page frame address #n starting offset starting offset from the mdl set by the chip stc = 0 19113a-28 also, at wbc=0 the chip stops incrementing the wmac register. when a new dma operation is initialized, the new first page offset value in the spa register (bits 11:0) is loaded into the wac register and dma operation is performed following the above steps. amd 6-17 dma engine 6.8.3 dma scatter C gather operation (non-4k aligned elements mdl not set) there is another way to implement a scatter-gather operation which does not force the data elements to be aligned on 4k boundaries. it assumes a traditional scatter-gather list of the following format: element 0 physical address byte count element 1 physical address byte count ... element n physical address byte count this second implementation is described as follows: 1. set the scsi start transfer count register ((b)+00h, (b)+04h, (b)+38h) to the byte count of the first scatter-gather element. 2. program the dma starting transfer count register ((b)+44h) to the byte count of the first scatter-gather element. 3. program the dma starting physical address register ((b)+48h) to the physical address of the first scatter-gather element. 4. start the scsi operation by issuing a scsi information transfer command. 5. start the dma engine with dma transfer interrupt enable (bit 6, (b)+40h). 6. when the scatter-gather elements byte count is exhausted, the dma engine will generate an interrupt. 7. reprogram the next scatter-gather elements byte count into the scsi start transfer count register and the dma starting transfer count register. 8. reprogram the dma starting physical address register ((b)+48h) to the physical address of the next scatter-gather element. 9. repeat steps 4C8 until the scatter-gather list is completed. 6.9 interrupts interrupts may come from two sources: the dma engine or the scsi block. upon receipt of an interrupt ( inta asserted), the dma status register should be serviced first to identify the interrupt source(s). dma engine related interrupts are cleared when the related flags are read in the dma status register. if the interrupt source is from the scsi block, the scsi status, internal state, and interrupt status registers should be read to obtain information about the scsi interrupt. scsi interrupts will only be cleared when the interrupt status register is read. the source of the dma interrupt will be flagged by the appropriate bit in the dma status register. the reasons for interrupt are: successful completion of a dma transfer request. (bit 6 in the dma command reg- ister ((b)+40h) must be set to enable this interrupt) an address error occurred on the pci bus during a dma transfer (bit 6 in the dma command register ((b)+40h) must be set to enable this interrupt) the pwdn pin is first asserted amd dma engine 6-18 an interrupt from the scsi block will automatically set bit 4 (scsiint) in the dma status register (address (b)+54h). the scsi block will generate an interrupt under the following conditions: scsi reset occurred illegal command code issued the target disconnects from the scsi bus scsi bus service request successful completion of a command the AM53C974A has been reselected in addition, under certain conditions, an interrupt will be generated upon receipt of a pci parity error. the following matrix explains the conditions which cause a pci parity error interrupt. pci parity error detection is controlled by the following items: a) bit 6, pci command register at address 04h b) bit 6, dma command register at address (b)+40h c) the state of the perr pin pci parity errors are reported in three locations: a) bit 15 and bit 8, pci status register at address 06h b) bit 1, dma status register at address (b)+54h c) interrupt asserted pci status reg dma status reg interrupt (06h) (b)+54h generated? pci cmd reg (04h) bit 6 = 1 bit 15 = 1 bit 1 = 1 no and bit 8 = 1 dma cmd reg (b)=40h bit 6 = 0 and perr asserted pci cmd reg (04h) bit 6 = 1 bit 15 = 1 bit 1 = 1 yes and bit 8 = 1 dma cmd reg (b)=40h bit 6 = 1 and perr asserted method of parity error reporting (these bits will be set) conditions of parity error detection (when all conditions are true) please note that the parity error detection and reporting scheme described above is true only during dma operations, when pc scsi is a master. expansion rom support 7-1 expansion rom support 7 7.1 introduction this chapter describes the rom support feature of the AM53C974A. the boot rom for the AM53C974A can be implemented using a standard prom or eprom and one external latch. this chapter shows a sample boot rom implementation as well as a typical rom access cycle for clarity. in addition, the expansion rom mapping as defined by the pci specfication, rev 2.0 is also described briefly. 7.2 rom base address register the AM53C974A supports expansion roms of up to 64 kbytes, with speed as slow as 250 ns, if the boot pin (pin 100) is tied high. this is done through use of the expansion rom base address register located at address 30h in the pci configuration space and built-in logic to simplify the rom interface. the base address register is 4 bytes wide and defines the base address and size of the expansion rom. figure 7-1 shows the base address register implemented on the AM53C974A. in this figure, only bits 31:16 and bit 0 are programmable while bits 15:11 are hardwired to 0. as a result, the AM53C974A specifies support for roms aligned to 64 kbyte boundaries. refer to the expansion rom base address register for the bit-level discription. figure 7-1 expansion rom base address register 31 16 15 11 10 1 0 programmed by host as base address 00000 reserved address decode enable 19113a-29 7.3 sample implementation figure 7-2 shows a sample implementation of an AM53C974A to boot rom interface. in figure 7-2, the implementation uses an am27c512 - 150 pc eprom and a 74ls273 positive edge-triggered octal dff to latch the high address byte. note that the roms ce signal is tied to its oe signal to save power consumed by the rom when it is not being accessed (t ce to data valid is 150 ns). however, this solution will cause the roms access time to be slightly extended. another method is to connect the roms ce to ground to minimize the access time (t ce to data valid is 50 ns). this is done at the expense of power consumed since the rom is always enabled. amd expansion rom support 7-2 figure 7-2 example of AM53C974A to rom interface ba7 ba6 ba5 ba4 ba3 ba2 ba1 ba0 lck oe bd7 bd6 bd5 bd4 bd3 bd2 bd1 bd0 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 oe ce d7 d6 d5 d4 d3 d2 d1 d0 v cc 74ls273 d1 d2 d3 d4 d5 d6 d7 d8 clk clr q1 q2 q3 q4 q5 q6 q7 q8 4.7 k w AM53C974A am27c512 - 150 pc 19113a-30 7.4 rom access cycle pci slave memory reads at the rom addresses initiate the AM53C974A read sequence to the expansion rom. figure 7-3 shows the rom access timing when the pci slave memory read cycle is initiated to the rom. in this figure, it is assumed that the roms oe is connected to its ce . note that the entire cycle requires 54 pci clocks from the time frame is sampled asserted to the time trdy is sampled asserted. note that if frame is kept asserted by the host after the AM53C974A asserts trdy , the AM53C974A will assert stop . this is shown by the dashed lines. amd expansion rom support 7-3 figure 7-3 pci slave memory read and rom access cycle 19113a-3 1 clk devsel frame c/ be ad 31:1 irdy trdy stop ce lck oe data bd 7:0 ba 7:0 high address low address low address low address low address 1st read 2nd read 3rd read 4th read 1st byte 2nd byte 3rd byte 4th byte 2 clk 9 clk 9 clk 9 clk 9 clk 1 pci clock figure 7-4 shows an expanded view of the lck signal relative to the valid high address byte on ba7:0. note that the time from the high address valid to the negative edge of lck is approximately 2 pci clocks and the time from the positive edge of lck to the high address invalid is approximately 1 pci clock. assuming a pci clock of 33 mhz (30 ns period), the recommended worst case setup and hold times for negative and positive edge triggered latches are as follows: latch type setup time hold time negative edge triggered 55 ns 55 ns positive edge triggered 85 ns 25 ns for example, a negative edge triggered latch with 50 ns setup and hold times will work with the AM53C974A. amd expansion rom support 7-4 figure 7-4 expanded picture of lck relative to high address valid high address valid 2 pci clks 1 pci clk 1 pci clk 19113a-32 7.5 expansion rom mapping the boot rom attached to the AM53C974A allows the host to access the rom code at power-up. this rom code can be accessed using the standard pci memory read instruction. during these reads, the AM53C974A will insert wait states by keeping trdy deasserted until the data is ready from the rom. this will compensate for the difference in access time due to the slower rom. figure 7-5 shows an example of the mapping of the pci expansion rom on the AM53C974A. in this figure, the first 19h bytes of the expansion rom area is defined as the rom header. offset 1ah to 30h is the pci data structure. the rom code starts at offset 31h. the expansion rom area starts at offset 00h to its maximum memory location. users may follow the mapping shown in figure 7-4 or they may allocate the pci data structure or rom code in some other offset address. however, the rom header offset must start at offset 00h. amd expansion rom support 7-5 figure 7-5 AM53C974A expansion rom mapping reserved 0 1 . .. 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 32 . . . 55 aa 00 1a rom signature reserved pointer to data structure AM53C974A signature vendor id device id pointer to data length revision class code image length revision level code/data code type indicator rom header pci data structure rom code 19113a-33 amd expansion rom support 7-6 8-1 scam tutorial scam tutorial 8 8.1 introduction the AM53C974A is designed to support level 1 scam as defined in the x3t9.2/93-109r5 (sept 30, 1993) specifications. as this specification is not yet finalized, users should treat the material in this chapter only as a tutorial and should refer to the original scam specification for a more detailed description of the scam protocol. also note that this tutorial assumes familiarity with the scsi protocol. scam stands for scsi configured automagically. it is a proposed protocol to assign ids to scsi devices after power-on or after a scsi bus reset. various types of devices (scam master devices, scam slave devices, scam tolerant devices, and scam intolerant devices) can be connected to a scam capable scsi bus. this chapter provides a quick tutorial of the scam protocol. 8.2 requirements in order to implement the scam protocol, the AM53C974A must: (1) perform scam selection (2) have a hard id (3) recognize scsi bus reset conditions (4) use selection time-out (5) shall not assert scsi rst upon a selection time-out other requirements: (1) the AM53C974A will be the only master on the scsi bus (2) all slaves will power-up concurrently or before the master (3) the AM53C974A must work with scam tolerant devices, scam devices with default ids, and scam intolerant devices 8.3 scam terminology scam devices any scsi device that implements the scam protocol. scam master devices any scam device that controls the assignments of soft ids. scam slave devices any scam device that receives soft id assignments through the scam protocol. if the slave device is on a scam capable bus it uses a soft id. if it is on a non-scam bus it uses its default id. note that for level 1 slave devices, once a slave device has received its soft id or has its default id assigned, it will act like a scam tolerant device. amd scam tutorial 8-2 scam tolerant devices any non-scam device that satisfies certain requirements on responding to scam selection, allowing scam tolerant devices to be freely intermixed with scam devices. scam intolerant devices any non-scam device that does not respond to scam selection. 8.4 normal scsi and scam selections level 1 scam selection sequence is different from normal non-scam or scsi selection sequence. the following describes normal scsi selection and level 1 scam selection. 8.4.1 normal scsi selection figure 8-1 shows the normal scsi arbitration and selection timing diagram. in fig- ure 8-1, any scsi device may assert bsy with its own id on the data bus when there is a bus free phase. after a minimum of 2.4 m s arbitration delay, all participating devices will examine the bus to determine if they have won ownership (the winner is the device with the highest id). at this point, all losers must release all scsi bus signals within a bus clear delay of 800 ns. only the winning device will then assert sel and the target id with whom it wants to communicate along with other signals during this selection phase. two de-skew delays after other signals such as atn or i/o have been asserted, the selecting device will release bsy. one selection time-out period (400 ns min) later, the selected target will assert bsy . two de-skew delays later, the selecting device will release sel , completing the selection process. figure 8-1 normal scsi arbitration and selection sequence arbitrate and win ---- put id on bus. wait minimum of 2.4 m s. assert sel if id is highest. arbitrate and lose -- put id on bus. any time before 2.4 m s, if id not the highest or external sel is on, then terminate by releasing all scsi signals. 2.4 m s 250 ms 90 ns 800 ns 1200 ns 90 ns bsy sel data atn i/o 19113a-34 winners id 8.4.2 level 1 scam selection figure 8-2 shows the timing sequence of scam devices in the scam selection process. the scam power-on to scam selection time (1 s) is the maximum time a scam device may wait after power-on before enabling its response to selection. the scam reset to amd 8-3 scam tutorial scam selection time (250 ms) is the minimum time a scam device may wait after a reset condition has occurred before initiating the scam protocol. once the scam device is ready to respond to scam selection, it may respond with a long or short selection time. when slow response is anticipated, a scam device will maintain a long scam selection time (minimum 250 ms). when rapid response is anticipated, a scam device will maintain a short scam selection time (minimum 1 ms). the scam default id selection response time (4 ms) is the minimum time in which a scam slave device may respond to selection of its unconfirmed default id. this is also the maximum selection time-out delay a scam master will use when examining the bus for scam tolerant devices. figure 8-2 timing diagram showing the scam device selection sequence time max power-on to scam selection time (1 s) min long scam sel response time (250 ms) min default id selection time (4 ms) min reset to sel time (250 ms) min short sel response time (1 ms) 19113a-35 figure 8-3 shows the timing sequence of scam tolerant devices in a scam selection process. the scam tolerant power-on to scam selection time (5 s) is the maximum time a scam tolerant device may wait after power-on before enabling its response to selection. the scam tolerant reset to scam selection time (250 ms) is the maximum time a scam tolerant device may wait after a reset condition has occurred before enabling its response to selection. the scam tolerant selection response time (1 ms) is the maximum time in which a scam tolerant device may respond to selection of its id. this is also the minimum selection time-out delay a scam master can use when examining the bus for scam tolerant devices. amd scam tutorial 8-4 figure 8-3 timing diagram showing the scam tolerant devices 19113a-36 time max power-on to selection time (5 s) max tolerant sel response time (1 s) min reset to sel time (250 ms) figure 8-4 shows the level 1 scam selection timing diagram to demonstrate the relation of the parameters specified in figure 8-2 and 8-3. the maximum power-on to scam selection time of 1 s (scam devices) or 5 s (scam tolerant devices) refers to the time it takes from power-on to bring up the system to point a in figure 8-4. for example, when a scam master selects a scam tolerant device, the scam master may release bsy (point a) five seconds after the scam tolerant device has powered-on. the scam tolerant device will recognize the selection and respond within 1 ms by asserting bsy (point b). similarly, when a scam master device selects a scam slave device, the scam master may release bsy 1 s after the scam slave device has powered-on. the scam slave device will respond with its default id by asserting bsy at least 4 ms after the master has released bsy . figure 8-4 level 1 scam arbitration and selection timing 19113a-37 bsy sel data masters id masters and targets ids target asserts bsy here selection response time a b it is the difference in selection response time which distinguish between scam slave and scam tolerant devices. 8.5 scam protocol the following describes the scam protocol for scam master and scam slave devices. amd 8-5 scam tutorial 8.5.1 scam master device operation figure 8-5 shows the flow diagram for level 1 scam master devices. whenever the scam master is powered-on, it should generate a scsi bus reset. once this has occurred, the scam master will initialize its internal table of ids to indicate that all ids are uncategorized (initialize state). the scam master will then proceed with categoriz- ing ids by winning arbitration and selecting an uncategorized id using a selection time-out delay less than the scam default id selection response time. this process is repeated until all ids are categorized. id categorization is done in four ways: (1) the scam master shall categorize its own id as in use. (2) if a target device responds to selection of an uncategorized id by asserting bsy , the master will categorized that id as in use. (3) if no device responds to selection of an uncategorized id within a scam tolerant selection response time, and the selection phase began later than both a scam tolerant power-on to selection time following the masters most recent power-on and a scam tolerant reset to selection time following the most recent reset condition, then the master may categorize that id as not in use. (4) the target may categorize ids through non-scam means such as configuration parameters. after categorizing ids, the scam master should initiate the scam protocol and assign ids. a scam master may initiate the scam protocol as often as it wishes. for example the master should subsequently initiate the scam protocol if it determines that a scam slave device has just been powered-on or reset. figure 8-5 level 1 scam master protocol 19113a-38 power up wake-up bus reset categorize ids assign ids bus reset amd scam tutorial 8-6 8.5.2 scam slave device operation figure 8-6 shows the flow diagram for level 1 scam slave devices. following a scsi bus reset or power-on, a scam slave device will cease responding to its former id and perform local initialization (wake-up state). after completing this, the scam slave device will monitor the bus for selection or reselection of its default id (if any), or for scam selection. a scam slave device will enter the monitor state no later than a scam power-on to scam selection time following power-on. similarly, the device will enter the monitor state no later than a scam reset to scam selection time following a bus reset condition. if a scam slave device detects selection or reselection of its default id while in the monitor state, the device must wait a minimum of a scam default id selection response time before asserting bsy . if the selection or reselection phase persists for longer than that time, the scam slave device will assert bsy . the scam slave device will then confirm its default id (confirmed state) only if it asserted bsy in response to selection or reselection of its default id. a device that has confirmed its default id will ignore scam selection and will respond to subsequent selection or reselection of its default id within a scam tolerant selection response time. the devices default id remains confirmed until the next bus reset condition or loss of power. if a scam slave device detects scam selection within a scam default id selection response time while in the monitor state, the slave device will accept an id assigned by the scam master. upon receiving a soft id assignment (assigned state), a scam slave device will ignore scam selection and will respond to subsequent selection or reselection of its soft id within a scam tolerant selection response time. the device will continue to use its soft id until the next bus reset condition or loss of power. figure 8-6 level 1 scam slave protocol 19113a-39 bus reset or power-on wake-up monitor assignable assign ids default id selected assert bsy after delay confirmed local initilization completed scam slave responds to scam selection scam master assigns id amd 8-7 scam tutorial 8.6 scam examples the following examples illustrate scam operation. example 1 a scsi bus has one scam master (the AM53C974A) with id of 1, one scam tolerant device with id of 4, and one scam slave device with default id of 2. a new soft id will be assigned to the scam slave device as shown. (1) scam tolerant and scam slave devices power-on before or concurrently with the AM53C974A. (2) the AM53C974A arbitrates for the bus and selects device with id of 2. the AM53C974A will not release bsy until 5 seconds after the scam tolerant or scam slave device has powered-up. (3) the AM53C974A deasserts and monitors bsy . within 1 ms, no device on the bus asserts bsy . at 5 ms, a device responds by asserting bsy . therefore, device with id of 2 is a scam slave device (default id confirmed). (4) the AM53C974A repeats (2) and (3) with target id of 4. a device asserts bsy within 1 ms. therefore, device with id of 4 is a scam tolerant device. (5) the AM53C974A repeats (2) and (3) with other target ids but no device on the bus asserts bsy . thus the AM53C974A has finished categorizing the bus ids. (6) the AM53C974A initiates scsi bus reset. (7) the AM53C974A arbitrates for the bus. (8) at least 250 ms later, the AM53C974A initiates the scam protocol and selects the scam slave device without id. (9) the AM53C974A assigns soft id to the scam slave device. example 2 same as example 1 except there is one more scam intolerant device with id of 6. the selection response time is 3 ms. this can be up to 250 ms maximum according to the scsi specification. (1) scam master repeat (1) through (3) in example 1 to categorize ids for scam tolerant devices. (2) the AM53C974A scans for scam slave devices by detecting a response within 4 ms. the AM53C974A detects scam slave device with id of 2, and a scam intolerant device with id of 6. (3) the AM53C974A initiates a scsi bus reset. (4) the AM53C974A assigns a soft id to the scam slave device with a value other than its default id of 2. (5) the AM53C974A assigns a soft id to the scam intolerant device with a value other than its default id of 6. the scam intolerant device does not respond to soft id assignment. as a result, the AM53C974A concludes that this device is a scam intolerant device with a hard id. (6) the AM53C974A initiates a scsi bus reset. (7) the AM53C974A assigns a soft id to the scam slave device only. amd scam tutorial 8-8 example 3 a scsi system has two scam tolerant devices with ids of 2 and 3, and one scam slave device with default id of 3. the following algorithm can be applied. (1) the host detects tolerant devices with ids of 2 and 3 by using selection time out of 1 ms. (2) the host initiates the scam selection sequences (discussed later) starting with the id of 0 up to 6. (3) scam slave devices respond to scam selection when the host selects device with id of 3 (the slave device). (4) the host assigns new id to scam slave device. 8.7 id assignment 8.7.1 protocol initialization the procedure for assigning soft ids can be divided into two major sequences: id categorization and id assignment. once ids have been categorized, the master may initiate the scam protocol to perform id assignments. an example of the id assignment sequence is shown in figure 8-7. the scam protocol begins with the arbitration and scam protocol initialization phases. the following shows the procedure for a level 1 master initiating the scam protocol. (1) scam master arbitrates with its id and wins. (2) scam master asserts msg and releases data bus after sel is asserted. (3) scam master releases bsy after at least 2 deskew delays. (4) scam master releases msg after at least a scam selection time. (5) scam slave device asserts bsy . (6) scam slave device asserts i /o, db6, db7 and scam master asserts i /o c /d, and db7 after at least 2 deskew delays. (7) scam master releases sel after at least 2 deskew delays. (8) all scam devices release db6. if c /d is not asserted, all scam devices will release all signals. (9) participating scam devices assert sel . amd 8-9 scam tutorial figure 8-7 scam protocol initialization sequence 19113a-40 bsy sel data c/d i /o db7 msg db6 a b c d a = minimum 2 deskew delays b = minimum a scam selection time c = minimum 2 deskew delays d = minimum 2 deskew delays the scam protocol functions through a sequence of transfer cycles. during each cycle, certain devices (there may be more than two devices participating) send data to all participating scam devices. the actual data received is the logical or of the data sent by all the sending devices. figure 8-8 shows the transfer cycle operation. figure 8-8 transfer cycle operation 19113a-41 latch data before asserting db0C4 db5 db6 db7 scam device initiates the transfer cycle by putting the data on db0-4, asserting db5, and releasing (deasserting) db7. the following steps shows the sequence of the transfer cycle. amd scam tutorial 8-10 (1) place data on db0-4, assert db5, release (deassert) db7. (2) wait until db7 is released by all other devices. (3) read and latch data, and assert db6. (4) release db5. (5) wait until db5 is released by all other devices. (6) release or change db0-4, assert db7, and release db6. (7) wait until db6 is released by all other devices. at the beginning and end of each cycle, db7 is asserted while db5 and db6 are released. figure 8-9 shows an example of a system with two scam devices in a transfer cycle. the sending device on a level 1 scam capable bus will be the only scam master. after the scam master places the data on db0-4, it asserts db5 and deasserts db7. when the scam slave device detects the assertion of db5, it under- stands that a transfer cycle is being initiated. at this point it will deassert db7 and asserts db5. during the time when db5 or db6 is asserted, it indicates that the transfer cycle is in progress. when the scam slave device finishes reading the data, it will assert db6. when the sending device senses the assertion of db6, it deasserts db5 and prepares for termination of the cycle. the receiving device deasserts its db5 to signal the completion of the read operation. the scam master will wait until db5 is released by all devices before releasing db0-4 and db7. when the slave device detects the assertion of db7, it will release db6. figure 8-9 example showing device output signal timing diagram during transfer cycle 19113a-42 db0C4 db5 db6 db7 sending device receiving device db0C4 db5 db6 db7 amd 8-11 scam tutorial 8.7.2 function codes successive transfer cycles are grouped into iterations. each iteration performs a distinct functional purpose, such as assigning an id to a single device. the first transfer cycle in each iteration transfers a synchronization pattern, which consists of all five data bits asserted. the master device asserts the synchronization pattern to begin a new iteration. this synchronization pattern may be asserted at any time to abort an iteration and begin a new one. the second transfer cycle in each iteration contains a function code. table 8-1 defines the function codes. table 8-1 table of function codes function code description 00000b assign id 00001b set priority flag 00010b to 01110b reserved 01111b dominant master contention 10000b to 11110b reserved 11111b synchronization pattern slave devices shall ignore any iteration whose function codes are reserved or are codes they do not recognize. figure 8-10 shows an example of a scam configuration se- quence. the sequence begins with a scam protocol initialization sequence shown in figure 8-6. the scam master will begin an iteration sequence by first sending a synchronization pattern to all scam slave devices. this will then be followed by a function code, identification string, and the tasks required for carrying out the function code. figure 8-10 example showing a scam configuration sequence 19113a-43 arbitration scam protocol synchronization function identification action codes synchronization pattern initialization pattern code string isolation iteration 8.7.3 identification string in a iteration sequence, each scam slave device will send out an identification string serially (will be explained later). this identification string (figure 8-11) consist of a two byte type code: the 8-byte vendor id code (from the inquiry data) followed by a vendor unique code which may consist of up to 21 bytes. amd scam tutorial 8-12 figure 8-11 identification string format 19113a-44 bit 7 bit 0 priority code max id code reserved id valid sna reserved id vendor id code (from inquiry data) (8 bytes) vendor unique id code (up to 21 bytes) this bit sent first this bit sent last the content of the header is explained below. priority code the 2 bit code which indicates the priority for a device winning an isolation stage. the values in this field depend upon the function code and are defined in the individual function code description. maximum id code the 2 bits encode the maximum scsi id that the device can accept. 00b device can accept up to 1fh 01b device can accept up to 0fh 10b device can accept up to 07h 11b reserved reserved this one bit code shall be sent as 0. a device that receives a 1 in this bit shall defer for the iteration. id valid the 2 bit code indicates the validity and content of the id field as follows. 00b id not valid 01b id field contains a default id or a soft id 10b id field contains a hard id. 11b reserved. a device that receives this code shall defer for the iteration. amd 8-13 scam tutorial sna a 1 in this one bit field indicates that the devices full identification string is available. if the devices identification string is not yet available, and the device continues to participate in the isolation stage, the device shall stall some subsequent handshake until its identification information is available. reserved the 3 bit code shall be sent as 0. id the devices default id, assigned soft id, or hard id. vendor id code the 8 byte code shows the vendor id code obtained from the inquiry data. vendor unique code this code may be up to 21 bytes in length. it contains the vendor unique code such as the devices serial number. during the isolation stage, each participating device sends an identification string bit serially. the bit values are encoded in bit 0 and 1 of db0-4. for example, a 0 will be encoded as 00001b while a 1 will be encoded as 00010b on db0-4. each participating device will send and read the data in each transfer cycle. the data is interpreted in table 8-2. table 8-2 bit pattern interpretation during identification string transfer bit value sent on db4C0 received on db4C0 condition 0 0001b 00001b continue 00011b defer 1 00010b 0001xb continue none 00000b 000x1b defer 0001xb defer 00000b terminate any 000xxb 100xxb terminate other combination other combination error the continue condition means the device shall continue to participate in the isolation stage. the defer condition means that the device has lost to a device with a higher identifica- tion string. the identification string of the winning device is obtained from db1. for example, suppose that device a sends a bit string of 1010110... and device b sends 1010100...., amd scam tutorial 8-14 device a device b bus data 00010 00010 00010 00001 00001 00001 00010 00010 00010 00001 00001 00001 00010 00010 00010 00010 00001 00011 00001 00001 00001 since the sixth data bit of device a has a higher value, device b has to defer the identification string transfer. however, device b shall continue to handshake data without asserting db0-4 and wait for the next synchronization pattern. the terminate condition means that the isolation stage has terminated. the scam master may terminate the transfer by asserting db4 (refer the above terminate condition). the error condition implies that a bus error or reserved pattern was encountered. the error condition is typically treated the same as the defer condition. the isolation stage normally terminates with a single remaining participating device. when this occurs, a master may assign this remaining device an id or instruct it to perform some other action. 8.7.4 assigning ids two function codes, the assign id and set priority flag functions, can be used to assign soft ids to scam slave devices. to assign ids, the scam master should arbitrate, initiate the scam protocol, send the assign id or set priority flag function code, enter the isolation stage, and assign ids by sending action codes (will be discuss later in this section). each scam device maintains a priority flag while the scam protocol is active. the priority flags value determines the content of the priority code field sent during the isolation stage for these functions. the priority code field will be sent as p0 (binary), where p is the current value of the devices priority flag. as a consequence, low priority devices (p=0) will defer to a high priority device (p=1). each scam device will set its priority flag to 1 (set by devices firmware) during scam selection. the clear priority flag action of the action code (defined later in this section) sets the priority flag to 0. the assigned id function leaves the flag unaltered while the set priority flag function sets the flag to 1. after the isolation stage terminates, the master device will send an action code to the remaining device(s). when this occurs, two situations may result: (1) one slave device responds to the action code ---- one slave device remains with high identification string. (2) more than one slave device responds to action code --- scam master terminates isolation stage by asserting db4. all slave devices will receive and act on action code. amd 8-15 scam tutorial action codes are two quintets sent on db4C0. in each quintet, db2C0 contains a three bit code value and db4C3 contains two check bits. the value in db4C3 is the count of the number of zero bits in db2C0. table 8-3 shows the possible action codes. table 8-3 possible action codes first quintet second quintet description 11000b ccnnnb assign scsi id 00nnnb 10001b ccnnnb assign scsi id 01nnnb 10010b ccnnnb assign scsi id 10nnnb 01011b ccnnnb assign scsi id 11nnnb 10100b 11000b clear priority bit 10001b reserved 10010b locate on 01011b locate off others reserved 01101b ccnnnb reserved 01110b ccnnnb reserved 00111b ccnnnb reserved an action code is valid if the check bits are correct and both quintets are received. the remaining device(s) performs a valid action code as soon as they receive it. transfer cycles after a valid action code and preceding the next synchronization pattern are ignored. the assign id action code assigns id to slave devices. the cc of the second quintet is the parity code while the nnn is the assigned id. the clear priority bit action code instructs the remaining device(s) to clear their priority flag. this function is typically used when the master wishes to defer assigning an id to any device(s) until a later iteration. the locate on and off action code instructs the remaining device(s) to provide assistance for users or service personnel attempting to physically locate the device. upon receiving a locate on action code, the recommended action is for the remaining device(s) to flash their fault indicators or some similar indication. the indication should be cleared upon receiving a locate off action code, a reset condition, after a time delay, or upon other vendor unique actions. a scam slave device that receives a valid id assignment should release all bus signals and cease participating in the scam protocol until the next reset condition or power-on. scam slave devices shall continue participating in the scam protocol if they receive any other action code, receive an invalid or reserved action code, or do not receive an action code. 8.5.5 default id and id assignment the default ids of different kinds of scam devices are suggested by the scsi commit- tee and is specified in the proposal for plug and play scsi specification version 0.96, december 13, 1993. the default ids listed in table 8-4 are required settings for all plug and play scsi devices as shipped from the factory. amd scam tutorial 8-16 table 8-4 as shipped scsi id assignment scsi id scsi default id 7 host adapter 6 disk drive 5 4 tape or r/w optical 3 cd-rom 2 scanner/printer 1 0 it is important to ensure consistent id assignment to scsi devices when the system is repeatedly powered-down or reset. figure 8-12 shows the algorithm for maintaining consistent id assignments. figure 8-13 algorithm that ensures consistence id assignments 19113a-45 requested default id already assigned? next lower level id available? assign highest available id assign requested id assign lower level id no no yes yes for example, a scsi system has two scam tolerant hard drives of ids 2 and 3, one scam tolerant cd-rom with id of 5, and a scam slave device with default id of 3. during the id assignment phase, since the default id of 3 has already been assigned to a hard drive, the algorithm will check if the next lower level id is available. since an id of 2 is also assigned to a hard drive, the algorithm will check for the highest available id, which is the id of 4. since this id is available, it will be assigned to the scam slave device. 9-1 design considerations for motherboards and adapter cards design considerations for motherboards and adapter cards 9 9.1 introduction this chapter covers motherboard and add-in card design considerations which use the AM53C974A. it discusses scsi component placement, signal routing, pci interface recommendations, noise considerations and termination schemes. 9.2 signal routing and scsi placement the main components for board design include the AM53C974A (whose maximum trace length from the pci speedway or adapter card edge connector is 1.5 ), scsi connec- tors (either one or two depending internal/external support), a 40 mhz crystal oscillator and regulated terminators (on-board) which can be up to .1 m (3.937 in) away from the AM53C974A. there are many ways to route scsi bus traces on a host adapter board or motherboard. ideally, traces from the internal scsi bus connector, from the AM53C974A and from the external scsi bus connector should all connect in series. care should be taken not to have any stubs in the scsi bus. (stubs are any extensions off of the main bus. the maximum scsi bus stub length allowed is .1 m). this routing scheme helps maintain signal integrity by reducing the possibility of signal reflections and other undesirable effects. auto-routing programs used for board layout may not follow this scheme, and may create non-ideal environments by routing internal and external on-board connec- tors first instead of routing both sets of traces to the AM53C974A. when peripherals are added either internally or externally, a three-pronged scsi bus will be created instead of a linear one. if this or any other stub problem occurs, changes should be made manually to follow the ideal scheme. refer to figures 9-1 and 9-2. amd design considerations for motherboards and adapter cards 9-2 figure 9-1 ideal routing scheme 19113a-46 connector for internal peripheral termination external scsi-2 bus cable external peripheral high-density scsi-2 connectors high-density scsi-2 termination AM53C974A to pci bus 25 linear bus- no stubs figure 9-2 a poor routing scheme 19113a-47 external scsi-2 bus cable external peripheral high-density scsi-2 connectors high-density scsi-2 termination AM53C974A to pci bus 25 connector for internal peripheral termination 3-pronged bus (not recommended) stub bracketed card joining ribbon cable with high- density scsi-2 cable amd 9-3 design considerations for motherboards and adapter cards 9.2.1 the motherboard the following two layouts may be used as a guideline for the design of motherboards which incorporate the AM53C974A. for both layouts, the scsi connectors should be placed as far away from the pci speedway as possible. each layout refers to termina- tion considerations which are described in further detail in section 9.4. 9.2.1.1 layout #1 this approach avoids the cost of placing an external connector on the motherboard. in this configuration, the AM53C974A is always at one end of the scsi bus, therefore, the regulated terminators remain active. this eliminates the problem of switching the regulated terminators on or off to accommodate peripheral configurations. this ap- proach also preserves the ideal linear routing scheme. the following lists the require- ments for implementation, while figure 9-3 illustrates this approach. one connector on the motherboard connected to one end of the internal bus ribbon cable and its components. the other end of the internal bus ribbon cable connected to one end of the external bus high density cable and its peripherals via a bracketed add-on card. the internal bus may also be crimped to a scsi connector mounted on a bracket. on board regulated terminators a maximum of .1 m (3.937 in) from the AM53C974A. external terminators connected to the end of the external bus. figure 9-3 motherboard layout CC approach #1 19113a-48 cpu memory external peripheral high-density scsi-2 termination high-density scsi-2 connector keyboard connector bracketed card joining ribbon cable with high-density scsi-2 cable external scsi-2 bus cable internal scsi bus cable connector for internal peripheral to dc power ferrite bead to scsi clk1 AM53C974A to pci bus always on 25 termination amd design considerations for motherboards and adapter cards 9-4 9.2.1.2 layout #2 this approach uses a pizza-box type of motherboard, which has been incorporated into pc systems and workstations. this design reduces the systems height so that its casing resembles a pizza box. this is partly the result of a riser card that enables cards to rest on their side instead of upright. this approach requires the following and is illustrated in figure 9-4: an external connector mounted on the motherboard with routings that connect to the AM53C974A. the AM53C974A must be as close as possible to this external connector since this part of the scsi bus consists of motherboard routings (not just ribbon cable). an internal connector on the motherboard to accommodate internal drives. on-board regulated terminators for scsi drives not mounted within the system. how- ever, should the user decide to connect a drive internally, terminators are not needed. if on-board regulated terminators are used, they should be placed within .1 m (3.937 in) from the AM53C974A. figure 9-4 motherboard layout #2 19113a-49 this is optional. use accordingly to terminate both ends of the scsi bus. cpu memory internal drive (terminated) riser card high-density scsi-2 termination external scsi bus cable external peripheral high-density scsi-2 connectors keyboard connector to scsi clk1 AM53C974A to dc power ferrite bead to pci bus termination 25 mounted high-density scsi-2 connector termination motherboard designs which place an internal and external connector on either side of the AM53C974A are discouraged since: two scsi connectors are required on the motherboardone more than what the other two approaches call for. amd 9-5 design considerations for motherboards and adapter cards when the number of internal and external bus components increase, the on-board terminators would have to be turned off either through software or hardware, which may be undesirable to a board designer. the possibility for creating stubs exists if the connectors and AM53C974A are not routed correctly. see figure 9-1 for the ideal routing scheme. 9.2.2 the adapter card generally, add-in scsi adapter cards provide both an internal and external scsi connector to allow for the attachment of scsi peripherals. as a result, care should be taken in the layout of the board so that the ideal scsi bus routing scheme is followed (figure 9-1). figure 9-5 shows a layout which preserves the ideal routing scheme and may be used as a guideline for the design of adapter cards which use the AM53C974A. figure 9-5 layout scheme for adapter card designs internal scsi connector scsi bus terminator AM53C974A the following lists the recommendations for add-in scsi card designs: a keyed 50-pin internal scsi header for connecting an internal scsi bus ribbon cable. a high-density 50-pin external scsi connector for connecting an external scsi-2 cable. on board regulated terminators a maximum of 0.1 m (3.937 in.) from the AM53C974A. this terminator can be designed to be automatically enabled or dis- abled depending on whether the adapter card is at one end of the scsi chain or in the middle of the chain (refer to section 9.4.1.3). a 4-pin header for connecting the front panel disk drive activity led. amd design considerations for motherboards and adapter cards 9-6 9.3 noise considerations some areas of a pci motherboard or host adapter design (which include the AM53C974A) are more susceptible to noise. they are: the 40 mhz crystal oscillator the scsi cables the dc power planes pins on the ics, specifically the AM53C974A. 9.3.1 electromagnetic interference (emi) there are several ways to reduce the amount of noise present in these areas: a 40 mhz crystal oscillator must be used in order to have a 10 mb/s scsi data rate. use of this 40 mhz crystal oscillator, which drives the scsi clk1 pin on the AM53C974A, introduces the possibility of unwanted high frequency components, in- cluding harmonics, coupling with AM53C974A signals. to help prevent this, a 33 ohm resistor should be placed in series with the oscillator to form a low pass filter with the input capacitance (10 pf) of the scsi clk1 pin. this filter reduces the edge rate of the clock waveform, increasing both rise and fall times by 2 ns. this removes higher frequencies, specifically harmonics from the crystal oscillator waveform and thus reduces the amount of noise introduced into the AM53C974A. a ferrite bead, which is essentially an inductor, may be used with the oscillator to pre- vent coupling of higher frequencies with dc power supply signals. the ferrite bead blocks high frequency noise while acting like a short to the dc components. from an emi standpoint, scsi-2 high-density cables should be used instead of a scsi-1 cables. unlike the scsi-1 flat ribbon cable, the scsi-2 cable is electrically more substantial. it is shielded and signal wires are strategically placed for better signal travel. 9.3.2 decoupling methods decoupling capacitors should be used across all v dd and v ss pins on motherboards and adapter cards. there are pairs of v dd and v ss pins on the AM53C974A that should each have their own decoupling capacitor (figure 9-6). the following decoupling method should be used for the v dd /v ss pairs: connect the capacitor directly between a v dd /v ss pair of the AM53C974A so that it sits on the component side of the board. this configuration will allow the capacitor to filter undesired high frequency components directly at the AM53C974A and not only at the power planes. this not only minimizes the noise on the power planes that the chip sees, but it also filters any noise generated by the chip before it reaches the power planes. the leads to each end of the capacitor should be wide and may contain several feed- throughs to the v dd and v ss planes to reduce the inductance present. the trace length from pin to capacitor should be less than 0.25 2 , assuming a 20 mil trace. the average decoupling should be at least 0.01 m f per v dd pin. additionally, all 3.3 v pins must also be decoupled with an average of at least 0.01 m f per gold finger. amd 9-7 design considerations for motherboards and adapter cards figure 9-6 decoupling capacitor placement where c1 C c9 are decoupling capacitors. 19113a-50 132 1 ad28 ad29 131 v ss3b 130 ad30 129 ad31 128 pci^req 127 ba7 126 v ss 125 pci^gnt 124 ba6 123 v dd 122 clk 121 pci^rst 120 v ss 119 ba5 118 inta 117 res_dnc 116 ba4 115 ba3 114 v ss 113 ba2 112 ba1 111 nc 110 v dd 109 v dd 108 nc 107 ba0 106 lck 105 oe 104 v dd 103 nc 102 bd0 101 boot 100 bd1 99 v ss 98 bd2 97 v dd 96 bd3 95 bd4 94 bd5 93 nc 92 v dd 91 bd6 90 bd7 89 v ss 88 i/o 87 c/d 86 msg 85 v dd 84 ack 83 v ssb 82 req 81 sel 80 v ss 79 sd p 78 sd 7 77 v ddb 76 sd 6 75 sd 5 74 sd 4 73 v ssb 72 sd 3 71 sd 2 70 sd 1 69 sd 0 68 v ssb 67 34 par 35 c/ be 1 36 ad15 37 v ss3b 38 ad14 39 ad13 40 ad12 41 ad11 42 ad10 43 v ss3b 44 ad9 45 ad8 46 v dd3b 47 c/ be 0 48 ad7 49 ad6 50 v ss3b 51 ad5 52 ad4 53 ad3 54 ad2 55 v ss3b 56 ad1 57 ad0 58 59 v dd 60 scsiclk1 61 v ss 62 busy 63 v ss 64 bsy 65 atn 66 scsi^rst v dd3b 2 ad27 3 ad26 4 v ss3b 5 ad25 6 ad24 7 c/ be 3 8 v dd 9 idsel 10 nc 11 v ss 12 ad23 13 ad22 14 v ss3b 15 ad21 16 ad20 17 v dd3b 18 ad19 19 ad18 20 v ss3b 21 ad17 22 ad16 23 c/ be 2 24 frame 25 irdy 26 trdy 27 devsel 28 stop 29 lock 30 v ss 31 perr 32 serr 33 v dd3b pwdn pc scsi ii (AM53C974A) c 9 c 8 c 7 c 1 c 2 c 3 c 4 c 6 c 5 decoupling methods which are not recommended include: connecting a capacitor only between the v dd and v ss planes so that it sits on the component side of the board. this doesnt allow the capacitor to reduce noise directly at the chip, but it does allow for a reduction of power plane noise and of board com- ponents. (capacitors). connecting a capacitor only between the v dd and v ss planes so that it sits on the sol- der side of the board. this configuration also doesnt allow direct decoupling at the chip. it does save board space, but it requires an extra manufacturing step. amd design considerations for motherboards and adapter cards 9-8 9.4 termination considerations the use of active or regulated termination for terminators on motherboards and adapter cards is recommended (see figure 9-7), while external scsi terminators can be used to terminate other parts of the scsi bus. terminators must match the impedance seen by a signal at the end of the scsi bus to the characteristic impedance of the scsi bus. this impedance is typically 84 +/C 12 w , but can vary greatly with pc board characteris- tics and cabling. figure 9-7 regulated termination v in v out low dropout voltage regulator v adj c1 10 m f alum. or 4.7 m f tant. 15 v r1 121 w 1% 1/4w r2 154 w 1% 1/4w c2 150 m f alum. or 22 ? tant. 10 v c3 .1 m f ceramic 25 v r3-20 are 110 w 1% r3-11 r12 r14 r15 r16 r17 r18 r19 r20 r13 termpwr db (0-7,p) atn bsy ack rst msg sel c/d req i/o 2.85 v 19113a-51 9.4.1 termination there are three general termination schemes that apply to motherboard or host adapter setups when using regulated terminators. each scheme recognizes that the scsi bus must be terminated on both ends. therefore, as more components and peripherals are added to the bus, terminators must be relocated accordingly. each scheme is also based on an ideal routing situation, that is one where the internal peripherals, external peripherals and the AM53C974A chip are connected by a linear scsi bus. see figure 9-1. in all schemes, it is recommended that active termination be used. 9.4.1.1 scheme #1 in this case, the system uses only scsi internal peripherals. the regulated terminators on board should be activated. peripherals can be added to the bus by connecting them to a 50-pin ribbon cable. a scsi terminator should be attached to the last peripheral to terminate the other end of the bus. 9.4.1.2 scheme #2 in this case, the system uses only external scsi peripherals. as in scheme #1, the on-board regulated terminators should be activated. in this scheme, a 50-pin high amd 9-9 design considerations for motherboards and adapter cards density scsi-2 cable should connect the external port on the motherboard or host adapter to the first external peripheral. peripherals may be added with more cables and the last peripheral should be terminated. 9.4.1.3 scheme #3 in this case, both internal and external scsi peripherals are used. the regulated terminators should be deactivated (since the AM53C974A will sit in the middle of the scsi bus). this may be accomplished through hardware. this approach involves developing a mechanism to detect peripherals connected to the scsi bus. this mechanism must then activate a signal to turn the regulated terminators on or off accordingly. care should be taken to ensure that each end of the bus is terminated. figure 9-8 shows the circuit to determine when to turn the on-board terminators on or off. in this figure, the inputs of the circuit are derived from one of the designated ground pins on each scsi connector (internal and external). in this example, pin 22 of the internal connector and pin 50 of the external connector are chosen for illustration purposes. when this is done, these ground pins are no longer connected to ground on the adapter card. instead, they are pulled to v dd through resistors r. as a result, when only internal or external peripherals are attached to the scsi bus, one of the inputs to the or gate will remain high so that the or output will be high to enable the active terminator. however, when both internal and external peripherals are attached to the scsi bus (the adapter card is in the middle of the scsi chain), both or inputs will be pulled low and the or output will go low to disable the active terminator. figure 9-8 circuit to automatically enable/disable on-board active termination 19113a-52 from pin 22 of 50-pin internal scsi connector external scsi connector from pin 36 of high density or r r v dd enable/disable active termination 9.5 other considerations the following are considerations for routing and layout for both motherboards and adapter cards. they should be taken into account along with scsi considerations where applicable. n high speed signals should be referenced only to the ground plane or exclusively to one of the power planes. if not, the power planes should be decoupled. n for a pci clk of 33 mhz, the maximum round trip time of any shared mother board signal should be less than 10 ns. n the AM53C974A provides expansion rom support which can be enabled/disabled via pin 100 (boot). for flexibility in building cards with or without boot rom capabil- ity, adapter cards may provide a pull-up or pull-down resistor stuffing option for this amd design considerations for motherboards and adapter cards 9-10 pin so that the boot rom can be enabled/disabled during the manufacturing of the board. in this case, the layout stuffing option can be made so that only one resistor can be stuffed. this can be done by laying the resistors perpendicular to each other while sharing one pad (figure 9-9). thus depending on which resistor is stuffed, the rom can be enabled or disabled. figure 9-9 layout of stuffing option for boot pin 19113a-53 r1 r2 trace to v dd to boot pin shared node trace to gnd n similarly, since the AM53C974A can be operated with or without an external oscilla- tor on the scsiclk1 pin, a stuffing option can also be provided for this feature. in this case, if the oscillator is used, then only the oscillator and a 33 ohm resistor are stuffed. however if the oscillator is not used, then only a 10k pull-up should be stuffed. as before, a perpendicular layout of the 33 and 10k ohm resistors can be used to insure that only one resistor is stuffed. amd 9-11 design considerations for motherboards and adapter cards figure 9-10 layout of stuffing option for scsiclk1 pin 19113a-54 33 ohm 10k trace to xtal to scsiclk1 shared node trace to v dd n all unused inputs on the AM53C974A should be pulled to the inactive state with a 10k resistor unless specified otherwise in this manual. n prsnt[1:2] pins on adapter cards should reflect the maximum power consumption of the card. typically these pins are grounded (7.5w maximum) for cards which use the AM53C974A. for motherboards, the prsnt[2:1] pins should each be decoupled to ground with 0.01 m f capacitors. n tdi and tdo pins on adapter cards should be connected together to provide jtag continuity. amd design considerations for motherboards and adapter cards 9-12 10-1 amd's pc scsi ii software amd's pc scsi ii software 10 10.1 introduction reduced time to market, support for all major operating systems, and the means to harness the performance and flexibility of the pci interface CC this is what amds pc scsi ii software solution is all about. at the heart of this solution is a scsi software architecture which provides maximum flexibility in low level scsi protocol chip software. the architecture represents a modular approach to software development and is the key factor which allows amd to meet the aggressive time schedules set forth by our customers. 10.2 pc scsi ii software architecture amds scsi software architecture is divided into two layers: a) hardware (h/w) dependent layer provides low level programming of scsi protocol chip utilizes functions and services provided by the operating system dependent layer independent of the operating system written only once for each scsi chip b) operating system (os) dependent layer acts as a manager for the h/w dependent layer by providing functions which the h/w dependent layer requires to execute desired requests written for specific operating system platforms provides dma services, request completion, interrupt services, memory allocation, i/o port, and address translation the operating system device drivers generate i/o requests which are translated into scsi requests that are executed by the o/s dependent layer. this o/s dependent layer then performs any operating system dependent functions and passes the requests to the h/w dependent layer for hardware delivery. amds pc scsi ii software architecture features: device level overlapped/multi-threaded operation tagged-queuing automatic request sense scatter-gather operation synchronous transfers (including fast scsi) amd amd's pc scsi ii software 10-2 10.3 operating system support amd pc scsi ii software supports the following operating systems: dos 5.0, 6.0 netware 3.1x, 4.x windows 3.1 os/2 2.x windows nt sco unix 3.2.4/odt 3.0 a brief description of amds device drivers and support tools under the above operating systems are highlighted below. 10.3.1 dos a) installation program installs dos device drivers and application programs update options in config.sys and autoexec.bat files. installs appropriate command line switches for device drivers based on users choices. supports windows 3.1 driver supports for updating installation floppies of os/2 2.x b) aspi device driver central execution point for aspi based dos device drivers compliant with aspi specification multi-threaded execution, virtual dma services, int13h interceptor/handler, and windows 3.1 support manages host adapter resources provides hardware independent aspi for scsi applications and drivers c) cd-rom device driver complies with microsoft cd-rom extensions operates via aspi interface supports data and audio functions d) removable media device driver supports for greater than two fixed disks under dos versions 3.31C4.0 operates via aspi interface command line switches controllable by user applications e) scsi low level format utility issues scsi commands via aspi to format disk media media scan functions which ensure media integrity allows user to select scsi options pertaining to media defect handling (e.g. automatic write reallocation, number of retries etc.) amd 10-3 amd's pc scsi ii software f) compact disk audio play utility operates via microsoft cd-rom extensions to provide support for audio tracks on cds provides play, up-track, down-track, pause and stop features 10.3.2 netware a) netware aspi netware loadable module based on the aspi interface for netware 386 (dated august 4, 1991) calls disks driver for netware accepts requests from aspi clients and parses them performs netware specific nlm initialization detects error and converts to aspi error codes b) netware server 3.1x + /4.x based on device driver function specification for netware operating system version 3.1x netware loadable module is accessible to users can server command line accepts commands from mass storage control, ioctl interface and i/o operations interface parses and dispatches commands to appropriate command routines 10.3.3 os/2 a) installation program detects the presence of the scsi controller. utilized to access the hardware. b) setup profile describes the installation data needed by the device driver utility provided with os/2. c) adapter device driver complies with ibm os/2 2.x original equipment manufacturers dasd and scsi device driver support document. 10.3.4 windows a) installation program same dos 5.0, 6.0 install program described previously. b) fastdisk driver installed only for windows version 3.1+ supports scatter-gather dma operations. c) aspi virtual device driver aspi complaint virtual device driver. amd amd's pc scsi ii software 10-4 provides aspi services to dos based programs that are running in a dos virtual machine within windows 3.1+. supports dos virtual machines and multi-threaded scsi execution. communicates with dos aspi driver. d) windows 3.1 aspi dll aspi compliant installable windows device driver. the main function of this driver is to provide aspi services to aspi aware windows applications. e) scsi for windows utility shows status and inquiry data for all devices on the scsi bus 10.3.5 windows nt a) miniport miniport driver for windows nt for scsi. based on the port/miniport architecture b) setup update file for scsi.inf setup file for microsoft windows nt operating system. installs the scsi miniport driver under windows nt. 10.3.6 sco unix a) boot-time loadable driver automatically loads device drivers into unix kernel at boot time. 10.3.7 scsi rom bios supports int 13h fixed disks interface to provide i/o capability to system 3 main modules CC int13 i/o handler CC initialization code CC minimal scsi handler supports virtual dma services to provide compactibility with windows 3.x enhanced mode and some dos extenders supports up to 2 fixed disks for dos 5.x, 6.x co-exists with other disks controllers (like st506, esdi, ide etc.) supports up to 7 fixed disks for dos 5.x and non-dos operating systems developed assuming a minimum of 386 processor amd 10-5 amd's pc scsi ii software 10.4 peripheral support amd software supports peripherals such as cd-roms, tape drives, fixed disk drives, and magneto-optical drives. a comprehensive list of the manufacturer names and model numbers is provided in amds pssa document. below is a brief list of supported manufacturers. a) fixed disk drives: conner compaq h-p ibm quantum seagate maxtor micropolis fujitsu b) cd-rom: chinon panasonic dec denon hitachi ibm lmsi nec toshiba sony c) tape drives: archive connor ncr caliper sankyo cipher serverdat sony teac emerald tecmar amd amd's pc scsi ii software 10-6 exabyte tandberg gigatrend transitional technologies h-p wangdat ibm wangtek maynard ardat mountain d) magneto optical drives: h-p ricoh sony maxoptix storage dimensions AM53C974A literature/tool support a-1 AM53C974A literature/tool support a to enhance the ease of use for the AM53C974A, bus mastering scsi-2 controller for pci systems, amd has provided the following list of literature/tool support: AM53C974A data sheet C pid #19084a AM53C974A technical manual C pid #19113a amd pc scsi ii software solutions brochure C pid #18203a embedding scsi on pci motherboards brochure C pid #18179a amds pci solutions brochure C pid #18684a AM53C974A pc scsi ii product evaluation kit containing hardware reference platform scsi cable scsi driver licensing information evaluation software drivers for scsi bios dos windows windows nt netware sco unix os/2 pci host adapter board users manual pc scsi ii driver installation manual os/peripheral compatibility summary AM53C974A data sheet AM53C974A technical manual performance benchmarking report pc scsi ii software test report to obtain any of the literature above, contact amd literature center at (800) 222-9323 or (408) 749-5703. for more information on the AM53C974A pc scsi ii product evaluation kit, please contact your nearest amd sales office. amd AM53C974A literature/tool support a-2 for information on additional scsi software products contact: sequoia advanced technologies, inc. (415) 459-7978 (415) 459-7988 fax 71332,1020 compuserve id for further scsi standards information, contact john lohmeyer chair x3t9.2 ncr corporation 1635 aeroplaza drive colorado springs co 80916 (719) 573-3362 for scsi standard documentation, contact global engineering documents 15 inverness way east englewood, co 80112-5704 (800) 854-7179 (303) 792-2181 |
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