1/10 june 2001 n high speed: f max = 150 mhz (typ.) at v cc = 5v n low power dissipation: i cc = 4 m a (max.) at t a =25c n compatible with ttl outputs: v ih = 2v (min.), v il = 0.8v (max) n power down protection on inputs & outputs n symmetrical output impedance: |i oh | = i ol = 8 ma (min) n balanced propagation delays: t plh @ t phl n operating voltage range: v cc (opr) = 4.5v to 5.5v n pin and function compatible with 74 series 174 n improved latch-up immunity n low noise: v olp = 0.8v (max.) description the 74vhct174a is an advanced high-speed cmos hex d-type flip flop with clear fabricated with sub-micron silicon gate and double-layer metal wiring c 2 mos technology. information signals applied to d inputs are transferred to the q outputs on the positive going edge of the clock pulse. when the clear input is held low, the q outputs are held low independently of the other inputs. power down protection is provided on all inputs and outputs and 0 to 7v can be accepted on inputs with no regard to the supply voltage. this device can be used to interface 5v to 3v since all inputs are equipped with ttl threshold. all inputs and outputs are equipped with protection circuits against static discharge, giving them 2kv esd immunity and transient excess voltage. 74vhct174a hex d-type flip flop with clear pin connection and iec logic symbols order codes package tube t & r sop 74VHCT174AM 74VHCT174AMtr tssop 74vhct174attr tssop sop
74vhct174a 2/10 input equivalent circuit pin description truth table x : dont care logic diagram this logic diagram has not to be used to estimate propagation delays pin no symbol name and function 1 clear asynchronous master reset (active low) 2, 5, 7, 10, 12, 15 q0 to q5 flip-flop outputs 3, 4, 6, 11, 13, 14 d0 to d5 data inputs 9 clock clock input (low-to-high, edge triggered) 8 gnd ground (0v) 16 v cc positive supply voltage inputs outputs function clear d clock q l x x l clear hl l hh h hx q n no change
74vhct174a 3/10 absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditi ons is not implied 1) v cc = 0v 2) high or low state recommended operating conditions 1) v cc = 0v 2) high or low state 3) vin from 0.8v to 2v symbol parameter value unit v cc supply voltage -0.5 to +7.0 v v i dc input voltage -0.5 to +7.0 v v o dc output voltage (see note 1) -0.5 to +7.0 v v o dc output voltage (see note 2) -0.5 to v cc + 0.5 v i ik dc input diode current - 20 ma i ok dc output diode current 20 ma i o dc output current 25 ma i cc or i gnd dc v cc or ground current 50 ma t stg storage temperature -65 to +150 c t l lead temperature (10 sec) 300 c symbol parameter value unit v cc supply voltage 4.5 to 5.5 v v i input voltage 0 to 5.5 v v o output voltage (see note 1) 0 to 5.5 v v o output voltage (see note 2) 0 to v cc v t op operating temperature -55 to 125 c dt/dv input rise and fall time (see note 3) (v cc = 5.0 0.5v) 0 to 20 ns/v
74vhct174a 4/10 dc specifications ac electrical characteristics (input t r = t f = 3ns) (*) voltage range is 5.0v 0.5v symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. v ih high level input voltage 4.5 to 5.5 222v v il low level input voltage 4.5 to 5.5 0.8 0.8 0.8 v v oh high level output voltage 4.5 i o =-50 m a 4.4 4.5 4.4 4.4 v 4.5 i o =-8 ma 3.94 3.8 3.7 v ol low level output voltage 4.5 i o =50 m a 0.0 0.1 0.1 0.1 v 4.5 i o =8 ma 0.36 0.44 0.55 i i input leakage current 0 to 5.5 v i = 5.5v or gnd 0.1 1.0 1.0 m a i cc quiescent supply current 5.5 v i = v cc or gnd 44040 m a i cc additional worst case supply current 5.5 one input at 3.4v, other input at v cc or gnd 1.35 1.5 1.5 ma i opd output leakage current 0 v out = 5.5v 0.5 5.0 5.0 m a symbol parameter test condition value unit v cc (v) c l (pf) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. t plh t phl propagation delay time clock to q 5.0 (*) 15 5.8 7.8 1.0 9.0 1.0 9.0 ns 5.0 (*) 50 6.3 8.8 1.0 10.0 1.0 10.0 t phl propagation delay time clear to q 5.0 (*) 15 7.6 10.4 1.0 13.0 1.0 13.0 ns 5.0 (*) 50 8.1 11.4 1.0 13.0 1.0 13.0 t w clear pulse width low 5.0 (*) 5.0 5.0 5.0 ns t w clear pulse width high or low 5.0 (*) 5.0 5.0 5.0 ns t s setup time d to clock, high or low 5.0 (*) 5.0 6.0 6.0 ns t h hold time d to clock, high or low 5.0 (*) 0.0 0.0 0.0 ns t rem recovery time clear to clock 5.0 (*) 3.0 3.0 3.0 ns f max maximum clock frequency 5.0 (*) 15 95 150 80 80 mhz 5.0 (*) 50 55 85 50 50
74vhct174a 5/10 capacitive characteristics 1) c pd is defined as the value of the ics internal equivalent capacitance which is calculated from the operating current consumption without load. (refer to test circuit). average operating current can be obtained by the following equation. i cc(opr) = c pd x v cc x f in + i cc /6 (per flip-flop) dynamic switching characteristics 1) worst case package. 2) max number of outputs defined as (n). data inputs are driven 0v to 3.0v, (n-1) outputs switching and one output at gnd. 3) max number of data inputs (n) switching. (n-1) switching 0v to 3.0v. inputs under test switching: 3.0v to threshold (v ild ), 0v to threshold (v ihd ), f=1mhz. test circuit c l =15/50pf or equivalent (includes jig and probe capacitance) r t = z out of pulse generator (typically 50 w ) symbol parameter test condition value unit t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. c in input capacitance 6101010pf c pd power dissipation capacitance (note 1) 28 pf symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. v olp dynamic low voltage quiet output (note 1, 2) 5.0 c l = 50 pf 0.3 0.8 v v olv -0.8 -0.3 v ihd dynamic high voltage input (note 1, 3) 5.0 2.0 v ild dynamic low voltage input (note 1, 3) 5.0 0.8
74vhct174a 6/10 waveform 1: propagation delays, setup and hold times (f=1mhz; 50% duty cycle) waveform 2: propagation delays (f=1mhz; 50% duty cycle)
74vhct174a 7/10 waveform 3: removal time (f=1mhz; 50% duty cycle)
74vhct174a 8/10 dim. mm. inch min. typ max. min. typ. max. a 1.75 0.068 a1 0.1 0.2 0.003 0.007 a2 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 c 0.5 0.019 c1 45 (typ.) d 9.8 10 0.385 0.393 e 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 f 3.8 4.0 0.149 0.157 g 4.6 5.3 0.181 0.208 l 0.5 1.27 0.019 0.050 m 0.62 0.024 s8 (max.) so-16 mechanical data po13h
74vhct174a 9/10 dim. mm. inch min. typ max. min. typ. max. a 1.2 0.047 a1 0.05 0.15 0.002 0.004 0.006 a2 0.8 1 1.05 0.031 0.039 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 d 4.9 5 5.1 0.193 0.197 0.201 e 6.2 6.4 6.6 0.244 0.252 0.260 e1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 bsc 0.0256 bsc k0 80 8 l 0.45 0.60 0.75 0.018 0.024 0.030 tssop16 mechanical data c e b a2 a e1 d 1 pin 1 identification a1 l k e 0080338d
74vhct174a 10/10 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco singapore - spain - sweden - switzerland - united kingdom ? http://www.st.com
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