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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com ? ? ? ? XRT72L71 ds3 atm uni/clear channel framer august 2002 rev. 1.1.0 general description the XRT72L71 ds3 atm user network interface (uni)/clear-channel framer is designed to function as either a ds3 atm uni or clear channel framer. for atm uni applications, this device provides the atm physical layer (physical medium dependent and transmission convergence sub-layers) interface for both the public and private networks at ds3 rates. for clear-channel framer applications, this device supports the transmission and reception of user da- ta via the ds3 payload bits. the XRT72L71incorporates receive, transmit, micro- processor interface, performance monitor, test and di- agnostic and line interface unit scan drive sections. applications ? private user network interfaces ? at m s w i t c h e s ? atm concentrators ? dslam equipment ? ds3 frame relay equipment features ? compliant with utopia level 1 and 2 with 8 or 16 bit interface specification and supports utopia bus speeds of up to 50 mhz ? contains on-chip 16 cell fifo in both the transmit (txfifo) and receive directions (rxfifo) ? contains on-chip 54 byte transmit oam cell buffer and a 108 byte receive oam cell buffer, for trans- mission, reception and processing of oam cells. ? supports plcp or atm direct mapping modes ? supports m13 and c-bit parity framing formats ? supports ds3 clear channel framing applications ? includes prbs generator and receiver ? supports local, remote-line, cell, and plcp loop-backs ? interfaces to 8 or 16 bit wide motorola and intel ps ? low power 3.3v, 5v input tolerant, cmos ? 160 pin pqfp package ? 3 and 4 channel version also available f igure 1. XRT72L71 s implified b lock d iagram with s ystem i nterfaces xrt73l00 rxuclav ds3/e3 liu tx rx tpdata tndata tck dmo rlos rlol llb rlb taos txlev encodis reqdis rpos rneg rclk1 utopia bus level 1 or 2 ds3 44.736 mhz 16 16 25, 33 or 50 mhz intel/motorola m m m m p configuration, control and status monitor atm switch d[15:0] d[7:0] a[8:0] 4 txuclav 5 address 5 XRT72L71 address atm layer processor tx utopia interface tx cell processor tx plcp processor tx ds3 framer performance monitor microprocessor interface feac processor lapd transceiver rx utopia interface rx ds3 framer rx plcp processor rx cell processor liu interface drive and scan 75 w coax 75 w coax txpos txneg tck dmo rlos rlol lloop rloop taos txlev req rxpos rxneg rxlineclk encodis wr_rw ale_as rd_ds rdy_dtck
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 2 f igure 2. b lock d iagram of the XRT72L71 ds3 uni test and diagnostic line interface drive and scan performance monitor receive ds3 framer receive cell processor receive utopia interface transmitter receiver lapd transceiver microprocessor interface (programmable registers and interrupt block) feac processor transmit utopia interface txuclk txudata[15:0] txuprty txusoc txuen txuclav txuaddr[4:0] transmit plcp processor/ clear channel transmit serial data processor transmit ds3 framer receive plcp processor/ clear channel receive serial data processor 16 cell fifo 16 cell fifo 2x54b oam buffer transmit cell processor 54b oam buffer a[8:0] wr_rw rd_ds cs ale_as reset int d[15:0] width16 moto/intel rdy_dtck txpos txneg txframe txohclk txlineclk txaisen txframeref txinclk txohins txohframe txoh txpohframe 8kref stuffctl txohind/txpframe txserdata/txpoh txpohclk txpohins txcelltxed txgfcclk txgfcmsb txgfc tdo tdi testmode tck tms taos dmo rlol txlev rloop lloop req rxred encodis rxlineclk rxneg rxpos rlos rxais rxohclk rxoh rxserclk rxlos rxframe rxohframe rxoof rxpred rxpohframe rxserclk/rxpohclk rxserdata/rxpoh rxohind/rxpframe rxplof rxpoof rxlcd rxcellrxed rxgfcclk rxgfcmsb rxgfc rxuclk rxuen rxuprty rxudata[15:0] rxusoc rxuclav rxuaddr[4:0]
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 3 ordering information f igure 3. p in o ut of the XRT72L71 ds3 atm uni txohclk 121 txohframe 122 txuen 123 txusoc 124 txuprty 125 txuclav 126 gnd 127 txudata8 128 txudata0 129 txudata9 130 txudata1 131 txudata10 132 txudata2 133 txudata11 134 txudata3 135 vdd 136 txudata4 137 txudata12 138 txudata5 139 txudata13 140 txudata6 141 txudata14 142 txudata7 143 txudata15 144 vdd 145 txuaddr4 146 txuaddr0 147 txuaddr3 148 txuaddr1 149 txuaddr2 150 txuclk 151 gnd 152 testmode 153 txgfcmsb 154 reset 155 txgfcclk 156 ale_as 157 txgfc 158 gnd 159 rdy_dtck 160 d15 1 taos 2 d14 3 d13 4 d12 5 dmo 6 moto/intel 7 rlol 8 d11 9 txframe 10 d10 11 req 12 d9 13 d8 14 vdd 15 d7 16 d6 17 d5 18 d4 19 width16 20 d3 21 encodis 22 d2 23 txlev 24 d1 25 rloop 26 d0 27 lloop 28 int 29 rxlcd 30 gnd 31 cs 32 rd_ds 33 rxgfc 34 wr_rw 35 rxserdata/rxpoh 36 a8 37 rxserclk/rxpohclk 38 a7 39 rxpohframe 40 120 txcelltxed 119 txoh 118 txpohclk 117 txohins 116 txpohins 115 txaisen 114 txserdata/txpoh 113 vdd 112 txlineclk 111 txneg 110 txpohframe 109 txpos 108 txohind/txpframe 107 txframeref 106 rxpoof 105 gnd 104 rxplof 103 txinclk 102 stuffctl 101 rxred 100 rxpred 99 rxlineclk 98 rxneg 97 rxpos 96 rxframe 95 rxohframe 94 rxohind/rxpframe 93 rxohclk 92 rxais 91 gnd 90 rxoof 89 rxoh 88 rxlos 87 8kref 86 rlos 85 tdo 84 tdi 83 tms 82 tck 81 rxuen XRT72L71iq 80 rxuaddr1 79 rxuaddr0 78 vdd 77 rxuaddr2 76 rxuclav 75 rxuaddr3 74 rxuprty 73 rxuaddr4 72 rxusoc 71 gnd 70 rxudata0 69 rxudata8 68 rxudata1 67 rxudata9 66 vdd 65 rxudata10 64 rxudata2 63 rxudata11 62 rxudata3 61 rxudata12 60 rxudata4 59 vdd 58 rxudata5 57 rxudata13 56 rxudata6 55 rxudata14 54 rxudata7 53 rxudata15 52 gnd 51 rxcellrxed 50 rxuclk 49 rxgfcclk 48 a0 47 rxgfcmsb 46 a1 45 a2 44 a3 43 a4 42 a5 41 a6 p art n umber p ackage o perating t emperature r ange XRT72L71iq 160 pqfp -40c to +85c
XRT72L71 ds3 atm uni/clear channel framer ic ? ? ? ? rev. 1.1.0 i table of contents general description ................................................................................................ 1 a pplications .............................................................................................................................. ................ 1 f eatures .............................................................................................................................. ...................... 1 figure 1. XRT72L71 simplified block diagram with system interfaces ............................................................ 1 figure 2. block diagram of the XRT72L71 ds3 uni ............................................................................... ......... 2 figure 3. pin out of the XRT72L71 ds3 atm uni ................................................................................. .......... 3 ordering information ............................................................................................... 3 table of contents ............................................................................................................. ....................... i p in d escriptions ( see figure 3) ............................................................................................................... 4 pin description ........................................................................................................... 4 absolute maximum ratings ................................................................................... 23 dc electrical characteristics .......................................................................... 23 ac electrical characteristics .......................................................................... 23 timing diagrams ...................................................................................................... 28 figure 4. XRT72L71 transmit utopia interface block timing ..................................................................... . 28 figure 5. gfc nibble-field serial input interface (at transmit cell processor) timing ................................. 28 figure 6. transmit plcp processorpoh byte serial input port interface timing ...................................... 29 figure 7. transmit ds3 frameroh bit serial input port interface timing ................................................... 29 figure 8. transmit ds3 framer line interface output timing (txpos and txneg are updated on the rising edge of txlineclk) ............................................................................................................ ............ 30 figure 9. transmit ds3 framer line interface output timing (txpos and txneg are updated on the falling edge of txlineclk) ............................................................................................................ ............ 30 figure 10. receive ds3 frameroh bit serial output port interface timing ............................................... 31 figure 11. receive ds3 framer line interface input signal timing (rxpos and rxneg are sampled on rising edge of rxlineclk) ............................................................................................................. .......... 31 figure 12. receive ds3 framer line interface input signal timing (rxpos and rxneg are sampled on the falling edge of rxlineclk) .................................................................................................... ......... 32 figure 13. receive plcp processorpoh byte serial output port interface timing .................................. 32 figure 14. gfc nibble-field serial output port timing (receive cell processor) ......................................... 33 figure 15. receive utopia interface block timing .............................................................................. ......... 33 figure 16. microprocessor interface timing - intel type programmed i/o read operations ........................ 34 figure 17. microprocessor interface timing - intel type programmed i/o write operations ........................ 34 figure 18. microprocessor interface timingmotorola type processors (read operations) non-burst mode . 35 figure 19. microprocessor interface timingmotorola type processor (write operations) non-burst mode ... 35 figure 20. microprocessor interface timing - reset pulse width ................................................................ ... 35 functional description ......................................................................................... 36 the atm uni mode of operation ......................................................................... 36 the receive section ..................................................................................................... 36 the transmit section .................................................................................................... 37 clear-channel-framing mode of operation .................................................................. 38 the receive section............................................................................................................ ...........................38 the transmit section ........................................................................................................... .........................38 the microprocessor interface section ........................................................................ 39 performance monitor section ...................................................................................... 39 test and diagnostic section ........................................................................................ 39 for atm uni applications ....................................................................................................... ......................39 for clear-channel framing applications......................................................................................... ...39 line interface drive and scan section ........................................................................ 40
? ? ? ? ds3 atm uni/clear channel framer ic XRT72L71 rev. 1.1.0 ii c lear c hannel m ode o peration ........................................................................................................... 40 features ...................................................................................................................... ... 41 transmit and receive sections ................................................................................... 41 utopia interface blocks ....................................................................................................... ............... 41 transmit cell processor block ................................................................................................. ............. 42 receive cell processor block .................................................................................................. ............. 42 transmit plcp processor block ................................................................................................. .......... 42 receive plcp processor block .................................................................................................. .......... 42 transmit/receive ds3 framer block ............................................................................................. ....... 42 microprocessor interface section .............................................................................................. ............ 42 performance monitor section ................................................................................................... ............. 43 test and diagnostic section ................................................................................................... .............. 43 line interface drive and scan section ......................................................................................... ......... 43 list of registers ....................................................................................................... 44 r egister summary l ist .......................................................................................................................... 44 t able 1: uni o perating m ode r egister ...................................................................................................... 46 t able 2: uni i/o c ontrol r egister ............................................................................................................. 47 t able 3: p art n umber r egister ................................................................................................................... 47 t able 4: v ersion n umber r egister ............................................................................................................. 47 t able 5: uni i nterrupt e nable r egister .................................................................................................... 48 t able 6: uni i nterrupt s tatus r egister .................................................................................................... 49 t able 7: t est c ell c ontrol and s tatus r egister ..................................................................................... 50 t able 8: t est c ell e rror a ccumulator h olding r egister ...................................................................... 51 t able 9: t est c ell h eader b yte -1 ............................................................................................................... 51 t able 10: t est c ell h eader b yte -2 ............................................................................................................. 51 t able 11: t est c ell h eader b yte -3 ............................................................................................................. 51 t able 12: t est c ell h eader b yte -4 ............................................................................................................. 51 t able 13: t est c ell e rror a ccumulator - msb ........................................................................................ 52 t able 14: t est c ell e rror a ccumulator - lsb ......................................................................................... 52 t able 15: r x ds3 c onfiguration and s tatus r egister ............................................................................. 53 t able 16: r x ds3 s tatus r egister .............................................................................................................. 54 t able 17: r x ds3 i nterrupt e nable r egister ............................................................................................ 54 t able 18: r x ds3 i nterrupt s tatus r egister ............................................................................................ 55 t able 19: r x ds3 feac r egister ................................................................................................................ 55 t able 20: r x ds3 feac i nterrupt e nable /s tatus r egister .................................................................... 56 t able 21: r x ds3 lapd c ontrol r egister ................................................................................................ 57 t able 22: r x ds3 lapd s tatus r egister ................................................................................................... 58 t able 23: t x ds3 c onfiguration r egister ................................................................................................. 59 t able 24: t x ds3 m-b it m ask r egister ....................................................................................................... 60 t able 25: t x ds3 f-b it m ask 1 r egister ...................................................................................................... 60 t able 26: t x d s 3 f-b it m ask 2 r egister ...................................................................................................... 61 t able 27: t x ds3 f-b it m ask 3 r egister ...................................................................................................... 61 t able 28: t x ds3 f-b it m ask 4 r egister ...................................................................................................... 61 t able 29: t x ds3 feac c onfiguration and s tatus r egister ................................................................... 62 t able 30: t x ds3 feac r egister ................................................................................................................ 62 t able 31: t x ds3 lapd c onfiguration r egister ....................................................................................... 63 t able 32: t x ds3 lapd s tatus /i nterrupt r egister .................................................................................. 64 t able 33: pmon lcv e vent c ount r egister - msb .................................................................................. 64 t able 34: pmon lcv e vent c ount r egister - lsb ................................................................................... 64 t able 35: pmon f raming b it e rror e vent c ount r egister - msb .......................................................... 65 t able 36: pmon f raming b it e rror e vent c ount r egister - lsb ........................................................... 65 t able 37: pmon p-b it e rror c ount r egister - msb ................................................................................ 65 t able 38: pmon p-b it e rror c ount r egister - lsb ................................................................................. 65 t able 39: pmon febe e vent c ount r egister - msb ................................................................................ 65
XRT72L71 ds3 atm uni/clear channel framer ic ? ? ? ? rev. 1.1.0 iii t able 40: pmon febe e vent c ount r egister - lsb ................................................................................. 66 t able 41: pmon plcp bip-8 e rror c ount r egister - msb ..................................................................... 66 t able 42: pmon plcp bip-8 e rror c ount r egister - lsb ...................................................................... 66 t able 43: pmon plcp f raming b yte e rror c ount r egister - msb ........................................................ 66 t able 44: pmon plcp f raming b yte e rror c ount r egister - lsb ......................................................... 67 t able 45: pmon plcp febe c ount r egister - msb ................................................................................. 67 t able 46: pmon plcp febe c ount r egister -lsb ................................................................................... 67 t able 47: pmon s ingle - bit hec e rror c ount - msb ................................................................................ 67 t able 48: pmon s ingle - bit hec e rror c ount - lsb ................................................................................. 68 t able 49: pmon m ultiple - bit hec e rror c ount - msb ............................................................................ 68 t able 50: pmon m ultiple - bit hec e rror c ount - lsb ............................................................................. 68 t able 51: pmon r eceived i dle c ell c ount /prbs e rror c ount - msb ................................................... 68 t able 52: pmon r eceived i dle c ell c ount /prbs e rror c ount - lsb .................................................... 69 t able 53: pmon r eceive v alid c ell c ount - msb ..................................................................................... 69 t able 54: pmon r eceive v alid c ell c ount - lsb ...................................................................................... 69 t able 55: pmon d iscarded c ell c ount - msb ........................................................................................... 69 t able 56: pmon d iscarded c ell c ount - lsb ............................................................................................ 70 t able 57: pmon t ransmit i dle c ell c ount - msb ...................................................................................... 70 t able 58: pmon t ransmit i dle c ell c ount - lsb ....................................................................................... 70 t able 59: pmon t ransmit v alid c ell c ount - msb ................................................................................... 70 t able 60: pmon t ransmit v alid c ell c ount - lsb .................................................................................... 71 t able 61: pmon h olding r egister .............................................................................................................. 71 t able 62: o ne s econd e rror s tatus r egister .......................................................................................... 71 t able 63: lcv - o ne s econd a ccumulator r egister - msb ...................................................................... 71 t able 64: lcv - o ne s econd a ccumulator r egister - lsb ....................................................................... 72 t able 65: p-b it e rrors - o ne s econd a ccumulator r egister - msb ...................................................... 72 t able 66: p-b it e rrors - o ne s econd a ccumulator r egister - lsb ....................................................... 72 t able 67: hec b yte e rrors - o ne s econd a ccumulator r egister - msb .............................................. 72 t able 68: hec b yte e rrors - o ne s econd a ccumulator r egister -lsb ................................................ 72 t able 69: r x plcp c onfiguration /s tatus r egister .................................................................................. 73 t able 70: r x plcp i nterrupt e nable r egister .......................................................................................... 73 t able 71: r x plcp i nterrupt s tatus r egister .......................................................................................... 74 t able 72: f uture u se .............................................................................................................................. ...... 74 t able 73: t x plcp fa1 b yte e rror m ask r egister ................................................................................... 74 t able 74: t x plcp fa2 b yte e rror m ask r egister ................................................................................... 74 t able 75: t x plcp bip-8 e rror m ask ......................................................................................................... 75 t able 76: t x plcp g1 b yte r egister .......................................................................................................... 75 t able 77: r x cp c onfiguration r egister ................................................................................................... 76 t able 78: r x cp a dditional c onfiguration r egister ................................................................................ 77 t able 79: r x cp i nterrupt e nable r egister .............................................................................................. 78 t able 80: r x cp i nterrupt s tatus r egister .............................................................................................. 79 t able 81: r x cp i dle c ell p attern h eader b yte -1 .................................................................................... 79 t able 82: r x cp i dle c ell p attern h eader b yte -2 .................................................................................... 80 t able 83: r x cp i dle c ell p attern h eader b yte -3 .................................................................................... 80 t able 84: r x cp i dle c ell p attern h eader b yte -4 .................................................................................... 80 t able 85: r x cp i dle c ell m ask h eader b yte -1 ......................................................................................... 81 t able 86: r x cp i dle c ell m ask h eader b yte -2 ......................................................................................... 81 t able 87: r x cp i dle c ell m ask h eader b yte -3 ......................................................................................... 82 t able 88: r x cp i dle c ell m ask h eader b yte -4 ......................................................................................... 82 t able 89: r x cp u ser c ell f ilter p attern h eader b yte -1 ...................................................................... 82 t able 90: r x cp u ser c ell f ilter p attern h eader b yte -2 ...................................................................... 83 t able 91: r x cp u ser c ell f ilter p attern h eader b yte -3 ...................................................................... 83 t able 92: r x cp u ser c ell f ilter p attern h eader b yte -4 ...................................................................... 83 t able 93: r x cp u ser c ell f ilter m ask h eader b yte -1 ............................................................................ 83
? ? ? ? ds3 atm uni/clear channel framer ic XRT72L71 rev. 1.1.0 iv t able 94: r x cp u ser f ilter c ell m ask h eader b yte -2 ........................................................................... 84 t able 95: r x cp u ser c ell f ilter m ask h eader b yte -3 ........................................................................... 84 t able 96: r x cp u ser c ell f ilter m ask h eader b yte -4 ........................................................................... 84 t able 97: t x cp c ontrol r egister ............................................................................................................. 85 t able 98: t x cp oam r egister ................................................................................................................... 86 t able 99: t x cp hec e rror m ask r egister .............................................................................................. 86 t able 100: f uture u se .............................................................................................................................. ... 86 t able 101: t x cp i dle c ell p attern h eader b yte -1 .................................................................................. 86 t able 102: t x cp i dle c ell p attern h eader b yte -2 .................................................................................. 87 t able 103: t x cp i dle c ell p attern h eader b yte -3 .................................................................................. 87 t able 104: t x cp i dle c ell p attern h eader b yte -4 .................................................................................. 87 t able 105: t x cp i dle c ell p attern h eader b yte -5 .................................................................................. 87 t able 106: t x cp i dle c ell p ayload r egister ........................................................................................... 87 t able 107: utopia c onfiguration r egister .............................................................................................. 88 t able 108: r x utopia i nterrupt e nable /s tatus r egister ....................................................................... 89 t able 109: r x utopia a ddress ................................................................................................................... 89 t able 110: r x utopia fifo s tatus r egister ............................................................................................ 90 t able 111: t x utopia i nterrupt /s tatus r egister .................................................................................... 91 t able 112: f uture u se .............................................................................................................................. ... 91 t able 113: t x utopia a ddress ................................................................................................................... 92 t able 114: t x utopia s tatus r egister ..................................................................................................... 92 t able 115: l ine i nterface d rive r egister .................................................................................................. 93 t able 116: l ine i nterface s can r egister ................................................................................................... 95 t able 117: pmon cp-b it e rror e vent c ount r egister - msb ................................................................ 96 t able 118: pmon cp-b it e rror e vent c ount r egister - lsb ................................................................. 96 t able 119: f rame cp-b it e rrors - o ne s econd a ccumulator r egister - msb ...................................... 96 t able 120: f rame cp-b it e rrors - o ne s econd a ccumulator r egister - lsb ....................................... 96 t able 121: u nused .............................................................................................................................. .......... 96 package dimensions ................................................................................................. 97 r evision h istory .............................................................................................................................. ....... 98
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 4 pin descriptions (see figure 3) pin description p in n o . s ymbol t ype d escription 1d15i/o msb of bi-directional data bus (microprocessor interface section): this pin, along with pins d0 - d14, function as the microprocessor interface bi-direc- tional data bus, and is intended to be interfaced to the local microprocessor. this pin is inactive if the microprocessor interface block is configured to oper- ate over an 8 bit data bus. 2taos o transmit all ones signal (taos) command (for the xrt7300 liu ic). this output pin is intended to be connected to the taos input pin of the xr- t7300 liu ic. the user can control the state of this output pin by writing a 0 or 1 to bit 4 (taos) within the line interface drive register (address = 0x72). if the user commands this signal to toggle "high" then it will force the xrt7300 ds3 line transmitter ic to transmit an "all ones" pattern onto the line. conversely, if the user commands this output signal to toggle "low" then the xrt7300 ds3 line transmitter ic will proceed to transmit data based upon the pattern that it receives via the txpos and txneg output pins. writing a "1" to bit 4 of the line interface drive register (address = 0x72) will cause this output pin to toggle "high". writing a "0" to this bit-field will cause this output pin to toggle "low". n ote : if the designer is not using the xrt7300 ds3/e3/sts-1 liu ic, then this output pin can be used for other purposes. 3 4 5 d14 d13 d12 i/o bi-directional data bus (microprocessor interface section): this pin is inactive if the microprocessor interface block is configured to operate over an 8 bit data bus. please see description for d15, pin 1. 6dmo i drive monitor output input (from the xrt7300 liu ic): this input pin is intended to be tied to the dmo output pin of the xrt7300 e3/ds3/sts-1 liu ic. the user can determine the state of this input pin by reading bit 2 (dmo) within the line interface scan register (address = 0x73). if this input signal is high, then it means that the drive monitor circuitry (within the xrt7300 liu ic) has not detected any bipolar signals at the mtip and mring inputs within the last 128 32 bit-periods. if this input signal is low, then it means that bipolar signals are being detected at the mtip and mring input pins of the xrt7300. n ote : if the designer is not using the xrt7300 e3/ds3/sts-1 liu ic, then this input pin can be used for other purposes. 7moto/intel i motorola/intel processor interface select mode: this input pin allows the user to configure the microprocessor interface to interface with either a motor- ola-type or intel-type microprocessor/microcontroller. tying this input pin to vdd, configures the microprocessor interface to operate in the motorola mode (e.g., the uni/framer can be readily interfaced to a motorola type local microprocessor). tying this input pin to gnd configures the microprocessor interface to operate in the intel mode (e.g., the uni/framer can be readily inter- faced to an intel type local microprocessor).
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 5 8rlol i receive loss of lock indicatorfrom the xrt7300 e3/ds3/sts-1 liu ic: this input pin is intended to be connected to the rlol (receive loss of lock) output pin of the xrt7300 liu ic. the user can monitor the state of this pin by reading the state of bit 1 (rlol) within the line interface scan register (address = 0x73). if this input pin is low, then it means that the phase-locked- loop circuitry, within the xrt7300 is properly locked onto the incoming ds3 data-stream; and is properly recovering clock and data from this ds3 data- stream. however, if this input pin is high, then it means that the phase- locked-loop circuitry, within the xrt7300 has lost lock with the incoming ds3 data-stream, and is not properly recovering clock and data. for more information on the operation of the xrt7300 e3/ds3/sts-1 liu ic, please consult the "xrt7300 e3/ds3/sts-1 liu ic" data sheet. n ote : if the designer is not using the xrt7300 ds3/e3/sts-1 liu ic, this input pin can be used for other purposes. 9d11i/o bi-directional data bus (microprocessor interface section): this pin is inactive if the microprocessor interface block is configured to operate over an 8-bit wide data bus. please see description for d15, pin 1. 10 txframe o transmit end of ds3 frame indicator: the function of this pin is same in both clear channel and atm uni modes of the XRT72L71. this pin marks the end of each ds3 frame. atm uni mode this pin is pulsed for one ds3 clock period when the transmit input interface is processing the last bit of the given ds3 frame. this just serves as an indica- tion to terminal equpiment in the atm uni mode. clear channel mode when the XRT72L71is configured to operate in the clear-channel framer mode, then the transmit ds3 framer block will pulse this output pin high (for one bit period) when the transmit payload data input interface block is pro- cessing the last bit of a given ds3 frame. the purpose of this output pin is to alert the terminal equipment that it needs to begin transmission of a new ds3 frame to the XRT72L71 (e.g., to permit the XRT72L71 to maintain transmit ds3 framing alignment control over the terminal equipment). 11 d10 i/o bi-directional data bus (microprocessor interface section): this pin is inactive if the microprocessor interface block is configured to operate over an 8 bit data bus. (please see description for d15, pin 1) 12 req o receive equalization bypass control output pin(to be connected to the xrt7300 e3/ds3/sts-1 liu ic): this output pin is intended to be con- nected to the req input pin of the xrt7300 e3/ds3/sts-1 liu ic. the user can control the state of this output pin by writing a 0 or 1 to bit 5 (req ) of the line interface driver register (address = 0x72). if the user commands this signal to toggle high then it will cause the incoming ds3 line signal to by- pass equalization circuitry, within the xrt7300. conversely, if the user com- mands this output signal to toggle low, then the incoming ds3 line signal with be routed through the equalization circuitry. for information on the criteria that should be used when deciding whether to bypass the equalization cir- cuitry or not, please consult the xrt7300 e3/ds3/sts-1 liu ic data sheet. writing a 1 to bit 5 of the line interface drive register (address = 0x72) will cause this output pin to toggle high. writing a 0 to this bit-field will cause this output pin to toggle low. n ote : if the designer is not using the xrt7300 e3/ds3/sts-1 liu ic, then this output pin can be used for other purposes. pin description (continued) p in n o . s ymbol t ype d escription
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 6 13 d9 i/o bi-directional data bus (microprocessor interface section): t his pin is inactive if the microprocessor interface block is configured to operate over an 8 bit data bus. please see description for d15, pin1. 14 d8 i/o bi-directional data bus (microprocessor interface section): this pin is inactive if the microprocessor interface block is configured to operate over an 8 bit data bus. please see description for d15, pin1. 15 vdd *** power supply pin 16 17 18 19 d7 d6 d5 d4 i/o bi-directional data bus (microprocessor interface section): please see description for d15, pin 1. 20 width16 i microprocessor interface block data bus width selector: this input pin permits the user to configure the microprocessor interface of the uni/framer, to operate over either an 8 or 16 bit wide bi-directional data bus. tying this pin to vdd configures the microprocessor interface data bus width to be 16 bits. tying this pin to gnd configures the microprocessor interface data bus width to be 8 bits. 21 d3 i/o bi-directional data bus (microprocessor interface section): please see description for d15, pin 1. 22 encodis o encoder (b3zs) disable output pin (intended to be connected to the xrt7300 e3/ds3/sts-1 liu ic): this output pin is intended to be connected to the encodis input pin of the xrt7300 liu ic. the user can control the state of this output pin by writing a 0 or 1 to bit 3 (encodis) of the line interface driver register (address = 0x72). if the user commands this signal to toggle high then it will disable the b3zs encoder circuitry within the xrt7300 ic. conversely, if the user commands this output signal to toggle low, then the b3zs encoder circuitry, within the xrt7300 ic will be enabled. writing a 1 to bit 3 of the line interface driver register (address = 0x72) will cause this output pin to toggle high. writing a 0 to this bit-field will cause this output pin to toggle low. n otes : 1. the user is advised to disable the b3zs encoder (within the xrt7300 ic) if the transmit and receive ds3 framers (within the uni) are con- figured to operate in the b3zs line code. 2. if the designer is not using the xrt7300 ds3/e3/sts-1 line trans- mitter ic, then output pin can be used for other purposes. 23 d2 i/o bi-directional data bus (microprocessor interface section): please see description for d15, pin1. pin description (continued) p in n o . s ymbol t ype d escription
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 7 24 txlev o transmit line build enable/disable select (to be connected to the txlev input pin of the xrt7300 e3/ds3/sts-1 liu ic): this output pin is intended to be connected to the txlev input pin of the xrt7300 e3/ds3/sts-1 liu ic. the user can control the state of this output pin by writing a 0 or a 1 to bit 2 (txlev) within the line interface driver register (address = 0x72). if the user commands this signal to toggle high then it will disable the trans- mit line build-out circuitry within the xrt7300. in this case, the xrt7300 will output unshaped (square-wave) pulses onto the transmit line signal. in order to insure that the xrt7300 generates a line signal that is compliant with the bellcore gr-499-core pulse template requirements (at the dsx-3 cross-connect), the user is advised to set this output pin high, if the cable length (between the transmit output of the xrt7300 and the dsx-3 cross- connect) is greater than 225 feet. conversely, if the user commands this signal to toggle high, then it will enable the transmit line build-out circuitry within the xrt7300. in this case, the xrt7300 will output shaped pulses onto the transmit line signal. in order to ensure that the xrt7300 generates a line signal that is compliant with the bellcore gr-499-core pulse template requirements (at the dsx-3 cross-connect), the user is advised to set this output pin low, if the cable length (between the transmit output of the xrt7300 and the dsx-3 cross connect) is less than 225 ft. of cable. writing a 1 to bit 2 of the line interface drive register (address = 0x72) will cause this output pin to toggle high. writing a 0 to this bit-field will cause this output pin to toggle low. n ote : if the customer is not using the xrt7300 ds3/e3/sts-1 liu ic, then this output pin can be used for other purposes. 25 d1 i/o bi-directional data bus (microprocessor interface section): please see description for d15, pin1. 26 rloop o remote loop-back output pin (to the xrt7300 ds3/e3/sts-1 liu ic): this output pin is intended to be connected to the rloop input pin of the xrt7300 liu ic. this output pin, along with the lloop input pin (pin 28) per- mits the user to configure the xrt7300 to operate in either of the following three (3) loop-back modes. ? analog local loop-back mode ? digital local loop-back mode ? remote loop-back mode. writing a 1 to bit 1 of the line interface drive register (address = 0x72) will cause this output pin to toggle high. writing a 0 to this bit-field will cause the rloop output to toggle low. n ote : if the customer is not using the xrt7300 ds3/e3/sts-1 ic, then this output pin can be used for other purposes. 27 d0 i/o bi-directional data bus (microprocessor interface section): please see description for d15, pin1. pin description (continued) p in n o . s ymbol t ype d escription
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 8 28 lloop o local loop-back output pin (to the xrt7300 e3/ds3/sts-1 liu ic): this output pin is intended to be connected to the lloop input pin of the xrt7300 liu ic. this input pin, along with rloop (pin 26) permits the user to config- ure the xrt7300 liu ic to operate in either of the following three (3) loop- back modes. ? analog local loop-back mode ? digital local loop-back mode ? remote loop-back mode. writing a 1 to bit 1 of the line interface drive register (address = 0x72) will cause this output pin to toggle high. writing a 0 to this bit-field will cause the rloop output to toggle low. n ote : if the user is not using the xrt7300 ds3/e3/sts-1 liu ic, then this output pin can be used for other purposes. 29 int o interrupt request output: this open-drain, active-low output signal will be asserted when the uni/framer is requesting interrupt service from the local microprocessor. this output pin should typically be connected to the interrupt request input of the local microprocessor. 30 rxlcd o loss of cell delineation indicator: this active-"high" output pin will be asserted whenever the receive cell processor has experienced a loss of cell delineation. this pin will return low once the receive cell processor has regained cell delineation. n ote : this output pin is only active if the XRT72L71 has been configured to operate in the atm uni mode. 31 gnd *** ground pin signal 32 cs i chip select input: this active-low input signal selects the microprocessor interface section of the uni/framer and enables read/write operations between the local microprocessor and the uni/framer on-chip registers and ram locations. 33 rd _ds i read data strobe (intel mode): if the microprocessor interface is operating in the intel mode, then this input will function as the rd (read strobe) input signal from the local m p . once this active-low signal is asserted, then the uni/framer will place the contents of the addressed registers (within the uni/framer ic) on the microprocessor data bus (d[15:0]). when this signal is negated, the data bus will be tri-stated. data strobe (motorola mode): if the microprocessor interface is operating in the motorola mode, then this pin will function as the active-low data strobe signal. 34 rxgfc o receive gfc nibble field serial output pin: this pin, along with the rxg- fcclk and the rxgfcmsb pins form the receive gfc nibble-field serial output port. this pin will serially output the contents of the gfc nibble field of each cell that is processed through the receive cell processor. this data is serially clocked out of this pin on the rising edge of the rxgfcclk signal. the most significant bit (msb) of each gfc value is designated by a pulse at the rxgfcmsb output pin. n ote : this output pin is only active if the XRT72L71 has been configured to operate in the atm uni mode. pin description (continued) p in n o . s ymbol t ype d escription
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 9 35 wr _rw i write data strobe (intel mode): if the microprocessor interface is operating in the intel mode, then this active-low input pin functions as the wr (write strobe) input signal from the m p. once this active-low signal is asserted, then the uni will latch the contents of the m p data bus, into the addressed register (or ram location) within the uni/framer ic. r/w input pin (motorola mode): when the microprocessor interface section is operating in the motorola mode, then this pin is functionally equivalent to the r/w* pin. in the motorola mode, a read operation occurs if this pin is at a logic 1. similarly, a write operation occurs if this pin is at a logic 0. 36 rxserdata/ rxpoh o receive serial output/ receive plcp frame path overhead (poh) byte serial output portoutput pin : the exact functionality of this output pin depends upon whether the XRT72L71 framer ic is operating in the clear channel or atm uni mode. clear channel mode: in clear channel mode, all ds3 data which is received by XRT72L71 will be output as a serial data stream via this pin. the XRT72L71 will output data (via this pin) upon the falling edge of rxserclk. as a consequence, this data should be sampled with the rising edge of rxserclk. atm uni mode: this output pin, along with rxpohclk, rxpohframe, and rxpohins pins comprise the receive plcp frame poh byte serial output port. for each plcp frame that is received by the receive plcp processor, this serial out- put port will output the contents of all 12 poh (path overhead) bytes. the data that is output via this pin, is updated on the rising edge of the rxpohclk output clock signal. the rxpohframe pin will pulse high when the first bit of the z6 byte is being output on this output pin. 37 a8 i address bus input (microprocessor interface)msb (most significant bit): this input pin, along with inputs a0 - a7 are used to select the on-chip uni register and ram space for read/write operations with the local micro- processor. 38 rxserclk/ rxpohclk o clear channel mode receive clock output signal for serial data interface/ receive plcp frame path overhead (poh) byte serial out- put portoutput clock signal : the exact functionality of this output pin depends upon whether the XRT72L71 framer ic is operating in the clear channel or atm uni mode. clear channel mode - rxserclk: in clear channel mode, this pin can be used by the external interface to sam- ple the clear channel serial data stream on rxser pin. the receive section of the XRT72L71 will output all inbound ds3 data, via the rxserdata output pin, upon the rising edge of this output pin. hence, the user should be sam- pling the data (on the rxserdata output pin) upon the rising edge of this clock. atm uni mode - rxpohclk: in the atm uni mode of operation, this pin serves as rxpohclk. this output clock pin, along with rxpoh, rxpohframe pins comprise the 'receive plcp oh serial output' interface. 39 a7 i address bus input (microprocessor interface): please see description for a8, pin 37. pin description (continued) p in n o . s ymbol t ype d escription
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 10 40 rxpohframe o receive plcp frame path overhead (poh) byte serial output port beginning of frame signal pin: this output pin, along with rxpoh, rxpo- hclk, and rxpohins pins comprise the receive plcp frame poh byte serial output port. this output pin provides framing information to external cir- cuitry receiving and processing this poh (path overhead) data, by pulsing high when the first bit of the z6 byte is output via the rxpoh output pin. this pin is low at all other times during this plcp poh framing cycle. n ote : this output pin is only active if the XRT72L71 has been configued to operate in the atm uni mode. 41 42 43 44 45 46 a6 a5 a4 a3 a2 a1 i address bus input (microprocessor interface): please see description for a8, pin 37. 47 rxgfcmsb o received gfc nibble fieldmsb indicator : this output pin functions as a part of the receive gfc-nibble field serial output port; which also consists of the rxgfc and rxgfcclk pins. this pin pulses high the instant that the msb (most significant bit) of a gfc nibble is being output on the rxgfc pin. n ote : this output pin is only active if the XRT72L71 has been configured to operate in the atm uni mode. 48 a0 i address bus input (microprocessor interface)lsb (least significant bit): please see description for a8, pin 37. 49 rxgfcclk o received gfc nibble serial output port clock signal: this output pin functions as a part of the receive gfc nibble-field serial output port; also consisting of the rxgfc and rxgfcmsb pins. this pin provides a clock pulse which allows external circuitry to latch in the gfc nibble-data via the rxgfc output pin. n ote : this output pin is only active if the XRT72L71 has been configured to operate in the atm uni mode. 50 rxuclk i receive utopia interface clock input: the byte (or word) data, on the receive utopia data bus is updated on the rising edge of this signal. the receive utopia interface can be clocked at rates up to 50 mhz. n ote : the user should tie this input pin to gnd whenever the XRT72L71 has been configured to operate in the clear-channel-framer mode. 51 rxcellrxed o receive cell processorcell received indicator: this output pin pulses high each time the receive cell processor receives a new cell from the receive plcp processor or the receive ds3 framer. n ote : this output pin is only active if the XRT72L71 has been configured to operate in the atm uni mode. 52 gnd *** ground pin signal 53 rxudata15 o receive utopia data bus output (msb): this output pin, along with rxudata14 through rxudata0 functions as the receive utopia data bus. atm cell data that has been received from the remote terminal equipment is output on the receive utopia data bus, where it can be read and pro- cessed by the atm layer processor. n ote : this output pin is only active if the XRT72L71 has been configured to operate in the atm uni mode. pin description (continued) p in n o . s ymbol t ype d escription
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 11 54 55 56 57 58 rxudata7 rxudata14 rxudata6 rxudata13 rxudata5 o receive utopia data bus output: please see description of rxudata15, pin 53. n ote : this output pin is only active if the XRT72L71 has been configured to operate in the atm uni mode. 59 vdd *** power supply pin 60 61 62 63 64 65 rxudata4 rxudata12 rxudata3 rxudata11 rxudata2 rxudata10 o receive utopia data bus output: please see description of rxudata15, pin 53. n ote : this output pin is only active if the XRT72L71 has been configured to operate in the atm uni mode. 66 vdd *** power supply pin 67 68 69 rxudata9 rxudata1 rxudata8 o receive utopia data bus output: please see description of rxudata15, pin 53. n ote : this output pin is only active if the XRT72L71 has been configured to operate in the atm uni mode. 70 rxudata0 o receive utopia data bus output - lsb: please see description of rxudata15, pin 53. n ote : this output pin is only active if the XRT72L71 has been configured to operate in the atm uni mode. 71 gnd *** ground signal pin 72 rxusoc o receive utopia interfacestart of cell indicator: this output pin allows the atm layer processor to determine the boundaries or the atm cells that are output via the receive utopia data bus. the receive utopia interface block will assert this signal when the first byte (or word) of a new cell is present on the receive utopia data bus; rxudata[15:0]. n ote : this output pin is only active if the XRT72L71 has been configured to operate in the atm uni mode. 73 rxuaddr4 i receive utopia address bus input (msb): this input pin, along with rxuaddr3 through rxuaddr0 functions as the receive utopia address bus inputs. these input pins are only active when the uni is operating in the multi- phy mode. the receive utopia address bus input is sampled on the rising edge of the rxuclk signal. the contents of this address bus are compared with the value stored in the rx ut address register (address = 6ch). if these two values match, then the uni will inform the atm layer processor on whether or not it has any new atm cells to be read from the rxfifo; by driv- ing the rxuclav output to the appropriate level. if these two address values do not match, then the uni will not respond to the atm layer processor; and will keep its rxuclav output signal tri-stated. n ote : the user should tie this pin to gnd, whenever the XRT72L71 has been configured to operate in the clear-channel-framer mode. 74 rxuprty o receive utopia interfaceparity output pin: the receive utopia interface block will compute the odd-parity of each byte (or word) that will place in the receive utopia data bus. this odd-parity value will be output on this pin, while the corresponding byte (or word) is present on the receive utopia data bus. n ote : this output pin is only active if the XRT72L71 has been configured to operate in the atm uni mode. pin description (continued) p in n o . s ymbol t ype d escription
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 12 75 rxuaddr3 i receive utopia address bus input: please see description for rxuaddr4, pin 73. n ote : the user should tie this pin to gnd whenever the XRT72L71 has been configured to operate in the clear-channel-framer mode. 76 rxuclav o receive utopiacell available: the receive utopia interface block will assert this output pin in order to indicate that the rx fifo has some atm cell data that needs to be read by the atm layer processor. the exact functional- ity of this pin depends upon whether the uni is operating in the octet level or cell level handshake mode. octet level handshaking mode when the receive utopia interface block is operating in the octet-level handshaking mode; this signal is asserted (toggles high) when at least one byte of cell data exists within the rxfifo (within the receive utopia inter- face block). this output pin will toggle low if the rxfifo is depleted of atm cell data. cell level handshaking mode when the receive utopia interface block is operating in the cell-level hand- shaking mode; this signal is asserted if the rxfifo contains at least one full cell of data. this signal will toggle low if the rxfifo is depleted of data, or if it contains less than one full cell of data. multi-phy operation: when the uni chip is operating in the multi-phy mode, this signal will be tri-stated until the rxuclk cycle following the asser- tion of a valid address on the receive utopia address bus input pins (e.g., if the contents on the receive utopia address bus pins match that with the receive utopia address register). afterwards, this output pin will behave in accordance with the cell-level handshake mode. n ote : this output pin is only active if the XRT72L71 has been configured to operate in the atm uni mode. 77 rxuaddr2 i receive utopia address bus input: please see description for rxuaddr4, pin 73. n ote : the user should tie this pin to gnd whenever the XRT72L71 has been configured to operate in the clear-channel-framer mode. 78 vdd **** power supply pin 79 rxuaddr0 i receive utopia address bus input - lsb: please see description for rxuaddr4, pin 73. n ote : the user should tie this pin to gnd whenever the XRT72L71 has been configured to operate in the clear-channel framer mode. 80 rxuaddr1 i receive utopia address bus input: please see description for rxuaddr4, pin 73. n ote : the user should tie this pin to gnd whenever the XRT72L71 has been configured to operate in the clear-channel framer mode. 81 rxuen i receive utopia interfaceoutput enable: this active-low input signal is used to control the drivers of the receive utopia data bus. when this sig- nal is high (negated) then the receive utopia data bus is tri-stated. when this signal is asserted, then the contents of the byte or word that is at the front of the rxfifo will be popped and placed on the receive utopia data bus on the very next rising edge of rxuclk. n ote : the user should tie this pin to gnd whenever the XRT72L71 has been configured to operate in the clear-channel-framer mode. pin description (continued) p in n o . s ymbol t ype d escription
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 13 82 tck i test clock: boundry scan clock input. n ote : this input pin should be pulled low for normal operation. 83 tms i test mode select: boundry scan mode select input. n ote : this input pin should be pulled low for normal operation. 84 tdi i test data in: boundry scan test data input. n ote : this input pin should be pulled low for normal operation. 85 tdo o test data out: boundry scan test data output. 86 rlos i receive los (loss of signal) indicator input (from xrt7300 e3/ds3/ sts-1 line interface unit). this input pin is intended to be connected to the rlos (receive loss of signal) output pin of the xrt7300 e3/ds3 /sts-1 line interface ic. the user can monitor the state of this pin by r eading the state of bit 0 (rlos) within the line interface scan register (address = 73h). if this input pin is low, then it means that the xrt7300 is detecting a sufficient amount of signal energy on the line, due to the incoming ds3 data-stream. how- ever, if this input pin is high, then it means that the xrt7300 is not detecting a sufficient amount of signal energy on the line, due to the incoming ds3 data- stream, and may be experiencing a loss of signal condition. for more information on the operation of the xrt7300 e3/ds3/sts-1 line interface unit ic, please consult the xrt7300 data sheet. n ote : asserting the rlos input pin will cause the XRT72L71 ds3 uni to declare an los (loss of signal) condition. therefore, this input pin should not be used as a general purpose input. 87 8kref i 8 khz reference clock input for the plcp processors: the transmit plcp processor can be configured to synchronize its plcp frame processing to this clock signal. the transmit plcp processor will also use this signal to compute the trailer nibble stuff opportunities. n otes : 1. this input signal is active only if the user has configured the plcp processors to use this signal as their master clock signal. the user can configure the uni to use this signal by setting timrefsel[1,0] (within the uni operating mode register) to 01. 2. the user should tie this pin to gnd whenever the XRT72L71 has been configured to operate in the clear-channel-framer mode. 88 rxlos o receive ds3 framerloss of signal output indicator: this pin is asserted when the receive ds3 framer encounters 180 consecutive 0s via the rxpos and rxneg pins. this pin will be negated once the receive ds3 framer has detected at least 60 1s out of 180 consecutive bits. 89 rxoh o receive overhead output port all overhead bits, which are received via the "receive section" of the framer ic; will be output via this output pin, upon the rising edge of rxohclk. 90 rxoof o receiver ds3 framerout of frame indicator: the receive ds3 framer- block will assert this output signal (e.g., pull it high) whenever it has declared an out of frame (oof) condition with the incoming ds3 frames. this signal is negated when the framer correctly locates the f- and m-bits and regains synchronization with the ds3 frame. 91 gnd *** ground signal pin pin description (continued) p in n o . s ymbol t ype d escription
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 14 92 rxais o receive alarm indication signal output pin: the uni/framer ic will assert this pin to indicate that the alarm indication signal (ais) has been identified in the receive ds3 data stream. an ais is detected if the payload consists of the recurring pattern of 1010... and this pattern persists for 63 m- frames. an additional requirement for ais indication is that the c-bits are set to 0, and the x-bits are set to 1. this pin will be negated when a sufficient number of frames, not exhibiting the 1010... pattern in the payload has been detected. 93 rxohclk o receive overhead output clock signal: this pin serves as the clock signal for external device to sample the overhead data on the rxoh pin. the external interface should use the rising edge of this clock to sample the oh data on rxoh pin. 94 rxohind/ rxpframe o receive overhead bit indicator/plcp frame boundary indicator outputreceive plcp processor. the exact functionality of this output pin depends upon whether the XRT72L71 uni/framer ic is operating in the clear channel or atm uni mode. clear channel mode - rxohind: in clear channel mode, this pin is pulsed high for one bit period whenever an over-head bit is being output via the rxserdata output pin. in other words, the rxserdata output pin will contain an over-head if this pin is sampled high. atm uni mode: this output pin pulses high when the receive plcp processor is receiving the last bit of a given plcp frame. 95 rxohframe o receive overhead frame boundary indicator: this pin is pulsed high for one rxohclk period whenever the first 'x' bit is output on rxoh pin. if external device samples this pin high on the rising edge of rxohclk, the data on rxoh is 'x' bit (first oh bit in the received ds3 frame). 96 rxframe o receive boundary of ds3 frame output indicator: the exact functionality of this output pin depends upon whether the XRT72L71 uni/framer ic is operating in the clear channel or atm uni mode. clear channel mode: in clear channel mode this pin is pulsed high for one ds3 clock period whenever the 'x' bit (first oh bit in the ds3 frame) of the frame is being output on the rxser pin. rxser will contain 'x' bit (first oh bit of ds3 frame) if this pin is sampled high. atm uni mode: in the atm uni mode, this signal indicates the start of the received ds3 frame and is "high" for one ds3 clock period. pin description (continued) p in n o . s ymbol t ype d escription
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 15 97 rxpos i receive positive data input: the exact role of this input pin depends upon whether the uni is operating in the unipolar or bipolar mode. unipolar mode: this input pin functions as the single-rail input for the incoming ds3 data stream. the signal at this input pin will be sampled and latched (into the receive ds3 framer) on the user-selected edge of the rxlineclk signal. bipolar mode: this input functions as one of the dual rail inputs for the incoming ami/b3zs encoded ds3 data that has been received from an exter- nal line interface unit (liu) ic. rxneg functions as the other dual rail input for the uni. when this input pin is asserted, it means that the liu has received a positive polarity pulse from the line. 98 rxneg i receive negative data input: the exact role of this input pin depends upon whether the uni is operating in the unipolar or bipolar mode. unipolar mode: this input pin is inactive, and should be pulled (low or "high") when the uni is operating in the unipolar mode. bipolar mode: this input pin functions as one of the dual rail inputs for the incoming ami/b3zs encoded ds3 data that has been received from an exter- nal line interface unit (liu) ic. rxpos functions as the other dual rail input for the uni. when this input pin is asserted, it means that the liu has received a negative polarity pulse from the line. 99 rxlineclk i receive liu (recovered) clock input: this input signal serves three pur- poses: 1. the receive ds3 framer uses it to sample and latch the signals at the rxpos and rxneg input pins (into the receive ds3 framer circuitry). 2. this input signal functions as the timing reference for the receive framer block. 3. the transmit ds3 framer block can be configured to use this input signal as its timing reference. n ote : note: this signal is the recovered clock from the external ds3 liu (line interface unit) ic, which is derived from the incoming ds3 data. 100 rxpred o receiver red alarm indicatorreceive plcp processor: the uni asserts this output pin to denote that one of the following events has been detected by the receive plcp processor: ? oofout of frame condition ? lofloss of frame condition n ote : this output pin is only active whenever the XRT72L71 has been con- figured to operate in the atm uni mode. 101 rxred o receiver red alarm indicatorreceive ds3 framer: the uni asserts this output pin to denote that one of the following conditions is currently being declared by the receive ds3 framer block: ? losloss of signal condition ? oofout of frame condition ? aisalarm indication signal detection n ote : this output pin is effectively, the wired-or of the rxlos, the rxoof and the rxais output pins. pin description (continued) p in n o . s ymbol t ype d escription
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 16 102 stuffctl i external plcp frame stuff control: this input allows the user to externally exercise or forego trailer nibble stuffing opportunities by the transmit plcp processor. plcp trailer nibble stuff opportunities occur in periods of three plcp frames (375s). the first plcp frame (first within a stuff opportunity period) will have 13 trailer nibbles appended to it. the second plcp frame (second within a stuff opportunity period) will have 14 trailer nibbles appended to it. the third plcp frame (the location of the stuff opportunity) will contain 13 trailer nibbles if the stuffctl input is low and 14 trailer nibbles is the stuffctl input is high. n ote : the user should tie this input pin to gnd whenever the XRT72L71 has been configured to operate in the clear-channel-framer mode. 103 txinclk i transmit ds3 framer blockclock signal: the transmit ds3 framer can be configured to use this input signal as the timing reference. if this input pin is chosen to be the timing reference, then the user must supply a "high" quality 44.736 mhz signal to this input pin. in this configuration, frame generation, by the transmit ds3 framer, will be asynchronous (with any other timing signals within the uni). however, frame timing will be based upon this clock signal. n ote : this input pin should be tied to gnd if it is not used as the transmit ds3 framer timing reference. 104 rxplof o receive plcploss of frame output indicator: the receive plcp processor will assert this pin, when it declares a loss of frame condition. this output will be negated when the receive plcp processor reaches the in frame condition. n ote : this output pin is only active if the user has configured the XRT72L71 to operate in the atm uni mode. 105 gnd *** ground signal pin 106 rxpoof o receive plcp out of frame indicator: the receive plcp processor will assert this pin, when it declares an out of frame condition. this output will be negated when the receive plcp processor reaches the in frame condi- tion. n ote : this output pin is only active if the user has configured the XRT72L71 to operate in the atm uni mode. 107 txframeref i transmit ds3 framerframe reference input pin: the transmit ds3 framer can be configured to use this input signal as the framing reference for the transmit ds3 framer block. if this input pin is chosen to be the timing ref- erence, then any rising edge at this input will cause the transmit ds3 framer to begin its creation a new ds3 m-frame. consequently, the user must supply a clock signal that is equivalent to the ds3 frame rate (or 9398.3 hz). fur- ther, the signal which is driving this input pin, must be synchronized witht he 44.736mhz clock signal, which is applied to the txinclk input pin. n ote : this input pin should be tied to gnd if it is not used as the transmit ds3 framer frame reference signal. pin description (continued) p in n o . s ymbol t ype d escription
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 17 108 txohind/ txpframe o transmit overhead data indicator/transmit plcp frame boundary indi- catoroutput: the exact functionality of this output pin depends upon whether the XRT72L71 framer ic is operating in the clear channel or atm uni mode. clear channel mode: in the clear channel mode, this pin serves as the transmit oh indication for the external interface. this pin is pulsed for one bit period of ds3 clock to indi- cate to the external device that the transmit input interface is going to process oh data at the rising edge of next clock. when the external interface samples txohind as high with the rising edge of ds3 clk; it is expected not to pro- vide useful payload data bit on txser pin. instead it can provide correspond- ing oh data bit on txser input. however, in that case the user has to program a register bit to configure XRT72L71 to accept the oh data from the txser input. otherwise, the oh data will be geaerated internally or be taken from the txoh pin if txohins is high. this pin is pulsed "high" for one bit period prior to all ds3 oh bit positions. atm uni mode: in atm uni mode of operation, this pin functions as transmit plcp frame signal which pulses "high" once for each outbound plcp frame, when the last nibble is being routed. 109 txpos o transmit positive polarity pulse: the exact role of this output pin depends upon whether the uni is operating in the unipolar or bipolar mode. unipolar mode: this output pin functions as the single-rail output signal for the outbound ds3 data stream. the signal, at this output pin, will be updated on the user-selected edge of the txlineclk signal. bipolar mode: this output pin functions as one of the two dual rail output sig- nals that commands the sequence of pulses to be driven on the line. txneg is the other output pin. this input is typically connected to the tpdata input of the external ds3 line interface unit ic. when this output is asserted, it will command the liu to generate a positive polarity pulse on the line. 110 txpohframe o transmit plcp frame path overhead byte serial input portbeginning of frame indicator. this output pin, along with the txpoh, txpohclk, and txpohins pins comprise the transmit plcp frame poh byte insertion serial input port. this particular pin will pulse high when the transmit plcp poh byte insertion serial input port is expecting the first bit of the z6 byte at the txpoh input pin. n ote : this output pin is only active if the XRT72L71 has been configured to operate in the atm uni mode. 111 txneg o transmit negative polarity pulse: the exact role of this output pin depends upon whether the uni is operating in the unipolar or bipolar mode. unipolar mode: this output signal pulses high for one bit period, at the end of each outbound ds3 frame. this output signal is at a logic low for all of the remaining bit-periods of the outbound ds3 frames. bipolar mode: this output pin functions as one of the two dual-rail output sig- nals that commands the sequence of pulses to be driven on the line. txpos is the other output pin. this input is typically connected to the tndata input of the external ds3 line interface unit ic. when this output is asserted, it will command the liu to generate a negative polarity pulse on the line. pin description (continued) p in n o . s ymbol t ype d escription
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 18 112 txlineclk o transmit line interface clock: this clock signal is output to the line interface unit, along with the txpos and txneg signals. the purpose of this output clock signal is to provide the liu with timing information that it can use to gen- erate the ami pulses and deliver them over the transmission medium to the far- end receiver. the user can configure the source of this clock to be either the rxlineclk (from the receiver portion of the uni) or the txiineclk input. the nom- inal frequency of this clock signal is 44.736 mhz. 113 vdd *** power supply pin 114 txserdata/ txpoh i transmit serial payload data input/transmit plcp frame poh byte insertion serial input: the exact functionality of this output pin depends upon whether the XRT72L71 framer ic is operating in the clear channel or atm uni mode. clear channel mode: in clear channel mode, this pin can be used by the external interface to pro- vide the serial input data (payload and oh) that has to be mapped in outgoing ds3 frame. if user want to insert oh data on txser pin then the user should configure the XRT72L71 accordingly. atm uni mode: this input pin becomes active when the user asserts the txpohins input pin. when this happens the user will be permitted to serially input their own value for plcp poh bytes into the outbound plcp frame. this data will be clocked into the uni framer via the txpohclk output signal. this uni will also assert the txpohmsb output pin when it expects the msb (most signifi- cant bit) of the z6 byte (within the plcp frame). 115 txaisen i transmit ais pattern input: when this input pin is pulled high then the transmit ds3 framer block will insert the ais pattern into the ds3 output data stream. 116 txpohins i transmit plcp frame poh data insert enable: this input can be asserted to allow the user to input his/her own value for the plcp poh bytes via the txpoh input pin, in each plcp frame, prior to transmission. if this input pin is not asserted, then the uni will generate its own plcp poh bytes. n ote : the user should tie this input pin to gnd if the XRT72L71 is going to be configured to operate in either the clear-channel-framer mode or in the direct-mapped atm mode. 117 txohins i transmit overhead data insert input: the function of this pin is the same in both clear channel and atm uni modes of the XRT72L71. this pin is used to indicate if the oh bit should be taken from the external interface. the oh data on txoh will be considered by the only if this pin is "high" during oh positions. 118 txpohclk o transmit plcp frame poh byte insertion clock: this pin, along with the txpoh and the txpohmsb input pins, function as the transmit plcp frame poh byte serial input port. this output pin functions as a clock output signal that is used to sample the users poh data at the txpoh input pin. this out- put pin is always active, independent of the state of the txpohins pin. n ote : this output pin is only active if the XRT72L71 has been configured to operate in the atm uni mode. pin description (continued) p in n o . s ymbol t ype d escription
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 19 119 txoh i transmit overhead input pin the transmit overhead data input interface accepts the overhead data via this input pin, and inserts into the "overhead" bit position within the very next "outbound" ds3 frame. if the "txohins" pin is pulled "high", the transmit overhead data input interface will sample the data at this input pin (txoh), on the falling edge of the "txohclk" output pin. conversely, if the "txohins" pin is pulled "low", then the transmit overhead data input interface will not sample the data at this input pin (txoh). consequently, this data will be ignored. 120 txcelltxed o transmit cell processorcell transmitted indicator: this output pin pulses high each time the transmit cell processor transmits a cell to the transmit plcp processor (or transmit ds3 framer). n ote : this output pin is only active if the XRT72L71 has been configured to operate in the atm uni mode. 121 txohclk o transmit overhead clock: the function of this pin is the same in both clear channel and atm uni modes of the XRT72L71. this pin serves as the clock signal for the external interface to insert the oh data on the txoh pin. the user can insert oh data on the txoh pin at the rising edge of this clock signal. 122 txohframe o transmit overhead framing pulse: the function of this pin is same in both clear channel and atm uni modes of XRT72L71. when the external interface samples this pin "high" at the rising edge of txohclk, it should provide 'x' bit (first oh bit within ds3 frame) on the txoh pin. this signal is "high" for one txohclk duration and repeats once for each ds3 frame. 123 txuen i transmit utopia interface blockwrite enable: this active-low signal, from the atm layer processor enables the data on the transmit utopia data bus to be written into the txfifo on the rising edge of txuclk. when this sig- nal is asserted, then the contents of the byte or word that is present, on the transmit utopia data bus, will be latched into the transmit utopia interface block, on the rising edge of txuclk. when this signal is negated, then the transmit utopia data bus inputs will be tri-stated. n ote : the user should tie this input pin to gnd whenever the XRT72L71 has been configured to operate in the clear-channel-framer mode. 124 txusoc i transmitterstart of cell (soc) indicator input: this input pin is driven by the atm layer processor and is used to indicate the start of an atm cell that is being transmitted from the atm layer processor. this input pin must be pulsed high when the first byte (or word) of a new cell is present on the transmit utopia data bus. this input pin must remain low at all other times. n ote : the user should tie this input pin to gnd whenever the XRT72L71 has been configured to operate in the clear-channel-framer mode. 125 txuprty i transmit utopia data busparity input: the atm layer processor will apply the parity value of the byte or word which is being applied to the trans- mit utopia data bus (e.g., txudata[7:0] or txudata[15:0]) inputs of the uni, respectively. note: this parity value should be computed based upon the odd-parity of the data applied at the transmit utopia data bus. the transmit utopia interface block (within the uni) will independently compute an odd- parity value of each byte (or word) that it receives from the atm layer proces- sor and will compare it with the logic level of this input pin. n ote : the user should tie this input pin to gnd whenever the XRT72L71 has been configured to operate in the clear-channel-framer mode. pin description (continued) p in n o . s ymbol t ype d escription
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 20 126 txuclav o transmit utopia interfacecell available output pin: this output pin supports data flow control between the atm layer processor and the transmit utopia interface block. the exact functionality of this pin depends upon whether the uni is operating in the octet level or cell level handshaking mode. octet level handshaking: when the transmit utopia interface block is operating in the octet-level handshaking mode, this signal is negated (toggles low) when the txfifo is not capable of handling four more write operations; by the atm layer processor to the transmit utopia interface block. this sig- nal will be asserted when the txfifo is capable of receiving four or more write operations of atm cell data. cell level handshaking: when the transmit utopia interface block is oper- ating the cell-level handshaking mode, this signal is asserted (toggles high) when the txfifo is capable of receiving at least one more full cell of data from the atm layer processor. this signal is negated, if the txfifo is not capable of receiving one more full cell of data from the atm layer processor. multi-phy operation: when the uni chip is operating in the multi-phy mode, this signal will be tri-stated until the txuclk cycle following the asser- tion of a valid address on the transmit utopia address bus input pins (e.g., when the contents on the transmit utopia address bus pins match that within the transmit utopia address register). afterwards, this output pin will behave in accordance with the cell-level handshake mode. n ote : this output pin is only active if the XRT72L71 has been configured to operate in the atm uni mode. 127 gnd *** ground signal pin. 128 129 130 131 132 133 134 135 txudata8 txudata0 txudata9 txudata1 txudata10 txudata2 txudata11 txudata3 i transmit utopia data bus input: please see description for txudata15, pin 144. n otes : the user should tie this input pin to gnd whenever the XRT72L71 has been configured to operate in the clear-channel-framer mode. txudata0 - transmit utopia data bus input - lsb. 136 vdd *** power supply pin 137 138 139 140 141 142 143 txudata4 txudata12 txudata5 txudata13 txudata6 txudata14 txudata7 i transmit utopia data bus input: please see description for txudata15 pin 144. n ote : the user should tie this input pin to gnd whenever the XRT72L71 has been configured to operate in the clear-channel-framer mode. 144 txudata15 i transmit utopia data bus inputmsb: this input pin, along with txudata14 through txudata0 comprise the transmit utopia data bus input pins. when the atm layer processor wishes to transmit atm cell data through the XRT72L71 ds3 uni, it must place this data on these pins. the data, on the transmit utopia data bus is latched into the transmit utopia interface block on the rising edge of txuclk. n ote : the user should tie this input pin to gnd whenever the XRT72L71 has been configured to operate in the clear-channel-framer mode. 145 vdd *** power supply pin pin description (continued) p in n o . s ymbol t ype d escription
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 21 146 txuaddr4 i transmit utopia address busmsb input: this input pin, along with txuaddr3 through txuaddr0 comprise the transmit utopia address bus input pins. the transmit utopia address bus is only in use when the uni is operating in the m-phy mode. when the atm layer processor wishes to write data to a particular uni device, it will provide the address of the intended uni on the transmit utopia address bus. the contents of the transmit utopia address bus input pins are sampled on the rising edge of txuclk. the ds3 uni will compare the data on the transmit utopia address bus with the pre-programmed contents of the txut address register (address = 70h). if these two values are identical and the txuen pin is asserted, then the txu- clav pin will be driven to the appropriate state (based upon the txfifo fill level) for the cell level handshake mode of operation. n ote : the user should tie this input pin to gnd whenever the XRT72L71 has been configured to operate in either the clear-channel-framer mode or in the single-phy mode. 147 txuaddr0 i transmit utopia address bus inputlsb: (see description for txuaddr4 pin 146). n ote : the user should tie this input pin to gnd whenever the XRT72L71 has been configured to operate in either the clear-channel-framer mode or in the single-phy mode. 148 149 150 txuaddr3 txuaddr1 txuaddr2 i transmit utopia address bus input: please see description for txuaddr4, pin 146. n ote : the user should tie this input pin to gnd whenever the XRT72L71 has been configured to operate in either the clear-channel-framer mode or in the single-phy mode. 151 txuclk i transmit utopia interface clock: the transmit utopia interface clock is used to latch the data on the transmit utopia data bus, into the transmit utopia interface block. this clock signal is also used as the timing source for circuitry used to process the atm cell data into and through the txfifo. during multi-phy operation, the data on the transmit utopia address bus pins is sampled on the rising edge of txuclk. n ote : the user should tie this input pin to gnd whenever the XRT72L71 has been configured to operate in the clear-channel-framer mode. 152 gnd *** ground signal pin 153 testmode *** factory test mode pin n ote : the user should tie this pin to ground. 154 txgfcmsb o transmit gfc nibble-field serial input portmsb indicator: this signal, along with txgfc and txgfcclk combine to function as the transmit gfc nibble field serial input port. this output signal will pulse high when the msb (most significant bit) of the gfc nibble (for a given cell) is expected at the txgfc input pin. n ote : this output pin is only active whenever the XRT72L71 has been con- figured to operate in the atm uni mode. 155 reset i reset input: when this active-low signal is asserted, the uni framer will be asynchronously reset. additionally, all outputs will be tri-stated, and all on-chip registers will be reset to their default values. pin description (continued) p in n o . s ymbol t ype d escription
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 22 156 txgfcclk o transmit gfc nibble field serial input port clock: this signal, along with txgfc, and txgfcmsb combine to function as the transmit gfc nibble- field serial input port. the transmit gfc nibble-field serial input port uses this output clock signal to sample the values applied to the txgfc pin, on its rising edge. this pin will provide four rising edges for each cell being transmit- ted. n ote : this output pin is only active whenever the XRT72L71 has been con- figured to operate in the atm uni mode. 157 ale_as i address latch enable/address strobe: this input is used to latch the address (present at the microprocessor interface address bus, a[8:0]) into the uni microprocessor interface circuitry and to indicate the start of a read/ write cycle. this input is active-"high" in the intel mode (moto = low) and active-low in the motorola mode (moto = high). 158 txgfc i transmit gfc nibble-field serial input port: this signal, along with txg- fcclk and txgfcmsb combine to function as the transmit gfc nibble- field serial input port. the user will specify the value of the gfc field, within a given atm cell, by serial transmitting its four bit value into this input. each of these four bits will be clocked into the uni via rising edge of the txgfcclk clock output signal. n ote : the user should tie this input pin to gnd whenever the XRT72L71 has been configured to operate in the clear-channel-framer mode. 159 gnd *** ground signal pin 160 rdy_dtck o ready or dtack: this active-low output pin will function as the ready output, when the microprocessor interface is running in the intel mode; and will function as the dtack output, when the microprocessor interface is running in the motorola mode. intel modeready output. when the uni negates this output pin (e.g., toggles it low), it indicates (to the m p) that the current read or write cycle is to be extended until this signal is asserted (e.g., toggled high). motorola mode:dtack (data transfer acknowledge) output. the uni framer will assert this pin in order to inform the local microprocessor that the present read or write cycle is nearly complete. if the uni framer requires that the current read or write cycle be extended, then the uni will delay its assertion of this signal. the 68000 family of m ps requires this signal from its peripheral devices, in order to quickly and properly complete a read or write cycle. pin description (continued) p in n o . s ymbol t ype d escription
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 23 absolute maximum ratings power supply....................................-0.5v to +3.6v power dissipation tqfp package ...........................1.2w storage temperature.......................-65 c to 150c input voltage (any pin)........................-0.5v to vdd + 5v voltage at any pin...........................-0.5v to vdd + 5 v input current (any pin).......................................+ 100ma dc electrical characteristics test conditions: t a = 25c, vdd = 3.3v 5% unless otherwise specified s ymbol p arameter m in .t yp .m ax .u nits c onditions i cc power supply current 120 ma txuclk and rxuclk are operating at 25mhz v il input low voltage 0.8 v v ih input high voltage 2.0 vdd v v ol output low voltage 0.0 0.4 v v oh output high voltage 2.4 vdd v i oc = 1.6ma i ih input high voltage current -10 10 a v ih = vdd i il input low voltage current -10 10 a v il = gnd ac electrical characteristics test conditions: t a = 25c, vdd = 3.3v 5% unless otherwise specified s ymbol p arameter m in .t yp .m ax .u nits c onditions transmit utopia interface block (see figure 4) t 1 txudata[15:0] to rising edge of txu- clk setup time 4ns t 2 txudata[15:0] hold time from rising edge of txuclk 1ns t 3 txutopia write enable setup time to rising edge of txuclk 4ns t 4 txutopia write enable hold time from rising edge of txuclk 1ns t 5 txuprty setup time to rising edge of txuclk 4ns t 6 txuprty hold time from rising edge of txuclk 1ns t 7 txusoc setup time to rising edge of txuclk 4ns t 8 txusoc hold time from rising edge of txuclk 1ns
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 24 t 9 txuaddr[4:0] setup time to rising edge of txuclk 4ns t 10 txuaddr[4:0] hold time from rising edge of txuclk 1ns t 11 txuclav signal valid (not hi-z) from first txuclk rising edge of valid and correct txuaddr[4:0] 616ns t 12 txuclav signal hi-z from first txuclk rising edge of different txuaddr[4:0] 919ns transmit cell processor (gfc serial input port)see figure 5 t 13 clock period of txgfcclk 232 ns there will be a periodic clock gap every six clocks. ftxgfcclk frequency of txgfcclk 5.592 mhz t 14 delay from rising edge of txgfcclk to rising edge of txgfcmsb pin 1.43 ns t 15 pulse width of txgfcmsb signal 232 ns t 16 txgfc data setup time to rising edge of txgfcclk 7ns t 17 txgfc data hold time from rising edge of txgfcclk 3ns transmit plcp processor (serial input port)see figure 6 t 18 clock period of txpohclk signal 232 ns periodically gapped t 19 delay from rising edge of txpohframe signal to rising edge of txpohclk signal 90 113 ns >0.5 t 18 t 20 txpoh setup time to rising edge of txpohclk signal 11 ns t 21 txpoh signal hold time from rising edge of txpohclk signal 3ns t 22 txpohins signal setup time to rising edge of txpohclk 11 ns t 23 txpohins signal hold time from rising edge of txpohclk 3ns transmit ds3 framer (serial input port)see figure 7 ftxohclk frequency of txohclk signal 526.3 khz t 24 period of txohclk clock signal 1900 ns 44.736mhz/85 t 25 delay from rising edge of txohframe signal to rising edge of txohclk signal 950 970 ns >0.5 t 24 t 26 txoh data setup time to rising edge of txohclk signal 11 ns ac electrical characteristics (continued) test conditions: t a = 25c, vdd = 3.3v 5% unless otherwise specified s ymbol p arameter m in .t yp .m ax .u nits c onditions
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 25 t 27 txoh data hold time from rising edge of txohclk signal 0ns t 28 txohins signal setup time to rising edge of txohclk 11 ns t 29 txohins signal hold time from rising edge of txohclk 0ns transmit ds3 framer (liu interface port)see figure 8 and figure 9 t 30 delay time of data on txpos or txneg, following the rising edge of the txlineclk 0.7 2.0 ns transmit ds3 framer is config- ured to update txpos and txneg on the rising edge of txlineclk. t 31 delay time of data on txpos or txneg following the falling edge of the txlineclk 0.7 1.5 ns transmit ds3 framer is config- ured to update txpos and txneg on the falling edge of txlineclk. ftxlineclk clock frequency of txlineclk 44.736 mhz t 32 period of txlineclk clock signal 10 ns t 33 bit period of data on txpos or txneg pins 10 ns receive ds3 framer (serial output port)see figure 10 frxohclk frequency of rxohclk signal 526.3 khz t 34 period of rxohclk clock signal 1900 ns t 35 delay time from rising edge of rxohclk to rxohframe signal 950 970 ns >0.5 t 34 t 36 delay time from rising edge of rxohclk to valid data at rxoh 950 970 ns >0.5 t 34 t 37 bit period of data at rxoh 1900 ns receive ds3 framer (liu interface port)see figure 11 and figure 12 t 38 rxpos/rxneg data setup time to rising edge of rxlineclk 6ns receive ds3 framer is configured to sample rxpos and rxneg on the rising edge of rxlineclk. t 39 rxpos/rxneg data hold time from rising edge of rxlineclk 3ns receive ds3 framer is configured to sample rxpos and rxneg on the rising edge of rxlineclk. t 40 rxpos/rxneg data setup time to falling edge of rxlineclk 6ns receive ds3 framer is configured to sample rxpos and rxneg on the falling edge of rxlineclk. t 41 rxpos/rxneg data hold time from falling edge of rxlineclk 3 ns receive ds3 framer is configured to sample rxpos and rxneg on the falling edge of rxlineclk. frxlineclk clock frequency of rxlineclk 44.736 mhz t 42 period of rxlineclk clock signal 10 ns ac electrical characteristics (continued) test conditions: t a = 25c, vdd = 3.3v 5% unless otherwise specified s ymbol p arameter m in .t yp .m ax .u nits c onditions
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 26 receive plcp processor (serial output port)see figure 13 t 43 clock period of rxpohclk signal 232 ns t 44 delay from rising edge of rxpohclk signal to rising edge of rxpohframe signal. 61.4ns t 45 delay from rising edge of rxpohclk to data valid at rxpoh output 310ns t 46 bit period of data at rxpoh output signal 232 ns 1 rxpohclk pulse width receive cell processor (gfc serial output port)see figure 14 t 47 clock period of rxgfcclk 232 ns t 48 delay from rising edge of rxgfcclk to rising edge of rxgfcmsb pin. 0.06 1.4 ns t 49 pulse width of rxgfcmsb signal 232 ns t 50 delay from rising edge of rxgfcmsb signal to first valid bit at rxgfc. 0ns t 51 delay from rising edge of rxgfcclk to valid bit at rxgfc. 0.9 2.4 ns t 52 pulse width of bit at rxgfc output. 232 ns receive utopia interface block -- see figure 15 t 53 delay time from rising edge of rxuclk to data valid at rxudata[15:0] 19.916ns t 54 rx utopia read enable setup time to rising edge of rxuclk 4ns t 55 delay time from rising edge of rxuclk to valid rxuprty bit 11016ns t 56 delay time from rising edge of rxuclk to valid rxusoc bit 19.916ns t 57 delay time from read enable false to data bus being tri-stated 111.516ns t 58 delay time from read enable false to rxuprty bit being tri-stated 11216ns t 59 delay time from read enable false to rxusoc bit being tri-stated 111.516ns t 60 rxuaddr[4:0] setup time to rising edge of rxuclk 4ns t 61 rxuaddr[4:0] hold time from rising edge of rxuclk 1ns t 62 rxuclav signal valid (not hi-z) from first rxuclk rising edge of valid and correct txuaddr[4:0] 17.816ns ac electrical characteristics (continued) test conditions: t a = 25c, vdd = 3.3v 5% unless otherwise specified s ymbol p arameter m in .t yp .m ax .u nits c onditions
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 27 t 63 rxuclav signal hi-z from first rxuclk rising edge of different rxuaddr[4:0]. 19.216ns microprocessor interfaceintel -- see figure 16 and figure 17 t 64 a8a0 setup time to ale_as low 3 ns t 65 a8a0 hold time from ale_as low. 2 ns t 66 rd _ds, wr _rw pulse width 30 ns intel type read operations -- see figure 16 t 67 data valid from rd _ds low. 6 11 ns t 68 data bus floating from rd _ds high. 10 ns t 69 ale to rd time 4 ns t 70 rd time to :not ready (e.g., rdy_dtck toggling low) 15 23 ns intel type write operations -- see figure 17 t 71 data setup time to wr _rw high 4 ns t 72 data hold time from wr _rw high 2 ns t 73 high time between reads and/or writes 20 ns t 74 ale to wr time 4 ns t 770 cs assertion to falling edge of wr _rw 20 ns microprocessor interfacemotorola read operations -- see figure 18 t 78 a8a0 setup time to falling edge of ale_as 5ns t 79 a8a0 rising edge of rd _ds to rising edge of rdy_dtck 0ns t 80 rising edge of rdy_dtck to tri-state of d[7:0] 0ns microprocessor interfacewrite operations -- see figure 19 t 78 a8a0 setup time to falling edge of ale_as 5ns t 81 d[7:0] setup time to falling edge of rd _ds 10 ns t 82 rising edge of rd _ds to rising edge of rdy_dtck delay 0ns reset pulse widthboth motorola and intel operations -- see figure 20 t 90 reset pulse width 30 ac electrical characteristics (continued) test conditions: t a = 25c, vdd = 3.3v 5% unless otherwise specified s ymbol p arameter m in .t yp .m ax .u nits c onditions
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer ic rev. 1.1.0 preliminary 28 timing diagrams f igure 4. XRT72L71 t ransmit utopia i nterface b lock t iming txudata[15:0] txuen txuprty txusoc txuaddr[4:0] txuclav txuclk t1 t3 t2 t5 t7 t6 t8 t4 t9 t10 t11 t12 f igure 5. gfc n ibble -f ield s erial i nput i nterface ( at t ransmit c ell p rocessor ) t iming txgfcclk txgfcmsb t14 txgfc t16 bit 3 bit 2 bit 1 bit 0 t17 t13 t15
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer ic rev. 1.1.0 29 f igure 6. t ransmit plcp p rocessor poh b yte s erial i nput p ort i nterface t iming txpohframe txpoh txpohins txpohclk t19 t20 t21 t23 t22 t18 f igure 7. t ransmit ds3 f ramer oh b it s erial i nput p ort i nterface t iming txohframe txoh txohins txohclk t25 t26 t27 t29 t28 t24
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer ic rev. 1.1.0 preliminary 30 f igure 8. t ransmit ds3 f ramer l ine i nterface o utput t iming (t x pos and t x neg are updated on the rising edge of t x l ine c lk ) f igure 9. t ransmit ds3 f ramer l ine i nterface o utput t iming (t x pos and t x neg are updated on the falling edge of t x l ine c lk ) txneg txpos txlineclk t 32 t 33 t 30 txneg txpos txlineclk t 32 t 33 t 31
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer ic rev. 1.1.0 31 f igure 10. r eceive ds3 f ramer oh b it s erial o utput p ort i nterface t iming rxoh rxohframe rxohclk t 34 t 37 t 35 f1 x1 f1 aic f0 t 36 f igure 11. r eceive ds3 f ramer l ine i nterface i nput s ignal t iming (r x pos and r x neg are sampled on rising edge of r x l ine c lk ) rxneg rxpos rxlineclk t 42 t 39 t 38
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer ic rev. 1.1.0 preliminary 32 f igure 12. r eceive ds3 f ramer l ine i nterface i nput s ignal t iming (r x pos and r x neg are sampled on the falling edge of r x l ine c lk ) rxneg rxpos rxlineclk t 42 t 41 t 40 f igure 13. r eceive plcp p rocessor poh b yte s erial o utput p ort i nterface t iming rxpoh rxpohframe rxpohclk t 43 t 46 t 44 t 45
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer ic rev. 1.1.0 33 f igure 14. gfc n ibble -f ield s erial o utput p ort t iming (r eceive c ell p rocessor ) rxgfc rxgfcmsb rxgfcclk t 52 t 48 t 50 t 47 bit 3 bit 2 bit 1 bit 0 t 51 t 49 f igure 15. r eceive utopia i nterface b lock t iming t 53 data valid address of another uni valid address address of another uni t 61 t 60 t 56 t 62 t 55 t 58 t 54 t 57 t 63 t 59 rxuclk rxuaddr[4:0] rxuclav rxusoc rxuprty rxuen rxudata[15:0]
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer ic rev. 1.1.0 preliminary 34 f igure 16. m icroprocessor i nterface t iming - i ntel t ype p rogrammed i/o r ead o perations t 64 t 66 t 70 t 69 ale_as t 68 t 65 t 67 wr_rw rdy_dtck rd_ds d[15:0] cs a[8:0] address of target not valid valid f igure 17. m icroprocessor i nterface t iming - i ntel t ype p rogrammed i/o w rite o perations t 64 t 66 t 770 ale_as t 72 t 65 t 71 t 73 wr_rw rd_ds d[15:0] cs a[8:0] address of target data to be written t 74
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer ic rev. 1.1.0 35 f igure 18. m icroprocessor i nterface t iming m otorola t ype p rocessors (r ead o perations ) n on -b urst m ode wr_rw ale_as rd_ds a[8:0] cs d[7:0] rdy_dtck not valid valid data address of target register t78 t79 t80 f igure 19. m icroprocessor i nterface t iming m otorola t ype p rocessor (w rite o perations ) n on -b urst m ode t78 ale_as a[8:0] cs d[7:0] rd_ds rdy_dtck data to be written address of target register wr_rw t82 t81 f igure 20. m icroprocessor i nterface t iming - r eset p ulse w idth reset t90
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 36 functional description the XRT72L71 ds3 atm uni/framer ic can be con- figured to operate in either the atm uni or in the clear-channel-framer mode. a brief listing of the features and description for each of these operating modes is presented below. the atm uni mode of operation when the XRT72L71 uni/framer has been config- ured to operate in the atm uni mode, it can func- tionally be subdivided into 6 different sections, as shown in figure 2. ? receive section ? transmit section ? microprocessor interface section ? performance monitor section ? test and diagnostic section ? line interface unit scan drive section the features of each of these functional sections are briefly outlined below. the receive section the purpose of the receive section of the XRT72L71 ds3 atm uni is to allow a local atm layer (or atm adaptation layer) processor to receive atm cell data from a remote piece of equipment via a public or leased ds3 transport medium. the receive section of the XRT72L71 ds3 uni con- sists of the following functional blocks. ? receive ds3 framer block ? receive plcp (physical layer convergence proto- col) processor block ? receive cell processor block ? receive utopia interface block each of these functional blocks, within the receive section of the uni framer will do the following: the rx ds3 framer block ? capable of receiving data, from the liu ic, in either the single-rail or dual-rail mode. ? capable of sampling the inbound ds3 data (at the rxpos and rxneg input pins) upon either the rising or falling edge of the rxlineclk signal. ? the receive ds3 framer will synchronize to the incoming ds3 data stream and remove or process the ds3 framing/overhead bits. this procedure will result in either extracting plcp frame data or direct-mapped atm cell data, from the payload portion of the incoming ds3 data stream. ? the receive ds3 framer can be used to receive feac (far end alarm & control) messages via an on-chip feac transceiver. ? the receive ds3 framer includes an on-chip lapd receiver along with 88 bytes of on-chip ram that can receive incoming path maintenance data link messages from the remote terminal equip- ment. ? detects and generates interrupts upon detection of p and cp-bit errors, change of state in los, ais, oof and ferf, receipt of new lapd (pmdl) message, validation and removal of feac message. n ote : the receive ds3 framer supports both m13 and c- bit parity frame formats. the rx plcp processor block ? the receive plcp processor will identify the frame boundary of each incoming plcp frame, extract and process the overhead bytes of these plcp frames (applies only if the uni is operating in the plcp mode). the receive plcp processor will also perform some error checking on the incoming plcp frames. the receive plcp processor will inform the remote terminal equipment of the results of this error-checking by internally routing these results to the near-end transmit plcp pro- cessor, for transmission back out to the remoteter- minal equipment. the rx cell processor block ? the receive cell processor will perform the follow- ing functions: C cell delineation C hec byte verification of incoming cells (optional) C cell-payload de-scrambling (optional) C idle cell detection and removal (optional) C user and oam cell filtering (optional) C oam cell processing (optional) ? the uni provides 108 bytes of on-chip ram that allows for the reception and processing of selected oam cells. ? the receive cell processor block will also verify the crc-10 value within all received oam cells, per itu-t i.610.
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 37 ? detects and generates interrupts upon detection of hec byte errors, change in lcd (loss of cell delineation) condition and receipt of oam cell. the receive utopia interface block ? provides a utopia level -2 compliant interface to either the atm or the atm adaptation layer. ? can be configured to operate in either the single- phy or multi-phy modes. ? supports either cell-level or octet-level hand- shaking. ? receive utopia data bus can be configured to be either 8 or 16-bits wide. ? the rxfifo, within the receive utopia interface block will temporarily hold any atm cells that pass through the receive cell processor, where they can be read out by the atm layer processor, over the receive utopia data bus. ? the size of the rxfifo is 16 cells. ? supports read operations (from the atm layer device) at rates upto 50mhz. ? detects and generates interrupts upon detection of runt cells and overrun of rxfifo. the transmit section the purpose of the transmit section of the XRT72L71 ds3 atm uni is to allow a local atm layer (or atm adaptation layer) processor to transmit atm cell da- ta to a remote piece of equipment via a public or leased ds3 transport medium. the transmit section of the XRT72L71 ds3 uni con- sists of the following functional blocks. ? transmit utopia interface block ? transmit cell processor block ? transmit plcp processor block ? transmit ds3 framer block each of these functional blocks, within the transmit section (of the uni/framer) will do the following: transmit utopia interface block ? can be configured to operate in either the single- phy or multi-phy mode. ? supports either the cell-level or octet-level handshaking mode. ? transmit utopia data bus can be configured to be either 8 or 16-bits wide. ? allow the atm layer processor to write atm cells into the transmit fifo (within the transmit utopia interface block) via a standard utopia level 2 interface. ? the size of the txfifo is 16 cells. however, the operating depth can be configured to be 4, 8, 12 or 16 cells. ? supports write operations (from the atm layer device) at rates upto 50mhz. ? detects and generates interrupts upon detection of parity errors, detection of runt cells and overrun of txfifo. transmit cell processor block ? the transmit cell processor will read in atm cells from the transmit fifo (if available) for further processing. ? if no cell is available within the transmit fifo, then the transmit cell processor will automatically gen- erate an idle cell. the uni is equipped with on-chip registers to allow for the generation of customized idle cells. ? the uni provides 54 bytes of on-chip ram that allows for the generation and transmission of user- specified oam cells. the transmit cell processor will generate and transmit these oam cells upon software command. ? the transmit cell processor block will also com- pute and insert a crc-10 value into each out- bound oam cell, per itu-t i.610. ? the transmit cell processor will (optionally) scramble the cell payload bytes and (optionally) compute and insert the hec (header error check) byte. this hec byte will be inserted into the fifth octet of each cell prior to being transferred to the transmit plcp processor (or the transmit ds3 framer). transmit plcp processor block ? the transmit plcp processor will pack 12 atm cells into each plcp frame and automatically determine the nibble-stuffing option of the current plcp frame. these plcp frames will also include an overhead byte that reflect bip-8 (bit interleaved parity) calcula- tion results, a byte that reflects the current stuffing option status of the current plcp frame, path over- head and identifier bytes, and diagnostic-related bytes reflecting any detected bip-8 errors and alarm conditions detected in the receive section of the uni chip. transmit ds3 framer block ? these plcp frames (or direct mapped atm cells) will be inserted into the payload of an outgoing ds3 frame, for transmission to the remote terminal, by the transmit ds3 framer. ? the transmit ds3 framer will transmit feac (far end alarm & control) messages to the remote ter- minal equipment via an on-chip feac transceiver.
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 38 ? additionally, the transmit ds3 framer can transmit path maintenance data link messages to the remote terminal equipment via the on-chip lapd transmitter. ? generates interrupts upon completion of trans- mission of lapd and feac messages. note: the transmit ds3 framer will support either m13 or c-bit parity framing formats. clear-channel-framing mode of opera- tion when the XRT72L71has been configured to operate in the clear-channel framer mode, it can be func- tionally subdivided into 6 different sections. ? receive section ? transmit section ? microprocessor interface section ? performance monitor section ? test and diagnostic section ? line interface unit scan/drive section. the features of each of the receive and transmit section (for clear-channel framer applications) are listed below. the receive section the purpose of the receive section of the XRT72L71 clear-channel ds3 framer is to allow a given termi- nal to receive data from a remote terminal, which is being transported over a ds3 data stream. the receive section of the XRT72L71 clear-channel ds3 framer ic consists of the following functional blocks. ? receive ds3 framer block ? receive overhead data output interface block ? receive payload data output interface block it should be noted that the receive ds3 framer block is also active, when the XRT72L71 has been configured to operate in the atm uni mode. each of these functional blocks, within the receive section of the framer will do the following. ? the receive ds3 framer block will synchronize to the incoming ds3 data stream. all inbound ds3 data will be routed to the receive payload data output interface block. all overhead bits (which are extracted from each inbound ds3 frame) will be routed to the receive overhead data output interface block. ? the receive ds3 framer block can also be used to receive feac (far-end-alarm & control) mes- sages and pmdl (path maintenance data link) messages via the on-chip receive hdlc control- ler block. ? the receive overhead output interface block out- puts all overhead bits, which have been received via the inbound ds3 data stream. the purpose of the receive overhead output interface block is to permit external circuitry (within the local terminal equipment) to have access to these overhead bits, for additional processing. ? the receive payload data output interface block outputs all data bits which have been received via the XRT72L71, to the local terminal equipment. since the receive payload data output interface block outputs both payload and overhead data bits, to the local terminal equipment; the receive payload data output interface block also includes an overhead indicator output pin. this output pin pulses high whenever an overhead bit is being output via the receive payload data output inter- face block. the transmit section the purpose of the transmit section of the XRT72L71 clear-channel ds3 framer is to allow a local terminal to transmit data to a remote terminal equipment, via a ds3 transport medium. the transmit section of the XRT72L71 clear-chan- nel ds3 framer consists of the following functional blocks. ? transmit payload data input interface block ? transmit overhead data input interface block ? transmit ds3 framer block it should be noted that the transmit ds3 framer block is also active, whenever the XRT72L71 has been configured to operate in the atm uni mode. the transmit section of the clear-channel ds3 framer will: ? accept all user data, (which is required to be transported to the remote terminal equipment via a ds3 data stream) via the transmit payload data input interface block. ? optionally accepts and insert overhead bits (into the outbound ds3 data-stream) via the transmit overhead input interface block. ? the transmit ds3 framer block will accept payload data (from the transmit payload data input inter- face block) and overhead data (from the transmit overhead data input interface block) and will cre- ate a ds3 data stream. if no overhead data is inserted via the transmit overhead data input interface block, then the transmit ds3 framer block will insert its own values for the overhead bits.
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 39 ? the transmit ds3 framer block will transmit feac (far-end-alarm & control) messages to the remote terminal equipment via an on-chip feac trans- mitter. ? the transmit ds3 framer block will also transmit pmdl (path maintenance data link) messages to the remote terminal equipment via an on-chip lapd transmitter. the microprocessor interface section the microprocessor interface section allows a user (or a local housekeeping processor) to do the following: ? to configure the uni/framer ic into a wide variety of operating modes; by writing data into any one of a large number of read/write registers. ? to monitor many aspects of the uni/framers perfor- mance by reading data from any one of a large num- ber of read/write and read-only registers. ? to run in a polling or interrupt-driven environment. the uni/framer ic contains an extensive interrupt structure consisting of a wide range of interrupt enable and interrupt status registers. ? to command the uni/framer ic to transmit oam cells, feac messages and/or lapd messages frames, upon software command. ? to read in and process received oam cells, feac messages and/or path maintenance data link messages from the uni/framer ic. ? the microprocessor interface allows the user to interface the XRT72L71 ds3 uni/framer to either an intel type or motorola type processor. addition- ally, the microprocessor interface can be configured to operate over an 8-bit or 16-bit data bus. ? the microprocessor interface section includes a loss of clock signal protection feature that auto- matically completes (or terminates) a read/write operation, should a loss of clock signal event occur. performance monitor section the performance monitor section of the XRT72L71 ds3 uni/framer consists of a large number of re- set-upon-read and read-only registers that con- tains cumulative and one-second statistics that re- flect the performance/health of the uni/framer chip/ system. these cumulative and one-second statis- tics are kept on the following parameters. ? number of line code violation events detected by the receive ds3 framer ? number of framing bit (f- and m-bit) errors detected by the receive ds3 framer ? number of p-bit errors detected by the receive ds3 framer ? number of cp-bit errors detected by the receive ds3 framer. ? number of febe events detected by the receive ds3 framer ? cumulative number of bip-8 errors, detected by the receive plcp processor ? number of plcp framing errors, detected by the receive plcp processor ? cumulative sum of the febe value, in the incoming g1 bytes (within each plcp frame), received by the receive plcp processor ? number of single-bit hec byte errors detected ? number of multi-bit hec byte errors detected ? number of received idle cells ? number of received valid (user and oam) cells discarded ? number of discarded cells ? number of transmitted idle cells ? number of transmitted valid cells test and diagnostic section the test and diagnostic section allows the user to perform a series of tests in order to verify proper func- tionality of the uni/framer chip and/or the users sys- tem. the test and diagnostic section provides the uni ic with the following capabilities. ? allows the uni/framer to operate in the line, cell, and plcp loop-back modes. for atm uni applications ? contains an internal test cell generator and an internal test cell receiver. the test cell generator will generate test cells with user-defined header byte patterns. the test cell generator will also fill the payload portion of these test cells with bytes from an on-chip prbs generator. ? the test cell generator can generate test cells in one shot mode (e.g., a burst of 1024 test cells) or in continuous mode (e.g., a continuous stream of test cells). ? the test cell receiver will identify and collect the test cells for further analyses, based upon the user-defined header byte patterns. additionally, the test cell receiver will report the occurrence of any errors by incrementing an on-chip register. for clear-channel framing applications ? contains an internal prbs pattern generator and receiver. the prbs pattern generator will generate
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 40 and insert a prbs pattern into the ds3 payload bits. ? the prbs receiver will receive these ds3 frames, and will attempt to acquire prbs lock with this ds3 frame data. additionally, the prbs receiver will report the occurrence of any errors by incre- menting an on-chip register. line interface drive and scan section the line interface drive and scan section allows the user to monitor and control many aspects of the xrt7300 e3/ds3/sts-1 line interface unit, via on- chip registers, within the uni ic. this feature elimi- nates the need for glue logic to interface the XRT72L71 ds3 uni/framer to the xrt7300 ds3 line interface unit ic. ? the on-chip line interface drive register allows the user to control the state of 6 output pins. the function of these output pins, when asserted, are tabulated below. clear channel mode operation signal name function of output pin req receive equalizer by-pass: 1 configures the xrt7300 to shut off its internal receive equalizer. 0 configures the xrt7300 to enable its internal receive equalizer. tao s transmit all ones pattern. 1 configures the xrt7300 liu ic to overwrite the ds3 data that is output via the txpos and out- puts, and transmit an all ones pattern onto the line. 0 configures the xrt7300 liu ic to transmit data, as is applied to it via the tpdata and tndata input pins. encodis b3zs encoder disable/enable select. "1" disables the b3zs encoder, within the xrt7300. "0" enables the b3zs decoder within the xrt7300. txlev transmit output signal line build out select. setting this bit-field to 1 disables the transmit line build out circuitry within the xrt7300. in this case, the xrt7300 will generate an unshaped square wave signal out onto the line (via the ttip and tring output pins). note: in order to configure the xrt7300 to generate a line signal that complies with the transmit output pulse template requirements (per bellcore gr-499-core), this setting is advised if the cable length between the transmit output of the xrt7300 and the dsx-3 cross-connect is greater than 225 feet. setting this bit-field to 0 enables the transmit line build out circuitry within the xrt7300. in this case, the xrt7300 will generate a shaped square wave out onto the line (via the ttip and tring output pins). note: in order to configure the xrt7300 to generate a line signal that complies with the transmit output pulse template requirements (per bellcore gr-499-core), this setting is advised if the cable length between the transmit output of the xrt7300 and the dsx-3 cross-connect is less than 225 feet.
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 41 ? the on-chip line interface scan register allows the user to monitor the state of 3 input pins. the function of these input pins, when asserted, are tabulated below. features transmit and receive sections utopia i nterface b locks ? compliant with utopia level 2 interface specifica- tion (e.g., supports single-phy or multi-phy opera- tion). ? 8-bit or 16-bit wide utopia data bus operation in the transmit and receive directions. ? the utopia data bus runs at clock rates of 25 mhz, 33 mhz and 50 mhz ? supports both octet-level and cell-level hand- shaking between the uni and the atm layer pro- cessor. ? the transmit utopia interface block performs par- ity checking of atm cell data that is written into it, by the atm layer processor. will optionally discard errored cells. ? contains on-chip 16 cell fifo in the transmit direc- tion (txfifo) ? the txfifo can be configured to operate with depths of 4, 8, 12 or 16 cells ? contains on-chip 16 cell fifo in the receive direction (rxfifo) rloop remote loop-back mode select: this bit-field, along with lloop can be used to configure the xrt7300 into one of four different loop- back modes. setting rloop to 1 (with lloop = 0) configures the xrt7300 to operate in the remote loop-back mode. setting rloop to 1 (with lloop = 1) configures the xrt7300 to operate in the digital local loop- back mode. setting rloop to 0 (with lloop = 1) configures the xrt7300 to operate in the analog local loop- back mode. setting rloop to 0 (with lloop = 0) configures the xrt7300 to operate in the normal (no-loop- back) mode. lloop local loop-back mode select: this bit-field along with rloop can be used to configure the xrt7300 into one of four different loop- back modes. setting lloop to 1 (with rloop = 0) configures the xrt7300 to operate in the analog local loop- back mode. setting lloop to 1 (with rloop = 1) configures the xrt7300 to operate in the digital local loop- back mode. setting lloop to 0 (with rloop = 0) configures the xrt7300 to operate in the normal (no-loop- back) mode. setting lloop to 0 (with rloop = 1) configures the xrt7300 to operate in the remote loop-back mode. signal name function of output pin s ignal n ame f unction of i nput p in if asserted dmo indicates that the "drive monitor" circuitry within the xrt7300 has not detected any bipolar signals within the last 128 32 bit periods. rlol indicates that the "clock recovery" circuit, within the xrt7300 has lost "lock" with the incoming ds3 line signal. rlos indicates that the xrt7300 is declaring an los (loss of signal) condition.
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 42 t ransmit c ell p rocessor b lock ? optionally computes and inserts hec byte into all cells (user, oam and idle). ? optionally scrambles the payload of each cell. ? idle cells are automatically generated when no user cells are available in the txfifo. ? uni contains on-chip registers that support the generation/transmission of default or custom idle cells. ? uni contains the on-chip transmit oam cell buffer (54 bytes) that allows the user to write in and store the contents of oam cells, in preparation for trans- mission. ? oam cells are transmitted upon software command. ? performs data path integrity check on all incoming cell data, originating from the atm layer processor. ? provides a serial input port to allow the user to insert the gfc (generic flow control) field exter- nally into the gfc nibble field of an outbound (e.g., transmit direction) valid atm cell. r eceive c ell p rocessor b lock ? performs cell delineation on either direct mapped atm cell data or plcp frames. ? verifies the hec bytes of incoming cells and cor- rects most cells with single bit errors. cells with multi-bit errors are detected and are optionally dis- carded. ? (optionally) performs filtering of idle cells. ? (optionally) performs filtering of user and oam cells. ? uni contains on-chip buffer space (receive oam cell buffer) that allows for the reception and pro- cessing of selected oam cells. ? optionally de-scrambles the payload of each cell. ? provides a serial output port that allows the user to read the gfc value of an incoming (e.g., receive direction) atm cell. ? inserts the data path integrity check patterns in all cells that are written to the rxfifo. t ransmit plcp p rocessor b lock ? can be disabled to support the direct mapped atm mode. ? packs 12 atm cells into each plcp frame along with various other overhead bytes. ? the transmit plcp processor will automatically determine its own stuffing options. ? overhead bytes include those that support bip-8 calculations (b1), indicator of stuff-option status for current plcp frame (c1), diagnostic byte that reflects alarms conditions that were detected in the receive section of the uni (g1); and path over- head bytes. ? provides a serial input port for user to insert plcp overhead bytes externally. r eceive plcp p rocessor b lock ? can be disabled to support the direct mapped atm mode. ? determines the frame boundaries of incoming plcp frames (from the receive ds3 framer). ? extracts and processes the plcp frame overhead bytes. ? provides a serial output port for user to read in the contents of the plcp overhead bytes from the incoming data. t ransmit /r eceive ds3 f ramer b lock ? supports the m13 and c-bit parity framing formats. ? transmit and receive ds3 framers can transmit/ receive data in the unipolar or the bipolar (ami or b3zs line codes) format. ? the transmit ds3 framer provides a serial input port that allows the user to insert his/her own values for the overhead bits of the outbound ds3 frames. ? the receive ds3 framer provides a serial output port that allows the user access to the values of the overhead bits of the incoming ds3 frames. ? the receive ds3 framer can be configured to sample the incoming ds3 data (at the rxpos and rxneg input pins) via the rising edge or falling edge of the receive line clock (rxlineclk) input. ? the transmit ds3 framer can be configured to update the outbound ds3 data (at the txpos and txneg output pins) at the rising edge or falling edge of the transmit line clock (txlineclk) output. ? uni includes on-chip ram space to support the trans- mission and reception of path maintenance data link messages via an on-chip lapd transceiver ? uni includes on-chip registers to support the trans- mission and reception of feac (far end alarm & control) messages via an on-chip feac transceiver. ? contains on-chip feac transceiver. ? contains on-chip lapd transceiver. m icroprocessor i nterface s ection ? can be interfaced to motorola or intel type of micro- processors/microcontrollers
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 43 ? microprocessor interface supports 8 bit wide or 16- bit wide read/write accesses. ? supports polled or interrupt-driven environments. ? supports burst mode read and write operations between the local microprocessor and the uni on- chip registers and ram locations. ? includes a loss of clock signal protection feature that terminates read/write cycles with the local m p, during a loss of clock signal event. p erformance m onitor s ection contains numerous on-chip read-only registers that allows the user to monitor the overall health of the system. t est and d iagnostic s ection ? supports line, plcp, and cell loop-back modes ? supports line-side testing ? contains an on-chip test cell generator and an on- chip test cell receiver ? test cell generator can generate a continuous stream of test cells, or a one-shot burst of 1024 test cells. ? the test cell receiver identifies, collects and eval- uates test cells for errors. ? the test cell receiver also reports the occurrence of errors to the user. l ine i nterface d rive and s can s ection ? consists of an on-chip read/write register that allows the user to control the state of 6 output pins. consists of an on-chip read-only register that al- lows the user to monitor the state of 3 input pins.
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 44 list of registers all even numbered registers get mapped onto the mi- croprocessor data bus higher byte d15-d8 all odd numbered registers get mapped onto the mi- croprocessor data bus lower byte d7-d0 register summary list even numbered register odd numbered register d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 r eg . # f unction 0 uni operating mode register 1 uni i/o control register 2 part number register 3 version number register 4 uni interrupt enable register 5 uni interrupt status register 6 test cell control and status register 7 test cell error accumulator holding register 8 test cell header byte-1 9 test cell header byte-2 10 test cell header byte-3 11 test cell header byte-4 12 test cell error accumulator-msb 13 test cell error accumulator-lsb 14 rx ds3 configuration and status register 15 rx ds3 status register 16 rx ds3 interrupt enable register 17 rx ds3 interrupt status register 18 rx ds3 feac register 19 rx ds3 feac interrupt enable/status register 20 rx ds3 lapd control register 21 rx ds3 lapd status register 22 tx ds3 configuration register 23 tx ds3 m-bit mask register 24 tx ds3 f-bit mask1 register 25 tx ds3 f-bit mask2 register 26 tx ds3 f-bit mask3 register 27 tx ds3 f-bit mask4 register 28 tx ds3 feac configuration and status register 29 tx ds3 feac register 30 tx ds3 lapd configuration register 31 tx ds3 lapd status/interrupt register 32 pmon lcv event count register-msb 33 pmon lcv event count register-lsb 34 pmon framing bit error event count register-msb 35 pmon framing bit error event count register-lsb 36 pmon p-bit error count register-msb 37 pmon p-bit error count register-lsb 38 pmon febe event count register-msb 39 pmon febe event count register-lsb 40 pmon plcp bip-8 error count register-msb 41 pmon plcp bip-8 error count register-lsb 42 pmon plcp framing byte error count register- msb 43 pmon plcp framing byte error count register- lsb 44 pmon plcp febe count register-msb 45 pmon plcp febe error count register-lsb 46 pmon single-bit hec error count-msb 47 pmon single-bit hec error count -lsb 48 pmon multiple-bit hec error count-msb 49 pmon multiple-bit hec error count-lsb 50 pmon received idle cell count/prbs error count- msb 51 pmon received idle cell count/prbs error count- lsb 52 pmon receive valid cell count-msb 53 pmon receive valid cell count-lsb 54 pmon discarded cell count-msb 55 pmon discarded cell count-lsb 56 pmon transmit idle cell count-msb r eg . # f unction
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 45 57 pmon transmit idle cell count-lsb 58 pmon transmit valid cell count-msb 59 pmon transmit valid cell count-lsb 60 pmon holding register 61 one second error status register 62 lcv - one second accumulator register-msb 63 lcv - one second accumulator register-lsb 64 p-bit errors-one second accumulator register-msb 65 p-bit errors-one second accumulator register- lsb 66 hec byte errors-one sec accumulator register- msb 67 hec byte errors-one sec accumulator register- lsb 68 rx plcp configuration/status register 69 rx plcp interrupt enable register 70 rx plcp interrupt status register 71 future use 72 tx plcp fa1 byte error mask register 73 tx plcp fa2 byte error mask register 74 tx plcp bip-8 error mask 75 tx plcp g1 byte register 76 rx cp configuration register 77 rx cp additional configuration register 78 rx cp interrupt enable register 79 rx cp interrupt status register 80 rx cp idle cell pattern header byte-1 81 rx cp idle cell pattern header byte-2 82 rx cp idle cell pattern header byte-3 83 rx cp idle cell pattern header byte-4 84 rx cp idle cell mask header byte-1 85 rx cp idle cell mask header byte-2 86 rx cp idle cell mask header byte-3 87 rx cp idle cell mask header byte-4 88 rx cp user cell filter pattern header byte-1 89 rx cp user cell filter pattern header byte-2 90 rx cp user cell filter pattern header byte-3 r eg . # f unction 91 rx cp user cell filter pattern header byte-4 92 rx cp user cell filter mask header byte-1 93 rx cp user cell filter mask header byte-2 94 rx cp user cell filter mask header byte-3 95 rx cp user cell filter mask header byte-4 96 tx cp control register 97 tx cp oam register 98 tx cp hec error mask register 99 future use 100 tx cp idle cell pattern header byte-1 101 tx cp idle cell pattern header byte-2 102 tx cp idle cell pattern header byte-3 103 tx cp idle cell pattern header byte-4 104 tx cp idle cell pattern header byte-5 105 tx cp idle cell payload register 106 utopia configuration register 107 rx utopia interrupt enable/status register 108 rx utopia address 109 rx utopia fifo status register 110 tx utopia interrupt/status register 111 future use 112 tx utopia address 113 tx utopia status register 114 line interface drive register 115 line interface scan register 116 pmon cp-bit error event count register - msb 117 pmon cp-bit error event count register - lsb 118 frame cp-bit errors-one second accumulator reg- ister - msb 119 frame cp-bit errors-one second accumulator reg- ister - lsb 120-133 unused r eg . # f unction
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 46 t able 1: uni o perating m ode r egister r egister 0 uni o perating m ode r egister h ex a ddress : 0 x 00 b it f unction t ype d efault d escription -o peration 7 local loop-back r/w 0 0: local loop-back mode operation is disabled 1: local loop-back mode operation is enabled. the transmit stream on txpos, txneg pins are looped back into the receive rxpos, rxneg pins 6 cell loop-back r/w 0 0: cell loop-back mode operation is disabled 1: cell loop-back mode operation is enabled. cells from the receive cell pro- cessor block are written into the tx fifo. n ote : this bit-field is only active if the XRT72L71 is operating in the atm uni mode. 5 plcp loop-back r/w 0 0: plcp loop-back mode operation is disabled 1: plcp loop-back mode operation is enabled. plcp frames are looped from the transmit plcp processor block into the receive plcp processor block. n ote : this bit-field is only active if the XRT72L71 is operating in the atm uni/ plcp mode. 4 reset r/w 0 0: normal operation 1: a 0 to 1 transition causes a reset of the uni/framer device. 3 direct-mapped atm r/w 1 0: plcp mode is enabled. transmit and receive plcp processor blocks are enabled. 1: direct-mapped atm mode. transmit and receive plcp processor blocks are disabled. n ote : this bit-field is only active if the XRT72L71 is operating in the atm uni mode. 2 c-bit/m13 r/w 0 0: XRT72L71 will support the ds3/c-bit parity framing format. 1: XRT72L71 will support the ds3/m13 framing format. 1 timing reference select (1) r/w 1 plcp block 00: transmitter timings taken from the receive plcp processor (loop-timing). 01: 8 khz reference signal on 8kref pin used for stuffing and framing 10: stuffctl is used for stuffing control, framing is asynchronous on power on 11: fixed stuffing pattern is used. framing is asynchronous on power on framer block 00: transmitter timings are taken from the receive ds3 framer (loop-timing) 01: framing is asynchronous on power-on, and txinclk is used as the transmit clock 10: transmitter follows external pin (txframeref) framing reference 11: framin is asynchronous on power-on, and txinclk is used as the transmit clock 0 timing reference select (0) r/w 1
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 47 t able 2: uni i/o c ontrol r egister r egister 1 uni i/o c ontrol r egister h ex a ddress :0 x 01 b it f unction t ype d efault d escription -o peration 7 disable loc r/w 1 0: internal loss of clock detection circuit enabled 1: internal loss of clock detection circuit disabled 6loc ro 0 0: indicates no loss of clock 1: indicates txlnclk or rxlinelck is not present. bit is valid only if disable loc is 0 5 interrupt enable reset r/q 1 0: interrupt enable register bits are not reset by the chip when active interrupts are read. 1: reading of status of an active interrupt resets the corresponding interrupt enable bit. 4 b3zs*/ami r/w 0 0: b3zs encoding and decoding is enabled. 1: b3zs encoding and decoding are disabled. n ote : dual-rail data must be selected (via bit 3 of this register) if b3zs encoding/decoding are enabled. 3 single-rail /dual- rail r/w 0 0: dual-rail data is transmitted and received between the XRT72L71 and the liu ic. 1: single-rail data is transmitted and received between the XRT72L71 and the liu ic. 2 tx clock invert r/w 0 0: outputs on txpos, txneg are updated on rising edge of txclk 1: ouputs on txpos, txneg are updated on falling edge of txclk 1 rx clock invert r/w 0 0: inputs on rxpos, rxneg are sampled at rising edge of rxclk 1: inputs on rxpos, rxneg are sampled at falling edge of rxclk 0 reframe r/w 0 0 to 1 transition forces the receive ds3 framer block to start frame search t able 3: p art n umber r egister r egister 2 p art n umber r egister h ex a ddress : 0 x 02 b it f unction t ype d efault d escription -o peration 7-0 part number ro 0x04 hex: 0x04 (0000 0100) t able 4: v ersion n umber r egister r egister 3 v ersion n umber r egister h ex a ddress : 0 x 03 b it f unction t ype d efault d escription -o peration 0-7 version number ro 0x01 hex 0x04: (0000 0001)
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 48 t able 5: uni i nterrupt e nable r egister r egister 4 uni i nterrupt e nable r egister h ex a ddress 0 x 04 b it f unction t ype d efault d escription -o peration 7 rx ds3 interrupt enable r/w 0 0: receive ds3 framer block interrupts are disabled 1: receive ds3 framer interrupts are enabled (at the block level) 6 rx plcp interrupt enable r/w 0 0: receive plcp processor block interrupts are disabled 1: receive plcp processor block interrupts enabled (at the block level) n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni/plcp modes. 5 rx cp interrupt enable r/w 0 0: receive cell processor block interrupts are disabled 1: receive cell processor block interrupts are enabled (at the block level) n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode. 4 rx utopia inter- rupt enable r/w 0 0: receive utopia interface block interrupts are disabled 1: receive utopia interface block interrupts are enabled (at the block level) n ote : t his bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode. 3 tx utopia inter- rupt enable r/w 0 0: transmit utopia interface block interrupts are disabled 1: transmit utopia interface block interrupts are enabled (at the block level) n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode. 2 tx cp interrupt enable r/w 0 0: transmit cell processor interrupts are disabled 1: transmit cell processor interrupts are enabled (at the block level). n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode . 1 tx ds3 interrupt enable r/w 0 0: transmit ds3 framer block interrupts are disabled 1: transmit ds3 framer block interrupts are enabled (at the block level). 0 one sec interrupt enable r/w 0 0: one second interrupt disabled 1: one second interrupt enabled
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 49 t able 6: uni i nterrupt s tatus r egister r egister 5 uni i nterrupt s tatus r egister h ex a ddress : 0 x 05 b it f unction t ype d efault d escription -o peration 7 rx ds3 interrupt status ro 0 0: no pending interrupt from the receive ds3 framer block 1: pending interrupt(s) from the receive ds3 framer block are awaiting ser- vice. 6 rx plcp interupt status ro 0 0: no pending interrupt from the receive plcp processor block 1: pending interrupt(s) from the receive plcp processor block are awaiting service. n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni/plcp modes. 5 rx cp interrupt status ro 0 0: no pending interrupt from the receive cell processor block. 1: pending interrupt(s) from the receive cell processor block are awaiting service. n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode. 4 rx utopia interrupt sta- tus ro 0 0: no pending interrupt from the receive utopia interface block. 1: pending interrupt(s) from receive utopia interface block are awaiting service. n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode. 3 tx utopia interrupt sta- tus ro 0 0: no pending interrupt from the transmit utopia interface block. 1: pending interrupt(s) from the transmit utopia interface block are await- ing service. n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode. 2 tx cp interrupt status ro 0 0: no pending interrupt from the transmit cell processor block 1: pending interrupt from the transmit cell processor block is awaiting ser- vice. n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode. 1 tx ds3 interrupt status ro 0 0: no pending interrupt from the transmit ds3 framer block 1: pending interrupt(s) from the transmit ds3 framer block are awaiting ser- vice. 0 one sec interrupt status rur 0 0: no pending interrupt requests from the one second pulse generator 1: pending one second interrupt is awaiting service.
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 50 t able 7: t est c ell c ontrol and s tatus r egister r egister 6 t est c ell c ontrol and s tatus r egister h ex a ddress : 0 x 06 b it f unction t ype d efault d escription -o peration 7 clear channel enable r/w 0 0: configures the XRT72L71 to operate in the atm uni mode. 1: configures the XRT72L71 to operate in the clear channel mode 6 tx overheard extracted data input r/w 0 0: transmit payload data interface does not accept overhead bits via the txserdata input pin 1: transmit payload data input interface block accepts overhead bits via the txserdata input pin. n ote : this register is only active if the XRT72L71 has been configured to operate in the atm uni mode. 5unused ro 0 4 test cell enable/ prbs enable r/w 0 if the XRT72L71 has been configured to operate in the atm uni mode: 0: disables the test cell generator and receiver 1: enables the test cell generator and receiver. the test cell generator will begin generating an inserting test cell into the outbound ds3 data stream. the test cell receiver will begin to look for test cells, and acquire a prbs pattern with the payload bytes of these test cells. if the XRT72L71 has beenconfigured to operate in the clear channel framer mode: 0: disables the prbs generator and receiver 1: enables the prbs generator and receiver. the prbs generator will begin to insert a prbs pattern into the outbound ds3 data strream. the prbs receiver will begin to look for this prbs pattern and acquire prbs lock 3 reserved r/w 0 this bit-field is unused 2 one-shot test r/w 0 o: continous mode - test cells are generated as long as the test cell enable bit is high 1: burst mode - 0 to 1 transition in the test cell enable bit results in the generation of 1024 test cells. n ote : this register is only active if the XRT72L71 has been configured to operate in the atm uni mode. 1 one shot done ro 0 0: test cell generator is currently generating its burst of 1024 test cells. 1: test cell generator has completed generating its latest burst of 1024 test cells. this bit-field is reset when a new cycle is begun by a 0 to 1 tran- sition within the test cell enable bit-field. n ote : this bit-field is only active if both of the following conditions are true. 1. the XRT72L71 has been configured to operate in the atm uni mode 2. the test cell generator/receiver has been configured to operate in the burst mode. 0 prbs lock ro 0 0: the test cell receiver (for atm uni applications or the prbs receiver (for clear-channel framer applications) has not yet acquired pattern lock with the prbs data bening generated by the test cell generator/prbs generator. 1: the test cell receiver/prbs receiver has been able to acquire pattern lock with the prbs data being generated by the test cell generator. n ote : once the test cell receiver/prbs receiver has acquired prbs lock, then it will begin to record pattern bit error events within the test cell error count (or prbs error count) registers.
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 51 t able 8: t est c ell e rror a ccumulator h olding r egister r egister 7 t est c ell e rror a ccumulator h olding r egister h ex a ddress : 0 x 07 b it f unction t ype d efault d escription -o peration 7-0 test cell holding register ro 0x00 holds the unread byte of the 16-bit test cell error accumulator, when that register is read. the XRT72L71 will transfer the contents of the unread byte to this holding register, anytime the bidirectional data bus (of the microprocessor interface) is configured to be 8-bits wide. n ote : this register is only active if the XRT72L71 has been configured to operate in the atm uni mode. t able 9: t est c ell h eader b yte -1 r egister 8 t est c ell h eader b yte -1 h ex a ddress : 0 x 08 b it f unction t ype d efault d escription -o peration 7-0 test cell header byte 1 r/w 0x11 test cell header byte - 1 permits the user to define the value of header byte # 1 within each test cell which is generated by the test cell generator. n ote : this register is only active if the XRT72L71 has been configured to operate in the atm uni mode. t able 10: t est c ell h eader b yte -2 r egister 9 t est c ell h eader b yte -2 h ex a ddress : 0 x 09 b it f unction t ype d efault d escription -o peration 7-0 test cell header byte 2 r/w 0x22 test cell header byte - 2 permits the user to define the value of header byte # 2 within each test cell which is generated by the test cell generator. n ote : this register is only active if the XRT72L71 has been configured to operate in the atm uni mode. t able 11: t est c ell h eader b yte -3 r egister 10 t est c ell h eader b yte -3 h ex a ddress : 0 x 0a b it f unction t ype d efault d escription -o peration 7-0 test cell header byte 3 r/w 0x33 test cell header byte - 3 permits the user to define the value of header byte # 3 within each test cell which is generated by the test cell generator. n ote : this register is only active if the XRT72L71 has been configured to operate in the atm uni mode. t able 12: t est c ell h eader b yte -4 r egister 11 t est c ell h eader b yte -4 h ex a ddress : 0 x 0b b it f unction t ype d efault d escription -o peration 7-0 test cell header byte 4 r/w 0x44 test cell header byte - 4 permits the user to define the value of header byte # 4 within each test cell which is generated by the test cell generator. n ote : this register is only active if the XRT72L71 has been configured to operate in the atm uni mode.
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 52 t able 13: t est c ell e rror a ccumulator - msb r egister 12 t est c ell e rror a ccumulator - msb h ex a ddress : 0 x 0c b it f unction t ype d efault d escription -o peration 7-0 test cell error - msb rur 0x00 test cell accumulator register - msb this register, along with test cell error - lsb contains the number of bit errors accumulated since the last read of these registers. this particular register contains the most significant byte value of the total number of test cell errors. n ote : this register is only active if the XRT72L71 has been configured to operate in the atm uni mode. t able 14: t est c ell e rror a ccumulator - lsb r egister 13 t est c ell e rror a ccumulator - lsb h ex a ddress : 0 x 0d b it f unction t ype d efault d escription -o peration 7-0 test cell error - lsb rur 0x00 test cell accumulator register - lsb this register, along with test cell error - msb contains the number of bit errors accumulated since the last read of these registers. this particular register contains the least significant byte value of the total number of test cell errors. n ote : this register is only active if the XRT72L71 has been configured to operate in the atm uni mode.
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 53 t able 15: r x ds3 c onfiguration and s tatus r egister r egister 14 r x ds3 c onfiguration and s tatus r egister h ex a ddress : 0 x 0e b it f unction t ype d efault d escription -o peration 7rx ais ro 0 receive ais alarm indicator: 0: indicates that the receive ds3 framer block is not detecting the ais (alarm indication signal) pattern, within the inbound ds3 data stream. 1: indicates that the receive ds3 framer block is currently detecting the ais pattern within the inbound ds3 data stream. 6rx los ro 0 receive los alarm indicator: 0: indicates that the receive ds3 framer block is not currently declaring an los (loss of signal) condition. 1: indicates that the receive ds3 framer block is currently declaring an los (loss of signal) condition. 5 rx idle ro 0 receive idle pattern indicator: 0: indicates that the receive ds3 framer block is not currently detecting the idle pattern, within the inbound ds3 data stream. 1: indicates that the receive ds3 framer block is currently detecting the idle pattern within the inbound ds3 data stream. 4 rx oof ro 1 receive oof (out of frame) alarm indicator: 0: indicates that the receive ds3 framer block is not currently declaring the oof (out of frame) condition. 1: indicates that the receive ds3 framer block is currently declaring the oof (out of frame) condition. 3 internal los disable r/w 0 0: on chip los detector is disabled. the XRT72L71 will only declare los (loss of signal) is the rlos input pin is pulled high. 1: on chip los detected is enabled. the XRT72L71 will declare and clear los based upon the absence of a certain number of pulses in the incoming ds3 data stream. 2 framing on parity r/w 0 framing on-parity (in-frame declaration criteria): 0: receive ds3 framer block declares the inframe condition after f-bit and m-bit synchronization have been achieved. p-bit checking is not a part of frame acquisition process. 1: receive ds3 framer block declares the inframe condition after f-bit and m-bit synchronization process. additionally, the receive ds3 framer block must also detect valid (e.g., un-erred) p-bits. 1 fsync algo r/w 0 0: oof (receive out of frame) condition is declared when 6 out of 16 con- secutive f bits are in error 1: oof (receive out of frame) condition is declared when 3 out of 16 con- secutive f bits are in error 0 msync algo r/w 0 0: m-bit errors do not result in declaration of oof 1: oof is declared when m-bits in 3 out of 4 frames are in error.
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 54 t able 16: r x ds3 s tatus r egister r egister 15 r x ds3 s tatus r egister h ex a ddress :0 x 0f b it f unction t ype d efault d escription -o peration 7-5 unused ro 0 4 rx ferf ro 0 receive ferf (far-end receive failure) alarm: 0: the receive ds3 framer block is not currently declaring the ferf condition. 1: the receive ds3 framer block is currently declaring the ferf condi- tion. 3rx aic ro 0 receive aic (application identification channe) state: 0: indicates that the aic bit-field was set to 0 within two or more of the last 15 m-frames. this indicates that the inbound ds3 data stream is of the m13 framing format. 1: incoming frame is found to be in the c-bit format (aic bit = 1) for at least 63 consecutive m-frames. this indicates that the inbound ds3 data stream is of the c-bit parity framing format. 2 rx febe(2) ro 0 received febe (far-end-block error) value: rxfebe[2:0] contains the value of the most recently received febe value. when rxfebe[2:0] = 011, this indicates that the remote terminal has detected cp-bits or framing bit errors in its ds3 data stream. when rxfebe[2:0] = 111, this indicates that the remote terminal is not cur- rently detecting any framing bit or cp-bit errors in its ds3 data stream. n ote : these bit-fields are only active if the XRT72L71 is configured to sup- port the c-bit parity framing format. 1 rxfebe(1) ro 0 0 rxfebe(0) ro 0 t able 17: r x ds3 i nterrupt e nable r egister r egister 16 r x ds3 i nterrupt e nable r egister h ex a ddress : 0 x 10 b it f unction t ype d efault d escription -o peration 7 cp bit error interupt enable r/w 0 0: detection of cp-bit error interrupt is disabled 1: generates interrupt upon detection of cp (path parity) bit error. 6 los interrupt enable r/w 0 0: change in los condition interrupt is disabled 1: generates interrupt upon change of los (loss of signal) status 5 ais interrupt enable r/w 0 0: change in ais condition interrupt is disabled 1: generates interrupt upon change of ais (alarm indication signal) status. 4 idle interrupt enable r/w 0 0: change in idle condition interrupt is disabled 1: generates interrupt upon change of idle status 3 ferf interrupt enable r/w 0 0: change in ferf (far-end receive failure) condition interrupt is disabled 1: generates interrupt upon change in ferf condition. 2 aic interrupt enable r/w 0 0: change in aic state interrupt is disabled 1: generates interrupt upon change of aic values, in inbound ds3 data steam. 1 oof interrupt enable r/w 0 0: change in oof (out of frame) condition interrupt is disabled 1: generates interrupt upon change of oof condition. 0 p-bit error interrupt enable r/w 0 0: detection of p-bit error interrupt disabled 1: generates interrupt upon detection of p-bit error.
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 55 t able 18: r x ds3 i nterrupt s tatus r egister r egister 17 r x ds3 i nterrupt s tatus r egister h ex a ddress : 0 x 11 b it f unction t ype d efault d escription -o peration 7 cp bit error interrupt sta- tus rur 0 0: no cp-bit errors have been detected since the last read of this register. 1: indicates that at least one cp-bit error was detected since the last time this register was read. 6 los interrupt status rur 0 0: los condition has not changed since the last read of this register. 1: los condition has changed since the last read of this register. 5 ais interrupt status rur 0 0: ais condition has not changed since the last read of this register. 1: ais condition has changed since the last read of this register. 4 idle interrupt status rur 0 0: idle condition has not changed since the last read of this register. 1: idle condition has changed since the last read of this register. 3 ferf interrupt status rur 0 0: ferf condition has not changed since the last read of this register. 1: ferf condition has changed since the last read of this register. 2 aic interrupt status rur 0 0: aic state has not changed since the last read of this register. 1: validated aic has changed since the last read of this register. 1 oof interrupt status rur 0 0: oof condition has not changed since the last read of this register. 1: oof status has changed since the last read of this register. 0 p-bit error interrupt status rur 0 0: no p-bit errors have been detected since the last read of this register. 1: indicates that at least one p-bit error was detected since the last time this register was read. t able 19: r x ds3 feac r egister r egister 18 r x ds3 feac r egister h ex a ddress : 0 x 12 b it f unction t ype d efault d escription -o peration 7unused ro 0 6 rx feac(0) ro 1 rxfeac[5:0] contains the most recently validated receive feac code word. n ote : these bit-fields are only active if the XRT72L71 is configured to sup- port the c-bit parity framing forma 5 rxfeac(1) ro 1 4 rxfeac(2) ro 1 3 rxfeac(3) ro 1 2 rxfeac(4) ro 1 1 rxfeac(5) ro 1 0unused ro 0
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 56 t able 20: r x ds3 feac i nterrupt e nable /s tatus r egister r egister 19 r x ds3 feac i nterrupt e nable /s tatus r egister h ex a ddress : 0 x 13 b it f unction t ype d efault d escription -o peration 7-5 unused ro 0 4 feac valid ro 0 0: received feac code (residing in rxfeac[5:0]) has been removed. 1: received feac code (residing in rxfeac[5:0]) has been validated. n ote : this bit-field is only valid if the XRT72L71 is configured to support the c-bit parity framing format. 3 rx feac remove interrupt enable r/w 0 0: rxfeac removal interrupt is disabled. 1: generates an interrupt upon removal of previously validated feac code is enabled n ote : this bit-field is only valid if the XRT72L71 is configured to support the c-bit parity framing format. 2 rx feac remove interrupt status rur 0 0: indicates that no received feac messages have been removed since the last read of this register. 1: indicates that a received feac message has been removed since the last read of this register. n ote : this bit-field is only valid if the XRT72L71is configured to support the c-bit parity framing format. 1 rx feac valid interrupt enable r/w 0 0: rxfeac validation interrupt is disabled. 1: generates an interrupt upon validation of a newly received feac mes- sage. n ote : this bit-field is only valid if the XRT72L71 is configured to support the c-bit parity framing format. 0 rx feac valid interrupt status rur 0 0: indicates that no received feac messages have been validated since the last read of this register. 1: indicates that a newly received feac message has been validated since the last read of this register. n ote : this bit-field is only valid if the XRT72L71 is configured to support the c-bit parity framing format.
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 57 t able 21: r x ds3 lapd c ontrol r egister r egister 20 r x ds3 lapd c ontrol r egister h ex a ddress : 0 x 13 b it f unction t ype d efault d escription -o peration 7 enable 5 f(4) r/w 1 0: particular frame f-bit search block disabled 1: particular frame f-bit search block enabled each bit is an enable to five f0bit framer parallel search blocks 6 enable 5 f(3) r/w 1 5 enable 5 f(2) r/w 1 4 enable 5 f(1) r/w 1 3 enable 5 f(0) r/w 1 2 rx lapd enable r/w 0 0: disables the lapd receiver 1: enables the lapd receiver n ote : this bit-field is only active if the XRT72L71 has been configured to support the c-bit parity framing format. 1 rx lapd interrupt enable r/w 0 0: receive lapd interrupt is disabled. 1: generates interrupt anytime the lapd receiver receives a new lapd (pmdl) message. n ote : this bit-field is only active if the XRT72L71 has been configured to support the c-bit parity framing format. 0 rx lapd interrupt status rur/ wo 0 0: a new lapd message has not been received (by the lapd receiver) since the last read of this register. 1: a new lapd message has been received (by the lapd receiver) since the last read of this register. n ote : this bit-field is only active if the XRT72L71 has been configured to support the c-bit parity framing format.
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 58 t able 22: r x ds3 lapd s tatus r egister r egister 21 r x ds3 lapd s tatus r egister h ex a ddress : 0 x 15 b it f unction t ype d efault d escription -o peration 7unused ro 0 6rx abort ro 0 0: indicates that the lapd receiver is not currently receiving an abort message. 1: indicates that the lapd receiver is currently receiving an abort mes- sage. n ote : this bit-field is only active if the XRT72L71 has been configured to support the c-bit parity framing format. 5 rx lapd type(0) ro 0 00: lapd message is test signal identification type. (ram depth is 76 bytes (38 words)) 01: lapd message is idle signal identification type. (ram depth is 76 bytes (38 words)) 10: lapd message is cl path identification type. (ram depth is 76 bytes (38 words)) 11: lapd message is itu-t path identification type. (ram depth is 82 bytes (41 words)) n ote : these two bit-fields are only active if the XRT72L71 has been con- figured to support the c-bit parity framing format. 4 rx lapd type(1) ro 0 3 rx cr type ro 0 0: received lapd message originated from customer installation 1: received lapd message originated from terminal in the network n ote : this bit-field is only active if the XRT72L71 has been configured to support the c-bit parity framing format. 2 rx fcs error ro 0 0: crc-16 error was not detected within the most recently received lapd message. 1: crc-16 error was detected within the most recently received lapd mes- sage. n ote : this bit-field is only active if the XRT72L71 has been configured to support the c-bit parity framing format. 1 rx end of message ro 0 0: indicates that either the receive lapd message buffer is empty, or that the lapd receiver is currently receiving a lapd message. 1: indicates that a full lapd message has been received by the lapd receiver and that this message is residing within the receive lapd mes- sage buffer. n ote : this bit-field is only active if the XRT72L71 has been configured to support the c-bit parity framing format. 0 flag present ro 0 0: indicates that the lapd receiver is not currently receiving the flag sequence, within the lapd channel. 1: indicates that the lapd receiver is currently receiving the flag sequence within the lapd channel. n ote : this bit-field is only active if the XRT72L71 has been configured to support the c-bit parity framing format.
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 59 t able 23: t x ds3 c onfiguration r egister r egister 22 t x ds3 c onfiguration r egister h ex a ddress : 0 x 16 b it f unction t ype d efault d escription -o peration 7 tx yellow alarm r/w 0 0: x-bits are transmitted as conditions (detected by the receive ds3 framer block) dictate. 1: all x-bits (within each outbound ds3 frame) are set to 0 (forced inser- tion of yellow alarm) n ote : this bit-field is ignored when the txidle, the txais or the txlos bits are set. 6 tx xbit r/w 0 0: x-bits are transmitted as conditions (detected by the receive ds3 framer block) dictate. 1: all x-bits (within each outbound ds3 frame) are forced to 1. n ote : this bit-field is ignored when the txidle, the txais or the txlos bits are set. 5tx idle r/w 0 0: the idle pattern is not transmitted into the outbound ds3 data stream. 1: the idle pattern is transmitted into the outbound ds3 data stream. n ote : this bit-field is ignored when the txais or the txlos bits are set. 4 tx ais r/w 0 0: the ais pattern is not transmitted into the outbound ds3 data stream. 1: the ais pattern is transmitted into the outbound ds3 data stream. n ote : this bit-field is ignored when the txlos bit is set. 3 tx los r/w 0 0: the all zeros pattern is not transmitted into the outbound ds3 data stream. 1: the los (e.g., all zeros) pattern is transmitted into the outbound ds3 data stream. 2 ferf on los r/w 1 0: ferf (far-end receive failure) is not transmitted whenever the receive ds3 framer block declares an los (loss of signal) condition. 1: ferf is transmitted whenever the receive ds3 framer block declares an los condition. 1 ferf on oof r/w 1 0: ferf (far-end receive failure) is not transmitted whenever the receive ds3 framer block declares an oof (out of frame) condition. 1: ferf is transmitted whenever the receive ds3 framer block declares an oof condition. 0 ferf on ais r/w 1 0: ferf is not transmitted whenever the receive ds3 framer block detects an ais pattern in the inbound ds3 data stream. 1: ferf is transmitted whenever the receive ds3 framer block detects the ais pattern in the inbound ds3 data stream.
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 60 t able 24: t x ds3 m-b it m ask r egister r egister 23 t x ds3 m-b it m ask r egister h ex a ddress : 0 x 17 b it f unction t ype d efault d escription -o peration 7 tx febe dat(2) r/w 0 the transmit ds3 framer block will transmit the value txfebedat[2:0] within the febe bit-fields, if the febe register enable bit-field is set to 1. n ote : this bit-field is only active if the XRT72L71 is configured to support the c-bit parity framing format. 6 tx febe dat(1) r/w 0 5 tx febe dat(0) r/w 0 4 febe register enable r/w 0 0: febe bits, for transmission, are internally generated based on conditions, as detected by the receive ds3 framer block. 1: transmit febe bits are taken from the txfebedat [2:0] register bits n ote : this bit-field is only active if the XRT72L71 is configured to support the c-bit parity framing format. 3 mbit mask(2) r/w 0 the transmit ds3 framer block performs an xor operation of the mbitmask bits with the corresponding m bit, within each outbound ds3 frame. mbitmask(2) corresponds to first m-bit (m0) in ds3 frame, mbitmask(1) corresponds to second m-bit (m1) in ds3 frame, mbitmask(0) corresponds to last m-bit (m0) in ds3 frame n otes : 1. setting any of these bit-fields to 1, will cause an erred m-bit to be transmitted onto the line. 2. for normal operation, the user should set each of these bit-fields to 0. 2 mbit mask(1) r/w 0 1 mbit mask(0) r/w 0 0 txerror pbit r/w 0 0: p bits are calculated from input payload and inserted into the p-bit fields. 1: calculated p bits are inverted before transmission (thereby creating a p- bit error). n ote : for normal operation, set this bit-field to 0. t able 25: t x ds3 f-b it m ask 1 r egister r egister 24 t x ds3 f-b it m ask 1 r egister h ex a ddress : 0 x 18 b it f unction t ype d efault d escription -o peration 7-4 unused ro 0 3 f-bit mask (27) r/w 0 the transmit ds3 framer block performs an xor operation of the f-bit mask bits, with the corresponding f bits, within each outbound ds3 frame. fbitmask(0) corresponds to first f-bit (f1) is the ds3 frame, fbitmask (1) corresponds to 2nd f-bit (f0)in the ds3 frame,...fbitmask(27) corresponds to the last f-bit of the m-frame. n otes : 1. setting any of these bit-fields to 1 will cause an erred f-bit to be transmitted onto the line. 2. for normal operation, the user should set each of these bit-fields to 0. 2 f-bit mask (26) r/w 0 1 f-bit mask (25) r/w 0 0 f-bit mask (24) r/w 0
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 61 t able 26: t x d s 3 f-b it m ask 2 r egister r egister 25 t x d s 3 f-b it m ask 2 r egister h ex a ddress : 0 x 19 b it f unction t ype d efault d escription -o peration 7 f-bit mask (23) r/w 0 the transmit ds3 framer block performs an xor operation of the f-bit mask bits, with the corresponding f bits, within each outbound ds3 frame. fbitmask(0) corresponds to first f-bit (f1) is the ds3 frame, fbitmask (1) corresponds to 2nd f-bit (f0)in the ds3 frame,...fbitmask(27) corresponds to the last f-bit of the m-frame. n otes : 1. setting any of these bit-fields to 1 will cause an erred f-bit to be transmitted onto the line. 2. for normal operation, set each of these bit-fields to 0. 6 f-bit mask (22) r/w 0 5 f-bit mask (21) r/w 0 4 f-bit mask (20) r/w 0 3 f-bit mask (19) r/w 0 2 f-bit mask (18) r/w 0 1 f-bit mask (17) r/w 0 0 f-bit mask (16) r/w 0 t able 27: t x ds3 f-b it m ask 3 r egister r egister 26 t x ds3 f-b it m ask 3 r egister h ex a ddress : 0 x 1a b it f unction t ype d efault d escription -o peration 7 f-bit mask (15) r/w 0 the transmit ds3 framer block performs an xor operation of the fbitmask bits, with the corresponding f bits, within each outbound ds3 frame. fbit- mask(0) corresponds to first f-bit (f1) is the ds3 frame, fbitmask (1) corre- sponds to 2nd f-bit (f0)in the ds3 frame,...fbitmask(27) corresponds to the last f-bit of the m-frame. n otes : 1. setting any of these bit-fields to 1 will cause an erred f- bit to be transmitted onto the line. 2. for normal operation,set each of these bit-fields to 0. 6 f-bit mask (14) r/w 0 5 f-bit mask (13) r/w 0 4 f-bit mask (12) r/w 0 3 f-bit mask (11) r/w 0 2 f-bit mask (10) r/w 0 1 f-bit mask (9) r/w 0 0 f-bit mask (8) r/w 0 t able 28: t x ds3 f-b it m ask 4 r egister r egister 27 t x ds3 f-b it m ask 4 r egister h ex a ddress : 0 x 1b b it f unction t ype d efault d escription -o peration 7 f-bit mask (7) r/w 0 the transmit ds3 framer block performs an xor operation of the fbitmask bits, with the corresponding f bits, within each outbound ds3 frame. fbit- mask(0) corresponds to first f-bit (f1) is the ds3 frame, fbitmask (1) corre- sponds to 2nd f-bit (f0)in the ds3 frame,...fbitmask(27) corresponds to the last f-bit of the m-frame. n otes : 1. setting any of these bit-fields to 1 will cause an erred f-bit to be transmitted onto the line. 2. for normal operation, set each of these bit-fields to 0. 6 f-bit mask (6) r/w 0 5 f-bit mask (5) r/w 0 4 f-bit mask (4) r/w 0 3 f-bit mask (3) r/w 0 2 f-bit mask (2 r/w 0 1 f-bit mask (1) r/w 0 0 f-bit mask (0) r/w 0
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 62 t able 29: t x ds3 feac c onfiguration and s tatus r egister r egister 28 t x ds3 feac c onfiguration and s tatus r egister h ex a ddress : 0 x 1c b it f unction t ype d efault d escription -o peration 7-5 unused ro 0 4 tx feac interrupt enable r/w 0 0: disables the transmit feac interrupt. 1: enables the transmit feac interrupt. n ote : this bit-field is only active if the XRT72L71 is configured to support the c-bit parity framing format. 3 tx feac interrupt status rur 0 0: indicates that the transmit feac interrupt has not occurred since the last read of this register. 1: indicates that the transmit feac interrupt request has occurred since the last read of this register. n ote : this bit-field is only active if the XRT72L71 is configured to support the c-bit parity framing format. 2 tx feac enable r/w 0 0: the transmit feac processor is disabled, and cannot be commanded to transmit a feac message to the remote terminal equipment. 1: the transmit feac processor is enabled, and is able to be commanded to transmit feac messages to the remote terminal equipment. n ote : this bit-field is only active if the XRT72L71 is configured to support the c-bit parity framing format. 1 tx feac go r/w 0 0 to 1 transition within this bit-field commands the transmit feac processor to begin its transmission of the feac message, which resides within the txfeac register. n ote : this bit-field is only active if the XRT72L71 is configured to support the c-bit parity framing format. 0 tx feac busy ro 0 0: indicates that the transmit feac processor is not currently transmitting a feac message to the remote terminal equipment 1: data from feac register is currently being transmitted to the remote ter- minal equipment. n ote : this bit-field is only active if the XRT72L71 is configured to support the c-bit parity framing format. t able 30: t x ds3 feac r egister r egister 29 t x ds3 feac r egister h ex a ddress 0 x 1d b it f unction t ype d efault d escription -o peration 7unused ro 0 6 tx feac (5) r/w 1 contains the value of the feac code (or message) that is to be transmitted to the remote terminal equipment. the lsb of this bit-field will be transmit- ted first. n ote : this register is only active if the XRT72L71 has been configured to operate in the c-bit parity framing format 5 tx feac (4) r/w 1 4 tx feac (3) r/w 1 3 tx feac (2) r/w 1 2 tx feac (1) r/w 1 1 tx feac (0) r/w 1 0unused ro 0
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 63 t able 31: t x ds3 lapd c onfiguration r egister r egister 30 t x ds3 lapd c onfiguration r egister h ex a ddress : 0 x 1e b it f unction t ype d efault d escription -o peration 7-5 unused ro 0 4 reserved r/w 0 set bit to 0 3 auto retransmit r/w 1 0: lapd transmitter will not automatically transmit a given pmdl (or lapd message) repeatedly at one second intervals. 1: lapd transmitter will transmit a given pmdl (or lapd message) repeat- edly at one second intervals. n ote : this bit-field is only active if the XRT72L71 has been configured to support the c-bit parity framing format. 2 tx lapd type(1) r/w 0 00: lapd message ram depth is 76 bytes (38 words) 01: lapd message ram depth is 76 bytes (38 words) 10: lapd message ram depth is 76 bytes (38 words) 11: lapd message ram dept his 82 bytes (41 words) n ote : these bit-fields are only active if the XRT72L71 has been configured to support the c-bit parity framing format. 1 tx lapd type(0) r/w 0 0 tx lapd enable r/w 0 0: lapd transmitter is disabled. the transmit ds3 framer block will set each outbound dl bit-field to 1. 1: lapd transmitter is enabled. the lapd transmitter will begin to transmit the flag sequence octet (0x7e), until a transmit lapd message command has been invoked. n ote : this bit-field is only active if the XRT72L71 has been configured to support the c-bit parity framing format.
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 64 t able 32: t x ds3 lapd s tatus /i nterrupt r egister r egister 31 t x ds3 lapd s tatus /i nterrupt r egister h ex a ddress : 0 x 1f b it f unction t ype d efault d escription -o peration 7-4 unused ro 0 3 tx dl start r/w 0 0 to 1 transition configures the lapd transmitter to begin its transmission of the pmdl (or lapd message) consisting of the data residing within the transmit lapd message buffer. n ote : this bit-field is only active if the XRT72L71 has been configured to support the c-bit parity framing format. 2 tx dl busy ro 0 0: lapd transmitter is not currently transmitting a lapd message to the remote terminal equipment; and is not available to transmit a new lapd message. 1: lapd transmitter is currently transmitting a lapd message to the remote terminal equipment. n ote : this bit-field is only active if the XRT72L71 has been config- ured to support the c-bit parity framing format. 1 tx lapd interrupt enable r/w 0 0: completion of transmission of lapd message interrupt is disabled. 1: completion of transmission of lapd message interrupt is enabled. the XRT72L71 will generate an interrupt, anytime the lapd transmitter has completed its transmission of a given lapd message. n ote : this bit-field is only active if the XRT72L71 has been configured to support the c-bit parity framing format. 0 tx lapd interrupt status rur 0 0: completion of transmission of lapd message interrupt has not occurred since the last read of this register. 1: completion of transmission of lapd message interrupt has occurred since the last read of this register. n ote : this bit-field is only active if the XRT72L71 has been configured to support the c-bit parity framing format. t able 33: pmon lcv e vent c ount r egister - msb r egister 32 pmon lcv e vent c ount r egister - msb h ex a ddress : 0 x 20 b it f unction t ype d efault d escription -o peration 7-0 lcv count high byte rur 0x00 this reset-upon-read register, along with pmon lcv event count reg- ister - lsb contains the 16-bit value for the total number of line code viola- tions that have been detected since the last read of this register. this register contains the high byte of this 16-bit expression. n ote : this register is only active if the b3zs decoder (within the XRT72L71) has been enabled. t able 34: pmon lcv e vent c ount r egister - lsb r egister 33 pmon lcv e vent c ount r egister - lsb h ex a ddress : 0 x 21 b it f unction t ype d efault d escription -o peration 7-0 lcv count low byte rur 0x00 this reset-upon-read register, along with pmon lcv event count reg- ister - msb contains the 16 bit value for the total number of line code viola- tions that have been detected since the last read of this register. this register contains the low byte of this 16-bit expression. n ote : this register is only active if the b3zs decoder (within the XRT72L71) has been enabled.
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 65 t able 35: pmon f raming b it e rror e vent c ount r egister - msb r egister 34 pmon f raming b it e rror e vent c ount r egister - msb h ex a ddress : 0 x 22 b it f unction t ype d efault d escription -o peration 7-0 f bit error count high-byte rur 0x00 this reset-upon-read register, along with pmon framing bit error count register - lsb contains the 16 bit value for the total number of framing bit (e.g., both f and m-bit) errors that have been detected since the last read of this register. this register contains the high byte value of this 16-bit expression. t able 36: pmon f raming b it e rror e vent c ount r egister - lsb r egister 35 pmon f raming b it e rror e vent c ount r egister - lsb h ex a ddress : 0 x 23 b it f unction t ype d efault d escription -o peration 7-0 f bit error count low-byte rur 0x00 this reset-upon-read register, along with pmon framing bit error count register - msb contains the 16 bit value for the total number of framing bit (e.g., both f and m-bit) errors that have been detected since the last read of this register. this register contains the low byte value of this 16-bit expression. t able 37: pmon p-b it e rror c ount r egister - msb r egister 36 pmon p-b it e rror c ount r egister - msb h ex a ddress : 0 x 24 b it f unction t ype d efault d escription -o peration 7-0 p-bit error count high-byte rur 0x00 this reset-upon-read register, along with pmon p-bit error count reg- ister - lsb contains the 16 bit value for the total number of p bit errors that have been detected since the last read of this register. this register con- tains the high byte value of this 16-bit expression. t able 38: pmon p-b it e rror c ount r egister - lsb r egister 37 pmon p-b it e rror c ount r egister - lsb h ex a ddress : 0 x 25 b it f unction t ype d efault d escription -o peration 7-0 p-bit error count low-byte rur 0x00 this reset-upon-read register, along with pmon p-bit error count reg- ister - msb contains the 16 bit value for the total number of p bit errors that have been detected since the last read of this register. this register con- tains the low byte value of this 16-bit expression. t able 39: pmon febe e vent c ount r egister - msb r egister 38 pmon febe e vent c ount r egister - msb h ex a ddress : 0 x 26 b it f unction t ype d efault d escription -o peration 7-0 febe event count high- byte rur 0x00 this reset-upon-read register, along with pmon febe event count register - lsb contains the 16 bit value for the total number of febe events that have been detected since the last read of this register. this register contains the high byte value of this 16-bit expression. n ote : this register is only active if the XRT72L71 has been configured to support the c-bit parity framing format.
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 66 t able 40: pmon febe e vent c ount r egister - lsb r egister 39 pmon febe e vent c ount r egister - lsb h ex a ddress : 0 x 27 b it f unction t ype d efault d escription -o peration 7-0 febe event count low- byte rur 0x00 this reset-upon-read register, along with pmon febe event count register - msb contains the 16 bit value for the total number of febe events that have been detected since the last read of this register. this reg- ister contains the low byte value of this 16-bit expression. n ote : this register is only active if the XRT72L71 has been configured to support the c-bit parity framing format. t able 41: pmon plcp bip-8 e rror c ount r egister - msb r egister 40 pmon plcp bip-8 e rror c ount r egister - msb h ex a ddress : 0 x 28 b it f unction t ype d efault d escription -o peration 7-0 plcp bip error count high-byte rur 0x00 this reset-upon-read register, along with pmon plcp bip-8 error count register - lsb contains the 16 bit value for the total number of plcp bip-8 errors that have been detected since the last read of this register. this register contains the high bye value of this 16-bit expression. n ote : this register is only active if the XRT72L71 has been configured to operate in both the atm uni and plcp modes. t able 42: pmon plcp bip-8 e rror c ount r egister - lsb r egister 41 pmon plcp bip-8 e rror c ount r egister - lsb h ex a ddress : 0 x 29 b it f unction t ype d efault d escription -o peration 7-0 plcp bip error count low-byte rur 0x00 this reset-upon-read register, along with pmon plcp bip-8 error count register - msb contains the 16 bit value for the total number of plcp bip-8 errors that have been detected since the last read of this register. this register contains the low bye value of this 16-bit expression. n ote : this register is only active if the XRT72L71 has been configured to operate in both the atm uni and plcp modes. t able 43: pmon plcp f raming b yte e rror c ount r egister - msb r egister 42 pmon plcp f raming b yte e rror c ount r egister - msb h ex a ddress : 0 x 2a b it f unction t ype d efault d escription -o peration 7-0 plcp fa error count high- byte rur 0x00 this reset-upon-read register, along with pmon plcp fa error count register - lsb contains the 16 bit value for the total number of plcp fram- ing (e.g, fa1 or fa2) byte errors that have been detected since the last read of this register. this register contains the high byte value of this 16-bit expression. n ote : this register is only active if the XRT72L71 has been configured to operate in both the atm uni and plcp modes.
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 67 t able 44: pmon plcp f raming b yte e rror c ount r egister - lsb r egister 43 pmon plcp f raming b yte e rror c ount r egister - lsb h ex a ddress : 0 x 2b b it f unction t ype d efault d escription -o peration 7-0 plcp fa error count low- byte rur 0x00 this reset-upon-read register, along with pmon plcp fa error count register - msb contains the 16 bit value for the total number of plcp fram- ing (e.g, fa1 or fa2) byte errors that have been detected since the last read of this register. this register contains the low byte value of this 16-bit expression. n ote : this register is only active if the XRT72L71 has been configured to operate in both the atm uni and plcp modes. t able 45: pmon plcp febe c ount r egister - msb r egister 44 pmon plcp febe c ount r egister - msb h ex a ddress : 0 x 2c b it f unction t ype d efault d escription -o peration 7-0 plcp febe count high- byte rur 0x00 this reset-upon-read register, along with pmon plcp febe count register - lsb contains the 16 bit value for the total number of plcp febe (far-end block error) events that have been detected since the last read of this register. this register contains the high byte value of this 16-bit expression. n ote : this register is only active if the XRT72L71 has been configured to operate in both the atm uni and plcp modes. t able 46: pmon plcp febe c ount r egister -lsb r egister 45 pmon plcp febe c ount r egister -lsb h ex a ddress : 0 x 2d b it f unction t ype d efault d escription -o peration 7-0 plcp febe count low- byte rur 0x00 this reset-upon-read register, along with pmon plcp febe count register - msb contains the 16 bit value for the total number of plcp febe (far-end block error) events that have been detected since the last read of this register. this register contains the low byte value of this 16-bit expres- sion. n ote : this register is only active if the XRT72L71 has been configured to operate in both the atm uni and plcp modes. t able 47: pmon s ingle - bit hec e rror c ount - msb r egister 46 pmon s ingle - bit hec e rror c ount - msb h ex a ddress : 0 x 2e b it f unction t ype d efault d escription -o peration 7-0 s-hec error count high- byte rur 0x00 this reset-upon-read register, along with pmon single-bit hec error count register - lsb contains the 16 bit value for the total number of sin- gle-bit hec byte errors that have been detected since the last read of this register. this register contains the high byte value of this 16-bit expres- sion. n ote : this register is only active if the XRT72L71 has been configured to operate in the atm uni mode.
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 68 t able 48: pmon s ingle - bit hec e rror c ount - lsb r egister 47 pmon s ingle - bit hec e rror c ount - lsb h ex a ddress : 0 x 2f b it f unction t ype d efault d escription -o peration 7-0 s-hec error count low- byte rur 0x00 this reset-upon-read register, along with pmon single-bit hec error count register - msb contains the 16 bit value for the total number of sin- gle-bit hec byte errors that have been detected since the last read of this register. this register contains the low byte value of this 16-bit expression. n ote : this register is only active if the XRT72L71 has been configured to operate in the atm uni mode. t able 49: pmon m ultiple - bit hec e rror c ount - msb r egister 48 pmon m ultiple - bit hec e rror c ount - msb h ex a ddress : 0 x 30 b it f unction t ype d efault d escription -o peration 7-0 m-hec error count high- byte rur 0x00 this reset-upon-read register, along with pmon multiple-bit hec error count register - lsb contains the 16 bit value for the total number of multi- bit hec byte errors that have been detected since the last read of this regis- ter. this register contains the high byte value of this 16-bit expression. n ote : this register is only active if the XRT72L71has been configured to operate in the atm uni mode. t able 50: pmon m ultiple - bit hec e rror c ount - lsb r egister 49 pmon m ultiple - bit hec e rror c ount - lsb h ex a ddress : 0 x 31 b it f unction t ype d efault d escription -o peration 7-0 m-hec error count low- byte rur 0x00 this reset-upon-read register, along with pmon multiple-bit hec error count register - msb contains the 16 bit value for the total number of multi- bit hec byte errors that have been detected since the last read of this regis- ter. this register contains the low byte value of this 16-bit expression. n ote : this register is only active if the device has been configured to oper- ate in the atm uni mode. t able 51: pmon r eceived i dle c ell c ount /prbs e rror c ount - msb r egister 50 pmon r eceived i dle c ell c ount /prbs e rror c ount - msb h ex a ddress : 0 x 32 b it f unction t ype d efault d escription -o peration 7-0 rx idle cell count high- byte/ prbs error count high- byte rur 0x00 atm mode : this register, along with pmon received idle cell count - lsb contains the 16 bit value for the total number of idle cells that have been received by the receive cell processor, since the last read of this register. this register contains the high byte value of this 16-bit expression. clear channel framer mode : this register, along with pmon prbs error count - lsb regster contains the 16 bit value for the total number of prbs bit errors that have been received (by the prbs receiver) since the last read of this register. this register contains the high byte value of this 16-bit expression.
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 69 t able 52: pmon r eceived i dle c ell c ount /prbs e rror c ount - lsb r egister 51 pmon r eceived i dle c ell c ount /prbs e rror c ount - lsb h ex a ddress : 0 x 33 b it f unction t ype d efault d escription -o peration 7-0 rx idle cell count low- byte/ prbs error count low- byte rur 0x00 atm mode : this register, along with pmon received idle cell count - msb contains the 16 bit value for the total number of idle cells that have been received by the receive cell processor, since the last read of this register. this register contains the low byte value of this 16-bit expression. clear channel framer mode: this register, along with pmon prbs error count - msb regster contains the 16 bit value for the total number of prbs bit errors that have been received (by the prbs receiver) since the last read of this register. this register contains the low byte value of this 16-bit expression. t able 53: pmon r eceive v alid c ell c ount - msb r egister 52 pmon r eceive v alid c ell c ount - msb h ex a ddress : 0 x 34 b it f unction t ype d efault d escription -o peration 7-0 rx valid cell count high- byte rur 0x00 this reset-upon-read register, along with pmon receive valid cell count - lsb contains the 16 bit value for the total number of valid cells that have been received since the last read of this register. this register contains the high byte value of this 16-bit expression. n ote : this register is only active if the XRT72L71 has been configured to operate in the atm uni mode. t able 54: pmon r eceive v alid c ell c ount - lsb r egister 53 pmon r eceive v alid c ell c ount - lsb h ex a ddress : 0 x 35 b it f unction t ype d efault d escription -o peration 7-0 rx valid cell count low- byte rur 0x00 this reset-upon-read register, along with pmon receive valid cell count - msb contains the 16 bit value for the total number of valid cells that have been received since the last read of this register. this register contains the low byte value of this 16-bit expression. n ote : this register is only active if the XRT72L71 has been configured to operate in the atm uni mode. t able 55: pmon d iscarded c ell c ount - msb r egister 54 pmon d iscarded c ell c ount - msb h ex a ddress : 0 x 36 b it f unction t ype d efault d escription -o peration 7-0 cell drop count high-byte rur 0x00 this reset-upon-read register, along with pmon discarded cell count - lsb contains the 16 bit value for the total number of cells that have been discarded since the last read of this register. this register contains the high byte value of this 16-bit expression. n ote : this register is only active if the XRT72L71 has been configured to operate in the atm uni mode.
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 70 t able 56: pmon d iscarded c ell c ount - lsb r egister 55 pmon d iscarded c ell c ount - lsb h ex a ddress : 0 x 37 b it f unction t ype d efault d escription -o peration 7-0 cell drop count low-byte rur 0x00 this reset-upon-read register, along with pmon discarded cell count - msb contains the 16 bit value for the total number of cells that have been discarded since the last read of this register. this register contains the low byte value of this 16-bit expression. n ote : this register is only active if the XRT72L71 has been configured to operate in the atm uni mode. t able 57: pmon t ransmit i dle c ell c ount - msb r egister 56 pmon t ransmit i dle c ell c ount - msb h ex a ddress : 0 x 38 b it f unction t ype d efault d escription -o peration 7-0 tx idle cell count high- byte rur 0x00 this reset-upon-read register, along with pmon transmit idle cell count - lsb contains the 16 bit value for the total number of idle cells that have been trnasmitted by the transmit cell processor, since the last read of this regis- ter. this register contains the high byte value of this 16-bit expression. n ote : this register is only active if the XRT72L71 has been configured to operate in the atm uni mode. t able 58: pmon t ransmit i dle c ell c ount - lsb r egister 57 pmon t ransmit i dle c ell c ount - lsb h ex a ddress : 0 x 39 b it f unction t ype d efault d escription -o peration 7-0 tx idle cell count low- byte rur 0x00 this reset-upon-read register, along with pmon transmit idle cell count - msb contains the 16 bit value for the total number of idle cells that have been trnasmitted by the transmit cell processor, since the last read of this register. this register contains the low byte value of this 16-bit expression. n ote : this register is only active if the XRT72L71 has been configured to operate in the atm uni mode. t able 59: pmon t ransmit v alid c ell c ount - msb r egister 58 pmon t ransmit v alid c ell c ount - msb h ex a ddress : 0 x 3a b it f unction t ype d efault d escription -o peration 7-0 tx valid cell count high- byte rur 0x00 this reset-upon-read register, along with pmon transmit valid cell count - lsb contains the 16 bit value for the total number of valid cells that have been trnasmitted by the transmit cell processor, since the last read of this register. this register contains the high byte value of this 16-bit expres- sion. n ote : this register is only active if the XRT72L71 has been configured to operate in the atm uni mode.
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 71 t able 60: pmon t ransmit v alid c ell c ount - lsb r egister 59 pmon t ransmit v alid c ell c ount - lsb h ex a ddress : 0 x 3b b it f unction t ype d efault d escription -o peration 7-0 tx valid cell count low- byte rur 0x00 this reset-upon-read register, along with pmon transmit valid cell count - msb contains the 16 bit value for the total number of valid cells that have been trnasmitted by the transmit cell processor, since the last read of this register. this register contains the low byte value of this 16-bit expression. n ote : this register is only active if the XRT72L71 has been configured to operate in the atm uni mode. t able 61: pmon h olding r egister r egister 60 pmon h olding r egister h ex a ddress : 0 x 3c b it f unction t ype d efault d escription -o peration 7-0 pmon hold value ro 0x00 if the bi-directional data bus (of the microprocessor interface) is configured to be 8-bits wide; then this register holds the companion byte of any 16-bit pmon count registers, 1-sec accumulator registers, or the test cell error accumulator register, when one of these registers are read, during the previ- ous bus cycle. t able 62: o ne s econd e rror s tatus r egister r egister 61 o ne s econd e rror s tatus r egister h ex a ddress : 0 x 3d b it f unction t ype d efault d escription -o peration 7-2 unused ro 0 1 errored second ro 0 0: no errors were detected during last one second accumulation interval 1: at least one error was detected during last one second accumulation inter- val 0 severe errored second ro 0 0: error rate did not exceed 1 in 10,000 in last one second interval 1: error rate in lat one second interval was greater than 1 in 10,000 t able 63: lcv - o ne s econd a ccumulator r egister - msb r egister 62 lcv - o ne s econd a ccumulator r egister - msb h ex a ddres : 0 x 3e b it f unction t ype d efault d escription -o peration 7-0 lcv 1sec high-byte ro 0x00 this read-only register, along with lcv - one second accumulator reg- ister - lsb contains a 16 bit value of the total number of line code viola- tions that have been detected within the last one-second accumulation interval. this register contains the high byte value of this expression.
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 72 t able 64: lcv - o ne s econd a ccumulator r egister - lsb r egister 63 lcv - o ne s econd a ccumulator r egister - lsb h ex a ddres : 0 x 3f b it f unction t ype d efault d escription -o peration 7-0 lcv 1sec low-byte ro 0x00 this read-only register, along with lcv - one second accumulator reg- ister - msb contains a 16 bit value of the total number of line code viola- tions that have been detected within the last one-second accumulation interval. this register contains the low byte value of this expression. t able 65: p-b it e rrors - o ne s econd a ccumulator r egister - msb r egister 64 p-b it e rrors - o ne s econd a ccumulator r egister - msb h ex a ddress : 0 x 40 b it f unction t ype d efault d escription -o peration 7-0 p-bit errors 1sec high- byte ro 0x00 this read-only register, along with p-bit errors - one second accumula- tor register - lsb contains the 16-bit expression for the total number of p- bit errors that have been detected within the last one second accumulation period. this register contains the high byte value of this expression. t able 66: p-b it e rrors - o ne s econd a ccumulator r egister - lsb r egister 65 p-b it e rrors - o ne s econd a ccumulator r egister - lsb h ex a ddress : 0 x 41 b it f unction t ype d efault d escription -o peration 7-0 p-bit errors 1sec low-byte ro 0x00 this read-only register, along with p-bit errors - one second accumula- tor register - msb contains the 16-bit expression for the total number of p- bit errors that have been detected within the last one second accumulation period. this register contains the low byte value of this expression. t able 67: hec b yte e rrors - o ne s econd a ccumulator r egister - msb r egister 66 hec b yte e rrors - o ne s econd a ccumulator r egister - msb h ex a ddress : 0 x 42 b it f unction t ype d efault d escription -o peration 7-0 hec errors 1sec high- byte ro 0x00 this read-only register, along with hec byte errors - one second accu- mulator register - lsb contains the 16-bit expression for the total number of hec byte errors that have been detected within the last one second accumu- lation period. this register contains the high byte value of this expression. n ote : this register is only active if the XRT72L71 has been configured to operate in the atm uni mode. t able 68: hec b yte e rrors - o ne s econd a ccumulator r egister -lsb r egister 67 hec b yte e rrors - o ne s econd a ccumulator r egister -lsb h ex a ddress : 0 x 43 b it f unction t ype d efault d escription -o peration 7-0 hec errors 1sec high- byte ro 0x00 this read-only register, along with hec byte errors - one second accu- mulator register - msb contains the 16-bit expression for the total number of hec byte errors that have been detected within the last one second accu- mulation period. this register contains the low byte value of this expres- sion. n ote : this register is only active if the XRT72L71 has been configured to operate in the atm uni mode.
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 73 t able 69: r x plcp c onfiguration /s tatus r egister r egister 68 r x plcp c onfiguration /s tatus r egister h ex a ddress : 0 x 44 b it f unction t ype d efault d escription -o peration 7-4 unused ro 0 3 plcp reframe r/w 0 0 to 1 transition commands the receive plcp processor block to transition into the fa1 and fa2 octet search state, and to reacquire plcp frame synchronization. n ote : this bit-field is only active if the XRT72L71 is operating in both the atm uni and the plcp modes. 2 poof status ro 1 0: indicates that the receive plcp processor block is not currently declar- ing an out of frame condition 1: indicates that the receive plcp processor block is currently declaring an out of frame condition. n ote : this bit-field is only active if the XRT72L71 is operating in both the atm uni and the plcp modes. 1 plof status ro 1 0: indicates that the receive plcp processor block is not currently declar- ing a loss of frame condition. 1: indicates that the receive plcp processor block is currently declaring a loss of frame condition. n ote : this bit-field is only active if the XRT72L71 is operating in both the atm uni and the plcp modes. 0 plcp yellow alarm ro 0 0: indicates that the receive plcp processor is currently declaring a yellow alarm condition. 1: indicates that the receive plcp processor is not currently declaring a yellow alarm condition. n ote : this bit-field is only active if the XRT72L71 is operating in both the atm uni and the plcp modes. t able 70: r x plcp i nterrupt e nable r egister r egister 69 r x plcp i nterrupt e nable r egister h ex a ddress : 0 x 45 b it f unction t ype d efault d escription -o peration 7-2 unused ro 0 1 poof interrupt enable r/w 0 0: the change in plcp oof condition interrupt is disabled. 1: the change in plcp oof condition interrupt is enabled. n ote : this bit-field is only active if the XRT72L71 is operating in both the atm uni and the plcp modes. 0 plof interrupt enable r/w 0 0: the change in plcp lof condition interrupt is disabled. 1: the change in plcp lof condition interrupt is enabled. n ote : this bit-field is only active if the XRT72L71is operating in both the atm uni and the plcp mode.
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 74 t able 71: r x plcp i nterrupt s tatus r egister r egister 70 r x plcp i nterrupt s tatus r egister h ex a ddress : 0 x 46 b it f unction t ype d efault d escription -o peration 7-2 unused ro 0 1 poof interrupt status rur 0 0: indicates that the change in poof condition interrupt has not occurred since the last read of this register. 1: indicates that the change in poof condition interrupt has occurred since the last read of this register. n ote : this bit-field is only active if the XRT72L71is operating in both the atm uni and the plcp modes. 0 plof interrupt status rur 0 0: indicates that the change in plof condition interrupt has not occurred since the last read of this register. 1: indicates that the change in plof condition interrupt has occurred since the last read of this register. n ote : this bit-field is only active if the XRT72L71 is operating in both the atm uni and the plcp modes. t able 72: f uture u se r egister 71 f uture u se h ex a ddress : 0 x 47 b it f unction t ype d efault d escription -o peration t able 73: t x plcp fa1 b yte e rror m ask r egister r egister 72 t x plcp fa1 b yte e rror m ask r egister h ex a ddress : 0 x 48 b it f unction t ype d efault d escription -o peration 7-0 fa1 error mask r/w 0x00 the transmit plcp processor block always xors contents of this register with the contents of the fa1 byte (within a plcp frame). this xored value is then written back into the fa1 byte field, within each outbound plcp frame; prior to transmission. setting any of these bit-fields to 1 introduces error in that specific bit, within each outbound fa1 byte. register must be set to 0x00 for normal operation, n ote : this bit-field is only active if the XRT72L71 is operating in both the atm uni and the plcp modes. t able 74: t x plcp fa2 b yte e rror m ask r egister r egister 73 t x plcp fa2 b yte e rror m ask r egister h ex a ddress : 0 x 49 b it f unction t ype d efault d escription -o peration 7-0 fa2 error mask r/w 0x00 the transmit plcp processor block always xors contents of this register with the contents of the fa2 byte (within a plcp frame). this xored value is then written back into the fa1 byte field, within each outbound plcp frame; prior to transmission. setting any of these bit-fields to 1 introduces error in that specific bit, within each outbound fa1 byte. register must be set to 0x00 for normal operation, n ote : this bit-field is only active if the XRT72L71 is operating in both the atm uni and the plcp modes.
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 75 t able 75: t x plcp bip-8 e rror m ask r egister 74 t x plcp bip-8 e rror m ask h ex a ddress : 0 x 4a b it f unction t ype d efault d escription -o peration 7-0 b1 error mask r/w 0x00 the transmit plcp processor block always xors contents of this register with the contents of the b1 byte (within a plcp frame). this xored value is then written back into the b1 byte field, within each outbound plcp frame; prior to transmission. setting any of these bit-fields to 1 introduces error in that specific bit, within each outbound b1 byte. register must be set to 0x00 for normal operation, n ote : this bit-field is only active if the XRT72L71 is operating in both the atm uni and the plcp modes. t able 76: t x plcp g1 b yte r egister r egister 75 t x plcp g1 b yte r egister h ex a ddress : 0 x 4b b it f unction t ype d efault d escription -o peration 7-5 unused ro 0 4 tx plcp febe mask r/w 0 0: febe count is transmitted, based upon b1 byte error conditions, as detected by the receive plcp processor. 1: febe is transmitted as 0000 n ote : this bit-field is only active if the XRT72L71 is operating in both the atm uni and the plcp modes. 3 force plcp yellow alarm r/w 0 0: plcp yellow alarm generated from receive plcp processor. 1: plcp yellow alarm is forced. n ote : this bit-field is only active if the XRT72L71 is operating in both the atm uni and the plcp modes. 2 lss(2) r/w 0 link status signal may be programmed by user 1 lss(1) r/w 0 0 lss(0) r/w 0
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 76 t able 77: r x cp c onfiguration r egister r egister 76 r x cp c onfiguration r egister h ex a ddress : 0 x 4c b it f unction t ype d efault d escription -o peration 7rx lcd ro 1 0: indicates that the receive cell processor currently has cell delineation within the incoming stream of atm cells. 1: indicates that the receive cell processor is currently declaring a loss of cell delineation. n ote : this bit-field is only active if the XRT72L71 is operating in the atm uni mode. 6 rdp chk pat r/w 0 0: receive cell processor will insert an alternating data path integrity check value of 0x55 and 0xaa into the 5th octet position of each cell, writ- ten into the rxfifo 1: receive cell processor will insert a fixed data path integrity check value of 0x55 into the 5th octet position of each cell, written into the rxfifo. n ote : this bit-field is only active if the XRT72L71 is operating in the atm uni mode. 5 rdp chk pat en r/w 0 0: data path integrity check value is not written into atm cells. atm cells (with their received hec byte value) are passed on into rxfifo without modification. 1:data path integrity check value of 0x55 and 0xaa into the 5th octet posi- tion of each cell, is written into each atm cell, which is routed to the rxfifo. n ote : t his bit-field is only active if the XRT72L71 is operating in the atm uni mode. 4 ic discard r/w 1 0: idle cells are not discarded by the receive cell processor block 1: idle cells are automatically discarded by the receive cell processor block. n ote : this bit-field is only active if the XRT72L71 is operating in the atm uni mode. 3 segoam pass through r/w 1 0: segment-type oam cells are not written into rxfifo. 1: segment-type oam cells are passed to receiver fifo n ote : this bit-field is only active if the XRT72L71 is operating in the atm uni mode. 2 de-scramble enable r/w 1 0: disables cell payload de-scrambling 1: enables cell payload de-scrambling n ote : this bit-field is only active if the XRT72L71 is operating in the atm uni mode. 1 rx coset enable r/w 1 0: coset polynomial is not added to the hec byte of each incoming atm cell. 1: coset polynomial is added to hec byte of each incoming atm cell. the receive cell processor needs to account for the coset polynomial during hec byte verification. n ote : this bit-field is only active if the XRT72L71 is operating in the atm uni mode. 0 hec error ignore r/w 0 0: discards/drops cells with hec byte errors. 1: retains cells with hec byte errors, for further processing. n ote : this bit-field is only active if the XRT72L71 is operating in the atm uni mode.
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 77 t able 78: r x cp a dditional c onfiguration r egister r egister 77 r x cp a dditional c onfiguration r egister h ex a ddress : 0 x 4d b it f unction t ype d efault d escription -o peration 7 rx oam fifo enable r/w 0 0: the receive oam cell buffer functions as one cell (54 byte) buffer 1: the receive oam cell buffer functions as two-54-byte buffers. n ote : this bit-field is only active if the XRT72L71 is operating in the atm uni mode. 6 rx crc10 enable r/w 0 0: crc-10 verification is not performed on received oam cells. 1: crc-10 verification is performed on received oam cells. n ote : this bit-field is only active if the XRT72L71 is operating in the atm uni mode. 5 user cell filter discard r/w 0 0: incoming cells with header bytes matching the user cell filtering criteria are written to the rxfifo (all remaining cells are discarded). 1: incoming cells with header bytes not matching the user cell filtering criteria are discarded (all remaining cells are written to rxfifo) n otes : 1. this bit-field is only active if the XRT72L71 is operating in the atm uni mode. 2. this bit-field is only active of the user cell filter is enabled. 4 user cell filter enable r/w 0 0: user cell filter is disabled. all user cells will be written to the rxfifo. 1: user cell filter is enabled. n ote : this bit-field is only active if the XRT72L71 is operating in the atm uni mode. 3 correction thresh(1) r/w 1 these two bits permit the user to specify the correction threshold that the receive cell processor will use, during hec byte verification. 00: sets correction threshold to 0. 01: sets correction threshold to 1. 10: sets correction threshold to 3. 11: sets correction threshold to 7. n ote : this bit-field is only active if the XRT72L71 is operating in the atm uni mode. 2 correction thresh(0) r/w 1 1 correction enable r/w 1 0: disables header error correction. 1: enables header error correction algorithm. n ote : this bit-field is only active if the XRT72L71 is operating in the atm uni mode. 0 oam pass through r/w 0 0: oam cells are subject to the idle cell and user cell filtering criteria. 1: oam cells are not subject to the idle cell and user cell filtering criteria. n ote : this bit-field is only active if the XRT72L71 is operating in the atm uni mode.
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 78 t able 79: r x cp i nterrupt e nable r egister r egister 78 r x cp i nterrupt e nable r egister h ex a ddress : 0 x 4e b it f unction t ype d efault d escription -o peration 7-3 unused ro 0 2 oam interrupt enable r/w 0 0: receipt of oam cell interrupt is disabled. 1: receipt of oam cell interrupt is enabled. n ote : this bit-field is only active if the XRT72L71 is operating in the atm uni mode. 1 lcd interrupt enable r/w 0 0: change in lcd (loss of cell delineation) condition interrupt is dis- abled. 1: change in lcd condition interrupt is enabled. n ote : this bit-field is only active if the XRT72L71 is operating in the atm uni mode. 0 hec error interrupt enable r/w 0 0: detection of hec byte error interrupt is disabled. 1: detection of hec byte error interrupt is enabled. n ote : this bit-field is only active if the XRT72L71 is operating in the atm uni mode.
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 79 t able 80: r x cp i nterrupt s tatus r egister r egister 79 r x cp i nterrupt s tatus r egister h ex a ddress : 0 x 4f b it f unction t ype d efault d escription -o peration 7 oam buffer/fifo overflow rur 0 0: receive oam cell buffer/fifo has not experienced an overrun event since the last read of this register. 1: receive oam cell buffer/fifo has experienced an overrun event since the last read of this register. n ote : this bit-field is only active if the XRT72L71 is operating in the atm uni mode. 6-3 unused ro 0 2 oam interrupt status/ oam cell pending rur/ro 0 oam fifo mode: 0: indicates that the receive oam cell fifo is empty and does not con- tain any new oam cell data. 1: indicates that there at least one unread oam cell exists within the receive oam cell fifo. n ote : if the receive oam cell buffer/fifo is configured to operate in the fifo mode, then this bit-field is read-only. oam buffer mode : 0: indicates that the receipt of oam cell interrupt has not occurred since the last read of this register. 1: indicates that the receipt of oam cell interrupt has occurred since the last read of this register. 1 lcd interrupt status rur 0 0: indicates that the change in lcd condition interrupt has not occurred since the last read of this register. 1: indicates that the change in lcd condition interrupt has occurred since the last read of this register. n ote : this bit-field is only active if the XRT72L71 is operating in the atm uni mode. 0 hec byte error interrupt status rur 0 0: indicates that the detection of hec byte error has not occurred since the last read of this register. 1: indicates that the detection of hec byte error has occurred since the last read of this register. n ote : this bit-field is only active if the XRT72L71 is operating in the atm uni mode. t able 81: r x cp i dle c ell p attern h eader b yte -1 r egister 80 r x cp i dle c ell p attern h eader b yte -1 h ex a ddress : 0 x 50 b it f unction t ype d efault d escription -o peration 7-0 rx idle cell pattern 1 r/w 0x00 this register (along with the rx idle cell mask 1 register) permits the user to specify the idle cell filtering criteria for header byte 1. n otes : 1. this register should be set to 0x00 when the receive cell proces- sor is receiving atm forum standard idle cells. 2. this bit-field is only active if the XRT72L71 is operating in the atm uni mode.
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 80 t able 82: r x cp i dle c ell p attern h eader b yte -2 r egister 81 r x cp i dle c ell p attern h eader b yte -2 h ex a ddress : 0 x 51 b it f unction t ype d efault d escription -o peration 7-0 rx idle cell pattern 2 r/w 0x00 this register (along with the rx idle cell mask 2 register) permits the user to specify the idle cell filtering criteria for header byte 2. n otes : 1. this register should be set to 0x00 when the receive cell proces- sor is receiving atm forum standard idle cells. 2. this bit-field is only active if the XRT72L71 is operating in the atm uni mode. t able 83: r x cp i dle c ell p attern h eader b yte -3 r egister 82 r x cp i dle c ell p attern h eader b yte -3 h ex a ddress : 0 x 52 b it f unction t ype d efault d escription -o peration 7-0 rx idle cell pattern 3 r/w 0x00 this register (along with the rx idle cell mask 3 register) permits the user to specify the idle cell filtering criteria for header byte 3. n otes : 1. this register should be set to 0x00 when the receive cell proces- sor is receiving atm forum standard idle cells. 2. this bit-field is only active if the XRT72L71 is operating in the atm uni mode. t able 84: r x cp i dle c ell p attern h eader b yte -4 r egister 83 r x cp i dle c ell p attern h eader b yte -4 h ex a ddress : 0 x 53 b it f unction t ype d efault d escription -o peration 7-0 rx idle cell pattern 4 r/w 0x01 this register (along with the rx idle cell mask 1 register) permits the user to specify the idle cell filtering criteria for header byte 4. n otes : 1. this register should be set to 0x01 when the receive cell proces- sor is receiving atm forum standard idle cells. 2. this bit-field is only active if the XRT72L71 is operating in the atm uni mode.
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 81 t able 85: r x cp i dle c ell m ask h eader b yte -1 r egister 84 r x cp i dle c ell m ask h eader b yte -1 h ex a ddress : 0 x 54 b it f unction t ype d efault d escription -o peration 7-0 rx idle cell mask 1 r/w 0xff this register, along with the rx idle cell pattern - 1 register permits the user to define idle cell filtering criteria for header byte 1. any 1 in this register, configures the receive cell processor to make the compar- ison between the corresponding bit-field within header byte 1 and the contents of the rx idle cell pattern - 1 register. any 0 in this register, configures the receive cell processor to not perform this comparison: this register should be set to 0xff when the receive cell processor is receiving the atm forum standard idle cells. n ote : this register is only active if the XRT72L71 has been configured to operate in the atm uni mode. t able 86: r x cp i dle c ell m ask h eader b yte -2 r egister 85 r x cp i dle c ell m ask h eader b yte -2 h ex a ddress : 0 x 55 b it f unction t ype d efault d escription -o peration 7-0 rx idle cell mask 2 r/w 0xff this register, along with the rx idle cell pattern - 2 register permits the user to define idle cell filtering criteria for header byte 2. any 1 in this register, configures the receive cell processor to make the compar- ison between the corresponding bit-field within header byte 2 and the contents of the rx idle cell pattern - 2 register. any 0 in this register, configures the receive cell processor to not perform this comparison: this register should be set to 0xff when the receive cell processor is receiving the atm forum standard idle cells. n ote : this register is only active if the XRT72L71 has been configured to operate in the atm uni mode.
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 82 t able 87: r x cp i dle c ell m ask h eader b yte -3 r egister 86 r x cp i dle c ell m ask h eader b yte -3 h ex a ddress : 0 x 56 b it f unction t ype d efault d escription -o peration 7-0 rx idle cell mask 3 r/w 0xff this register, along with the rx idle cell pattern - 3 register permits the user to define idle cell filtering criteria for header byte 3. any 1 in this register, configures the receive cell processor to make the comparison between the corresponding bit-field within header byte 3 and the contents of the rx idle cell pattern - 3 register. any 0 in this register, configures the receive cell processor to not per- form this comparison: this register should be set to 0xff when the receive cell processor is receiving the atm forum standard idle cells. n ote : this register is only active if the XRT72L71 has been configured to operate in the atm uni mode. t able 88: r x cp i dle c ell m ask h eader b yte -4 r egister 87 r x cp i dle c ell m ask h eader b yte -4 h ex a ddress : 0 x 57 b it f unction t ype d efault d escription -o peration 7-0 rx idle cell mask 4 r/w 0xff this register, along with the rx idle cell pattern - 4 register permits the user to define idle cell filtering criteria for header byte 4. any 1 in this register, configures the receive cell processor to make the comparison between the corresponding bit-field within header byte 4 and the contents of the rx idle cell pattern - 4 register. any 0 in this register, configures the receive cell processor to not per- form this comparison: this register should be set to 0xff when the receive cell processor is receiving the atm forum standard idle cells. n ote : this register is only active if the XRT72L71 has been configured to operate in the atm uni mode. t able 89: r x cp u ser c ell f ilter p attern h eader b yte -1 r egister 88 r x cp u ser c ell f ilter p attern h eader b yte -1 h ex a ddress : 0 x 58 b it f unction t ype d efault d escription -o peration 7-0 rxuser cell filter pattern 1 r/w 0x00 this register (along with the rx user cell mask 1 register) permits the user to specify the user cell filtering criteria for header byte 1. n ote : this bit-field is only active if the XRT72L71 is operating in the atm uni mode.
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 83 t able 90: r x cp u ser c ell f ilter p attern h eader b yte -2 r egister 89 r x cp u ser c ell f ilter p attern h eader b yte -2 h ex a ddress : 0 x 59 b it f unction t ype d efault d escription -o peration 7-0 rxuser cell filter pattern 2 r/w 0x00 this register (along with the rx user cell mask 2 register) permits the user to specify the user cell filtering criteria for header byte 2. n ote : this bit-field is only active if the XRT72L71 is operating in the atm uni mode. t able 91: r x cp u ser c ell f ilter p attern h eader b yte -3 r egister 90 r x cp u ser c ell f ilter p attern h eader b yte -3 h ex a ddress : 0 x 5a b it f unction t ype d efault d escription -o peration 7-0 rxuser cell filter pattern 3 r/w 0x00 this register (along with the rx user cell mask 3 register) permits the user to specify the user cell filtering criteria for header byte 3. n ote : this bit-field is only active if the XRT72L71 is operating in the atm uni mode. t able 92: r x cp u ser c ell f ilter p attern h eader b yte -4 r egister 91 r x cp u ser c ell f ilter p attern h eader b yte -4 h ex a ddress : 0 x 5b b it f unction t ype d efault d escription -o peration 7-0 rxuser cell filter pattern 4 r/w 0x00 this register (along with the rx user cell mask 4 register) permits the user to specify the user cell filtering criteria for header byte 4. n ote : this bit-field is only active if the XRT72L71 is operating in the atm uni mode. t able 93: r x cp u ser c ell f ilter m ask h eader b yte -1 r egister 92 r x cp u ser c ell f ilter m ask h eader b yte -1 h ex a ddress : 0 x 5c b it f unction t ype d efault d escription -o peration 7-0 rx user cell filter mask 1 r/w 0xff this register, along with the rx user cell pattern - 1 register permits the user to define user cell filtering criteria for header byte 1. any 1 in this register, configures the receive cell processor to make the comparison between the corresponding bit-field within header byte 1 and the contents of the rx user cell pattern - 1 register. any 0 in this register, configures the receive cell processor to not per- form this comparison: n ote : this register is only active if the XRT72L71 has been configured to operate in the atm uni mode.
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 84 t able 94: r x cp u ser f ilter c ell m ask h eader b yte -2 r egister 93 r x cp u ser f ilter c ell m ask h eader b yte -2 h ex a ddress : 0 x 5d b it f unction t ype d efault d escription -o peration 7-0 rx user cell filter mask 2 r/w 0xff this register, along with the rx user cell pattern - 2 register permits the user to define user cell filtering criteria for header byte 2. any 1 in this register, configures the receive cell processor to make the comparison between the corresponding bit-field within header byte 2 and the contents of the rx user cell pattern - 2 register. any 0 in this register, configures the receive cell processor to not per- form this comparison: n ote : this register is only active if the XRT72L71 has been configured to operate in the atm uni mode. t able 95: r x cp u ser c ell f ilter m ask h eader b yte -3 r egister 94 r x cp u ser c ell f ilter m ask h eader b yte -3 h ex a ddress : 0 x 5e b it f unction t ype d efault d escription -o peration 7-0 rx user cell filter mask 3 r/w 0xff this register, along with the rx user cell pattern - 3 register permits the user to define user cell filtering criteria for header byte 3. any 1 in this register, configures the receive cell processor to make the comparison between the corresponding bit-field within header byte 3 and the contents of the rx user cell pattern - 3 register. any 0 in this register, configures the receive cell processor to not per- form this comparison: n ote : this register is only active if the XRT72L71 has been configured to operate in the atm uni mode. t able 96: r x cp u ser c ell f ilter m ask h eader b yte -4 r egister 95 r x cp u ser c ell f ilter m ask h eader b yte -4 h ex a ddress : 0 x 5f b it f unction t ype d efault d escription -o peration 7-0 rx user cell filter mask 4 r/w 0xff this register, along with the rx user cell pattern - 1 register permits the user to define user cell filtering criteria for header byte 1. any 1 in this register, configures the receive cell processor to make the comparison between the corresponding bit-field within header byte 1 and the contents of the rx user cell pattern - 1 register. any 0 in this register, configures the receive cell processor to not per- form this comparison: n ote : this register is only active if the XRT72L71 has been configured to operate in the atm uni mode.
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 85 t able 97: t x cp c ontrol r egister r egister 96 t x cp c ontrol r egister h ex a ddress : 0 x 60 b it f unction t ype d efault d escription -o peration 7 scrambler enable r/w 1 0: disables scrambling of payload bits 1: enables scrambling of payload bits 6 coset enable r/w 1 0: disables addition of coset polynomial to hec byte 1: enables addition of coset polynomial to hec byte 5 valid cell hec insert enable r/w 1 0: hec byte calculation and insertion is disabled. hence, no modification is performed on the 5th octet within each outbound valid atm cell. 1: hec byte calculation and insertion are enabled. n otes : 1. this register bit-field only applies to valid (e.g., user and oam) cells. 2. this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode. 4 tdp check pattern r/w 1 0: an alternating 0x55/0xaa pattern is expected (as the data path integrity check byte) in the fifth octet position, within each valid cell that is processed by the transmit cell processor. 1: a constant 0x55 pattern is expected (as the data path integrity check byte) in the fifth octet position, within each valid cell that is processed by the transmit cell processor. n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode. 3 gfc insert enable r/w 0 0: the gfc input port is disabled. 1: the gfc input port is enabled. data is read via txgfc serial input pin and is inserted into gfc nibble-field within of each outbound atm cell. n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode. 2 tdp error interrupt enable r/w 0 0: disables the data path integrity check interrupt. 1: enables the data path integrity check interrupt. 1 idle cell hec insert enable r/w 1 0: hec byte calculation and insertion is disabled. hence, no modification is performed on the 5th octet within each outbound idle atm cell. 1: hec byte calculation and insertion are enabled. n otes : 1. this register bit-field only applies to idle cells. 2. this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode. 0 tdp error interrupt status rur 0 0: indicates that the data path integrity check interrupt has not occurred since the last read of this register. 1: indicates that the data path integrity check interrupt has occurred since the last read of this register. n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode.
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 86 t able 98: t x cp oam r egister r egister 97 t x cp oam r egister h ex a ddress : 0 x 61 b it f unction t ype d efault d escription -o peration 7 send oam sem 0 a 0 to 1 transitions configures the transmit cell processor to transmit an oam cell. n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode. 6 tx crc10 enable r/w 0 0: oam cell crc-10 calculation and insertion are disabled. 1: oam cell crc-10 calculation and insertion is enabled. the transmit cell processor will compute and insert the crc-10 value within each out- bound oam cell. n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode. 5-0 unused ro 0x00 t able 99: t x cp hec e rror m ask r egister r egister 98 t x cp hec e rror m ask r egister h ex a ddress : 0 x 62 b it f unction t ype d efault d escription -o peration 7-0 hec error mask r/w 0x00 the transmit cell processor block always xors contents of this register with the contents of the hec byte (within each outbound atm cell). this xored value is then written back into the hec byte field, within each outbound atm cell; prior to transmission. setting any of these bit-fields to 1 introduces error in that specific bit, within each outbound hec byte. register must be set to 0x00 for normal operation, n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode. t able 100: f uture u se r egister 99 f uture u se h ex a ddress : 0 x 63 b it f unction t ype d efault d escription -o peration t able 101: t x cp i dle c ell p attern h eader b yte -1 r egister 100 t x cp i dle c ell p attern h eader b yte -1 h ex a ddress : 0 x 64 b it f unction t ype d efault d escription -o peration 7-0 tx idle cell pattern 1 r/w 0x00 contains pattern for the first header byte of each outbound idle cell. register is set to 0x00 when transmitting standard idle cell pattern. n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode.
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 87 t able 102: t x cp i dle c ell p attern h eader b yte -2 r egister 101 t x cp i dle c ell p attern h eader b yte -2 h ex a ddress : 0 x 65 b it f unction t ype d efault d escription -o peration 7-0 tx idle cell pattern 2 r/w 0x00 contains pattern for the second header byte of each outbound idle cell. register is set to 0x00 when transmitting standard idle cell pattern. n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode. t able 103: t x cp i dle c ell p attern h eader b yte -3 r egister 102 t x cp i dle c ell p attern h eader b yte -3 h ex a ddress : 0 x 66 b it f unction t ype d efault d escription -o peration 7-0 tx idle cell pattern 3 r/w 0x00 contains pattern for the third header byte of each outbound idle cell. register is set to 0x00 when transmitting standard idle cell pattern. n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode. t able 104: t x cp i dle c ell p attern h eader b yte -4 r egister 103 t x cp i dle c ell p attern h eader b yte -4 h ex a ddress : 0 x 67 b it f unction t ype d efault d escription -o peration 7-0 tx idle cell pattern 4 r/w 0x01 contains pattern for the fourth header byte of each outbound idle cell. register is set to 0x01 when transmitting standard idle cell pattern. n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode. t able 105: t x cp i dle c ell p attern h eader b yte -5 r egister 104 t x cp i dle c ell p attern h eader b yte -5 h ex a ddress : 0 x 68 b it f unction t ype d efault d escription -o peration 7-0 tx idle cell pattern 5 r/w 0x52 contains pattern for the fifth header byte of each outbound idle cell. register is set to 0x00 when transmitting standard idle cell pattern. n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode. t able 106: t x cp i dle c ell p ayload r egister r egister 105 t x cp i dle c ell p ayload r egister h ex a ddress : 0 x 69 b it f unction t ype d efault d escription -o peration 7-0 tx idle cell payload r/w 0x5a this register contains the value of the payload bytes within each outbound idle cell. the contents of this register will be repeated 48 times, when filling the payload of each outbound idle cell. pregister is set to 0x5a when transmitting standard idle cell pattern. n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode.
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 88 t able 107: utopia c onfiguration r egister r egister 106 utopia c onfiguration r egister h ex a ddress : 0 x 6a b it f unction t ype d efault d escription -o peration 7-6 unused ro 0 5 handshake mode r/w 0 0: transmit and receive utopia interface blocks operate in the octet-level handshake mode 1: transmit and receive utopia interfaces blocks operate in the cell-level handshake mode n ote : this bit-field is ignore if the XRT72L71 is configured to operate in the clear-channel framer mode, or if the chip is configured to operate in the multi-phy mode. 4m phy r/w 1 0: transmit and receive utopia interface block operates in the single- phy mode 1: transmit and receive utopia interface block operates in the multi-phy mode n ote : t his bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode. 3 cell of 52bytes r/w 0 0: transmit and receive utopia interface blocks process 53 bytes/cell when the utopia data bus width is set to 8 bits. the transmit and receive utopia interface blocks process 54 bytes when the utopia data bus width is set to 16 bits. 1: transmit and receive utopia interface blocks process 52 bytes/cell, independent of the utopia data bus width. n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode. 2 tx fifo depth(1) r/w 0 00: operating depth of transmit fifo is 16 cells 01: operating depth of transmit fifo is 12 cells 10: operating depth of transmit fifo is 8 cells 11: operating depth of transmit fifo is 4 cells n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode. 1 tx fifo depth(0) r/w 0 0 utopia width16 r/w 0 0: transmit and receive utopia data bus width is configured to be 8 bits. 1: transmit and receive utopia data bus width is configured to be16 bits. n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode.
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 89 t able 108: r x utopia i nterrupt e nable /s tatus r egister r egister 107 r x utopia i nterrupt e nable /s tatus r egister h ex a ddress : 0 x 6b b it f unction t ype d efault d escription -o peration 7unused ro 0 6 r fifo reset r/w 0 0: normal operation a 0 to 1 transition resets the read-write pointers and fifo memory n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode. 5 rx fifo overrun interrupt enable r/w 0 0: disables the rx fifo over-run interrupt. 1: enables the rx fifo over-run interrupt. n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode. 4 rx fifo underrun inter- rupt enable ro 0 0: disables the rx fifo under-run interrupt. 1: enables the rx fifo under-run interrupt. n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode. 3 rcoca interrupt enable r/w 0 0: disables the detection of rxrunt cell interrupt. 1: enables the detection of rxrunt cell interrupt. n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode. 2 r fifo ovr interrupt sta- tus rur 0 0: indicates that the rxfifo overrun interrupt has not occurred since the last read of this register. 1: indicates that the rxfifo overrun interrupt has occurred since the last read of this register. n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode. 1 r fifo under interrupt status ro 0 0: indicates that the rxfifo underrun interrupt has not occurred since the last read of this register. 1: indicates that the rxfifo underrun interrupt has occurred since the last read of this register. n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode. 0 rcoca interrupt stats rur 0 0: indicates that the detection of runt cell interrupt has not occurred since the last read of this register. 1: indicates that the detection of runt cell interrupt has occurred since the last read of this register. n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode. t able 109: r x utopia a ddress r egister 108 r x utopia a ddress h ex a ddress : 0 x 6c b it f unction t ype d efault d escription -o peration 7-5 unused ro 000 4-0 rx utopia address r/w 00000 programmable rx utopia address register to select device
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 90 t able 110: r x utopia fifo s tatus r egister r egister 109 r x utopia fifo s tatus r egister h ex a ddress : 0 x 6d b it f unction t ype d efault d escription -o peration 7 rx fifo 16 r/w 0 0: operating depth of rxfifo is 4 cells deep. 1: operating depth of rxfifo is 16 cells deep. n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode. 6 reserved r/w 0 set to 0 4-2 unused ro 0 1 rx fifo full ro 0 0: rxfifo is not full 1: rxfifo is full and if next event is not a read operation, it may cause over- run. n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode. 0 rx fifo empty ro 1 0: rxfifo is not empty 1: rxfifo is empty and any subsequent read operation may cause and under-run to occur. n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode.
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 91 t able 111: t x utopia i nterrupt /s tatus r egister r egister 110 t x utopia i nterrupt /s tatus r egister h ex a ddress : 0 x 6e b it f unction t ype d efault d escription -o peration 7 tx fifo reset r/w 0 0 to 1 transition resets internal fifo memory and its read-write pointers. n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode. 6 discard upon perr r/w 0 0: transmit utopia parity errors do not result in cell discard 1: cells in which a transmit utopia parity error is detected are discarded. n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode. 5 tx parity error interrupt enable r/w 0 0: disables the transmit utopia detection of parity error interrupt. 1: enables the transmit utopia detection of parity error interrupt. n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode. 4 tx fifo overrun interrupt enable r/w 0 0: disables the txfifo overrun interrupt. 1: enables the txfifo overrun interrupt. n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode. 3 tc out of cell alignment interrupt enable r/w 0 0: disables the detection of txrunt cell interrupt. 1: enables the detection of txrunt cell interrupt. n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode. 2 tp error interrupt status rur 0 0: indicates that the detection of transmit utopia - parity error interrupt has not occurred since the last read of this register. 1: indicates that the detection of transmit utopia - parity error interrupt has occurred since the last read of this register. n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode. 1 tx fifo interrupt status rur 0 0: indicates that the txfifo overrun interrupt has not occurred since the last read of this register. 1: indicates that the txfifo overrun interrupt has occurred since the last read of this register. n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode. 0 tc oca interrupt status rur 0 0: indicates that the detection of txrunt cell interrupt has not occurred since the last read of this register. 1: indicates that the detection of txrunt cell interrupt has occurred since the last read of this register. n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode. t able 112: f uture u se r egister 111 f uture u se h ex a ddress : 0 x 6f b it f unction t ype d efault d escription -o peration
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 92 t able 113: t x utopia a ddress r egister 112 t x utopia a ddress h ex a ddress : 0 x 70 b it f unction t ype d efault d escription -o peration 7-5 unused ro 000 4-0 tx utopia address r/w 00000 programmable tx utopia address register for device selection t able 114: t x utopia s tatus r egister r egister 113 t x utopia s tatus r egister h ex a ddress : 0 x 71 b it f unction t ype d efault d escription -o peration 7-2 unused ro 0 1 tx fifo full ro 0 0: indicates that the tx fifo is not full. 1: indicates that the tx fifo is full and that the next write operation may cause an overrun in the txfifo. n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode. 0 tx fifo empty ro 1 0: indicates that the txfifo is not empty 1: indicates that the txfifo is empty n ote : this bit-field is only active if the XRT72L71 is configured to operate in the atm uni mode.
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 93 t able 115: l ine i nterface d rive r egister r egister 114 l ine i nterface d rive r egister h ex a ddress : 0 x 72 b it f unction t ype d efault d escription -o peration 7 reserved r/w 0 6 reserved r/w 0 5 reqb r/w 0 this read/write bit-field permits the user to control the state of the reqb output pin. the reqb output pin can be connected to the reqb input pin of the xrt7300 and xrt73l00 device. 0: sets the reqb output pin to 0. if this output pin is connected to the reqb input pin of the liu ic, then this setting will enable the receive equalizer within the liu ic. 1: sets the reqb output pin to 1. if this output pin is connected to the reqb input pin of the liu ic, then this setting will disable the receive equalizer within the liu ic. n ote : for guidelines on when to enable or disable the receive equalizer, within the liu ic, please consult the xrt7300 or the xrt73l00 data sheet. 4taos r/w 0 this read/write bit-field permits the user to control the state of the taos output pin. the taos output pin can be connected to the taos input pin of the xrt7300 and xrt73l00 devices. 0: sets the taos output pin to 0. if this output pin is connected to the taos input of the liu ic, then this setting will configure the transmit sec- tion of the liu ic to transmit an all ones pattern. 1: sets the taos output pin to 1. if this output pin is connected to the taos input pin of the liu ic, then this setting will not configure the trans- mit section of the liu ic to transmit an all ones pattern. 3 encodis r/w 1 this read/write bit-field permits the user to control the state of the enco- dis output pin. the encodis output pin can be connected to both the encodis and decodis input pins of the xrt7300 device, or the end- ecdis input pin of the xrt73l00 device. 0: sets the encodis output pin to 0. if this output pin is connected to the (encodis and decodis) or endecdis input pins of the liu ic, then this settting will enable the hdb3/b3zs encoder/decoder blocks within the liu ic. 1: sets the encodis output pin to 1. if this output pin is connected to the (encodis and decodis) or endecdis input pins fo the liu ic, then this setting will disable the hdb3/b3zs encoder/decoder blocks within the liu ic. 2 tx lev r/w 0 this read/write bit-field permits the user to control the state of the txlev output pin. the txlev output pin can be connected to the txlev input pin of the xrt7300 or the xrt73l00 device. 0: sets the txlev output pin to 0. if this output pin is connected to the txlev input pin of the liu ic, then this setting will enable the transmit line build-out circuit, within the transmit section of the liu ic. 1: sets the txlev output pin to 1. if this output pin is connected to the txlev input of the liu ic, then this setting will disable the transmit line build-out circuit, within the transmit section of the liu ic. n ote : for guidelines on when to enable or disable the transmit line build- out circuit, within the liu ic, please consult either the xrt7300 or the xrt73l00 data sheet.
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 94 1 rloop r/w 0 this read/write bit-field permits the user to control the state of the rloop output pin. the rloop output pin can be connected to the rloop input pin of the xrt7300 or the xrt73l00 device. 0: sets the rloop output pin to 0. if this output pin is connected to the rloop input of the liu ic, then a variety of liu loop-back modes can be configured via this register bit. 1: sets the rloop output pin to 1. n ote : for information on the various loopback modes, which are available via the xrt7300 and xrt73l00 device, please consult the xrt7300 or the xrt73l00 data sheet. 0 lloop r/w 0 this read/write bit-field permits the user to control the state of the lloop output pin. the rloop output pin can be connected to the lloop input pin of the xrt7300 or the xrt73l00 device. 0: sets the lloop output pin to 0. if this output pin is connected to the lloop input of the liu ic, then a variety of liu loop-back modes can be configured via this register bit. 1: sets the lloop output pin to 1. n ote : for information on the various loopback modes, which are available via the xrt7300 and xrt73l00 device, please consult the xrt7300 or the xrt73l00 data sheet. t able 115: l ine i nterface d rive r egister r egister 114 l ine i nterface d rive r egister h ex a ddress : 0 x 72 b it f unction t ype d efault d escription -o peration
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 95 line interface scan register provides ds3uni framer chip capability to monitor status of line interface units. configuration in this register is connected directly to the corresponding discrete i/o pins. note: these signals drive and scan the line interface chip xrt7300. t able 116: l ine i nterface s can r egister r egister 115 l ine i nterface s can r egister h ex a ddress : 0 x 73 b it f unction t ype d efault d escription -o peration 7-3 unused ro 0 2 dmo ro 0 this read-only bit-field permits the user to determine the current state of the dmo input pin. this input pin can be connected to the dmo output pin of either the xrt7300 or the xrt73l00 device. 0: indicates that the current state of the dmo input pin is low. if this input pin is connected to the dmo output of the liu ic, then this may indi- cate the occurrence of a fault condition in the transmit output line. 1: indicates that the current state of the dmo input pin is high. if this input pin is connected to the dmo output of the liu ic, then this may indi- cate the occurrence of normal operation in the transmit output line. n ote : for more detailed information on the behavior of the dmo output pin (from the liu), please consult either the xrt7300 or the xrt73l00 data sheet. 1rlol ro 0 this read-only bit-field permits the user to determine the current state of the rlol input pin. this input pin can be connected to the rlol output pin of either the xrt7300 or the xrt73l00 device. 0: indicates that the current state of the rlol input pin is low. if this input pin is connected to the rlol output of the liu ic, then it indicates that the clock recovery pll (within the liu ic) is locked onto the incom- ing ds3 line signal. 1: indicates that the current state of the rlol input pin is high. if this input pin is connected to the rlol output of the liu ic, then it indicates that the clock recovery pll (within the liu ic) is not locked onto the incoming ds3 line signal. n ote : for more detailed information on the behavior of the rlol output pin (from the liu), please consult either the xrt7300 or the xrt73l00 data sheet. 0rlos ro 0 this read-only bit-field permits the user to determine the current state of the rlos input pin. this input pin can (and should be) connected to the rlos output pin of either the xrt7300 or the xrt73l00 device. 0: indicates that the current state of the rlos input pin is low. if this input pin is connected to the rlos output pin of the liu ic, then it indi- cates that the liu is not currently declaring an los (loss of signal) condi- tion. 1: indicates that the current state of the rlos input pin is high. if this input pin is connected to the rlos output pin of the liu ic, then it indicates that the liu is currently declaring an los condition. n otes : 1. if this input pin is pulled high, then the XRT72L71 will automatically declare an los condition. as a conse- quence, the user should not treat the the rlos input pin as a general purpose input pin. 2. for more detailed on the los declaration criteria for the xrt7300 or the xrt73l00 device, please consult either the xrt7300 or the xrt73l00 data sheet.
XRT72L71 ? ? ? ? ds3 atm uni/clear channel framer rev. 1.1.0 96 . t able 117: pmon cp-b it e rror e vent c ount r egister - msb r egister 116 pmon cp-b it e rror e vent c ount r egister - msb h ex a ddress : 0 x 74 b it f unction t ype d efault d escription -o peration 7-0 cp-bit error count high- byte rur 0x00 this reset-upon-read register, along with pmon cp-bit error count register - lsb contains the 16 bit value for the total number of cp bit errors that have been detected since the last read of this register. this register contains the high byte value of this 16-bit expression. t able 118: pmon cp-b it e rror e vent c ount r egister - lsb r egister 117 pmon cp-b it e rror e vent c ount r egister - lsb h ex a ddress : 0 x 75 b it f unction t ype d efault d escription -o peration 7-0 cp-bit error count low- byte rur 0x00 this reset-upon-read register, along with pmon cp-bit error count register - msb contains the 16 bit value for the total number of cp bit errors that have been detected since the last read of this register. this reg- ister contains the low byte value of this 16-bit expression. t able 119: f rame cp-b it e rrors - o ne s econd a ccumulator r egister - msb r egister 118 f rame cp-b it e rrors - o ne s econd a ccumulator r egister - msb h ex a ddress : 0 x 76 b it f unction t ype d efault d escription -o peration 7-0 cp- bit err 1 sec h ro 0x00 this read-only register, along with cp-bit errors - one second accmula- tor register - lsb contains the 16-bit expression for the total number of cp- bit errors that have been detected within the last one second accumulation period. this register contains the high byte value of this expression. t able 120: f rame cp-b it e rrors - o ne s econd a ccumulator r egister - lsb r egister 119 f rame cp-b it e rrors - o ne s econd a ccumulator r egister - lsb h ex a ddress : 0 x 77 b it f unction t ype d efault d escription -o peration 7-0 cp- bit err 1 sec l ro 0x00 this read-only register, along with cp-bit errors - one second accmula- tor register - msb contains the 16-bit expression for the total number of cp-bit errors that have been detected within the last one second accumula- tion period. this register contains the low byte value of this expression. t able 121: u nused r egister 120 to 133 u nused h ex a ddress : 0 x 78 h to 0 x 85 b it f unction t ype d efault d escription -o peration
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 97 ordering information p art n umber p ackage o perating t emperature r ange XRT72L71iq160 28 x28 mm plastic qfp -40c to +85c package dimensions p
? ? ? ? XRT72L71 ds3 atm uni/clear channel framer rev. 1.1.0 98 notice exar corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no represen- tation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration purposes and may vary depending upon a users specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support sys- tem or to significantly affect its safety or effectiveness. products are not authorized for use in such applica- tions unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corpo- ration is adequately protected under the circumstances. copyright 2002 exar corporation datasheet august 2002. reproduction, in part or whole, without the prior written consent of exar corporation is prohibited. revision history r ev . # d ate d escription 1.0.1 september 2000 made edits to device name, general information and added description for test mode pin. p1.0.2 september 2000 added additional sections on functional descriptions p1.0.3 october 2000 added timing diagrams, expanded block diagram and table of registers. p1.0.4 december 2000 created long-shortform data sheet from p1.0.3 removing sections, and adding table of registers. changed electrical spec/definition of t78, t79, t80, t78, t81 and t82. replaced figures 17 and 18. p1.0.5 december 2000 added register summary list, made typo corrections to text and figures. 1.1.0 august 2002 removed preliminary designation. deleted ioc and ill from dc electrical characteris- tics.

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