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1 smbus interfaced battery charger with internal fets isl95871c the isl95871c is a highly integrated lithium-ion battery charger controller, programmable over the system management bus (smbus) with internal switching fets. high efficiency is achieved with a dc/dc synchronous-rectifier buck converter, equipped with diode emulation for enhanced light load efficiency and system bus boosting prevention. the isl95871c charges one to four lithium-ion series cells, and delivers up to 8a charge current. integrated mosfets and bootst rap diode result in fewer components and smaller implementation area. low offset current-sense amplifiers provide high accuracy with 10m sense resistors. the isl95871c provides 0.5% battery voltage accuracy. the isl95871c also provides a di gital output that indicates the presence of the ac-adapter as well as an analog output which indicates the adapter current within 4% accuracy. applications ? notebook computers ? tablet pcs ? portable equipment with rechargeable batteries features ? internal synchronous buck output stage power fets ? 0.5% battery voltage accuracy ? 3% adapter current limit accuracy ? 3% charge current accuracy ? smbus 2-wire serial interface ? battery short circuit protection ? fast response for pulse-charging ? fast system-load transient response ? monitor outputs - adapter current (3% accuracy) - ac-adapter detection ? 11-bit battery voltage setting ? 6 bit charge current/adapter current setting ? 8a maximum battery charger current ? 11a maximum adapter current ? +8v to +22v adapter voltage range ? pb-free (rohs compliant) related literature ? see an1590 , isl95871c evaluation board user guide figure 1. efficiency vs ch arge current and battery voltage (efficiency dcin = 20v) figure 2. derating curve with natural air flow (measured on 10cm x 10cm evaluation board) 60 65 70 75 80 85 90 95 100 023468 charge current (a) efficiency (%) 157 1 cell 2 cell 4 cell 3 cell 0 1 2 3 4 5 6 7 8 9 0 25 50 75 100 125 150 ambient temperature (c) charge current (a) 1 cell 2 cell 4 cell 3 cell june 8, 2011 fn6856.2 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2010, 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl95871c 2 fn6856.2 june 8, 2011 pin configuration isl95871c (50 ld 5x7 qfn) top view 1 2 3 4 5 6 7 50 49 48 47 46 45 44 17 18 19 20 21 23 vfb csop dcin nc phase phase nc vin vin icm acok scl agnd sda phase nc vcomp nc vddsmb agnd cson 43 24 vin icomp 8 9 10 11 12 vddp pgnd vddp agnd phase 41 40 39 38 37 36 35 34 33 32 31 30 nc agnd csin vdd acin agnd csip ugate vin ugate boot vin vddp dcin3 vin phase phase7 51 52 49 55 42 25 vin vref 22 phase 54 ugate 53 29 vin 28 vin 27 vin 26 vin 13 pgnd 14 pgnd 15 pgnd 16 pgnd pin descriptions pin number symbol description 1, 8, 37, 51 agnd analog ground. connect directly to the backsi de paddle. connect to pgnd and the system ground plane under the ic. 2 acok ac-adapter detection output. this open drain output is high impedance when acin is greater than 3.2v. the acok output remains low when the isl95871c is powe red down. connect a 10k pull-up resistor from acok to vddsmb. range: 0v to 5v. 3 vfb battery voltage remote sense. connect to the battery pack positive terminal. 4 cson charge current-sense negative input. range: zero to battery voltage. 5 csop charge current-sense positive input. range: zero to battery voltage. 6 dcin charger bias supply input. bypass dcin with a 0. 1f capacitor to agnd. range: zero to adapter voltage. 7, 21, 39, 45, 50 nc no connection. pins 7, 21, 39, 45 and 50 are not connected. 9, 10, 52 vddp linear regulator output. vddp is the output of the 5.2v linear regulator supplied from dcin. vddp also directly supplies the lfet gate driver and the boot strap diode. bypass with a 1f ceramic capacitor from vddp to pgnd. range: zero to 5.3v. 11, 17, 18, 19, 20, 54 phase output inductor connection. connected to the source of the internal high-side n-channel mosfet source and low-side n-channel mosfet drain. range: 1 diode drop below ground to 1 diode drop above adapter voltage. 12, 13, 14, 15, 16 pgnd power ground. connect pgnd to the source of the low side mosfet and to the system ground plane.
isl95871c 3 fn6856.2 june 8, 2011 22, 23, 24, 25, 26, 27, 28, 29, 30, 55 vin power input to the switching fets connected to the drai n of internal upper fet. a very low esr capacitor should be place from the vin pins to the pgnd pins. range: min battery voltage to adapter voltage. 32, 33, 53 ugate upper gate of the internal power fet. a 4700p f cap must be placed between ugate and phase. range: 1 diode drop below ground to 5.3v above adapter voltage. 34 boot high-side power mosfet driver power-supply connec tion. connect a 0.1f capacitor from boot to phase. range: 1 diode drop below ground to 5.3v above adapter voltage. 35 vdd power input for internal analog circuits. connect a 4.7 resistor from vdd to vddp and a 1f ceramic capacitor from vdd to agnd. range: 0v to 5.3v. 36 csin input current-sense negative input. range: battery voltage to adapter voltage. 38 csip input current-sense positive input. range: battery voltage to adapter voltage. 40 acin ac-adapter detection input. connect to a resistor divider from the ac-adapter output. output switching is disabled when acin is below it threshold. the divider sh ould be designed to pull acin above its threshold when the adapter voltage is above battery voltage. range: 0v to 5v. 42 vref 3.2v internal reference voltage. place a 0.1f cera mic capacitor from vref to agnd pin close to the ic. 43 icomp compensation point for the charging current and ad apter current regulation loop. connect 0.01f to agnd. see the ?charge current control loop? on page 21 for details of selecting the icomp capacitor. range: 0v to 5.3v. 44 vcomp compensation point for the voltage regulation loop. co nnect a resistor in series with a small ceramic capacitor to agnd, typically 4.7k in series with 0.01f. see ?voltage control loop? on page 22 for details on selecting vcomp components. range: 0v to 5v. 46 icm input current monitor output. icm voltage equals 20 x (v csip - v csin ). range: 0v to 5v. 47 sda smbus data i/o. open-drain output. connect an exte rnal pull-up resistor according to smbus specifications. range: 0v to 5v. 48 scl smbus clock input. connect an external pull-up resistor according to smbus specifications. range: 0v to 5v. 49 vddsmb smbus interface supply voltage input. bypass with a 0.1f capacitor to agnd. range: 0v to 5v. 51, 52, 53, 54, 55 back side paddles 5 terminals on the back side of the package provide additional electrical and thermal connec tion to isl95871c agnd, vddp, ugate, phase and vin. phase and vin paddles are the lowest thermal resistance from the switching mosfets and should relatively large areas of copper to have low thermal resistance from the fets to the pcb and the ambient air. the agnd padd le is the lowest thermal resistance from the control ic and should be connected to a relatively large area of copper to have low thermal resistance from the fets to the pcb and the ambient air. pin descriptions (continued) pin number symbol description ordering information part number (notes 1, 2, 3) part marking temp range (c) package (pb-free) pkg. dwg. # isl95871chrz isl 95871chrz -10 to +100 50 ld 5x7 qfn l50.5x7 notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ specia l pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). in tersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requir ements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl95871c . for more information on msl please see techbrief tb363 .
isl95871c 4 fn6856.2 june 8, 2011 figure 3. functional block diagram daci vref + - gmi icm vin ugate phase vddp pgnd gnd boot vddsmb sda scl csip csin icomp csop cson vfb vcomp + - 20x + - 20x dacs + - gms dacv + - gmv 11 6 6 dacv daci dacs smbus en acin acok vref + - reference vddp vddp reg dcin vddp vddp 100k 500k min current buffer min voltage buffer feed forward pulse width modulator acok en phase boot vin pgnd isl95871c csin csip csop cson acin scl vref dcin sda vddsmb icm icomp vcomp vdd acok vddp agnd ac-adapter smart to system host vfb r s1 r s2 agnd pgnd agnd figure 4. typical application circuit pgnd scl sda battery ugate agnd r vcomp c vcomp c icomp in-rush limit circuit
isl95871c 5 fn6856.2 june 8, 2011 table of contents absolute maximum ratings.............................................................. 6 thermal information .......................................................................... 6 recommended operating conditions ............................................. 6 smbus timing specification ............................................................. 8 typical operating performance.........................................................9 theory of operation ......................................................................... 12 introduction ................................................................................. 12 pwm control................................................................................ 12 ac-adapter detection................................................................. 12 current measurement................................................................ 12 vddp regulator .......................................................................... 12 vddsmb supply .......................................................................... 12 short circuit protection and 0v battery charging ................. 12 undervoltage detect and batte ry trickle charging ............... 12 over-temperature protection ................................................... 12 overvoltage protection .............................................................. 12 the system management bus.................................................. 13 general smbus architecture..................................................... 13 data validity ................................................................................ 13 start and stop conditions............................................................. 13 acknowledge........................................................................................ 13 smbus transactions........................................................................... 14 byte format ................................................................................. 14 isl95871c and smbus.............................................................. 14 battery charger registers ......................................................... 14 enabling and disabling charging ............................................. 14 setting charge voltage .............................................................. 15 setting charge current .............................................................. 17 setting input-current limit........................................................ 18 charger timeout ......................................................................... 19 isl95871c data byte order ..................................................... 19 writing to the internal registers .............................................. 19 reading from the internal registers ....................................... 19 application information................................................................... 19 inductor selection ...................................................................... 19 output capacitor selection ....................................................... 19 snubber design .......................................................................... 20 input capacitor selection.......................................................... 20 loop compensation design...................................................... 20 transconductance amplifiers gmv, gmi and gms ............... 20 pwm gain fm ............................................................................. 20 charge current control loop .................................................... 21 adapter current limit control loop......................................... 21 voltage control loop.................................................................. 22 output lc filter transfer functions ......................................... 22 compensation break frequency equations ........................... 23 pcb layout considerations ............................................................. 23 power and signal layers placement on the pcb........................ 23 component placement.............................................................. 23 signal ground and power ground connection....................... 23 agnd and vdd pin..................................................................... 24 pgnd pins ................................................................................... 24 phase pins.................................................................................. 24 boot pin...................................................................................... 24 csop, cson, csip and csin pins ............................................ 24 dcin pin....................................................................................... 24 copper size for the phase node .............................................. 24 identify the power and signal ground .................................... 24 clamping capacitor for switching mosfet............................ 24 revision history ................................................................................ 25 products ............................................................................................. 25 package outline drawing ............................................................... 26
isl95871c 6 fn6856.2 june 8, 2011 absolute maximum rating s thermal information dcin, csip, csin, csop, cson, vin to pgnd . . . . . . . . . . . . . . . -0.3v to +28v dcin, csip, csin, vin to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +28v csop, cson, vfb to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +28v csip-csin, csop-cson, pgnd-agnd . . . . . . . . . . . . . . . . . . -0.3v to +0.3v phase-pgnd and vin-phase . . . . . . . . . . . . . . . . . . . . . . . . . . . -6v to +28v ugate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . phase - 0.3v to boot + 0.3v boot to pgnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +33v boot to phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6v icomp, vcomp, vref, to agnd. . . . . . . . . . . . . . . . . . . .-0.3v to vdd + 0.3v vddsmb, scl, sda, acin, acok to agnd . . . . . . . . . . . . . . . . -0.3v to +6v vdd to agnd, vddp to pgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6v thermal resistance (typical) ja (c/w) jc (c/w) 50 ld 5x7 qfn package (notes 4, 5) . . . . . . 32 2 operating junction temperature range . . . . . . . . . . . . . .-10c to +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions ambient temperature (see figure 11). . . . . . . . . . . . . . . .-10c to +100c supply voltage dcin and vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8v to 22v vddsmb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.5v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured with the component mounted on a high effective ther mal conductivity test board in free air. see tech brief tb379 f or details. 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications vin = dcin = v csip = v csin = 19v, v csop = v cson = 12v, vddp = 5.1v, v boot -v phase = 5v, agnd = pgnd = 0v, vddsmb = 5v. all typical specifications t a = +25c. boldface limits apply over the junction temperature range, -10c to +125c. parameter conditions min (note 6) typ max (note 6) units charge voltage regulation battery full charge voltage and accuracy chargevoltage = 0x41a0 16.716 16.8 16.884 v -0.5 0.5 % chargevoltage = 0x3130 12.529 12.592 12.655 v -0.5 0.5 % chargevoltage = 0x20d0 8.358 8.4 8.442 v -0.5 0.5 % chargevoltage = 0x1060 4.163 4.192 4.221 v -0.7 0.7 % battery trickle charge threshold vfb rising 2.55 2.7 2.85 v battery trickle charge threshold hysteresis 100 200 400 mv charge current regulation csop to cson full-scale current-sense voltage 78.22 80.64 83.06 mv charge current and accuracy rs2 = 10m (see figure 4) chargecurrent = 0x1f80 cson from 0v to 19.2v 7.822 8.064 8.306 a -3 3 % rs2 = 10m (see figure 4) chargecurrent = 0x0f80 cson from 0v to 19.2v 3.849 3.968 4.087 a -3 3 % rs2 = 10m (see figure 4) chargecurrent = 0x0080 cson from 0v to 19.2v 64 128 220 ma charge current gain error based on charge current = 128ma and 8.064a -1.6 1.4 %
isl95871c 7 fn6856.2 june 8, 2011 battery quiescent current adapt er present, not charging, i csop + i cson + i phase + i fb v phase = v cson = v csop = v dcin = 19v, v acin =5v 0.1 2 a adapter absent i csop + i cson + i phase + i csip + i csin + i fb v phase = v cson = v csop = 19v, v dcin = 0v 0.1 2 a adapter quiescent current i dcin + i csip + i csin v adapter = 8v to 22v 2.5 5 ma vin leakage current phase = 0v, vin = 22v 0.3 1.5 a input current regulation csip to csin full-scale current-sense voltage v csip = 19v 106.7 110.08 113.3 mv input current accuracy rs1 = 10m (see figure 4) adapter current = 11008ma or 3584ma -3 3 % rs1 = 10m (see figure 4) adapter current = 2048ma -5 5 % input current limit gain error based on inputcurrent = 1024ma and 11008ma -2 2 % input current limit offset -1 1 mv icm gain v csip- v csin = 110mv 19.9 v/v icm accuracy v csip- v csin = 110mv -2.5 2.5 % v csip- v csin = 55mv or 35mv -4 4 % v csip- v csin = 20mv -8 8 % icm load regulation v csip- v csin = 0.1v, icm load from zero to 500a 10 mv supply and linear regulator vddp output voltage 8.0v < v dcin < 22v, no load 4.95 5.1 5.23 v vddp load regulation 0 < i vddp < 30ma 35 100 mv vddsmb uvlo rising 2.3 2.5 2.61 v vddsmb uvlo falling 2.2 2.4 2.5 v vddsmb uvlo hysteresis 100 mv vdd uvlo rising 4.25 4.5 4.65 v vdd uvlo hysteresis 150 280 400 mv vddsmb quiescent current vddp = scl = sda = 5.5v 20 27 a voltage reference vref output voltage 0 < i vref < 300a 3.168 3.2 3.232 v acok acok sink current v acok = 0.4v, acin = 1.5v 2 8ma acok leakage current v acok = 5.5v, acin = 2.5v 1 a acin acin rising threshold 3.15 3.2 3.28 v acin threshold hysteresis 40 60 90 mv acin input leakage current acin = 3.7v 1 a electrical specifications vin = dcin = v csip = v csin = 19v, v csop = v cson = 12v, vddp = 5.1v, v boot -v phase = 5v, agnd = pgnd = 0v, vddsmb = 5v. all typical specifications t a = +25c. boldface limits apply over the junction temperature range, -10c to +125c. (continued) parameter conditions min (note 6) typ max (note 6) units
isl95871c 8 fn6856.2 june 8, 2011 switching regulator frequency 330 400 440 khz dead time 50 ns error amplifiers gmv amplifier transconductance 200 250 300 a/v gmi amplifier transconductance 40 50 60 a/v gms amplifier transconductance 40 50 60 a/v gmi/gms saturation current 15 20 25 a gmv saturation current 10 17 30 a icomp, vcomp clamp voltage 0.25v < v icomp, v vcomp < 3.5v 200 300 400 mv logic levels sda/scl input low voltage vddsmb = 2.7v to 5.5v 0.8 v sda/scl input high voltage vddsmb = 2.7v to 5.5v 2 v sda/scl input bias current vddsmb = 2.7v to 5.5v 1 a sda, output sink current v sda = 0.4v 7 15 ma note: 6. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. temperature limits established by characterization and are not production tested. electrical specifications vin = dcin = v csip = v csin = 19v, v csop = v cson = 12v, vddp = 5.1v, v boot -v phase = 5v, agnd = pgnd = 0v, vddsmb = 5v. all typical specifications t a = +25c. boldface limits apply over the junction temperature range, -10c to +125c. (continued) parameter conditions min (note 6) typ max (note 6) units smbus timing specification vddsmb = 2.7v to 5.5v parameters symbol conditions min typ max units smbus frequency fsmb 10 100 khz bus free time t buf 4.7 s start condition hold time from scl thd:sta 4 s start condition setup time from scl tsu:sta 4.7 s stop condition setup time from scl tsu:sto 4 s sda hold time from scl thd:dat 300 ns sda setup time from scl tsu:dat 250 ns scl low timeout (note 7) t timeout 22 25 30 ms scl low period t low 4.7 s scl high period t high 4 s maximum charging period without a smbus write to chargevoltage or chargecurrent register 140 175 220 s notes: 7. if scl is low for longer than the sp ecified time, the charger is disabled. 8. limits established by characteriza tion and are not production tested.
isl95871c 9 fn6856.2 june 8, 2011 typical operating performance dcin = 19v, 3s2p li-battery, t a = +25 c , unless otherwise noted. figure 5. vddp load regulation figure 6. typical charging voltage and current figure 7. icm accuracy vs ac-adapter current figure 8. efficiency vs charge current and battery voltage (efficiency dcin = 20v) figure 9. charge current accuracy figure 10. charge voltage accuracy 4.90 4.95 5.00 5.05 5.10 5.15 0 102030405060708090100 vddp load current (ma) vddp (v) 10.0 10.5 11.0 11.5 12.0 12.5 13.0 0 20 40 60 80 100 120 140 160 battery voltage (v) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 charge current (a) battery voltage (v) charge current time (minutes) -15 -10 -5 0 5 10 15 0 234 678 adapter current (a) icm accuracy(%) 15 60 65 70 75 80 85 90 95 100 023468 charge current (a) efficiency (%) 157 1 cell 2 cell 4 cell 3 cell -4 -3 -2 -1 0 1 2 3 4 2 4 6 8 10 12 14 16 18 battery voltage (v) charge current accuracy(%) charge current = 2.048a charge current = 4.096a charge current = 6.016a charge current = 8.064a -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 2 45678 charge current (a) charge voltage accuracy (%) 2 cell 3 cell 4 cell 1 cell 13
isl95871c 10 fn6856.2 june 8, 2011 figure 11. derating curve with natural air flow (measured on 10cm x 10cm evaluation board) figure 12. derating curve with 200lfm air flow (measured on 10cm x 10cm evaluation board) figure 13. switching waveforms in diode emulation mode figure 14. switching waveforms in cc mode figure 15. charge enable: write 1f80 (8.064a) to chargecurrent register figure 16. charge disable: write 0000 (0a) to chargecurrent register typical operating performance dcin = 19v, 3s2p li-battery, t a = +25 c , unless otherwise noted. (continued) 0 1 2 3 4 5 6 7 8 9 0 25 50 75 100 125 150 ambient temperature (c) charge current (a) 1 cell 2 cell 4 cell 3 cell 0 1 2 3 4 5 6 7 8 9 0 25 50 75 100 125 150 ambient temperature (c) charge current (a) 1 cell 2 cell 4 cell 3 cell phase ugate-phase inductor current phase ugate-phase inductor current vcomp charge current sda icomp vcomp icomp sda charge current
isl95871c 11 fn6856.2 june 8, 2011 figure 17. battery removal figure 18. battery insertion figure 19. system load transient response typical operating performance dcin = 19v, 3s2p li-battery, t a = +25 c , unless otherwise noted. (continued) vcomp icomp cson charge current vcomp icomp cson charge current adapter current system current charge current cson voltage
isl95871c 12 fn6856.2 june 8, 2011 theory of operation introduction the isl95871c includes all of th e functions necessary to charge 1- to 4-cell li-ion and li-polymer batteries. a high efficiency synchronous buck converter is used to control the charging voltage up to 19.2v and char ging current up to 8a. the isl95871c also has input current limiting up to 11a. the input current limit, charge current limi t and charge volt age limit are set by internal registers written with smbus. the isl95871c ?typical application circuit? is shown in figure 4. the isl95871c charges the battery with constant charge current, set by the chargecurrent register, until the battery voltage rises to a voltage set by the chargevoltage register. the charger will then operate at a constant voltage. the adapter current is monitored and if the adapter current rises to the limit set by the inputcurrent register, battery charge current is reduced so the charger does not reduce the adapter current available to the system. the isl95871c features a voltage regulation loop (vcomp) and 2 current regulation loops (icomp). the vcomp voltage regulation loop monitors vfb to limit the battery charge voltage. the icomp current regulation loop limits the battery charging current delivered to the battery to ensure that it never exceeds the current set by the chargecurrent register. the icomp current regulation loop also limits the input current drawn from the ac-adapter to ensure that it never exceeds the limit set by the inputcurrent register, and to prevent a system crash and ac-adapter overload. pwm control the isl95871c employs a fixed frequency pwm control architecture with a feed-forwa rd function. the feed-forward function maintains a constant modula tor gain of 11 to achieve fast line regulation as the input voltage changes. the duty cycle of the buck regulator is controlled by the lower of the voltages on icomp and vcomp. the voltage on icomp and vcomp are inputs to a lower voltage buffer (lvb) whose output is the lower of the 2 inputs. the output of the lvb is compared to an internal 400khz ramp to produce the pulse width modulated signal that controls the ufet and lfet gate drivers. an internal clamp holds the higher of the 2 voltages (0.3v) above the lower voltage. this speeds the transition from voltage loop cont rol to current loop control or vice versa. the isl95871c can operate up to 99.6% duty cycle if the input voltage drops close to or below the battery charge voltage (drop out mode). the dc/dc converter has a timer to prevent the frequency from dropping into the audible frequency range. to prevent boosting of the system bus voltage, the battery charger drives the lower fet in a way that prevents negative inductor current. an adaptive gate drive scheme is used to control the dead time between two switches. the dead ti me control circuit monitors the lfet gate driver output and prevents the upper side mosfet from turning on until 20ns after the lfet gate driver falls below 1v v gs , preventing cross-conduction and shoot-through. the same occurs for lfet turn on. ac-adapter detection connect the ac-adapter voltage through a resistor divider to acin to detect when ac power is available, as shown in figure 4. acok is an open-drain output and is active low when acin is less than acin falling threshold, and high when acin is above acin rising threshold. the acin rising threshold is 3.2v (typ) with 57mv hysteresis. current measurement use icm to monitor the adapter cu rrent being sensed across csip and csin. the output voltage range is 0v to 2.5v. the voltage of icm is proportional to the voltag e drop across csip and csin, and is given by equation 1: where i input is the dc current drawn from the ac-adapter. it is recommended to have an rc filter at the icm output for minimizing the switching noise. vddp regulator vddp provides a 5.2v supply voltage from the internal ldo regulator from dcin and can deliver up to 30ma of continuous current. the mosfet drivers are powered by vddp. vddp also supplies power to vdd through a low pass filter as shown in figure 4 on page 4. bypass vddp and vdd with a 1f capacitor. vddsmb supply the vddsmb input provides power to the smbus interface. connect vddsmb to vdd, or apply an external supply to vddsmb to keep the smbus interface active while the supply to dcin is removed. when vddsmb is biased, the internal registers are maintained. bypass vddsmb to agnd with a 0.1f or greater ceramic capacitor. short circuit protection and 0v battery charging since the battery charger will regulate the charge current to the limit set by the chargecurrent regi ster, it automatically has short circuit protection and is able to provide the charge current to wake up an extremely discharged battery. undervoltage trickle charge folds back current if there is a short circuit on the output. undervoltage detect and battery trickle charging if the voltage at vfb falls below 2.5v, isl95871c reduces the charge current limit to 128ma to trickle charge the battery. when the voltage rises above 2.7v, the charge current reverts to the programmed value in the chargecurrent register. over-temperature protection if the die temperature exceeds +150c, it stops charging. once the die temperature drops below +125c, charging will start-up again. overvoltage protection isl95871c has an overvoltage prot ection circuit that limits the output voltage when the battery is removed or disconnected by a pulse charging circuit. if cson exceeds the output voltage set v icm 20 i input r s1 20 v csip v csin ? () = ?? = (eq. 1)
isl95871c 13 fn6856.2 june 8, 2011 point in the charge voltage register by more than 300mv, an internal comparator pulls vcomp down and turns off both upper and lower fets of the buck as in figure 20. there is a delay of approximately 1s between v out exceeding the ovp trip point and pulling vcomp, lgate and ugate low. after ugate and lgate are turned off, inductor current continues to flow through the body diode of the lower fet and v out continues to rise until inductor current reaches zero. the system management bus the system management bus (smbus) is a 2-wire bus that supports bidirectional communications. the protocol is described briefly here. more detail is available from www.smbus.org . general smbus architecture data validity the data on the sda line must be stable during the high period of the scl, unless generating a start or stop condition. the high or low state of the data line can only change when the clock signal on the scl line is low. refer to figure 22. start and stop conditions as shown in figure 23, start condition is a high-to-low transition of the sda line while scl is high. the stop condition is a low-to-h igh transition on the sda line while scl is high. a stop condition must be sent before each start condition. acknowledge each address and data transmission uses 9-clock pulses. the ninth pulse is the acknowledge bit (ack). after the start condition, the master sends 7-slave address bits and a r/w bit during the next 8- clock pulses. during the ninth clock pulse, the device that recognizes its own address holds the data line low to acknowledge. the acknowledge bit is also used by both the master and the slave to acknowledge receipt of register addresses and data (see figure 24). figure 20. overvoltage protection in isl88731c inductor current v out phase battery current vddsmb sda output input scl control smbus master cpu sda control to other slave devices output input registers, output input scl control sda control output input smbus slave state machine, registers, memory, etc output input scl control sda control output input smbus slave scl state machine, memory, etc figure 21. sda scl data line stable data valid change of data allowed figure 22. data validity sda scl start condition figure 23. start and stop waveforms stop condition sp sda scl figure 24. acknowledge on the i 2 c bus 1 2 8 9 acknowledge msb start from slave
isl95871c 14 fn6856.2 june 8, 2011 smbus transactions all transactions start with a co ntrol byte sent from the smbus master device. the control byte begins with a start condition, followed by 7-bits of slave address (0001001 for the isl95871c) followed by the r/w bit. the r/w bit is 0 for a write or 1 for a read. if any slave devices on the smbus bu s recognize their address, they will acknowledge by pulling the serial data (sda) line low for the last clock cycle in the control byte. if no slaves exist at that address or are not ready to communicate, the data line will be 1, indicating a not acknowledge condition. once the control byte is sent, and the isl95871c acknowledges it, the 2nd byte sent by the mast er must be a re gister address byte such as 0x14 for the chargecurrent register. the register address byte tells the isl95871c which register the master will write or read. see table 1 for details of the registers. once the isl95871c receives a register addr ess byte it responds with an acknowledge. byte format every byte put on the sda line must be eight bits long and must be followed by an acknowledge bit. data is transferred with the most significant bit first (msb) an d the least significant bit last (lsb). isl95871c and smbus the isl95871c receives control inputs from the smbus interface. the serial interface complies with the smbus protocols as documented in the system mana gement bus specification v1.1, which can be downloaded from www.smbus.org. the isl95871c uses the smbus read-word and write-word protocols (see figure 25) to communicate with the smar t battery. the isl95871c is an smbus slave device and does not initiate communication on the bus. it responds to the addresses in the following. read address = 0b00010011 (0x13) and write address = 0b00010010 (0x12). in addition, the isl95871c has two identification (id) registers: a 16-bit device id register and a 16-bit manufacturer id register. the data (sda) and clock (scl) pi ns have schmitt-trigger inputs that can accommodate slow edges. choose pull-up resistors for sda and scl to achieve rise times according to the smbus specifications. the isl95871c is controlled by the data written to the registers described in table 1. battery charger registers the isl95871c supports five battery-charger registers that use either write-word or read-word protocols, as summarized in table 1. manufacturerid and deviceid are ?read only? registers and can be used to identify the isl95871c. on the isl95871c, manufacturerid always returns 0x0049 (ascii code for ?i? for intersil) and deviceid always returns 0x0001. enabling and disabling charging after applying power to isl95871c, the internal registers contain their por values (see table 1). the por values for charge current and charge voltage are 0x0000. these values disable charging. to enable charging, the chargecurrent register must be written with a number >0x007f and the ch argevoltage register must be written with a number >0x000f. charging can be disabled by writing 0x0000 to either of these registers. table 1. battery charger register summary register address register name read/w rite description por state 0x14 chargecurrent read or write 6-bit charge current setting 0x0000 0x15 chargevoltage read or write 11-bit charge voltage setting 0x0000 0x3f inputcurrent read or write 6-bit charge current setting 0x0080 0xfe manufacturerid read only manufacturer id 0x0049 0xff deviceid read only device id 0x0001
isl95871c 15 fn6856.2 june 8, 2011 setting charge voltage charge voltage is set by writing a valid 16-bit number to the chargevoltage register. this 16-bit number translates to a 65.535v full-scale voltage. th e isl95871c ignores the first 4 lsbs and uses the next 11 bits to set the voltage dac. the charge voltage range of the isl95871c is 1.024v to 19.200v. numbers requesting charge voltag e greater than 19.200v result in a chargevoltage of 19.200v. all numbers requ esting charge voltage below 1.024v result in a voltage set point of zero, which terminates charging. upon initial power-up or reset, the chargevoltage and chargecurrent registers are reset to 0 and the charger remains shut down until valid numbers are sent to the chargevoltage and chargecurrent registers. use the write-word protocol (see figure 25) to write to the chargevoltage register. the register address for chargevoltage is 0x15. the 16-bit binary number formed by d15?d0 represents the charge voltage set point in mv. however, the resolution of the isl95871c is 16mv because the d0?d3 bits are ignored as shown in table 2. the d15 bit is also ignored because it is not needed to span the 1.024v to 19.2v range. table 2 shows the mapping between the charge-voltage set point and the 16-bit number written to the chargevoltage register. the chargevoltage register can be read back to verify its contents. figure 25. smbus/isl95871c read and write protocol a s a n p slave addr + w register addr hi byte data lo byte data a a a s a p slave addr + w register addr hi byte data lo byte data a a n s a slave addr + r p acknowledge no acknowledge sstart pstop driven by the master driven by isl95871c write to a register read from a register
isl95871c 16 fn6856.2 june 8, 2011 table 2. chargevoltage (register 0x15) bit bit name description 0not used. 1not used. 2not used. 3not used. 4 charge voltage, dacv 0 0 = adds 0mv of charger voltage, 1024mv min. 1 = adds 16mv of charger voltage. 5 charge voltage, dacv 1 0 = adds 0mv of charger voltage, 1024mv min. 1 = adds 32mv of charger voltage. 6 charge voltage, dacv 2 0 = adds 0mv of charger voltage, 1024mv min. 1 = adds 64mv of charger voltage. 7 charge voltage, dacv 3 0 = adds 0mv of charger voltage, 1024mv min. 1 = adds 128mv of charger voltage. 8 charge voltage, dacv 4 0 = adds 0mv of charger voltage, 1024mv min. 1 = adds 256mv of charger voltage. 9 charge voltage, dacv 5 0 = adds 0mv of charger voltage, 1024mv min. 1 = adds 512mv of charger voltage. 10 charge voltage, dacv 6 0 = adds 0ma of charger voltage. 1 = adds 1024mv of charger voltage. 11 charge voltage, dacv 7 0 = adds 0mv of charger voltage. 1 = adds 2048mv of charger voltage. 12 charge voltage, dacv 8 0 = adds 0mv of charger voltage. 1 = adds 4096mv of charger voltage. 13 charge voltage, dacv 9 0 = adds 0mv of charger voltage. 1 = adds 8192mv of charger voltage. 14 charge voltage, dacv 10 0 = adds 0mv of charger voltage. 1 = adds 16384mv of charger voltage, 19200mv max. 15 not used. normally a 32768mv weight.
isl95871c 17 fn6856.2 june 8, 2011 setting charge current isl95871c has a 16-bit chargecu rrent register that sets the battery charging current. isl95871c controls the charge current by controlling the csop-cson voltage. the register?s lsb translates to 10v at cson-csop. with a 10m charge current sensing resistor (r s2 in figure 4 on page 4), the lsb translates to 1ma charge current. the isl95871c ignores the first 7 lsbs and uses the next 6 bits to control the current dac. the charge-current range of the isl 95871c is 0a to 8.064a (using a 10m current-sense resistor). al l numbers requesting charge current above 8.064a result in a current setting of 8.064a. all numbers requesting charge cu rrent between 0ma to 128ma result in a current setting of 0ma. the default charge current setting at power-on reset (por) is 0ma. to stop charging, set chargecurrent to 0. upon initia l power-up, the chargevoltage and chargecurrent registers are reset to 0 and the charger is disabled. to start the charger, write valid numbers to the chargevoltage and chargecurrent registers. the chargecurrent register uses the write-word protocol (see figure 25). the register code for chargecurrent is 0x14 (0b00010100). table 3 shows the mapping between the charge current set point and the chargecurrent number. the chargecurrent register can be read back to verify its contents. the isl95871c includes a fault limiter for low battery conditions. if the battery voltage is less than 2.5v, the charge current is temporarily set to 128ma. the chargecurrent register is preserved and becomes active again when the battery voltage is higher than 2.7v. this function effectively provides a foldback current limit, which protects the charger during short circuit and overload. table 3. chargecurrent (register 0x14) (10m sense resistor, rs2) bit bit name description 0not used. 1not used. 2not used. 3not used. 4not used. 5not used. 6not used. 7 charge current, daci 0 0 = ad ds 0ma of charger current. 1 = adds 128ma of charger current. 8 charge current, daci 1 0 = ad ds 0ma of charger current. 1 = adds 256ma of charger current. 9 charge current, daci 2 0 = ad ds 0ma of charger current. 1 = adds 512ma of charger current. 10 charge current, daci 3 0 = adds 0ma of charger current. 1 = adds 1024ma of charger current. 11 charge current, daci 4 0 = adds 0ma of charger current. 1 = adds 2048ma of charger current. 12 charge current, daci 5 0 = adds 0ma of charger current. 1 = adds 4096ma of charger current, 8064ma max. 13 not used. 14 not used. 15 not used.
isl95871c 18 fn6856.2 june 8, 2011 setting input-current limit the total power from an ac-ada pter is the sum of the power supplied to the system and the power into the charger and battery. when the input current exceeds th e set input current limit, the isl95871c decreases the charge current to provide priority to system load current. as the system load rises, the available charge current drops linearly to zero. th ereafter, the total input current can increase to the limit of the ac-adapter. the internal amplifier compares the differential voltage between csip and csin to a scaled vo ltage set by the inputcurrent register. the total input current is the sum of the device supply current, the charger input current, and the system load current. the total input current can be estimated as shown in equation 2. where is the efficiency of the dc/dc converter (typically 85% to 95%). the isl95871c has a 16-bit inputcurrent register that translates to a 2ma lsb and a 131.071a full scale current using a 10m current-sense resistor (rs1 in figure 4 on page 4). equivalently, the 16-bit inputcurrent number sets the voltage across csip and csin inputs in 20v per lsb incr ements. to set the input current limit use the smbus to write a 16-bit inputcurrent register using the data format listed in table 4. the inputcurrent register uses the write-word protocol (see figure 25). the register code for inputcurrent is 0x3f (0b00111111). the inputcurrent register can be read back to verify its contents. the isl95871c ignores the first 7 lsbs and uses the next 6 bits to control the input-current dac. the input-current range of the isl95871c is from 256ma to 11.004a. all 16-bit numbers requesting input current above 11.0 04a result in an input-current setting of 11.004a. all 16-bit numbers requesting input current between 0ma to 256ma result in an input-current setting of 0ma. the default input-current-limit setting at por is 256ma. when choosing the current-sense resistor rs1, carefully calculate its power rating. take into account variations in the system?s load current and the overall accuracy of the sense amplifier. note that the voltage drop across rs1 contributes additional power loss, which reduces efficiency. system currents normally fluctuate as portions of the system are powered up or put to sleep. without input current regulation, the input source must be able to deliver the maximum system current an d the maximum charger-input current. by using the input-current-limit circuit, the output-current capability of the ac wall adapter can be lowered, reducing system cost. i input i system i charge v battery () v in () ? [] + = (eq. 2) table 4. inputcurrent (register 0x3f) (10m sense resistor, rs1) bit bit name description 0not used. 1not used. 2not used. 3not used. 4not used. 5not used. 6not used. 7 input current, dacs 0 0 = adds 0ma of input current. 1 = adds 256ma of input current. 8 input current, dacs 1 0 = adds 0ma of input current. 1 = adds 512ma of input current. 9 input current, dacs 2 0 = adds 0ma of input current. 1 = adds 1024ma of input current. 10 input current, dacs 3 0 = adds 0ma of input current. 1 = adds 2048ma of input current. 11 input current, dacs 4 0 = adds 0ma of input current. 1 = adds 4096ma of input current. 12 input current, dacs 5 0 = adds 0ma of input current. 1 = adds 8192ma of input current, 11004ma max. 13 not used. 14 not used. 15 not used.
isl95871c 19 fn6856.2 june 8, 2011 charger timeout the isl95871c includes 2 timers to insure the smbus master is active and to prevent overcharging the battery. isl95871c will terminate charging if the charger has not received a write to the chargevoltage or chargecurrent re gister within 175s or if the scl line is low for more than 25ms. if a time-out occurs, either chargevoltage or chargecurrent registers must be written to re-enable charging. isl95871c data byte order each register in isl95871c contains 16-bits or 2-, 8-bit bytes. all data sent on the smbus is in 8 bit bytes and 2 bytes must be written or read from each register in isl95871c. the order in which these bytes are transmitted appears reversed from the way they are normally written. the low byte is sent first and the hi byte is sent second. for example, when writing 0x41a0, 0xa0 is written first and 0x41 is sent second. writing to the internal registers in order to set the charge current, charge voltage or input current, valid 16-bit numbers must be written to isl95871c?s internal registers via the smbus. to write to a register in the isl95871c, the master sends a control byte with the r/w bit set to 0, indicating a write. if it receives an acknowledge from th e isl95871c it sends a register address byte setting the register to be written (i.e., 0x14 for the chargecurrent register). the isl95871c will respond with an acknowledge. the master then sends the lower data byte to be written into the desired register. the isl95871c will respond with an acknowledge. the master then sends the higher data byte to be written into the desired register. the isl95871c will respond with an acknowledge. the master then issues a stop condition, indicating to the isl95871c that the current transaction is complete. once this transaction completes the isl95871c will begin operating at the new current or voltage. the isl95871c does not support wr iting more than one register per transaction. reading from the internal registers the isl95871c has the ability to read from 5 internal registers. prior to reading from an internal register, the master must first select the desired register by writing to it and sending the registers address byte. this process begins by the master sending a control byte with the r/w bit set to 0, indicating a write. once it receives an acknowledge from the isl95871 c it sends a register address byte representing the internal register it wants to read. the isl95871c will respond with an acknowledge. the master must then respond with a stop conditio n. after the stop condition, the master follows with a new start condition then sends a new control byte with the isl95871c slave address and the r/w bit set to 1, indicating a read. the isl95871c will acknowledge then send the lower byte stored in that register. after receiving the byte, the master acknowledges by holding sda low during the 9th clock pulse. isl95871c then sends the higher byte stored in the register. after the second byte neither device holds sda low (no acknowledge). the master will then produce a stop condition to end the read transaction. the isl95871c does not support reading more than 1 register per transaction. application information the following battery charger design refers to the ?typical application circuit? (see figure 4 on page 4), where typical battery configuration of 3s2p is used. this section describes how to select the external componen ts including the inductor, input and output capacitors, switchin g mosfets and current sensing resistors. inductor selection the inductor selection has tr ade-offs between cost, size, crossover frequency and efficiency. for example, the lower the inductance, the smaller the size, bu t ripple current is higher. this also results in higher ac losses in the magnetic core and the windings, which decreases the system efficiency. on the other hand, the higher inductance results in lower ripple current and smaller output filter capacitors, but it has higher dcr (dc resistance of the inductor) loss, lower saturation current and has slower transient response. thus, th e practical inductor design is based on the inductor ripple curre nt being 15% to 20% of the maximum operating dc current at maximum input voltage. maximum ripple is at 50% duty cycle or v bat =v in,max /2. the required inductance for 15% ripp le current can be calculated from equation 3: where v in,max is the maximum input voltage, f sw is the switching frequency and i l,max is the max dc current in the inductor. for v in,max = 20v, v bat = 12.6v, i bat,max = 4.5a, and f s = 400khz, the calculated induct ance is 9.3h. choosing the closest standard value gives l = 10h. ferrite cores are often the best choice since they are optimized at 400khz to 600khz operation with low core loss. the core must be large enough not to saturate at the peak inductor current i peak in equation 4: inductor saturation can lead to cascade failures due to very high currents. conservative design limits the peak and rms current in the inductor to less than 90% of the rated saturation current. crossover frequency is heavily dependent on the inductor value. f co should be less than 20% of the switching frequency and a conservative design has f co less than 10% of the switching frequency. the highest f co is in voltage control mode with the battery removed and may be calculated (approximately) from equation 5: output capacitor selection the output capacitor in parallel with the battery is used to absorb the high frequency switching ripple current and smooth the l v in max , 4f sw 0.3 i ? lmax , ?? ------------------------------------------------------ - = (eq. 3) i peak i lmax , 1 2 --- + i ripple ? = (eq. 4) f co 511r s2 ?? 2 l ? ----------------------------- - = (eq. 5)
isl95871c 20 fn6856.2 june 8, 2011 output voltage. the rms value of the output ripple current i rms is given by equation 6: where the duty cycle d is the ratio of the output voltage (battery voltage) over the input voltage for continuous conduction mode which is typical operation for the battery charger. during the battery charge period, the output voltage varies from its initial battery voltage to the rated battery voltage. thus, the duty cycle varies from 0.53 for the minimum battery voltage of 7.5v (2.5v/cell) to 0.88 for the maximum battery voltage of 12.6v. the maximum rms value of the output ripple current occurs at the duty cycle of 0.5 and is expressed as equation 7: for v in,max = 19v, v bat = 16.8v, l = 10h, and f s = 400khz, the maximum rms current is 0.19a. a typical 20f ceramic capacitor is a good choice to absorb this current and also has very small size. organic polymer capacitors have high capacitance with small size and have a significant equivalent series resistance (esr). although esr adds to ripple voltage, it also creates a high frequency ze ro that helps the closed loop operation of the buck regulator. emi considerations usually make it desirable to minimize ripple current in the battery leads. beads may be added in series with the battery pack to increase the battery impedance at 400khz switching frequency. switching ripple current splits between the battery and the output capacitor depending on the esr of the output capacitor and battery impeda nce. if the esr of the output capacitor is 10m and battery impedance is raised to 2 with a bead, then only 0.5% of the ripple current will flow in the battery. snubber design isl95871c's buck regulator oper ates in discontinuous current mode (dcm) when the load cu rrent is less than half the peak-to-peak current in the inductor. after the low-side fet turns off, the phase voltage rings due to the high impedance with both fets off. this can be seen in figure 15 on page 10. adding a snubber (resistor in series with a capacitor) from the phase node to ground can greatly reduce the ringing. in some situations a snubber can improve output ripple and regulation. the snubber capacitor should be approximately twice the parasitic capacitance on the phase node. this can be estimated by operating at very low load current (100ma) and measuring the ringing frequency. c snub and r snub can be calculated from equations 8 and 9: input capacitor selection the input capacitor absorbs the ripple current from the synchronous buck converter, which is given by equation 10: where i bat is the battery charging current. this rms ripple current must be smaller than the rated rms current in the capacitor datasheet. non-tantalum chemistries (ceramic, aluminum, or oscon) are preferre d due to their resistance to power-up surge currents when the ac-adapter is plugged into the battery charger. for notebook battery charger applications, it is recommended that ceramic capacitors or polymer capacitors from sanyo be used due to their small size and reasonable cost. loop compensation design isl95871c has three closed loop control modes. one, controls the output voltage when the battery is fully charged or absent. a second, controls the current into the battery when charging and the third, limits current drawn from the adapter. the charge current and input current control loops are compensated by a single capacitor on the icomp pi n. the voltage control loop is compensated by a network on the vcomp pin. descriptions of these control loops and guidelin es for selecting compensation components will be given in the following sections. which loop controls the output is determined by the minimum current buffer and the minimum voltage buffer shown in the ?functional block diagram? on page 4. these three loops will be described separately. transconductance amplifiers gmv, gmi and gms isl95871c uses several transconductance amplifiers (also known as gm amps). most commer cially available op amps are voltage controlled voltage sources with gain expressed as a=v out /v in . gm amps are voltage co ntrolled current sources with gain expressed as gm = i out /v in . gm will appear in some of the equations for poles and zeros in the compensation. pwm gain f m the pulse width modulator in the isl95871c converts voltage at vcomp to a duty cycle by comparing vcomp to a triangle wave (duty = vcomp/v p-p ramp ). the low-pass filter formed by l and c o convert the duty cycle to a dc output voltage (vo = v dcin *duty). in isl95871c, the triangle wave amplitude is proportional to v dcin . making the ramp am plitude proportional to dcin makes the gain from vcomp to the phase output a constant 11 and is independent of dcin. for small signal ac analysis, the battery is modeled by its internal resistance. the total output resistance is the su m of the sense resistor and the internal resistance of the mosfets, inductor and capacitor. figure 26 shows the small sign al model of the pulse width modulator (pwm), power stage, output filter and battery. i rms1 v in max , 12 l f sw ?? ---------------------------------- d1d ? () ?? = (eq. 6) i rms1 max () v in max , 412lf sw ??? ------------------------------------------ = (eq. 7) c snub 2 2 f ring () 2 l ? ----------------------------------- - = (eq. 8) r snub 2l ? c snub ----------------- = (eq. 9) (eq. 10) i rms2 i bat v out v in v out ? () v in -------------------------------------------------- ? =
isl95871c 21 fn6856.2 june 8, 2011 in most cases, the battery resistance is very small (<200m ) resulting in a very low q in the output filter. this results in a frequency response from the inpu t of the pwm to the inductor current with a single pole at the frequency calculated in equation 11: the output capacitor creates a pole at a very high frequency due to the small resistance in parallel with it. the frequency of this pole is calculated in equation 12: charge current control loop when the battery is less than fully charged, the voltage error amplifier goes to its maximum output (limited to 0.3v above icomp) and the icomp voltage controls the loop through the minimum voltage buffer. figure 28 shows the charge current control loop. the compensation capacitor (c icomp ) gives the error amplifier (gmi) a pole at a very low frequency (<<1hz) and a zero at f z1 . f z1 is created by the 0.25*ca2 output added to icomp. the frequency can be calculated from equation 13: placing this zero at a frequency equal to the pole calculated in equation 12 will result in maximum gain at low frequencies and phase margin near 90. if the zero is at a higher frequency (smaller c icomp ), the dc gain will be higher but the phase margin will be lower. use a capacitor on icomp that is equal to or greater than the value calculated in equation 14. the factor of 1.5 is to ensure the zero is at a frequency lower than the pole including tolerance variations. a filter should be added between r s2 and csop and cson to reduce switching noise. the filter roll-off frequency should be between the crossover frequency and the switching frequency (~100khz). r f2 should be small (<10 ) to minimize offsets due to leakage current into csop. the filter cutoff frequency is calculated using equation 15: the crossover frequency is determined by the dc gain of the modulator and output filter and the pole in equation 12. the dc gain is calculated in equation 16 and the crossover frequency is calculated with equation 17. the bode plot of the loop gain, the compensator gain and the power stage gain is shown in figure 28. adapter current limit control loop if the combined battery charge current and system load current draws current that equals the adapter current limit set by the inputcurrent register, isl95871c will reduce the current to the battery and/or reduce the output voltage to hold the adapter current at the limit. above th e adapter current limit, the minimum current buffer equals the output of gms and icomp controls the charger output. figu re 29 shows the adapter current limit control loop. figure 26. small signal ac model drivers ramp gen v ramp = v in /11 v in - + 11 pwm input l c o l r esr c o r s2 r bat r fet_rdson pwm input r l_dcr pwm gain=11 f pole1 r s2 r ds on () r dcr r bat +++ () 2 l ? ----------------------------------------------------------------------------------- - = (eq. 11) f pole2 1 2 c o r bat ?? ------------------------------------ = (eq. 12) (eq. 13) f zero 4gm2 ? 2 c icomp ? () ------------------------------------ - = gm2 50 av ? = figure 27. charge current limit loop r s2 r bat icomp cson phase r esr c o 11 + - 20x csop s + - 0.25 daci + - gmi c f2 r f2 c icomp l r fet_rdson r l_dcr ca2 c icomp 1.5 4 50 av ? () l ?? ? r s2 r ds on () r dcr r bat +++ () ----------------------------------------------------------------------------------- - = (eq. 14) f filter 1 2 c f2 r f2 ?? () ---------------------------------------- - = (eq. 15) a dc 11 r ? s2 r s2 r ds on () r dcr r bat +++ () ----------------------------------------------------------------------------------- - = (eq. 16) f co a dc f pole ? 11 r ? s2 2 l ? --------------------- - == (eq. 17)
isl95871c 22 fn6856.2 june 8, 2011 the loop response equations, bo de plots and the selection of c icomp are the same as the charge cu rrent control loop with loop gain reduced by the duty cycle and the ratio of r s1 /r s2 . in other words, if r s1 = r s2 and the duty cycle d = 50%, the loop gain will be 6db lower than the loop gain in figure 29. this gives lower crossover frequency and higher ph ase margin in this mode. if r s1 /r s2 = 2 and the duty cycle is 50% then the adapter current loop gain will be identical to the gain in figure 29. a filter should be added between r s1 and csip and csin to reduce switching noise. the filter roll off frequency should be between the crossover frequency and the switching frequency (~100khz). voltage control loop when the battery is charged to the voltage set by chargevoltage register the voltage error amplifier (gmv) takes control of the output (assuming that the adapte r current is below the limit set by aclim). the voltage error amplifier (gmv) discharges the cap on vcomp to limit the output voltage. the current to the battery decreases as the cells charge to the fixed voltage and the voltage across the internal battery resi stance decreases. as battery current decreases, the 2 current error amplifiers (gmi and gms) output their maximum current and charge the capacitor on icomp to its maximum voltage (limited to 0.3v above vcomp). with high voltage on icomp, the minimum voltage buffer output equals the voltage on vcomp. the voltage control loop is shown in figure 30. output lc filter transfer functions the gain from the phase node to the system output and battery depend entirely on external components. typical output lc filter response is shown in figure 31. transfer function a lc (s) is shown in equation 18: the resistance r o is a combination of mosfet r ds(on) , inductor dcr, r s2 and the internal resistance of the battery (normally between 50m and 200m ). the worst case for voltage mode control is when the battery is absent. this results in the highest q of the lc filter and the lowest phase margin. the compensation network consists of the voltage error amplifier gmv and the compensation network r vcomp , c vcomp which give the loop very high dc gain, a very low frequency pole and a zero at f zero1 . inductor current information is added to the feedback to create a second zero f zero2 . the low pass filter r f2 , c f2 between r s2 and isl95871c add a pole at f filter . r 3 and r 4 are internal divider resistors that set the dc output voltage. for a 3-cell battery, r 3 =500k and r 4 = 100k . the equations following relate the compensation network?s poles, ze ros and gain to the components in figure 30. figure 32 shows an asymptotic bode plot of the dc/dc converter?s gain vs frequenc y. it is strongly recommended that f zero1 is approximately 30% of f lc and f zero2 is approximately 70% of f lc . figure 28. charge current loop bode plots -60 -40 -20 0 20 40 60 10 100 1k 10k 100k 1m frequency (hz) gain (db) compensator modulator loop f zero f filter f pole2 f pole1 c icomp r bat icomp phase 11 s + - 0.25 dacs + - gms r s1 dcin cssn + - ca1 20 cssp c f1 r f1 r s2 cson + - 20x csop c f2 r f2 r esr c o l r fet_rdson r l_dcr ca2 figure 29. adapter current limit loop figure 30. voltage control loop vcomp cson phase 11 csop s + - 0.25 + - gmv c vcomp r vcomp dacv r3 r4 + - 20x r s2 r bat r esr c o c f2 r f2 l r fet_rdson r l_dcr ca2 a lc 1 s esr ------------- - ? ?? ?? s 2 dp ---------- - s lc q ? () ----------------------- 1 ++ ?? ?? ?? -------------------------------------------------------- - = esr 1 r esr c o ? () ----------------------------- = lc 1 lc o ? () ---------------------- - = qr o l c o ----- - ? = (eq. 18)
isl95871c 23 fn6856.2 june 8, 2011 compensation break frequency equations choose r vcomp equal or lower than the value calculated from equation 25. next, choose c vcomp equal or higher than the value calculated from equation 26. pcb layout considerations power and signal layers placement on the pcb as a general rule, power layers should be close together, either on the top or bottom of the board, with signal layers on the opposite side of the board. as an example, layer arrangement on a 4-layer board is shown below: 1. top layer: signal lines, or half board for signal lines and the other half board for power lines 2. signal ground 3. power layers: power ground 4. bottom layer: power mosfet, inductors and other power traces separate the power voltage and current flowing path from the control and logic level signal path. the controller ic will stay on the signal layer, which is isolated by the signal ground to the power signal traces. component placement the highest priority for placement cl ose to the ic are the high current components. place the vin capacitors as close as possible to the vin and pgnd pins. the power inductor, charge current sense resistor and output caps are the second highest priority. a layer of power ground under these components and high current pins on isl95871c (pins 9 through 33) will keep current loops small and minimize emi radiated from this high current loops. small signals such as current se nse and compensation should be placed near their connections to isl95871c and have an area of agnd ?quiet ground?) on the adjacent layer. an area of quiet ground should be on the layer under isl95871c pins 1 through 8 and 34 through 50. the best tie-point between the signal ground and the power ground is at the negative side of the output capacitor on each side, where there is little noise; a noisy trace beneath the ic is not recommended. signal ground and power ground connection at minimum, a reasonably large area of copper, which will shield other noise couplings through the ic, should be used as signal ground beneath the ic. the best tie-point between the signal ground and the power ground is at the negative side of the output capacitor on each side, where there is little noise; a noisy trace beneath the ic is not recommended. 10 0 -10 -20 -40 -50 -60 -30 -20 -40 -60 -80 -120 -140 -160 -100 100 200 500 1k 2k 5k 10k 20k 50k 100k 200k 500k figure 31. frequency response of the lc output filter phase () gain (db) frequency (hz) r battery = 200m ? r battery = 50m ? no battery -60 -40 -20 0 20 40 60 100 1k 10k 100k 1m frequency (hz) gain (db) compensator modulator loop f pole1 f lc f filter f esr f zero2 f zero1 figure 32. asymptotic bode plot of the voltage control loop gain f zero1 1 2 c vcomp r vcomp ?? () ---------------------------------------------------------------- - = (eq. 19) f zero2 r vcomp 2 r s2 c ? o ? -------------------------------- - ?? ?? ?? r 4 r 4 r 3 + -------------------- ?? ?? ?? gm1 5 ------------ ?? ?? ?? = (eq. 20) f lc 1 2 lc o ? () ------------------------------ = (eq. 21) f filter 1 2 r f2 c f2 ?? () ---------------------------------------- - = (eq. 22) f pole1 1 2 r s2 c o ?? () ------------------------------------- - = (eq. 23) f esr 1 2 c o r esr ?? () ----------------------------------------- = (eq. 24) r vcomp 0.7 f lc ? () 2 c o r s2 ?? () 5 gm1 ------------ ?? ?? r 3 r 4 + r 4 -------------------- ?? ?? ?? ??? = (eq. 25) c vcomp 1 0.3 f lc ? () 2 r vcomp ? () ? ---------------------------------------------------------------------- = (eq. 26)
isl95871c 24 fn6856.2 june 8, 2011 agnd and vdd pin at least one high quality ceramic decoupling capacitor should be used to cross these two pins. the decoupling capacitor can be put close to the ic. pgnd pins pgnd pin should be laid out to the negative side of the relevant output capacitor with separate tr aces. the negative side of the output capacitor must be close to the source node of the bottom mosfet. this trace is the return path of lfet gate drive. phase pins connect this pin to the output inductor. this trace should be short, and positioned away from other weak signal traces. this node has a very high dv/dt with a voltage swing from the input voltage to ground. no trace should be in parallel with it. boot pin this pin carries gate drive current and trace should be as short as possible. csop, cson, csip and csin pins accurate charge current and adap ter current sensing is critical for good performance. the curren t sense resistor connects to the cson and the csop pins through a low pass filter with the filter capacitor very near the ic (see figure 4 on page 4). traces from the sense resistor should start at the pads of the sense resistor and should be routed close together, through the low pass filter and to the csop and cson pins (see figure 33). the cson pin is also used as the battery voltage feedback. the traces should be routed away from the high dv/dt and di/dt pins like phase, boot pins. in general, the current sense resistor should be close to the ic. these guidelines should also be followed for the adapter current sense resistor and csip and csin. other layout arrangements should be adjusted accordingly. dcin pin this pin connects to ac-adapter output voltage, and should be less noise sensitive. copper size for the phase node the capacitance of phase should be kept very low to minimize ringing. it would be best to lim it the size of the phase node copper in strict accordance with the current and thermal management of the application. identify the power and signal ground the input and output capacitors of the converters, the source terminal of the bottom switching mosfet pgnd should connect to the power ground. the other components should connect to signal ground. signal and power gr ound are tied together at one point as close as possible to the isl95871c. clamping capacitor for switching mosfet it is recommended that ceramic capacitors be used closely connected to vin and pgnd (the drain of the high-side mosfet and the source of the low-side mosfet). this capacitor reduces the noise and the power loss of the mosfets. figure 33. current sense resistor layout high current trace high current trace kelvin connection traces to th e lo w pass filter an d csop and cson sense resistor
isl95871c 25 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn6856.2 june 8, 2011 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentation an d related parts, please see the respective device information page on intersil.com: isl95871c to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.com/reports/sear revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 5/27/11 fn6856.2 on page 7 in the ?electrical specifications? table: removed ?icm gain? limits removed ?icm offset? specs 9/28/10 fn6856.1 corrected max limit of ?acin rising threshold? on page 7 from 3.25v to 3.28v 9/20/10 fn6856.0 initial release.
isl95871c 26 fn6856.2 june 8, 2011 package outline drawing l50.5x7 50 lead quad flat no-lead plastic package rev 0, 1/10 located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.10 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.015mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view angular 2.50 7.00 index area pin 1 5.00 2.575 0.45 0.35 2.525 6x 0.15 1.40 2x 3.20 3.50 50x 0.20 36x 0.40 2x 6.00 1.275 6x 0.1950 max. 1.0 (50x 0.20) (46x 0.40) (3.50) (2x 3.20) (4.20) (2x 6.0) (0.35) (0.45) (2.575) (2.725) 1.725 1.40 0.296 1.8749 0.5885 1.7299 2x 1.00 2x 0.60 46x 0.40 (6x 0.395) (36x 0.60) (1.275) (1.725) (0.35) 0.35 0.35 0.62 (0.62) (0.35) (5.40) (2x 7.4) (1.40) (1.40) (1.8749) (0.7885) (1.7299) (0.496) a b 0.10 2x 4 0.10 c a m b 5 0-0.05 c 0 . 2 ref c 0.10 seating plane 0.05 c c see detail "x" package outline pin #1 pin one 25 50 42 41 26 17 16 1 identification

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