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1/45 sta308a may 2004 this is preliminary information on a new product now in development. details are subject to change without notice. 1 features 8 channels of 24-bit ddx? >100db snr and dynamic range selectable 32khz-192khz input sample rates 6 channels of dsd/sacd input i 2 c control with selectable device address digital gain/attenuation +58db to -100db in 0.5db steps soft volume update individual channel and master gain/ attenuation plus channel trim (-10db to +10db) up to 10 independent 32-bit user programmable biquads (eq) per channel bass/treble tone control pre and post eq full 8-channel input mix on all 8 channels dual independent limiters/compressors dynamic range compression or anti-clipping modes automodes?: ? 5-band graphic eq ? 32 preset eq curves (rock, jazz, pop, etc.) ? automatic volume controlled loudness ? 5.1 to 2 channels channels downmix ? simultaneous 5.1 and 2 channel downmix outputs ? 3 preset volume curves ? 2 preset anti-clipping modes ? preset movie nighttime listening mode ? preset tv channel/commercial agc mode ? 5.1 bass management configurations ? 2.1 bass management ? am frequency automatic output pwm fre- quency shifting ? qsurround5.1 ? 8 preset crossover filters individual channel and master soft and hard mute automatic zero-detect mute automatic invalid input detect mute advanced popfreetm operation advanced am interference frequency switching and noise suppression modes pscorrecttm power supply ripple correction 8-channel i2s input and output data interface i2s output channel mapping function independent channel volume and dsp bypass channel mapping of any input to any processing/ddx channel dc blocking selectable high-pass filter selectable per-channel ddx damped ternary or binary pwm output selectable de-emphasis variable max power correction for lower full- power thd variable per channel ddx output delay control pwm half and double speed modes internal loop mode for up to 1 channel of 80 programmable biquads 192khz internal processing sample rate, 24- bit to 36-bit precision 3.3v single supply operation * provided only under license from qsound labs, inc. 2 description the sta308a is a single chip solution for digital au- dio processing and control in multi-channel applica- tions. it provides output capabilities for ddx tm (direct digital amplification). in conjunction with a ddx tm power device, it provides high-quality, high-efficien- cy, all digital amplification. the device is extremely versatile allowing for input of most digital formats in- cluding 6.1/7.1 channel and 192khz, 24-bit dvd-au- dio, dsd/sacd. in 5.1 application the additional 2 product preview multichannel digital audio processor with ddx? rev. 1 figure 1. package t able 1. order code part number package sta308a tqfp64 tqfp64
sta308a 2/45 description (continued) channels can be used for line-out or loadphone drive figure 2. block diagram figure 3. channel signal flow out1a/b out2a/b out3a/b out4a/b out5a/b out6a/b out7a/b out8a/b lrcki bicki sdi12 sdi34 sdi56 sdi78 sa serial data in i 2 c channel mapping variable over- sampling treble, bass, eq (biquads) volume limiting sdo78 sdo12 sdo34 sdo56 oversampling variable down- sampling power down pwdn eapd pll pllb xti ckout scl sda lrcko bicko mvo serial data out system control system timing ddx 1x,2x,4x interp biquads b/ t volume limiter 2x interp distortion compensation ns c_con pwm ddx output interp_rate 8 inputs from i2s dsd conversion 6 inputs from dsd mapping/ mix #1 dsde mix #2 prescale high-pass filter biqu ad #2 biqu ad #3 biquad #4 biqu ad #5 biqu ad #6 biquad #7 biquad #8 bas s har d s et t o -18db w hen automode eq (ameq) hard set coeffecients when automode eq (ameq) har d s et coeffecients w hen au t omod e bass management crossover (ambmxe) har d set coeffecients when deemphasis en abled (demp) from mix #1 engine or previous channel biquad#10 output (cxblp) to mix# 2 engin e treble us er progammable biquad #1 when high-pass bypassed (hpb) user programmable biquads #9 and #10 when tone bypassed (cxtcb)
3/45 sta308a figure 4. pin connection (top view) table 2. pin function pin name description pad type 1 mvo/dsd_clk master volume override/ dsd input clock 5v tolerant ttl input buffer 6 sdi_78/dsd_6 input serial data channels 7 & 8/ dsd input channel 6 5v tolerant ttl input buffer 7 sdi_56/dsd_5 input serial data channels 5 & 6/ dsd input channel 5 5v tolerant ttl input buffer 8 sdi_34/dsd_4 input serial data channels 3 & 4/ dsd input channel 4 5v tolerant ttl input buffer 9 sdi_12/dsd_3 input serial data channels 1 & 2/ dsd input channel 3 5v tolerant ttl input buffer 10 lrcki/dsd_2 input left/right clock/ dsd input channel 2 5v tolerant ttl input buffer 11 bicki/dsd_1 input serial clock/ dsd input channel 1 5v tolerant ttl input buffer 15 reset global reset 5v tolerant ttl schmitt trigger input buffer 16 pll_bypass bypass phase locked loop cmos input buffer with pull-down 17 sa select address (i 2 c) cmos input buffer with pull-down 18 sda i 2 c serial data bidirectional buffer: 5v tolerant ttl schmitt trigger input; 3.3v capable 2ma slew-rate controlled output. 19 scl i 2 c serial clock 5v tolerant ttl schmitt trigger input buffer 20 xti crystal oscillator input (clock input) 5v tolerant ttl schmitt trigger input buffer 21 filter_pll pll filter analog pad 22 vdda pll supply 3.3v analog power supply voltage 23 gnda pll ground analog ground 25 ckout clock output 3.3v capable ttl tristate 4ma output buffer 29 out8b pwm channel 8 output b 3.3v capable ttl 2ma output buffer 1 2 3 5 6 4 7 8 9 10 27 11 28 29 30 31 32 59 58 57 56 54 55 53 52 51 50 49 43 42 41 39 38 40 48 47 46 44 45 s di_78 nc gnd gnd mvo vdd bicki lrcki s di_12 s di_56 s di_34 vdda gnda vdd ckout gnd nc vdd out8_b out8_a out7_b out7_a vdd sdo_3 4 sdo_1 2 lrcko nc bicko gnd vdd eapd out1_ a out1_ b out3_ a out3_ b out4_ a out5_ a out5_ b out4_ b out2_ a out2_ b nc vdd gnd sta308apincon 22 23 24 25 26 60 gnd 61 nc 62 sdo_5 6 63 sdo_7 8 64 pwdn sa sda scl xti f ilter_pll 17 18 19 20 21 37 36 34 33 35 nc gnd out6_ a out6_ b vdd 12 13 14 15 16 pllb r eset nc vdd gnd
sta308a 4/45 table 3. absolute maximum ratings table 4. thermal data table 5. recommended dc operating conditions pin name description pad type 30 out8a pwm channel 8 output a 3.3v capable ttl 2ma output buffer 31 out7b pwm channel 7 output b 3.3v capable ttl 2ma output buffer 32 out7a pwm channel 7 output a 3.3v capable ttl 2ma output buffer 33 out6b pwm channel 6 output b 3.3v capable ttl 2ma output buffer 34 out6a pwm channel 6 output a 3.3v capable ttl 2ma output buffer 38 out5b pwm channel 5 output b 3.3v capable ttl 2ma output buffer 39 out5a pwm channel 5 output a 3.3v capable ttl 2ma output buffer 40 out4b pwm channel 4 output b 3.3v capable ttl 2ma output buffer 41 out4a pwm channel 4 output a 3.3v capable ttl 2ma output buffer 42 out3b pwm channel 3 output b 3.3v capable ttl 2ma output buffer 43 out3a pwm channel 3 output a 3.3v capable ttl 2ma output buffer 47 out2b pwm channel 2 output b 3.3v capable ttl 2ma output buffer 48 out2a pwm channel 2 output a 3.3v capable ttl 2ma output buffer 49 out1b pwm channel 1 output b 3.3v capable ttl 2ma output buffer 50 out1a pwm channel 1 output a 3.3v capable ttl 2ma output buffer 51 eapd ext. amp power down 3.3v capable ttl 4ma output buffer 55 bicko output serial clock 3.3v capable ttl 2ma output buffer 56 lrcko output left/right clock 3.3v capable ttl 2ma output buffer 57 sdo_12 output serial data channels 1&2 3.3v capable ttl 2ma output buffer 58 sdo_34 output serial data channels 3&4 3.3v capable ttl 2ma output buffer 3,12,24,28,3 5,44,52,59 vdd 3.3v supply 3.3v digital power supply voltage 2,4,13,27, 36,45,53,60 gnd ground digital ground 5,14,26,37,4 6,54,61 nc no connect 62 sdo_56 output serial data channels 5&6 3.3v capable ttl 2ma output buffer 63 sdo_78 output serial data channels 7&8 3.3v capable ttl 2ma output buffer 64 pwdn device powerdown 5v tolerant ttl schmitt trigger input buffer symbol parameter value unit v dd 3.3v i/o power supply -0.5 to 4 v v dda 3.3v logic power supply -0.5 to 4 v v i voltage on input pins -0.5 to (vdd+0.5) v v o voltage on output pins -0.5 to (vdd+0.3) v t stg storage temperature -40 to +150 c t amb ambient operating temperature -20 to +85 c symbol parameter value unit r thj-amb thermal resistance junction to ambient 85 c/w symbol parameter value unit v dd i/o power supply 3.0 to 3.6 v v dda logic power supply 3.0 to 3.6 v t j operating junction temperature -20 to +125 c table 2. pin function (continued)
5/45 sta308a 3 electrical characteristcs (v dd3 = 3.3v 0.3v; v dda = 3.3v 0.3v; t amb = 0 to 70 c; unless otherwise specified) table 6. general interface electrical characteristics note 1: the leakage currents are generally very small, < 1na. the values given here are maximum after an electrostatic stress o n the pin. note 2: human body model table 7. dc electrical characteristics: 3.3v buffers 4 pin description 4.1 mvo: master volume override this pin enables the user to bypass the volume control on all channels. when mvo is pulled high, the master volume register is set to 00h, which corresponds to its full scale setting. the master volume register setting offsets the individual channel volume settings, which default to 0db. 4.2 sdi_12 through 78: serial data in audio information enters the device here. six format choices are available including i2s, left- or right-justified, lsb or msb first, with word widths of 16, 18, 20 and 24 bits. 4.3 reset driving this pin (low) turns off the outputs and returns all settings to their defaults. 4.4 i 2 c the sa, sda and scl pins operate per the philips i2c specification. see section 5. symbol parameter test condition min. typ. max. unit note i il low level input no pull-up v i = 0v 1 a1 i ih high level input no pull-down v i = v dd3 2 a1 i oz tristate output leakage without pullup/down v i = v dd3 2 a1 v esd electrostatic protection leakage < 1 a2000 v2 symbol parameter test condition min. typ. max. unit v il low level input voltage 0.8 v v ih high level input voltage 2.0 v v ilhyst low level threshold input falling 0.8 1.35 v v ihhyst high level threshold input rising 1.3 2.0 v v hyst schmitt trigger hysteresis 0.3 0.8 v v ol low level output ioi = 100ua 0.2 v v oh high level output ioh = -100ua ioh = -2ma vdd3-0.2 2.4 v v
sta308a 6/45 4.5 pll: phase locked loop the phase locked loop section provides the system timing signals and ckout. 4.6 ckout: clock out system synchronization and master clocks are provided by the ckout. 4.7 out1 through out8: pwm outputs the pwm outputs provide the input signal for the power devices. 4.8 eapd: external amplifier power-down this signal can be used to control the power-down of ddx power devices. 4.9 sdo_12 through 78: serial data out audio information exits the device here. six different format choices are available including i2s, left- or right- justified, lsb or msb first, with word widths of 16, 18, 20 and 24 bits. 4.10 pwdn: device power-down this puts the sta308a into a low-power state via appropriate power-down sequence. pulling pwdn low begins power-down sequence, and eapd goes low ~30ms later. 5i 2 c bus specification the sta308a supports the i 2 c protocol via the input ports scl and sda_in (master to slave) and the output port sda_out (slave to master). this protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. the device that controls the data transfer is known as the master and the other as the slave. the master always starts the transfer and provides the serial clock for synchronization. the sta308a is always a slave device in all of its communications. 5.1 communication protocol 5.1.1 data transition or change data changes on the sda line must only occur when the scl clock is low. sda transition while the clock is high is used to identify a start or stop condition. 5.1.2 start condition start is identified by a high to low transition of the data bus sda signal while the clock signal scl is stable in the high state. a start condition must precede any command for data transfer. 5.1.3 stop condition stop is identified by low to high transition of the data bus sda signal while the clock signal scl is stable in the high state. a stop condition terminates communication between sta308a and the bus master. 5.1.4 data input during the data input the sta308a samples the sda signal on the rising edge of clock scl. for correct device operation the sda signal must be stable during the rising edge of the clock and the data can change only when the scl line is low.
7/45 sta308a 5.2 device addressing to start communication between the master and the omega ddx core, the master must initiate with a start con- dition. following this, the master sends onto the sda line 8-bits (msb first) corresponding to the device select address and read or write mode. the 7 most significant bits are the device address identifiers, corresponding to the i 2 c bus definition. in the sta308a the i 2 c interface has two device addresses depending on the sa port configuration, 0x40 or 0100000x when sa = 0, and 0x42 or 0100001x when sa = 1. the 8 th bit (lsb) identifies read or write operation rw, this bit is set to 1 in read mode and 0 for write mode. after a start condition the sta308a identifies on the bus the device address and if a match is found, it ac- knowledges the identification on sda bus during the 9 th bit time. the byte following the device identification byte is the internal space address. 5.3 write operation following the start condition the master sends a device select code with the rw bit set to 0. the sta308a acknowledges this and the writes for the byte of internal address. after receiving the internal byte address the sta308a again responds with an acknowledgement. 5.3.1 byte write in the byte write mode the master sends one data byte, this is acknowledged by the omega ddx core. the master then terminates the transfer by generating a stop condition. 5.3.2 multi-byte write the multi-byte write modes can start from any internal address. the master generating a stop condition ter- minates the transfer. figure 5. write mode sequence figure 6. read mode sequence dev-addr ack start rw sub-addr ack data in ack stop byte write dev-addr ack start rw sub-addr ack data in ack stop multibyte write data in ack dev-addr ack start rw data no ack stop current address read dev-addr ack start rw sub-addr ack dev-addr ack stop random address read data no ack start rw dev-addr ack start data ack data ack stop sequential current read data no ack dev-addr ack start rw sub-addr ack dev-addr ack sequential random read data ack start rw data ack no ack stop data rw = high
sta308a 8/45 6 register summary table 8. register summary address name d7 d6 d5 d4 d3 d2 d1 d0 0x00 confa cos1 cos0 dspb ir1 ir0 mcs2 mcs1 mcs0 0x01 confb saifb sai3 sai2 sai1 sai0 0x02 confc saofb sao3 sao2 sao1 sao0 0x03 confd mpc csz4 csz3 csz2 csz1 csz0 om1 om0 0x04 confe c8bo c7bo c6bo c5bo c4bo c3bo c2bo c1bo 0x05 conff pwms2 pwms1 pwms0 bql psl demp drc hpb 0x06 confg mpcv dccv hpe am2e ame cod sid pwmd 0x07 confh ecle ldte bcle ide zde sve zce nsbw 0x08 confi eapd psce 0x09 mmute mmute 0x0a mvol mv7 mv6 mv5 mv4 mv3 mv2 mv1 mv0 0x0b c1vol c1v7 c1v6 c1v5 c1v4 c1v3 c1v2 c1v1 c1v0 0x0c c2vol c2v7 c2v6 c2v5 c2v4 c2v3 c2v2 c2v1 c2v0 0x0d c3vol c3v7 c3v6 c3v5 c3v4 c3v3 c3v2 c3v1 c3v0 0x0e c4vol c4v7 c4v6 c4v5 c4v4 c4v3 c4v2 c4v1 c4v0 0x0f c5vol c5v7 c5v6 c5v5 c5v4 c5v3 c5v2 c5v1 c5v0 0x10 c6vol c6v7 c6v6 c6v5 c6v4 c6v3 c6v2 c6v1 c6v0 0x11 c7vol c7v7 c7v6 c7v5 c7v4 c7v3 c7v2 c7v1 c7v0 0x12 c8vol c8v7 c8v6 c8v5 c8v4 c8v3 c8v2 c8v1 c8v0 0x13 c1vtmb c1m c1vbp c1vt4 c1vt3 c1vt2 c1vt1 c1vt0 0x14 c2vtmb c2m c2vbp c2vt4 c2vt3 c2vt2 c2vt1 c2vt0 0x15 c3vtmb c3m c3vbp c3vt4 c3vt3 c3vt2 c3vt1 c3vt0 0x16 c4vtmb c4m c4vbp c4vt4 c4vt3 c4vt2 c4vt1 c4vt0 0x17 c5vtmb c5m c5vbp c5vt4 c5vt3 c5vt2 c5vt1 c5vt0 0x18 c6vtmb c6m c6vbp c6vt4 c6vt3 c6vt2 c6vt1 c6vt0 0x19 c7vtmb c7m c7vbp c7vt4 c7vt3 c7vt2 c7vt1 c7vt0 0x1a c8vtmb c8m c8vbp c8vt4 c8vt3 c8vt2 c8vt1 c8vt0 0x1b c12im c2im2 c2im1 c2im0 c1im2 c1im1 c1im0 0x1c c34im c4im2 c4im1 c4im0 c3im2 c3im1 c3im0 0x1d c56im c6im2 c6im1 c6im0 c5im2 c5im1 c5im0 0x1e c78im c8im2 c8im1 c8im0 c7im2 c7im1 c7im0 0x1f auto1 amdm amgc2 amgc1 amgc0 amv1 amv0 ameq1 ameq0 0x20 auto2 sub rss1 rss0 css1 css0 fss ambmxe ambmm e 0x21 auto3 amam2 amam1 amam0 amame msa amps 0x22 preeq xo2 xo1 xo0 peq4 peq3 peq2 peq1 peq0 0x23 ageq ageq4 ageq3 ageq2 ageq1 ageq0 0x24 bgeq bgeq4 bgeq3 bgeq2 bgeq1 bgeq0 0x25 cgeq cgeq4 cgeq3 cgeq2 cgeq1 cgeq0 0x26 dgeq dgeq4 dgeq3 dgeq2 dgeq1 dgeq0 0x27 fgeq egeq4 egeq3 egeq2 egeq1 egeq0 0x28 bqlp c8blp c7blp c6blp c5blp c4blp c3blp c2blp c1blp
9/45 sta308a 0x29 mxlp c8mxlp c7mxlp c6mxlp c5mxlp c4mxlp c3mxlp c2mxlp c1mxlp 0x2a eqbp c8eqbp c7eqbp c6eqbp c5eqbp c4eqbp c3eqbp c2eqbp c1eqbp 0x2b tonebp c8tcb c7tcb c6tcb c5tcb c4tcb c3tcb c2tcb c1tcb 0x2c tone ttc3 ttc2 ttc1 ttc0 btc3 btc2 btc1 btc0 0x2d c1234ls c4ls1 c4ls0 c3ls1 c3ls0 c2ls1 c2ls0 c1ls1 c1ls0 0x2e c5678ls c8ls1 c8ls0 c7ls1 c7ls0 c6ls1 c6ls0 c5ls1 c5ls0 0x2f l1ar l1a3 l1a2 l1a1 l1a0 l1r3 l1r2 l1r1 l1r0 0x30 l1atrt l1at3 l1at2 l1at1 l1at0 l1rt3 l1rt2 l1rt1 l1rt0 0x31 l2ar l2a3 l2a2 l2a1 l2a0 l2r3 l2r2 l2r1 l2r0 0x32 l2atrt l2at3 l2at2 l2at1 l2at0 l2rt3 l2rt2 l2rt1 l2rt0 0x33 c12ot c2ot2 c2ot1 c2ot0 c1ot2 c1ot1 c1ot0 0x34 c34ot c4ot2 c4ot1 c4ot0 c3ot2 c3ot1 c3ot0 0x35 c56ot c6ot2 c6ot1 c6ot0 c5ot2 c5ot1 c5ot0 0x36 c78ot c8ot2 c8ot1 c8ot0 c7ot2 c7ot1 c7ot0 0x37 c12om c2om2 c2om1 c2om0 c1om2 c1om1 c1om0 0x38 c34om c4om2 c4om1 c4om0 c3om2 c3om1 c3om0 0x39 c56om c6om2 c6om1 c6om0 c5om2 c5om1 c5om0 0x3a c78om c8om2 c8om1 c8om0 c7om2 c7om1 c7om0 0x3b cfaddr1 cfa9 cfa8 0x3c cfaddr2 cfa7 cfa6 cfa5 cfa4 cfa3 cfa2 cfa1 cfa0 0x3d b1cf1 c1b23 c1b22 c1b21 c1b20 c1b19 c1b18 c1b17 c1b16 0x3e b1cf2 c1b15 c1b14 c1b13 c1b12 c1b11 c1b10 c1b9 c1b8 0x3f b1cf3 c1b7 c1b6 c1b5 c1b4 c1b3 c1b2 c1b1 c1b0 0x40 b2cf1 c2b23 c2b22 c2b21 c2b20 c2b19 c2b18 c2b17 c2b16 0x41 b2cf2 c2b15 c2b14 c2b13 c2b12 c2b11 c2b10 c2b9 c2b8 0x42 b2cf3 c2b7 c2b6 c2b5 c2b4 c2b3 c2b2 c2b1 c2b0 0x43 a1cf1 c3b23 c3b22 c3b21 c3b20 c3b19 c3b18 c3b17 c3b16 0x44 a1cf2 c3b15 c3b14 c3b13 c3b12 c3b11 c3b10 c3b9 c3b8 0x45 a1cf3 c3b7 c3b6 c3b5 c3b4 c3b3 c3b2 c3b1 c3b0 0x46 a2cf1 c4b23 c4b22 c4b21 c4b20 c4b19 c4b18 c4b17 c4b16 0x47 a2cf2 c4b15 c4b14 c4b13 c4b12 c4b11 c4b10 c4b9 c4b8 0x48 a2cf3 c4b7 c4b6 c4b5 c4b4 c4b3 c4b2 c4b1 c4b0 0x49 b0cf1 c5b23 c5b22 c5b21 c5b20 c5b19 c5b18 c5b17 c5b16 0x4a b0cf2 c5b15 c5b14 c5b13 c5b12 c5b11 c5b10 c5b9 c5b8 0x4b b0cf3 c5b7 c5b6 c5b5 c5b4 c5b3 c5b2 c5b1 c5b0 0x4c cfud wa w1 0x4d mpcc1 mpcc15 mpcc14 mpcc13 mpcc12 mpcc11 mpcc10 mpcc9 mpcc8 0x4e mpcc2 mpcc7 mpcc6 mpcc5 mpcc4 mpcc3 mpcc2 mpcc1 mpcc0 0x4f dcc1 dcc15 dcc14 dcc13 dcc12 dcc11 dcc10 dcc9 dcc8 0x50 dcc2 dcc7 dcc6 dcc5 dcc4 dcc3 dcc2 dcc1 dcc0 0x51 psc1 rcv11 rcv10 rcv9 rcv8 rcv7 rcv6 rcv5 rcv4 0x52 psc2 rcv3 rcv2 rcv1 rcv0 cnv11 cnv10 cnv9 cnv8 0x53 psc3 cnv7 cnv6 cnv5 cnv4 cnv3 cnv2 cnv1 cnv0 address name d7 d6 d5 d4 d3 d2 d1 d0 table 8. register summary (continued)
sta308a 10/45 6.1 configuration register a (address 00h) 6.1.1 master clock select the ddx8000 will support sample rates of 32khz, 44.1khz, 48khz, 88.2khz, 96khz, 176.4khz, 192khz, and 2.8224mhz dsd. therefore the internal clock will be: ? 65.536mhz for 32khz ? 90.3168mhz for 44.1khz, 88.2khz, 176.4khz, and dsd ? 98.304mhz for 48khz, 96khz, and 192khz the external clock frequency provided to the xti pin must be a multiple of the input sample frequency(fs). the relationship between the input clock and the input sample rate is determined by both the mcsx and the irx (in- put rate) register bits. the mcsx bits determine the pll factor generating the internal clock and the irx bits determine the oversampling ratio used internally. table 9. 6.1.2 interpolation ratio select the sta308a has variable interpolation (oversampling) settings such that internal processing and ddx output rates remain consistent. the first processing block interpolates by either 4 times, 2 times, or 1 time (pass- through). the oversampling ratio of this interpolation is determined by the ir bits. 0x54 qsnd qsfs qfour qen 0x55 qsec1 qsec15 qsec14 qsec13 qsec12 qsec11 qsec10 qsec9 qsec8 0x56 qsec2 qsec7 qsec6 qsec5 qsec4 qsec3 qsec2 qsec1 qsec0 0x57 bist1 r6bact r5bact r4bact r3bact r2bact r1bact r0bact 0x58 bist2 r6bend r5bend r4bend r3bend r2bend r1bend r0bend 0x59 bist3 r6bbad r5bbad r4bbad r3bbad r2bbad r1bbad r0bbad d7 d6 d5 d4 d3 d2 d1 d0 cos1 cos0 dspb ir1 ir0 mcs2 mcs1 mcs0 10000011 bit r/w rst name description 0 r/w 1 mcs0 master clock select : selects the ratio between the input i 2 s sample frequency and the input clock. 1r/w 1 mcs1 2r/w 0 mcs2 input sample rate fs (khz) ir mcs(2..0) 1xx 011 010 001 000 32, 44.1, 48 00 128fs 256fs 384fs 512fs 768fs 88.2, 96 01 64fs 128fs 192fs 256fs 384fs 176.4, 192 10 64fs 128fs 192fs 256fs 384fs dsd 11 2fs 4fs 6fs 8fs 10fs bit r/w rst name description 3 r/w 0 ir0 interpolation ratio select: selects internal interpolation ratio based on input i 2 s sample frequency 4r/w 0 ir1 address name d7 d6 d5 d4 d3 d2 d1 d0 table 8. register summary (continued)
11/45 sta308a table 10. ir bit settings as a function of input sample rate.i 6.1.3 dsp bypass9 setting the dspb bit bypasses the biquad functionality of the omega ddx core. 6.1.4 clock output select: 6.2 serial input formats(address 01h) 6.2.1 6.2.2 serial data interface the sta308a audio serial input was designed to interface with standard digital audio components and to accept a number of serial data formats. sta308a always acts a slave when receiving audio input from standard digital audio components. serial data for eight channels is provided using 6 input pins: left/right clock lrcki (pin xx), serial clock bicki (pin xx), serial data 1 & 2 sdi12 (pin xx), serial data 3 & 4 sdi34 (pin xx), serial data 5 & 6 sdi56 (pin xx), and serial data 7 & 8 sdi78 (pin xx). the sai register (configuration register x - xxh, bits dx- dx) and the saifb register (configuration register x - 0xh, bit dx) are used to specify the serial data format. the default serial data format is i2s, msb-first. available formats are shown in the tables and figure that follow. input sample rate fs (khz) ir(1,0) 1 st stage interpolation ratio 32 00 4 times oversampling 44.1 00 4 times oversampling 48 00 4 times oversampling 88.2 01 2 times oversampling 96 01 2 times oversampling 176.4 10 pass-through 192 10 pass-through dsd 11 dsd -> 176.4khz conversion bit r/w rst name description 0 r/w 0 dspb dsp bypass bit: 0 ? normal operation 1 ? bypass of biquad and bass/treble functionality cos(1,0) ckout frequency 00 pll output 01 pll output/4 10 pll output/8 11 pll output/16 d7 d6 d5 d4 d3 d2 d1 d0 saifb sai3 sai2 sai1 sai0 0 0000 bit r/w rst name description 0 r/w 0 sai0 serial audio input interface format: determines the interface format of the input serial digital audio interface. 1 r/w 0 sai1 2 r/w 0 sai2 3 r/w 0 sai3
sta308a 12/45 table 11. serial data first bit note: serial input and output formats (see section 8.2) are specified distinctly for example, sai=1110 and saifb=1 would specify right-justified 16-bit data, lsb-first. table 4 below lists the serial audio input formats supported by sta308a as related to bicki = 32/48/64fs, where sampling rate fs = 32/44.1/48/88.2/96/176.4/192 khz. saifb format 0msb-first 1 lsb-first table 12. supported serial audio input formats bicki sai (3...0) saifb interface format 32fs 1100 x i 2 s 15bit data 1110 x left/right-justified 16bit data 48fs 0100 x i 2 s 23bit data 0100 x i 2 s 20bit data 1000 x i 2 s 18bit data 0100 0 msb first i 2 s 16bit data 1100 1 lsb first i 2 s 16bit data 0001 x left-justified 24bit data 0101 x left-justified 20bit data 1001 x left-justified 18bit data 1101 x left-justified 16bit data 0010 x right-justified 24bit data 0110 x right-justified 20bit data 1010 x right-justified 18bit data 1110 x right-justified 16bit data 64fs 0000 x i 2 s 24bit data 0100 x i 2 s 20bit data 1000 x i 2 s 18bit data 0000 0 msb first i 2 s 16bit data 1100 1 lsb first i 2 s 16bit data 0001 x left-justified 24bit data 0101 x left-justified 20bit data 1001 x left-justified 18bit data 1101 x left-justified 16bit data 0010 x right-justified 24bit data 0110 x right-justified 20bit data 1010 x right-justified 18bit data 1110 x right-justified 16bit data
13/45 sta308a 6.3 6.3.1 ddx power output mode the ddx power output mode selects how the ddx output timing is configured. different power devices use different output modes. the ddx-2060 recommended use is om = 10. table 13. output modes 6.3.2 ddx compensating pulse size register table 14. compensating pulse size 6.3.3 max power correction setting the mpc bit turns on special processing that corrects the ddx-2060 power device at high power. this mode should lower the thd+n of a full ddx-2060 ddx system at maximum power output and slightly below. this mode will only be operational in om(1,0) = 01. d7 d6 d5 d4 d3 d2 d1 d0 mpc csz4 csz3 csz2 csz1 csz0 om1 om0 11000010 bit r/w rst name description 0 r/w 0 om0 ddx power output mode: selects configuration of ddx output. 1r/w 1 om1 om(1,0) output stage ? mode 00 ddx-2060/2100 ? drop compensation 01 discrete output stage ? tapered compensation 10 ddx-2060/2100 ? full power mode 11 variable drop compensation (cszx bits) bit r/w rst name description 2 r/w 0 csz0 contra size register: when om(1,0) = 11, this register determines the size of the ddx compensating pulse from 0 clock ticks to 31 clock periods. 3r/w 0 csz1 4r/w 0 csz2 5r/w 0 csz3 6r/w 1 csz4 csz(4..0) compensating pulse size 00000 0 clock period compensating pulse size 00001 1 clock period compensating pulse size ?? 11111 31 clock period compensating pulse size bit r/w rst name description 7 r/w 1 mpc max power correction: setting of 1 enables ddx-2060 correction for thd reduction near maximum power output.
sta308a 14/45 6.4 6.4.1 binary output enable registers each individual channel output can be set to output a binary pwm stream. in this mode output a of a channel will be considered the positive output and output b is negative inverse. 6.5 6.5.1 high-pass filter bypass the sta308a features an internal digital high-pass filter for the purpose of ac coupling. the purpose of this filter is to prevent dc signals from passing through a ddx amplifier. dc signals can cause speaker damage. if hpb = 1, then the filter that the high-pass filter utilizes is made available as user-programmable biquad#1. 6.5.2 dynamic range compression/anti-clipping bit both limiters can be used in one of two ways, anti-clipping or dynamic range compression. when used in anti- clipping mode the limiter threshold values are constant and dependent on the limiter settings. in dynamic range compression mode the limiter threshold values vary with the volume settings allowing a night- time listening mode that provides a reduction in the dynamic range regardless of the volume level. d7 d6 d5 d4 d3 d2 d1 d0 c8bo c7bo c6bo c5bo c4bo c3bo c2bo c1bo 00000000 bit r/w rst name description 0 r/w 0 c1bo channels 1, 2, 3, 4, 5, 6, 7, & 8 binary output mode enable bits. a setting of 0 indicates ordinary ddx tri-state output. a setting of 1 indicates binary output mode. 1r/w 0 c2bo 2r/w 0 c3bo 3r/w 0 c4bo 4r/w 0 c5bo 5r/w 0 c6bo 6r/w 0 c7bo 7r/w 0 c8bo d7 d6 d5 d4 d3 d2 d1 d0 pwms2 pwms1 pwms0 bql psl demp drc hpb 00000000 bit r/w rst name description 0 r/w 0 hpb high-pass filter bypass bit. setting of one bypasses internal ac coupling digital high-pass filter bit r/w rst name description 1 r/w 0 drc dynamic range compression/anti-clipping 0 ? limiters act in anti-clipping mode 1 ? limiters act in dynamic range compression mode
15/45 sta308a 6.5.3 de-emphasis by setting this bit to one de-emphasis will implemented on all channels. when this is used it takes the place of biquad #7 in each channel and any coefficients using biquad #1 will be ignored. dspb(dsp bypass) bit must be set to 0 for de-emphasis to function. 6.5.4 post-scale link post-scale functionality can be used for power-supply error correction. for multi-channel applications running off the same power-supply, the post-scale values can be linked to the value of channel 1 for ease of use and update the values faster. 6.5.5 biquad coefficient link for ease of use, all channels can use the biquad coefficients loaded into the channel 1 coefficient ram space by setting the bql bit to 1. therefore, any eq updates only have to be performed once. 6.5.6 pwm speed mode table 15. 6.6 table 16. bit r/w rst name description 2 r/w 0 demp de-emphasis: 0 ? no de-emphasis 1 ? de-emphasis bit r/w rst name description 3 r/w 0 psl post-scale link: 0 ? each channel uses individual post-scale value 1 ? each channel uses channel 1 post-scale value bit r/w rst name description 4 r/w 0 bql biquad link: 0 ? each channel uses coefficient values 1 ? each channel uses channel 1 coefficient values bit r/w rst name description 7..5 r/w 00 pwms(2..0) pwm speed selection: pwms(1..0) pwm output speed 000 normal speed(384khz) all channels 001 half speed(192khz) all channels 010 double speed(768khz) all channels 011 normal speed channels 1-6, double speed channels 7-8 100 odd speed(341.3khz) all channels d7 d6 d5 d4 d3 d2 d1 d0 mpcv dccv hpe am2e ame cod sid pwmd 00000000
sta308a 16/45 6.6.1 output signal disables 6.6.2 am mode enable the sta308a features a ddx processing mode that minimizes the amount of noise generated in frequency range of am radio. this mode is intended for use when ddx is operating in a device with an am tuner active. the snr of the ddx processing is reduced to ~83db in this mode, which is st ill greater t han the snr of am radio. 6.6.3 am2 mode enable the sta308a features a 2 ddx processing modes that minimize the amount of noise generated in frequency range of am radio. this second mode is intended for use when ddx is operating in a device with an am tuner active. this mode eliminates the noise-shaper. 6.6.4 headphone enable channels 7 and 8 can be configured to be processed and output in such a manner that headphones can be driven using and appropriate output device. this signal is a fully differential 3-wire drive called ddx headphone. 6.6.5 distortion compensation variable enable bit r/w rst name description 0 r/w 0 pwmd pwm output disable: 0 - pwm output normal 1 - no pwm output 1r/w 0 sid serial interface(i 2 s out) disable: 0 - i 2 s output normal 1 - no i 2 s output 2 r/w 0 cod clock output disable: 0 - clock output normal 1 - no clock output bit r/w rst name description 3 r/w 0 ame am mode enable: 0 ? normal ddx operation. 1 ? am reduction mode ddx operation. bit r/w rst name description 4 r/w 0 am2e am2 mode enable: 0 ? normal ddx operation. 1 ? am2 reduction mode ddx operation. bit r/w rst name description 5 r/w 0 hpe ddx headphone enable: 0 ? channels 7 & 8 normal ddx operation 1 ? channels 7 & 8 headphone operation bit r/w rst name description 6 r/w 0 dccv distortion compensation variable enable: 0 ? uses preset dc coefficient. 1 ? uses dcc coefficient.
17/45 sta308a 6.6.6 max power correction variable 6.7 conf h table 17. 6.7.1 noise-shaper bandwidth selection 6.7.2 zero-crossing volume enable the zce bit enables zero-crossing volume adjustments. when volume is adjusted on digital zero-crossings no clicks will be audible. 6.7.3 soft volume update enable 6.7.4 zero-detect mute enable setting the zde bit enables the zero-detect automatic mute. the zero-detect circuit looks at the input data to each processing channel after the channel-mapping block. if any channel receives 2048 consecutive zero value samples (regardless of fs) then that individual channel is muted if this function is enabled. 6.7.5 invalid input detect mute enable setting the ide bit enables this function, which looks at the input i2s data and will automatically mute if the sig- nals are perceived as invalid. bit r/w rst name description 7 r/w 0 mpcv max power correction variable: 0 ? use standard mpc coefficient 1 ? use mpcc bits for mpc coefficient d7 d6 d5 d4 d3 d2 d1 d0 ecle ldte bcle ide zde sve zce nsbw 01111110 bit r/w rst name description 0 r/w 0 nsbw noise-shaper bandwidth selection: 1 ? 3 rd order ns 0 ? 4 th order ns bit r/w rst name description 1 r/w 1 zce zero-crossing volume enable: 1 ? volume adjustments will only occur at digital zero-crossings 0 ? volume adjustments will occur immediately bit r/w rst name description 2 r/w 1 sve soft volume enable: 1 ? volume adjustments ramp according to svr settings 0 ? volume adjustments will occur immediately bit r/w rst name description 3 r/w 1 zde zero-detect mute enable: setting of 1 enables the automatic zero-detect mute bit r/w rst name description 4 r/w 1 ide invalid input detect mute enable: setting of 1 enables the automatic invalid input detect mute
sta308a 18/45 6.7.6 detects loss of input mclk in binary mode and w ill output 50% duty cycle. 6.7.7 actively prevents double trigger of lrclk. 6.7.8 when active w ill issue a power device power down si gnal(eapd) on clock loss detection 6.8 conf table 18. i 6.8.1 pscorrect? enable this feature utilizes an adc on sdi78 that provides power supply ripple information for correction. registers psc1, psc2, psc3 are utilized in this mode. 6.8.2 external amplifier power down 6.8.3 master mute register 6.8.4 master volume register note : value of volume derived from mvol is dependent on amv automode volume settings. bit r/w rst name description 5 r/w 1 bcle binary output mode clock loss detection enable bit r/w rst name description 6 r/w 1 ldte lrclk double trigger protection enable bit r/w rst name description 7 r/w 0 ecle auto eapd on clock loss d7 d6 d5 d4 d3 d2 d1 d0 eapd psce 0 0 bit r/w rst name description 0 r/w 0 psce power supply ripple correction enable: 0 ? normal operation 1 ? pscorrect operation bit r/w rst name description 7 r/w 0 eapd external amplifier power down: 0 ? external power stage power down active 1 ? normal operation d7 d6 d5 d4 d3 d2 d1 d0 mmute 0 d7 d6 d5 d4 d3 d2 d1 d0 mv7 mv6 mv5 mv4 mv3 mv2 mv1 mv0 11111111
19/45 sta308a 6.8.5 channels 1,2,3,4,5,6,7,8 mute 6.8.6 channel 1 volume 6.8.7 channel 2 volume 6.8.8 channel 3 volume 6.8.9 channel 4 volume 6.8.10channel 5 volume 6.8.11channel 6 volume 6.8.12channel 7 volume 6.8.13channel 8 volume 6.8.14channel 1 volume trim, mute, bypass d7 d6 d5 d4 d3 d2 d1 d0 c8m c7m c6m c5m c4m c3m c2m c1m 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c1v7 c1v6 c1v5 c1v4 c1v3 c1v2 c1v1 c1v0 01100000 d7 d6 d5 d4 d3 d2 d1 d0 c2v7 c2v6 c2v5 c2v4 c2v3 c2v2 c2v1 c2v0 01100000 d7 d6 d5 d4 d3 d2 d1 d0 c3v7 c3v6 c3v5 c3v4 c3v3 c3v2 c3v1 c3v0 01100000 d7 d6 d5 d4 d3 d2 d1 d0 c4v7 c4v6 c4v5 c4v4 c4v3 c4v2 c4v1 c4v0 01100000 d7 d6 d5 d4 d3 d2 d1 d0 c5v7 c5v6 c5v5 c5v4 c5v3 c5v2 c5v1 c5v0 01100000 d7 d6 d5 d4 d3 d2 d1 d0 c6v7 c6v6 c6v5 c6v4 c6v3 c6v2 c6v1 c6v0 01100000 d7 d6 d5 d4 d3 d2 d1 d0 c7v7 c7v6 c7v5 c7v4 c7v3 c7v2 c7v1 c7v0 01100000 d7 d6 d5 d4 d3 d2 d1 d0 c8v7 c8v6 c8v5 c8v4 c8v3 c8v2 c8v1 c8v0 01100000 d7 d6 d5 d4 d3 d2 d1 d0 c1m c1vbp c1vt4 c1vt3 c1vt2 c1vt1 c1vt0 00010000
sta308a 20/45 6.8.15channel 2 volume trim, mute, bypass 6.8.16channel 3 volume trim, mute, bypass 6.8.17channel 4 volume trim, mute, bypass 6.8.18channel 5 volume trim, mute, bypass 6.8.19channel 6 volume trim, mute, bypass 6.8.20channel 7 volume trim, mute, bypass 6.8.21channel 8 volume trim, mute, bypass the volume structure of the sta308a consists of individual volume registers for each channel and a master volume register that provides an offset to each channels volume setting. there is also an additional offset for each channel called the channel volume trim. the individual channel volumes are adjustable in 0.5db steps from +48db to -78 db. as an example if c5v = xxh or +xxxdb and mv = xxh or -xxdb, then the total gain for channel 5 = xxdb. the channel volume trim is adjustable independently on each channel from -10db to +10db in 1 db steps. the master mute when set to 1 will mute all channels at once, whereas the individual channel mutes(cxm) will mute only that channel. both the master mute and the channel mutes provide a "soft mute" with the volume ramping down to mute in 8192 samples from the maximum volume setting at the internal pro- cessing rate(~192khz). a "hard mute" can be obtained by commanding a value of all 1's(255) to any channel volume register or the master volume register. when volume offsets are provided via the master volume reg- ister any channel that whose total volume is less than -91db will be muted. all changes in volume take place at zero-crossings when zce = 1(configuration register b) on a per channel basis as this creates the smoothest possible volume transitions. when zce=0, volume updates w ill occur immediately. each c hannel also contains an individual channel volume bypass. if a particular channel has volume bypassed via the cxvbp = 1 register then only the channel volume setting for that particular channel affects the volume setting, the master volume setting will not affect that channel. each channel also contains a channel mute. if cxm = 1 a soft mute is per- formed on that channel. d7 d6 d5 d4 d3 d2 d1 d0 c2m c2vbp c2vt4 c2vt3 c2vt2 c2vt1 c2vt0 00010000 d7 d6 d5 d4 d3 d2 d1 d0 c3m c3vbp c3vt4 c3vt3 c3vt2 c3vt1 c3vt0 00010000 d7 d6 d5 d4 d3 d2 d1 d0 c4m c4vbp c4vt4 c4vt3 c4vt2 c4vt1 c4vt0 00010000 d7 d6 d5 d4 d3 d2 d1 d0 c5m c5vbp c5vt4 c5vt3 c5vt2 c5vt1 c5vt0 00010000 d7 d6 d5 d4 d3 d2 d1 d0 c6m c6vbp c6vt4 c6vt3 c6vt2 c6vt1 c6vt0 00010000 d7 d6 d5 d4 d3 d2 d1 d0 c7m c7vbp c7vt4 c7vt3 c7vt2 c7vt1 c7vt0 00010000 d7 d6 d5 d4 d3 d2 d1 d0 c8m c8vbp c8vt4 c8vt3 c8vt2 c8vt1 c8vt0 00010000
21/45 sta308a table 19. master volume offset as a function of mv(7..0). table 20. channel volume as a function of cxv(7..0) table 21. mv(7..0) volume offset from channel value 00000000(00h) 0db 00000001(01h) -0.5db 00000010(02h) -1db ?? 01001100(4ch) -38db ?? 11111110(feh) -127db 11111111(ffh) hard master mute cxv(7..0) volume 00000000(00h) +48db 00000001(01h) +47.5db 00000010(02h) +47db ?? 01100001(5fh) +0.5db 01100000(60h) 0db 01011111(61h) -0.5db ?? 11111110(feh) -79.5 db 11111111(ffh) hard channel mute cxvt(4..0) volume 00000(00h) +10db ?? 00110(06h) +10db 00111(07h) +9db ?? 01111(0fh) +1db 10000(10h) 0db 10001(11h) -1db ?? 11001(19h) -9db 11010(1ah) -10db ?? 11111(1fh) -10db
sta308a 22/45 6.9 input mapping 6.9.1 channel input mapping channels 1 & 2 6.9.2 channel input mapping channels 3 & 4 6.9.3 channel input mapping channels 5 & 6 6.9.4 channel input mapping channels 7 & 8 each channel received via i2s can be mapped to any internal processing channel via the channel input map- ping registers. this allows for flexibility in processing, simplifies output stage designs, and enables the ability to perform crossovers. the default settings of these registers map each i2s input channel to its corresponding processing channel. table 22. channel mapping as a function of cxim bits. 6.10 automode? registers: 6.10.1register - automodes eq, volume, gc 6.10.2automode eq d7 d6 d5 d4 d3 d2 d1 d0 c2im2 c2im1 c2im0 c1im2 c1im1 c1im0 001 000 d7 d6 d5 d4 d3 d2 d1 d0 c4im2 c4im1 c4im0 c3im2 c3im1 c3im0 011 010 d7 d6 d5 d4 d3 d2 d1 d0 c6im2 c6im1 c6im0 c5im2 c5im1 c5im0 101 100 d7 d6 d5 d4 d3 d2 d1 d0 c8im2 c8m1 c8im0 c7im2 c7im1 c7im0 111 1 1 0 cxim(2..0) serial input from 000 channel 1 001 channel 2 010 channel 3 011 channel 4 100 channel 5 101 channel 6 110 channel 7 111 channel 8 d7 d6 d5 d4 d3 d2 d1 d0 amdm amgc2 amgc1 amgc0 amv1 amv0 ameq1 ameq0 00000000 ameq(1,0) mode(biquad 2-6) 00 user programmable 01 preset eq ? peq bits 10 graphic eq ? xgeq bits 11 auto volume controlled loudness curve
23/45 sta308a by setting ameq to any setting other than 00 enables automode eq, biquads 1-5 are not user programmable. any coefficient settings for these biquads will be ignored. also when automode eq is used the pre-scale value for channels 1-6 becomes hard-set to -18db. 6.10.3automode volume 6.10.4automode gain compression/limiters 6.10.5amdm - automode 5.1 downmix automode downmix setting uses channels 7-8 of mix#1 engine and therefore these channels of this function are hard-set and not allowed to be user set when in this mode. channels 1-6 must be arranged via channel mapping (cxim) if necessary in the following manner for this op- eration: channel 1 - left channel 2 - right channel 3 - left surround channel 4 - right surround channel 5 - center channel 6 - lfe 6.10.6register - automodes bass management2 6.10.7 amv(1,0) mode(mvol) 00 mvol 0.5db 256 steps(standard) 01 mvol auto curve 30 steps 10 mvol auto curve 40 steps 11 mvol auto curve 50 steps amgc(2..0) mode 000 user programmable gc 001 ac no clipping 010 ac limited clipping(10%) 011 drc nighttime listening mode 100 drc tv commercial/channel agc 101 ac 5.1 no clipping 110 ac 5.1 limited clipping(10%) bit r/w rst name description 7 r/w 0 amdm 0 ? normal operation 1 ? channels 7-8 are 2 channel downmix of channels 1-6 d7 d6 d5 d4 d3 d2 d1 d0 sub rss1 rss0 css1 css0 fss ambmxe ambmme 10000000 bit r/w rst name description 0 r/w 0 ambmme 0 ? automode bass management mix disabled 1 ? automode bass management mix enabled
sta308a 24/45 6.10.8 setting the ambmme bit enables the proper mixing to take place for various preset bass management config- urations. setting the ambmxe bit enables the proper crossover filtering in biquad #7 to take place. the cross- over for bass management is always 2 nd order (24db/octave) and the frequency of crossover is determined by the xox bits in preset eq register. all configurations of dolby bass-management can be performed in the ic. these different configurations are selected as they would be by the end-user. the automode bass management settings utilize channels 1-6 on the mix #1 engine, channels 1-6 biquad #6, and channels 1-2 on the mix#2 engine in configuration #2. these functions cannot be user programmed while the bass management automode is active. not all settings are valid as some configurations are unlikely and do not have to be supported be dolby speci- fication. automatic crossover settings are pr ovided or custom crossovers can be implemented using the xxxxx settings in the ram array. input channels must be mapped using channel-mapping feature in the following manner for bass management to be performed properly. 1 - left front 2 - right front 3 - left rear 4 - right rear 5 - center 6 - lfe table 23. table 24. when ambmxe = 1, biquad #7 on channels 1-6 are utilized for bass-management crossover filter, this biquad is not user programmable in this mode. the xo settings determine the crossover frequency used, the crossover is 2 nd order for both high-pass and low-pass with a -3db cross point. higher order filters can be obtained be programming coefficients in other biquads if desired. it is recommended to use settings of 120-160hz when using small, single driver sate llite s peakers as the fre- quency response of these speakers normally are limited to this region. bit r/w rst name description 1 r/w 0 ambmxe 0 ? automode bass management crossover disabled 1 ? automode bass management crossover enabled register/setting 10 01 00 css ? center speaker size off large small rss ? rear speaker size off large small register/setting 1 0 fss ? front speaker size large small sub - subwoofer on off
25/45 sta308a 6.10.9register - auto3 automode am/pre-scale/bass management scale 6.10.10 6.10.11 6.10.12 table 25. automode am switching frequency selection 6.10.13register - preset eq settings table 26. d7 d6 d5 d4 d3 d2 d1 d0 amam2 amam1 amam0 amame msa amps 0000 00 bit r/w rst name description 0 r/w 0 amps automode pre-scale 0 ? -18db used for pre-scale when ameq /= 00 1 ? user defined pre-scale when ameq /= 00 bit r/w rst name description 1 r/w 0 msa bass management mix scale adjustment 0 ? -12db scaling on satellite channels in config #1 1 ? no scaling on satellite channels in config #1 bit r/w rst name description 4 r/w 0 amame automode am enable 0 ? switching frequency determined by pwms settings 1 ? switching frequency determined by amam settings amam(2..0) 48khz/96khz input fs 44.1khz/88.2khz input fs 000 0.535mhz ? 0.720mhz 0.535mhz ? 0.670mhz n 001 0.721mhz ? 0.900mhz 0.671mhz ? 0.800mhz o 010 0.901mhz ? 1.100mhz 0.801mhz ? 1.000mhz n 011 1.101mhz ? 1.300mhz 1.001mhz ? 1.180mhz o 100 1.301mhz ? 1.480mhz 1.181mhz ? 1.340mhz n 101 1.481mhz ? 1.600mhz 1.341mhz ? 1.500mhz o 110 1.601mhz ? 1.700mhz 1.501mhz ? 1.700mhz n d7 d6 d5 d4 d3 d2 d1 d0 xo2 xo1 xo0 peq4 peq3 peq2 peq1 peq0 10100000 xo(2..0) bass management crossover frequency 000 70 hz 001 80 hz 010 90 hz 011 100 hz 100 110 hz 101 120 hz 110 140 hz 111 160 hz
sta308a 26/45 table 27. 6.10.14register ? graphic eq 80hz band 6.10.15register ? graphic eq 300hz band peq(3..0) setting 00000 flat 00001 rock 00010 soft rock 00011 jazz 00100 classical 00101 dance 00110 pop 00111 soft 01000 hard 01001 party 01010 vocal 01011 hip-hop 01100 dialog 01101 bass-boost #1 01110 bass-boost #2 01111 bass-boost #3 10000 loudness 1 10001 loudness 2 10010 loudness 3 10011 loudness 4 10100 loudness 5 10101 loudness 6 10110 loudness 7 10111 loudness 8 11000 loudness 9 11001 loudness 10 11010 loudness 11 11011 loudness 12 11100 loudness 13 11101 loudness 14 11110 loudness 15 11111 loudness 16 d7 d6 d5 d4 d3 d2 d1 d0 ageq4 ageq3 ageq2 ageq1 ageq0 01111 d7 d6 d5 d4 d3 d2 d1 d0 bgeq4 bgeq3 bgeq2 bgeq1 bgeq0 01111
27/45 sta308a 6.10.16register ? graphic eq 1khz band 6.10.17register ? graphic eq 3khz band 6.10.18register ? graphic eq 8khz band table 28. 6.10.19biquad internal channel loop-through each internal processing channel can receive two possible inputs at the input to the biquad block as shown in figure x. the input can be received from the output of that channels mix#1 engine or from the output of bass/treble(bi- quad#10) of the previous channel. in this scenario channel 1 would receive channel 8. this enables the use of more than 10 biquads on any given channel at the loss of the number of separate internal processing channels. cxblp: 0 - input from channel x mix#1 engine output - normal operation 1 - input from channel x-1 biquad #10 output - loop operation d7 d6 d5 d4 d3 d2 d1 d0 cgeq4 cgeq3 cgeq2 cgeq1 cgeq0 01111 d7 d6 d5 d4 d3 d2 d1 d0 dgeq4 dgeq3 dgeq2 dgeq1 dgeq0 01111 d7 d6 d5 d4 d3 d2 d1 d0 egeq4 egeq3 egeq2 egeq1 egeq0 01111 xgeq(4..0) boost/cut 11111 +16 11110 +15 11101 +14 ?? 10000 +1 01111 0 01110 -1 ?? 00001 -14 00000 -15 d7 d6 d5 d4 d3 d2 d1 d0 c8blp c7blp c6blp c5blp c4blp c3blp c2blp c1blp 00000000
sta308a 28/45 6.10.20mix internal channel loop-through each internal processing channel can receive two possible sets of inputs at the inputs to the mix#1 block as shown in figure x. the inputs can be received from the outputs of the interpolation block as normally oc- curs(cxmxlp = 0) or the inputs can be received from the outputs of the mix#2 block. this enables the ability to perform additional filtering after the second mix block at the expense of losing this processing capability on the channel. cxmxlp: 0 - inputs to channel x mix#1 engine from interpolation outputs - normal operation 1 - inputs from channel x mix#1 engine from mix#2 engine outputs - loop operation 6.10.21eq bypass eq control can be bypassed on a per channel basis. if eq control is bypassed on a given channel the prescale and all 10 filters (high-pass, biquads, de-emphasis, bass management cross-over, bass, treble in any combina- tion) are bypassed for that channel. cxeqbp: 0 ? perform eq on channel x ? normal operation 1 ? bypass eq on channel x 6.10.22tone control bypass tone control(bass/treble) can be bypassed on a per channel basis. if tone control is bypassed on a given chan- nel the two filters that tone control utilizes are made available as user programmable biquads #9 and #10. 6.10.23tone control d7 d6 d5 d4 d3 d2 d1 d0 c8mxlp c7mxlp c6mxlp c5mxlp c4mxlp c3mxlp c2mxlp c1mxlp 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c8eqbp c7eqbp c6eqbp c5eqbp c4eqcbp c3eqbp c2eqbp c1eqbp 0000 0 000 d7 d6 d5 d4 d3 d2 d1 d0 c8tcb c7tcb c6tcb c5tcb c4tcb c3tcb c2tcb c1tcb 00000000 d7 d6 d5 d4 d3 d2 d1 d0 ttc3 ttc2 ttc1 ttc0 btc3 btc2 btc1 btc0 01110 1 1 1
29/45 sta308a 6.10.24tone control boost/cut as a function of btc and ttc bits. 6.11 dynamics control 6.11.1channel limiter select channels 1,2,3,4 6.11.2channel limiter select channels 5,6,7,8 6.11.3limiter 1 attack/release rate 6.11.4limiter 1 attack/release threshold 6.11.5limiter 2 attack/release rate 6.11.6limiter 2 attack/release threshold btc(3..0)/ttc(3..0) boost/cut 0000 -12db 0001 -12db ?? 0111 -4db 0110 -2db 0111 0db 1000 +2db 1001 +4db ?? 1101 +12db 1110 +12db 1111 +12db d7 d6 d5 d4 d3 d2 d1 d0 c4ls1 c4ls0 c3ls1 c3ls0 c2ls1 c2ls0 c1ls1 c1ls0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c8ls1 c8ls0 c7ls1 c7ls0 c6ls1 c6ls0 c5ls1 c5ls0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 l1a3 l1a2 l1a1 l1a0 l1r3 l1r2 l1r1 l1r0 01101 0 1 0 d7 d6 d5 d4 d3 d2 d1 d0 l1at3 l1at2 l1at1 l1at0 l1rt3 l1rt2 l1rt1 l1rt0 01101001 d7 d6 d5 d4 d3 d2 d1 d0 l2a3 l2a2 l2a1 l2a0 l2r3 l2r2 l2r1 l2r0 01101 0 1 0 d7 d6 d5 d4 d3 d2 d1 d0 l2at3 l2at2 l2at1 l2at0 l2rt3 l2rt2 l2rt1 l2rt0 01101001
sta308a 30/45 the sta308a includes 2 independent limiter blocks. the purpose of the limiters is to automatically reduce the dynamic range of a recording to prevent the outputs from clipping in anti-clipping mode or to actively reduce the dynamic range for a better listening environment such as a night-time listening mode which is often needed for dvds. the two modes are selected via the drc bit in configuration register b, bit 7 address 0x02. each chan- nel can be mapped to either limiter or not mapped, meaning that channel will clip when 0dbfs is exceeded. each limiter will look at the present value of each c hannel that is mapped to it, select the maximum absolute value of all these channels, perform the limiting algorithm on that value, and then if needed adjust the gain of the mapped channels in unison. the limiter attack thresholds are determined by the lxat registers. it is recommended in anti-clipping mode to set this to 0dbfs, which corresponds to the maximum unclipped output power of a ddx amplifier. since gain can be added digitally within the sta308a it is possible to exceed 0dbfs or any other lxat setting, when this occurs, the limiter, when active, will automatically start reducing the gain. the rate at which the gain is reduced when the attack threshold is exceeded is dependent upon the attack rate register setting for that limiter. the gain reduction occurs on a peak-detect algorithm. the release of limiter, when the gain is again increased, is dependent on a rms-detect algorithm. the output of the volume/limiter block is passed through a rms filter. the output of this filter is compared to the release threshold, determined by the release threshold register. when the rms filter output falls below the release threshold, the gain is again increased at a rate dependent upon the release rate register. the gain can never be increased past it's set value and therefore the release will only occur if the limiter has already reduced the gain. the release threshold value can be used to set what is effectively a minimum dynamic range, this is helpful as over-limiting can reduce the dynamic range to virtually zero and cause program material to sound "lifeless". in ac mode the attack and release thresholds are set relative to full-scale. in drc mode the attack threshold is set relative to the maximum volume setting of the channels mapped to that limiter and the release threshold is set relative to the maximum volume setting plus the attack threshold. figure 7. basic limiter and volume flow diagram. table 29. channel limiter mapping as a function of cxls bits cxls(1,0) channel limiter mapping 00 channel has limiting disabled 01 channel is mapped to limiter #1 10 channel is mapped to limiter #2 gain attenuation saturation rms limiter gain/volume input output
31/45 sta308a table 30. limiter attack rate as a function of lxa bits. table 31. limiter release rate as a function of lxr bits. lxa(3..0) attack rate db/ms 0000 3.1584 fast 0001 2.7072 0010 2.2560 0011 1.8048 0100 1.3536 0101 0.9024 0110 0.4512 0111 0.2256 1000 0.1504 1001 0.1123 1010 0.0902 1011 0.0752 1100 0.0645 1101 0.0564 1110 0.0501 1111 0.0451 slow lxr(3..0) release rate db/ms 0000 0.5116 fast 0001 0.1370 0010 0.0744 0011 0.0499 0100 0.0360 0101 0.0299 0110 0.0264 0111 0.0208 1000 0.0198 1001 0.0172 1010 0.0147 1011 0.0137 1100 0.0134 1101 0.0117 1110 0.0110 1111 0.0104 slow
sta308a 32/45 6.12 anti-clipping mode table 32. limiter attack threshold as a function of lxat bits (ac-mode). table 33. limiter release threshold as a as a function of lxrt bits (ac-mode). lxat(3..0) ac(db relative to fs) 0000 -12 0001 -10 0010 -8 0011 -6 0100 -4 0101 -2 0110 0 0111 +2 1000 +3 1001 +4 1010 +5 1011 +6 1100 +7 1101 +8 1110 +9 1111 +10 lxrt(3..0) ac(db relative to fs) 0000 - 0001 -29db 0010 -20db 0011 -16db 0100 -14db 0101 -12db 0110 -10db 0111 -8db 1000 -7db 1001 -6db 1010 -5db 1011 -4db 110 0 -3db 110 1 -2db 1110 -1db 1111 -0db
33/45 sta308a 6.13 dynamic range compression mode table 34. limiter attack threshold as a function of lxat bits (drc-mode). table 35. limiter release threshold as a as a function of lxrt bits (drc-mode). lxat(3..0) drc(db relative to volume) 0000 -31 0001 -29 0010 -27 0011 -25 0100 -23 0101 -21 0110 -19 0111 -17 1000 -16 1001 -15 1010 -14 1011 -13 1100 -12 1101 -10 1110 -7 1111 -4 lxrt(3..0) drc(db relative to volume + lxat) 0000 - 0001 -38db 0010 -36db 0011 -33db 0100 -31db 0101 -30db 0110 -28db 0111 -26db 1000 -24db 1001 -22db 1010 -20db 1011 -18db 1100 -15db 1101 -12db 1110 -9d b 1111 -6db
sta308a 34/45 6.14 pwm output timing 6.14.1channel 1&2 output timing 6.14.2channel 3&4 output timing 6.14.3channel 5&6 output timing 6.14.4channel 7&8 output timing the centering of the individual channel pwm output periods can be adjusted by the output timing registers. pwm slot settings can be chosen to insure that pulse transitions do not occur at the same time on different chan- nels using the same power device. there are 8 possible settings, the appropriate setting varying based on the application and connections to the ddx power devices. table 36. channel output timing as a function of cxot bits. 6.15 i2s output channel mapping 6.15.1channel i2s output mapping channels 1 & 2 6.15.2channel i2s output mapping channels 3 & 4 d7 d6 d5 d4 d3 d2 d1 d0 c2ot2 c2ot1 c2ot0 c1ot2 c1ot1 c1ot0 100 000 d7 d6 d5 d4 d3 d2 d1 d0 c4ot2 c4ot1 c4ot0 c3ot2 c3ot1 c3ot0 110 010 d7 d6 d5 d4 d3 d2 d1 d0 c6ot2 c6ot1 c6ot0 c5ot2 c5ot1 c5ot0 101 001 d7 d6 d5 d4 d3 d2 d1 d0 c8ot2 c8ot1 c8ot0 c7ot2 c7ot1 c7ot0 111 011 cxot(2..0) pwm slot 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 8 d7 d6 d5 d4 d3 d2 d1 d0 c2om2 c2om1 c2om0 c1om2 c1om1 c1om0 001 000 d7 d6 d5 d4 d3 d2 d1 d0 c4om2 c4om1 c4om0 c3om2 c3om1 c3om0 011 010
35/45 sta308a 6.15.3channel i2s output mapping channels 5 & 6 6.15.4channel i2s output mapping channels 7 & 8 each i2s output channel can receive data from any channel output of the volume block. which channel a par- ticular i2s output receives is dependent upon that channels cxom register bits. table 37. channel mapping as a function of cxom bits. 6.16 user-defined coefficient control 6.16.1coefficient address register 1 6.16.2coefficient address register 2 6.16.3coefficient b1data register bits 23..16 6.16.4coefficient b1data register bits 15..8 d7 d6 d5 d4 d3 d2 d1 d0 c6om2 c6om1 c6om0 c5om2 c5om1 c5om0 101 100 d7 d6 d5 d4 d3 d2 d1 d0 c8om2 c8m1 c8om0 c7om2 c7om1 c7om0 111 110 cxom(2..0) serial output from 000 channel 1 001 channel 2 010 channel 3 011 channel 4 100 channel 5 101 channel 6 110 channel 7 111 channel 8 d7 d6 d5 d4 d3 d2 d1 d0 cfa9 cfa8 00 d7 d6 d5 d4 d3 d2 d1 d0 cfa7 cfa6 cfa5 cfa4 cfa3 cfa2 cfa1 cfa0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c1b23 c1b22 c1b21 c1b20 c1b19 c1b18 c1b17 c1b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c1b15 c1b14 c1b13 c1b12 c1b11 c1b10 c1b9 c1b8 00000000
sta308a 36/45 6.16.5coefficient b1data register bits 7..0 6.16.6coefficient b2 data register bits 23..16 6.16.7coefficient b2 data register bits 15..8 6.16.8coefficient b2 data register bits 7..0 6.16.9coefficient a1 data register bits 23..16 6.16.10coefficient a1 data register bits 15..8 6.16.11coefficient a1 data register bits 7..0 6.16.12coefficient a2 data register bits 23..16 6.16.13coefficient a2 data register bits 15..8 6.16.14coefficient a2 data register bits 7..0 d7 d6 d5 d4 d3 d2 d1 d0 c1b7 c1b6 c1b5 c1b4 c1b3 c1b2 c1b1 c1b0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c2b23 c2b22 c2b21 c2b20 c2b19 c2b18 c2b17 c2b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c2b15 c2b14 c2b13 c2b12 c2b11 c2b10 c2b9 c2b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c2b7 c2b6 c2b5 c2b4 c2b3 c2b2 c2b1 c2b0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c1b23 c1b22 c1b21 c1b20 c1b19 c1b18 c1b17 c1b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c3b15 c3b14 c3b13 c3b12 c3b11 c3b10 c3b9 c3b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c3b7 c3b6 c3b5 c3b4 c3b3 c3b2 c3b1 c3b0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c4b23 c4b22 c4b21 c4b20 c4b19 c4b18 c4b17 c4b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c4b15 c4b14 c4b13 c4b12 c4b11 c4b10 c4b9 c4b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c4b7 c4b6 c4b5 c4b4 c4b3 c4b2 c4b1 c4b0 00000000
37/45 sta308a 6.16.15coefficient b0 data register bits 23..16 6.16.16coefficient b0 data register bits 15..8 6.16.17coefficient b0 data register bits 7..0 6.16.18coefficient write control register coefficients for eq and bass management are handled internally in the sta308a via ram. access to this ram is available to the user via an i2c register interface. a collection of i2c registers are dedicated to this function. one contains a coefficient base address, five sets of three store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the write of the coefficient(s) to ram. the following are instructions for reading and writing coefficients. 6.17 reading a coefficient from ram write top 2-bits of address to i 2 c register 3bh write bottom 8-bits of address to i 2 c register 3ch read top 8-bits of coefficient in i 2 c address 3dh read middle 8-bits of coefficient in i 2 c address 3eh read bottom 8-bits of coefficient in i 2 c address 3fh 6.18 reading a set of coefficients from ram write top 2-bits of address to i 2 c register 3bh write bottom 8-bits of address to i 2 c register 3ch read top 8-bits of coefficient in i 2 c address 3dh read middle 8-bits of coefficient in i 2 c address 3eh read bottom 8-bits of coefficient in i 2 c address 3fh read top 8-bits of coefficient b2 in i 2 c address 40h read middle 8-bits of coefficient b2 in i 2 c address 41h read bottom 8-bits of coefficient b2 in i 2 c address 42h read top 8-bits of coefficient a1 in i 2 c address 43h read middle 8-bits of coefficient a1 in i 2 c address 44h read bottom 8-bits of coefficient a1 in i 2 c address 45h read top 8-bits of coefficient a2 in i 2 c address 46h read middle 8-bits of coefficient a2 in i 2 c address 47h d7 d6 d5 d4 d3 d2 d1 d0 c5b23 c5b22 c5b21 c5b20 c5b19 c5b18 c5b17 c5b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c5b15 c5b14 c5b13 c5b12 c5b11 c5b10 c5b9 c5b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c5b7 c5b6 c5b5 c5b4 c5b3 c5b2 c5b1 c5b0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 wa w1 00
sta308a 38/45 read bottom 8-bits of coefficient a2 in i 2 c address 48h read top 8-bits of coefficient b0 in i 2 c address 49h read middle 8-bits of coefficient b0 in i 2 c address 4ah read bottom 8-bits of coefficient b0 in i 2 c address 4bh 6.19 writing a single coefficient to ram write top 2-bits of address to i 2 c register 3bh write bottom 8-bits of address to i 2 c register 3ch write top 8-bits of coefficient in i 2 c address 3dh write middle 8-bits of coefficient in i 2 c address 3eh write bottom 8-bits of coefficient in i 2 c address 3fh write 1 to w1 bit in i 2 c address 4ch 6.20 writing a set of coefficients to ram write top 2-bits of starting address to i 2 c register 3bh write bottom 8-bits of starting address to i 2 c register 3ch write top 8-bits of coefficient b1 in i 2 c address 3dh write middle 8-bits of coefficient b1 in i 2 c address 3eh write bottom 8-bits of coefficient b1 in i 2 c address 3fh write top 8-bits of coefficient b2 in i 2 c address 40h write middle 8-bits of coefficient b2 in i 2 c address 41h write bottom 8-bits of coefficient b2 in i 2 c address 42h write top 8-bits of coefficient a1 in i 2 c address 43h write middle 8-bits of coefficient a1 in i 2 c address 44h write bottom 8-bits of coefficient a1 in i 2 c address 45h write top 8-bits of coefficient a2 in i 2 c address 46h write middle 8-bits of coefficient a2 in i 2 c address 47h write bottom 8-bits of coefficient a2 in i 2 c address 48h write top 8-bits of coefficient b0 in i 2 c address 49h write middle 8-bits of coefficient b0 in i 2 c address 4ah write bottom 8-bits of coefficient b0 in i 2 c address 4bh write 1 to wa bit in i 2 c address 4ch the mechanism for writing a set of coefficients to ram provides a method of updating the five coefficients cor- responding to a given biquad (filter) simultaneously to avoid possible unpleasant acoustic side-effects. when using this technique, the 10-bit address would specify the address of the biquad b1 coefficient (e.g. 0, 5, 10, 15, ?, 100, ? 395 decimal), and the sta308a will generate the ram addresses as offsets from this base value to write the complete set of coefficient data.
39/45 sta308a 7 equalization and mixing: figure 8. 7.1 post-scale the sta308a provides one additional multiplication after the last interpolation stage and before the distortion compensation on each channel. this is a 24-bit signed fractional multiply. the scale factor for this multiply is loaded into ram using the same i2c registers as the biquad coefficients and the bass-management. this post-scale factor can be used in conjunction with an adc equipped micro-controller to perform power-sup- ply error correction. all channels can use the channel 1 by setting the post-scale link bit. channel 1 channel 2 channel 3 channel 4 channel 5 channel 6 channel 7 channel 8 cxmix1 cxmix2 cxmix3 cxmix4 cxmix5 cxmix6 cxmix7 cxmix8 channel x
sta308a 40/45 table 38. ram block for biquads, mixing, and bass management index (decimal) index (hex) coefficient default 0 00h channel 1 ? biquad 1 c1h10(b1/2) 000000h 1 01h c1h11(b2) 000000h 2 02h c1h12(a1/2) 000000h 3 03h c1h13(a2) 000000h 4 04h c1h14(b0/2) 400000h 5 05h channel 1 ? biquad 2 c1h20 000000h ??? ? ? 49 31h channel 1 ? biquad 10 c1ha4 400000h 50 32h channel 2 ? biquad 1 c2h10 000000h 51 33h c2h11 000000h ??? ? ? 99 63h channel 2 ? biquad 10 c2ha4 400000h 100 64h channel 3 ? biquad 1 c3h10 000000h ??? ? ? 399 18fh channel 8 ? biquad 10 c8ha4 400000h 400 190h channel 1 ? pre-scale c1pres 7fffffh 401 191h channel 2 ? pre-scale c2pres 7fffffh 402 192h channel 3 ? pre-scale c3pres 7fffffh ??? ? ? 407 197h channel 8 ? pre-scale c8pres 7fffffh 408 198h channel 1 ? post-scale c1psts 7fffffh 409 199h channel 2 ? post-scale c2psts 7fffffh ??? ? ? 415 19fh channel 8 ? post-scale c8psts 7fffffh 416 1a0h channel 1 ? mix#1 1 c1mx11 7fffffh 417 1a1h channel 1 ? mix#1 2 c1mx12 000000h ??? ? ? 423 1a7h channel 1 ? mix#1 8 c1mx18 000000h 424 1a8h channel 2 ? mix#1 1 c2mx11 000000h 425 1a9h channel 2 ? mix#1 2 c2mx12 7fffffh ??? ? ? 463 1cfh channel 8 ? mix#1 8 c8mx18 7fffffh 464 1d0h channel 1 ? mix#2 1 c1mx21 7fffffh 465 1d1h channel 1 ? mix#2 2 c1mx22 000000h ??? ? ? 471 1d7h channel 1 ? mix#2 8 c1mx28 000000h 472 1d8h channel 2 ? mix#2 1 c2mx21 000000h 473 1d9h channel 2 ? mix#2 2 c2mx22 7fffffh ??? ? ? 527 20fh channel 8 ? mix#2 8 c8mx28 7fffffh
41/45 sta308a 7.2 variable max power correction: mpcc bits determine the 16 msbs of the mpc compensation coefficient. this coefficient is used in place of the default coefficient when mpcv = 1 7.2.1 . 7.2.2 7.3 variable distortion compensation: dcc bits determine the 16 msbs of the distortion compensation coefficient. this coefficient is used in place of the default coefficient when dccv = 1 7.3.1 . 7.3.2 7.4 pscorrect: adc is used to input ripple data to sdi78. the left channel(7) is used internally. no audio data can therefore be used on these channels. though all channel mapping and mixing from other inputs to channels 7 and 8 inter- nally are still valid. 7.4.1 ripple correction value - rcv equivalent to negative maximum ripple peak as a percentage of vcc (mpr), scaled by the inverse of maximum ripple p-p as percentage of full-scale analog input to adc. represented as a 1.11 signed fractional number. 7.4.2 correction normalization value - cnv equivalent to 1/(1+mpr) expressed as a 0.12 unsigned fractional number. 7.4.3 d7 d6 d5 d4 d3 d2 d1 d0 mpcc15 mpcc14 mpcc13 mpcc12 mpcc11 mpcc10 mpcc9 mpcc8 00101101 d7 d6 d5 d4 d3 d2 d1 d0 mpcc7 mpcc6 mpcc5 mpcc4 mpcc3 mpcc2 mpcc1 mpcc0 11000000 d7 d6 d5 d4 d3 d2 d1 d0 dcc15 dcc14 dcc13 dcc12 dcc11 dcc10 dcc9 dcc8 11110011 d7 d6 d5 d4 d3 d2 d1 d0 dcc7 dcc6 dcc5 dcc4 dcc3 dcc2 dcc1 dcc0 00110011 d7 d6 d5 d4 d3 d2 d1 d0 rcv11 rcv10 rcv9 rcv8 rcv7 rcv6 rcv5 rcv4 0 0 000000
sta308a 42/45 7.4.4 7.4.5 7.5 qsurround5.1 control register: 7.5.1 qen: 1-qsurround5.1 automode enabled, if security enabled 7.5.2 qfour: 0-5.1 mode, 1-4.1 mode 7.5.3 qsfs : 0 ? 48khz input sample rate, 1 ? 44.1 qsurround requires the use of both mix#1 and mix#2 blocks for channels 1-6, it also ut ilizes bi quad #8 on all channels. inputs must be mapped to channel 1/left and channel 2/right. channel outputs are in standard ddx8001 configuration. xo crossover bits will determine internal crossover point. enabling ambmxe bit will place crossover filters on all channels. either a 4.1 or 5.1 output mode can be selected via the qfour bit. all automodes excluding de-emphasis are st ill available w hen qsurround is enabled. 7.5.4 qsound security enable: a 16-bit register is provided, an exact number that is contained in the "qsec enable list"(separate document) must be put into this register for the qsurround5.1 automode to be enabled. 7.5.5 7.5.6 d7 d6 d5 d4 d3 d2 d1 d0 rcv3 rcv2 rcv1 rcv0 cnv11 cnv10 cnv9 cnv8 0000 1 1 11 d7 d6 d5 d4 d3 d2 d1 d0 cnv7 cnv6 cnv5 cnv4 cnv3 cnv2 cnv1 cnv0 11111111 d7 d6 d5 d4 d3 d2 d1 d0 qsfs qfour qen 000 bit r/w rst name description 0 r/w 0 qen 0 ? qsurround5.1 automode disabled 1 ? qsurround5.1 automode enabled bit r/w rst name description 1 r/w 0 qfour 0 ? 5.1 qsurround output mode 1 ? 4.1 qsurround output mode(no center) bit r/w rst name description 2 r/w 0 qsfs 0 ? 48/96/192khz input sample frequency 1 ? 44.1/88.2/176.4khz input sample frequency d7 d6 d5 d4 d3 d2 d1 d0 qsec15 qsec14 qsec13 qsec12 qsec11 qsec10 qsec9 qsec8 d7 d6 d5 d4 d3 d2 d1 d0 qsec7 qsec6 qsec5 qsec4 qsec3 qsec2 qsec1 qsec0
43/45 sta308a figure 9. tqfp44 (10 x 10 x 1.4mm) mechanical data & package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.30 0.37 0.45 0.012 0.015 0.018 c 0.09 0.20 0.004 0.008 d 11.80 12.00 12.20 0.464 0.472 0.480 d1 9.80 10.00 10.20 0.386 0.394 0.401 d3 8.00 0.315 e 11.80 12.00 12.20 0.464 0.472 0.480 e1 9.80 10.00 10.20 0.386 0.394 0.401 e3 8.00 0.315 e 0.80 0.031 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 k 0?(min.), 3.5?(typ.), 7?(max.) tqfp44 (10 x 10 x 1.4mm) a a2 a1 b seating plane c 11 12 22 23 33 34 44 e1 e d1 d e 1 k b tqfp4410 l 0.10mm .004 0076922 d
sta308a 44/45 table 39. revision history date revision description of changes may 2004 1 first issue
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