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description the A8510 is a multi-output white led driver for lcd backlighting. it integrates a current-mode boost converter with internal power switch and 8 current sinks. the boost converter can drive up to 96 leds with 12 leds at 40 ma per string. the led sinks can also be paralleled together to achieve even higher led currents, up to 320 ma. the A8510 can operate from a single power supply, from 5 to 40 v. if required, the A8510 can drive an external p-fet to disconnect the input supply from the system in the event of a fault. the A8510 provides protection against output short and overvoltage, open or shorted diode, open or shorted led pin, and overtemperature. a dual level cycle-by-cycle current limit function provides soft start and protects the internal current switch against high current overloads. the A8510 has a synchronization pin that allows pwm switching frequencies to be synchronized in the range of 580 khz to 2.3 mhz. the device package is a 26-contact, 4 mm 4 mm, 0.75 mm nominal overall height qfn, with exposed pad for enhanced thermal dissipation. it is lead (pb) free, with 100% matte tin leadframe plating. A8510-ds, rev. 2 features and benefits ? integrated 2 mhz capable boost converter with 60 v dmos switch with ovp protection ? sync function to synchronize boost converter switching frequencies up to 2.3 mhz ? led current up to 40 ma per led channel into 8 channels ? drives up to 12 series leds in 8 parallel strings (v f = 3.5 v, i f = 40 ma), v in = 8 v, switching frequency of 1 mhz ? single en/pwm pin interface for pwm dimming and enable functions ? apwm pin for fine-tuning color adjustment and/or maximizing contrast ratio ? integrated driver for optional external pmos input disconnect switch ? typical led accuracy of 0.7% and 0.8% for led-to-led matching ? internal bias supply for single-supply operation from 5 to 40 v ? extensive protection features wide input voltage range, high efficiency fault tolerant led driver typical application diagram A8510 package: 26-pin qfn (suffix ec) applications ? industrial lcd displays ? backlighting lcd displays ? infotainment displays figure 1. typical application circuit showing vin to gnd short protection using p-mosfet sensing approximate scale 1:1 vgate sw sw q1 l1 d1 c vdd ovp v out r ovp c out r sc r adj vsense vin vdd en/pwm apwm iset fset/sync agnd pgnd pgnd comp c p r z c z led8 led1 led2 led3 led4 led5 led6 led7 fault pad A8510 120 v c 22 h 169 k 0.056 590 100 k r iset 8.25 k r fset 25.5 k 4.7 f 50 v c in 4.7 f/ 50 v 0.1 f 0.47 f 120 pf v in 2 a / 60 v
wide input voltage range, high efficiency fault tolerant led driver A8510 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com absolute maximum ratings* characteristic symbol notes rating unit ledx pin ?0.3 to 55 v ovp pin ?0.3 to 60 v vin, vsense, vgate pins v sense and v gate should not exceed v in by more than 0.4 v. ?0.3 to 40 v sw pin continuous ?0.6 to 62 v t < 50 ns ?1.0 v f a u l t pin ?0.3 to 40 v iset, fset/sync, apwm, and comp pins ?0.3 to 5.5 v all other pins ?0.3 to 7 v operating ambient temperature t a range g ?40 to 105 oc maximum junction temperature t j (max) 150 oc storage temperature t stg ?55 to 150 oc *stresses beyond those listed in this table may cause permanent damage to the device. the absolute maximum ratings are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the elec trical characteristics table is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reli ability. selection guide part number packing A8510gectr-t 7000 pieces per 13-in. reel thermal characteristics may require derating at maximum conditions characteristic symbol test conditions* value unit package thermal resistance r ja on 2-layer, 3 in. 3 in. pcb 48.5 oc/w *additional thermal information available on the allegro website
wide input voltage range, high efficiency fault tolerant led driver A8510 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com functional block diagram vdd regulator uvlo internal soft start enable pwm thermal shutdown open/short led detect iset fault led driver 1.235 v ref driver circuit internal v cc internal v cc v ref internal v cc v ref v ref i ss i ss i adj goff 100 k agnd current sense input current sense amplifier pmos driver diode open sense ovp sense oscillator sw vin fset/sync comp vsense vgate en/pwm apwm pgnd pgnd agnd iset ovp led2 led1 led4 led5 led6 led7 led8 led3 fault agnd pgnd + ? + ? + ? + ? + ? sw
wide input voltage range, high efficiency fault tolerant led driver A8510 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com pin-out diagram terminal list table number name function 1 vin input power to the A8510 as well as the positive input used for the current sense resistor. 2 f a u l t this pin is used to indicate a fault condition, it is an open drain type configuration that will be pulled low when a fault occurs; connect a 100 k resistor between this pin and the required logic level voltage. 3, 9 nc no connect. 4 comp output of the error amplifier and compensation node; connect a series r z c z network from this pin to gnd for control loop compensation. 5 apwm analog trimming option or dimming; applying a digital pwm signal to this pin adjusts the internal i set current. 6 en/pwm pwm dimming pin used to control the led intensity by using pulse width modulation, with the typical pwm dimming frequency is in the range of 200 hz to 1 khz; also used to enable the A8510. 7 fset/sync frequency/synchronization pin; connect a resistor r fset from this pin to gnd to set the switching frequency. this pin can also be used to synchronize two or more converters in the system; the maximum synchronization frequency is 2.3 mhz. 8 iset connect the r iset resistor between this pin and gnd to set the led 100% current level. 10 to 18 led8 to led1 connect the cathode of each led string to these pins. 19 vdd output of internal ldo; connect a 0.1 f decoupling capacitor between this pin and gnd. 20, 21 pgnd power ground for internal nmos device. 22 ovp this pin is used to sense an overvoltage condition; connect the r ovp resistor from v out to this pin to adjust the overvoltage protection (ovp) function. 23, 24 sw the drain of the internal nmos switch of the boost converter. 25 vgate gate driver pin for external p-mosfet disconnect switch. 26 vsense connect this pin to the negative sense side of the current sense resistor r sc ; the threshold voltage is measured as v in ? v sense . ?pad exposed pad of the package providing enhanced thermal dissipation; this pad must be connected to the ground plane(s) of the pcb with at least 8 thermal vias, directly in the pad. pad 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 26 25 24 23 22 vsense vgate sw sw ovp iset nc agnd led8 led7 led6 led5 pgnd pgnd vdd led1 led2 led3 led4 vin fault nc comp apwm en/pwm fset/sync
wide input voltage range, high efficiency fault tolerant led driver A8510 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics 1 valid at v in = 16 v, t a = 25c, indicates specifications guaranteed by design and characterization over the full operating temperature range with t a = t j = ?40c to 105c; unless otherwise noted characteristics symbol test conditions min. typ. 2 max. unit input voltage specifications operating input voltage range 3 v in 5 ? 40 v uvlo start threshold v uvlorise v in rising ? ? 4.35 v uvlo stop threshold v uvlofall v in falling ? ? 3.90 v uvlo hysteresis 4 v uvlohys ? 450 ? mv input currents input quiescent current i q en/pwm = v ih ; sw = 2 mhz, no load ? 5.5 ? ma input sleep supply current i qsleep v in = 16 v, en/pwm = sync = 0 v ? 2 10.0 a input logic levels (en/pwm, apwm) input logic level-low v il v in throughout operating input voltage range ? ? 400 mv input logic level-high v ih v in throughout operating input voltage range 1.5 ? ? v en/pwm pin pin pull-down resistor r en en/pwm = 5 v ? 100 ? k apwm pin pull-down resistor r apwm apwm = v ih ? 100 ? k apwm apwm frequency f apwm 20 ? 1000 khz error amplifier open loop voltage gain a vol ? 48 ? db transconductance g m i comp = 10 a ? 990 ? a/v source current i ea(src) v comp = 1.5 v ? ?350 ? a sink current i ea(sink) v comp = 1.5 v ? 350 ? a comp pin pull-down resistor r comp ? 2000 ? overvoltage protection overvoltage threshold v ovp(th) ovp connected to v out 7.7 8.1 8.5 v ovp sense current i ovph 188 199 210 a ovp leakage current i ovplkg r ovp = 40.2 k , v in = 16 v, en/pwm = v il ? 0.1 1 a secondary overvoltage protection v ovp(sec) ? 55 ? v boost switch switch on-resistance r sw i sw = 0.750 a, v in = 16 v ? 300 ? m switch leakage current i swlkg v sw = 16 v, en/pwm = v il ? 0.1 1 a switch current limit i sw(lim) 3.0 3.5 4.2 a secondary switch current limit 4 i sw(lim2) higher than i sw(lim) (max) for all conditions, device latches when detected ? 7.0 ? a soft start boost current limit i swss(lim) initial soft start current for boost switch ? 700 ? ma minimum switch on-time t swontime ? 85 ? ns minimum switch off-time t swofftime ? 47 ? ns continued on the next page?
wide input voltage range, high efficiency fault tolerant led driver A8510 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com oscillator frequency oscillator frequency f sw r fset = 10 k 1.8 2 2.2 mhz r fset = 20 k ? 1 ? mhz r fset = 35.6 k ? 580 ? khz fset/sync pin voltage v fset r fset = 10 k ? 1.00 ? v fset frequency range f fset 580 ? 2500 khz synchronization synchronized pwm frequency f swsync 580 ? 2300 khz synchronization input minimum off-time t pwsyncoff 150 ?? ns synchronization input minimum on-time t pwsyncon 150 ?? ns sync input logic voltage v sync(h) fset/sync pin, high level ?? 0.4 v v sync(l) fset/sync pin, low level 2.0 ?? v led current sinks ledx accuracy err led i set = 120 a ?? 3% ledx matching ledx i set = 120 a ?? 3% ledx regulation voltage v led v led1 through v led8 all equal, i set = 120 a ? 680 ? mv i set to i ledx current gain a iset i set = 120 a 317 327 337 a/a iset pin voltage v iset ? 1.003 ? v allowable iset current i set 40 ? 120 a v led short detect v ledsc while led sinks are in regulation, sensed from ledx pin to gnd 4.6 ?? v soft start ledx current i ledss current through each enabled ledx pin during soft start, i set = 120 a ? 1.06 ? ma maximum pwm dimming until off-time 3 t pwml measured while en/pwm = low, during dimming control and internal references are powered-on (exceeding t pwml results in shutdown) ? 32750 ? f sw cycles minimum en/pwm on-time t pwmh first cycle when powering-up device ? 0.75 2 s en/pwm high to led-on delay t dpwm(on) time between en/pwm enable and ledx current reaching 90% of maximum ? 0.5 1 s en/pwm low to led-off delay t dpwm(off) time between en/pwm enable going low and ledx current reaching 10% of maximum ?? 500 ns vgate pin vgate pin sink current i gsink v gs = v in ?? 104 ? a vgate pin fault shutdown t gfault ?? 3 s vgate pin voltage v gs gate to source voltage measured when gate is on ? ?6.7 ? v electrical characteristics 1 (continued) valid at v in = 16 v, t a = 25c, indicates specifications guaranteed by design and characterization over the full operating temperature range with t a = t j = ?40c to 105c; unless otherwise noted characteristics symbol test conditions min. typ. 2 max. unit continued on the next page?
wide input voltage range, high efficiency fault tolerant led driver A8510 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com vsense pin vsense pin sink current i adj 18.8 20.3 21.8 a vsense trip point v sensetrip measured between vin and vsense, r adj = 0 ? 180 ? mv f a u l t pin f a u l t pin pull-down voltage v fault i fault = 1 ma (400 ) ?? 0.5 v f a u l t pin leakage current i faultlkg v fault = 5 v ?? 1 a thermal protection (tsd) thermal shutdown threshold 4 t sd temperature rising ? 165 ? oc thermal shutdown hysteresis 4 t sdhys ? 20 ? oc 1 for input and output current specifications, negative current is defined as coming out of the node or pin (sourcing); positive current is defined as going into the node or pin (sinking). 2 typical specifications are at t a = 25oc. 3 minimum v in = 5 v is only required at startup. after startup is completed, the ic is able to function down to v in = 4 v. 4 ensured by design and characterization, not production tested. electrical characteristics 1 (continued) valid at v in = 16 v, t a = 25c, indicates specifications guaranteed by design and characterization over the full operating temperature range with t a = t j = ?40c to 105c; unless otherwise noted characteristics symbol test conditions min. typ. 2 max. unit
wide input voltage range, high efficiency fault tolerant led driver A8510 8 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com typical characteristic performance -50-40-30-20-10 102030405060708090100110 0 -50-40-30-20-10 102030405060708090100110 0 -50-40-30-20-10 102030405060708090100110 0 -50-40-30-20-10 102030405060708090100110 0 -50-40-30-20-10 102030405060708090100110 0 -50-40-30-20-10 102030405060708090100110 0 7.7 7.6 7.8 7.9 8.0 8.1 8.2 8.3 8.4 v ovp(th) (v) 190 192 194 196 198 200 202 204 206 208 210 i ovph ( a) 3.60 3.61 3.62 3.63 3.64 3.65 3.66 3.67 3.68 3.69 3.70 1.80 1.85 1.90 1.95 2.00 2.05 2.10 2.15 2.20 f sw (mhz) switching frequency ovp pin sense current ovp pin overvoltage threshold 4.00 4.05 4.10 4.15 4.20 4.25 4.30 4.35 4.40 v uvlorise (v) v uvlofall (v) 0 1 2 3 4 5 i qsleep ( a) vin input sleep mode current versus ambient temperature vin uvlo rising threshold voltage vin uvlo falling threshold voltage versus ambient temperature versus ambient temperature versus ambient temperature versus ambient temperature versus ambient temperature temperature (c) temperature (c) temperature (c) temperature (c) temperature (c) temperature (c)
wide input voltage range, high efficiency fault tolerant led driver A8510 9 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com -50-40-30-20-10 102030405060708090100110 0 -50-40-30-20-10 102030405060708090100110 0 -50-40-30-20-10 102030405060708090100110 0 -50-40-30-20-10 102030405060708090100110 0 -50-40-30-20-10 102030405060708090100110 0 -50-40-30-20-10 102030405060708090100110 0 20.0 20.1 20.2 20.3 20.4 20.5 20.6 20.7 20.8 i adj ( a) vsense pin sink current -6.9 -6.8 -6.7 -6.6 -6.5 -6.4 -6.3 v gs (v) input disconnect switch voltage gate to source 330 329 328 327 326 325 324 323 322 321 320 a iset temperature (c) temperature (c) temperature (c) temperature (c) iset to led current gain versus ambient temperature versus ambient temperature versus ambient temperature ledx current versus ambient temperature i set = 120 a led current, i ledx (ma) 40.0 39.8 39.6 39.4 39.2 39.0 38.8 38.6 38.4 38.2 38.0 10.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 10.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 ledx (%) led to led matching accuracy temperature (c) temperature (c) versus ambient temperature led set point accuracy versus ambient temperature ledx accuracy, err led (%) 92 90 88 86 84 92 80 e ? ciency, (%) input voltage, v in (v) e ? ciency for 10 series leds per channel i led = 40 ma, led v f 3.2 v 7 9 11 13 15 17 19 21 f sw 800 khz 1 mhz 95 90 85 75 70 e ? ciency, (%) input voltage, v in (v) e ? ciency for 12 series leds per channel i led = 40 ma, led v f 3.2 v 7 9 11 13 15 17 19 21 f sw 800 khz 1 mhz f s w 800 khz 1 mh z
wide input voltage range, high efficiency fault tolerant led driver A8510 10 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com the A8510 incorporates a current-mode boost controller with internal dmos switch, and eight led current sinks. it can be used to drive eight led strings of up to 12 white leds in series, with current up to 40 ma per string. for optimal efficiency, the output of the boost stage is adaptively adjusted to the mini- mum voltage required to power all of the led strings. this is expressed by the following equation: v out = max ( v led1 ,..., v led8 ) + v reg (1) where v ledx is the voltage drop across led strings 1 through 8, and v reg is the regulation voltage of the led current sinks (typi- cally 0.68 v at the maximum led current). enabling the ic the ic turns on when a logic high signal is applied on the en/pwm pin with a minimum duration of t pwmh for the first clock cycle, and the input voltage present on the vin pin is greater than the 4.35 v necessary to clear the uvlo (v uvlorise ) threshold. the power-up sequence is shown in figure 2. before the leds are enabled, the A8510 driver goes through a system check to determine if there are any possible fault conditions that might prevent the system from functioning correctly. also, if the fset/sync pin is pulled low, the ic will not power-up. more information on the fset/sync pin can be found below, in the synchronization section of this document. powering up: led pin short-to-gnd check the vin pin has a uvlo function that prevents the A8510 from powering-up until the uvlo threshold is reached. after the vin pin goes above uvlo, and a high signal is present on the en/ pwm pin, the ic proceeds to power-up. as shown in figure 3, at this point the A8510 enables the disconnect switch and checks if any led pins are shorted to gnd and/or are not used. the led detect phase starts when the vgate voltage of the disconnect switch is equal to v in ? 4.5 v. after the voltage threshold on the ledx pins exceeds 120 mv, a timer of 3000 to 4000 clock cycles is used to determine the status of the pins. thus, the led detection duration varies with the switching frequency, as shown in the following table: switching frequency (khz) detection time (ms) 2000 1.5 to 2 1000 3 to 4 800 3.75 to 5 600 5 to 6.7 the led pin detection voltage thresholds are as follows: led pin voltage led pin status action <70 mv short-to-gnd power-up is halted 150 mv not used led removed from operation >325 mv led pin in use none functional description figure 2. power-up diagram at f sw = 2 mhz; shows vdd (ch1, 2 v/div.), fset/sync (ch2, 1 v/div.), iset (ch3, 1 v/div.), and en/pwm (ch4, 2 v/ div.) pins, t = 200 s/div. figure 3. power-up diagram; shows the relationship of an ledx pin with respect to the gate voltage of the disconnect switch (if used) during the led detect phase, as well as the duration of the led detect phase for a switching frequency of 800 khz; shows vgate (ch1, 5 v/div.), ledx (ch2, 500 mv/div.), iset (ch3, 1 v/div.), and en/pwm (ch4, 5 v/div.) pins, t = 1 ms/div. t vdd en/pwm fset/sync iset c1 c3 c4 c2 t vgate v gate = v in ? 4.5 v led detection period en/pwm ledx iset c1 c3 c4 c2
wide input voltage range, high efficiency fault tolerant led driver A8510 11 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com all unused pins should be connected with a 4.75 k resistor to gnd, as shown in figure 5. the unused pin, with the pull-down resistor, will be taken out of regulation at this point and will not contribute to the boost regulation loop. if an ledx pin is shorted to ground the A8510 will not proceed with soft start until the short is removed from the ledx pin. this prevents the A8510 from powering-up and putting an uncon- trolled amount of current through the leds. the various detect scenarios are presented in figures 4a and 4b. 4a. example with led8 pin not being used; f sw is 2 mhz, the detect voltage is about 150 mv; shows led1-7 (ch1, 500 mv/div.), led8 (ch2, 500 mv/div.), iset (ch3, 1 v/div.), and en/pwm (ch4, 5 v/div.) pins, t = 500 s/div. 4b. example with one led shorted to gnd. the ic will not proceed with power- up until the shorted led pin is released, at which point the led is checked to see if it is being used; shows led1 (ch1, 500 mv/div.), led2 (ch2, 500 mv/div.), iset (ch3, 1 v/div.), and en/pwm (ch4, 5 v/div.) pins, t = 1 ms/div. . figure 5. channel select setup: (left) channel led8 not used, (right) using all channels. gnd 4.75 k A8510 led1 led2 led3 led4 led5 led6 led7 led8 A8510 led1 led2 led3 led4 led5 led6 led7 led8 gnd t pin shorted short removed en/pwm led2 led1 iset c1 c3 c4 c2 t led detection period en/pwm led8 led1-7 iset c1 c3 c4 c2
wide input voltage range, high efficiency fault tolerant led driver A8510 12 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 f sw (mhz) resistance for r set (k ) 10.0 30.0 20.0 12.5 32.5 22.5 17.5 15.0 25.0 35.0 soft start function during soft start the ledx pins are set to sink (i ledss ) and the boost switch current is reduced to the i swss(lim) level to limit the inrush current generated by charging the output capacitors. when the converter senses that there is enough voltage on the ledx pins, the converter proceeds to increase the led current to the preset regulation current and the boost switch current limit is switched to the i sw(lim) level to allow the A8510 to deliver the necessary output power to the leds. this is shown in figure 7. frequency selection the switching frequency on the boost regulator is set by the resistor connected to the fset/sync pin, and the switching frequency can be can be anywhere from 580 khz to 2.3 mhz. figure 6 shows the typical switching frequencies for given resis- tor values. if during operation a fault occurs that will increase the switch- ing frequency, the fset/sync pin is clamped to a maximum switching frequency of no more than 3.5 mhz. synchronization the A8510 can also be synchronized using an external clock on the fset/sync pin. figure 8 shows the correspondence of a sync signal and the sw pin, and figure 9 shows the result when a sync signal is detected: the led current does not show any variation while the frequency synchronization occurs. at power- up if the fset/sync pin is held low, the ic will not power-up. only when the fset/sync pin is tri-stated to allow for the pin to rise, to about 1 v, or when a sync clock is detected, will the A8510 try to power-up. figure 7. startup diagram showing the input current, output voltage, and output current, f sw = 800 khz; shows i out (ch1, 500 ma/div.), i in (ch2, 1 a/ div.), v out (ch3, 20 v/div.), and en/pwm (ch4, 5 v/div.), t = 1 ms/div. figure 6. typical switching frequency versus value of r fset resistor. figure 9. transition of the sw waveform when the sync pulse is detected. the A8510 switching at 800 khz, applied sync pulse at 1.5 mhz; shows v out (ch1, 20 v/div.), i out (ch2, 500 ma/div.), fset/ sync (ch3, 2 v/div.), and sw node (ch4, 20 v/div.), t = 2 s/div. t inrush current caused by enabling the disconnect switch (when used) operation during i swss(lim) normal operation i sw(lim) en/pwm i in i out v out c1 c3 c4 c2 t sw node fset/sync i led v out c1 c3 c4 c2 figure 8. diagram showing a synchronized fset/sync pin and switch node; shows v out (ch1, 20 v/div.), i led (ch2, 200 ma/div.), fset/sync (ch3, 2 v/div.), and sw node (ch4, 20 v/div.), t = 2 s/div. t sw node 800 khz operation 1.5 mhz operation fset/sync i out v out c1 c3 c4 c2
wide input voltage range, high efficiency fault tolerant led driver A8510 13 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com the basic requirement of the sync signal is 150 ns minimum on-time and 150 ns minimum off time, as indicated by the speci- fications for t pwsyncon and t pwsyncoff . figure 10 shows the timing for a synchronization clock into the A8510 at 800 khz. thus any pulse with a duty cycle of 12% to 88% at 800 khz can be used to synchronize the ic. the sync pulse duty cycle ranges for selected switching fre- quencies are: sync pulse frequency (khz) duty cycle range (%) 2200 33 to 66 2000 30 to 70 1000 15 to 85 800 12 to 88 600 9 to 91 if during operation a sync clock is lost, the ic will revert to the preset switching frequency that is set by the resistor r fset . dur- ing this period the ic will stop switching for a maximum period of about 7 s to allow the sync detection circuitry to switch over to the externally preset switching frequency. if the clock is held low for more than 7 s, the A8510 will shut down. in this shutdown mode the ic will stop switching, the input disconnect switch is open, and the leds will stop sinking current. to shutdown the ic into low power mode, the ic must be disabled by keeping the en/pwm pin low for a period of 32750 clock cycles. if the fset/sync pin is released at any time after 7 s, the A8510 will proceed to soft start. led current setting and led dimming the maximum led current can be up to 40 ma per channel, and is set through the iset pin. to set the i led current, connect a resistor, r iset , between this pin and gnd, according to the fol- lowing formula: r iset = (1.003 327) / i led (2) where i led is in ma and r iset is in . this sets the maximum current through the leds, referred to as the 100% current . stan- dard r iset values, at gain equals 327, are as follows: standard resistor value closest to r iset (k ) led current per led, i led (ma) 8.25 40 10.5 30 13.0 25 16.2 20 pwm dimming the led current can be reduced from the 100% current level by pwm dimming using the en/pwm pin. when the en/pwm pin is pulled high, the A8510 turns on and all enabled leds sink 100% current. when en/pwm is pulled low, the boost converter and led sinks are turned off. the compensation (comp) pin is floated, and critical internal circuits are kept active. the typical pwm dimming frequencies fall between 200 hz and 1 khz. fig- ures 12a to 12d provide examples of pwm switching behavior. another important feature of the A8510 is the pwm signal to led current delay. this delay is typically less than 500 ns, which allows greater accuracy at low pwm dimming duty cycles, as shown in figure 11. 150 ns t = 1.25 s 950 ns t pwsyncon t pwsyncoff 150 ns figure 10. sync pulse on and off time requirements, for an 800-khz clock. figure 11. percentage error of the led current versus pwm duty cycle (at 200 hz pwm frequency), for 500 ns delay. 10 8 6 4 2 0 err led (%) pwm duty cycle, d (%) 0.1 1 10 100 worst-case typical
wide input voltage range, high efficiency fault tolerant led driver A8510 14 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com figure 12a. typical pwm diagram showing v out , i led , and comp pin as well as the pwm signal. pwm dimming frequency is 200 hz at 50% duty cycle; shows v out (ch1, 10 v/div.), i led (ch2, 50 ma/div.), comp (ch3, 2 v/div.), en/pwm (ch4, 5 v/div.), t = 1 ms/div. figure 12b. typical pwm diagram showing v out , i led , and comp pin as well as the pwm signal. pwm dimming frequency is 200 hz at 1% duty cycle ; shows v out (ch1, 10 v/div.), i led (ch2, 50 ma/div.), comp (ch3, 2 v/div.), en/pwm (ch4, 5 v/div.), t = 2 ms/div. figure 12c. delay from rising edge of pwm signal to led current; shows en/pwm (ch1, 2 v/div.), and i led (ch2, 20 ma/div.), t = 200 ns/div. figure 12d. delay from falling edge of pwm signal to led current turn off; shows en/pwm (ch1, 2 v/div.), and i led (ch2, 50 ma/div.), t = 200 ns/div. t i led en/pwm comp v out c1 c3 c4 c2 t i led en/pwm c1 c2 t i led en/pwm c1 c2 t i led en/pwm comp v out c1 c3 c4 c2
wide input voltage range, high efficiency fault tolerant led driver A8510 15 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com apwm pin the apwm pin is used in conjunction with the iset pin. this is a digital signal pin that internally adjusts the iset current. the typical input signal frequency is between 20 khz and 1 mhz. the duty cycle of this signal is inversely proportional to the percent- age of current that is delivered to the leds (figure 14). as an example, a system that delivers a full led current of 40 ma per led would deliver 20 ma of current per led when an apwm signal is applied with a duty cycle of 50%. when this pin is not used it should be tied to gnd. to use this pin for a trim function, the user should set the maxi- mum output current to a value higher than the required current by at least 5%. the led iset current is then trimmed down to the figure 13. simplified block diagram of the apwm iset block. figure 16. diagram showing the transition of led current from 40 ma to 20 ma, when a 50% duty cycle signal is applied to the apwm pin; en/pwm = 1; shows en/pwm (ch1, 5 v/div.), apwm (ch2, 5 v/div.), and i led (ch3, 20 ma/div.), t = 1 ms/div. figure 17. diagram showing the transition of led current from 20 ma to 40 ma, when a 50% duty cycle signal is removed from the apwm pin. en/pwm = 1; shows en/pwm (ch1, 5 v/div.), apwm (ch2, 5 v/div.), and i led (ch3, 20 ma/div.), t = 1 ms/div. figure 14. led current versus pwm duty cycle; 200 khz apwm frequency. figure 15. percentage error of the led current versus apw m signals. apwm apwm iset current adjust iset current mirror led driver iset r iset en/pwm A8510 40 30 20 10 0 i led (ma) pwm duty cycle, d (%) 04060 20 80 100 5 v 200 khz 1.5 v 200 khz 1.5 v 50 khz 5 v 50 khz 25 20 15 10 5 0 pwm duty cycle, d (%) 04060 20 80 100 err led (%) t i led apwm en/pwm c1 c3 c2 t i led apwm en/pwm c1 c3 c2
wide input voltage range, high efficiency fault tolerant led driver A8510 16 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com appropriate value. in cases where the user-supplied apwm has significant duty cycle limitations, it might be preferable to set the maximum iset current to be 25% to 50% higher, thus allowing the apwm signal to have duty cycles that are between 50% and 75%. although the apwm dimming function has a wide frequency range, if this function is used strictly as an analog dimming function it is recommended to use frequency ranges between 50 and 500 khz for best accuracy. the frequency range must be considered only if the user is not using this function as a closed loop trim function. there is a few millisecond propagation delay between the apwm signal and i led current. this effect is shown in figures 16 through 18. analog dimming the A8510 can also be dimmed by using an external dac or another voltage source applied either directly to the ground side of the r iset resistor or through an external resistor to the iset pin (see figure 19). ? for a single resistor (upper panel of figure 19), the iset current is controlled by the following formula: i set = v iset ? v dac r iset ? v dac (3) where v iset is the iset pin voltage and v dac is the dac out- put voltage. when the dac voltage is equal to v iset , the internal reference, there is no current through r iset . when the dac voltage starts to decrease, the iset current starts to increase, thus increasing the led current. when the dac voltage is 0 v, the led current will be at its maximum. ? for a dual-resistor configuration (lower panel of figure 19), the iset current is controlled by the following formula: i set = ? v iset r iset v dac ? v iset r 1 (4) the advantage of this circuit is that the dac voltage can be higher or lower, thus adjusting the led current to a higher or lower value of the preset led current set by the r iset resistor: ? vdac = 1.003 v; the output is strictly controlled by r iset ? vdac > 1.003 v; the led current is reduced ? vdac < 1.003 v; the led current is increased figure 18. transition of output current level when a 50% duty cycle signal is applied to the apwm pin, in conjunction with a 50% duty cycle pwm dimming being applied to the en/pwm pin; shows en/pwm (ch1, 5 v/ div.), apwm (ch2, 5 v/div.), and i led (ch3, 20 ma/div.), t = 1 ms/div. t i out apwm en/pwm c1 c3 c2 figure 19. simplified diagrams of voltage control of i led : typical applications using a dac to control i led using a single resistor (upper), and dual resistors (lower). gnd dac vdac gnd A8510 iset gnd dac vdac gnd A8510 iset r iset r1 r iset
wide input voltage range, high efficiency fault tolerant led driver A8510 17 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com led short detect all of the ledx pins are capable of handling the maximum v out that the converter can deliver, thus providing protection from the led pin to v out in the event of a connector short. any ledx pin that has a voltage exceeding v ledsc will be removed from operation (see figure 20). this is to prevent the ic from dissipating too much power by having a large voltage pres- ent on the ledx pin. while the ic is being pwm-dimmed, the ic rechecks the dis- abled ledx pin every time the pwm signal goes high, to prevent false tripping of an ledx short event. this also allows some self- correction if an intermittent ledx pin short-to-v out is present. overvoltage protection the A8510 has overvoltage protection (ovp) and open schottky diode (d1) protection. the ovp protection has a default level of 8 v and can be increased up to 55 v by connecting r ovp between the ovp pin and v out . when the current into the ovp pin exceeds 199 a typical, the ovp comparator goes low and the boost stops switching. the following equation can be used to determine the resistance for setting the ovp level: r ovp = ( v outovp ? v ovp(th) ) / i ovph (4) where: v outovp is the target overvoltage level, r ovp is the value of the external resistor, in , v ovp(th) is the pin ovp trip point found in the electrical charac- teristics table, and i ovph is the current into the ovp pin. there are several possibilities for why an ovp condition would be encountered during operation, the two most common being: an open led string, and a disconnected output. examples of these are provided in figures 21 and 22. figure 21 illustrates when the output of the A8510 is discon- nected from load during normal operation. the output voltage instantly increases up to ovp voltage level and then the boost stops switching to prevent damage to the ic. if the output is drained off, eventually the boost might start switching for a short duration until the ovp threshold is hit again. figure 20. example of the disabling of an led string when the led pin voltage is increased above 4.6 v; shows v led (ch1, 5 v/div.), en/pwm (ch2, 5 v/div.), and i led (ch3, 50 ma/div.), t = 20 s/div. t i led v led en/pwm c1 c3 c2
wide input voltage range, high efficiency fault tolerant led driver A8510 18 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com figure 21. ovp protection in an output disconnect from load event; shows v out (ch1, 10 v/div.), sw node (ch2, 20 v/div.), en/pwm (ch3, 5 v/div.), and i led (ch4, 50 ma/div.), t = 2 ms/div. figure 23. ovp protection in an open schottky diode d1 event, while the ic is in normal operation; shows sw node (ch1, 50 v/div.), i out (ch2, 500 ma/div.), f a u l t (ch3, 5 v/div.), and en/pwm (ch4, 5 v/div.), t = 2 s/div. figure 22. ovp protection in an open led string event; shows v out (ch1, 10 v/div.), sw node (ch2, 20 v/div.), en/pwm (ch3, 5 v/div.), and i led (ch4, 200 ma/div.), t = 1 ms/div. figure 24. ovp protection when the ic is enabled during an open diode condition; shows en/pwm (ch1, 5 v/div.), sw node (ch2, 50 v/div.), v out (ch3, 10 v/div.), and i led (ch4, 200 ma/div.), t = 500 s/div. t v out en/pwm sw node output disconnect event detected i led c1 c3 c4 c2 t v out en/pwm sw node open diode condition detected i led c1 c3 c4 c2 t v out en/pwm sw node i led c1 c3 c4 c2 led string open condition detected figure 22 displays a typical ovp event caused by an open led string. after the ovp condition is detected, the boost stops switching, and the open led string is removed from operation. afterwards v out is allowed to fall, and eventually the boost will resume switching and the A8510 will resume normal operation. A8510 also has built-in secondary overvoltage protection to pro- tect the internal switch in the event of an open diode condition. open schottky diode (d1) detection is implemented by detecting overvoltage on the sw pins of the device. if voltage on the sw pins exceeds the device safe operating voltage rating, the A8510 disables and remains latched. to clear this fault, the ic must be shut down either by using the pwm signal or by going below the uvlo threshold on the vin pin. figure 23 illustrates this. as soon as the switch node voltage (sw) exceeds v ovp(sec) , the ic shuts down. due to small delays in the detection circuit, as well as there being no load present, the switch node voltage will rise above the trip point voltage. figure 24 illustrates when the A8510 is being enabled during an open diode condition. the ic goes through all of its initial led detection and then tries to enable the boost, at which point the open diode is detected. t en/pwm sw node open diode condition detected i out c1 c3 c4 c2 fault
wide input voltage range, high efficiency fault tolerant led driver A8510 19 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com boost switch overcurrent protection the boost switch is protected with cycle-by-cycle current limiting set at a minimum of 3.0 a. there is also a secondary cur- rent limit that is sensed on the boost switch. when detected this current limit immediately shuts down the A8510. the level of this current limit is set above the cycle-by-cycle current limit to pro- tect the switch from destructive currents when the boost inductor is shorted. various boost switch overcurrent conditions are shown in figures 25 through 27. input overcurrent protection and disconnect switch the primary function of the input disconnect switch is to protect the system and the device from catastrophic input currents during a fault condition. the external circuit implementing the discon- nect is shown in figure 28. if the input disconnect switch is not used, the vsense pin must be tied to vin and the vgate pin must be left open. figure 25. normal operation of the switch node (sw); inductor current (i l ) and output voltage (v out ) for 12 series leds in each of 8 strings configuration; shows i l (ch1, 500 ma/div.), sw node (ch2, 20 v/div.), v out (ch3, 20 v/div.), and en/pwm (ch4, 5 v/div.), t = 1 s/div. figure 26. cycle-by-cycle current limiting; inductor current (il), note reduction in output voltage as compared to normal operation with the same configuration (figure 25); shows il (ch1, 1 a/div.), sw node (ch2, 20 v/div.), vout (ch3, 10 v/div.), and en/pwm (ch4, 5 v/div.), t = 2 s/div. figure 27. secondary boost switch current limit; when this limit is hit, the A8510 immediately shuts down; shows en/pwm (ch1, 5 v/div.), f a u l t (ch2, 5 v/div.), sw node (ch3, 50 v/div.), and i l (ch4, 2 a/div.), t = 200 ns/div. t v out en/pwm sw node i l c1 c2 c3 c3 t v out en/pwm sw node i l c1 c3 c4 c2 t i l en/pwm sw node c1 c3 c4 c2 fault
wide input voltage range, high efficiency fault tolerant led driver A8510 20 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com when selecting the external pmos, check for the following parameters: ? drain-source breakdown voltage v (br)dss > ?40 v ? gate threshold voltage (make sure it is fully conducting at v gs = -4 v, and cut-off at ?1 v) ? r ds(on) : make sure the on-resistance is rated at v gs = -4.5 v or similar, not at -10 v; derate it for higher temperature if the input current level goes above the preset current limit threshold, the A8510 will shut down in less than 3 s regardless of user input (figure 29). this is a latched condition. the fault flag is also set to indicate a fault. this feature is meant to prevent catastrophic failure in the system due to a short of the inductor or output voltage to gnd. figure 28. typical circuit showing the implementation of the input disconnect feature. vgate r adj r sc vsense vin A8510 v in q1 to l1 figure 29. diagram showing input disconnect current limit wave forms during fault condition; shows f a u l t (ch1, 5 v/div.), vgate (ch2, 10 v/div.), i in (ch3, 2 a/div.), and en/pwm (ch4, 5 v/div.), t = 5 s/div. t vgate en/pwm i in c1 c3 c4 c2 fault A8510 shuts down
wide input voltage range, high efficiency fault tolerant led driver A8510 21 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com setting the current sense resistor the typical threshold for the current sense circuit is 180 mv, when r adj is 0 . this voltage can be trimmed by the r adj resistor. the typical trip point should be set at about 3 a, which coincides with the cycle-by-cycle current limit minimum thresh- old. a sample calculation is done below: given: 2.85 a of input current, and the calculated maximum value of the sense resistor, r sc = 0.063 . the r sc chosen is 0.056 , a standard value. also: r adj = ( v sensetrip ? v adj ) / i adj (5) the typical trip point voltage is calculated as: v adj = 2.85 a 0.056 = 0.160 v r adj = (0.180 ? 0.160 v) / (20.3 a) = 1.0 k input uvlo when v in and v sense rise above the uvlo enable hysteresis (v uvlorise + v uvlohys ), the A8510 is enabled. A8510 is disabled when v in falls below the v uvlofall threshold for more than 50 s. this lag is to avoid shutting down because of momentary glitches in the input power supply. vdd the vdd pin provides regulated bias supply for internal circuits. connect the capacitor c vdd with a value of 0.1 f or greater to this pin. shutdown if the en/pwm pin is pulled low for more than t pwml , the device enters shutdown mode and clears all internal fault regis- ters. as an example, at a 2-mhz clock frequency, the maximum pwm low period, while avoiding shutdown, is 16 ms. in shut down, the ic disables all current sources and waits until the en/pwm pin goes high to re-enable the ic and proceed with power-up. fault protection during operation the A8510 constantly monitors the state of the system to deter- mine if any fault conditions occur during normal operation. the response to a triggered fault condition is summarized in the fault mode table, on the next page. the possible fault conditions that the device can detect are: open led pin, led pin shorted to gnd, shorted inductor, v out short to gnd, sw pin shorted to gnd, iset pin shorted to gnd, and input disconnect switch source shorted to gnd. note the following: ? some of the protection features might not be active during startup, to prevent false triggering of fault conditions. ? some of these faults will not be protected if the input disconnect switch is not being used. an example of this is vout short to ground.
wide input voltage range, high efficiency fault tolerant led driver A8510 22 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com fault mode table fault name type active fault flag set description boost disconnect switch sink driver primary switch overcurrent protection (cycle-by-cycle current limit) auto-restart always no this fault condition is triggered by the cycle-by- cycle current limit, isw(lim). off for a single cycle on on secondary switch current limit latched always yes when the current through the boost switch exceeds secondary current sw limit (i sw(lim2) ) the device immediately shuts down the disconnect switch, led drivers, and boost. the fault flag is set. to re- enable the device, the en/pwm pin must be pulled low for 32750 clock cycles. off off off input disconnect current limit latched always yes the device is immediately shut off if the voltage across the input sense resistor is above the v sensetrip threshold. the fault flag is set. to re- enable the part the en/pwm pin must be pulled low for 32750 clock cycles. off off off secondary ovp latched always yes secondary overvoltage protection is used for open diode detection. when diode d1 opens, the sw pin voltage will increase until v ovp(sec) is reached. this fault latches the ic. the input disconnect switch is disabled as well as the led drivers, and the fault flag is set. to re-enable the part the en/pwm pin must be pulled low for 32750 clock cycles. off off off ledx pin short protection auto-restart startup no this fault prevents the device from starting-up if any of the ledx pins are shorted. the device stops soft-start from starting while any of the led pins are determined to be shorted. once the short is removed, soft-start is allowed to start. off on off ledx pin open auto-restart normal operation no when an ledx pin is open the device will determine which ledx pin is open by increasing the output voltage until ovp is reached. any led string not in regulation will be turned off. the device will then go back to normal operation by reducing the output voltage to the appropriate voltage level. on on off for open pins. on for all others. iset short protection auto-restart always no this fault occurs when the iset current goes above 150% of the maximum current. the boost will stop switching and the ic will disable the led sinks until the fault is removed. when the fault is removed the ic will try to regulate to the preset led current. off on off continued on the next page?
wide input voltage range, high efficiency fault tolerant led driver A8510 23 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com fset/sync short protection auto-restart always yes fault occurs when the fset/sync current goes above 150% of maximum current. the boost will stop switching, the disconnect switch will turn off and the ic will disable the ledx sinks until the fault is removed. when the fault is removed the ic will try to restart with soft-start. off off off overvoltage protection auto-restart always no fault occurs when ovp pin exceeds v ovp(th) threshold. the A8510 will immediately stop switching to try to reduce the output voltage. if the output voltage decreases then the A8510 will restart switching to regulate the output voltage. stop during ovp event. on on led short protection auto-restart always no fault occurs when the ledx pin voltage exceeds 5.1 v. when the led short protection is detected the led string above the threshold will be removed from operation. on on off for shorted pins. on for all others. overtemperature protection auto-restart always no fault occurs when the die temperature exceeds the overtemperature threshold, typically 165c. off off off vin uvlo auto-restart always no fault occurs when v in drops below v uvlo , typically 3.90 v. this fault resets all latched faults. off off off fault mode table (continued) fault name type active fault flag set description boost disconnect switch sink driver
wide input voltage range, high efficiency fault tolerant led driver A8510 24 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com applications information design example for boost configuration this section provides a method for selecting component values when designing an application using the A8510. an example schematic is provided in figure 30. assumptions: for the purposes of this example, the following are given as the application requirements: ? v bat : 10 to 14 v ? quantity of led channels, # channels : 8 ? quantity of series leds per channel, # seriesleds : 12 ? led current per channel, i led : 40 ma ? v f at 40 ma: 3.2 v ? f sw : 800 khz ? t a (max): 65c ? pwm dimming frequency: 200 hz, 1% duty cycle procedure: the procedure consists of selecting the appropriate configuration and then the individual component values, in an ordered sequence. it should be noted that in many calculations the minimum and/or maximum specification values are used to guarantee proper system operation. step 1 connect leds to pins led1 through led8. step 2 determining the led current setting resistor r iset : r iset = 1.003 327 / i led (6) = 327.981 / 40 ma = 8.20 k choose a 8.25 k resistor. step 3 determining the ovp resistor. the ovp resistor is connected between the ovp pin and the output voltage of the converter. step 3a the first step is determining the maximum voltage based on the led requirements. then this value and the regula- tion voltage (v led ) should be added together, as well as another 750 mv to take noise and output ripple into consideration. the regulation voltage, v led , of the A8510 is 680 mv. v out(ovp) = # seriesleds v f + v led + 2 (7) = 12 3.2 v+ 0.680 v + 2 v = 41.08 v then the ovp resistor is: r ovp = ( v out(ovp) ? v ovp(th) ) / i ovph (8) = (41.08 v ? 8.1 v) / 199 a = 165.73 k where both i ovph and v ovp(th) are taken from the electrical characteristics table. chose a value of resistor that is higher value than the calculated r ovp . in this case a value of 169 k was selected. below is the actual value of the minimum ovp trip level with the selected resistor: v out(ovp) = 169 k 199 a + 8.1 v = 41.7 v step 3b at this point a quick check must be done to see if the conversion ratio is acceptable for the selected frequency. d maxofboost = 1 ? t swofftime f sw (9) = 1 ? 1.5 47 ns 800 khz = 94.36% where minimum off time (t swofftime ) is found in the electrical characteristics table. the theoretical maximum v out is then calculated as: v outthe (max) v d =? 1 ? d maxofboost v in (min) 0.4 177 v == ? 1 ? 0.9436 10 v (10) where v d is the diode forward voltage. the theoretical maximum v out value must be greater than the value v out(ovp) . if this is not the case, the switching frequency of the boost converter must be reduced to meet the maximum duty cycle requirements. step 4 selecting the inductor. the inductor must be chosen such that it can handle the necessary input current. in most applica- tions, due to stringent emi requirements, the system must operate in continuous conduction mode throughout the whole input volt- age range.
wide input voltage range, high efficiency fault tolerant led driver A8510 25 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com step 4a determining the duty cycle, calculated as follows: d (max) v d = + v in (min) v out(ovp) 76.3% == 41.7 v + 0.4 v 1 ? 1 ? 10 v (11) the voltage drop of the diode can be approximated to be about 0.4 v. step 4b determining the maximum and minimum input current to the system. the minimum input current will dictate the induc- tor value. the maximum current rating will dictate the current rating of the inductor. first, the maximum input current, given: i out = # channels i led 0.320 a == 8 0.040 a (12) then: i in (max) = v in (min) v out(ovp) i out h 1.483 a == 41.7 v 10 v 0.9 0.320 a (13) where is efficiency. next, calculate minimum input current, as follows: i in (min) = v in (max) v out(ovp) i out h 1.059 a == 41.7 v 14 v 0.9 0.320 a (14) a good approximation of efficiency, , can be taken from the efficiency curves located in the diode datasheet. a value of 90% is a good starting approximation. step 4c determining the inductor value. to ensure that the inductor operates in continuous conduction mode, the value of the inductor must be set such that the ? inductor ripple current is not greater than the average minimum input current. a first past assumes i ripple to be 30% of the maximum inductor current: i l = i in (max) 0.3 (15) = 1.48 a 0.3 = 0.444 a then: l = v in (min) d (max) f sw i l 21.4 h 0.444 a == 0.76 10 v 800 khz (16) step 4d double-check to make sure the ? current ripple is less than i in (min): i in (min) > 1 / 2 i l (17) 1.059 a > 0.222 a a good inductor value to use would be 22 h, l used . step 4e this step is used to verify that there is sufficient slope compensation for the inductor chosen. the slope compensation value is determined by the following formula: 2 10 6 slope compensation == f sw 4.5 1.8 a / s (18) next insert the inductor value used in the design: = v in (min) d (max) f sw l used i lused 22 h 0.434 a == 0.763 10 v 800 khz (19) calculate the minimum required slope: = (1 ? d (max)) (1 ? 0.763) f sw required slope (min) i lused 0.434 a 1 1 1 10 ? 6 110 ? 6 == 1.46 a/ s 800 khz (20) if the minimum required slope is larger than the calculated slope compensation, the inductor value must be increased. note: that the slope compensation value is in a/ s, and 1 10 ?6 is a constant multiplier. step 4f determining the inductor current rating. the inductor current rating must be greater than the i in (max) value plus the ripple current i l , or about 1.7 a, calculated as follows: i l (min) = i in (max) + 1 / 2 i lused (21) = 1.483 a + 0.217 a = 1.70 a
wide input voltage range, high efficiency fault tolerant led driver A8510 26 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com step 5 determining the resistor value for a particular switching frequency. use the r fset values shown in figure 6. for example, a 25.5 k resistor will result in an 800 khz switching frequency. step 6 choosing the proper switching diode. the switching diode must be chosen for three characteristics when it is used in led lighting circuitry. the most obvious two are: current rating of the diode and reverse voltage rating. the reverse voltage rating should be such that during operation condition, the voltage rating of the device is larger than the maxi- mum output voltage. in this case it is v out(ovp) . the peak current through the diode is calculated as: i dp = i in (max) + 1 / 2 i lused (22) = 1.483 a + 0.217 a = 1.70 a the third major component in deciding the switching diode is the reverse current, i r , characteristic of the diode. this characteristic is especially important when pwm dimming is implemented. during pwm off-time the boost converter is not switching. this results in a slow bleeding off of the output voltage, due to leakage currents. i r can be a large contributor, especially at high tempera- tures. on the diode that was selected in this design, the current varies between 1 and 100 a. step 7 choosing the output capacitors. the output capacitors must be chosen such that they can provide filtering for both the boost converter and for the pwm dimming function. the big- gest factors that contribute to the size of the output capacitor are pwm dimming frequency and pwm duty cycle. another major contributor is leakage current ( i lk ). this current is the combina- tion of the ovp leakage current as well as the reverse current of the switching diode. in this design the pwm dimming frequency is 200 hz and the minimum duty cycle is 1%. typically the volt- age variation on the output (v cout ) during pwm dimming must be less than 250 mv, so that no audible hum can be heard. the capacitance can be calculated as follows: c out = f pwm(dimming) 1 ? d (min) 1 ? 0.01 200 hz i lk 200 a 3.96 f == 0.250 v v cout (23) a capacitor larger than 3.96 f should be selected due to degra- dation of capacitance at high voltages on the capacitor. a ceramic 4.7 f 50 v capacitor is a good choice to fulfill this requirement. corresponding capacitors include: vendor value part number murata 4.7 f 50 v grm32er71h475ka88l murata 2.2 f 50 v grm31cr71h225ka88l the rms current through the capacitor is given by: i cout rms = 1 ? d (max) d (max) + ? i lused i out 0.320 a 0.583 a 12 == i in (max) 1 ? 0.763 0.763 + 0.434 a 1.48 a 12 (24) the output capacitor must have a current rating of at least 583 ma. the capacitors selected in this design have a combined rms current rating of 3 a. step 8 selecting input capacitor. the input capacitor must be selected such that it provides a good filtering of the input voltage waveform. a good rule of thumb is to set the input voltage ripple v in to be 1% of the minimum input voltage. the minimum input capacitor requirements are as follows: c in = f sw 0.434 a ? i lused 0.68 f 8 == ? v in 800 khz 0.1 v 8 (25) the rms current through the capacitor is given by: i in rms = (1 ? d (max)) i out ? i lused 0.11 a 12 = = i in (max) (1 ? 0.763) 0.320 a 0.434 a 1.48 a 12 (26) a good ceramic input capacitor with ratings of 2.2 f 50v or 4.7 f 50 v will suffice for this application.
wide input voltage range, high efficiency fault tolerant led driver A8510 27 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com figure 30. the schematic diagram showing calculated values from the design example above corresponding capacitors include: vendor value part number murata 4.7 f 50 v grm32er71h475ka88l murata 2.2 f 50 v grm31cr71h225ka88l step 9 choosing the input disconnect switch components. set the input disconnect current limit to 3 a by choosing a corre- sponding sense resistor. the calculated maximum value of the sense resistor is: r sc (max) = v sensetrip / 3.0 a (27) = 0.180 v / 3.0 a= 0.060 the r sc chosen is 0.056 , a standard value. the trip point voltage must be: v adj = 3.0 a 0.056 = 0.168 v r adj = ( v sensetrip ? v adj ) / i adj (28) = (0.180 v ? 0.168 v) / 20.3 a = 591 a value of 590 was chosen for this design. vgate sw sw q1 l1 d1 c vdd ovp v out r ovp c out r sc r adj vsense vin vdd en/pwm apwm iset fset/sync agnd pgnd pgnd comp c p r z c z led8 led1 12 leds each string led2 led3 led4 led5 led6 led7 fault pad A8510 120 v c 22 h 169 k 0.056 590 100 k r iset 8.25 k r fset 25.5 k 4.7 f 50 v c in 4.7 f/ 50 v 0.1 f 0.47 f 120 pf v in 2 a / 60 v
wide input voltage range, high efficiency fault tolerant led driver A8510 28 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com design example for sepic configuration this section provides a method for selecting component values when designing an application using the A8510 in sepic (sin- gle-ended primary-inductor converter) circuit. sepic topology has the advantage that it can generate a positive output voltage either higher or lower than the input voltage. the resulting design is diagrammed in figure 31. assumptions: for the purposes of this example, the following are given as the application requirements: ? v bat : 6 to 14 v ( v in (min): 5 v and v in (max): 16 v ) ? quantity of led channels, # channels : 8 ? quantity of series leds per channel, # seriesleds : 4 ? led current per channel, i led : 40 ma ? led v f at 60 ma: 3.3 v ? f sw : 800 khz ? t a (max): 65c ? pwm dimming frequency: 200 hz, 1% duty cycle procedure: the procedure consists of selecting the appropriate configuration and then the individual component values, in an ordered sequence. step 1 connecting leds to ledx pins. if only some of the led channels are needed, the unused ledx pins should be pulled to ground using a 1.5 k resistor. step 2 determining the led current setting resistor r iset : r iset = ( v iset a iset ) / i led (29) = (1.003 (v) 327) / 0.40 (a) = 8.20 k choose an 8.25 k 1% resistor. step 3 determining the ovp resistor. the ovp resistor is connected between the ovp pin and the output voltage of the converter. step 3a the first step is determining the maximum voltage based on the led requirements. the regulation voltage, v led , of the A8510 is 720 mv. a constant term, 2 v, is added to give margin to the design due to noise and output voltage ripple. v out(ovp) = # seriesleds v f + v led + 2 (v) (30) = 4 3.3 (v) + 0.680 (v) + 2 (v) = 15.9 v then the ovp resistor is: r ovp = ( v out(ovp) ? v ovp(th) ) / i ovph (31) = (15.9 (v) ? 8.1 (v)) / 0.199 (ma) = 39.196 k where both i ovph and v ovp(th) are taken from the electrical characteristics table. in this case a value of 39.2 k was selected. below is the actual value of the minimum ovp trip level with the selected resistor: v out(ovp) = 39.2 (k ) 0.199 (ma) + 8.1 (v) = 15.9 v step 3b at this point a quick check must be done to determine if the conversion ratio is acceptable for the selected frequency. d max = 1 ? t swofftime f sw (32) = 1 ? 1.5 47 (ns) 800 (khz) = 94.4% where the minimum off-time (t swofftime ) is found in the electri- cal characteristics table. the theoretical maximum v out is then calculated as: v out (max) = v d ? 1 ? d max d max v in (min) 0.4 (v) 77.9 v == ? 1 ? 0.94 0.94 5 (v) (33) where v d is the diode forward voltage. the theoretical maximum v out value must be greater than the value v out(ovp) . if this is not the case, it may be necessary to reduce the frequency to allow the boost to convert the volt- age ratios. step 4 selecting the inductor. the inductor must be chosen such that it can handle the necessary input current. in most applica-
wide input voltage range, high efficiency fault tolerant led driver A8510 29 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com tions, due to stringent emi requirements, the system must operate in continuous conduction mode throughout the whole input volt- age range. step 4a determining the duty cycle, calculated as follows: d (max) v d = + v d + v out(ovp) + v in (min) v out(ovp) 76.5% == 5 (v) + 15.9 (v) + 0.4 (v) + 0.4 (v) 15.9 (v) (34) step 4b determining the maximum and minimum input current to the system. the minimum input current will dictate the induc- tor value. the maximum current rating will dictate the current rating of the inductor. first, the maximum input current, given: i out = # channels i led 0.320 a == 8 40 (ma) (35) then: i in (max) = v in (min) v out(ovp) i out h 1.131 a == 15.9 (v) 5 (v) 0.90 0.32 (a) (36) where is efficiency. next, calculate minimum input current, as follows: i in (min) = v in (max) v out(ovp) i out h 0.353 a == 15.9 (v) 16 (v) 0.90 0.32 (a) (37) step 4c determining the inductor value. to ensure that the inductor operates in continuous conduction mode, the value of the inductor must be set such that the ? inductor ripple current is not greater than the average minimum input current. as a first pass assume i ripple to be 30% of the maximum inductor current: i l = i in (max) i ripple (38) = 1.131 0.30 = 0.339 a then: l = v in (min) d (max) f sw i l 14.1 h 0.339 (a) = = 0.765 5 (v) 800 (khz) (39) step 4d double-check to make sure the ? current ripple is less than i in (min): i in (min) > 1 / 2 i l (40) 0.353 a > 0.170 a a good inductor value to use would be 15 h. step 4e next insert the inductor value used in the design to determine the actual inductor ripple current: = v in (min) d (max) f sw l used i lused 15 ( h) 0.319 a == 0.765 5 (v) 800 (khz) (41) step 4f determining the inductor current rating. the inductor current rating must be greater than the i in (max) value plus half of the ripple current i l , calculated as follows: l (min) = i in (max) + 1 / 2 i lused (42) = 1.131 (a) + 0.160 (a) = 1.291 a step 5 determining the resistor value for a particular switching frequency. use the r fset values shown in figure 6. for example, a 25.5 k resistor will result in an 800 khz switching frequency. step 6 choosing the proper switching diode. the switching diode must be chosen for three characteristics when it is used in led lighting circuitry. the most obvious two are: current rating of the diode and reverse voltage rating.
wide input voltage range, high efficiency fault tolerant led driver A8510 30 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com the reverse breakdown voltage rating for the output diode in a sepic circuit should be: v bd > v out(ovp) (max) + v in (max) (43) > 15.9 (v) + 16 (v) = 31.9 v because the maximum output voltage in this case is v out(ovp) . the peak current through the diode is calculated as: i dp = i in (max) + 1 / 2 i lused (44) = 1.131 (a) + 0.160 (a) = 1.291 a the third major component in deciding the switching diode is the reverse current, i r , characteristic of the diode. this characteristic is especially important when pwm dimming is implemented. during pwm off-time the boost converter is not switching. this results in a slow bleeding off of the output voltage, due to leakage currents. i r can be a large contributor, especially at high tempera- tures. on the diode that was selected in this design, the current varies between 1 and 100 a. it is often advantageous to pick a diode with a much higher breakdown voltage, just to reduce the reverse current. therefore for this example, pick a diode rated for a v bd of 60 v, instead of just 40 v. step 7 choosing the output capacitors. the output capacitors must be chosen such that they can provide filtering for both the boost converter and for the pwm dimming function. the biggest factors that contribute to the size of the output capacitor are: pwm dimming frequency and pwm duty cycle. another major contributor is leakage current, i lk . this current is the combina- tion of the ovp leakage current as well as the reverse current of the switching diode. in this design the pwm dimming frequency is 200 hz and the minimum duty cycle is 1%. typically, the volt- age variation on the output, v cout , during pwm dimming must be less than 250 mv, so that no audible hum can be heard. the capacitance can be calculated as follows: c out = f pwm(dimming) 1 ? d (min) 1 ? 0.01 200 (hz) i lk 200 ( a) 3.96 f == 0.250 (v) v cout (45) a capacitor larger than 3.96 f should be selected due to degra- dation of capacitance at high voltages on the capacitor. select a 4.7 f capacitor for this application. the rms current through the capacitor is given by: i cout rms = 1 ? d (max) d (max) i out 0.320 (a) 0.577 a == 1 ? 0.765 0.765 (46) the output capacitor must have a ripple current rating of at least 600 ma. the capacitor selected for this design is a 4.7 f 50 v capacitor with a 1.5 a current rating. step 8 selecting input capacitor. the input capacitor must be selected such that it provides a good filtering of the input voltage waveform. a estimation rule is to set the input voltage ripple, v in , to be 1% of the minimum input voltage. the minimum input capacitor requirements are as follows: c in = f sw 0.319 (a) ? i lused 1.00 f 8 == ? v in 800 (khz) 0.05 (v) 8 (47) the rms current through the capacitor is given by: c in rms = ? i lused 0.092 a 12 = = 0.319 (a) 12 (48) a good ceramic input capacitor with a rating of 2.2 f 25 v will suffice for this application.
wide input voltage range, high efficiency fault tolerant led driver A8510 31 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com vgate sw sw q1 l1 d1 c vdd ovp v out c out r sc r adj r1 vsense vin vdd en/pwm apwm iset fset/sync agnd pgnd pgnd comp c p r z c z led8 led1 led2 led3 led4 led5 led6 led7 fault pad A8510 v c r iset r fset c in 6 to 14 v 0.056 590 100 k 120 8.25 k 25.5 k 39.2 k 120 pf 2.2 f 25 v 0.1 f 0.47 f 4.7 f 50 v 3.3 f / 25 v 2 a / 60 v v in c sw r ovp l2 15 h 15 h figure 31. typical application showing sepic configuration, with accurate input current sense, and vsense to gnd protection. step 9 selecting coupling capacitor c sw . the minimum capaci- tance of c sw is related to the maximum voltage ripple allowed across it: c sw = f sw 0.32 (a) 0.765 i out d max 0.627 f == ? v sw 800 (khz) 0.1 (v) (49) the rms current requirement of the coupling capacitor is given by: i csw rms = 1 ? d (max) d (max) i in (max) 1.131 (a) 0.627 a == 1 ? 0.765 0.765 (50) the voltage rating of the coupling capacitor must be greater than v in (max), or 16 v in this case. a ceramic capacitor rated for 2.2 f 25 v will suffice for this application.
wide input voltage range, high efficiency fault tolerant led driver A8510 32 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package ec, 26-pin qfn with exposed thermal pad 0.95 c seating plane c 0.08 27x 26 26 2 1 1 2 26 2 1 a d c a terminal #1 mark area coplanarity includes exposed thermal pad and terminals b exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) for reference only (reference jedec mo-220wgge) dimensions in millimeters exact case and lead configuration at supplier discretion within limits shown c d reference land pattern layout (reference ipc7351 qfn40p400x400x80-29m) all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) 1.23 1.10 1.23 1.10 2.45 2.45 4.00 0.20 0.40 4.00 4.00 0.15 4.00 0.15 0.75 0.05 0.20 0.05 0.40 bsc 0.40 +0.15 ?0.10 b pcb layout reference view top view bottom view
wide input voltage range, high efficiency fault tolerant led driver A8510 33 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com copyright ?2010-2011, allegro microsystems, inc. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com revision history revision revision date description of revision rev. 2 december 15, 2011 update to application examples, add v sync

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