shangh ai belling corp., ltd BL55077 zip: 200233 tel: 86-021-64850700 fax: 86-021-64855865 1 lcd driver for 160 display units BL55077 1 general description the BL55077 is a general lcd driver ic for 160 unit s lcd panel. it features a wide operating supply voltage range, incorporates simple communication interface with microcomputer and is suitable for multiple applicat ion. 2 features advanced low power cmos technology selection of 1/2 or 1/3 bias, selection of 1/2 or 1 /3 or 1/4 duty. operation voltage: 2.5~5.5v serial data interface 160(40x4) display units low power dissipation design: power saving mode: i dd=14ua at 5v and idd=9ua at 3.3v; sleeping mode: idd<2ua maybe cascaded up to 16pcs for large lcd applicatio ns on-chip rc oscillator vlcd for adjusting lcd operating voltage excellent emc immunity compatible with general microcomputer 3 pin assignment fig 1
shangh ai belling corp., ltd BL55077 zip: 200233 tel: 86-021-64850700 fax: 86-021-64855865 2 4 pin description pin no. pin name function 10 sda serial data input/output 11 sci serial clock input 12 sync cascade synchronization clock 13 clk external clock input 14 vdd supply voltage 15 osc oscillator input 16-18 a0 a1 a2 subaddress inputs 19 sa0 slave address input;bit0 20 vss ground 21 vlcd lcd supply voltage 25-28 com0 com2 com1 com3 common terminal driving output 29-32 34-37 49-64 2-7 s0 s39 segment terminal driving output 1 8 9 22 23 24 33 48 nc unused tab.1 5 function description 1.function circuit the bl550077 has all function circuits that can dir ectly drive any static or multiplexed lcd containing up to four commons and up to 40 segm ents. the function circuits include:power-on reset, lcd bias generator, lcd vol tage selector, oscillator, display ram, timing, display latch, shift register, common/segme nt outputs, input/output bank selector, blinker, data pointer, subaddress counter,etc. 2.display function decription the display ram is a static 40x 4-bit ram which sto res lcd data. a logic 1 in the ram bit-map indicates the on state of the correspon ding lcd segment; similarly, a logic 0 indicates the off state. there is a one-to-one corr espondence between the ram addresses and the segment outputs, and between the individual bit s of a ram word and the common outputs. (see fig.2). display ram address and segment s0~s39 output 0 1 2 3 36 37 38 39 0 1 2 com (com0~ com3) 3 fig2 when display data is transmitted to the bl550 77, the display bytes received are stored in the display ram in accordance with the selected lcd drive mode. to illustrate the filling order, an example of a 7-segment numeric display sh owing all drive modes is given in fig.3; the ram filling organization depicted applies equal ly to other lcd types.
shangh ai belling corp., ltd BL55077 zip: 200233 tel: 86-021-64850700 fax: 86-021-64855865 3 fig 3 3. i 2 c-bus protocol two i 2 c-bus slave addresses (0111000 and 0111001) are res erved for the BL55077. the least significant bit of the slave address that a BL55077 will respond to is defined by the level tied at its input sa0. therefore, two types o f BL55077 can be distinguished on the same i 2 c-bus which allows: 1. up to 16 BL55077 on the same i2c-bus for very la rge lcd applications. 2. the use of two types of lcd multiplex on the sam e i2c-bus. the i2c-bus protocol is shown in fig.4. the se quence is initiated with a start condition (s) from the i2c-bus master which is foll owed by one of the two BL55077 slave addresses available. all BL55077s with the correspo nding sa0 level acknowledge in parallel with the slave address but all BL55077s with the al ternative sa0 level ignore the whole i2c-bus transfer. after acknowledgement, one or mor e command bytes (m) follow which define the status of the addressed BL55077s. the la st command byte is tagged with a cleared most significant bit, the continuation bit c. the c ommand bytes are also acknowledged by all addressed BL55077s on the bus. after the last comma nd byte, a series of display data bytes(n) may follow. these display bytes are stored in the d isplay ram at the address specified by the data pointer and the subaddress counter. both data pointer and subaddress counter are automatically updated and the data is directed to t he intended BL55077 device. the acknowledgement after each byte is made only by the (a0, a1 and a2) addressed BL55077. after the last display byte, the i2c-bus master iss ues a stop condition (p).
shangh ai belling corp., ltd BL55077 zip: 200233 tel: 86-021-64850700 fax: 86-021-64855865 4 fig 4 4. command decoder the command decoder identifies command bytes that a rrive on the i 2 c-bus. all available commands carry a continuation bit c in th eir most significant bit position. the five commands available to the BL55077 are defined in fi g 5.
shangh ai belling corp., ltd BL55077 zip: 200233 tel: 86-021-64850700 fax: 86-021-64855865 5 fig 5 6 absolute maximum rating parameter symbol rating unit supply voltage vdd -0.5 +6.0 v lcd operating voltage vlcd 0 vdd v input voltage vi vss-0.5 vdd+0.5 v output voltage vo vlcd-0.5 vdd+0.5 v vdd,vss,vlcd current idd,iss,ilcd -50 +50 ma maximum power consumption ptot 400 mw operating temperature topr -40 +75 o c storage temperature tstg -65 +150 o c 7 dc characteristic symbol parameter test condition min typ max unit vdd ic operating voltage 2.5 - 5.5 v vlcd lcd operating voltage 0 - vdd-2 v idd1 supply current vdd=5v,vlcd=0v,normal mode,internal oscillator - 25 50 ua idd2 supply current vdd=5v,vlcd=0v,power saving mode,internal oscillator - 14 30 ua idd3 supply current vdd=3.3v,vlcd=0v,normal mode,internal oscillator - 16 30 ua idd4 supply current vdd=3.3v,vlcd=0v,power saving mode,internal oscillator - 9 15 ua i sl sleep current vdd=5v,vlcd=0v - 1.5 2 ua vil low voltage input sda,scl vss - 0.3vdd v vih high voltage input sda,scl 0.7vdd - 6.0 v rph pull high resister sync 30 60 100 k
shangh ai belling corp., ltd BL55077 zip: 200233 tel: 86-021-64850700 fax: 86-021-64855865 6 8 ac characteristic ta=25 o c symbol parameter test condition min typ max unit fclk oscillator frequency vdd=5v,normal mode 125 180 300 khz fclk oscillator frequency vdd=3.3v, power saving mode 21 31 48 khz tclk half oscillator cycle 1 - 3 ua tsh1 cs start hold time 5 - us tsh2 scl start hold time 5 - us tlow high time 5 - us thig low time 4 - us thd scl hold time 250 ns fig 6 9 typical application circuit no te: 1/ when i 2 c are idle mode,sda and scl must be connect to high level(by pull up resistor),otherwise the device maybe can no t go into power saving mode. 2/ in power-saving mode, scl frequency must be l ess than 21khz. 3/ work at 1/3 bias, vdd C vlcd must be more than 2.9v 1/ single application
shangh ai belling corp., ltd BL55077 zip: 200233 tel: 86-021-64850700 fax: 86-021-64855865 7 2/ cascade application fig 7 10 package outline lqfp64 unit d e e b f m n mm(tolerance) 10.0(0.1) 12.0(0.15) 0.5 0.22(0.05) 1 .25(0.2) 1.0 0.6(0.15)
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