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SY89202U precision 1:8 lvpecl fanout buffer with three 1/2/4 clock divider output banks precision edge is a registered trademark of micrel, inc micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 ( 408 ) 944 - 0800 ? fax + 1 (408) 474 - 1000 ? htt p://www.micrel.com august 2007 m9999 - 083107-c hbwhelp@micrel.com or (408) 955 - 1690 general description the SY89202U is a precision, high - speed, integrated clock divider lvpecl fanout buffer capable of handling clocks up to 1.5ghz. optimized for communications applications, the three independently controlled output banks are phase match ed and can be configured for pass - through (1), 2 or 4 divide ratios. the differential input includes micrel?s unique, 3 - pin input termination architecture that allows the user to interface to any ac - or dc - coupled signal as small as 100mv (200mv pp ) with out any level shifting or termination resistor networks in the signal path. the low skew, low jitter outputs are 800mv, 100k compatible lvpecl, with extremely fast rise/fall times guaranteed to be less than 220ps. the en (enable) input guarantees that the 1, 2 and 4 outputs will start from the same state without any runt pulse after an asynchronous mr (master reset) is asserted. this is accomplished by enabling the outputs after a four - clock delay to allow the counters to synchronize. the SY89202U is par t of micrel?s precision edge ? product family. datasheets and support documentation can be found on micrel?s web site at www.micrel.com. precision edge ? features three low - skew lvpecl output banks with programmable 1, 2 and 4 divider options ? three in dependently programmable output banks ? guaranteed ac performance over temp and voltage: ? >1.5ghz clock frequency (f max ) ? <930ps in - to - out t pd ? < 220 ps t r /t f ? ultra - low jitter design: ? <1ps rms random jitter (rj) ? <10ps pp total jitter (clock) ? internal inpu t termination ? patent - pending input termination and vt pin accepts ac - and dc - coupled inputs (cml, pecl, lvds) ? 800mv lvpecl output swing ? cmos/ttl - compatible output enable (en) and divider select control ? power supply 2.5v + 5% or 3.3v + 10% ? ? 40 o c to +85 o c indu strial temperature range ? available in 32 - pin qfn package applications ? all sonet/sdh channel select applications ? all fibre channel multi - channel select applications ? all gigabit ethernet multi - channel select applications markets ? lan/wan ? enterprise servers ? at e ? test and measurement
micrel, inc. SY89202U august 2007 2 m9999 - 083107-c hbwhelp@micrel.com or (408) 955 - 1690 functional block diagram
micrel, inc. SY89202U august 2007 3 m9999 - 083107-c hbwhelp@micrel.com or (408) 955 - 1690 ordering information part number package type operating range package marking lead finish SY89202Umg qfn -32 industrial SY89202U with pb - free bar - line indicator nipdau pb - free SY89202Umgtr (2) qfn -32 industrial SY89202U with pb - free bar - line indicator nipdau pb - free notes: 1. contact factory for die availability. dice are guaranteed at t a = 25_c, dc electricals only. 2. tape and reel. pin configuration 32- pin qfn
micrel, inc. SY89202U august 2007 4 m9999 - 083107-c hbwhelp@micrel.com or (408) 955 - 1690 pin description pin numbe r pin name pin function 2, 7, 8 divsel1 divsel2 divsel3 single - ended inputs: these ttl/cmos inputs select the divide ratio for each of the three banks of outputs. note that each of these inputs is internally connected to a 25k ? pull - up resistor and will d efault to logic high state if left open. the input - switching threshold is v cc /2. 3, 6 in, /in differential input: this input pair is the differential signal input to the device. this input accepts ac - or dc - coupled signals as small as 100mv. the input pai r internally terminates to a vt pin through 50 ?. note that these inputs will default to an indeterminate state if left open. please refer to the ?input interface applications? section for more details. 4 vt input termination center - tap: each side of the differential input pair terminat es to the vt pin. the vt pin provides a center - tap to a termination network for maximum interface flexibility. see ?input interface applications? section for more details. 5 vref -ac reference voltage: this output biases to v cc ? 1.2v. it is used for ac - cou pling inputs in and /in. for ac - coupled applications, connect v ref - ac directly to the vt pin. bypass with 0.01f low esr capacitor to v cc . 9 en single - ended input: this ttl/cmos input disables and enables the q0 ? q7 outputs. this input is internally con nected to a 25k ? pull - up resistor and will default to logic high state if left open. the input - switching threshold is v cc /2. for the input enable and disable functional description, refer to ?timing diagram? section. 10, 19, 22, 31 vcc positive power supp ly. bypass with 0.1f||0.01f low esr capacitors as close to vcc pins as possible. 16, 15, 14, 13, 12, 11 q4, /q4, q5, /q5, q6, /q6 bank 2 lvpecl differential output pairs controlled by divsel2: low, q4 ? q6 = 2, high, q4 ? q6 = 4. unused output pairs may be left open. each output is designed to drive 800mv into 50 ? terminated at v cc ? 2v. 30, 29, 28, 27, 26, 25, 24, 23 q0, /q0, q1, /q1, q2, /q2, q3, /q3 bank 1 lvpecl differential output pairs controlled by divsel1: low, q0 ? q3 = 1, high, q0 ? q3 = 2 . unused output pairs may be left open. each output is designed to drive 800mv into 50 ? terminated at v cc ? 2v. 18, 17 q7, /q7 bank 3 lvpecl differential output pair controlled by divsel3: low, q7 = 2, high, q7 = 4. unused output pairs may be left open. each output is designed to drive 800mv into 50 ? terminated at v cc ? 2v. 32 /mr single - ended input: this ttl/cmos - compatible master reset function asynchronously sets q0 ? q7 outputs low and /q0 ? /q7 outputs high, and holds them in that state as long as the /mr input remains low. this input is internally connected to a 25k ? pull - up resistor and will default to a logic high state if left open. the input - switching threshold is v cc /2. 1, 20, 21 gnd, exposed pad ground: ground pin and exposed pad must be conn ected to the same ground plane. truth table /mr ( 1) en ( 2, 3) divsel1 divsel2 divsel3 q0 ? q3 q4 ? q6 q7 0 x x x x 0 0 0 1 0 x x x 0 0 0 1 1 0 0 0 ? 1 ? 2 ? 2 1 1 1 1 1 ? 2 ? 4 ? 4 notes: 1. /mr asynchronously forces q0 ? q7 low (/q0 - /q7 high). 2. en fo rces q0 ? q7 low between 2 and 6 input clock cycles after the falling edge of en. refer to ?timing diagram? section. 3. en synchronously enables the outputs between 2 and 6 input clock cycles after the rising edge of en. refer to ?timing diagram ? section.
micrel, inc. SY89202U august 2007 5 m9999 - 083107-c hbwhelp@micrel.com or (408) 955 - 1690 a bsolute maximum ratings (1) supply voltage (v cc ) .......................... ? 0.5v to +4.0v input voltage (v in ) .................................. ? 0.5v to v cc termination current source or sink current on v t ................... 100ma output current source or sink current on in, /in .............. 50ma v ref-ac current source or sink current on v ref-ac ............ 1.5ma lead temperature (soldering, 20 sec.) .......... +260oc storage temperature (t s ) ................. ? 65oc to 150oc operating ratings (2) supply voltage (v cc ) .................. +2.375v to +2.625v ..................................................... +3.0v to +3.6v ambient temperature (t a ) ................ ? 40oc to +85oc package thermal resistance (3) qfn ( ja ) still - air ..................................................... 35oc/w qfn ( jb ) junction - to - board .................................... 20oc/w dc electrical characteristics (4) t a = ? 40c to +85c, unless noted. symbol parameter condition min typ max units v cc power supply 2.375 3.0 2.625 3.6 v v i cc power supply current no load , max. v cc 125 180 ma r diff_in differential input resistance (in -to - /in) 90 100 110 ? r in input resistance (in -to -v t ) 45 50 55 ? v ih input high voltage (in, /in) 1.2 v cc v v il input low voltage (in, /in) 0 v ih ? 0.1 v v in input voltage swing (in, /in) see figure 1a. 0.1 v cc v v diff_in differential input voltage swing |in - /in| see figure 1b. 0.2 v v ref - ac output reference voltage (v ref - ac ) v cc ? 1.3 v cc ? 1.2 v cc ? 1.1 v in -to -v t voltage from input to v t 1.8 v notes: 1. permanent device damag e may occur if absolute maximum ratings are exceeded. this is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. exposure to absolute maximum ratings conditio ns for extended periods may affect device reliability. 2. the data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most neg ative potential on the pcb. ja and jb values are determined for a 4 - layer board in still air, unless otherwise stated. 4. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been established .
micrel, inc. SY89202U august 2007 6 m9999 - 083107-c hbwhelp@micrel.com or (408) 955 - 1690 lvpecl outputs dc electrical characteristics (5) v cc = 2.5v 5% or 3.3v 10%; t a = ? 40oc to + 85oc; r l = 50 ? to v cc ? 2v, unless otherwise stated. symbol parameter condition min typ max units v oh output high voltage q, /q v cc - 1.145 v cc ? 0.895 v v ol output low voltage q, /q v cc - 1.945 v cc ? 1.695 v v out output voltage swing q, /q see figure 1a. 550 800 mv v diff - out differential output voltage swing |q ? /q| see figure 1b. 1100 1600 mv lvttl/cmos dc electrical characteristics (5) v cc = 2.5v 5% or 3.3v 10%; t a = ? 40oc to + 85oc, unless otherwise stated. symbol parameter condition min typ max units v ih input high voltage 2.0 v v ih input low voltage 0.8 v i ih input high current ? 125 30 a i il input low current ? 300 a note: 5. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been established.
micrel, inc. SY89202U august 2007 7 m9999 - 083107-c hbwhelp@micrel.com or (408) 955 - 1690 ac electrical characteristics (6) v cc = 2.5v 5% or 3.3v 10%; t a = ? 40oc to + 85oc, r l = 50 ? to v cc ? 2v, unless otherwise stated. symbol parameter condition min typ ma x units f max maximum output toggle frequency output swing 400mv 1.5 ghz maximum input frequency 3.0 ghz t pd differential propagation delay /mr ? q propagation delay in -to -q 530 700 930 ps 900 ps t pd tempco differential propagation delay t emperature coefficient 115 fs/ o c t skew within - bank skew within same fanout bank, note 7 10 25 ps bank -to - bank skew same divide setting, note 8 15 35 ps bank -to - bank skew different divide setting, note 8 25 50 ps part -to - part skew note 9 200 ps t jitter deterministic jitter (dj) note 10 10 ps pp random jitter (rj) note 11 1 ps rms total jitter note 12 10 ps pp cycle -to - cycle jitter note 13 1 ps rms t r, t f output rise/fall time 20% to 80%, at full output swing. 70 130 220 ps notes: 6. measured with 100mv input swing. see ?timing diagrams? section for definition of parameters. high - frequency ac - parameters are guaranteed by design and characterization. 7. within - bank skew is the difference in propagation delays among the outputs withi n the same bank. 8. bank - to - bank skew is the difference in propagation delays between outputs from different banks. bank - to - bank skew is also the phase offset between each bank, after mr is applied. 9. part - to - part skew is defined for two parts with identical p ower supply voltages at the same temperature and with no skew of the edges at the respective inputs. 10. deterministic jitter is measured with a k28.7 101010 pattern, measured at micrel, inc. SY89202U august 2007 8 m9999 - 083107-c hbwhelp@micrel.com or (408) 955 - 1690 single- ended and differential swings figure 1a. single - ended voltage swing figure 1b. differential voltage swing timing diagrams timing diagram showi ng reset with output enabled
micrel, inc. SY89202U august 2007 9 m9999 - 083107-c hbwhelp@micrel.com or (408) 955 - 1690 timing diagram showing enable timing timing diagram showing disable timing
micrel, inc. SY89202U august 2007 10 m9999 - 083107-c hbwhelp@micrel.com or (408) 955 - 1690 typical operating characteristics functional characteristics
micrel, inc. SY89202U august 2007 11 m9999 - 083107-c hbwhelp@micrel.com or (408) 955 - 1690 input and output stages figure 2a. simplified differential input stage figure 2 b . simplified lvpecl output stage input interface applications figure 3 a. lvpecl interface (dc - coupled) figure 3b . lvpecl interface (ac - coupled) figure 3c . cml interface (dc - coupled) figure 3d . cml interface (ac - coup led) figure 3e . lvds interface (dc - coupled) figure 3f . lvds interface (ac - coupled)
micrel, inc. SY89202U august 2007 12 m9999 - 083107-c hbwhelp@micrel.com or (408) 955 - 1690 lvpecl output interface applications lvpecl has high input impedance, and very low output impedance (open emitter), and small signal swing which results in low emi. lvpecl is ideal for driving 50 ? - and 100? - controllled impedance transmission lines. there are several techniques for terminating the lvpecl output: parallel termination - thevenin equivalent, parallel termination (3 - resistor), and ac - coupled termination. unu sed output pairs may be left floating. however, single - ended outputs must be terminated, or balanced. figure 4. parallel termination - thevenin equivalent figure 5 . parallel termination (3 - resistor) related product and support documentation part num ber function datasheet link sy89200u ultra - precision 1:8 lvds fanout with three 1/ 2/ 4 clock divider output banks http://www.micrel.com/_pdf/hbw/sy89200u.pdf#page= 1 hbw solutions new products and applications http://www.micrel.com/page.do?page=/product - info/as/hbwsolutions.shtml
micrel, inc. SY89202U august 2007 13 m9999 - 083107-c hbwhelp@micrel.com or (408) 955 - 1690 package information 32- pin qfn micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944 - 0800 fax +1 (408) 4 74 - 1000 web http://www.micrel.com the information furnished by micrel in this data sheet is believed to be accurate and reliable. however, no responsibility is assumed by micrel for its use. micrel reserves the right to change circuitry and specification s at any time without notification to the customer. micrel products are not designed or authorized for use as components in life support appliances, devices or systems where mal function of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a signific ant injury to the user. a purcha ser?s use or sale of micrel products for use in life support appliances, devices or systems is a purchaser?s own risk and pur chaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2006 micrel, incorporated.

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