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w wm8768 24-bit, 192khz 8-channel dac wolfson microelectronics plc to receive regular email updates, sign up at http://www.wolfsonmicro.com/enews production data, july 2010, rev 4.3 copyright ? 2010 wolfson microelectronics plc description the wm8768 is a multi-channel audio dac ideal for dvd and surround sound processing applications for home hi-fi, automotive and other audio visual equipment. four stereo 24-bit multi-bit sigma delta dacs are used with oversampling digital interpolation filters. digital audio input word lengths from 16-32 bits and sampling rates from 8khz to 192khz are supported. each dac channel has independent digital volume and mute control. the audio data interface supports i 2 s, left justified, right justified and dsp digital audio formats. the device is controlled either via a 3 wire serial interface or directly using the hardware interface. these interfaces provide access to features including channel selection, volume controls, mutes, de-emphasis and power management facilities. the device is available in a 28-lead ssop. features ? 8-channel dac with pcm. ? audio performance ? 103db snr (?a? weighted @ 48khz) dac ? dac sampling frequency: 8khz ? 192khz ? 3-wire spi serial or hardware control interface ? programmable audio data interface modes ? i 2 s, left, right justified or dsp ? 16/20/24/32 bit word lengths ? four independent stereo dac outputs with independent digital volume controls ? master or slave audio data interface ? 2.7v to 5.5v analogue, 2.7v to 3.6v digital supply operation ? 28 lead ssop package applications ? dvd players ? surround sound av processors and hi-fi systems ? automotive audio block diagram vrefn vrefp vmid dgnd avdd dvdd md/dm mc/iwl ml/i2s mode mute testref1 agnd
wm8768 production data w pd rev 4.3 july 2010 2 table of contents description ................................................................................................................1 features......................................................................................................................1 applications ..............................................................................................................1 block diagram ..........................................................................................................1 table of contents ..................................................................................................2 pin configuration 28 lead ssop ........................................................................3 ordering information ...........................................................................................3 pin description ? 28 lead ssop ............................................................................4 absolute maximum ratings ..................................................................................5 recommended operating conditions ..............................................................6 electrical characteristics ...............................................................................6 master clock timing ....................................................................................................... 8 digital audio interface ? master mode ................................................................... 8 digital audio interface ? slave mode ...................................................................... 9 mpu interface timing .................................................................................................... 11 internal power on reset circuit ...................................................................12 device description ................................................................................................13 introduction .................................................................................................................. . 13 pcm audio data sampling rates ................................................................................ 13 hardware control modes ......................................................................................... 14 digital audio interface ............................................................................................... 16 powerdown modes ....................................................................................................... 19 software control interface operation ............................................................. 20 control interface registers .................................................................................. 20 register map ............................................................................................................32 digital filter characteristics ........................................................................33 dac filter responses ..........................................................................................33 digital de-emphasis characteristics ..................................................................... 34 applications information ..................................................................................35 recommended external components .................................................................... 35 recommended external components values ..................................................... 35 suggested analogue low pass post dac filters ............................................. 36 package drawing ...................................................................................................37 important notice ...................................................................................................38 address: ...................................................................................................................... ...... 38
production data wm8768 w pd rev 4.3 july 2010 3 pin configuration 28 lead ssop ordering information device temperature range package moisture sensitivity level peak soldering temperature wm8768geds/v -25 to +85 o c 28-lead ssop (pb-free) msl3 260c wm8768geds/rv -25 to +85 o c 28-lead ssop (lpb-free, tape and reel) msl3 260c note: reel quantity = 2,000
wm8768 production data w pd rev 4.3 july 2010 4 pin description ? 28 lead ssop pin name type description 1 mode digital input control format selection 0 = software control 1 = hardware control 2 mclk digital input master clock; 128, 192, 256, 384, 512, 768fs or 1152fs (fs = word clock frequency) 3 bclk digital input/output audio interface bit clock 4 lrclk digital input/output audio left/right word clock 5 dvdd supply digital positive supply 6 dgnd supply digital negative supply 7 din1 digital input dac channel 1 data input 8 din2 digital input dac channel 2 data input 9 din3 digital input dac channel 3 data input 10 din4 digital input dac channel 4 data input 11 ml/i2s digital input software mode: serial interface latch signal hardware mode: input audio data format 12 mc/iwl digital input software mode: serial control interface clock hardware mode: audio data input word length 13 md/dm digital input software mode: serial interface data hardware mode: de-emphasis selection 14 mute digital input/output dac zero flag output or dac mute input 15 testref1 analogue output test pin 16 vrefn analogue input dac negative reference supply 17 vrefp analogue input dac positive reference supply 18 vmid analogue output midrail divider decoupling pin; 10uf external decoupling 19 vout4l analogue output dac channel 4 left output 20 vout4r analogue output dac channel 4 right output 21 vout1l analogue output dac channel 1 left output 22 vout1r analogue output dac channel 1 right output 23 vout2l analogue output dac channel 2 left output 24 vout2r analogue output dac channel 2 right output 25 vout3l analogue output dac channel 3 left output 26 vout3r analogue output dac channel 3 right output 27 agnd supply analogue negative supply and substrate connection 28 avdd supply analogue positive supply note : digital input pins have schmitt trigger input buffers.
production data wm8768 w pd rev 4.3 july 2010 5 absolute maximum ratings absolute maximum ratings are stress ratings only. permanent damage to the device may be caused by continuously operating at or beyond these limits. device functional operating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of this device. wolfson tests its package types according to ipc/jedec j-std-020b for moisture sensitivity to determine acceptable storage conditions prior to surface mount assembly. these levels are: msl1 = unlimited floor life at <30 c / 85% relative humidity. not normally stored in moisture barrier bag. msl2 = out of bag storage for 1 year at <30 c / 60% relative humidity. supplied in moisture barrier bag. msl3 = out of bag storage for 168 hours at <30 c / 60% relative humidity. supplied in moisture barrier bag. the moisture sensitivity level for each package type is specified in ordering information. condition min max digital supply voltage -0.3v +5v analogue supply voltage -0.3v +7v voltage range digital inputs dgnd -0.3v dvdd +0.3v voltage range analogue inputs agnd -0.3v avdd +0.3v master clock frequency 37mhz operating temperature range, t a -25 c +85 c storage temperature after soldering -65 c +150 c notes: 1. analogue and digital grounds must always be within 0.3v of each other for normal operation of the device.
wm8768 production data w pd rev 4.3 july 2010 6 recommended operating conditions parameter symbol test conditions min typ max unit digital supply range dvdd 2.7 3.6 v analogue reference supply vrefp 2.7 5.5 v analogue supply range avdd 2.7 5.5 v ground agnd, vrefn, dgnd 0 v difference dgnd to agnd -0.3 0 +0.3 v note: digital supply dvdd must never be more than 0.3v greater than avdd for normal operation of the device. electrical characteristics test conditions avdd, vrefp = 5v, dvdd = 3.3v, agnd, vrefn = 0v, dgnd = 0v, t a = +25 o c, fs = 48khz, mclk = 256fs, unless otherwise stated. parameter symbol test conditions min typ max unit digital logic levels (cmos levels) input low level v il 0.3 x dvdd v input high level v ih 0.7 x dvdd v output low v ol i ol =1ma 0.1 x dvdd v output high v oh i oh = -1ma 0.9 x dvdd v analogue reference levels reference voltage v vmid vrefp/2 v potential divider resistance r vmid vrefp to vmid and vmid to vrefn 100 k dac performance (load = 10k , 50pf) 0dbfs full scale output voltage 1.0 x vrefp/5 vrms snr (note 1,2,4) a-weighted, @ fs = 48khz 95 103 db snr (note 1,2,4) a-weighted @ fs = 96khz 101 db snr (note 1,2,4) a-weighted @ fs = 192khz 101 db snr (note 1,2,4) a-weighted @ fs = 48khz, avdd = 3.3v 101 db snr (note 1,2,4) a-weighted @ fs = 96khz, avdd = 3.3v 96 db dynamic range (note 2,4) dnr a-weighted, -60db full scale input 95 103 db total harmonic distortion (thd) (note 4) 1khz, 0dbfs -90 -83 db mute attenuation 1khz input, 0db gain 100 db dac channel separation 100 db power supply rejection ratio psrr 1khz 100mvpp 50 db 20hz to 20khz 100mvp-p 45 db supply current analogue supply current avdd = 5v 18.4 ma digital supply current dvdd = 3.3v 14.6 ma
production data wm8768 w pd rev 4.3 july 2010 7 notes: 1. ratio of output level with 1khz full scale input, to the output level with all zeros into the digital input, measured ?a? weighted. 2. all performance measurements done with 20khz low pass filter, and where noted an a-weight filter. failure to use such a filter will result in higher thd+n and lower snr and dynamic range readings than are found in the electrical characteristics. the low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. 3. vmid decoupled with 10uf and 0.1uf capacitors (smaller values may result in reduced performance). 4. the performance of each dac is measured separately terminology 1. signal-to-noise ratio (db) - snr is a measure of the difference in level between the full scale output and the output with no signal applied. (no auto-zero or automute function is employed in achieving these results). 2. dynamic range (db) - dnr is a measure of the difference between the highest and lowest portions of a signal. normally a thd+n measurement at 60db below full scale. the measured signal is then corrected by adding the 60db to it. (e.g. thd+n @ -60db= -32db, dr= 92db). 3. thd+n (db) - thd+n is a ratio of the rms values of (noise + distortion)/signal. 4. stop band attenuation (db) - is the degree to which the frequency spectrum is attenuated (outside audio band). 5. channel separation (db) - also known as crosstalk. this is a measure of the amount one channel is isolated from the other. normally measured by sending a full scale signal down one channel and measuring the other. 6. pass-band ripple - any variation of the frequency response in the pass-band region.
wm8768 production data w pd rev 4.3 july 2010 8 master clock timing mclk t mclkl t mclkh t mclky figure 1 dac master clock timing requirements test conditions avdd, vrefp = 5v, dvdd = 3.3v, agnd, vrefn = 0v, dgnd = 0v, t a = +25 o c, fs = 48khz, mclk = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit system clock timing information mclk system clock pulse width high t mclkh 11 ns mclk system clock pulse width low t mclkl 11 ns mclk system clock cycle time t mclky 28 1000 ns mclk duty cycle 40:60 60:40 power-saving mode activated after mclk stopped 2 10 us normal mode resumed after mclk re-started 0.5 1 mclk cycle table 1 master clock timing requirements note: if mclk period is longer than maximum specified above, power-saving mode is entered and dacs are powered down with internal digital audio filters being reset. in this power-saving mode, all registers will retain their values and can be accessed in the normal manner through the control interface. once mclk is restored, the dacs are automatically powered up, but a write to the volume update register bit is required to restore the correct volume settings. digital audio interface ? master mode bclk din1/2/3/4 lrclk wm8768 dac dsp/ decoder 4 figure 2 audio interface - master mode
production data wm8768 w pd rev 4.3 july 2010 9 bclk (output) lrclk (output) t dl din1/2/3/4 t dht t dst figure 3 digital audio data timing ? master mode test conditions avdd, vrefp = 5v, dvdd = 3.3v, agnd, vrefn, dgnd = 0v, t a = +25 o c, master mode, fs = 48khz, mclk = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit audio data input timing information lrclk propagation delay from bclk falling edge t dl 0 10 ns din1/2/3/4 setup time to bclk rising edge t dst 10 ns din1/2/3/4 hold time from bclk rising edge t dht 10 ns table 2 digital audio data timing ? master mode digital audio interface ? slave mode bclk din1/2/3/4 lrclk wm8768 dac dsp/ decoder 4 figure 4 audio interface ? slave mode
wm8768 production data w pd rev 4.3 july 2010 10 bclk lrclk t bch t bcl t bcy din1/2/3/4 t lrsu t ds t lrh figure 5 digital audio data timing ? slave mode test conditions avdd = 5v, dvdd = 3.3v, agnd = 0v, dgnd = 0v, t a = +25 o c, slave mode, fs = 48khz, mclk = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit audio data input timing information bclk cycle time t bcy 50 ns bclk pulse width high t bch 20 ns bclk pulse width low t bcl 20 ns lrclk set-up time to bclk rising edge t lrsu 10 ns lrclk hold time from bclk rising edge t lrh 10 ns din1/2/3/4 set-up time to bclk rising edge t ds 10 ns din1/2/3/4 hold time from bclk rising edge t dh 10 ns table 3 digital audio data timing ? slave mode
production data wm8768 w pd rev 4.3 july 2010 11 mpu interface timing ml/i2s mc/iwl md/dm t csl t dho t dsu t csh t scy t sch t scl t scs lsb t css figure 6 spi compatible control interface input timing test conditions avdd = 5v, dvdd = 3.3v, agnd, dgnd = 0v, t a = +25 o c, fs = 48khz, mclk = 256fs unless otherwise stated parameter symbol min typ max unit mc/iwl rising edge to ml/i2s rising edge t scs 60 ns mc/iwl pulse cycle time t scy 80 ns mc/iwl pulse width low t scl 30 ns mc/iwl pulse width high t sch 30 ns md/dm to mc/iwl set-up time t dsu 20 ns mc/iwl to md/dm hold time t dho 20 ns ml/i2s pulse width low t csl 20 ns ml/i2s pulse width high t csh 20 ns ml/i2s rising to mc/iwl rising t css 20 ns table 4 3-wire spi compatible control interface input timing information
wm8768 production data w pd rev 4.3 july 2010 12 internal power on reset circuit figure 7 internal power on reset circuit schematic the wm8768 includes an internal power-on-reset circuit, as shown in figure 7, which is used reset the digital logic into a default state after power up. the por circuit is powered from dvdd and monitors dvdd. it asserts porb low if dvdd is below a minimum threshold. figure 8 typical power-up sequence figure 8 shows a typical power-up sequence. when dvdd goes above the minimum threshold, vpord, there is enough voltage for the circuit to guarantee porb is asserted low and the chip is held in reset. in this condition, all writes to the control interface are ignored. when dvdd rises to vpor_on, porb is released high and all registers are in their default state and writes to the control interface may take place. on power down, porb is asserted low whenever dvdd drops below the minimum threshold vpor_off. symbol min typ max unit v pord 0.3 0.5 0.8 v v por_on 1.3 1.7 2.0 v v por_off 1.3 1.7 2.0 v table 5 typical por operation (typical values, not tested)
production data wm8768 w pd rev 4.3 july 2010 13 device description introduction wm8768 is a complete 8-channel dac including digital interpolation and decimation filters and switched capacitor multi-bit sigma delta dacs with digital volume controls on each channel and output smoothing filters. the device is implemented as four separate stereo dacs in a single package and controlled by a single interface. each stereo dac has its own data input din1/2/3/4. dac word clock lrclk, dac bit clock bclk and dac master clock mclk are shared between them. the audio interface may be configured to operate in either master or slave mode. in slave mode, lrclk and bclk are all inputs. in master mode, lrclk and bclk are all outputs. each dac has its own digital volume control that is adjustable in 0.5db steps. the digital volume controls may be operated independently. in addition, a zero cross detect circuit is provided for each dac for the digital volume controls. the digital volume control detects a transition through the zero point before updating the volume. this minimises audible clicks and ?zipper? noise as the gain values change. control of internal functionality of the device is by 3-wire serial or pin programmable control interface. the software control interface may be asynchronous to the audio data interface as control data will be re-synchronised to the audio processing internally. operation using master clocks of 128fs, 192fs, 256fs, 384fs, 512fs, 768fs or 1152fs is provided for the dac in slave mode selection between clock rates is automatically controlled. audio sample rates (fs) from less than 8ks/s up to 192ks/s are allowed for the dac, provided the appropriate master clock is input. in pcm mode, the audio data interface supports right justified, left justified and i 2 s (philips left justified, one bit delayed) interface formats along with a highly flexible dsp serial port interface. pcm audio data sampling rates in a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. this clock is often referred to as the audio system?s master clock. the external master system clock can be applied directly through the dac mclk input pin(s) with no software configuration necessary the dac master clock for wm8768 supports audio sampling rates from 128fs to 1152fs, where fs is the audio sampling frequency (lrclk) typically 32khz, 44.1khz, 48khz, 96khz or 192khz. the master clock is used to operate the digital filters and the noise shaping circuits. in slave mode the wm8768 has a master clock detection circuit that automatically determines the relationship between the system clock frequency and the sampling rate (to within +/- 32 master clocks). if there is a greater than 32 clocks error the interface defaults to 1152fs mode. the wm8768 is tolerant of phase variations or jitter on the master clock. table 6 shows the typical master clock frequency inputs for the wm8768. the signal processing for the wm8768 typically operates at an oversampling rate of 128fs. the exception to this is for operation with a 128/192fs system clock, e.g. for 192khz operation, when the oversampling rate is 64fs.
wm8768 production data w pd rev 4.3 july 2010 14 sampling rate (lrclk) system clock frequency (mhz) 128fs 192fs 256fs 384fs 512fs 768fs 1152fs 32khz 4.096 6.144 8.192 12.288 16.384 24.576 36.864 44.1khz 5.6448 8.467 11.2896 16.9340 22.5792 33.8688 unavailable 48khz 6.144 9.216 12.288 18.432 24.576 36.864 unavailable 96khz 12.288 18.432 24.576 36.864 unavailable unavailable unavailable 192khz 24.576 36.864 unavailable unavailable unavailable unavailable unavailable table 6 system clock frequencies versus sampling rate hardware control modes when the mode pin is held high, the following hardware modes of operation are available. mute and automute operation in both hardware and software modes, the mute pin controls the selection of mute directly, and can be used to enable and disable the automute function. this pin becomes an output when left floating and indicates infinite zero detect (izd) has been detected. description 0 normal operation 1 mute dac channels floating enable izd, mute pin becomes an output to indicate when izd occurs. l=izd not detected, h=izd detected. table 7 mute and automute control figure 9 shows the application and release of mute whilst a full amplitude sinusoid is being played at 48khz sampling rate. when mute (lower trace) is asserted, the output (upper trace) begins to decay exponentially from the dc level of the last input sample. the output will decay towards v mid with a time constant of approximately 64 input samples. when mute is de-asserted, the output will restart almost immediately from the current input sample. figure 9 application and release of soft mute -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 0 0.001 0.002 0.003 0.004 0.005 0.006 time(s)
production data wm8768 w pd rev 4.3 july 2010 15 in hardware mode (mode pin set high) the mute pin becomes a bi-directional pin. therefore if it is driven low the device will never softmute. if it is driven high then all channels will softmute immediately. however if the pin is connected to a high impedance, or left floating, then when all four internal zero flags are raised. the wm8768 will also drive a weak logic high signal on the mute pin (output impedance 10kohms) which can be used to drive an external device. it is not possible to perform analogue mute in hardware mode. figure 10 mute logic in hardware mode input format selection in hardware mode, ml/i2s and mc/iwl become input controls for selection of input data format type and input data word length for the dac. ml/i2s mc/iwl input data mode 0 0 24-bit right justified 0 1 20-bit right justified 1 0 16-bit i 2 s 1 1 24-bit i 2 s table 8 input format selection note: in 24 bit i 2 s mode, any width of 24 bits or less is supported provided that the left/right clo cks (lrclk) are high for a minimum of 24 bit clocks (bclk) and low for a minimum of 24 bit clocks. if exactly 32 bit clocks occur in one left/right clock (16 high, 16 low) the chip will auto detect and run a 16 bit data mode. de-emphasis control in hardware mode, the md/dm pin becomes an input control for selection of de-emphasis filtering to be applied. md/dm de-emphasis 0 off 1 on table 9 de-emphasis control
wm8768 production data w pd rev 4.3 july 2010 16 digital audio interface master and slave modes the audio interface operates in either slave or master mode, selectable using the ms control bit. in both master and slave modes din1/2/3/4 are always inputs to the wm8768. the default is slave mode. in slave mode, lrclk and bclk are inputs to the wm8768 (figure 11). din1/2/3/4 and lrclk are sampled by the wm8768 on the rising edge of bclk. by setting the control bit bcp the polarity of bclk may be reversed so that din1/2/3/4 and lrclk are sampled on the falling edge of bclk . bclk din1/2/3/4 lrclk wm8768 dac dsp/ decoder 4 figure 11 slave mode in master mode, lrclk and bclk are outputs from the wm8768 (figure 12). lrclk and bclk are generated by the wm8768. din1/2/3/4 are sampled by the wm8768 on the rising edge of bclk so the controller must output dac data that changes on the falling edge of bclk. by setting control bit bcp the polarity of bclk may be reversed so that din1/2/3/4 are sampled on the falling edge of bclk.. bclk din1/2/3/4 lrclk wm8768 dac dsp/ decoder 4 figure 12 master mode
production data wm8768 w pd rev 4.3 july 2010 17 audio interface formats audio data is applied to the internal dac filters via the digital audio interface. 5 popular interface formats are supported: ? left justified mode ? right justified mode ? i 2 s mode ? dsp mode a ? dsp mode b all 5 formats send the msb first and support word lengths of 16, 20, 24 and 32 bits, with the exception of 32 bit right justified mode, which is not supported. in left justified, right justified and i 2 s modes, the digital audio interface receives dac data on the din1/2/3/4 inputs. audio data for each stereo channel is time multiplexed with lrclk indicating whether the left or right channel is present. lrclk is also used as a timing reference to indicate the beginning or end of the data words. in left justified, right justified and i 2 s modes, the minimum number of bclks per lrclk period is 2 times the selected word length. lrclk must be high for a minimum of word length bclks and low for a minimum of word length bclks. any mark to space ratio on lrclk is acceptable provided the above requirements are met. in dsp modes a or b, all 8 dac channels are time multiplexed onto din1. lrclk is used as a frame sync signal to identify the msb of the first word. the minimum number of bclks per lrclk period is 8 times the selected word length. any mark to space ratio is acceptable on lrclk provided the rising edge is correctly positioned. left justified mode in left justified mode, the msb of din1/2/3/4 is sampled by the wm8768 on the first rising edge of bclk following a lrclk transition. lrclk is high during the left samples and low during the right samples (figure 13). figure 13 left justified mode timing diagram left channel right channel lrcin bckin din1/2/3/4 1/fs n 3 2 1 n-2 n-1 lsb msb n 3 2 1 n-2 n-1 lsb msb
wm8768 production data w pd rev 4.3 july 2010 18 right justified mode in right justified mode, the lsb of din1/2/3/4 is sampled by the wm8768 on the rising edge of bclk preceding a lrclk transition. lrclk are high during the left samples and low during the right samples (figure 14). figure 14 right justified mode timing diagram i2s mode in i 2 s mode, the msb of din1/2/3/4 is sampled by the wm8768 on the second rising edge of bclk following a lrclk transition. lrclk are low during the left samples and high during the right samples. figure 15 i 2 s mode timing diagram dsp mode a in dsp mode a, the msb of dac channel 1 left data is sampled by the wm8768 on the second rising edge on bclk following a lrclk rising edge. dac channel 1 right and dac channels 2/3/4 data follow dac channel 1 left data (figure 16). figure 16 dsp mode a timing diagram ? dac data input left channel right channel lrcin bckin din1/2/3/4 1/fs n 3 2 1 n-2 n-1 lsb msb n 3 2 1 n-2 n-1 lsb msb left channel right channel lrcin bckin din1/2/3/4 1/fs n 3 2 1 n-2 n-1 lsb msb n 3 2 1 n-2 n-1 lsb msb 1 bckin 1 bckin 1 bckin lrcin bckin din1 input word length (iwl) 1/fs channel 1 left n 2 1 n-1 lsb msb n 2 1 n-1 channel 1 right 2 1 channel 2 left n n-1 channel 4 right no valid data 1 bckin
production data wm8768 w pd rev 4.3 july 2010 19 dsp mode b in dsp mode b, the msb of dac channel 1 left data is sampled by the wm8768 on the first bclk rising edge following a lrclk rising edge. dac channel 1 right and dac channels 2/3/4 data follow dac channel 1 left data (figure 17). figure 17 dsp mode b timing diagram ? dac data input in both dsp modes a and b, dacl1 is always sent first, followed immediately by dacr1 and the data words for the other 8 channels. no bclk edges are allowed between the data words. the word order is dac1 left, dac1 right, dac2 left, dac2 right, dac3 left, dac3 right, dac4 left, dac4 right . powerdown modes the wm8768 has powerdown control bits allowing specific parts of the wm8768 to be powered off when not being used. the four stereo dacs each have a separate powerdown control bit, dacd[2:0] & dacd4, allowing individual stereo dacs to be powered off when not in use. setting dacd will power down everything except the reference vmid. this may be powered down by setting pdwn. setting pdwn will override all other powerdown control bits. it is recommended that the dacs are powered down before setting pdwn. lrcin bckin din1 input word length (iwl) 1/fs channel 1 left n 2 1 n-1 lsb msb n 2 1 n-1 channel 1 right 2 1 channel 2 left n n-1 channel 4 right no valid data 1
wm8768 production data w pd rev 4.3 july 2010 20 software control interface operation the wm8768 is controlled using a 3-wire serial interface in software mode or pin programmable in hardware mode. the control mode is selected by the state of the mode pin. 3-wire (spi compatible) serial control mode md/dm is used for the program data, mc/iwl is used to clock in the program data and ml/i2s is used to latch the program data. md/dm is sampled on the rising edge of mc/iwl. the 3-wire interface protocol is shown in figure 18. b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ml/i2s mc/iwl md/dm figure 18 3-wire spi compatible interface 1. b[15:9] are control address bits 2. b[8:0] are control data bits 3. ml/i2s is edge sensitive ? the data is latched on the rising edge of ml/i2s. control interface registers attenuator control mode setting the atc register bit causes the left channel attenuation settings to be applied to both left and right channel dacs from the next audio input sample. no update to the attenuation registers is required for atc to take effect. register address bit label default description 0000010 dac channel control 3 atc 0 attenuator control mode: 0 : right channels use right attenuations 1: right channels use left attenuations
production data wm8768 w pd rev 4.3 july 2010 21 dac output control the dac output control word determines how the left and right inputs to the audio interface are applied to the left and right dacs: register address bit label default description 0000010 dac control 8:5 pl[3:0] 1001 pl[3:0] left output right output 0000 mute mute 0001 left mute 0010 right mute 0011 (l+r)/2 mute 0100 mute left 0101 left left 0110 right left 0111 (l+r)/2 left 1000 mute right 1001 left right 1010 right right 1011 (l+r)/2 right 1100 mute (l+r)/2 1101 left (l+r)/2 1110 right (l+r)/2 1111 (l+r)/2 (l+r)/2 dac digital audio interface control register interface format is selected via the fmt[1:0] register bits: register address bit label default description 0000011 interface control 1:0 fmt [1:0] 00 interface format select 00 : right justified mode 01: left justified mode 10: i 2 s mode 11: dsp modes a or b in left justified, right justified or i 2 s modes, the lrp register bit controls the polarity of lrclk. if this bit is set high, the expected polarity of lrclk will be the opposite of that shown figure 13, figure 14 and figure 15. note that if this feature is used as a means of swapping the left and right channels, a 1 sample phase difference will be introduced. in dsp modes, the lrp register bit is used to select between modes a and b. register address bit label default description 0000011 interface control 2 lrp 0 in left/right/i 2 s modes: lrclk polarity (normal) 0 : normal lrclk polarity 1: inverted lrclk polarity in dsp mode: 0 : dsp mode a 1: dsp mode b
wm8768 production data w pd rev 4.3 july 2010 22 by default, lrclk and din1/2/3/4 are sampled on the rising edge of bclk and should ideally change on the falling edge. data sources that change lrclk and din1/2/3/4 on the rising edge of bclk can be supported by setting the bcp register bit. setting bcp to 1 inverts the polarity of bclk to the inverse of that shown in figure 13, figure 14, figure 15, figure 16, figure 17 and figure 18. register address bit label default description 0000011 interface control 3 bcp 0 bclk polarity 0 : normal bclk polarity 1: inverted bclk polarity the iwl[1:0] bits are used to control the input word length. register address bit label default description 0000011 interface control 5:4 iwl [1:0] 00 input word length 00 : 16 bit data 01: 20 bit data 10: 24 bit data 11: 32 bit data note: if 32-bit mode is selected in right justified mode, the wm8768 defaults to 24 bits. in all modes, the data is signed 2's complement. the digital filters always input 24-bit data. if the dac is programmed to receive 16 or 20 bit data, the wm8768 pads the unused lsbs with zeros. if the dac is programmed into 32 bit mode, the 8 lsbs are ignored. note: in 24 bit i 2 s mode, any width of 24 bits or less is supported provided that lrclk is high for a minimum of 24 bclks and low for a minimum of 24 bclks. if exactly 32 bit clocks occur in one left/right clock (16 high, 16 low) the chip will auto detect and run a 16 bit data mode. a number of options are available to control how data from the digital audio interface is applied to the dac channels. dac output phase the dac phase control word determines whether the output of each dac is non-inverted or inverted register address bit label default description 0000011 dac phase 8:6 phase [2:0] 000 bit dac phase 0 dac1l/r 1 = invert 1 dac2l/r 1 = invert 2 dac3l/r 1 = invert 0001111 dac4 control 3 phase4 0 n/a dac4l/r 1 = invert digital zero cross-detect the digital volume control also incorporates a zero cross detect circuit which detects a transition through the zero point before updating the digital volume control with the new volume. this is enabled by control bit dzcen. register address bit label default description 0001001 dac control 0 dzcen 0 dac digital volume zero cross enable: 0: zero cross detect enabled 1: zero cross detect disabled
production data wm8768 w pd rev 4.3 july 2010 23 softmute the digital muting function used in software and hardware mode applies a softmute with the operating characteristics shown in figure 19. figure 19 soft mute operation when the softmute is applied the output of the device will decay towards v mid with a time constant of approximately 64 input samples. when the mute is released, either manually or automatically by the chip, the output will restart immediately from the current input sample. analogue mute analogue mute can only be used in software mode and will cause the output of the selected dac to perform an analogue mute that clamps the output of the dac to vmid. this function is dependent in the izd bit which is described in section infinite zero detect, later. -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 0 0.001 0.002 0.003 0.004 0.005 0.006 time(s)
wm8768 production data w pd rev 4.3 july 2010 24 software mute modes the wm8768 can be muted in a number of different ways when in software mode (mode pin pulled low). refer to figure 20 which shows a representation of the interaction between functions described below. figure 20 internal mute logic 1024 zeros detect dzfm selector zflag1 zflag2 zflag3 mute (pin) 10kohm channel1 softmute channel2 softmute channel3 softmute mute (register) decode izd mpd dmute4, dmute(2:0) din2 din3 din4 channel1 analogue mute channel2 analogue mute channel3 analogue mute muteall din1 zflag4 channel3 analogue mute channel4 softmute
production data wm8768 w pd rev 4.3 july 2010 25 dmute and muteall the wm8768 can be directly muted using the dmute and dmute4 register bits to control which channels are muted. the mute happens as soon as the serial write is performed. register address bit label default description 0001001 dac mute 5:3 dmute [2:0] 000 dac 3,2 and 1 soft mute select 0001111 dac4 control 2 dmute4 0 dac 4 soft mute select {dmute4,dmute [2:0]} dac channel 4 dac channel 3 dac channel 2 dac channel 1 0000 not mute not mute not mute not mute 0001 not mute not mute not mute mute 0010 not mute not mute mute not mute 0011 not mute not mute mute mute 0100 not mute mute not mute not mute 0101 not mute mute not mute mute 0110 not mute mute mute not mute 0111 not mute mute mute mute 1000 mute not mute not mute not mute 1001 mute not mute not mute mute 1010 mute not mute mute not mute 1011 mute not mute mute mute 1100 mute mute not mute not mute 1101 mute mute not mute mute 1110 mute mute mute not mute 1111 mute mute mute mute table 10 dac mute control an overall mute to all channels can be applied by using the muteall register. register address bit label default description 0000010 dac mute 0 muteall 0 soft mute select: 0 : normal operation 1: soft mute all channels
wm8768 production data w pd rev 4.3 july 2010 26 mute pin as input the wm8768 can be muted externally by driving the mute pin high. when the mute pin is driven low the device will never automute, although direct mutes can still be applied via the dmute or muteall registers. the dzfm bits are used to decode the operation of a mute pin (decides which channels will be affected by the logic level present on the mute pin). mpd (mute pin decode) is used to enable the dzfm operation. if mpd is set, the selection made by the dzfm bits will be ignored and all channels will be muted when the pin is driven high. table 11 below describes which channels will be softmuted when the mute pin is driven high depending on the mpd and dzfm bits. mpd {dzfm4,dzfm [1:0]} channels muted when mute pin high 0 000 all channels 0 001 ch1 0 010 ch2 0 011 ch3 0 100 ch4 0 101 ch1 and ch2 0 110 ch1, ch2 and ch3 0 111 ch3 and ch4 1 000 all channels 1 001 all channels 1 010 all channels 1 011 all channels 1 100 all channels 1 101 all channels 1 110 all channels 1 111 all channels table 11 mute pin decode when mute pin as input
production data wm8768 w pd rev 4.3 july 2010 27 automute the wm8768 can automute by counting zero samples on the din1/2/3/4 inputs. when 1024 zero samples are counted on one channel, one of four internal zero flags (zflag1/2/3/4 shown in figure 2) is raised. depending on the external hardware and settings of dzfm, mpd and izd, different automute operations are possible. mute pin as output if the mute pin is connected to a high impedance (input to external mute circuitry for example) or left floating, zflag1/2/3/4 will be output on the mute pin dependent on dzfm settings. this is described in table 12 below. the output impedance of the mute pin is 10kohms {dzfm4,dzfm [1:0]} condition under which mute pin driven high 000 zflag1, 2, 3 and 4 all high 001 zflag1 high 010 zflag2 high 011 zflag3 high 100 zflag4 high 101 zflag1 and 2 high 110 zflag1, 2 and 3 high 111 zflag3 and 4 high table 12 effect of dzfm on mute pin output when the mute pin is used as an output, its logic level remains connected to the dzfm selector inside the chip (see figure 1). so, when the wm8768 drives the mute pin high, the output dacs will also softmute as described by table 13. mpd {dzfm4,dzfm [1:0]} channels muted when mute pin driven high 0 000 all channels 0 001 ch1 0 010 ch2 0 011 ch3 0 100 ch4 0 101 ch1 and ch2 0 110 ch1, ch2 and ch3 0 111 ch3 and ch4 1 000 all channels 1 001 all channels 1 010 all channels 1 011 all channels 1 100 all channels 1 101 all channels 1 110 all channels 1 111 all channels table 13 mute pin decode when mute pin as output
wm8768 production data w pd rev 4.3 july 2010 28 infinite zero detect when it is set, the izd register causes an analogue mute of the dac channel output amplifier both when there are 1024 zeros on that channel?s din pin or when it is manually muted by dmute or muteall. register address bit label default description 0000010 dac channel control 4 izd 0 izd enable 0 : disable infinite zero mute 1: enable infinite zero mute this operation is only available in software mode and can sometimes create a very small click at the output of the device. de-emphasis mode each stereo dac channel has an individual de-emphasis control bit: register address bit label default description 0001001 dac de-emphahsis control [8:6] deemph [2:0] 000 dac 3, 2 and 1 de-emphasis channel selection select: 0001111 dac4 control 4 deemph4 0 dac 4 de-emphasis channel selection select: {deemph4,deemph [2:0]} dac channel 4 dac channel 3 dac channel 2 dac channel 1 0000 not-deemph not-deemph not-deemph not-deemph 0001 not-deemph not-deemph not-deemph deemph 0010 not-deemph not-deemph deemph not-deemph 0011 not-deemph not-deemph deemph deemph 0100 not-deemph deemph not-deemph not-deemph 0101 not-deemph deemph not-deemph deemph 0110 not-deemph deemph deemph not-deemph 0111 not-deemph deemph deemph deemph 1000 deemph not-deemph not-deemph not-deemph 1001 deemph not-deemph not-deemph deemph 1010 deemph not-deemph deemph not-deemph 1011 deemph not-deemph deemph deemph 1100 deemph deemph not-deemph not-deemph 1101 deemph deemph not-deemph deemph 1110 deemph deemph deemph deemph 1111 deemph deemph deemph deemph table 14 de-emphasis control refer to figure 25, figure 26, figure 27, figure 28, figure 29 and figure 30 for details of the de- emphasis performance at different sample rates. register address bit label default description 0000010 dac deemph 1 deemp all 0 deemph select: 0 : normal operation 1: de-emphasis all channels
production data wm8768 w pd rev 4.3 july 2010 29 powerdown mode and dac disable setting the pdwn register bit immediately powers down the dacs on the wm8768, overriding the dacd powerdown bits control bits. all trace of the previous input samples is removed, but all control register settings are preserved. when pdwn is cleared the digital filters will be reinitialised register address bit label default description 0000010 powerdown control 2 pdwn 0 power down all dac?s select: 0: all dacs enabled 1: all dacs disabled the dacs may also be powered down individually by setting the dacpd disable bits. each stereo dac channel has a separate disable dacpd[2:0]. setting dacpd for a channel will disable the dacs and select a low power mode. register address bit label default description 0001010 powerdown control 3:1 dacd[2:0] 000 dac disable 0001111 dac4 control 1 dacd4 0 dac 4 powerdown {dacd4,dacd [2:0]} dac channel 4 dac channel 3 dac channel 2 dac channel 1 0000 active active active active 0001 active active active di sable 0010 active active disable active 0011 active active disable di sable 0100 active disable active active 0101 active disable active di sable 0110 active disable disable active 0111 active disable disable di sable 1000 di sable active active active 1001 di sable active active disable 1010 di sable active disable active 1011 di sable active disable disable 1100 di sable disable active active 1101 di sable disable active disable 1110 di sable disable disable active 1111 di sable disable disable disable table 15 dac disable control master powerdown control bit pwrdnall overrides the {dacd4,dacd[2:0]} bits and powers everything down including the reference vmid. it is recommended that the dacs are powered down first before setting this bit. register address bit label default description 0001010 interface control 4 pwrdnall 0 master power down bit 0: not powered down 1: powered down
wm8768 production data w pd rev 4.3 july 2010 30 master mode select control bit ms selects between audio interface master and slave modes. in master mode lrclk and bclk are outputs and are generated by the wm8768. in slave mode lrclk and bclk are inputs to wm8768. register address bit label default description 0001010 interface control 5 ms 0 audio interface master/slave mode select: 0: slave mode 1: master mode master mode lrclk frequency select in master mode the wm8768 generates lrc and bclk. these clo cks are derived from the master clock and the ratio of mclk to lrck is set by rate. register address bit label default description 0001010 interface control 8:6 rate[2:0] 010 master mode mclk: lrclk ratio select: 000: 128fs 001: 192fs 010: 256fs 011: 384fs 100: 512fs 101: 768fs mute pin decode the mute pin can either be used as an output or an input. when used as an input the mute pins action can be controlled by setting the dzfm and dzfm4 bit to select the corresponding dac for applying the mute to. as an output its meaning is selected by the dzfm and dzfm4 control bits. by default selecting the mute pin to represent if dac1 has received more than 1024 midrail samples will cause the mute pin to assert a softmute on dac1. disabling the decode block will cause any logical high on the mute pin to apply a softmute to all dac?s. for compatibility with the wm8772 register the mute pin decode bit is also found in the adc control register, which is redundant on this chip. the or of these two register bit is taken internally. register address bit label default description 0001100 adc control 6 mpd 0 mute pin decode disable: 0: mute pin decode enable 1: mute pin decode disable 0001111 dac4 control 5 mpd 0 mute pin decode disable: 0: mute pin decode enable 1: mute pin decode disable
production data wm8768 w pd rev 4.3 july 2010 31 dac digital volume control the dac volume may also be adjusted in the digital domain using independent digital attenuation control registers register address bit label default description 0000000 digital attenuation dacl1 7:0 lda1[7:0] 11111111 (0db) digital attenuation data for left channel dacl1 in 0.5db steps. see table 16 8 update not latched controls simultaneous update of all attenuation latches 0: store lda1 in intermediate latch (no change to output) 1: store lda1 and update attenuation on all channels 0000001 digital attenuation dacr1 7:0 rda1[6:0] 11111111 (0db) digital attenuation data for right channel dacr1 in 0.5db steps. see table 16 8 update not latched controls simultaneous update of all attenuation latches 0: store rda1 in intermediate latch (no change to output) 1: store rda1 and update attenuation on all channels. 0000100 digital attenuation dacl2 7:0 lda2[7:0] 11111111 (0db) digital attenuation data for left channel dacl2 in 0.5db steps. see table 16 8 update not latched controls simultaneous update of all attenuation latches 0: store lda2 in intermediate latch (no change to output) 1: store lda2 and update attenuation on all channels. 0000101 digital attenuation dacr2 7:0 rda2[7:0] 11111111 (0db) digital attenuation data for right channel dacr2 in 0.5db steps. see table 16 8 update not latched controls simultaneous update of all attenuation latches 0: store rda2 in intermediate latch (no change to output) 1: store rda2 and update attenuation on all channels. 0000110 digital attenuation dacl3 7:0 lda3[7:0] 11111111 (0db) digital attenuation data for left channel dacl3 in 0.5db steps. see table 16 8 update not latched controls simultaneous update of all attenuation latches 0: store lda3 in intermediate latch (no change to output) 1: store lda3 and update attenuation on all channels. 0000111 digital attenuation dacr3 7:0 rda3[7:0] 11111111 (0db) digital attenuation data for right channel dacr3 in 0.5db steps. see table 16 8 update not latched controls simultaneous update of all attenuation latches 0: store rda3 in intermediate latch (no change to output) 1: store rda3 and update attenuation on all channels. 0001101 digital attenuation dacl4 7:0 lda3[7:0] 11111111 (0db) digital attenuation data for left channel dacl4 in 0.5db steps. see table 16 8 update not latched controls simultaneous update of all attenuation latches 0: store lda4 in intermediate latch (no change to output) 1: store lda4 and update attenuation on all channels. 0001110 digital attenuation dacr4 7:0 rda3[7:0] 11111111 (0db) digital attenuation data for right channel dacr4 in 0.5db steps. see table 16 8 update not latched controls simultaneous update of all attenuation latches 0: store rda4 in intermediate latch (no change to output) 1: store rda4 and update attenuation on all channels. 0001000 master digital attenuation (all channels) 7:0 mastda [7:0] 11111111 (0db) digital attenuation data for all dac channels in 0.5db steps. see table 16 8 update not latched controls simultaneous update of all attenuation latches 0: store gain in intermediate latch (no change to output) 1: store gain and update attenuation on all channels.
wm8768 production data w pd rev 4.3 july 2010 32 note: when mclk is removed, digital volume settings are re-set to default (0db). when mclk is re-applied, the user must write the desired volume level to the volume control registers. l/rdax[7:0] attenuation level 00(hex) - db (mute) 01(hex) -127.5db : : : : : : fe(hex) -0.5db ff(hex) 0db table 16 digital volume control attenuation levels software register reset writing to register 11111 will cause a register reset, resetting all register bits to their default values. this reset will last either 2*mclk periods or until another write is made to the serial interface. register map the complete register map is shown below. the detailed description can be found in the relevant text of the device description. the wm8768 can be configured using the control interface. all unused bits should be set to ?0?. register b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 default r0(00h) 0 0 0 0 0 0 0 update lda1[7:0] 011111111 r1(01h) 0 0 0 0 0 0 1 update rda1[7:0] 011111111 r2(02h) 0 0 0 0 0 1 0 pl[8:5] izd atc pdwn all dac deemp all dac mute all dac 100100000 r3(03h) 0 0 0 0 0 1 1 phase[8:6] daciwl[5:4] dacbcp daclrp dacfmt[1:0] 000000000 r4(04h) 0 0 0 0 1 0 0 update lda2[7:0] 011111111 r5(05h) 0 0 0 0 1 0 1 update rda2[7:0] 011111111 r6(06h) 0 0 0 0 1 1 0 update lda3[7:0] 011111111 r7(07h) 0 0 0 0 1 1 1 update rda3[7:0] 011111111 r8(08h) 0 0 0 1 0 0 0 update mastda[7:0] 011111111 r9(09h) 0 0 0 1 0 0 1 deemp[8:6] dmute[5:3] dzfm[2:1] zcd 000000000 r10(0ah) 0 0 0 1 0 1 0 dacrate[8:6] dacms pwrdn all dacd[3:1] 0 010000000 r12(0ch) 0 0 0 1 1 0 0 0 0 mpd 0 0 0 0 0 0 000000000 r13(0dh) 0 0 0 1 1 0 1 update lda4[7:0] 011111111 r14(0eh) 0 0 0 1 1 1 0 update rda4[7:0] 011111111 r15(0fh) 0 0 0 1 1 1 1 0 0 0 mpd deemp 4 phase4 dmute 4 dzfm4 dacd4 000000000 r31(1fh) 0 0 1 1 1 1 1 reset 000000000
production data wm8768 w pd rev 4.3 july 2010 33 digital filter characteristics parameter test conditions min typ max unit dac filter passband 0.05 db 0.444fs -3db 0.487fs passband ripple 0.05 db stopband 0.555fs stopband attenuation f > 0.555fs -60 db group delay 21 fs table 17 digital filter characteristics dac filter responses -120 -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 response (db) frequency (fs) -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 response (db) frequency (fs) figure 21 dac digital filter frequency response ? 44.1, 48 and 96khz figure 22 dac digital filter ripple ?44.1, 48 and 96khz -80 -60 -40 -20 0 0 0.2 0.4 0.6 0.8 1 response (db) frequency (fs) -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 response (db) frequency (fs) figure 23 dac digital filter frequency response ? 192khz figure 24 dac digital filter ripple ? 192khz
wm8768 production data w pd rev 4.3 july 2010 34 digital de-emphasis characteristics -10 -8 -6 -4 -2 0 0 2 4 6 8 10 12 14 16 response (db) frequency (khz) -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 0 2 4 6 8 10 12 14 16 response (db) frequency (khz) figure 25 de-emphasis frequency response (32khz) figure 26 de-emphasis error (32khz) -10 -8 -6 -4 -2 0 0 5 10 15 20 response (db) frequency (khz) -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0 5 10 15 20 response (db) frequency (khz) figure 27 de-emphasis frequency response (44.1khz) figure 28 de-emphasis error (44.1khz) -10 -8 -6 -4 -2 0 0 5 10 15 20 response (db) frequency (khz) -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 5 10 15 20 response (db) frequency (khz) figure 29 de-emphasis frequency response (48khz) figure 30 de-emphasis error (48khz)
production data wm8768 w pd rev 4.3 july 2010 35 applications information recommended external components figure 31 recommended external component diagram recommended external components values component reference suggested value description c1 and c5 10 f de-coupling for dvdd and avdd. c2 to c4 0.1 f de-coupling for dvdd and avdd. c6 0.1 f reference de-coupling capacitors for vmid. c7 10 f c8 0.1 f de-coupling for testref1 c9 100 f filtering for vrefp. omit if avdd low noise. r1 33 filtering for vrefp. use 0 if avdd low noise. table 18 external components description
wm8768 production data w pd rev 4.3 july 2010 36 suggested analogue low pass post dac filters it is recommended that a lowpass filter be applied to the output from each dac channel for hi fi applications. typically a second order filter is suitable and provides sufficient attenuation of high frequency components (the unique low order, high bit count multi-bit sigma delta dac structure used in wm8768 produces much less high frequency output noise than normal sigma delta dacs. this filter is typically also used to provide the 2x gain needed to provide the standard 2vrms output level from most consumer equipment. figure 32 shows a suitable post dac filter circuit, with 2x gain. alternative inverting filter architectures might also be used with as good results. 7.5k 1.8k 10uf 1.0nf 47k 4.7k 680pf 4.7k 51 op_fil vout1l op_fil vout1r op_fil vout2r op_fil vout2l op_fil vout3l op_fil vout3r op_fil vout4l op_fil vout4r figure 32 recommended post dac filter circuit
production data wm8768 w pd rev 4.3 july 2010 37 package drawing notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0.20mm. d. meets jedec.95 mo-150, variation = ah. refer to this specification for further details. dm007.e ds: 28 pin ssop (10.2 x 5.3 x 1.75 mm) symbols dimensions (mm) min nom max a ----- ----- 2.0 a 1 0.05 ----- 0.25 a 2 1.65 1.75 1.85 b 0.22 0.30 0.38 c 0.09 ----- 0.25 d 9.90 10.20 10.50 e e 7.40 7.80 8.20 5.00 5.30 5.60 l 0.55 0.75 0.95 a a2 a1 14 1 15 28 e1 e c l gauge plane 0.25 e b d seating plane -c- 0.10 c ref: jedec.95, mo-150 e 1 l 1 1.25 ref 0.65 bsc l 1 0 o 4 o 8 o
wm8768 production data w pd rev 4.3 july 2010 38 important notice wolfson microelectronics plc (?wolfson?) products and services are sold subject to wolfson?s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. wolfson warrants performance of its products to the specifications in effect at the date of shipment. wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. customers should therefore obtain the latest version of relevant information from wolfson to verify that the information is current. testing and other quality control techniques are utilised to the extent wolfson deems necessary to support its warranty. specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. in order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. wolfson is not liable for applications assistance or customer product design. the customer is solely responsible for its selection and use of wolfson products. wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a wolfson product. wolfson?s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. any use of products by the customer for such purposes is at the customer?s own risk. wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. any provision or publication of any third party?s products or services does not constitute wolfson?s approval, licence, warranty or endorsement thereof. any third party trade marks contained in this document belong to the respective third party owner. reproduction of information from wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon. any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in wolfson?s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person?s own risk. wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. address: wolfson microelectronics plc westfield house 26 westfield road edinburgh eh11 2qb united kingdom tel :: +44 (0)131 272 7000 fax :: +44 (0)131 272 7001 email :: sales@wolfsonmicro.com

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