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| d a t a sh eet product speci?cation supersedes data of 1998 sep 07 file under integrated circuits, ic02 2000 may 03 integrated circuits SAA6750h encoder for mpeg2 image recording (empire)
2000 may 03 2 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h contents 1 features 2 general description 2.1 general 2.2 function 2.3 application fields 2.3.1 general 2.3.2 video editing (pc applications) 2.3.3 camera signal transmission 2.3.4 video recording for surveillance 2.3.5 digital vcr 3 quick reference data 4 ordering information 5 block diagram 6 pinning 7 functional description 7.1 global architecture description 7.1.1 general 7.1.2 architecture structure 7.2 start-up and operating modes 7.2.1 start-up requirements 7.2.2 reset processing 7.2.3 description of operating modes 7.2.4 pin behaviour 7.3 video front-end and formatter 7.3.1 general 7.3.2 data input format 7.3.3 functional description 7.4 macroblock processor 7.4.1 general 7.4.2 functional description 7.5 bitstream assembly 7.5.1 general 7.5.2 pre-packer and packer 7.6 data output port 7.6.1 general 7.6.2 data output format 7.6.3 functional description 7.7 application specific instruction-set processor (asip) 7.7.1 general 7.8 global controller 7.8.1 general 7.9 i 2 c-bus interface and controller 7.9.1 general 7.9.2 special considerations 7.9.3 i 2 c-bus data transfer modes 7.9.4 i 2 c-bus memories and registers 7.9.5 i 2 c-bus initialization 7.10 dram interface 7.10.1 general 7.10.2 application hints 7.10.3 functional description 7.11 fifo memories 7.12 clock distribution 7.13 input/output levels 7.14 boundary scan test 7.14.1 general 7.14.2 initialization of boundary scan circuit 7.14.3 device identification codes 8 limiting values 9 thermal characteristics 10 characteristics 11 application information 12 package outline 13 soldering 13.1 introduction to soldering surface mount packages 13.2 reflow soldering 13.3 wave soldering 13.4 manual soldering 13.5 suitability of surface mount ic packages for wave and reflow soldering methods 14 data sheet status 15 definitions 16 disclaimers 17 purchase of philips i2c components 2000 may 03 3 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h 1 features digital yuv input according to itu-t 601 and itu-t 656 ntsc and pal (720 pixels 480 lines at 60 hz and 720 pixels 576 lines at 50 hz) integrated colour conversion 4 :2:2to4:2:0 integrated format conversion to sif format (optional) real time mpeg2 simple profile at main level (sp@ml) encoding ip frame or i frame only encoding supported programmable group of pictures (gop) size integrated motion estimation, half pixel accuracy motion compensated noise reduction elementary stream data output compliant to mpeg2 standard ( iso 13818-2 ) bitstream output compatible to 16-bit parallel interface with motorola (68xxx like) protocol style no external host processor required 4 4 mbit external dram required i 2 c-bus controlled single external video clock 27 mhz power supply voltage 3.3 v digital inputs 5 v tolerant boundary scan test (bst) supported. 2 general description 2.1 general the SAA6750h is a new approach towards a stand-alone mpeg2 video encoder ic. it combines high quality sp@ml compliant real time encoding with cost-effectiveness, allowing for the first time the use of an mpeg2 encoder ic in applications and markets with a high cost pressure. this has been achieved by means of a number of innovations in architecture and algorithms developed by the philips research laboratories, e.g.: the unique motion estimation algorithm supports highly efficient encoding by using only i frame and ip frame mode. b frames need not be used. this leads to a significantly smaller internal circuitry and also reduces dram memory requirements from at least 4 to 2 mbyte. in addition, the absence of b frames simplifies editing of the compressed data stream. the patented, motion-compensated temporal noise filtering which was developed by philips for professional equipment reduces noise in the input video before compression is performed. this technique gives visible improvements in picture quality, especially in the field of home recordings with noisy signal sources where this has proved to be of significant benefit. internally the SAA6750h uses a hardware solution for data compression and a specially developed high performance processor for control purposes. 2.2 function the SAA6750h is a stand-alone single chip video encoder performing real time mpeg2 compression of digital video data. the video data input of the SAA6750h accepts a digital yuv video data stream in itu-t 601 format. pal standard at 50 hz and 720 pixels by 576 lines, as well as ntsc at 60 hz and 720 pixels by 480 lines, are covered. the video synchronization may either follow itu-t 656 recommendation or can also be supplied by external signals. the external reference clock of 27 mhz to pin vclk has to be synchronized to the video data. the product family saa7111 of philips semiconductors provides a suitable video data stream and reference clock. other sources are also supported by the flexible i 2 c-bus controlled data input interface of the SAA6750h. see section 7.3 for detailed information. an internal 4:2:2to4:2:0 colour format conversion is performed. optionally, a itu-t 601 to sif format conversion may be activated by the i 2 c-bus control settings. the real time data encoding part of the SAA6750h combines high-compression rates with high quality picture performance. this is achieved by the integration of philips unique motion estimation algorithm and a patented motion-compensated noise filtering. the compression algorithm uses i or ip mode encoding. normally it selects automatically the suitable mode but may also be forced to i mode operating only by the i 2 c-bus control settings. 2000 may 03 4 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h in contrast to the encoding part which is designed in dedicated hardware, control functions and data stream handling tasks such as e.g. header generation and bit-rate control are carried out by a dedicated control processor, the so-called application specific instruction-set processor (asip). the asips microcode is contained in an internal ram and is loaded via the i 2 c-bus before start of operation. the asip is able to communicate with the outside world via the i 2 c-bus. the SAA6750h generates an mpeg2 elementary stream (es) in accordance with the mpeg2 standard ( iso 13818-2 ). the 16-bit data output interface supports motorola (68xxx like) protocol style. data processing and control functions are managed by loosely coupled processes. fifo memories are used to connect these processes. in addition to these internal storages the SAA6750h needs 4 4 mbit of external dram memory (t rac = 60 ns). a block diagram is shown in fig.1. selectable i 2 c-bus addresses and a special reset mode affecting the output pin behaviour allow the use of two SAA6750h devices in one application. 2.3 application ?elds 2.3.1 g eneral the SAA6750h can be applied within the following application domains: video editing (pc applications) camera signal transmission digital versatile disc (dvd) recording video recording for surveillance digital vcr. all those systems have to compress video data in order to manage the storage or transmission of digitized video data. the SAA6750h can be handled for most of the applications as a stand-alone device. that means at start-up a microcode and a couple of the i 2 c-bus settings are loaded and the SAA6750h is started. if needed, settings such as gop size or bit-rate are changed on-the-fly via the i 2 c-bus. 2.3.2 v ideo editing (pc applications ) for video editing the SAA6750h can be interfaced gluelessly to a video input processor with itu-t 656 compliant digital video output. in order to link the SAA6750h to the pc, the use of the pci bridge saa7146 is recommended. by this bridge the mpeg2 video es can be transmitted via the pci-bus to a harddisc (hd). furthermore all the i 2 c-bus settings can be send from the pc via the bridge to the i 2 c-bus components on the encoder board. the saa7146 supports pulse code modulation (pcm) audio capturing. multiplexing with an audio stream or audio encoding can be done by the cpu of the pc. a block diagram is shown in fig.18. 2.3.3 c amera signal transmission in this application the SAA6750h will be located inside a camera to compress the received digital video data for transmission. 2.3.4 v ideo recording for surveillance for surveillance systems vcrs with a huge amount of storage capacity are required. a high picture resolution is very important when there is action in the captured picture. the SAA6750h can control the encoded bit-rate by motion detection by its integrated motion estimation algorithm. doing so the bit-rate can vary from 0.5 to 10 mbit/s. vcrs with a storage space of 6 month are possible. 2.3.5 d igital vcr in stand-alone vcrs the SAA6750h works together with an audio encoder and a multiplexer. the SAA6750h is clocked by the video clock of the video input processor (saa7111 or derivatives). a master clock is derived from the frame pulse. the video clock and master clock domain are de-coupled by a fifo. the audio clock can be derived from the master clock. the video packetized elementary stream (pes) packetizer has to take care of the fullness of the output buffer of the SAA6750h. 2000 may 03 5 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h 3 quick reference data 4 ordering information symbol parameter min. typ. max. unit v dd digital supply voltage 3.0 3.3 3.6 v i dd(tot) total digital supply current - 0.22 0.56 a p tot total power dissipation - 0.73 2.0 w f vclk video clock frequency 25.6 27.0 28.6 mhz f scl i 2 c-bus clock frequency 100 - 400 khz b output bit-rate 1.5 - 40 mbit/s v ih high-level input voltage 2.0 - 5.5 v v il low-level input voltage - 0.5 - +0.8 v v oh high-level output voltage 2.4 - v dd v v ol low-level output voltage -- 0.4 v t amb ambient temperature 0 - 70 c type number package name description version SAA6750h sqfp208 plastic shrink quad ?at package; 208 leads (lead length 1.3 mm); body 28 28 3.4 mm; high stand-off height sot316-1 2000 may 03 6 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 5 block diagram mhb661 an dbook, full pagewidth 64 52 to 49, 47 to 44, 42 to 39, 37 to 34, 32 to 29, 20 to 17, 15 to 12, 10 to 7, 5 to 2, 208 to 205, 203 to 200, 198 to 195, 193 to 190, 188 to 185, 175 to 172, 170 to 167 9 64, 62 to 59, 57 to 54 69 1.8 k w 1.8 k w dram interface test control block for boundary scan test and scan test 101 mem_st 125 csn ad15 to ad0 yuv7 to yuv0 16 124 138 to 141, 143 to 146, 148 to 151, 153 to 156 gpio11 to gpio2 10 8 119 to 116, 114 to 111, 109, 108 i_mn data63 to data0 adr8 to adr0 oen i 2 c-bus transceiver 97 start mad global controller SAA6750h line based processing 91 vsync 90 hsync 89 87 to 84, 74 to 71 fid 98 sda clock generation 93 vclk (27 mhz) 27 mhz 96 resetn 99 scl macroblock based processing bitstream based processing data output port asip test 123 dtack_rdy 158 165 v ss 1, 11, 21, 33, 43, 53, 63, 70, 92, 95, 105, 115, 137, 147, 157, 171, 189, 199 cs_test 164 tdi 163 n.c. 184 tms 161 tck 160 trst 159 tdo 121 lrqn 122 urqn 135 as_ale 136 ds_rdn 106 gpio0 107 gpio1 68 wen 67 rasn 65 casn 16 22, 24, 26, 76, 78, 80, 82, 126, 128, 130, 132, 134, 162, 178, 180, 182 + 3.3 v v ddco 18 18 6, 16, 28, 38, 48, 58, 66, 88, 94, 100, 110, 120, 142, 152, 166, 176, 194, 204 + 3.3 v v dd v ss 103 fad_en fad_rdyn 102 fad_rwn v ss v dd 1.8 k w 104 v dd v dd v ssco 23, 25, 27, 75, 77, 79, 81, 83, 127, 129, 131, 133, 177, 179, 181, 183 16 fig.1 block diagram. 2000 may 03 7 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h 6 pinning symbol pin input/output (1) i max (ma) description v ss 1 ground - ground for pad ring data28 2 input/output 3 dram data interface bit 28 data29 3 input/output 3 dram data interface bit 29 data30 4 input/output 3 dram data interface bit 30 data31 5 input/output 3 dram data interface bit 31 v dd 6 supply - supply voltage for pad ring data32 7 input/output 3 dram data interface bit 32 data33 8 input/output 3 dram data interface bit 33 data34 9 input/output 3 dram data interface bit 34 data35 10 input/output 3 dram data interface bit 35 v ss 11 ground - ground for pad ring data36 12 input/output 3 dram data interface bit 36 data37 13 input/output 3 dram data interface bit 37 data38 14 input/output 3 dram data interface bit 38 data39 15 input/output 3 dram data interface bit 39 v dd 16 supply - supply voltage for pad ring data40 17 input/output 3 dram data interface bit 40 data41 18 input/output 3 dram data interface bit 41 data42 19 input/output 3 dram data interface bit 42 data43 20 input/output 3 dram data interface bit 43 v ss 21 ground - ground for pad ring v ddco 22 supply - supply voltage for core logic v ssco 23 ground - ground for core logic v ddco 24 supply - supply voltage for core logic v ssco 25 ground - ground for core logic v ddco 26 supply - supply voltage for core logic v ssco 27 ground - ground for core logic v dd 28 supply - supply voltage for pad ring data44 29 input/output 3 dram data interface bit 44 data45 30 input/output 3 dram data interface bit 45 data46 31 input/output 3 dram data interface bit 46 data47 32 input/output 3 dram data interface bit 47 v ss 33 ground - ground for pad ring data48 34 input/output 3 dram data interface bit 48 data49 35 input/output 3 dram data interface bit 49 data50 36 input/output 3 dram data interface bit 50 data51 37 input/output 3 dram data interface bit 51 v dd 38 supply - supply voltage for pad ring data52 39 input/output 3 dram data interface bit 52 2000 may 03 8 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h data53 40 input/output 3 dram data interface bit 53 data54 41 input/output 3 dram data interface bit 54 data55 42 input/output 3 dram data interface bit 55 v ss 43 ground - ground for pad ring data56 44 input/output 3 dram data interface bit 56 data57 45 input/output 3 dram data interface bit 57 data58 46 input/output 3 dram data interface bit 58 data59 47 input/output 3 dram data interface bit 59 v dd 48 supply - supply voltage for pad ring data60 49 input/output 3 dram data interface bit 60 data61 50 input/output 3 dram data interface bit 61 data62 51 input/output 3 dram data interface bit 62 data63 52 input/output 3 dram data interface bit 63 (msb) v ss 53 ground - ground for pad ring adr0 54 output/3-state 3 dram address interface bit 0 (lsb) adr1 55 output/3-state 3 dram address interface bit 1 adr2 56 output/3-state 3 dram address interface bit 2 adr3 57 output/3-state 3 dram address interface bit 3 v dd 58 supply - supply voltage for pad ring adr4 59 output/3-state 3 dram address interface bit 4 adr5 60 output/3-state 3 dram address interface bit 5 adr6 61 output/3-state 3 dram address interface bit 6 adr7 62 output/3-state 3 dram address interface bit 7 v ss 63 ground - ground for pad ring adr8 64 output/3-state 3 dram address interface bit 8 (msb) casn 65 output/3-state 6 dram column address strobe (active low) v dd 66 supply - supply voltage for pad ring rasn 67 output/3-state 3 dram row address strobe (active low) wen 68 output/3-state 3 dram write enable (active low) oen 69 output/3-state 3 dram chip select (active low) v ss 70 ground - ground for pad ring yuv0 71 input - video input signal bit 0 (lsb) yuv1 72 input - video input signal bit 1 yuv2 73 input - video input signal bit 2 yuv3 74 input - video input signal bit 3 v ssco 75 ground - ground for core logic v ddco 76 supply - supply voltage for core logic v ssco 77 ground - ground for core logic v ddco 78 supply - supply voltage for core logic v ssco 79 ground - ground for core logic symbol pin input/output (1) i max (ma) description 2000 may 03 9 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h v ddco 80 supply - supply voltage for core logic v ssco 81 ground - ground for core logic v ddco 82 supply - supply voltage for core logic v ssco 83 ground - ground for core logic yuv4 84 input - video input signal bit 4 yuv5 85 input - video input signal bit 5 yuv6 86 input - video input signal bit 6 yuv7 87 input - video input signal bit 7 (msb) v dd 88 supply - supply voltage for pad ring fid 89 input - odd/even ?eld identi?cation hsync 90 input - horizontal reference signal vsync 91 input - vertical reference signal v ss 92 ground - ground for pad ring vclk 93 input - video clock input (27 mhz) v dd 94 supply - supply voltage for pad ring v ss 95 ground - ground for pad ring resetn 96 input - hard reset input (active low) mad 97 input - module address (i 2 c-bus) sda 98 input/open-drain output 6 serial data input/output (i 2 c-bus) scl 99 input/open-drain output - serial clock input (i 2 c-bus) v dd 100 supply - supply voltage for pad ring mem_st 101 output/3-state 3 do not use in the application (reserved) fad_rwn 102 input - asip port data read/ wr ite fad_en 103 input - asip port data enable fad_rdyn 104 open-drain output 3 asip port data ready (active low) v ss 105 ground - ground for pad ring gpio0 106 input/output 3 asip port data bit 0 (lsb) gpio1 107 input/output 3 asip port data bit 1 gpio2 108 input/output 3 asip port data bit 2; note 2 gpio3 109 input/output 3 asip port data bit 3; note 2 v dd 110 supply - supply voltage for pad ring gpio4 111 input/output 3 asip port data bit 4; note 2 gpio5 112 input/output 3 asip port data bit 5; note 2 gpio6 113 input/output 3 asip port data bit 6; note 2 gpio7 114 input/output 3 asip port data bit 7; note 2 v ss 115 ground - ground for pad ring gpio8 116 input/output 3 asip port data bit 8; note 2 gpio9 117 input/output 3 asip port data bit 9; note 2 gpio10 118 input/output 3 asip port data bit 10; note 2 gpio11 119 input/output 3 asip port data bit 11 (msb); note 2 symbol pin input/output (1) i max (ma) description 2000 may 03 10 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h v dd 120 supply - supply voltage for pad ring lrqn 121 open-drain output 3 output port lower watermark interrupt request (active low) urqn 122 open-drain output 3 output port upper watermark interrupt request (active low) dtack_rdy 123 open-drain output 3 output port data transfer acknowledge/ready/request i_mn 124 input - output port reserved mode/motorola bus style selection input (active low); with internal pull-up resistor csn 125 input - output port chip select for external address mode (active low); with internal pull-up resistor v ddco 126 supply - supply voltage for core logic v ssco 127 ground - ground for core logic v ddco 128 supply - supply voltage for core logic v ssco 129 ground - ground for core logic v ddco 130 supply - supply voltage for core logic v ssco 131 ground - ground for core logic v ddco 132 supply - supply voltage for core logic v ssco 133 ground - ground for core logic v ddco 134 supply - supply voltage for core logic as_ale 135 input - output port address strobe/address latch enable ds_rdn 136 input - output port data strobe/ read v ss 137 ground - ground for pad ring ad15 138 input/output 3 output port multiplexed address/data line bit 15 (msb) ad14 139 input/output 3 output port multiplexed address/data line bit 14 ad13 140 input/output 3 output port multiplexed address/data line bit 13 ad12 141 input/output 3 output port multiplexed address/data line bit 12 v dd 142 supply - supply voltage for pad ring ad11 143 input/output 3 output port multiplexed address/data line bit 11 ad10 144 input/output 3 output port multiplexed address/data line bit 10 ad9 145 input/output 3 output port multiplexed address/data line bit 9 ad8 146 input/output 3 output port multiplexed address/data line bit 8 v ss 147 ground - ground for pad ring ad7 148 input/output 3 output port multiplexed address/data line bit 7/data bus bit 7 (msb) ad6 149 input/output 3 output port multiplexed address/data line bit 6/data bus bit 6 ad5 150 input/output 3 output port multiplexed address/data line bit 5/data bus bit 5 ad4 151 input/output 3 output port multiplexed address/data line bit 4/data bus bit 4 v dd 152 supply - supply voltage for pad ring ad3 153 input/output 3 output port multiplexed address/data line bit 3/data bus bit 3 ad2 154 input/output 3 output port multiplexed address/data line bit 2/data bus bit 2 ad1 155 input/output 3 output port multiplexed address/data line bit 1/data bus bit 1 ad0 156 input/output 3 output port multiplexed address/data line bit 0 (lsb)/data bus bit 0 (lsb) symbol pin input/output (1) i max (ma) description 2000 may 03 11 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h v ss 157 ground - ground for pad ring tdo 158 output 3 boundary scan test data output; pin not active during normal operating; with 3-state output; note 3 trst 159 input - boundary scan test reset; pin must be set to low for normal operating; with internal pull-up resistor; notes 3 and 4 tck 160 input - boundary scan test clock; pin must be set to low during normal operating; with internal pull-up resistor; note 3 tms 161 input - boundary scan test mode select; pin must ?oat or set to high during normal operating; with internal pull-up resistor; note 3 v ddco 162 supply - supply voltage for core logic tdi 163 input - boundary scan test data input; pin must ?oat or set to high during normal operating; with internal pull-up resistor; note 3 cs_test 164 input - test mode for the internal rams; pin must be set to low during normal operating test 165 input - test mode; pin must be set to low during normal operating v dd 166 supply - supply voltage for pad ring data0 167 input/output 3 dram data interface bit 0 (lsb) data1 168 input/output 3 dram data interface bit 1 data2 169 input/output 3 dram data interface bit 2 data3 170 input/output 3 dram data interface bit 3 v ss 171 ground - ground for pad ring data4 172 input/output 3 dram data interface bit 4 data5 173 input/output 3 dram data interface bit 5 data6 174 input/output 3 dram data interface bit 6 data7 175 input/output 3 dram data interface bit 7 v dd 176 supply - supply voltage for pad ring v ssco 177 ground - ground for core logic v ddco 178 supply - supply voltage for core logic v ssco 179 ground - ground for core logic v ddco 180 supply - supply voltage for core logic v ssco 181 ground - ground for core logic v ddco 182 supply - supply voltage for core logic v ssco 183 ground - ground for core logic n.c. 184 -- reserved pin; do not connect data8 185 input/output 3 dram data interface bit 8 data9 186 input/output 3 dram data interface bit 9 data10 187 input/output 3 dram data interface bit 10 data11 188 input/output 3 dram data interface bit 11 v ss 189 ground - ground for pad ring data12 190 input/output 3 dram data interface bit 12 data13 191 input/output 3 dram data interface bit 13 symbol pin input/output (1) i max (ma) description 2000 may 03 12 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h notes 1. all input pins, input/output pins (in input mode), output pins (in 3-state mode) and open-drain output pins are 5.0 v tolerant. 2. this pin is recommended to be set to ground or to the supply voltage v dd via a resistor. 3. in accordance with the ieee 1149.1 standard. 4. special function of pin trst: a) for board designs without boundary scan implementation, pin trst must be connected to ground. b) pin trst provides easy initialization of the internal bst circuit. by applying a low it can be used to force the internal test access port (tap) controller to the test-logic-reset state (normal operating) at once. data14 192 input/output 3 dram data interface bit 14 data15 193 input/output 3 dram data interface bit 15 v dd 194 supply - supply voltage for pad ring data16 195 input/output 3 dram data interface bit 16 data17 196 input/output 3 dram data interface bit 17 data18 197 input/output 3 dram data interface bit 18 data19 198 input/output 3 dram data interface bit 19 v ss 199 ground - ground for pad ring data20 200 input/output 3 dram data interface bit 20 data21 201 input/output 3 dram data interface bit 21 data22 202 input/output 3 dram data interface bit 22 data23 203 input/output 3 dram data interface bit 23 v dd 204 supply - supply voltage for pad ring data24 205 input/output 3 dram data interface bit 24 data25 206 input/output 3 dram data interface bit 25 data26 207 input/output 3 dram data interface bit 26 data27 208 input/output 3 dram data interface bit 27 symbol pin input/output (1) i max (ma) description the 208 pins are divided in following groups: video input port (11 pins): 8 data pins and 3 control pins. data output port (23 pins): 16 data pins and 7 control pins. gpio port (15 pins): 12 data pins and 3 control pins. dram (77 pins): 64 data pins 9 address pins 4 control pins. others (14 pins): 1 video clock input pin 3 pins related to the i 2 c-bus 1 pin for reset control 7 pins for test purposes 1 pin not connected 1 pin for internal test purposes. supply (68 pins): 16 core supply pins 18 i/o cell supply pins 16 core ground pins 18 i/o cell ground pins. 2000 may 03 13 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h fig.2 pin configuration. handbook, halfpage SAA6750h 1 208 157 53 104 52 156 105 mbk768 7 functional description 7.1 global architecture description 7.1.1 g eneral the SAA6750h has a multi-processor architecture. the different processing and control modules are not locked to each other but run independently within the limits of the global scheduling. the data transfer between the processing units is carried out via fifo memories or the external dram (see fig.1). the set of functions of the SAA6750h is determined to a high extent by the microcode of the internal application specific instruction-set processor (asip). detailed information is given in the software specification. global settings and selection of the operating modes are carried out via the i 2 c-bus (see sections 7.2 and 7.9). 7.1.2 a rchitecture structure the architecture consist of a data processing, a control and a memory part. 7.1.2.1 data processing part the data processing flow can be split-up as follows: line based processing: video front-end and formatter (see section 7.3) including: 1. 4:2:2to4:2:0 pre-filter 2. optional sif subsampling. the video front-end processes the incoming video data and writes it to the external dram. macroblock based processing: macroblock processor (mbp) (see section 7.4) including: 1. discrete cosine transformation/inverse discrete cosine transformation (dct/idct) 2. variable length encoding/run length encoding (vle/rle) 3. motion estimation/motion compensation (me/mc) 4. motion compensation noise reduction (mcnr) 5. quantization/inverse quantization (q/iq) 6. frame/field (ff) reshuffling and zigzag (zz) scan. the mbp gets the pre-processed video data from the external dram and performs the data compression. 2000 may 03 14 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h bitstream based processing: bitstream assembly (see section 7.5) (pre-packer, packer, stuffing unit and output buffer) and data output port (see section 7.6). the bitstream processing part gets the compressed data from the mbp and the header information from the control part. it provides an mpeg2 compliant elementary stream (es) at the output. 7.1.2.2 control part the control part consists of three modules: 1. application specific instruction-set processor (asip) (see section 7.7): controls the mbp, generates motion vectors, headers and stuffing information 2. the global controller (see section 7.8): generates the global scheduling information for the mbp, the dram interface and the asip 3. the i 2 c-bus interface and controller (see section 7.9): download of asip microcode, tables and constants as well as mbp quantizer table, used for external control settings, allows communication between asip and application environment. 7.1.2.3 memory part the control and data processing modules exchange data via internal fifos and the external dram: 1. dram interface (see section 7.10); provides access to the external dram memory 2. fifo memories (see section 7.11); a number of fifos of different size is used to connect internal processing units. 7.2 start-up and operating modes 7.2.1 s ta rt - up requirements simultaneously with power-on, the SAA6750h requires a low level at pin resetn. this external reset has to be kept active until the external video clock signal vclk has been running stable within the specified limits for at least 10 clock cycles (see chapter quick reference data). a suitable combination of resetn and clock signal is e.g. provided by philips product family saa7111a. for proper reset behaviour and operation pin trst has to be low. after power-on and the related internal reset the initialization via the i 2 c-bus has to be carried out (see section 7.9.5). it should be noted that a delay of at least 0.5 ms between the end of resetn low state and start of the i 2 c-bus initialization sequence is required. see table 1 for information about the operating modes. 7.2.2 r eset processing the SAA6750h has internally an asynchronous and a synchronous reset processing. the asynchronous reset is directly derived from the external reset signal resetn and gets active as soon as resetn becomes low. it is not depending on the external clock signal. the asynchronous reset forces the SAA6750h into reset mode which does directly affect the behaviour of the output and i/o pins (see table 2). this does guarantee a defined state of the pins even if no clock signal is available. in addition it initiates the internal synchronous reset which gets active as soon as the vclk signal is available. the internal synchronous reset is controlled by resetn and the settings of control bits e_st and e_sp. for proper operating the external clock signal vclk has to be stable within the specified limits. the internal synchronous reset gets active if resetn is low or by setting the control bits e_st and e_sp to soft reset mode (see table 1). it does affect all internal modules except the i 2 c-bus controller and therefore also the output and i/o pins (see table 2). in addition, but only if combined with an external reset resetn, it does reset the i 2 c-bus control register. it does not affect the contents of the embedded microcode and constant memories (see section 7.9.4). see table 2 for detailed information about the impact of external and internal reset signals as well as control bit settings on the behaviour of internal modules and output pins. after release of the external reset or setting back bits e_st and e_sp to operating mode, the internal synchronous reset remains active for 7562 clock cycles (approximately 260 m s). during this time the dram initialization sequence is carried out (see section 7.10.3.2). all other internal modules except the i 2 c-bus control register stay in reset mode for this time. the external dram will not be refreshed during internal synchronous reset. 2000 may 03 15 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h 7.2.3 d escription of operating modes depending on the reset processing and the setting of the i 2 c-bus control bits e_st and e_sp (see tables 22 and 23) the SAA6750h can be set to different operating modes. purpose and behaviour are described in table 1. after an external reset pulse at resetn, the init mode will be active because control bits e_st and e_sp are set to low. 7.2.4 p in behaviour the behaviour of i/o and output pins is depending on the operation mode of the SAA6750h. in reset mode the pins are forced to a certain behaviour even if no clock vclk is available. reset mode overrules all other internal pin settings. during soft reset mode all output and i/o pins that could create driver conflicts with other devices are forced to 3-state or input mode. the internal reset is active during a period of 7562 clock cycles after reset mode and soft reset mode. the status of pins is determined by the reset behaviour of the internal modules. the internal reset behaviour applies also for the init mode because init mode always follows internal reset. in operation mode the status of the pins is depending on the function of the SAA6750h. table 1 SAA6750h operating modes mode activated by description resetn e_st e_sp reset mode 0 x x in reset mode all i/o and output pins are forced to a de?ned state with resetn = low (refer to table 2). after vclk is available, also the internal reset becomes active, which puts the internal modules in reset state. the i 2 c-bus control register is cleared in this mode. after setting resetn back to high, the internal reset will remain active for 7562 clock cycles. the dram initialization sequence will run during this time (see section 7.10.3.2). init mode 1 0 0 in init mode the device initialization via the i 2 c-bus has to be performed. the external dram is not refreshed. see table 2 for behaviour of pins during init mode. this mode will be active after external reset due to reset of e_st and e_sp. remark: do not switch from operating mode to init mode directly. always use the soft reset or reset mode as intermediate step. soft reset mode 1 0 1 activates the internal synchronous reset. all internal modules except the i 2 c-bus control register are in reset mode. this mode allows e.g. operation of a second device SAA6750h. therefore output and i/o pins are in input or 3-state mode (see table 2). the external dram will not be refreshed. after setting e_sp back to low, the internal reset will remain active for 7562 clock cycles. the dram initialization sequence will run during this time (see section 7.10.3.2). operating mode 1 1 0 normal operating. - 1 1 1 internal use only. 2000 may 03 16 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h table 2 behaviour of output and i/o pins note 1. only defined if external clock is available. pin name description pin status reset mode init mode and internal reset soft reset mode data0 to data63 dram data input/output input input input adr0 to adr8 dram address output 3-state output 3-state casn dram column address strobe output 3-state output 3-state rasn dram row address strobe output 3-state output 3-state wen dram write enable output 3-state output 3-state oen dram chip select output 3-state output 3-state sda i 2 c-bus data input/open-drain output input normal operating normal operating scl i 2 c-bus clock input/output input normal operating normal operating mem_st reserved output 3-state output 3-state fad_rdyn asip data port; data ready output open-drain; note 1 open-drain open-drain gpio0 to gpio11 asip data port; input/output input input input lrqn output port lower watermark interrupt request open-drain on open-drain urqn output port upper watermark interrupt request open-drain on open-drain dtack_rdy output port data transfer acknowledge/ready/request open-drain on open-drain ad0 to ad15 output port address/data input/output input input input 7.3 video front-end and formatter 7.3.1 g eneral the video front-end and formatter module consists of an 8-bit data input interface, a formatter sub-module and a luminance and a chrominance address processing unit. the interface is designed for use with philips saa7111 video decoder family or similar products. the input interface accepts a digital video input stream according to itu-t 601 . pal standard at 50 hz and 720 pixels by 576 lines as well as ntsc at 60 hz and 720 pixels by 480 lines are covered. the video synchronization may either follow itu-t 656 recommendation or can also be supplied by external signals (hsync, vsync and fid). the formatter module performs a colour conversion from 4:2:2to4:2:0 format. optionally, also an sif down-scaling may be activated for pal as well as ntsc standard signals. the luminance and chrominance processing units do generate the addresses for storing the front-end output data in the external dram memory. 7.3.2 d ata input format the 8-bit video input data has to be transferred at a rate of 27 mwords/s (13.5 mhz for luminance and 6.25 mhz for both chrominance components) i.e. one data word per clock cycle has to be sent. the elements of a data stream have the following order: c b ,y,c r ,y,c b ,y,c r , y, etc. the byte combinations 00h and ffh are reserved for synchronization purposes, so that only a subset of 254 of all possible 2 8 = 256 combinations are used. see section 7.3.3 for detailed information about the synchronization signals. the external reference clock vclk has to be synchronized to the video input data. 2000 may 03 17 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h 7.3.3 f unctional description 7.3.3.1 general the video front-end and formatter module consists of four submodules: 1. the 8-bit data interface and the related control signals connect the SAA6750h to external data sources such as e.g. philips saa711x product family 2. the formatter submodule covers two main functions: the processing of the synchronization information (sync processing) and the processing of the picture contents (line based processing) 3. the luminance and chrominance submodules generate the addresses in the external dram memory where the output data of the video front-end and formatter module is stored. the video front-end and formatter module offers various operating modes. the appropriate setting can be selected in the i 2 c-bus control register (see tables 3 and 22). it should be noted that changes of video standard or synchronization settings are only allowed in init mode or soft reset mode. see section 7.2.3 for information of the operating modes. table 3 video front-end and formatter mode selection note 1. x = dont care. control bits (1) mode function std ss smod 0 0 x ntsc ntsc input signal processing (60 hz and 720 pixels by 480 lines) 1 0 x pal pal input signal processing (50 hz and 720 pixels by 576 lines) 0 1 x ntsc-sif ntsc input signal processing (60 hz and 720 pixels by 480 lines); sif down-scaling active 1 1 x pal-sif pal input signal processing (50 hz and 720 pixels by 576 lines); sif down-scaling active x x 0 itu-t 656 itu-t 656 mode sync processing mode; sync information is embedded in the video data input stream x x 1 external sync external sync processing mode; sync information is provided via pins fid, hsync and vsync 2000 may 03 18 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h 7.3.3.2 interface de?nition the data input interface uses in total 11 pins. pins yuv0 to yuv7 carry video and synchronization data and 3 pins are reserved for control purposes (see table 4). table 4 list of pins data input port note 1. in itu-t 656 mode sync signals are embedded in the video data input stream. the external sync signals are not used. 7.3.3.3 line based processing the line based processing works the same way for pal and ntsc signals. each of the three components of the video signals y, u and v are filtered horizontally. the filter is symmetrical and has seven taps. the seven taps are weighted with three programmable parameters a1, a2 and a3 as shown in table 5. table 5 horizontal ?ltering the three parameters must be loaded by setting the i 2 c-bus control register words a1, a2 and a3. the valid range is 0 to 255. reset state is 0. to convert the video signal from 4 : 2 : 2 to 4:2:0 format, vertical filtering and subsampling of the chrominance components has to be performed. the vertical filter has six taps. the filter coefficients are given in table 6. table 6 vertical ?ltering as mentioned, optionally an sif mode conversion of pal or ntsc standard input signals may be activated by setting the i 2 c-bus control bit ss (see tables 3 and 22). to convert the video signal to sif resolution the bottom fields are discarded. furthermore, all components of the video signal are horizontally subsampled by factor two. pin name pin type description yuv0 to yuv7 input video input signal (synchronous to vclk) fid input odd/even ?eld identi?cation signal; note 1 hsync input horizontal synchronization signal; note 1 vsync input vertical synchronization signal; note 1 tap - 3 - 2 - 1 0 +1 +2 +3 horizontal ?ltering f(a1, a2 and a3) a3 a2 a1 1 - 2(a1 + a2 + a3) a1 a2 a3 tap 123456 vertical ?ltering top ?elds - 3 +13 +30 +24 +4 - 4 vertical ?ltering bottom ?elds - 4 +4 +24 +30 +13 - 3 2000 may 03 19 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h 7.3.3.4 sync processing because the synchronization information may be delivered by a video data source in two different ways, the internal sync processing of the SAA6750h is carried out in two related modes: 1. the itu-t 656 mode: the itu-t 656 recommendation describes the unidirectional interconnection between a video data source and a video data sink. luminance and chrominance data as well as the complete set of control data (v-sync, h-sync, field indication or byte information such as sav, eav, etc.) are transferred interleaved on one 8-bit bus. both, sync and data signal, are in the form of binary coded 8-bit words. the external sync signals hsync, vsync and fid are not used. 2. the external sync mode: the synchronization may also be provided via pins hsync, vsync and fid. in this case, the 8-bit bus carries only the video data information. the internal sync processing mode may be selected by the i 2 c-bus control bit smod (see tables 3 and 22). sync signals must be active at regular time intervals. if a time interval is too short, a sync is skipped. top and bottom fields must follow each other. if two top fields or two bottom fields follow each other immediately, than the second field is skipped. the number of clock cycles and h-sync signals that have to occur before processing starts (horizontal and vertical shift) can be set via the i 2 c-bus. in this way the active part of the video can be determined. the vertical shift can be specified independently for top and bottom fields by using the control words vertical shift top field and vertical shift bottom field (see table 22). the horizontal shift is controlled by control word horizontal shift. the shift can be programmed in a range of 127 clock cycles in horizontal direction respectively 127 lines in vertical direction. horizontal shift should be carried out in steps of a multiple of 4 because a minimum data sequence (c b ,y,c r and y) needs 4 clock cycles. it should be noted that the horizontal blanking in pal mode takes 280 clock cycles and in ntsc mode 268 cycles. due to the fact that the horizontal offset value can not compensate the whole blanking interval, the polarity of the three external sync lines (h-sync, v-sync and fid) can also be adapted via the i 2 c-bus. control bits hrefp, vrefp and fidp are used for this purpose (see table 22). internally, the edge-detection circuitries for these signals change polarity with these settings. by this way different synchronization schemes are supported. the horizontal respectively vertical processing starts with the selected edge. due to requirements from the internal vertical filtering the line based processing needs 3 horizontal sync pulses during vertical blanking which have to follow directly the active part of the frame (e.g. 288 active lines in pal mode). the related line data is not processed. this restriction does not allow edge selection at the end of the previous field [e.g. vertical sync of line 623 or line 1 (see fig.3)]. in this case the polarity bit vrefp has to be set to select the falling edge of the sync lines. the following sections contain descriptions of different styles of synchronization signals and how they are handled in the SAA6750h. 7.3.3.5 sync processing pal (50 hz) the pal (50 hz) input signal has 625 lines per frame and typically takes 1728 clock cycles per line. the minimum number of clock cycles per line is 1706. the active part of a field consists of 288 lines of 720 pixels (see fig.7). figures 3 and 4 and the related table 7 give an example illustrating how different sources providing different external sync signals can be adapted to the SAA6750h. in the given example, the saa711x is connected to pins hsync, vsync and fid and provides external sync signals in two different modes: according to the timing convention of the itu-t 656 mode and in a saa711x proprietary format. in addition another mode href/vref is mentioned in table 7. from a timing point of view the href/vref mode behaves like itu-t 656, but horizontal sync and vertical sync signals (vsync) are inverted. see data sheet saa7111a for detailed information. as mentioned, in addition to the external sync mode, the itu-t 656 mode is supported. sections 7.3.3.7, 7.3.3.8 and figs 7 and 8 contain detailed information on this sync mode. 2000 may 03 20 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h handbook, full pagewidth 621 (1) 622623 12345678 (308) (2) (309) (310) (1) (2) (3) (4) (5) (6) (7) (8) 624 625 (311) (312) fid (itu-t 656 timing) fid (saa711x proprietary timing) vsync (itu-t 656 timing) vsync (saa711x proprietary timing) mhb662 fig.3 external sync timing of saa711x; 50 hz; lines 621 to 8. (1) the line numbers not in parenthesis refer to itu-t counting. (2) the line numbers in parenthesis refer to single field counting. handbook, full pagewidth fid (itu-t 656 timing) fid (saa711x proprietary timing) vsync (itu-t 656 timing) vsync (saa711x proprietary timing) 308 (1) 309 310 311 312 313 314 315 316 317 318 319 320 321 (308) (2) (309) (310) (1) (2) (3) (4) (5) (6) (7) (8) (311) (312) (313) mhb663 fig.4 external sync timing of saa711x; 50 hz; lines 308 to 321. (1) the line numbers not in parenthesis refer to itu-t counting. (2) the line numbers in parenthesis refer to single field counting. 2000 may 03 21 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h table 7 pal mode programming example for different sync modes and timing schemes notes 1. changes of video standard or synchronization set-up settings are only allowed in init mode or soft reset mode. see section 7.2.3 for information of the SAA6750h operating modes. 2. see the saa711x documentation. 3. as illustrated in figs 3 and 4. pal sync mode and timing control bit and control word settings (1) smod fidp vrefp hrefp vertical shift top field vertical shift bottom field horizontal shift itu-t 656 mode 0 0 0 0 0 0 0 external sync mode; vref/href mode input signals; itu-t 656 timing; note 2 10 0 0 0 0 0 external sync mode; itu-t 656 timing; note 3 10 1 1 0 0 0 external sync mode; saa711x proprietary timing; note 3 1 0 1 1 15 16 0 7.3.3.6 sync processing ntsc (60 hz ? 59.94 hz) this ntsc (60 hz) input signal has 525 lines per frame and typically takes 1716 clock cycles per line. the minimum number of clock cycles per line is 1706. the active part of a field consists of 240 lines of 720 pixels (see fig.9). figures 5 and 6 and the related table 8 give an example illustrating how different sources providing different external sync signals can be adapted to the SAA6750h. in the given example, the saa711x is connected to pins hsync, vsync and fid of the SAA6750h and provides external sync signals in two different modes: according to the timing convention of the itu-t 656 mode and in an saa711x proprietary format. in addition, another mode, href/vref, is mentioned in table 7. from timing point of view the href/vref mode behaves like itu-t 656, but signals horizontal sync and vertical sync (vsync) are inverted. see data sheet saa7111a for detailed information. as mentioned, in addition to the external sync mode, the itu-t 656 mode is supported. sections 7.3.3.7, 7.3.3.8 and figs 9 and 10 contain detailed information on this sync mode. 2000 may 03 22 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h handbook, full pagewidth 523 (1) 5245251234567891011 (260) (2) (261) (262) (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) fid (itu-t 656 timing) fid (saa711x proprietary timing) vsync (itu-t 656 timing) vsync (saa711x proprietary timing) mhb664 fig.5 external sync timing of saa711x; 60 hz; lines 523 to 11. (1) the line numbers not in parenthesis refer to itu-t counting. (2) the line numbers in parenthesis refer to single field counting. handbook, full pagewidth 261 (1) 262 263 264 265 266 267 268 269 270 271 272 273 274 (261) (2) (262) (263) (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) fid (itu-t 656 timing) fid (saa711x proprietary timing) vsync (itu-t 656 timing) vsync (saa711x proprietary timing) mhb665 fig.6 external sync timing of saa711x; 60 hz; lines 261 to 274. (1) the line numbers not in parenthesis refer to itu-t counting. (2) the line numbers in parenthesis refer to single field counting. 2000 may 03 23 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h table 8 ntsc mode programming example for different sync modes and timing schemes notes 1. changes of video standard or synchronization set-up settings are only allowed in init mode or soft reset mode. see section 7.2.3 for information of the SAA6750h operating modes. 2. see data sheet saa711x documentation. 3. as illustrated in figs 5 and 6. 7.3.3.7 sync processing coding characteristics according to itu-t 656 the video data and the control data h_sync, v_sync and field identification are interleaved as follows. ntsc sync mode and timing control bit and control word settings (1) smod fidp vrefp hrefp vertical shift top field vertical shift bottom field horizontal shift itu-t 656 mode 0 0 0 0 0 0 0 external sync mode; vref/href mode input signals; itu-t 656 timing; note 2 10 0 0 0 0 0 external sync mode; itu-t 656 timing; note 3 10 1 1 0 0 0 external sync mode; saa711x proprietary timing; note 3 10 1 1 9 10 0 handbook, full pagewidth mhb666 f f 0 0 0 0 x y 4 280 1728 1440 f f 0 0 0 0 x y 4 eav code start of digital line start of digital active line internal h control signal next line blanking co-sited co-sited sav code c b yc r yc b yc r yc r yf f 8 0 1 0 8 0 1 0 8 0 1 0 fig.7 digital horizontal blanking (pal) in a digital video stream. 2000 may 03 24 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h table 9 digital vertical timing (pal) line number f v h (eav) h (sav) 1to22 0 1 1 0 23 to 310 0 0 1 0 311 and 312 0 1 1 0 313 to 335 1 1 1 0 336 to 623 1 0 1 0 624 and 625 1 1 1 0 handbook, full pagewidth mhb667 blanking field 1 active video blanking field 2 active video field 1 (f = 0) odd line 1 field 2 (f = 1) even h = 1 eav h = 0 sav line 313 line 625 line 1 (v = 1) line 23 (v = 0) line 311 (v = 1) line 625 (v = 1) line 624 (v = 1) line 336 (v = 0) blanking fig.8 digital vertical timing (pal). 2000 may 03 25 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h handbook, full pagewidth mhb668 f f 0 0 0 0 x y 4 268 1716 1440 f f 0 0 0 0 x y 4 eav code start of digital line start of digital active line internal h control signal next line blanking co-sited co-sited sav code c b yc r yc b yc r yc r yf f 8 0 1 0 8 0 1 0 8 0 1 0 fig.9 digital horizontal blanking (ntsc) in a digital video stream. handbook, full pagewidth mhb669 blanking field 1 active video optional blanking blanking field 2 active video optional blanking field 1 (f = 0) odd line 4 field 2 (f = 1) even h = 1 eav h = 0 sav line 266 line 3 line 1 (v = 1) line 10 (v = x) line 20 (v = 0) line 264 (v = 1) line 525 (v = 0) line 273 (v = 1) line 283 (v = 0) fig.10 digital vertical timing (ntsc). 2000 may 03 26 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h table 10 digital vertical timing (ntsc) line number f v h (eav) h (sav) 1to3 1 1 1 0 4to19 0 1 1 0 20 to 263 0 0 1 0 264 and 265 0 1 1 0 266 to 282 1 1 1 0 283 to 525 1 0 1 0 7.3.3.8 video timing reference codes (itu-t 656) there are two timing reference signals, one at the beginning of each video data block (start of active video, sav) and one at the end of each video data block (end of active video, eav). each timing reference signal consists of a four word sequence in the following format: ff 00 00 xy (values are expressed in hexadecimal notation). the first three words are a fixed preamble. the forth word xy contains information defining field 2 identification, the state of field blanking, and the state of line blanking. the assignment of bits within the timing reference signal is shown in table 11. table 11 video timing reference codes notes 1. f = 0 during field 1; f = 1 during field 2. 2. v = 1 during field blanking; v = 0 elsewhere. 3. h = 0 in sav; h = 1 in eav. 4. protection bits are ignored by SAA6750h data processing. 7.4 macroblock processor 7.4.1 g eneral the macroblock processor (mbp) performs the compression of macroblocks. it fetches its input data from the external dram memory where this was stored by the video front-end and formatter. the data processing is macroblock related. the processing start information and the global scheduling is provided by the global controller module. the functionality of the mbp is controlled by the application specific instruction-set processor (asip). the asip does also perform some computing of data needed by the mbp. the compressed data is fed to the packer module. 7.4.2 f unctional description 7.4.2.1 general the mbp performs source coding on macroblock level. it contains several items: motion estimation; motion compensation, noise reduction and frame field conversion; discrete and inverse discrete cosine transformations (dct and idct), quantization and inverse quantization; motion decompensation and frame-field conversion; zigzag scanning; dc trend removal (residue); run-length encoding (rle) and variable-length encoding (vle). 7.4.2.2 motion estimation the motion estimator considers frame based motion. furthermore, the frame distance is one frame and, consequently, can only be used for p frames. the motion estimation is based on the recursive block matching algorithm. per macroblock the asip must feed the motion estimator with five candidate vectors. depending on a control word, the last two vectors can be relative to the computed vector of the previous macroblock or can be absolute. the vectors are compared by the minimum absolute difference (mad) of the estimated macroblock in the previous frame and the current macroblock. the vector that leads to the smallest mad is selected. the fifth vector gets a penalty and can be used as random vector candidate. the two coordinates of the selected vector and the corresponding mad value are returned to the asip. 7.4.2.3 noise ?ltering the availability of the motion estimator makes motion compensated adaptive temporal filtering possible. the functioning of this filter can be programmed by two parameters. these parameters are provided by the asip. the noise reduction may only be activated if control bit intra is set to logic 0 (see table 22). 1f (1) v (2) h (3) p 3 (4) p 2 (4) p 1 (4) p 0 (4) 2000 may 03 27 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h 7.4.2.4 intra/inter coded macroblock selection in p frames the selection of intra or inter coded macroblock compression mode depends on a control byte from the asip or on the mad value. a macroblock is coded intra, if the asip demands so or when the mad resulting from the motion estimation is above a threshold value. this threshold value is provided by the asip. the resulting encoding mode is returned to the asip. 7.4.2.5 field/frame dct coded macroblock selection for luminance blocks depending on motion between the two fields comprising a frame, the four 8 8 pixel dct luminance blocks of a macroblock are differently derived from the 16 16 pixels. the luminance pixels of a macroblock are vertically walsh-hadamard transformed in order to detect the field motion. if the first coefficient is higher than a threshold value, then the dct is performed field-wise. the asip can force frame dct coding. the result, i.e. frame or field dct coding, is returned to the asip. the output of the dct are four luminance and two chrominance blocks consisting of 8 8 pixels each. 7.4.2.6 quantization the quantization performs the redundancy removal, depending on settings provided by the asip. the quantization may be customized by using a dedicated quantization table which can be loaded via the i 2 c-bus (see section 7.9.4). the quantization table data is part of the software packages and will be described in the software specification. 7.4.2.7 trend removal dc coefficients are coded differentially. however, at the start of every slice and for every intra coded macroblock, the absolute values are coded. therefore, the asip sends a control word to the mbp indicating the start of a slice. 7.4.2.8 run-length coding and variable-length coding the mbp compresses the quantized dct coefficients by (zero) run-length coding (rlc) and variable-length coding (vlc). to inform the asip about the achieved compression, it sends the number of bits used in the bitstream to the asip. the maximum number of bits used for each of the six blocks (see section 7.4.2.5) must be set by the asip. furthermore, the coded block pattern is sent to the asip. 7.4.2.9 addressing the mbp only relies on the format used to store macroblocks in the external dram. it works independently from the memory map where to find which macroblock. the asip has to keep track of the macroblocks base addresses and has to inform the mbp where to find the data. the mbp only increments the addresses to fetch next data or to write results back. 7.4.2.10 communication with the asip the communication with the asip is the same for every macroblock. that means that although many settings remain unchanged they have to be repeatedly sent from the asip to the mbp. the communication is handled by fifos. 7.5 bitstream assembly 7.5.1 g eneral while mbp only processes the incoming video data and the asip generates the corresponding mpeg2 compliant header and stuffing information, these information must be gathered to form a complete output stream. parts involved are: packing unit (packer and pre-packer) stuffing unit (buffer_out_address and buffer_out_data) various fifos connecting all parts together. the packing unit does the bit-wise processing of the asip and mbp generated streams while the stuffing unit is byte oriented. handshaking of all blocks is done via fifos. 7.5.2 p re - packer and packer the packing unit (consisting of packer and pre-packer) is responsible to compose a fluent bitstream. each clock cycle the packer gets a certain amount of valid bits (0 to 24) as input data either from the asip (e.g. header information) or from the mbp (compressed macroblock coefficients via pre-packer) and generates 64-bit words with valid bits only. these words are stored into the 4 mbit output buffer located in the external dram. to reduce the memory needs of the compressed macroblock data, a pre-packing to get words of 24 valid bits is performed before storing data for packing. 2000 may 03 28 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h 7.6 data output port 7.6.1 g eneral the data output port connects the data output stream of the SAA6750h to the outside world. the data output port interface implements a motorola-style bus protocol with different addressing modes. the status of the internal data buffer is reported by dedicated output signals. the data output interface of the SAA6750h will always behave as a slave on the bus. 7.6.2 d ata output format the output data is provided in 16-bit words. the most significant bit of the data word represents the first bit in the serial mpeg2 elementary stream. depending on the addressing mode the external host uses the bus transfers plain data (non-multiplex mode) or a multiplex of addresses and data (multiplex mode) for selection of the data output port, see section 7.6.3 for information about the interface protocol. 7.6.3 f unctional description 7.6.3.1 general the data output port supports motorola-style bus protocol. the addressing can be carried out by the external host in two different modes: 1. internal address decoding the data output port provides a programmable internal address decoding. this does support e.g. the use of several slaves on the bus. the data output ports 16-bit address is determined by the setting of bytes bus address (msb) and bus address (lsb) in the i 2 c-bus control register (see table 21). during reset mode the contents of bus address will be set to 0000h. the external host may select the data output port by sending the address value that was programmed in the i 2 c-bus control register. in internal address decoding mode, the output data bus carries multiplexed address and data information. pin csn is not used in this mode and must be set to high. 2. external address decoding external address decoding mode may be appropriate if e.g. an external address decoding hardware is available or if the SAA6750h is the only slave on the bus. the data output port is selected by setting pin csn to low. in this mode, the internal address decoder is disabled and consequently the setting of bytes bus address is ignored. in external address decoding mode, the output data bus carries plain data information. the bus protocol mode and address decoding mode are depending on the setting of the i 2 c-bus control register bit bus. see tables 12 and 22 and section 7.6.3.4 for detailed information. table 12 data output port mode selection notes 1. bit bus is set to logic 0 during reset mode. 2. the 16-bit data output port address (see table 21) must be loaded via the i 2 c-bus with the application specific value. the default address is set to 0000h during reset mode. 3. x = dont care. bit bus pin i_mn function 0 low motorola-style protocol mode with external address decoding (non-multiplexed bus); note 1 1 low motorola-style protocol mode with internal 16-bit address decoding (multiplexed bus); notes 1 and 2 x (3) high reserved 2000 may 03 29 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h 7.6.3.2 interface de?nition the data output interface uses in total 23 pins. pins ad0 to ad15 carry data and address information. 7 pins are reserved for control purposes. partly, the functionality of these pins changes with the selected address or protocol mode (see tables 13 and 14). table 13 list of pins data output port table 14 protocol mode depending pins pin name pin type description ad0 to ad15 input/output internal address decoding: multiplexed address/data bus; external address decoding: non-multiplexed data bus as_ale input protocol mode depending functionality; see table 14 csn input internal address decoding: not used; connect to high; external address decoding: data output port select input ds_rdn input protocol mode depending functionality; see table 14 dtack_rdy output protocol mode depending functionality; see table 14 i_mn input select protocol mode: low is motorola-style protocol mode (must be set to logic 0); high is reserved mode lrqn output low indicates that the fullness of the output buffer is below the programmable lower watermark value; see table 22 urqn output low indicates that the fullness of the output buffer is higher than the programmable higher watermark value; see table 22 pin name motorola-style protocol mode reserved mode as_ale as address strobe ale reserved ds_rdn ds data strobe rdn reserved dtack_rdy dtack data transfer acknowledge rdy reserved 7.6.3.3 status reporting data output buffer the data output port of the SAA6750h provides information about the status of the internal 4 mbit output buffer. two signals that are available via pins lrqn and urqn are related to internal buffer watermarks. the external host may use this information to control the data stream in a way that highest rates are possible without out-of-data or buffer-overflow situations. the watermark levels are programmable via the i 2 c-bus (see table 22). the lower watermark reporting may be used by the host to prevent out-of-data situations. the fullness of the data output buffer is monitored. if the current value is below the threshold programmed in control word bs_buffer lower level in the i 2 c-bus control register, the signal lrqn goes to low. the host may use this information to stop requesting data. value bs_buffer lower level has a range of 0 to 63. if the value is set to 0, lrqn will not be activated. the threshold can be selected in 64-bit steps. the upper watermark reporting may be used by the host to prevent data overflow of the output buffer of the SAA6750h. the fullness of the data output buffer located in the external dram is monitored. if the current value is two times or more than two times the value programmed in bytes bs_buffer upper level in the i 2 c-bus control register, the signal urqn goes to low. the host may use this information to start requesting data. if it does not, an internal buffer overflow may result in loss of data. value bs_buffer upper level has a valid range of 1 to 32752. the threshold can be selected in 128-bit steps. the maximum watermark value equals 4 mbit. during reset mode, bs_buffer lower level and bs_buffer upper level are set to logic 0. the i 2 c-bus control register values bs_buffer should be initialized with the desired values before starting operating mode. if bs_ buffer lower level has a value greater than 0, lrqn will be low as long as no valid data is available. 2000 may 03 30 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h 7.6.3.4 motorola-style protocol mode 1. internal address decoding the host starts a data transfer cycle by applying the data output port address onto the multiplexed address/data lines (see fig.16). by setting as_ale to low the host indicates that the address is valid and by setting ds_rdn to low that it gives up driving the address data and allows the data output interface of the SAA6750h to send data via the bus. the SAA6750h will drive dtack_rdy to low, when it has placed valid data onto ad15 to ad0. a ds_rdn = high by the host will force the SAA6750h to set dtack_rdy back to high, to stop driving the data bus and to interrupt the transfer of the current word, however, this may lead to a loss of data. the data read sequence may be repeated by setting ds_rdn to low and so forth. the transfer cycle is ended as soon as the host sets ds_rdn and as_ale back to high. after this, the SAA6750h will also set dtack_rdy to high and stops driving data after a delay t dz (see chapter characteristics). a new transfer cycle may not be started as long as dtack_rdy is low or the SAA6750h is driving the data bus. csn has to be high all the time. see fig.16 and chapter characteristics for timing information. 2. external address decoding the host starts a data transfer cycle by setting the csn signal to low (see fig.17). by setting ds_rdn to low the host indicates that it wants to read a data word and allows the data output interface of the SAA6750h to send data via the bus. the SAA6750h will drive dtack_rdy to low, when it has placed valid data onto ad15 to ad0. a ds_rdn = high by the host will force the SAA6750h to set dtack_rdy back to high, to stop driving the data bus and to interrupt the transfer of the current word however this may lead to a loss of data. the data read sequence may be repeated by setting ds_rdn to low and so forth. the transfer cycle is ended as soon as the host sets ds_rdn and csn back to high. after this, the SAA6750h will also set dtack_rdy to high and stop driving data after a delay t dz (see chapter characteristics). a new transfer cycle may not be started as long as dtack_rdy is low or the SAA6750h is driving the data bus. as_ale has to be high all the time. see fig.17 and chapter characteristics for timing information. 7.7 application speci?c instruction-set processor (asip) 7.7.1 g eneral the asip is a programmable controller specially designed for the architecture and system requirements of the SAA6750h. generally it has to cover internal control functions. the following tasks are handled: controlling of the mbp macroblock base address generation for the mbp motion vector generation bitstream header generation management of bitstream assembly bit-rate control. the microcode of the asip has to be downloaded by the i 2 c-bus into internal rams during initialization of the SAA6750h. the asip is able to communicate with the outside world via an i 2 c-bus interface (see section 7.9.4). 7.8 global controller 7.8.1 g eneral the global controller generates a global scheduling for the loosely coupled processes of the SAA6750h. it is controlled by the bits e_st, e_sp, ss and std which are located in the i 2 c-bus control register (see table 22). the global controller is automatically synchronized with the front-end block. 7.9 i 2 c-bus interface and controller 7.9.1 g eneral the i 2 c-bus interface within the SAA6750h is a slave transceiver. it is used to download the microcode of the asip, constants and tables as well as the quantization matrix table to the mbp. in addition, all control settings are carried out via the i 2 c-bus. the read mode may be used to read back data from registers connected internally to the asip. in total 8 subaddresses are used to store or read data. the i 2 c-bus interface is compliant to the i 2 c-bus standard at 100 and 400 khz clock frequency and suitable for bus-line voltage levels from 3.3 to 5 v. the i 2 c-bus slave address (sad) is 40h respectively 42h depending on the state of pin mad. this allows the use of two devices SAA6750h in one application. see the general i 2 c-bus specification for detailed information on the bus protocol. 2000 may 03 31 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h 7.9.2 s pecial considerations eight subaddresses are used to read or write data from or to the internal sram memories and registers of the SAA6750h. an explanation of purpose, function and data transfer will be given in the following chapters. it should be noted that all subaddresses can only be used as data sink or as data source. it is not possible to write data into a register and read it back later on. due to the internal memory architecture data may only be transmitted to the subaddresses 00h to 03h when the SAA6750h is in init mode. after the control bit e_st is set to logic 1, sending data via the i 2 c-bus to the srams 00h to 03h is forbidden. the i 2 c-bus interface will not respond to the general call address 00h and it will not use clock stretch to slow down a data transmission. the acknowledgement of a data byte by the i 2 c-bus interface only indicates that the transmission was received and that the correct slave address was used. it does not necessarily say that the data reached its destination. e.g. also if a subaddress outside the valid range from 00h to 007h was sent to the SAA6750h or a transmission to subaddress 01h took place while bit e_st was logic 1, the i 2 c-bus interface will return an acknowledge. a special sequence of commands is used to read data from the subaddress 04h. see section 7.9.3.4 for detailed information. 7.9.3 i 2 c- bus data transfer modes 7.9.3.1 general data transfer follows the i 2 c-bus specification for fast (400 khz) or normal (100 khz) mode. the SAA6750h slave address in write mode is: 40h if pin mad is low 42h if pin mad is high. for read operations the following slave addresses have to be used: 41h if pin mad is low 43h if pin mad is high. the i 2 c-bus will transfer data always as a whole byte consisting of 8 bits. if the address or data word consists of several bytes, the most significant byte (msb) has to be sent first and the least significant byte (lsb) last. this rule does also apply for read operations. in this case the msb will be received first. if the memorys address or data word does not have a width of a multiple of 8 bits, dummy bits have to be added on the left side (most significant bit side) of the msb. e.g. the asip microcode has 177 bits wide data words. 177 divided by 8 gives 22 and a remainder of 1. therefore the i 2 c-bus master has to send 23 data bytes of which the higher 7 bits of the msb are dummy bits. also the same rule applies for read operations. depending on the type of storage the data transfer to or from the memories and registers has to be carried out in different modes which will be described in the following chapters. table 15 abbreviations used in data transfer diagrams abbreviation function si 2 c-bus start condition, generated by master rs i 2 c-bus repeated start condition, generated by master sad higher 7 bits of slave address byte: 7-bit slave address: 0100000 (pin mad = low), 40h/41h; 7-bit slave address: 0100001 (pin mad = high), 42h/43h w write mode: lsb of slave address byte = 0 r read mode: lsb of slave address byte = 1 ma master acknowledge (acknowledge generated by master) mn master acknowledge not (no acknowledge by master) sa slave acknowledge (acknowledge generated by SAA6750h) sd 8-bit subaddress adr address byte data data byte to be written/read pi 2 c-bus stop condition, generated by master 2000 may 03 32 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h 7.9.3.2 random access memory write mode this mode provides random access to specific memory addresses. the data has to be written according to following scheme: table 16 data transfer using random access write mode in this example the address word consists of 2 bytes and the data word out of n bytes. this sequence has to be repeated for every data word that has to be sent to the memory. 7.9.3.3 write mode the write mode is used if a number of data bytes has to be written to a subaddress if there is no specific memory address. i.e. this mode is used to write data to registers. the data has to be sent according to following scheme: table 17 data transfer using write mode in this example the data word consists of n bytes. 7.9.3.4 read mode this mode is used to read data bytes from memories or registers. it is not possible to access a specific memory address. the first byte to be received will be the msb. if a certain information is needed, the read transfer has to be carried out until the specific byte is available. the data transfer has to be closed by the i 2 c-bus master by sending an mn (not acknowledge) after the last data byte. this tells the SAA6750h to stop sending further data. the transfer has to follow this scheme: table 18 data transfer using read mode in this example the read operation gets n data bytes out of the SAA6750h. s sad w sa sd sa adr1 (msb) sa adr2 (lsb) sa data 1 (msb) sa ... data n - 1 sa data n (lsb) sa p ssadwsasdsa data 1 (msb) sa data 2 (msb - 1) sa data 3 (msb - 2) sa ... data n - 1 sa data n (lsb) sa p s sad w sa sd sa rs sad r data 1 (msb) ma data 2 (msb - 1) ma ... data n - 1 ma data n (lsb) mn p 2000 may 03 33 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h 7.9.4 i 2 c- bus memories and registers eight different sram memories and registers may be written or read via the i 2 c-bus. each has a specific subaddress. this chapter will explain the purpose of these storages and how they have to be used. 7.9.4.1 allocation of subaddresses following table shows which memories or registers are allocated to the subaddresses 00h to 07h: table 19 subaddresses and related memories subaddress (hex) storage name design block depth (words) width(bits) description 00 quantizatio n matrix sram mbp 128 8 sram memory containing a constant table for the macroblock processor quantization function 01 microcode sram asip 1024 177 sram memory containing the microcode of the asip 02 microcode rom table asip 512 24 sram memory containing the microcode rom table of the asip 03 microcode constants asip 256 24 sram memory containing the microcode constants of the asip 04 serial output register asip 7 24 register bank that can be written by the asip; contents depending on the asip software 05 serial input register asip 14 24 register bank that can be read by the asip; used to control the asip externally; the function of the register settings is depending on the asip software 06 control register i 2 c-bus 1 160 register containing the hardware control bits of the SAA6750h 07 internal use none --- 2000 may 03 34 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h 7.9.4.2 i 2 c-bus data transfer to subaddresses the following tables describe the data transfer to or from the subaddresses 0 to 7. see sections 7.9.3.2, 7.9.3.3 and 7.9.3.4 for information of the data transfer modes. table 20 data transfer to subaddresses 7.9.4.3 quantization matrix sram sram memory containing a constant table for the macroblock processor quantization function. the data to be loaded into this memory will be part of the application software and described in the software specification. remark : data may only be sent to this subaddress if the SAA6750h is in the init mode (see table 23). 7.9.4.4 microcode sram sram memory containing the asips microcode. the microcode to be loaded into this memory will be part of the application software and described in the software specification. remark : data may only be sent to this subaddress if the SAA6750h is in the init mode (see table 23). subaddress (hex) storage name data transfer mode address bytes per transmission data bytes per transmission i 2 c-bus byte transfers per transmission 00 quantization matrix sram random access write mode 1 1 4=2+1+1 01 microcode sram random access write mode 2 23 27=2+2+23 02 microcode rom table random access write mode 2 3 7=2+2+3 03 microcode constants random access write mode 1 3 6=2+1+3 04 serial output register read mode 0 21 24 = 2 + 1 + 21 05 serial input register random access write mode 1 24 6=2+1+3 06 control bits register write mode 0 20 22 = 2 + 20 07 internal use none --- subaddress (hex) storage name design block depth (words) width (bits) data transfer mode 00 quantization matrix sram mbp 128 8 random access write mode subaddress (hex) storage name design block depth (words) width (bits) data transfer mode 01 microcode sram asip 1024 177 random access write mode 2000 may 03 35 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h 7.9.4.5 microcode rom table sram sram memory containing special tables that are needed by the asip software. the quantization matrix data loaded into subaddress 0 is also part of this set of data. the data to be loaded into this memory will be included in the application software and described in the software specification. remark : data may only be sent to this subaddress if the SAA6750h is in the init mode (see table 23). 7.9.4.6 microcode constant sram sram memory containing constants that are needed by the asip software. the data to be loaded into this memory will be included in the application software and described in the software specification. remark : data may only be sent to this subaddress if the SAA6750h is in the init mode (see table 23). 7.9.4.7 serial output register register bank that can be written by the asip and read by the i 2 c-bus. the asip is able to access a specific register by writing the address and the related data word. on the contrary it is not possible to access a specific register by the i 2 c-bus. starting an i 2 c-bus read operation will return the data of register 0 first, starting with the most significant byte. after the lsb of register 0 was received, the register address will be incremented automatically and the msb of register 1 will be received next. consequently, 21 data words have to be read if the data of register 6 is needed. the register data depends on the asips software and the state of the SAA6750h. a description will be part of the software specification. subaddress (hex) storage name design block depth (words) width (bits) data transfer mode 02 microcode rom table sram asip 512 24 random access write mode subaddress (hex) storage name design block depth (words) width (bits) data transfer mode 03 microcode constants sram asip 256 24 random access write mode subaddress (hex) storage name design block depth (words) width (bits) data transfer mode 04 serial output register asip 7 24 read mode 2000 may 03 36 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h 7.9.4.8 serial input register register bank that can be read by the asip. used to control the asip externally. the function of register settings is depending on the asip software. a description will be part of the software specification. the valid address range reaches from 01h to 0eh. any data sent by the i 2 c-bus to address 00h will always be overwritten by an internal signal. 7.9.4.9 control register register bank used to control internal signals. the allocation of control bits in the register is shown in table 21. the function of the specific bits is described in table 22. during external reset, all register bits will be set to logic 0. during initialization all 20 bytes starting with the msb and ending with the lsb (control) have to be sent by the i 2 c-bus in one go. subaddress (hex) storage name design block depth (words) width (bits) data transfer mode 05 serial input register asip 14 24 random access write mode subaddress (hex) storage name design block depth (words) width (bits) data transfer mode 06 control register i 2 c 1 160 write mode 2000 may 03 37 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h table 21 description of the i 2 c-bus control register; note 1 note 1. x = dont care; should be set to logic 0 during initialization. register byte bit address (hex) msb lsb d7 d6 d5 d4 d3 d2 d1 d0 control 00 to 07 std ss intra bus e_st e_sp smod byp fifo pmi(s) time slot setting 08 to 0f pmi7 pmi6 pmi5 pmi4 pmi3 pmi2 pmi1 pmi0 fifo wr_ad(mc) time slot setting 10 to 17 wr7 wr6 wr5 wr4 wr3 wr2 wr1 wr0 fifo rd_adr(ma) time slot setting 18 to 1f rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 fifo buf_adr(h) time slot setting 20 to 27 buf7 buf6 buf5 buf4 buf3 buf2 buf1 buf0 fifo refr(g) time slot setting 28 to 2f rfr7 rfr6 rfr5 rfr4 rfr3 rfr2 rfr1 rfr0 fifo mc(e) time slot setting 30 to 37 mc7 mc6 mc5 mc4 mc3 mc2 mc1 mc0 fifo ml(b) time slot setting 38 to 3f ml7 ml6 ml5 ml4 ml3 ml2 ml1 ml0 fidp and vertical shift bottom ?eld 40 to 47 fidp vsb6 vsb5 vsb4 vsb3 vsb2 vsb1 vsb0 vrefp and vertical shift top ?eld 48 to 4f vrefp vst6 vst5 vst4 vst3 vst2 vst1 vst0 hrefp and horizontal shift 50 to 57 hrefp hor6 hor5 hor4 hor3 hor2 hor1 hor0 filter coef?cient a3 58 to 5f fa37 fa36 fa35 fa34 fa33 fa32 fa31 fa30 filter coef?cient a2 60 to 67 fa27 fa26 fa25 fa24 fa23 fa22 fa21 fa20 filter coef?cient a1 68 to 6f fa17 fa16 fa15 fa14 fa13 fa12 fa11 fa10 shift start 70 to 77 sh7 sh6 sh5 sh4 sh3 sh2 sh1 sh0 bs_buffer lower level 78 to 7f x x bl5 bl4 bl3 bl2 bl1 bl0 bs_buffer upper level (lsb) 80 to 87 bu7 bu6 bu5 bu4 bu3 bu2 bu1 bu0 bs_buffer upper level (msb) 88 to 8f x bu14 bu13 bu12 bu11 bu10 bu9 bu8 bus address (lsb) 90 to 97 dadr7 dadr6 dadr5 dadr4 dadr3 dadr2 dadr1 dadr0 bus address (msb) 98 to 9f dadr15 dadr14 dadr13 dadr12 dadr11 dadr10 dadr9 dadr8 2000 may 03 38 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h table 22 description of the i 2 c-bus control bits and words bit address (hex) bit name control word name data byte description 00 byp 19 internal use; it must be set to low during initialization 01 smod (1) external/internal sync signal selection; low: sync is derived from the sav and eav information decoded from the data stream at port yuv; high: sync is derived from the external sync signals at pins fid, hsync and vsync 02 e_sp engine stop; see table 23 03 e_st engine start; see table 23 04 bus data output port address mode selection; low: external address decoding (csn pin); high: internal address decoding (ad pin) 05 intra maximum output bit-rate selection; use default setting given in the software speci?cation 06 ss (1) non sif mode/sif mode selection; low: subsampling off; high: subsampling on (sif mode convertion active) 07 std (1) ntsc/pal selection; low: ntsc mode input signal expected; high: pal mode input signal expected 08 to 0f pmi0 to pmi7 18 use default setting given in the software speci?cation 10 to 17 wr0 to wr7 17 use default setting given in the software speci?cation 18 to 1f rd0 to rd7 16 use default setting given in the software speci?cation 20 to 27 buf0 to buf7 15 use default setting given in the software speci?cation 28 to 2f rfr0 to rfr7 14 use default setting given in the software speci?cation 30 to 37 mc0 to mc7 13 use default setting given in the software speci?cation 38 to 3f ml0 to ml7 12 use default setting given in the software speci?cation 40 to 46 vsb0 to vsb6 vertical shift bottom ?eld 11 value determines number of h-syncs occurring after v-sync before the bottom ?eld line based processing starts; note 2 47 fidp (1) fid signal polarity selection; low: fid signal not inverted (fid = low indicates odd ?eld); high: fid signal inverted (fid = high indicates odd ?eld); this setting takes affect for external as well as for sav and eav sync 2000 may 03 39 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h notes 1. changes of this setting are only allowed in init mode or soft reset mode. see section 7.2.3 for information of the SAA6750h operating modes. 2. the range of sensible values is 00h to 10h for pal and 00h to 07h for ntsc. 48 to 4e vst0 to vst6 (1) vertical shift top ?eld 10 value determines number of h-syncs occurring after v-sync before the top ?eld line based processing starts; note 2 4f vrefp (1) vsync signal polarity selection; low: vsync signal not inverted, vref signal expected at pin vsync; high: vsync signal inverted, vertical blanking quali?er expected at vsync pin; this setting does not affect the sync derived from sav and eav codes 55 to 56 hor0 to hor6 (1) horizontal shift 9 setting determines the number of clock cycles occurring after the h-sync before the line based processing starts; value should have a multiple of 4 because a minimum data sequence (c b ,y,c r and y) needs 4 clock cycles 57 hrefp (1) hsync signal polarity selection; low: hsync signal not inverted, href signal expected at pin hsync; high: hsync signal inverted, horizontal blanking quali?er expected at pin hsync; this setting does not affect the sync derived from sav and eav codes 58 to 5f fa30 to fa37 filter coef?cient a3 8 ?lter coef?cient a3 for the horizontal ?ltering of video input signal 60 to 67 fa20 to fa27 filter coef?cient a2 7 ?lter coef?cient a2 for the horizontal ?ltering of video input signal 68 to 6f fa10 to fa17 filter coef?cient a1 6 ?lter coef?cient a1 for the horizontal ?ltering of video input signal 70 to 77 sh0 to sh7 shift start (time slot) 5 use default setting given in the software speci?cation 78 to 7d bl0 to bl5 bs_buffer lower level 4 lower watermark value for data output buffer monitoring in 64-bit steps 7e to 7f - not used; it must be set to low during initialization 80 to 87 bu0 to bu7 bs_buffer upper level (lsb) 3 upper watermark value for data output buffer monitoring (lsb); the valid range for bs_buffer upper level is 1 to 32752 in 128-bit steps 88 to 8e bu8 to bu14 bs_buffer upper level (msb) 2 upper watermark value for data output buffer monitoring (msb); the valid range for bs_buffer upper level is 1 to 32752 in 128-bit steps 8f - not used; it must be set to low during initialization 90 to 97 dadr0 to dadr7 bus address (lsb) 1 address value for internal address decoding mode of data output port (lsb) 98 to 9f dadr8 to dadr15 bus address (msb) 0 address value for internal address decoding mode of data output port (msb) bit address (hex) bit name control word name data byte description 2000 may 03 40 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h table 23 description of engine bits the engine control bits are used to set the SAA6750h in a specific operating mode. after reset mode the init mode will be activated automatically. for information about the operating modes of the SAA6750h refer to table 1. 7.9.5 i 2 c- bus initialization after power-on and the related resetn pulse the SAA6750h has to be initialized via the i 2 c-bus. the internal rams must be loaded and the control bits must be set. the internal memories reachable via subaddresses 00h, 01h, 02h and 03h should be loaded first. use the data files that belong to a specific asip software version. the control register should be written at last. activate bit e_st only if all other settings have the desired state. there has to be a 0.5 ms delay between the end of the external reset resetn and the start of the i 2 c-bus initialization. the registers and memories of the SAA6750h should be initialized in following order: 1. subaddress 00h: mbp quantization matrix 2. subaddress 01h: asip microcode 3. subaddress 02h: asip microcode rom table 4. subaddress 03h: asip microcode constant 5. subaddress 05h: asip serial input 6. subaddress 06h: control register (see table 24). the following example shows a control register setting for pal input signal, sav/eav sync and external output port address decoding for inter and intra mode. it should be noted that the settings for the intra bit and the fifo time slot values are depending on a specific asip software version. use in any case those settings given in the asip software specification. e_st e_sp selected operating mode 0 0 init mode 0 1 soft reset mode 1 0 operating mode 1 1 internal use only 2000 may 03 41 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h table 24 example for control register settings register byte data byte inter/intra mode intra force mode binary hex binary hex control 19 1000 1000 88 1010 1000 a8 pmi 18 0010 0011 23 0010 0011 23 wr 17 1000 0100 84 1000 0100 84 rd 16 0110 1011 6b 1000 0001 81 buf 15 0000 0111 07 0000 0111 07 rfr 14 0000 0001 01 0000 0001 01 mc 13 1010 0001 a1 1010 0001 a1 ml 12 1001 0111 97 1001 0111 97 fidp and vertical shift bottom 11 0000 0000 00 0000 0000 00 vrefp and vertical shift top 10 0000 0000 00 0000 0000 00 hrefp and horizontal shift 9 0000 0000 00 0000 0000 00 filter coef?cient a3 8 0000 0000 00 0000 0000 00 filter coef?cient a2 7 0000 0000 00 0000 0000 00 filter coef?cient a1 6 0000 0000 00 0000 0000 00 shift start 5 0000 1000 08 0000 0100 04 bs_buffer lower level 4 0000 0000 00 0000 0000 00 bs_buffer upper level (lsb) 3 1111 1111 ff 1111 1111 ff bs_buffer upper level (msb) 2 0100 1111 4f 0100 1111 4f bus address (lsb) 1 1111 1111 ff 1111 1111 ff bus address (msb) 0 1111 1111 ff 1111 1111 ff 7.10 dram interface 7.10.1 g eneral the dram interface of the SAA6750h schedules and handles all accesses of internal read and write clients to the external 4 4 mbit dram memory. it also takes care of the dram refresh after power-on reset and performs the initialization of the external dram. four fast page mode or extended data out (edo) dram devices (t rac = 60 ns) with 16-bit data and 9-bit row and column address have to be applied in parallel. therefore the accessible dram format is 262144 64 bits. 7.10.2 a pplication hints it should be noted that the dram interface is timing sensitive. make sure that wires between the SAA6750h and the external dram memories are as short as possible. in addition the casn, rasn, address and data lines should have approximately the same parasitic load. 7.10.3 f unctional description 7.10.3.1 interface de?nition the connection between the dram interface and the memory consists of 77 signals. adr0 to adr8 are used to transfer the row or the column address. the signals casn and rasn indicate, that a column/row address is present on adr0 to adr8. wen enables a write access and oen selects/deselects the associated memory chip. the signals casn, rasn, wen and oen are active low. 7.10.3.2 dram initialization after the external reset signal resetn becomes inactive, the dram interface immediately starts generating a dram initialization sequence. first, the row address strobe (rasn) and column address strobe (casn) are kept stable in high state for a minimum of 200 m s. after this the dram interface generates a sequence of initialization pulses. this sequence consists of 9 casn cycles before rasn refresh (cbr) events (see fig.15). 2000 may 03 42 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h 7.10.3.3 dram refresh the dram interface takes care of periodically refresh of the external dram. refresh is carried out by addressing the specific dram page. it should be noted that refresh only works if the SAA6750h is in operating mode (see table 1). 7.10.3.4 memory sharing the SAA6750h can be part of a system in which it shares the memory with other devices. to this end the dram interface output ports of the SAA6750h can be put to 3-state respectively input state by an appropriate setting of the i 2 c-bus control register (see table 1). another ic cannot use the memory concurrently with the SAA6750h. 7.10.3.5 scheduling the dram interface allows access to the external dram once every two clock cycles. therefore the nominal fast page mode cycle time is t pc = 74 ns for a 27 mhz clock. if the dram address changes from one page to another page, which means a change in the most significant 9 bits of the address, a page transition occurs. a page transition also happens, if the data direction changes from read to write or vice versa (a change of the wen signal). a detailed description of the timing can be found in figs 13 and 14 and chapter characteristics. all internal clients of the dram interface are served using a round robin scheme where the access time of each client can be programmed via the i 2 c-bus within some limits. these settings are depending on the embedded microcode and will be provided in the software package. within one macroblock-period, which is defined as 650 clock cycles of the 27 mhz system clock, all clients have to be served at least with two accesses but the sum of all client accesses is not allowed to exceed the time of one macroblock period. 7.11 fifo memories the fifos are data buffers which connect the internal processes. this kind of coupling is necessary because due to the multi-processor architecture e.g. one process may give bursts of data, while the next process consumes the data at constant rate. the state of the fifos therefore also has an impact on the process behaviour. as long as the fifo buffers are not full or empty, the depending processes work at their normal speed. if a data read or write request from or to a fifo cannot be served, the depending process is interrupted. 7.12 clock distribution the SAA6750h needs a video clock signal vclk as specified in chapter quick reference data. the external clock signal has to be synchronous to the video input data stream. in the standard application e.g. the clock signal is provided by a saa7111a colour decoder. the internal clock generation unit creates all internal processing clocks. 7.13 input/output levels all input and i/o pad cells are 5 v tolerant. the output and i/o pad cells provide 3.3 v output levels. see chapters quick reference data and limiting values for detailed information. 7.14 boundary scan test 7.14.1 g eneral the SAA6750h has built-in logic and 5 dedicated pins to support boundary scan testing, which allows board testing without special hardware (nails). the SAA6750h follows the ieee std. 1149.1 - standard test access port and boundary scan architecture set by the joint test action group (jtag) chaired by philips. the 5 special pins are test mode select (tms), test clock (tck), test reset (trst), test data input (tdi) and test data output (tdo). the boundary scan test (bst) functions bypass, extest, sample, clamp and idcode are all supported (see table 25). details about the jtag bst-test can be found in the specification ieee std. 1149.1 . a file containing the detailed boundary scan description language (bsdl) description of the SAA6750h is available on request. 2000 may 03 43 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h table 25 boundary scan test (bst) instructions supported by the SAA6750h instruction description bypass this mandatory instruction provides a minimum length serial path (1 bit) between tdi and tdo, when no test operation of the component is required. extest this mandatory instruction allows testing of off-chip circuitry and board level interconnections. sample this mandatory instruction can be used to take a sample of the inputs during normal operating of the component. it can also be used to preload data values into the latched outputs of the boundary scan register. clamp this optional instruction is useful for testing, when not all ics have bst. this instruction addresses the bypass register, while the boundary scan register is in external test mode. idcode this optional instruction will provide information on the components manufacturer, part number and version number. 7.14.2 i nitialization of boundary scan circuit the test access port (tap) controller of an ic should be in the reset state (test_logic_reset), when the ic is in functional mode. this reset state also forces the instruction register into a functional instruction such as idcode or bypass. to solve the power-up reset, the standard specifies that the tap controller will be forced asynchronously to the test_logic_reset state by setting pin trst to low. 7.14.3 d evice identification codes a device identification register is specified in ieee std. 1149.1-1990 -ieee standard test access port and boundary scan architecture . it is a 32-bit register which contains fields for the specification of the ic manufacturer, the ic part number and the ic version number. its biggest advantage is the possibility to check for the correct ics mounted after production and determination of the version number of ics during field service. when the idcode instruction is loaded into the bst instruction register, the identification register will be connected between tdi and tdo of the ic. the identification register will load a component specific code during the capture_data_register state of the tap controller and this code can subsequently be shifted out. at board level this code can be used to verify component manufacturer, type and version number. the device identification register contains 32 bits, numbered 31 to 0, where bit 31 is the most significant bit (nearest to tdi) and bit 0 is the least significant bit (nearest to tdo); see fig.11. handbook, full pagewidth mhb670 31 28 27 11 12 1 0 msb lsb 0001 0010 1011 0110 0000 0000 0010 101 4 bits version code 16-bit part number 11-bit manufacturer identification 1 tdi tdo fig.11 32 bits of identification code. 2000 may 03 44 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h 8 limiting values in accordance with the absolute maximum rating system (iec 60134). notes 1. all input pads, input/output pads in input mode and output pads in 3-state mode are 5 v tolerant. 2. human body model: c = 100 pf; r = 1.5 k w . 3. machine model: c = 200 pf; l = 0.75 m h; r = 0 w . 9 thermal characteristics symbol parameter conditions min. max. unit v dd digital supply voltage - 0.5 +4.0 v v i digital input voltage note 1 - 0.5 +5.5 v v o digital output voltage - 0.5 v dd + 0.5 v i lu(prot) latch-up protection current - 100 ma p tot total power dissipation - 2.0 w t stg storage temperature - 25 +150 c t amb ambient temperature 0 70 c v es electrostatic handling voltage note 2 - 2000 +2000 v note 3 - 200 +200 v symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air; soldered to a pcb with supply and ground plane 28 k/w 2000 may 03 45 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h 10 characteristics v ddco = 3.3 v; v dd = 3.3 v; supply voltages v dd and v ddco are connected externally together; grounds v ss and v ssco are connected externally together; t amb =25 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supplies: v dd and v ddco v dd digital supply voltage (i/o cells) 3.0 3.3 3.6 v v ddco digital supply voltage (core) 3.0 3.3 3.6 v i dd digital supply current (i/o cells) - 40 - ma i ddco digital supply current (core) - 180 - ma i dd(tot) total digital supply current - 0.22 0.56 a p tot total power dissipation - 0.73 2.0 w inputs: yuv7 to yuv0, fid, hsync, vsync, vclk, resetn, mad, fad_rwn, fad_en, as_ale, ds_rdn, cs_test and test; note 1 v il low-level input voltage - 0.5 - +0.8 v v ih high-level input voltage v dd = 3.6 v 2.0 - 5.5 v i il low-level input current v il =v ss -- 1 m a i ih high-level input current v ih =v dd - 1 --m a c i input capacitance -- 10 pf inputs: trst, tck, tms, tdi, i_mn and csn; notes 1 and 2 v il low-level input voltage - 0.5 - +0.8 v v ih high-level input voltage v dd = 3.6 v 2.0 - 5.5 v i pu pull-up input current v il =v ss -- 125 m a i ih high-level input current v ih =v dd - 10 --m a c i input capacitance -- 10 pf inputs/outputs (3-state): data63 to data0, ad15 to ad0, gpio11 to gpio0; note 1 v il low-level input voltage - 0.5 - +0.8 v v ih high-level input voltage v dd = 3.6 v 2.0 - 5.5 v v ol low-level output voltage 3 ma sink current -- 0.4 v v oh high-level output voltage 3 ma load current 2.4 - v dd v i tl 3-state leakage current v ih =v dd ; v il =v ss - 5 - +5 m a c i input capacitance -- 10 pf c l load capacitance -- 40 pf output (3-state): tdo; note 3 v ol low-level output voltage 3 ma sink current -- 0.4 v v oh high-level output voltage 3 ma load current 2.4 - v dd v i tl 3-state leakage current v ih =v dd; v il =v ss - 5 - +5 m a c l load capacitance -- 40 pf 2000 may 03 46 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h outputs (3-state): adr8 to adr0, casn, rasn, wen and oen; note 3 v ol low-level output voltage 3 ma sink current; casn: 6 ma sink current -- 0.4 v v oh high-level output voltage 3 ma load current; casn: 6 ma load current 2.4 - v dd v i tl 3-state leakage current v ih =v dd; v il =v ss - 5 - +5 m a c l load capacitance any pin except casn -- 40 pf only casn pin -- 60 pf outputs (open-drain): lrqn, urqn, dtack_rdy and fad_rdyn; note 4 v ol low-level output voltage 3 ma sink current -- 0.4 v v oh high-level output voltage 2.4 - v dd v i sl switch-off leakage current v oh =v dd - 5 --m a c l load capacitance -- 40 pf video clock input timing: vclk; see fig.12 t cy cycle time 35 37 39 ns d duty factor t high /t cy 40 50 60 % t r(vclk) rise time v dd = 0.8 to 2.0 v -- 5ns t f(vclk) fall time v dd = 2.0 to 0.8 v -- 6ns video input data and control input timing: yuv7 to yuv0, fid, hsync and vsync; see fig.12 t su; dat data set-up time 6 -- ns t hd; dat data hold time 3 -- ns symbol parameter conditions min. typ. max. unit 2000 may 03 47 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h dram interface data, address and control timing: data63 to data0, adr8 to adr0, casn, rasn, wen and oen; see figs 13 to 15 t pc fast page mode cycle time 60 2t cy - ns t rp rasn precharge time 60 2t cy - ns t rhcp rasn hold time from casn precharge 60 2t cy - ns t rdh read data hold time 0 -- ns t cas casn pulse width 30 t cy 45 ns t cp precharge time (page mode) 30 t cy - ns t rcs read command set-up time 60 2t cy - ns t rch read command hold time referenced to casn 30 t cy - ns t wcs wen set-up time 60 2t cy - ns t wch wen hold time referenced to casn 30 2t cy - ns t rrh read command hold time referenced to rasn 30 t cy - ns t css chip select oen set-up time 60 2t cy - ns t csh chip select oen hold time referenced to casn 0 -- ns t asr row address set-up time 20 t cy - ns t rah row address hold time 12 1 2 t cy - ns t asc column address set-up time 10 note 5 - ns t cah column address hold time 20 t cy - ns t ds data write set-up time 20 t cy - ns t dh data write hold time 20 t cy - ns t rac access time from rasn -- 60 ns t cac access time from casn -- 20 ns t rci read/write cycle time in initialization mode 160 5t cy - ns t rasi rasn pulse width in initialization mode 100 3t cy - ns t csr casn set-up time 30 t cy - ns t chr casn hold time 30 t cy - ns symbol parameter conditions min. typ. max. unit 2000 may 03 48 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h notes 1. all input pins are 5 v tolerant. 2. in accordance with the ieee1149.1 standard the input pins tck, tdi, tms and trst must have an internal pull-up resistor. 3. the outputs, which can be switched in the 3-state mode, are 5 v tolerant due to the bus application of 5 v. 4. the open-drain outputs, which can be switched off, are 5 v tolerant due to the 5 v application. 5. 1 2 t cy applies for ?rst column address after a row address, t cy for all other modes. 6. typical values are maximum when data is available. 7. i/o pins of the i 2 c-bus interface must not obstruct the sda and scl lines if the supply voltage v dd is switched off. data output interface timing: dtack_rdy, i_mn, csn, as_ale, ds_rdn and ad15 to ad0; see figs 16 and 17 and table 13 t as address set-up time 15 -- ns t ah address hold time 20 -- ns t az address 3-state time 20 -- ns t cs csn set-up time 0 -- ns t dhr data hold time read 0 -- ns t dsr data set-up time read 0 -- ns t idl as pulse width 60 -- ns t drtl dtack reaction time low note 6 - 2t cy - ns t drth dtack reaction time high - t cy - ns t rwi read/write or data strobe pulse width 60 -- ns t dz data 3-state 0 - 60 ns i 2 c-bus interface: scl and sda; note 7 f scl scl clock frequency 100 - 400 khz v il low-level input voltage -- 0.3v dd v v ih high-level input voltage 0.7v dd - 5.5 v i i input current - 10 - +10 m a v ol low-level output voltage 3 ma sink current 0 - 0.4 v 6 ma sink current 0 - 0.6 v t low scl low time 1.3 --m s t high scl high time 0.6 --m s t r rise time sda and scl -- 0.3 m s t f fall time sda and scl -- 0.3 m s t su;dat data set-up time 100 -- ns t hd;sta hold time start condition 0.6 --m s t su;sto set-up time stop condition 0.6 --m s symbol parameter conditions min. typ. max. unit 2000 may 03 49 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h handbook, full pagewidth mhb671 t high t low t cy t su;dat t hd;dat t oh;dat t f(vclk) t r(vclk) valid data and control inputs vclk not valid valid 2.0 v 0.8 v 1.5 v 0.8 v valid data and control outputs not valid valid 2.4 v 0.4 v 2.0 v fig.12 clock data timing. 2000 may 03 50 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h h andbook, full pagewidth mhb672 t rp t rhcp t cas t wcs t pc t wch t rrh t ds t asc t asr high rasn casn wen oen adr8 to adr0 data63 to data0 t dh t cah t cp t rah data5 data4 data3 data2 data1 ra ca1 ca2 ca3 ca4 ca5 fig.13 dram fast page mode write cycles to external dram. ra = row address. ca = column address. 2000 may 03 51 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h handbook, full pagewidth mhb673 t rp t rhcp t cas t css t rdh t pc t rch t csh t rrh t asc t asr rasn casn wen oen adr8 to adr0 data63 to data0 t cah t cp t rac t cac t rah t rcs data4 data3 data2 data1 xxxx ra ca1 ca2 ca3 ca4 ca5 fig.14 dram fast page mode read cycles from external dram. ra = row address. ca = column address. handbook, full pagewidth mhb674 t rp 9 cycles are provided t rp t csr casn rasn t chr t rasi t rci t vclk fig.15 dram initialization sequence. 2000 may 03 52 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h handbook, full pagewidth mhb675 address low high i_mn dtack_rdy ds_rdn as_ale ad15 to ad0 csn address address phase t ah t as t rwi t idl t dz t dhr t az t dsr t drtl t drth first data phase second data phase stop read data read data fig.16 motorola-style protocol mode (internal address decoding). handbook, full pagewidth mhb676 low high i_mn dtack_rdy ds_rdn as_ale ad15 to ad0 csn address phase t rwi t idl t dz t dhr t dsr t cs t drtl t drth first data phase second data phase stop read data read data fig.17 motorola-style protocol mode (external address decoding). 2000 may 03 53 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h 11 application information handbook, full pagewidth mhb677 audio clock audio data pci to scsi saa7146a pci bridge i 2 c-bus pci-bus debi d1 i 2 s i 2 c d1 audio input (analog) saa1309 audio ad/da audio output (analog) s-video or cvbs input (analog) s-video or cvbs output (analog) saa7112 / saa7114 cvbs decoder cvbs es data saa7185 video encoder SAA6750h mpeg2 video encoder 16 mbit external dram harddisk vga monitor cpu and memory fig.18 pc application circuit. 2000 may 03 54 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h 12 package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 0.50 0.25 3.6 3.2 0.25 0.27 0.17 0.20 0.09 28.1 27.9 0.5 30.9 30.3 1.39 1.11 8 0 o o 0.08 0.2 1.3 0.08 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot316-1 ms-029 99-12-27 00-01-25 d (1) (1) (1) 28.1 27.9 h d 30.9 30.3 e z 1.39 1.11 d pin 1 index b p e q e a 1 a l p detail x l (a ) 3 b 52 c d h b p e h a 2 v m b d z d a z e e v m a x 1 208 157 156 105 104 53 y w m w m 0 5 10 mm scale 208 leads (lead length 1.3 mm); body 28 x 28 x 3.4 mm; high stand-off height sqfp208: plastic shrink quad flat package; sot316-1 a max. 4.10 2000 may 03 55 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h 13 soldering 13.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering is not always suitable for surface mount ics, or for printed-circuit boards with high population densities. in these situations reflow soldering is often used. 13.2 re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 230 c. 13.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 13.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 2000 may 03 56 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h 13.5 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 4. wave soldering is only suitable for lqfp, tqfp and qfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 14 data sheet status note 1. please consult the most recently issued data sheet before initiating or completing a design. package soldering method wave reflow (1) bga, lfbga, sqfp, tfbga not suitable suitable hbcc, hlqfp, hsqfp, hsop, htqfp, htssop, sms not suitable (2) suitable plcc (3) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (3)(4) suitable ssop, tssop, vso not recommended (5) suitable data sheet status product status definitions (1) objective speci?cation development this data sheet contains the design target or goal speci?cations for product development. speci?cation may change in any manner without notice. preliminary speci?cation quali?cation this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. product speci?cation production this data sheet contains ?nal speci?cations. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. 2000 may 03 57 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h 15 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 16 disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 17 purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011. 2000 may 03 58 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h notes 2000 may 03 59 philips semiconductors product speci?cation encoder for mpeg2 image recording (empire) SAA6750h notes ? philips electronics n.v. sca all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. internet: http://www.semiconductors.philips.com 2000 69 philips semiconductors C a worldwide company for all other countries apply to: philips semiconductors, international marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 3 figtree drive, homebush, nsw 2140, tel. +61 2 9704 8141, fax. +61 2 9704 8139 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101 1248, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 20 0733, fax. +375 172 20 0773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 68 9211, fax. +359 2 68 9102 canada: philips semiconductors/components, tel. +1 800 234 7381, fax. +1 800 943 0087 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: sydhavnsgade 23, 1780 copenhagen v, tel. +45 33 29 3333, fax. +45 33 29 3905 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615 800, fax. +358 9 6158 0920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 4099 6161, fax. +33 1 4099 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 2353 60, fax. +49 40 2353 6300 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: pt philips development corporation, semiconductors division, gedung philips, jl. buncit raya kav.99-100, jakarta 12510, tel. +62 21 794 0040 ext. 2501, fax. +62 21 794 0080 ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, via casati, 23 - 20052 monza (mi), tel. +39 039 203 6838, fax +39 039 203 6800 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5057 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381, fax +9-5 800 943 0087 middle east: see italy netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland : al.jerozolimskie 195 b, 02-222 warsaw, tel. +48 22 5710 000, fax. +48 22 5710 001 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 319762, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 58088 newville 2114, tel. +27 11 471 5401, fax. +27 11 471 5398 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 93 301 6312, fax. +34 93 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 5985 2000, fax. +46 8 5985 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2741 fax. +41 1 488 3263 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2886, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: yukari dudullu, org. san. blg., 2.cad. nr. 28 81260 umraniye, istanbul, tel. +90 216 522 1500, fax. +90 216 522 1813 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 208 730 5000, fax. +44 208 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381, fax. +1 800 943 0087 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 3341 299, fax.+381 11 3342 553 printed in the netherlands 753504/25/02/pp 60 date of release: 2000 may 03 document order number: 9397 750 06806 |
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