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| pci2060 asynchronous pci-to-pci bridge data manual literature number: scps096a april 2005 printed on recycled pape r
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband interface interface.ti.com digital control www.ti.com/digitalcontrol logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security telephony www.ti.com/telephony video & imaging www.ti.com/video wireless www.ti.com/wireless mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2005, texas instruments incorporated iii april 2005 scps096a contents section page 1 pci2060 features 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 introduction 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 description 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 related documents 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 trademarks 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 document conventions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 ordering information 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 terminal assignments 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 terminal descriptions 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 principles of operation 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 types of transactions 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 decoding options 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 configuration cycles 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 type 0 configuration transaction 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 type 1 to type 0 translation 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3 type 1 to type 1 forwarding 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4 special cycle 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 write transaction 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1 posted write transaction 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 delayed write transaction 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.3 discard timer 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.4 write transaction address boundaries 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.5 fast back-to-back write transactions 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.6 write combining 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 read transactions 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 prefetchable read transactions 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.2 prefetch optimization 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.3 nonprefetchable read transactions 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.4 delayed read transaction 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.5 discard timer 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 transaction termination 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.1 termination initiated by the master 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.2 termination initiated by the target 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 bus arbitrations 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.1 primary bus arbitration 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.2 internal secondary bus arbitration 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.3 external secondary bus arbitration 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 parity error handling 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.1 address parity error 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.2 data parity error 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 system error handling 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10 clocks 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.1 secondary bus clock behavior 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11 interrupt routing 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12 mode selection 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12.1 compactpci hot-swap support 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12.2 pci power management 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . contents iv april 2005 scps096a section page 3.13 jtag support 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.1 test port instructions 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.2 instruction register 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.3 1-bit bypass register 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.4 boundary scan register 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.14 gpio interface 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.14.1 secondary clock mask 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.14.2 transaction forwarding control 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 configuration header space 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 vendor id register (00h) 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 device id register (02h) 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 primary command register (04h) 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 primary status register (06h) 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 revision id register (08h) 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 programming interface register (09h) 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 subclass code register (0ah) 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8 base class code register (0bh) 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9 cache line size register (0ch) 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10 primary latency timer register (0dh) 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11 header type register (0eh) 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.12 bist register (0fh) 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.13 primary bus number register (18h) 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.14 secondary bus number register (19h) 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.15 subordinate bus number register (1ah) 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.16 secondary latency timer register (1bh) 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.17 i/o base address register (1ch) 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.18 i/o limit address register (1dh) 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.19 secondary status register (1eh) 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.20 memory base address register (20h) 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.21 memory limit address register (22h) 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.22 prefetchable memory base address register (24h) 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.23 prefetchable memory limit address register (26h) 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.24 prefetchable memory base address upper 32-bit register (28h) 45 . . . . . . . . . . . . . . . . . . . . . . . . 4.25 prefetchable memory limit address upper 32-bit register (2ch) 45 . . . . . . . . . . . . . . . . . . . . . . . . 4.26 i/o base-address upper 16-bit register (30h) 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.27 i/o limit-address upper 16-bit register (32h) 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.28 capabilities pointer register (34h) 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.29 interrupt line register (3ch) 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.30 interrupt pin register (3dh) 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.31 bridge control register (3eh) 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 extension registers 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 chip control register (40h) 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 extended diagnostic register (41h) 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 arbiter control register (42h) 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 p_serr event disable register (64h) 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 gpio output data register (65h) 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 gpio output enable register (66h) 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7 gpio input data register (67h) 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v april 2005 scps096a section page 5.8 secondary clock control register (68h) 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.9 p_serr status register (6ah) 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.10 capability id register (dch) 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.11 next item pointer register (ddh) 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.12 power-management capabilities register (deh) 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.13 power-management control/status register (e0h) 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.14 power-management bridge-support extension register (e2h) 56 . . . . . . . . . . . . . . . . . . . . . . . . . . 5.15 power-management data register (e3h) 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.16 hot-swap capability id register (e4h) 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.17 hot-swap next-item pointer register (e5h) 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.18 hot-swap control and status register (e6h) 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.19 ti diagnostic register (f0h) 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 electrical characteristics 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 absolute maximum ratings over operating temperature ranges ? 59 . . . . . . . . . . . . . . . . . . . . . 6.2 recommended operating conditions (see note 3) 60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 electrical characteristics over recommended operating conditions 61 . . . . . . . . . . . . . . . . . . . . 6.4 66-mhz pci clock signal ac parameters 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 66-mhz pci signal timing 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6 parameter measurement information 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7 pci bus parameter measurement information 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 mechanical data 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figures vi april 2005 scps096a list of figures figure page 2?1 pci2060 ghk-package terminal diagram 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?1 system block diagram 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?2 secondary clock block diagram 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?3 clock mask read timing after reset 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?1 pci clock signal ac parameter measurements 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?3 load circuit and voltage waveforms 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?4 rstin timing waveforms 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii april 2005 scps096a list of tables table page 2?1 257-terminal ghk signal names sorted by terminal number 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?2 257-terminal ghk signal names sorted alphabetically 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?3 pci primary bus terminals 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?4 pci primary bus address and data terminals 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?5 pci primary bus control terminals 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?6 pci secondary bus system terminals 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?7 pci secondary bus address and data terminals 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?8 pci secondary bus control terminals 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?9 miscellaneous terminals 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?10 jtag terminals 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?11 power supply terminals 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?12 no connect terminals 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?1 pci2060 pci transactions 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?2 pci ad31?ad0 during address phase of a type 0 configuration type 17 . . . . . . . . . . . . . . . . . . . . . . . . . 3?3 pci ad31?ad0 during address phase of a type 1 configuration type 17 . . . . . . . . . . . . . . . . . . . . . . . . . 3?4 device number to idsel s_ad pin mapping 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?5 write transaction forwarding 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?6 write transaction disconnect address boundaries 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?7 read behavior 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?8 read connect threshold level 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?9 config66, p_m66ena, and s_m66ena configuration 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?10 sec_async_sel and sec_async_rate configuration 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?11 config66, p_m66ena, s_m66ena, sec_async_sel, and sec_async_rate configuration 28 3?12 interrupt routing scheme 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?13 mode selections 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?14 jtag instructions and op codes 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?15 boundary scan terminal order 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?16 clock mask data format 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?1 pci configuration header space 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?2 primary command register 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?3 primary status register 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?4 i/o base register 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?5 i/o limit address register 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?6 secondary status register 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?7 memory base address register 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?8 memory limit address register 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?9 prefetchable memory base address register 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?10 prefetchable memory limit address register 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?11 prefetchable memory base address upper 32-bit register 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?12 prefetchable memory limit address upper 32-bit register 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?13 i/o base-address upper 16-bit register 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?14 i/o limit-address upper 16-bit register 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?15 bridge control register 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?1 chip control register 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?2 extended diagnostic register 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?3 arbiter control register 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?4 p_serr event disable register 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tables viii april 2005 scps096a table page 5?5 gpio output data register 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?6 gpio output enable register 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?7 gpio input data register 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?8 secondary clock control register 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?9 p_serr status register 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?10 power-management capabilities register 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?11 power-management control/status register 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?12 power-management bridge-support extension register 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?13 hot-swap control and status register (e6h) 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?14 ti diagnostic register 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . features 1 april 2005 scps096a 1 pci2060 features fully supports pci local bus specification , revision 2.3 fully supports pci-to-pci bridge specification , revision 1.1 fully supports advanced configuration power interface (acpi) specification architecture configurable for pci bus power management interface specification , revision 1.0 and revision 1.1 two 32-bit, 66-mhz asynchronous pci buses 1.8-v core logic with universal pci interface compatible with 3.3-v and 5-v pci signaling environments provides concurrent primary and secondary bus operations independent read and write buffers for each direction burst data transfers with pipeline architecture to maximize data throughput in both directions up to three delayed transactions for all pci configuration, i/o, and memory read commands in both directions provides 10 secondary pci bus clock outputs provides internal two-tier arbitration for up to nine secondary bus masters provides external arbitration option provides compactpci tm hot-swap functionality provides a 4-terminal general-purpose i/o interface provides an ieee standard 1149.1 joint test action group (jtag) interface packaged in 257-terminal pbga package table 1?1. figure 1?1. microstar bga is a trademark of texas instruments. other trademarks are the property of their respective owners. introduction 2 april 2005 scps096a 2 introduction 2.1 description the texas instruments pci2060 is a 32-bit, asynchronous, pci-to-pci bridge that is fully compliant with the pci local bus specification , revision 2.3 and the pci-to-pci bridge specification , revision 1.1. the pci2060 bridge makes it possible for the primary and secondary bus clocks to be completely asynchronous and supports the pci clock frequency up to 66 mhz. the pci2060 bridge is architecture-configurable for the pci bus power interface specification . it can be configured to support either revision 1.0 or revision 1.1. power conservation is made possible by using 1.8-v core logic with a universal pci interface compatible with 3.3-v and 5-v pci signaling environments. the pci2060 bridge allows the primary and secondary buses to operate concurrently. it provides independent read and write buffers for each direction and utilizes pipeline architecture for burst data transfer. the pci2060 bridge makes it possible to overcome the electrical loading limit of ten devices per pci bus and one pci device per expansion slot by creating hierarchical buses. each pci2060 bridge that is added to the system creates a new pci bus. the pci2060 bridge provides a two-tier internal arbitration for up to nine secondary bus masters and may be implemented with an external arbiter. the pci2060 bridge provides compactpci hot-swap support that is compliant with the picmg compactpci hot-swap specification, revision 1.0. 2.2 related documents ? advanced configuration and power interface (acpi) specification, revision 2.0 ? pci local bus specification, revision 2.3 ? pci-to-pci bridge specification, revision 1.1 ? pci bus power management interface specification, revision 1.1 ? picmg compactpci hot-swap specification, revision 1.0 ? ieee standard test access port and boundary-scan architecture 2.3 trademarks ? compactpci is a trademark of picmg ? pci industrial computer manufacturers group, inc. ? intel is a trademark of intel corporation. ? ti and microstar bga are trademarks of texas instruments ? other trademarks are the property of their respective owners 2.4 document conventions throughout this data manual, several conventions are used to convey information. these conventions are listed below: 1. to identify a binary number or field, a lower case b follows the numbers. for example: 000b is a 3-bit binary field. 2. to identify a hexadecimal number or field, a lower case h follows the numbers. for example: 8afh is a 12-bit hexadecimal field. 3. all other numbers that appear in this document that do not have either a b or h following the number are assumed to be decimal format. 4. if the signal or terminal name has a bar above the name (for example, p_rst ), then this indicates the logical not function. when asserted, this signal is a logic low, 0, or 0b. 5. rsvd indicates that the referenced item is reserved. introduction 3 april 2005 scps096a 2.5 ordering information ordering number voltage temperature package pci2060 3.3-v, 5-v tolerant i/os 0 0 c to 70 0 c 257-terminal ghk pci2060i 3.3-v, 5-v tolerant i/os ?40 0 c to 85 0 c 257-terminal ghk 2.6 terminal assignments the pci2060 bridge is packaged in a 257-terminal ghk microstar bga tm . figure 2?1 is a ghk-package terminal diagram. table 2?1 lists the terminal assignments in terminal-number order with corresponding signal names for the ghk package. table 2?2 lists the terminal assignments arranged in alphanumerical order by signal name with corresponding terminal numbers for the ghk package. terminal e5 on the ghk package is an identification ball used for device orientation. 7 j b a 1 d c e g f h 24 3 6 5 t k m l p n r w u v 12 8 9 10 11 15 14 13 16 17 18 19 bottom view figure 2?1. pci2060 ghk-package terminal diagram introduction 4 april 2005 scps096a table 2?1. 257-terminal ghk signal names sorted by terminal number ghk number signal name ghk number signal name ghk number signal name ghk number signal name a2 nc c8 v cc f11 s_frame k14 tms a3 v cc c9 s_ad18 f12 s_c/be1 k15 v cc a4 s_ad31 c10 nc f13 gnd k17 tdo a5 s_ad28 c11 s_irdy f14 s_ad9 k18 tdi a6 s_ad25 c12 s_lock f15 s_ad10 k19 nc a7 gnd c13 s_par f17 s_ad8 l1 s_clkout0 a8 s_ad20 c14 v cc f18 gnd l2 s_clkout1 a9 v cc c15 gnd f19 s_ad7 l3 nc a10 s_c/be2 c16 nc g1 s_gnt3 l5 s_clkout2 a11 s_devsel c17 nc g2 s_gnt2 l6 gnd a12 gnd c18 nc g3 gnd l14 hsled a13 v cc c19 nc g5 s_req8 l15 hsenum a14 gnd d1 nc g6 s_req3 l17 mask_in a15 s_ad13 d2 v cc g14 s_ad6 l18 config66 a16 v cc d3 nc g15 s_c/be0 l19 p_vio a17 nc d17 nc g17 v cc m1 s_clkout3 a18 nc d18 sec_async_rate g18 s_ad5 m2 v cc b1 nc d19 gnd g19 s_ad4 m3 s_clkout4 b2 nc e1 s_req5 h1 s_gnt7 m5 gnd b3 nc e2 s_req4 h2 s_gnt6 m6 s_clkout5 b4 s_req0 e3 s_req1 h3 s_gnt5 m14 p_ad4 b5 s_ad29 e5 nc h5 s_gnt4 m15 v cc b6 s_ad26 e6 s_ad30 h6 s_gnt1 m17 p_ad1 b7 s_c/be3 e7 gnd h14 s_ad3 m18 p_ad0 b8 s_ad21 e8 s_ad23 h15 gnd m19 gnd b9 nc e9 gnd h17 s_ad2 n1 s_clkout6 b10 gnd e10 s_ad16 h18 v cc n2 s_clkout7 b11 s_trdy e11 v cc h19 s_ad1 n3 v cc b12 s_stop e12 s_perr j1 s_gnt8 n5 bpcce b13 s_serr e13 s_ad15 j2 gnd n6 s_clkout8 b14 s_ad14 e14 s_ad11 j3 s_clk n14 p_ad8 b15 s_ad12 e17 ms0 j5 s_rst n15 v cc b16 nc e18 s_m66ena j6 s_cfn n17 gnd b17 nc e19 v cc j14 gnd n18 p_ad3 b18 nc f1 s_gnt0 j15 s_ad0 n19 p_ad2 b19 nc f2 s_req7 j17 s_vio p1 s_clkout9 c1 sec_async_clk f3 s_req6 j18 trst p2 p_rst c2 nc f5 s_req2 j19 tck p3 p_clk c3 nc f6 v cc k1 gpio3/hsswitch p5 gnd c4 sec_async_sel f7 v cc k2 gpio2 p6 p_req c5 gnd f8 s_ad22 k3 v cc p7 v cc c6 s_ad27 f9 s_ad19 k5 gpio1 p8 v cc c7 s_ad24 f10 s_ad17 k6 gpio0 p9 p_ad18 introduction 5 april 2005 scps096a table 2?1. 257-terminal ghk signal names sorted by terminal number (continued) ghk number signal name ghk number signal name ghk number signal name ghk number signal name p10 p_c/be2 r18 p_c/be0 u15 p_ad10 v18 nc p11 p_trdy r19 gnd u16 nc v19 nc p12 p_lock t1 p_ad30 u17 nc w2 nc p13 p_c/be1 t2 v cc u18 nc w3 nc p14 p_ad12 t3 nc u19 nc w4 v cc p15 v cc t17 nc v1 nc w5 p_ad28 p17 p_ad7 t18 v cc v2 nc w6 p_ad25 p18 p_ad6 t19 ms1 v3 nc w7 p_idsel p19 p_ad5 u1 gnd v4 nc w8 v cc r1 p_gnt u2 nc v5 nc w9 p_ad21 r2 nc u3 nc v6 gnd w10 v cc r3 p_ad31 u4 nc v7 p_c/be3 w11 p_frame r6 p_ad29 u5 gnd v8 p_ad22 w12 p_stop r7 p_ad26 u6 p_ad27 v9 p_ad20 w13 p_serr r8 gnd u7 p_ad24 v10 p_ad17 w14 p_ad15 r9 p_ad19 u8 p_ad23 v11 v cc w15 v cc r10 gnd u9 gnd v12 nc w16 p_m66ena r11 p_devsel u10 p_ad16 v13 p_par w17 gnd r12 p_perr u11 p_irdy v14 gnd w18 nc r13 p_ad14 u12 gnd v15 p_ad11 r14 gnd u13 v cc v16 v cc r17 p_ad9 u14 p_ad13 v17 nc introduction 6 april 2005 scps096a table 2?2. 257-terminal ghk signal names sorted alphabetically signal name ghk number signal name ghk number signal name ghk number signal name ghk number bpcce n5 nc a17 nc w18 p_irdy u11 config66 l18 nc a18 nc w3 p_lock p12 gnd a7 nc b1 p_ad0 m18 p_m66ena w16 gnd a12 nc b2 p_ad1 m17 p_par v13 gnd a14 nc b3 p_ad2 n19 p_perr r12 gnd b10 nc b9 p_ad3 n18 p_req p6 gnd c5 nc b16 p_ad4 m14 p_rst p2 gnd c15 nc b17 p_ad5 p19 p_serr w13 gnd d19 nc b18 p_ad6 p18 p_stop w12 gnd e7 nc b19 p_ad7 p17 p_trdy p11 gnd e9 nc c2 p_ad8 n14 p_vio l19 gnd f13 nc c3 p_ad9 r17 s_ad0 j15 gnd f18 nc c10 p_ad10 u15 s_ad1 h19 gnd g3 nc c16 p_ad11 v15 s_ad2 h17 gnd h15 nc c17 p_ad12 p14 s_ad3 h14 gnd j2 nc c18 p_ad13 u14 s_ad4 g19 gnd j14 nc c19 p_ad14 r13 s_ad5 g18 gnd l6 nc d1 p_ad15 w14 s_ad6 g14 gnd m5 nc d3 p_ad16 u10 s_ad7 f19 gnd m19 nc d17 p_ad17 v10 s_ad8 f17 gnd n17 nc e5 p_ad18 p9 s_ad9 f14 gnd p5 nc k19 p_ad19 r9 s_ad10 f15 gnd r8 nc l3 p_ad20 v9 s_ad11 e14 gnd r10 nc r2 p_ad21 w9 s_ad12 b15 gnd r14 nc t3 p_ad22 v8 s_ad13 a15 gnd r19 nc t17 p_ad23 u8 s_ad14 b14 gnd u1 nc u2 p_ad24 u7 s_ad15 e13 gnd u5 nc u3 p_ad25 w6 s_ad16 e10 gnd u9 nc u4 p_ad26 r7 s_ad17 f10 gnd u12 nc u16 p_ad27 u6 s_ad18 c9 gnd v6 nc u17 p_ad28 w5 s_ad19 f9 gnd v14 nc u18 p_ad29 r6 s_ad20 a8 gnd w17 nc u19 p_ad30 t1 s_ad21 b8 gpio0 k6 nc v1 p_ad31 r3 s_ad22 f8 gpio1 k5 nc v2 p_clk p3 s_ad23 e8 gpio2 k2 nc v3 p_c/be0 r18 s_ad24 c7 gpio3/hsswitch k1 nc v4 p_c/be1 p13 s_ad25 a6 hsenum l15 nc v5 p_c/be2 p10 s_ad26 b6 hsled l14 nc v12 p_c/be3 v7 s_ad27 c6 mask_in l17 nc v17 p_devsel r11 s_ad28 a5 ms0 e17 nc v18 p_frame w11 s_ad29 b5 ms1 t19 nc v19 p_gnt r1 s_ad30 e6 nc a2 nc w2 p_idsel w7 s_ad31 a4 introduction 7 april 2005 scps096a table 2?2. 257-terminal ghk signal names sorted alphabetically (continued) signal name ghk number signal name ghk number signal name ghk number signal name ghk number s_cfn j6 s_gnt1 h6 s_rst j5 v cc h18 s_clk j3 s_gnt2 g2 s_serr b13 v cc k3 s_clkout0 l1 s_gnt3 g1 s_stop b12 v cc k15 s_clkout1 l2 s_gnt4 h5 s_trdy b11 v cc m2 s_clkout2 l5 s_gnt5 h3 s_vio j17 v cc m15 s_clkout3 m1 s_gnt6 h2 tck j19 v cc n3 s_clkout4 m3 s_gnt7 h1 tdi k18 v cc n15 s_clkout5 m6 s_gnt8 j1 tdo k17 v cc p7 s_clkout6 n1 s_irdy c11 tms k14 v cc p8 s_clkout7 n2 s_lock c12 trst j18 v cc p15 s_clkout8 n6 s_m66ena e18 v cc a3 v cc t2 s_clkout9 p1 s_par c13 v cc a9 v cc t18 s_c/be0 g15 s_perr e12 v cc a13 v cc u13 s_c/be1 f12 s_req0 b4 v cc a16 v cc v11 s_c/be2 a10 s_req1 e3 v cc c8 v cc v16 s_c/be3 b7 s_req2 f5 v cc c14 v cc w4 sec_async_clk c1 s_req3 g6 v cc d2 v cc w8 sec_async_rate d18 s_req4 e2 v cc e11 v cc w10 sec_async_sel c4 s_req5 e1 v cc e19 v cc w15 s_devsel a11 s_req6 f3 v cc f6 s_frame f11 s_req7 f2 v cc f7 s_gnt0 f1 s_req8 g5 v cc g17 2.7 terminal descriptions table 2?3 through table 2?12 give a description of the terminals. these terminals are grouped in tables by functionality. each table includes the terminal name, terminal number, i/o type, and terminal description. table 2?3. pci primary bus terminals terminal name ghk number i/o description p_clk p3 i primary pci bus clock. p_clk provides timing for all transactions on the primary pci bus. all primary pci signals are sampled at the rising edge of p_clk. p_rst p2 i pci reset. when the primary pci bus reset is asserted, p_rst causes the bridge to place all output buffers in a high-impedance state and to reset all internal registers. when asserted, the secondary interface is driven low and the device is completely nonfunctional. after p_rst is deasserted, the bridge is in its default state. introduction 8 april 2005 scps096a table 2?4. pci primary bus address and data terminals terminal name ghk number i/o description p_ad31 p_ad30 p_ad29 p_ad28 p_ad27 p_ad26 p_ad25 p_ad24 p_ad23 p_ad22 p_ad21 p_ad20 p_ad19 p_ad18 p_ad17 p_ad16 p_ad15 p_ad14 p_ad13 p_ad12 p_ad11 p_ad10 p_ad9 p_ad8 p_ad7 p_ad6 p_ad5 p_ad4 p_ad3 p_ad2 p_ad1 p_ad0 r3 t1 r6 w5 u6 r7 w6 u7 u8 v8 w9 v9 r9 p9 v10 u10 w14 r13 u14 p14 v15 u15 r17 n14 p17 p18 p19 m14 n18 n19 m17 m18 i/o primary address/data bus. these signals make up the multiplexed pci address and data bus on the primary interface. during the address phase of a primary bus pci cycle, p_ad31 through p_ad0 contain a 32-bit address or other destination information. during the data phase, p_ad31 through p_ad0 contain data. p_c/be3 p_c/be2 p_c/be1 p_c/be0 v7 p10 p13 r18 i/o primary bus commands and byte enables. these signals are multiplexed on the same pci terminals. during the address phase of a primary bus pci cycle, p_c/be3 through p_c/be0 define the bus command. during the data phase, this 4-bit bus is used as a byte enable. the byte enable determines which byte paths of the full 32-bit data bus carry meaningful data. p_c/be0 applies to byte 0 (p_ad7 through p_ad0), p_c/be1 applies to byte 1 (p_ad15 through p_ad8), p_c/be2 applies to byte 2 (p_ad23 through p_ad16), and p_c/be3 applies to byte 3 (p_ad31 through p_ad24). introduction 9 april 2005 scps096a table 2?5. pci primary bus control terminals terminal name ghk number i/o description p_devsel r11 i/o primary device select. the bridge asserts p_devsel to claim a pci cycle as the target device. as a pci master on the primary bus, the bridge monitors p_devsel until a target responds. if no target responds before the time-out occurs, then the bridge terminates the cycle with a master abort. p_frame w11 i/o primary cycle frame. p_frame is driven by the master of a primary bus cycle. p_frame is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. when p_frame is deasserted, the primary bus transaction is in the final data phase. p_gnt r1 i primary bus grant to bridge. p_gnt is driven by the primary pci bus arbiter to grant the bridge access to the primary pci bus after the current data transaction has completed. p_gnt may or may not follow a primary bus request, depending on the primary bus-arbitration algorithm. p_idsel w7 i primary initialization device select. p_idsel selects the bridge during configuration space accesses. p_idsel can be connected to 1 of the upper 24 pci address lines on the primary pci bus. note: there is no idsel signal interfacing the secondary pci bus; thus, the entire configuration space of the bridge can only be accessed from the primary bus. p_irdy u11 i/o primary initiator ready. p_irdy indicates the ability of the primary bus master to complete the current data phase of the transaction. a data phase is completed on a rising edge of p_clk where both p_irdy and p_trdy are asserted. until both p_irdy and p_trdy are sample-asserted, wait states are inserted. p_lock p12 i/o primary pci bus lock. p_lock locks the primary bus and gains exclusive access as a bus master. p_par v13 i/o primary parity. in all primary bus read and write cycles, the bridge calculates even parity across the p_ad and p_c/be buses. as a bus master during pci write cycles, the bridge outputs this parity indicator with a one p_clk delay. as a target during pci read cycles, the calculated parity is compared to the parity indicator of the master; a miscompare can result in a parity error assertion (p_perr ). p_perr r12 i/o primary parity error indicator. p_perr is driven by a primary-bus pci device to indicate the calculated parity does not match p_par when p_perr is enabled through the primary command register (offset 04h). p_req p6 o primary pci bus request. asserted by the bridge to request access to the primary pci bus as a master. p_serr w13 o primary system error. output pulsed from the bridge when enabled through the primary command register (offset 04h) indicating a system error has occurred. the bridge need not be the target of the primary pci cycle to assert this signal. when s_serr is enabled in the bridge control register (offset 3eh), this signal also pulses, indicating that a system error has occurred on one of the subordinate buses downstream from the bridge. p_stop w12 i/o primary cycle stop signal. this signal is driven by a pci target to request that the master stop the current primary bus transaction. this signal is used for target disconnects and is commonly asserted by target devices which do not support burst data transfers. p_trdy p11 i/o primary target ready. p_trdy indicates the ability of the primary bus target to complete the current data phase of the transaction. a data phase is completed upon a rising edge of p_clk where both p_irdy and p_trdy are asserted. until both p_irdy and p_trdy are asserted, wait states are inserted. introduction 10 april 2005 scps096a table 2?6. pci secondary bus system terminals terminal name ghk number i/o description s_clkout9 s_clkout8 s_clkout7 s_clkout6 s_clkout5 s_clkout4 s_clkout3 s_clkout2 s_clkout1 s_clkout0 p1 n6 n2 n1 m6 m3 m1 l5 l2 l1 o secondary pci bus clocks. provide timing for all transactions on the secondary pci bus. each secondary bus device samples all secondary pci signals at the rising edge of the corresponding s_clkout input. s_clk j3 i secondary pci bus clock input. this input synchronizes the pci2060 bridge to the secondary bus clocks. s_cfn j6 i secondary external arbiter enable. when this signal is low, the secondary internal arbiter is enabled. when this signal is high, the secondary external arbiter is enabled. when the external arbiter is enabled, the s_req0 terminal is reconfigured as a secondary bus grant input to the bridge and s_gnt0 is reconfigured as a secondary bus master request to the external arbiter on the secondary bus. s_rst j5 o secondary pci reset. s_rst is the logical or of p_rst and the state of the secondary bus reset bit (bit 6) of the bridge-control register (offset 3eh). s_rst is asynchronous with respect to the state of the secondary interface clk signal. introduction 11 april 2005 scps096a table 2?7. pci secondary bus address and data terminals terminal name ghk number i/o description s_ad31 s_ad30 s_ad29 s_ad28 s_ad27 s_ad26 s_ad25 s_ad24 s_ad23 s_ad22 s_ad21 s_ad20 s_ad19 s_ad18 s_ad17 s_ad16 s_ad15 s_ad14 s_ad13 s_ad12 s_ad11 s_ad10 s_ad9 s_ad8 s_ad7 s_ad6 s_ad5 s_ad4 s_ad3 s_ad2 s_ad1 s_ad0 a4 e6 b5 a5 c6 b6 a6 c7 e8 f8 b8 a8 f9 c9 f10 e10 e13 b14 a15 b15 e14 f15 f14 f17 f19 g14 g18 g19 h14 h17 h19 j15 i/o secondary address/data bus. these signals make up the multiplexed pci address and data bus on the secondary interface. during the address phase of a secondary bus pci cycle, s_ad31 through s_ad0 contain a 32-bit address or other destination information. during the data phase, s_ad31 through s_ad0 contain data. s_c/be3 s_c/be2 s_c/be1 s_c/be0 b7 a10 f12 g15 i/o secondary bus commands and byte enables. these signals are multiplexed on the same pci terminals. during the address phase of a secondary bus pci cycle, s_c/be3 through s_c/be0 define the bus command. during the data phase, this 4-bit bus is used as a byte enable. the byte enable determines which byte paths of the full 32-bit data bus carry meaningful data. s_c/be0 applies to byte 0 (s_ad7 through s_ad0), s_c/be1 applies to byte 1 (s_ad15 through s_ad8), s_c/be2 applies to byte 2 (s_ad23 through s_ad16), and s_c/be3 applies to byte 3 (s_ad31 through s_ad24). introduction 12 april 2005 scps096a table 2?8. pci secondary bus control terminals terminal name ghk number i/o description s_devsel a11 i/o secondary device select. the bridge asserts s_devsel to claim a pci cycle as the target device. as a pci master on the secondary bus, the bridge monitors s_devsel until a target responds. if no target responds before time-out occurs, then the bridge terminates the cycle with a master abort. s_frame f11 i/o secondary cycle frame. s_frame is driven by the master of a secondary bus cycle. s_frame is asserted to indicate that a bus transaction is beginning and data transfers continue while s_frame is asserted. when s_frame is deasserted, the secondary bus transaction is in the final data phase. s_gnt8 s_gnt7 s_gnt6 s_gnt5 s_gnt4 s_gnt3 s_gnt2 s_gnt1 s_gnt0 j1 h1 h2 h3 h5 g1 g2 h6 f1 o secondary bus grant. the bridge provides internal arbitration and these signals grant potential secondary pci bus masters access to the bus. ten potential masters (including the bridge) can be located on the secondary pci bus. when the internal arbiter is disabled, s_gnt0 is reconfigured as an external secondary bus request signal for the bridge. s_irdy c11 i/o secondary initiator ready. s_irdy indicates the ability of the secondary bus master to complete the current data phase of the transaction. a data phase is completed on a rising edge of s_clk where both s_irdy and s_trdy are asserted. until s_irdy and s_trdy are asserted, wait states are inserted. s_lock c12 i/o secondary pci bus lock. s_lock locks the secondary bus and gains exclusive access as a master. s_par c13 i/o secondary parity. in all secondary bus read and write cycles, the bridge calculates even parity across the s_ad and s_c/be buses. as a master during pci write cycles, the bridge outputs this parity indicator with a one s_clk delay. as a target during pci read cycles, the calculated parity is compared to the master parity indicator. a miscompare can result in a parity error assertion (s_perr ). s_perr e12 i/o secondary parity error indicator. s_perr is asserted when a data parity error is detected for data received on the secondary interface. s_req8 s_req7 s_req6 s_req5 s_req4 s_req3 s_req2 s_req1 s_req0 g5 f2 f3 e1 e2 g6 f5 e3 b4 i secondary pci request signals. the bridge provides internal arbitration, and these signals are used as inputs from secondary pci bus masters requesting the bus. ten potential masters (including the bridge) can be located on the secondary pci bus. when the internal arbiter is disabled, the s_req0 signal is reconfigured as an external secondary bus grant for the bridge. s_serr b13 i secondary system error. s_serr is passed through the primary interface by the bridge if enabled through the bridge control register (offset 3eh). s_serr is never asserted by the bridge. s_stop b12 i/o secondary-cycle stop signal. s_stop is driven by a pci target to request that the master stop the current secondary bus transaction. s_stop is used for target disconnects and is commonly asserted by target devices that do not support burst data transfers. s_trdy b11 i/o secondary target ready. s_trdy indicates the ability of the secondary bus target to complete the current data phase of the transaction. a data phase is completed on a rising edge of s_clk where both s_irdy and s_trdy are asserted. until s_irdy and s_trdy are asserted, wait states are inserted. introduction 13 april 2005 scps096a table 2?9. miscellaneous terminals terminal name ghk number i/o description bpcce n5 i bus/power clock-control management terminal. when the bpcce signal is tied high and when the pci2060 bridge is placed in the d3 power state, it enables the pci2060 bridge to place the secondary bus in the b2 power state. the pci2060 bridge disables the secondary clocks and drives them to 0. when tied low, placing the pci2060 bridge in the d3 power state has no effect on the secondary bus clocks. gpio3/ hsswitch gpio2 gpio1 gpio0 k1 k2 k5 k6 i/o general-purpose i/o terminals gpio3 is hsswitch in the compactpci mode. hsswitch provides the status of the ejector handle switch to the compactpci logic. hsenum l15 o hot-swap enum . this signal notifies the host that a card insertion or removal event is pending. hsled l14 o hot-swap led output ms0 e17 i mode select 0 ms1 t19 i mode select 1 p_m66ena w16 i primary interface 66-mhz enable. this input-only signal terminal designates the primary interface bus speed. this signal must be pulled low for 33-mhz operation on the primary bus. in this case, the s_m66ena signal is driven low by the pci2060 bridge, forcing the secondary bus to run at 33 mhz. for 66-mhz operation, this signal must be pulled high. config66 l18 i configure 66-mhz operation. this input-only terminal specifies whether the pci2060 bridge is capable of running at 66 mhz. if this terminal is tied high, then the device can be run at 66 mhz. if this terminal is tied low, then the pci2060 bridge can only function under the 33-mhz pci specification. s_m66ena e18 i/o secondary 66-mhz enable. this signal designates the secondary bus speed. see section 3.10.1 for more detail on the use of the s_m66ena signal. note that s_m66ena is an open-drained output. sec_async_clk c1 i secondary asynchronous clock. this terminal is the secondary clock input when the sec_async_sel terminal is high. sec_async_sel c4 i secondary clock select. this terminal selects the clock that generates the secondary bus clock. if sec_async_sel is low, then the primary pci clock (p_clk) input generates the secondary bus clock. if sec_async_sel is high, then the sec_async_clk generates the secondary bus clock. sec_async_rate d18 i secondary clock rate. this terminal selects the clock speed of the secondary bus clock. if sec_async_rate is low, then the secondary clock outputs are one-half of the input clock frequency. if sec_async_rate is high, then the secondary clock outputs are the same as the input clock frequency. mask_in l17 i secondary clock disable serial input. this input-only signal is used by the hardware mechanism to disable secondary clock outputs. the serial stream is received by the mask_in, starting when p_rst is detected as deasserted and s_rst is detected as asserted. this serial data is used for selectively disabling the secondary clock outputs and is shifted into the secondary clock control register (offset 68h). this input can be tied low to enable all secondary clock outputs or tied high to drive all secondary clock outputs high. introduction 14 april 2005 scps096a table 2?10. jtag terminals terminal name ghk number i/o description tck j19 i jtag boundary scan clock. tck is the clock controlling the jtag logic. tdi k18 i jtag serial data in. tdi is the serial input through which jtag instructions and test data enter the jtag interface. the new data on tdi is sampled on the rising edge of tck. tdo k17 o jtag serial data out. tdo is the serial output through which test instructions and test data from the test logic leave the pci2060 bridge. tms k14 i jtag test mode select. tms causes state transitions in the test-access port controller. trst j18 i jtag reset. when trst is asserted low, the tap controller is asynchronously forced to enter a reset state and initialize the test logic. table 2?11. power supply terminals terminal description name ghk number description v cc a3, a9, a13, a16, c8, c14, d2, e11, e19, f6, f7, g17, h18, k3, k15, m2, m15, n3, n15, p7, p8, p15, t2, t18, u13, v11, v16, w4, w8, w10, w15 3.3-v power terminals gnd a7, a12, a14, b10, c5, c15, d19, e7, e9, f13, f18, g3, h15, j2, j14, l6, m5, m19, n17, p5, r8, r10, r14, r19, u1, u5, u9, u12, v6, v14, w17 device ground terminals p_vio l19 primary interface i/o voltage. this signal must be tied to either 3.3 v or 5 v, corresponding to the signaling environment of the primary pci bus as described in the pci local bus specification , revision 2.3. when any device on the primary pci bus uses 5-v signaling levels, tie p_vio to 5 v. when all the devices on the primary bus use 3.3-v signaling levels, tie p_vio to 3.3 v. s_vio j17 secondary interface i/o voltage. this signal must be tied to either 3.3 v or 5 v, corresponding to the signaling environment of the secondary pci bus as described in the pci local bus specification , revision 2.3. when any device on the secondary pci bus uses 5-v signaling levels, tie s_vio to 5 v. when all the devices on the secondary bus use 3.3-v signaling levels, tie s_vio to 3.3 v. table 2?12. no connect terminals terminal description name ghk number description nc a2, a17, a18, b1, b2, b3, b9, b16, b17, b18, b19, c2, c3, c10, c16, c17, c18, c19, d1, d3, d17, e5, k19, l3, r2, t3, t17, u2, u3, u4, u16, u17, u18, u19, v1, v2, v3, v4,v5, v12, v17, v18, v19, w2, w3, w18 these terminals have no function on the pci2060 bridge. principles of operation 15 april 2005 scps096a 3 principles of operation the pci2060 is a bridge between two pci buses and is compliant with both the pci local bus specification and the pci-to-pci bridge specification . the pci2060 bridge makes it possible for both the primary and secondary bus clocks to be completely asynchronous and supports the pci clock frequency up to 66 mhz. the primary and secondary buses operate independently in either 3.3-v or 5-v signaling environment. the core logic of the bridge, however, is powered at 1.8-v to reduce power consumption. figure 3?1 shows a simplified block diagram of a typical system implementation using the pci2060 bridge. pci option card cpu memory host bridge pci2050b pci device pci device pci bus 0 pci bus 1 host bus pci option slot pci2060 pci device pci device pci bus 2 (option) pci option card figure 3?1. system block diagram host software interacts with the bridge through internal registers. these internal registers provide the standard pci status and control for both the primary and secondary buses. many vendor-specific features that exist in the ti extension register set are included in the bridge. the pci configuration header of the bridge is only accessible from the primary pci interface. the bridge provides internal arbitration for the nine possible secondary bus masters, and provides each with a dedicated active low request/grant pair (req /gnt ). the arbiter features a two-tier rotational scheme with the pci2060 bridge defaulting to the highest priority tier. the pci2060 bridge also supports external arbitration. upon system power up, power-on self-test (post) software configures the bridge according to the devices that exist on subordinate buses, and enables performance-enhancing features of the pci2060 bridge. in a typical system, this is the only communication with the bridge internal register set. 3.1 types of transactions pci bus commands indicate to the target the type of transaction the master is requesting. table 3?1 lists the pci command and name of each pci transaction on the command/byte enable (c/be ) bus during the address phase of a bus cycle. the master and target columns indicate pci2060 support for each transaction when the pci2060 bridge initiates transactions as a master, on the primary bus and on the secondary bus, and when the pci2060 bridge responds to transactions as a target, on the primary bus and on the secondary bus. principles of operation 16 april 2005 scps096a table 3?1. pci2060 pci transactions c/be3 ? c/be0 pci2060 as the master pci2060 as the target c/be3 ? c/be0 primary secondary primary secondary 0000 = interrupt acknowledge no no no no 0001 = special cycle yes yes no no 0010 = i/o read yes yes yes yes 0011 = i/o write yes yes yes yes 0100 = reserved reserved reserved reserved reserved 0101 = reserved reserved reserved reserved reserved 0110 = memory read yes yes yes yes 0111 = memory write yes yes yes yes 1000 = reserved reserved reserved reserved reserved 1001 = reserved reserved reserved reserved reserved 1010 = configuration read no yes yes no 1011 = configuration write type 1 yes yes type 1 1100 = memory read multiple yes yes yes yes 1101 = memory write multiple yes yes yes yes 1110 = memory read line yes yes yes yes 1111 = memory write line yes yes yes yes as a pci master, the pci2060 bridge never initiates the interrupt acknowledge and reserved commands. as a target, the pci2060 bridge ignores the interrupt acknowledge and reserved commands. the pci2060 bridge never responds as a pci target to the special cycle command. the bridge does, however, initiate special cycles on both interfaces when a type 1 configuration cycle issues the special cycle request. the pci2060 bridge never initiates a type 0 configuration transaction on the primary bus. the bridge never responds to a type 0 configuration transaction on the secondary bus. the remaining pci commands address memory, i/o, or configuration space. the bridge accepts pci cycles by asserting devsel as a medium-speed device; for example, devsel is asserted two clock cycles after the address phase. the pci2060 bridge converts memory write-and-invalidate commands to memory write commands when forwarding transactions from either the primary or secondary side of the bridge, if the bridge cannot guarantee that an entire cache line will be delivered. 3.2 decoding options the pci-to-pci bridge architecture specification supports both positive and subtractive decoding. positive decoding is a method of address decoding in which a device responds only to accesses within an assigned address range. subtractive decoding is a method of address decoding in which a device responds only to accesses outside of an assigned address range. the pci2060 bridge supports positive decoding on the primary bus and subtractive decoding on the secondary bus. 3.3 configuration cycles the pci local bus specification defines two types of pci configuration read and write transactions: type 0 and type 1. the bridge decodes each type differently. type 0 configuration transactions are intended for devices on the primary bus, while type 1 configuration transactions are intended for devices on some hierarchically subordinate bus. the difference between these two types of transactions is the encoding of the primary pci (p_ad) bus during the address phase of the transaction. table 3?2 shows the p_ad bus encoding during the address phase of a type 0 configuration transaction. table 3?3 shows the p_ad bus encoding during the address phase of a type 1 configuration transaction. principles of operation 17 april 2005 scps096a table 3?2. pci ad31?ad0 during address phase of a type 0 configuration type 31 11 10 8 7 2 1 0 reserved function number register number 0 0 table 3?3. pci ad31?ad0 during address phase of a type 1 configuration type 31 24 23 16 15 11 10 8 7 2 1 0 reserved bus number device number function number register number 0 1 the 6-bit register number field in both type 0 and type 1 configuration transactions represents an 8-bit address with the two lower bits masked to 00b, indicating a doubleword boundary. this results in a 256-byte configuration address space per function per device. individual byte accesses may be selected within a doubleword by using the p_c/be signals during the data phase of the cycle. 3.3.1 type 0 configuration transaction the pci2060 configuration space is accessed by a type 0 configuration transaction on the primary bus. the bridge never responds to a type 0 configuration transaction on the secondary bus. the pci2060 bridge claims only type 0 configuration cycles when its p_idsel terminal is asserted during the address phase of the configuration cycle and the pci function number encoded in the cycle is 0. if the function number is 1 or greater, then the bridge does not recognize the configuration command. in this case, the bridge does not assert p_devsel and the configuration transaction results in a master abort. the bridge services a valid type 0 configuration read or write cycle by accessing internal registers from the bridge configuration header (see table 4?1). the pci2060 bridge limits all configuration accesses to a single doubleword data transfer and returns a target disconnect with the first data transfer if additional data phases are requested. read transactions to the bridge configuration space do not have side-effects; all bytes in the requested doubleword are returned regardless of the value of the byte-enable bits. 3.3.2 type 1 to type 0 translation the type 1 configuration transactions are intended for devices on some hierarchically subordinate bus. a bridge is the only device that is capable of responding to a type 1 configuration transaction. when the pci2060 bridge claims a type 1 configuration transaction that has a bus number equal to its secondary bus number, the pci2060 bridge converts the type 1 configuration transaction to a type 0 configuration transaction and asserts the proper s_ad line as the idsel (see t able 3?4). the pci2060 bridge can only generate a type 0 configuration on the secondary bus. it can never generate a type 1 configuration on the secondary bus. when the pci2060 bridge converts the type 1 transaction to a type 0 transaction on the secondary bus, it performs the following conversion: ? the two lower address bits on s_ad[1:0] are set to 00b. ? the device number is decoded and drives the bit pattern specified in table 3?4 onto s_ad[31:16] for the purpose of asserting the device?s idsel signal. ? the device number, function number, and register number fields are left unchanged. the mapping of the secondary bus address lines depends on the device number in the type 1 address bits p_ad[15:11]. table 3?4 presents the mapping of the address lines. principles of operation 18 april 2005 scps096a table 3?4. device number to idsel s_ad pin mapping device number secondary idsel s_ad31 ? s_ad16 s_ad asserted 0h 0000 0000 0000 0001 16 1h 0000 0000 0000 0010 17 2h 0000 0000 0000 0100 18 3h 0000 0000 0000 1000 19 4h 0000 0000 0001 0000 20 5h 0000 0000 0010 0000 21 6h 0000 0000 0100 0000 22 7h 0000 0000 1000 0000 23 8h 0000 0001 0000 0000 24 9h 0000 0010 0000 0000 25 ah 0000 0100 0000 0000 26 bh 0000 1000 0000 0000 27 ch 0001 0000 0000 0000 28 dh 0010 0000 0000 0000 29 eh 0100 0000 0000 0000 30 fh 1000 0000 0000 0000 31 10h ? 1eh 0000 0000 0000 0000 ? 3.3.3 type 1 to type 1 forwarding when a type 1 transaction accesses a bus number greater than the bridge secondary bus number but less than or equal to its subordinate bus number, the pci2060 bridge forwards the type 1 transaction as a type 1 transaction on the secondary bus. 3.3.4 special cycle the pci2060 bridge is required to generate special cycles on both buses through a type 1 configuration transaction conversion. during a type 1 configuration transaction on the primary bus, if the bus number field matches the bridge secondary bus number, the device number field is 1fh, and the function number field is 07h, then the bridge generates a special cycle transaction on the secondary bus with a message that matches the data in the type 1 configuration transaction. if the bus number is a subordinate bus and not the secondary bus, then the bridge passes the type 1 special cycle request through to the secondary bus along with the proper message. during a type 1 configuration transaction on the secondary bus, if the bus number field matches the bridge primary bus number, the device number field is 1fh, and the function number field is 07h, then the bridge generates a special cycle transaction on the primary bus with a message that matches the data in the type 1 configuration transaction. special cycle transactions are never passed through the bridge. type 1 configuration transactions with a special cycle request can propagate in both directions. 3.4 write transaction a write transaction is treated as either a posted write or delayed write transaction. t able 3?5 shows the method of forwarding used for each type of write operation. principles of operation 19 april 2005 scps096a table 3?5. write transaction forwarding type of transaction type of forwarding memory write posted memory write-and-invalidate posted i/o write delayed type 1 configuration write delayed 3.4.1 posted write transaction all memory write and memory write-and-invalidate transactions are handled as posted write transactions and must be completed on the destination bus. the pci2060 bridge has two 64-doubleword posted write fifos; one for upstream transaction and the other for downstream transactions (these fifos are shared with delayed request transactions). when a posted write transaction is to be forwarded across the bridge, the pci2060 bridge asserts the devsel with medium timing and the trdy in the same cycle. due to the asynchronous clock implementation, the pci2060 bridge requires eight doublewords of free space in the fifo before it accepts any posted write transactions. the pci2060 bridge continues to accept write data until one of the following events occurs: ? the initiator terminates the transaction by deasserting frame and irdy . ? an internal write address boundary is reached, such as a cache line boundary or an aligned 4-kb boundary, depending on the transaction type. ? the posted write data buffer fills up. when one of the last two events occurs, the pci2060 bridge returns a target disconnect to the requesting initiator to terminate the transaction. once the pci2060 bridge makes a request for the target bus and receives the grant for the target bus, the pci2060 bridge asserts frame and drives the stored write address out on the target bus when the target bus is idle. on the next cycle, the pci2060 bridge drives the first doubleword of the write data and continues to transfer write data until all write data corresponding to that transaction is delivered. the pci2060 bridge ends the transaction on the target bus when one of the following conditions is met: ? all posted write data has been delivered to the target. ? the target returns a target disconnect or a target retry (the pci2060 bridge then starts another transaction to deliver the rest of the write data). ? the target returns a target abort (the pci2060 bridge discards remaining write data). ? the master latency timer expires and the pci2060 bridge no longer has the target bus grant (the pci2060 then starts another transaction to deliver remaining write data). the pci2060 bridge handles memory write-and-invalidate transactions in two different ways: ? if bit 1 (mwi_mw_conversion) in the ti diagnostic register (offset f0h) is cleared to 0b, and the pci2060 bridge has fifo space for a full cache line, then the pci2060 bridge accepts the memory write-and-invalidate transaction. if the pci2060 bridge does not have enough fifo space for a full cache line, then the bridge converts the memory write-and-invalidate transaction to the memory transaction. the pci2060 bridge waits until a full cache line of data is in the fifo before initiating a memory write-and-invalidate transaction on the destination bus. ? if the mwi_mw_conversion bit is set to 1b, then the bridge converts all memory write-and-invalidate transactions to memory write transactions before putting them in the fifo. principles of operation 20 april 2005 scps096a 3.4.2 delayed write transaction a delayed write transaction is used for i/o write transactions and for type 1 configuration write transactions. a delayed write transaction assures that the actual target response is returned back to the initiator without holding the initiating bus in wait states. a delayed write transaction is limited to a single doubleword data transfer. the pci2060 bridge is capable of supporting up to three delayed transactions in each direction at any given time. a delayed write transaction consists of three phases: ? an initiator issues the write request. the pci2060 bridge claims the access by asserting the devsel and returns a target retry to the initiator. ? the pci2060 bridge initiates the write request on the target bus and writes data to the target. if a target retry is received in response to the write transaction on the target bus, the bridge continues to repeat the write transaction until the data transfer is completed, or until an error condition is encountered. if the pci2060 bridge is unable to write the data to the target after 2 24 attempts, then the pci2060 bridge stops further write attempts, discards the write request, returns a target abort to the initiator, and conditionally sets the serr signal. ? the initiator repeats the same write request. if the data has been written to the target, then the pci2060 bridge claims the access by asserting devsel and returns trdy to the initiator to indicate the completion of the write data process. if the data have not been written to the target, then the pci2060 bridge returns a target retry to the initiator. the pci2060 bridge continues to return a target retry to the initiator until either the write data is delivered to the target or until an error condition is encountered. if the initiator requests multiple doublewords, then the pci2060 bridge asserts the stop in conjunction with trdy to signal a target disconnect. 3.4.3 discard timer a discard timer starts counting when the delayed write completion is at the head of the delayed transaction queue. the initial value of this timer can be set to one of two values: 2 10 or 2 15 pci clocks. the value of this timer is selectable through bits 8 and 9 (pri_dis and sec_dt) in the bridge control register (offset 3eh). if the initiator does not repeat the write request before the discard timer expires, then the pci2060 bridge discards the data or the status of the delayed transaction that was completed and conditionally sets the serr signal. 3.4.4 write transaction address boundaries the pci2060 bridge uses the internal address boundaries when accepting write data. when the address boundaries are reached, the pci2060 bridge returns a target disconnect to the initiator. table 3?6 lists the disconnect address boundaries for the write transaction. table 3?6. write transaction disconnect address boundaries type of transaction condition aligned address boundary delayer write all single doubleword posted memory write memory write disconnect bit = 0b queue full or 4-kb boundary posted memory write memory write disconnect bit = 1b queue full, 4-kb boundary, cache line posted memory write-and-invalidate cache line size 1, 2, 4, 8, 16 4-kb boundary posted memory write-and-invalidate cache line size = 1, 2, 4, 8 nth cache line boundary, where a cache line boundary is reached and less than 8 free doublewords of posted write buffer space remain posted memory write-and-invalidate cache line size = 16 16-doubleword aligned address boundary 3.4.5 fast back-to-back write transactions the pci2060 bridge can recognize and post fast back-to-back write transactions. when the pci2060 bridge cannot accept the second transaction because of buffer space limitations, it returns a target retry to the initiator. principles of operation 21 april 2005 scps096a when the pci2060 bridge has posted multiple write transactions, it can initiate fast back-to-back write transactions if bit 9 (fbb_enb) in the primary command register (offset 04h) is set to 1b for upstream write transactions and if bit 7 (fbb_en) in the bridge control register (offset 3eh) is set to 1b for downstream write transactions. 3.4.6 write combining the pci2060 bridge supports write combining for upstream and downstream transactions. this feature combines separate sequential memory write transactions into a single burst transaction. this feature can only be used if the address of the next memory write transaction is the next sequential address after the address of the last doubleword of the previous memory transaction. for example, if the current memory transaction ends at address x and the next memory transaction starts at address x+1, then the pci2060 bridge combines both transactions into a single transaction. the write combining feature of the pci2060 bridge is enabled by default on power-on reset. this feature can be disabled by setting bit 0 (pw_combining_dis) in the ti diagnostics register (offset f0h) to 1b. 3.5 read transactions read transactions are treated as either prefetchable or nonprefetchable. table 3?7 shows the read behavior for each type of read transaction. table 3?7. read behavior type of transaction read behavior condition i/o read nonprefetchable configuration read nonprefetchable memory read nonprefetchable nonprefetchable address space memory read prefetchable prefetchable address space memory read line prefetchable memory read multiple prefetchable 3.5.1 prefetchable read transactions a prefetchable read transaction is a read transaction where the bridge reads data from the target before it is requested by the initiator. memory that is prefetchable has the attribute that it returns the same data when read multiple times and does not alter any other device state when it is read. the bridge is required to discard any prefetched read data not consumed when the initiator concludes the read transaction. prefetchable behavior is used for memory read line and memory read multiple transactions, as well as for memory read transactions that fall into prefetchable memory space. 3.5.2 prefetch optimization the pci2060 bridge incorporates a memory read prefetch optimization method that is intended to improve the performance of an initiating pci master. the prefetch optimization method is used only on read burst transactions (memory read, memory read line, and memory read multiple). the prefetch optimization method is not implemented in the nonburst read transactions. when the target of a read burst transaction is on the opposite side of the pci2060 bridge, the chances of the read being broken up on the initiating bus into multiple transactions increase as the latency between the primary and secondary buses becomes greater. in an effort to reduce the impact on system performance, the pci2060 bridge contains two independent threshold levels. one is called the primary connect threshold level (pctl) and the other is called the secondary connect threshold level (sctl). the pctl is used for transactions that originate from the primary bus and target the secondary bus, while the sctl is used for transactions that originate from the secondary bus and target the primary bus. table 3?8 lists the value used for each threshold level. principles of operation 22 april 2005 scps096a table 3?8. read connect threshold level ratio (pri:sec) pctl (dw) sctl (dw) > 2:1 8 1 2:1 thru 1:2 1 1 <1:2 1 8 the pci2060 bridge uses these threshold levels to know when to provide data to a master. for example, a master initiates a memory-read burst transaction that targets a device on the opposite side of the pci2060 bridge. the pci2060 bridge immediately retries this transaction until the pci2060 bridge has one complete connect threshold level in its fifo. once the level has been reached, the pci2060 bridge provides the data to the master. 3.5.3 nonprefetchable read transactions a nonprefetchable read transaction is a read transaction during which the pci2060 bridge requests only one doubleword from the target and disconnects the initiator after delivery of the first doubleword of the read data. nonprefetchable behavior is used for i/o and configuration read transactions, as well as for memory read transactions that fall into nonprefetchable memory address space. 3.5.4 delayed read transaction all read transactions are delayed read transactions. a delayed read transaction assures that the actual target response is returned back to the initiator without holding the initiating bus in a wait state. the pci2060 bridge is capable of supporting up to three delayed transactions in each direction at any given time. a delayed read transaction consists of three phases: 1. an initiator issues the read request. the pci2060 bridge claims the access by asserting the devsel and returns a target retry to the initiator. 2. the pci2060 bridge initiates the read request on the target bus. if a target retry is received in response to the read transaction on the target bus, then the bridge continues to repeat the write transaction until the data transfer is completed, or until an error condition is encountered. if the pci2060 bridge is unable to read the data from the target after 2 24 attempts, then the pci2060 bridge stops further read attempts, returns a target abort to the initiator, and conditionally sets the serr signal. if the read transaction is terminated via normal master termination or a target disconnect after at least one data transfer has been completed, then the pci2060 bridge does not initiate any further attempts to read more data. 3. the initiator repeats the same read request, the pci2060 bridge claims the access by asserting devsel , and returns trdy and read data to the initiator. the pci2060 bridge returns a target disconnect along with the transfer of the last doubleword of read data to the initiator. if the initiator terminates the transaction before all read data has been transferred, then the remaining read data left in the bridge data buffers is discarded. 3.5.5 discard timer a discard timer starts counting when the delayed read completion is at the head of the delayed transaction queue. the initial value of this timer can be set to one of two values: 2 10 or 2 15 pci clocks. the value of this timer is selectable through bits 8 and 9 (pri_dis and sec_dt) in the bridge control register (offset 3eh). if the initiator does not repeat the read request before the discard timer expires, then the pci2060 bridge discards the read data and the read transaction from its buffer and conditionally sets the serr signal. 3.6 transaction termination either the master or the target may initiate the termination of a pci transaction. an idle state is achieved when the frame and irdy signals are deasserted. principles of operation 23 april 2005 scps096a 3.6.1 termination initiated by the master a termination initiated by the master occurs when frame is deasserted and irdy is still asserted. this condition signals to the target that the final data phase is in progress. the final data transfer occurs when both irdy and trdy are asserted. the transaction is completed when both frame and irdy are deasserted. the master terminates a transaction under following conditions: ? the master has completed the intended transaction to the target. ? with the exception of the memory write-and-invalidate transaction, the master latency timer may have expired and the master gnt line is deasserted. the intended transaction is not necessarily concluded. the timer may have expired because of target-induced access latency or because the intended operation was very long. ? the target terminates the transaction with a retry, a disconnect, or a target abort event. if the master is delivering posted write data when it terminates the transaction because the master latency timer expires, then it initiates another transaction to deliver the remaining write data. the address of the transaction is updated to reflect the address of the current doubleword to be delivered. if the master is prefetching read data when it terminates the transaction because the master latency timer expires, then it does not repeat the transaction to obtain more data. 3.6.2 termination initiated by the target when a target is unable to complete a request initiated by the master, it uses the stop signal to initiate termination of the transaction. the three types of target-initiated terminations are: ? the target returns a target retry to the initiator when it cannot accept write data or return read data because the target is busy and temporarily unable to process the transaction. this can happen if: ? the target is unable to meet the initial latency requirement. ? the target is currently locked by another initiator. ? there is an internal resource conflict. the target signals retry by asserting stop and not asserting trdy on the initial data phase of the transaction. when the target uses retry, no data is transferred. ? the target returns a target disconnect to an initiator when one of the following conditions is met: ? the target hits an internal address boundary. ? the target cannot accept any more write data. ? the target has no more read data to deliver. disconnect with data may be signaled on any data phase by asserting trdy and stop together. this termination is used when the target is only willing to complete the current data phase and no more. disconnect without data may be signaled on any subsequent data phase (meaning data was transferred on the previous data phase) by deasserting trdy and asserting stop . ? the target returns a target abort to an initiator when one of the following conditions is met: ? the target detects a fatal error. ? the target is unable to obtain delayed read data from the target or to deliver delayed write data to the target after 2 24 attempts. the target signals target-abort by deasserting devsel and asserting stop at the same time. principles of operation 24 april 2005 scps096a 3.7 bus arbitrations the pci2060 bridge implements bus request (p_req ) and bus grant (p_gnt ) terminals for primary pci bus arbitration. nine secondary bus requests and nine secondary bus grants are provided on the secondary bus of the pci2060 bridge. ten potential initiators, including the bridge, can be located on the secondary bus. the pci2060 bridge provides a two-tier arbitration scheme on the secondary bus for priority bus-master handling. the two-tier arbitration scheme improves performance in systems in which master devices do not all require the same bandwidth. any ma ster that requires frequent use of the bus can be programmed to be in the higher priority tier. 3.7.1 primary bus arbitration the pci2060 bridge, acting as an initiator on the primary bus, asserts p_req when forwarding transactions upstream to the primary bus. if a target disconnect, a target retry, or a target abort is received in response to a transaction initiated on the primary bus by the pci2060 bridge, then the bridge deasserts p_req for two pci clock cycles. when the primary bus arbiter asserts p_gnt in response to a p_req from the pci2060 bridge, the bridge initiates a transaction on the primary bus during the next pci clock cycle after the primary bus is sampled idle. when p_req is not asserted and the primary bus arbiter asserts p_gnt to the pci2060 bridge, the bridge responds by parking the p_ad31?p_ad0 bus, the c/be3 ?c/be0 bus, and primary parity (p_par) by driving them to valid logic levels. if the pci2060 bridge is parking the primary bus and wants to initiate a transaction on the bus, then it can start the transaction on the next pci clock by asserting the primary cycle frame (p_frame ) while p_gnt is still asserted. if p_gnt is deasserted, then the bridge must re-arbitrate for the bus to initiate a transaction. 3.7.2 internal secondary bus arbitration the s_cfn terminal controls the state of the secondary internal arbiter. when s_cfn is low, the secondary internal arbiter is enabled. when s_cfn is high, the secondary external arbiter function is enabled. the pci2060 bridge provides nine secondary bus request terminals and nine secondary bus grant terminals. including the bridge, there are total of ten potential secondary bus masters. when an external arbiter is implemented, s_req8 through s_req1 and s_gnt8 through s_gnt1 are placed in a high-impedance mode. 3.7.3 external secondary bus arbitration an external secondary bus arbiter can be used instead of the pci2060 internal bus arbiter. when using an external arbiter, the pci2050b internal arbiter must be disabled by pulling s_cfn high. when an external secondary bus arbiter is used, the pci2050b bridge internally reconfigures the s_req0 and s_gnt0 signals so that s_req0 becomes the secondary bus grant for the bridge and s_gnt0 becomes the secondary bus request for the bridge. this is done because s_req0 is an input and can thus provide the grant input to the bridge, and s_gnt0 is an output and can thus provide the request output from the bridge. when an external arbiter is used, all unused secondary bus grant outputs (s_gnt8 through s_gnt1 ) are placed in a high-impedance mode. any unused secondary bus request inputs (s_req8 through s_req1 ) must be pulled high to prevent the inputs from oscillating. 3.8 parity error handling when forwarding transactions, the pci2060 bridge attempts to pass the parity condition from one interface to the other unchanged, whenever possible, to allow the master and target devices to handle the error condition. principles of operation 25 april 2005 scps096a 3.8.1 address parity error the pci2060 bridge checks address parity for all transactions on both buses, for all addresses and all bus commands. when the pci2060 bridge detects an address parity error on the primary bus, the following events occur: ? if bit 6 (perr_enb) in the primary command register (offset 04h) is set to 1b, then the pci2060 bridge does not claim the transaction with p_devsel ; this allows the transaction to terminate in a master abort. ? if bit 6 (perr_enb) is not set, then the pci2060 bridge proceeds normally and accepts the transaction if it is directed to or across the pci2060 bridge. ? the pci2060 bridge sets bit 15 (par_err) in the primary status register (offset 06h). ? the pci2060 bridge asserts p_serr and sets bit 14 (sys_p_serr) in the primary status register (of fset 06h), if both of the following conditions are met: ? bit 8 (serr_enb) is set in the primary command register (offset 04h). ? bit 6 (perr_enb) is set in the primary command register (offset 04h). when the pci2060 bridge detects an address parity error on the secondary bus, the following events occur: ? if bit 0 (perr_en) in the bridge control register (offset 3eh) is set to 1b, then the pci2060 bridge does not claim the transaction with s_devsel ; this allows the transaction to terminate in a master abort. ? if the perr_en bit is not set, then the pci2060 bridge proceeds normally and accepts the transaction if it is directed to or across the pci2060 bridge. ? the pci2060 bridge sets bit 15 (par_err) in the secondary status register (offset 1eh). ? the pci2060 bridge asserts p_serr and sets bit 14 (sys_p_serr) in the primary status register (of fset 06h), if the following conditions are met: ? bit 8 (serr_enb) is set in the primary command register (offset 04h). ? bit 0 (perr_en) is set in the bridge-control register (offset 3eh). 3.8.2 data parity error if bit 6 (perr_enb) in the primary command register (offset 04h) is set, then the pci2060 bridge signals perr when it receives bad data. when the bridge detects bad parity, bit 15 (p ar_err) in the primary status register (offset 06h) is set. if the pci2060 bridge is configured to respond to parity errors via the perr_enb bit in the primary command register (offset 04h), then bit 8 (datapar) in the primary status register (offset 06h) is set when the bridge detects bad parity. the datapar bit is also set when the bridge, as a bus master, asserts perr or detects perr. 3.9 system error handling the pci2060 bridge can be configured to signal a system error (serr) on the primary bus for a variety of conditions. the p_serr event disable register (offset 64h) and the p_serr status register (offset 6ah) provide control and status bits for each condition for which the bridge can signal p_serr . by default, the pci2060 bridge does not signal p_serr . if bit 8 (serr_enb) in the primary command register (offset 04h) is set, then the bridge signals serr if any of the error conditions in the p_serr event disable register occur and that condition is enabled. by default, all error conditions are enabled in the p_serr event disable register. when the bridge signals serr on the primary bus, bit 14 (sys_p_serr) in the primary status register (offset 06h) is also set. principles of operation 26 april 2005 scps096a when the pci2060 bridge detects the assertion of the serr on the secondary bus, bit 14 (sys_s_serr) in the secondary status register (offset 1eh) is also set. if bit 1 (serr_en) in the bridge control register (of fset 3eh) and bit 8 (serr_enb) in the primary command register (offset 04h) are set, then the pci2060 bridge signals serr on the primary bus. the pci2060 bridge conditionally asserts p_serr for any of the following reasons: ? target abort detected during posted write transaction ? master abort detected during posted write transaction ? posted write data discarded after 2 24 attempts to deliver ? parity error reported on target bus during posted write transaction ? delayed write data discarded after 2 24 attempts to deliver ? delayed read data cannot be transferred from target after 2 24 attempts ? master timeout on delayed transaction 3.10 clocks 3.10.1 secondary bus clock behavior the pci2060 bridge has ten secondary clock outputs: s_clkout [9:0]. nine secondary clock outputs can be used as clock inputs for up to nine external secondary bus devices. one secondary clock output has to be used for the pci2060 secondary clock input (s_clk) for internal state-machine synchronization purposes. figure 3?2 shows a block diagram of the secondary clock function. the pci2060 bridge is designed to use either the primary pci clock input (p_clk) or the new sec_async_clk clock input to generate the secondary bus clocks. the maximum clock frequency that the p_clk and the sec_async_clk inputs support is 66 mhz. when using the primary pci clock (p_clk) as the clock input to generate the secondary bus clocks, the primary and secondary clocks must be synchronized to each other. the pci2060 bridge is capable of supporting the following frequency combinations when using the primary pci clock (p_clk) as the clock input: ? 66-mhz primary bus, 66-mhz secondary bus ? 66-mhz primary bus, 33-mhz secondary bus ? 33-mhz primary bus, 33-mhz secondary bus when using the primary pci clock (p_clk) as the clock input to generate the secondary bus clocks, the pci2060 bridge does not support 33-mhz primary bus/66-mhz secondary bus operation, where the secondary bus is operating at twice the frequency of the primary bus. principles of operation 27 april 2005 scps096a pci2060 pci device s_clkout8 s_clkout9 pci device s_clkout7 s_clk p_clk s_async_clk s_async_sel s_sync_rate figure 3?2. secondary clock block diagram when using the sec_async_clk as the clock input to generate the secondary bus clocks, the secondary bus clocks do not need to be synchronized to the primary clock input. the pci2060 bridge is capable of supporting operations in which the secondary bus clock frequencies can be greater than the primary clock frequency. the sec_async_sel selects the clock that generates the secondary bus clock. if sec_async_sel is low, then the primary pci clock (p_clk) input generates the secondary bus clock. if sec_async_sel is high, then the sec_async_clk generates the secondary bus clock. the sec_async_rate input determines if the secondary reference clock is directly output on the secondary clock terminals or if the secondary reference clock is divided by two before being output on the secondary clock terminals. if sec_async_rate is 0, then the clock outputs are divided by two. if sec_async_rate is 1, then the clock outputs are the same frequency as the secondary reference clock. table 3?9 illustrates the relationship between the config66, p_m66ena, and s_m66ena signals. table 3?9. config66, p_m66ena, and s_m66ena configuration config66 p_m66ena s_m66ena primary pci interface time specification secondary pci interface time specification 1 1 1 66 mhz 66 mhz 1 1 0 66 mhz 33 mhz 1 0 1 33 mhz 66 mhz 1 0 0 33 mhz 33 mhz 0 x x 33 mhz 33 mhz principles of operation 28 april 2005 scps096a table 3?10 illustrates the relationship between the sec_async_se l and the sec_async_rate signals. table 3?10. sec_async_sel and sec_async_rate configuration sec_async_sel sec_async_rate secondary clock source clock frequency ratio 1 1 sec_async_clk 1 1 0 sec_async_clk 1/2 0 1 p_clk 1 0 0 p_clk 1/2 table 3?11 illustrates the configuration of the config66, p_m66ena, s_m66ena, sec_async_sel, and sec_async_rate signals using some common frequencies as examples. table 3?11. config66, p_m66ena, s_m66ena, sec_async_sel, and sec_async_rate configuration p_clk sec_async_clk config66 p_m66ena s_m66ena sec_async_sel sec_cl_rate s_clk 66 mhz x 1 1 1 0 1 66 mhz 66 mhz 50 mhz 1 1 1 1 1 50 mhz 66 mhz x 1 1 0 0 0 33 mhz 66 mhz 50 mhz 1 1 0 1 0 25 mhz 33 mhz 66 mhz 1 0 1 1 1 66 mhz 33 mhz 50 mhz 1 0 1 1 1 50 mhz 33 mhz x 0 x x 0 1 33 mhz 33 mhz 50 mhz 0 x x 1 0 25 mhz the rules for using secondary clocks are: ? each secondary clock output is limited to one load. ? one of the secondary clock outputs must be used for the pci2060 s_clk input. the clock line used for s_clk must match the length of the longest secondary output trace. ? use an equivalent amount of etch on the board for all secondary clocks, to minimize skew between them, and use a maximum etch delay of 2 ns. ? route clock signals on the top layer and avoid vias for these signals. ? terminate or disable unused secondary clock outputs using the secondary clock control register to reduce power dissipation and noise in the system. 3.11 interrupt routing all parallel pci interrupts on the secondary bus interface must be routed as sideband signals to the pci interrupts on the primary interface. ti suggests that the board designer implement the interrupt routing scheme outlined in section 2.2.6 of the pci local bus specification revision 2.2. table 3?12 summarizes section 2.2.6. principles of operation 29 april 2005 scps096a table 3?12. interrupt routing scheme device number on secondary bus interrupt terminal on device interrupt terminal on connector 0, 4, 8, 12, 16, 20, 24, 28 inta intb intc intd inta intb intc intd 1, 5, 9, 13, 17, 21, 25, 29 inta intb intc intd intb intc intd inta 2, 6, 10, 14, 18, 22, 26, 30 inta intb intc intd intc intd inta intb 3, 7, 11, 15, 19, 23, 27, 31 inta intb intc intd intd inta intb intc 3.12 mode selection the pci2060 bridge supports three modes of operation: intel-compatible mode, pci power-management 1.1 mode, and compactpci hot-swap mode. table 3?13 shows how each mode is selected using the ms0 and ms1 terminals. ms0 and ms1 can only be configured while the pci2060 bridge is in reset. table 3?13. mode selections ms0 ms1 mode 0 0 compact pci hot-swap mode gpio3 functions as hsswitch pci bus power management interface specification, revision 1.1 0 1 pci power-management 1.1 mode gpio3 functions as gpio3 pci bus power management interface specification, revision 1.1 1 x intel-compatible mode pci bus power management interface specification, revision 1.0 3.12.1 compactpci hot-swap support the pci2060 bridge is designed to support the requirements for hot swap friendly silicon in the compactpci 2.1 r1 specification. to be hot swap friendly the pci2060 bridge supports the following: ? compliance with the pci local bus specification ? tolerance of v cc from early power ? asynchronous reset ? tolerance of precharge voltage ? i/o buffers meet the compactpci modified v/i requirements ? limited i/o terminal current at precharge voltage ? hot-swap control and status programming via an extended pci capabilities linked list ? hot-swap terminals: hsenum , hsswitch , and hsled the pci2060 bridge provides this functionality when configured into compactpci mode. principles of operation 30 april 2005 scps096a 3.12.2 pci power management the pci bus power management interface specification establishes the infrastructure required to let the operating system control the power of pci functions. this is accomplished by defining a standard pci interface and operations to manage the power of pci functions on the bus. the pci bus and the pci functions can be assigned one of four software-visible power-management states, which result in varying levels of power savings. the four power-management states of the pci functions are: d0?fully on state, d1 and d2?intermediate states, and d3?off state. similarly, bus power states of the pci bus are b0 through b3. the bus power states b0 through b3 are derived from the device power state of the originating pci2060 device. for the operating system to manage the device power states on the pci bus, the pci function supports four power-management operations: ? capabilities reporting ? power status reporting ? setting the power state ? system wake-up the operating system identifies the capabilities of the pci function by traversing the new capabilities list. the presence of the new capabilities list is indicated by bit 4 (caplist) in the primary status register (offset 06h). 3.12.2.1 behavior in low-power states the pci2060 bridge supports d0, d1, d2, and d3 hot power states when in the ti mode. the pci2060 bridge only supports d0 and d3 power states when in the intel mode. the pci2060 bridge is fully functional only in d0 state. in the lower power state, the pci2060 bridge does not accept any memory or i/o transactions. these transactions are aborted by the master. the bridge accepts type 0 configuration transactions in all power states except d3 cold . the bridge also accepts type 1 configuration transactions but does not pass these cycles to the secondary bus in any of the lower power states. type 1 configuration writes are discarded and reads return all 1s. all error reporting is done in the low power states. when in d2 and d3 hot states, the bridge turns off all secondary clocks for further power savings. when going from d3 hot to d0, an internal reset is generated. this reset initializes all pci configuration registers to their default values except the ti specific registers (40h ? ffh) and power-management registers. 3.13 jtag support the pci2060 bridge implements a jtag test port based on the ieee standard 1149.1 standard test access port and boundary-scan architecture . the jtag port consists of the following: ? a 5-wire test access port ? a test access port controller ? an instruction register ? a bypass register ? a boundary-scan register 3.13.1 test port instructions the pci2060 bridge supports the following jtag instructions: ? extest, bypass, and sample ? highz and clamp ? private (various private instructions used by ti for test purposes) 3.13.2 instruction register table 3?14 lists and describes the different test port instructions, and gives the op code of each one. the instruction register selects and controls the operation of the boundary-scan and bypass registers. principles of operation 31 april 2005 scps096a table 3?14. jtag instructions and op codes instruction op code description extest 00000 drives terminals from the boundary scan register sample 00001 samples i/o terminals clamp 00100 drives terminals from the boundary scan register and selects the bypass register for shifts. highz 00101 puts all outputs and i/o terminals except for the tdo terminal into a high-impedance state. bypass 11111 selects the bypass register for shifts 3.13.3 1-bit bypass register the 1-bit bypass register is a 1-bit shift register that provides a means for effectively bypassing the jtag test logic through a single-bit serial connection through the chip from tdi to tdo. at board-level testing, this helps reduce overall length of the scan ring. 3.13.4 boundary scan register the boundary-scan register is a single-shift register-based path formed by boundary-scan cells placed at the chip?s signal terminals. the register is accessed through the jtag port?s tdi and tdo terminals. 3.13.4.1 boundary-scan register cells each boundary-scan cell operates in conjunction with the current instruction and the current state in the test access port controller state machine. the function of the boundary-scan register cells is determined by the associated terminals, as follows: ? input-only terminals?the boundary-scan cell is basically a 1-bit shift register. the cell supports sample and shift functions. ? output-only terminals?the boundary-scan cell comprises a 1-bit shift register and an output multiplexer. the cell supports the sample, shift, and drive output functions. ? bidirectional terminals?the boundary-scan cell is identical to the output-only terminal cell, but it captures test data from the incoming data line. the cell supports sample, shift, drive output, and hold output functions. it is used at all i/o terminals. the information in table 3?15 is for implementation of boundary scan interface signals to permit in-circuit testing. principles of operation 32 april 2005 scps096a table 3?15. boundary scan terminal order boundary scan register no. ghk terminal number terminal name group disable register boundary-scan cell type 0 j15 s_ad0 19 bidirectional 1 h19 s_ad1 19 bidirectional 2 h17 s_ad2 19 bidirectional 3 h14 s_ad3 19 bidirectional 4 g19 s_ad4 19 bidirectional 5 g18 s_ad5 19 bidirectional 6 g14 s_ad6 19 bidirectional 7 f19 s_ad7 19 bidirectional 8 g15 s_c/be0 19 bidirectional 9 f17 s_ad8 19 bidirectional 10 f14 s_ad9 19 bidirectional 11 e18 s_m66ena 19 bidirectional 12 f15 s_ad10 19 bidirectional 13 e17 ms0 ? input 14 d18 sec_async_rate ? bidirectional 15 e14 s_ad11 19 bidirectional 16 b15 s_ad12 19 bidirectional 17 a15 s_ad13 19 bidirectional 18 b14 s_ad14 19 bidirectional 19 e13 s_ad15 19 bidirectional 20 ? ? ? ? 21 f12 s_c/be1 19 bidirectional 22 c13 s_par 19 bidirectional 23 b13 s_serr ? input 24 e12 s_perr 26 bidirectional 25 c12 s_lock 26 bidirectional 26 b12 s_stop 26 bidirectional 27 ? ? ? ? 28 a11 s_devsel 26 bidirectional 29 b11 s_trdy 26 bidirectional 30 c11 s_irdy 26 bidirectional 31 f11 s_frame 26 bidirectional 32 a10 s_c/be2 48 bidirectional 33 e10 s_ad16 48 bidirectional 34 f10 s_ad17 48 bidirectional 35 c9 s_ad18 48 bidirectional 36 f9 s_ad19 48 bidirectional 37 a8 s_ad20 48 bidirectional 38 b8 s_ad21 48 bidirectional 39 f8 s_ad22 48 bidirectional 40 e8 s_ad23 48 bidirectional 41 b7 s_c/be3 48 bidirectional 42 c7 s_ad24 48 bidirectional principles of operation 33 april 2005 scps096a table 3?15. boundary scan terminal order (continued) boundary scan register no. ghk terminal number terminal name group disable register boundary-scan cell type 43 a6 s_ad25 48 bidirectional 44 b6 s_ad26 48 bidirectional 45 c6 s_ad27 48 bidirectional 46 a5 s_ad28 48 bidirectional 47 b5 s_ad29 48 bidirectional 48 e6 s_ad30 48 bidirectional 49 ? ? ? ? 50 a4 s_ad31 48 bidirectional 51 b4 s_req0 ? input 52 e3 s_req1 ? input 53 c4 sec_async_sel ? input 54 c1 sec_async_clk ? input 55 f5 s_req2 ? input 56 g6 s_req3 ? input 57 e2 s_req4 ? input 58 e1 s_req5 ? input 59 f3 s_req6 ? input 60 f2 s_req7 ? input 61 g5 s_req8 ? input 62 f1 s_gnt0 61 output 63 h6 s_gnt1 61 output 64 ? ? ? control 65 g2 s_gnt2 61 output 66 g1 s_gnt3 61 output 67 h5 s_gnt4 61 output 68 h3 s_gnt5 61 output 69 h2 s_gnt6 61 output 70 h1 s_gnt7 61 output 71 j1 s_gnt8 61 output 72 j3 s_clk ? input 73 j5 s_rst 78 output 74 j6 s_cfn ? input 75 k1 gpio3 78 bidirectional 76 k2 gpio2 78 bidirectional 77 k5 gpio1 78 bidirectional 78 k6 gpio0 78 bidirectional 79 l1 s_clkout0 ? output 80 l2 s_clkout1 ? output 81 ? ? ? ? 82 l5 s_clkout2 ? output 83 m1 s_clkout3 ? output 84 m3 s_clkout4 ? output 85 m6 s_clkout5 ? output principles of operation 34 april 2005 scps096a table 3?15. boundary scan terminal order (continued) boundary scan register no. ghk terminal number terminal name group disable register boundary-scan cell type 86 n1 s_clkout6 ? output 87 n2 s_clkout7 ? output 88 n6 s_clkout8 ? output 89 p1 s_clkout9 ? output 90 p2 p_rst ? input 91 n5 bpcce ? input 92 p3 p_clk ? input 93 r1 p_gnt ? input 94 p6 p_req 92 output 95 ? ? ? ? 96 r3 p_ad31 111 bidirectional 97 t1 p_ad30 111 bidirectional 98 r6 p_ad29 111 bidirectional 99 w5 p_ad28 111 bidirectional 100 u6 p_ad27 111 bidirectional 101 r7 p_ad26 111 bidirectional 102 w6 p_ad25 111 bidirectional 103 u7 p_ad24 111 bidirectional 104 v7 p_c/be3 111 bidirectional 105 w7 p_idsel ? input 106 u8 p_ad23 111 bidirectional 107 v8 p_ad22 111 bidirectional 108 w9 p_ad21 111 bidirectional 109 v9 p_ad20 111 bidirectional 110 r9 p_ad19 111 bidirectional 111 p9 p_ad18 111 bidirectional 112 v10 p_ad17 111 bidirectional 113 u10 p_ad16 111 bidirectional 114 ? ? ? ? 115 p10 p_c/be2 111 bidirectional 116 w11 p_frame 118 bidirectional 117 u11 p_irdy 118 bidirectional 118 p11 p_trdy 118 bidirectional 119 r11 p_devsel 118 bidirectional 120 w12 p_stop 118 bidirectional 121 ? ? ? ? 122 p12 p_lock 118 input 123 r12 p_perr 118 bidirectional 124 w13 p_serr 142 output 125 v13 p_par 142 bidirectional 126 p13 p_c/be1 142 bidirectional 127 w14 p_ad15 142 bidirectional principles of operation 35 april 2005 scps096a table 3?15. boundary scan terminal order (continued) boundary scan register no. ghk terminal number terminal name group disable register boundary-scan cell type 128 r13 p_ad14 142 bidirectional 129 u14 p_ad13 142 bidirectional 130 p14 p_ad12 142 bidirectional 131 v15 p_ad11 142 bidirectional 132 u15 p_ad10 142 bidirectional 133 t19 ms1 ? input 134 r17 p_ad9 142 bidirectional 135 n14 p_ad8 142 bidirectional 136 r18 p_c/be0 142 bidirectional 137 p17 p_ad7 142 bidirectional 138 p18 p_ad6 142 bidirectional 139 p19 p_ad5 142 bidirectional 140 m14 p_ad4 142 bidirectional 141 n18 p_ad3 142 bidirectional 142 n19 p_ad2 142 bidirectional 143 m17 p_ad1 142 bidirectional 144 m18 p_ad0 142 bidirectional 145 ? ? ? ? 146 l17 mask_in ? input 147 ? ? ? ? 148 l15 hs_enum 144 output 149 l14 hs_led 144 output 3.14 gpio interface the pci2060 bridge implements a four-terminal general-purpose i/o (gpio) interface. besides functioning as a gpio interface, the gpio terminals can read the secondary clock mask and stop the bridge from accepting i/o and memory transactions. 3.14.1 secondary clock mask the pci2060 bridge uses gpio0, gpio2 and msk_in to shift the secondary clock mask from an external shift register. a secondary mask timing diagram is shown in figure 3?3. table 3?16 lists the format for clock mask data. bit 15 m sk_in bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 gpio2 gpio0 p_rst s_rst figure 3?3. clock mask read timing after reset principles of operation 36 april 2005 scps096a table 3?16. clock mask data format bit clock [0:1] s_clkout0 [2:3] s_clkout1 [4:5] s_clkout2 [6:7] s_clkout3 8 s_clkout4 9 s_clkout5 10 s_clkout6 11 s_clkout7 12 s_clkout8 13 s_clkout9 [14:15] reserved 3.14.2 transaction forwarding control the pci2060 bridge stops forwarding i/o and memory transactions if bit 5 in the chip control register (offset 40h) is set to 1b and gpio3 is driven high. the bridge completes all queued posted writes and delayed requests, but delayed completions are not returned until gpio3 is driven low. this feature is not available in compactpci hot-swap mode because gpio3 is used as the hs_switch in this mode. configuration header space 37 april 2005 scps096a 4 configuration header space this cha pter describes the configuration header space of the pci2060 bridge. the configuration head space is in compliance with the pci local bus specification ( revision 1.1). table 4?1 shows the pci configuration head space, which includes predefined portion of the bridge configuration space. address spaces starting at offset 40h are device-specific registers. the pci configuration offset is shown in the right column under the offset heading. table 4?1. pci configuration header space register name offset device id vendor id 00h primary status primary command 04h class code revision id 08h bist header type latency timer cache line size 0ch reserved 10h reserved 14h secondary latency timer subordinate bus number secondary bus number primary bus number 18h secondary status i/o limit i/o base 1ch memory limit memory base 20h prefetchable memory limit prefetchable memory base 24h prefetchable base upper 32 bits 28h prefetchable limit upper 32 bits 2ch i/o limit upper 16 bits i/o base upper 16 bits 30h reserved capabilities pointer 34h reserved 38h bridge control interrupt pin interrupt line 3ch arbiter control extended diagnostic chip control 40h reserved 44h?60h gpio input data gpio output enable gpio output data p_ser event disable 64h reserved p_ser status secondary clock control 68h reserved 6ch?d8hh power-management capabilities pm next item pointer pm capability id dch data (reserved) pmcsr bridge support power-management control and status e0h reserved hot-swap control and status hs next item pointer hs capability id e4h reserved e8h?ech reserved ti diagnostic f0h reserved f4h?fch 4.1 vendor id register (00h) the value in this 16-bit read-only register is allocated by the pci special interest group (sig) and identifies the manufacturer of the device. this register contains the value 104ch, which identifies texas instruments as the manufacturer of this device. bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset state 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 configuration header space 38 april 2005 scps096a 4.2 device id register (02h) the value in this 16-bit read-only register is assigned by the device manufacturer and identifies the type of device. the device id for the pci2060 asynchronous bridge is ac2ch. bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset state 1 0 1 0 1 1 0 0 0 0 1 0 1 1 0 0 4.3 primary command register (04h) the primary command register provides basic control over the pci2060?s ability to respond to and/or perform pci accesses. bits [15:11] are reserved for future use and must return 00000b. see table 4?2 for a complete description of the register contents. bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 4?2. primary command register bit field name description 15:11 rsvd reserved. returns 00000b when read. 10 int_disable intx disable. this bit enables or disables device-specific interrupts. the pci2060 bridge does not generate any interrupts internally. this bit is read-only and returns 0b when it is read. 9 fbb_enb fast back-to-back enable 0 = the pci2060 bridge does not generate back-to-back transactions on the primary bus. 1 = the pci2060 bridge generates back-to-back transactions on the primary bus. 8 serr_enb p_serr enable 0 = disables the signaling of p_serr by pci2060 bridge 1 = enables the signaling of p_serr by pci2060 bridge 7 step_enb address/data stepping control. the pci2060 bridge does not support address/data stepping. this bit is read-only and returns 0b when it is read. 6 perr_enb parity error response enable 0 = the pci2060 bridge must ignore any address or data parity errors that it detects on the primary bus and continue normal operation. 1 = the pci2060 bridge must take the appropriate action when any address or data parity errors are detected on the primary bus. 5 vga_enb vga palette snoop enable. when set, the pci2060 bridge passes i/o writes on the primary pci bus with addresses 3c6h, 3c8h, and 3c9h inclusive of isa aliases (that is, only p_ad[9:0] are included in the decode). 4 mwi_enb memory write-and-invalidate enable. the pci2060 bridge generates memory write-and-invalidate transactions only when operating on behalf of another master whose memory write-and-invalidate transaction is crossing the pci2060 bridge. this bit is read-only and returns 0b when it is read. 3 special special cycle enable. the pci2060 bridge does not respond to special cycle transactions. this bit is read-only and returns 0b when it is read. 2 master_enb bus master enable 0 = the pci2060 bridge does not initiate i/o or memory transactions on the primary bus and does not respond to i/o or memory transactions on the secondary bus. 1 = the pci2060 bridge is enabled to be an initiator on the primary bus and responds to i/o or memory transactions on the secondary bus. 1 memory_enb memory space enable 0 = the pci2060 bridge does not respond to the memory transactions on the primary bus. 1 = the pci2060 bridge responds to the memory transactions on the primary bus. 0 io_enb i/o space enable 0 = the pci2060 bridge does not respond to the i/o transactions on the primary bus. 1 = the pci2060 bridge responds to the i/o transactions on the primary bus. configuration header space 39 april 2005 scps096a 4.4 primary status register (06h) the status register provides status of the primary bus of the pci2060 bridge. bits in this register are cleared by writing a 1b to the respective bit; writing a 0b to a bit location has no effect. bits 6 and [2:0] are reserved for future use and must return 0s. see table 4?3 for a complete description of the register contents. bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 0 1 0 0 0 x ? 1 0 0 0 0 ? the default state of this bit is controlled by the config66 terminal. table 4?3. primary status register bit field name description 15 par_err detected parity error. this bit is set when the pci2060 bridge detects an address or data parity error on the primary bus. this bit is set regardless of the state of bit 6 (perr_enb) in the primary command register (offset 04h). 0 = no parity error detected 1 = parity error detected 14 sys_p_serr signaled system error. this bit is set when the pci2060 bridge signals p_serr on the primary bus. 0 = p_serr is not signaled 1 = p_serr is signaled 13 mabort received master abort. this bit is set when the pci2060 bridge is acting as a master on the primary bus and receives a master abort. 0 = master abort not received on the primary bus 1 = master abort received on the primary bus 12 tabort_rec received target abort. this bit is set when the pci2060 bridge is acting as a master on the primary bus and receives a target abort from the primary target. 0 = target abort not received on the primary bus 1 = target abort received on the primary bus 11 tabort_sig signaled target abort. this bit is set when the pci2060 bridge is acting as a target on the primary bus and returns a target abort to the primary master. 0 = target abort not signaled on the primary bus 1 = target abort signaled on the primary bus 10:9 devsel timing devsel timing. these two bits indicate the slowest response to a nonconfiguration command on the primary bus. these two bits are read-only and read 01b to indicate the pci2060 bridge responds no slower than with medium timing. 8 datapar master data parity error. this bit is set when the following conditions are met: ? the pci2060 device is the bus master on the primary bus during the data parity error. ? p_perr was asserted by any pci device on the primary bus including the pci2060 device. ? bit 6 (perr_enb) is set in the primary command register (offset 04h). 0 = no data parity error detected on the primary bus 1 = data parity error detected on the primary bus 7 fbb_cap fast back-to-back capable. the pci2060 bridge is able to accept fast back-to-back transactions; thus, this bit is hardwired to 1b. 6 rsvd reserved. returns 0b when read. 5 66mhz 66-mhz capable. this bit indicates whether the primary interface is 66 mhz capable. it reads 0b when config66 is tied low to indicate that pci2060 bridge is not 66 mhz capable. it reads 1b when config66 is tied high to indicate that the primary bus is 66 mhz capable. 4 caplist capabilities list. this read-only bit indicates whether or not a device implements the pointer for a new capabilities linked list at offset 34h. this bit returns 1b when read, indicating that the pci2060 bridge supports additional pci capabilities. 3 int_status interrupt status. this read-only bit reflects the state of the interrupt in the device. since the pci2060 bridge does not generate an interrupt internally, this bit returns 0b when it is read. 2:0 rsvd reserved. returns 000b when read. configuration header space 40 april 2005 scps096a 4.5 revision id register (08h) the value in this 8-bit read-only register specifies a device-specific revision identifier. the revision id register returns 00h when it is read. bit number 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 0 0 0 4.6 programming interface register (09h) the value in this 8-bit read-only register specifies a register-level programming interface so that device-independent software can interface with the device. the programming interface register returns 00h when it is read. bit number 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 0 0 0 4.7 subclass code register (0ah) the value in this 8-bit read-only register returns 04h when it is read, classifies the pci2060 as a pci-to-pci bridge. bit number 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 1 0 0 4.8 base class code register (0bh) the value in this 8-bit read-only register returns 06h when it is read, classifies the pci2060 as a bridge device. bit number 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 1 1 0 4.9 cache line size register (0ch) this read/write register is programmed by host software to indicate the system-cache line size needed by the bridge for memory read line, memory read multiple, and memory write-and-invalidate transactions. the pci2060 bridge supports cache line sizes up to and including 16 doublewords for memory write-and-invalidate. if the cache line size is larger than 16 doublewords, then the command is converted to a memory write command. bit number 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 0 0 0 4.10 primary latency timer register (0dh) this read/write register defines the minimum period of time (in pci clock cycles since p_frame is asserted) that the pci2060 bridge may continue a burst transaction even if it is preempted (p_gnt is deasserted). when this register is set to 00h, the pci2060 bridge relinquishes the bus after the first data transfer when p_gnt is deasserted. bit number 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 0 0 0 configuration header space 41 april 2005 scps096a 4.11 header type register (0eh) the header type register is read-only and returns 01h when read, indicating that the pci2060 configuration space adheres to the pci-to-pci bridge configuration. only the layout for bytes 10h?3fh of the configuration space is considered. bit number 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 0 0 1 4.12 bist register (0fh) the pci2060 bridge does not support built-in self-test (bist). the bist register is read-only and returns the value 00h when read. bit number 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 0 0 0 4.13 primary bus number register (18h) the primary bus number register indicates the primary bus number to which the pci2060 bridge is connected. the bridge uses this register, in conjunction with the secondary bus number and subordinate bus number registers, to decode type 1 configuration transactions on the secondary interface that must be either converted to special cycle transactions on the primary interface or passed upstream unaltered. bit number 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 0 0 0 4.14 secondary bus number register (19h) this read/write register specifies the bus number of the pci bus segment that the secondary interface is connected to. the pci2060 bridge uses this register to determine when to respond to and forward type 1 configuration transactions on the primary interface, and to determine when to convert them to type 0 or special cycle transactions on the secondary interface. bit number 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 0 0 0 4.15 subordinate bus number register (1ah) this read/write register specifies the bus number of the highest number pci bus segment that is subordinate to the pci2060 bridge. in conjunction with the secondary bus number register, the pci2060 bridge uses this register to determine when to respond to type 1 configuration transactions on the primary interface and pass them to the secondary interface as a type 1 configuration transaction. bit number 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 0 0 0 4.16 secondary latency timer register (1bh) this read/write register defines the minimum period of time (in pci clock cycles since s_frame is asserted) that the pci2060 bridge may continue a burst transaction even if it is preempted (the pci2060 secondary bus grant is deasserted). when this register is set to 00h, the pci2060 bridge relinquishes the bus after the first data transfer when its secondary bus grant is deasserted. bit number 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 0 0 0 configuration header space 42 april 2005 scps096a 4.17 i/o base address register (1ch) the i/o base address register defines the lower limit of the i/o address range that is used by the pci2060 bridge to determine when to forward i/o transactions from one interface to the other. bits [3:0] are read-only and default to 1h to indicate that the pci2060 bridge supports 32-bit i/o addressing. the upper 4 bits are writable and correspond to address bits [15:12]. the lower 12 address bits of the i/o base address are assumed to be 000h. thus, the bottom of the defined i/o address range is aligned on a 4k-byte boundary. the upper 16 address bits of the 32-bit i/o base address correspond to the contents of the i/o base address upper 16 bits register (offset 30h). see table 4?4 for a complete description of the register contents. bit number 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 0 0 1 table 4?4. i/o base register bit field name description 7:4 iobase [15:12] i/o base. defines the bottom address of the i/o address range that determines when to forward i/o transactions from one interface to the other. the upper 4 bits are writable and correspond to address bits [15:12]. the lower 12 bits are assumed to be 000h. the 16 bits corresponding to address bits [31:16] of the i/o address are defined in the i/o base address upper 16 bits register. 3:0 iotype i/o type. this field is read-only. it reads 1h indicating that the pci2060 bridge supports 32-bit i/o addressing. 4.18 i/o limit address register (1dh) this read/write register defines the upper limit of the i/o addresses range that is used by the pci2060 bridge to determine when to forward i/o transactions from one interface to the other. bits [3:0] are read-only and default to 1h to indicate that the pci2060 bridge supports 32-bit i/o addressing. the upper 4 bits are writable and correspond to address bits [15:12]. the lower 12 address bits of the i/o limit address are considered fffh. thus, the top of the defined i/o address range is aligned on a 4k-byte boundary. the upper 16 address bits of the 32-bit i/o limit address correspond to the contents of the i/o limit address upper 16 bits register (offset 32h). see table 4?5 for a complete description of the register contents. bit number 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 0 0 1 table 4?5. i/o limit address register bit field name description 7:4 iolimit [15:12] i/o limit. defines the top address of the i/o address range that determines when to forward i/o transactions from one interface to the other. the upper 4 bits are writeable and correspond to address bits [15:12]. the lower 12 bits are assumed to be fffh. the 16 bits corresponding to address bits [31:16] of the i/o address are defined in the i/o limit address upper 16 bits register. 3:0 iotype i/o type. this field is read-only. it reads 1h indicating that the pci2060 bridge supports 32-bit i/o addressing. configuration header space 43 april 2005 scps096a 4.19 secondary status register (1eh) the status register provides status of the primary bus of the pci2060 bridge. writing a 1b to the respective bit clears bits in this register; writing a 0b to a bit location has no effect. see table 4?6 for a complete description of the register contents. bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 0 1 0 0 0 x ? 0 0 0 0 0 ? the default state of this bit is dependent on the state of the config66 terminal. table 4?6. secondary status register bit field name description 15 par_err detected parity error. this bit is set when an address or data parity error is detected on the secondary bus. this bit is set regardless of the state of bit 0 (perr_en) in the bridge control register (offset 3eh). 0 = parity error is not detected 1 = parity error is detected 14 sys_s_serr received system error. this bit reports the detection of the assertion of s_serr on the secondary bus. 0 = s_serr assertion is not detected on the secondary bus 1 = s_serr assertion is detected on the secondary bus 13 mabort received master abort. this bit reports the detection of a master-abort termination by the pci2060 bridge when it is the master of a transaction on its secondary bus. 0 = master abort is not detected by the pci2060 bridge on its secondary bus 1 = unsupported request or master abort is detected by the pci2060 bridge on its secondary bus 12 tabort_rec received target abort. this bit reports the detection of a target-abortion termination by the pci2060 bridge when it is the master of a transaction on its secondary bus. 0 = target abort is not detected by the pci2060 bridge on its secondary bus 1 = target abort is detected by the pci2060 bridge on its secondary bus 11 tabort_sig signaled target abort. this bit reports the signaling of a target-abort termination by the pci2060 bridge when it responds as the target of a transaction on its secondary bus. 0 = target abort is not signaled by the pci2060 bridge on its secondary bus 1 = target abort is signaled by the pci2060 bridge on its secondary bus 10:9 pci_speed devsel timing. these bits indicate the slowest response time to a command on the secondary bus. these bits return 01b, indicating that the pci2060 bridge responds no slower than with medium timing. 8 datapar master data parity error. this bit is set to 1b when the following conditions have been met: ? the pci2060 bridge is the bus master. ? s_perr was asserted by any pci device on the secondary bus, including the pci2060 bridge. ? bit 0 (perr_en) is set in the bridge control register (offset 3eh). 0 = data parity error is not detected on the secondary interface 1 = data parity error is detected on the secondary interface 7 fbb_cap fast back-to-back capable. this bit reads 1b to indicate pci2060 bridge is able to respond to fast back-to-back transaction on the secondary bus. 6 rsvd reserved. returns 0b when read. 5 66mhz 66-mhz capable. this bit indicates whether the secondary interface is 66-mhz capable. it reads 0b when config66 is tied low to indicate that pci2060 bridge is not 66-mhz capable. it reads 1b when config66 is tied high to indicate that the secondary bus is 66-mhz capable. 4:0 rsvd reserved. returns 00000b when read. configuration header space 44 april 2005 scps096a 4.20 memory base address register (20h) the memory base address register defines the bottom address of a memory- mapped i/o address range used by the bridge to determine when to forward memory transactions from one interface to the other. the upper 12 bits of this register are read/write and correspond to the address bits [31:20]. the lower 20 address bits are assumed to be 00000h; thus, the address range is aligned to a 1m-byte boundary. the bottom four bits are reserved and return 0h when read. see table 4?7 for a complete description of the register contents. bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 4?7. memory base address register bit field name description 15:4 membase memory base. defines the bottom address of the memory address range that determines when to forward memory transactions from one interface to the other. these bits correspond to address bits [31:20] in the memory address. the lower 20 bits are assumed to be 00000h. 3:0 rsvd reserved. returns 0h when read. 4.21 memory limit address register (22h) the memory limit address register defines the upper-limit address of a memory-mapped i/o address range used by the pci2060 bridge to determine when to forward memory transactions from one interface to the other. the upper 12 bits of this register are read/write and correspond to the address bits [31:20]. the lower 20 address bits are assumed to be fffffh; thus, the address range is aligned to a 1m-byte boundary. the bottom 4 bits are reserved and return 0h when read. see table 4?8 for a complete description of the register contents. bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 4?8. memory limit address register bit field name description 15:4 memlimit memory limit. defines the top address of the memory address range that determines when to forward memory transactions from one interface to the other. these bits correspond to address bits [31:20] in the memory address. the lower 20 bits are assumed to be fffffh. 3:0 rsvd reserved. returns 0h when read. 4.22 prefetchable memory base address register (24h) the prefetchable memory base address register defines the bottom address of a prefetchable memory address range used by the pci2060 bridge to determine when to forward memory transactions from one interface to the other. bits [3:0] are read-only and default to 1h to indicate that the pci2060 bridge supports 64-bit memory addressing. the upper 12 bits of this register are read/write and correspond to the address bits [31:20]. the lower 20 address bits are assumed to be 00000h; thus, the address range is aligned to a 1m-byte boundary. see table 4?9 for a complete description of the register contents. bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 table 4?9. prefetchable memory base address register bit field name description 15:4 prebase prefetchable memory base. defines the bottom address of the prefetchable memory address range that determines when to forward memory transactions from one interface to the other. these bits correspond to address bits [31:20] in the memory address. the lower 20 bits are assumed to be 00000h. the prefetchable base-address upper 32-bit register specifies the bit [63:32] of the 64-bit prefetchable memory address. 3:0 64bit 64-bit memory indicator. this field is read-only. it reads 1h indicating that the pci2060 bridge supports 64-bit memory addressing. configuration header space 45 april 2005 scps096a 4.23 prefetchable memory limit address register (26h) the prefetchable memory-limit address register defines the upper-limit address of a prefetchable memory address range that determines when to forward memory transactions from one interface to the other. bits [3:0] are read-only and default to 1h to indicate the pci2060 bridge supports 64-bit memory addressing. the upper 12 bits of this register are read/write and correspond to the address bits [31:20]. the lower 20 address bits are considered fffffh; thus, the address range is aligned to a 1m-byte boundary. see table 4?10 for a complete description of the register contents. bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 table 4?10. prefetchable memory limit address register bit field name description 15:4 prelimit prefetchable memory limit. defines the top address of the prefetchable memory address range that determines when to forward memory transactions from one interface to the other. these bits correspond to address bits [31:20] in the memory address. the lower 20 bits are assumed to be fffffh. the prefetchable-limit upper 32-bit register specifies the bit [63:32] of the 64-bit prefetchable memory address. 3:0 64bit 64-bit memory indicator. this field is read-only. it reads 1h indicating that the pci2060 bridge supports 64-bit memory addressing. 4.24 prefetchable memory base address upper 32-bit register (28h) the prefetchable memory-base address upper 32-bit register and the prefetchable memory-base address register define the base address of the 64-bit prefetchable memory address range used by the pci2060 bridge to determine when to forward memory transactions from one interface to the other. the prefetchable memory base address upper 32-bit register must be programmed to 0000 0000h when 32-bit addressing is being used. see table 4?11 for a complete description of the register contents. bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reset state 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 4?11. prefetchable memory base address upper 32-bit register bit field name description 31:0 prebase prefetchable memory-base upper 32 bits. defines the upper 32 bits of the bottom address of the prefetchable memory address range that determines when to forward memory transactions from one interface to the other. 4.25 prefetchable memory limit address upper 32-bit register (2ch) the prefetchable memory-limit address upper 32-bit register and prefetchable memory-limit address register define the upper-limit address of the 64-bit prefetchable memory address range used by the pci2060 bridge to determine when to forward memory transactions from one interface to the other. the prefetchable memory-limit address upper 32-bit register must be programmed to 0000 0000h when 32-bit addressing is being used. see table 4?12 for a complete description of the register contents. bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reset state 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 4?12. prefetchable memory limit address upper 32-bit register bit field name description 31:0 prelimit prefetchable memory-limit upper 32 bits. defines the upper-limit of the 64-bit prefetchable memory address range that determines when to forward memory transactions from one interface to the other. configuration header space 46 april 2005 scps096a 4.26 i/o base-address upper 16-bit register (30h) the i/o base-address upper 16-bit register and the i/o base-address register define the base address of the 32-bit i/o memory-address range that determines when to forward i/o transactions from one interface to the other. the i/o base-address upper 16-bit register must be programmed to 0000h when 16-bit addressing is being used. see table 4?13 for a complete description of the register contents. bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 4?13. i/o base-address upper 16-bit register bit field name description 15:0 iobase i/o base upper 16 bits. defines the upper 16 bits of the bottom address of the i/o address range that determines when to forward i/o transactions from one interface to the other. 4.27 i/o limit-address upper 16-bit register (32h) the i/o limit-address upper 16-bit register and i/o limit-address register define the upper-limit address of the 32-bit i/o memory-address range used by the pci2060 bridge to determine when to forward i/o transactions from one interface to the other. the i/o limit-address upper 16-bit register must be programmed to 0000h when 16-bit addressing is being used. see table 4?14 for a complete description of the register contents. bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 4?14. i/o limit-address upper 16-bit register bit field name description 15:0 iolimit i/o limit upper 16 bits. defines the upper-limit address of the 32-bit i/o memory address range used by the pci2060 bridge to determine when to forward i/o transactions from one interface to the other. 4.28 capabilities pointer register (34h) the capabilities pointer register points to a linked list of additional capabilities implemented by a device. for the pci2060 bridge, the capabilities pointer register provides the pointer to the pci configuration header where the pci power-management register block resides. the capabilities pointer register is read-only and returns dch when read, indicating the power-management registers are located at pci header offset dch. bit number 7 6 5 4 3 2 1 0 reset state 1 1 0 1 1 1 0 0 4.29 interrupt line register (3ch) the interrupt line register is read/write and communicates interrupt-line routing information. since the bridge does not implement an interrupt signal terminal, this register defaults to 00h. bit number 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 0 0 0 4.30 interrupt pin register (3dh) this register returns 00h when it is read, indicating the pci2060 bridge does not implement an interrupt pin. bit number 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 0 0 0 configuration header space 47 april 2005 scps096a 4.31 bridge control register (3eh) the bridge control register provides extensions to the command register that are specific to a bridge. the bridge control register provides many of the same controls for the secondary interface that are provided by the command register for the primary interface. see table 4?15 for a complete description of the register contents. bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 4?15. bridge control register bit field name description 15:12 rsvd reserved. returns 0h when read. 11 dtserr discard timer serr enable. this bit controls the assertion of p_serr on the primary interface when either the primary discard timer or the secondary discard timer expires and a delayed transaction is discarded from a queue in the bridge. 0 = do not assert p_serr on the primary bus as a result of expiration of either the primary discard timer or the secondary discard timer 1 = assert p_serr on the primary bus if either the primary discard timer or the secondary discard timer expires and a delayed transaction is discarded 10 dtstatus discard timer status. this bit is set to a 1b when either the primary discard timer or the secondary discard timer expires and a delayed completion is discarded from a queue in the bridge. 0 = no discard timer error 1 = discard timer error 9 sec_dt secondary discard timer. selects the number of pci clocks that the pci2060 bridge will wait for a master on the secondary bus to repeat a delayed transaction request. the counter starts once the delayed completion (the completion of the delayed transaction on the primary bus) has reached the head of the downstream queue of the bridge (that is, all ordering requirements have been satisfied and the bridge is ready to complete the delayed transaction with the initiating master on the secondary bus). if the master does not repeat the transaction before the counter expires, then the bridge deletes the delayed transaction from its queue and sets the discard timer status bit. 0 = the secondary discard timer counts 2 15 pci clock cycles 1 = the secondary discard timer counts 2 10 pci clock cycles 8 pri_dis primary discard timer. selects the number of pci clocks that the bridge will wait for a master on the primary bus to repeat a delayed transaction request. the counter starts once the delayed completion (the completion of the delayed transaction on the secondary interface) has reached the head of the upstream queue of the bridge (that is, all ordering requirements have been satisfied and the bridge is ready to complete the delayed transaction with the initiating master on the primary bus). if the master does not repeat the transaction before the counter expires, then the bridge deletes the delayed transaction from its queue and sets the discard timer status bit. 0 = the primary discard timer counts 2 15 pci clock cycles 1 = the primary discard timer counts 2 10 pci clock cycles 7 fbb_en fast back-to-back enable. this bit controls the ability of the pci2060 bridge to generate fast back-to-back transactions to different devices on the secondary interface. 0 = the pci2060 bridge is disabled to generate fast back-to-back transactions on the secondary pci bus 1 = the pci2060 bridge is enabled to generate fast back-to-back transactions on the secondary pci bus 6 srst secondary bus reset. setting this bit to 1b forces the assertion of s_rst on the secondary interface. the s_rst is asserted by the bridge whenever this bit is set or the p_rst terminal on the primary bus is asserted. when this bit is cleared, s_rst on the secondary bus is asserted whenever the primary interface rst is asserted. 0 = do not force the assertion of the s_rst 1 = force the assertion of the s_rst configuration header space 48 april 2005 scps096a table 4?15. bridge control register (continued) bit field name description 5 mam master abort mode. controls how the bridge responds to a master abort that occurs on either interface when the bridge is the master. if this bit is set, the posted write transaction has completed on the requesting interface, and serr enable (bit 8) of the primary command register (offset 04h) is 1b, then p_serr is asserted when a master abort occurs. if the transaction has not completed, then a target abort is signaled. if the bit is cleared, then all 1s are returned on reads and write data is accepted and discarded when a transaction that crosses the bridge is terminated with master abort. 0 = do not report master aborts (returns ffff ffffh on reads and discards data on writes) 1 = the pci2060 bridge returns a target abort on the initiator bus for delayed transactions. for posted write transactions, the bridge asserts p_serr if bit 8 (serr_enb) is set in the primary command register 4 rsvd reserved. returns 0b when read. 3 vga vga enable. this bit modifies the response by the pci2060 bridge to vga-compatible addresses. if this bit is set, then the pci2060 bridge positively decodes and forwards the following accesses on the primary to the secondary bus (and, conversely, blocks the forwarding of these addresses from the secondary to primary bus): ? memory accesses in the range 000a 0000h to 000b ffffh ? i/o addresses in the first 64 kb of the i/o address space (address bits [31:16] are 0000h) and where address bits [9:0] are in the range of 3b0h to 3bbh or 3c0h to 3dfh (inclusive of isa address aliases?address bits [15:10] may possess any value and are not used in the decoding) if the vga enable bit is set, then forwarding of vga addresses is independent of: the value of bit 2 (isa), the i/o address range and memory address ranges defined by the i/o base and limit registers, the memory base and limit registers, and the prefetchable memory base and limit registers of the bridge. the forwarding of vga addresses is qualified by bits 0 (io_enb) and 1 (memory_enb) in the primary command register (offset 04h). 0 = do not forward vga-compatible memory and i/o addresses from the primary to secondary bus (addresses defined above) unless they are enabled for forwarding by the defined i/o and memory address ranges 1 = forward vga-compatible memory and i/o addresses (addresses defined above) from the primary to the secondary bus (if the i/o enable and memory enable bits are set) independent of the i/o and memory address ranges and independent of bit 2 (isa) 2 isa isa enable. this bit modifies the response by the pci2060 bridge to isa i/o addresses. this applies only to i/o addresses that are enabled by the i/o base and i/o limit registers and are in the first 64 kb of pci i/o address space (0000 0000h to 0000 ffffh). if this bit is set, then the pci2060 bridge blocks forwarding i/o transactions from primary to secondary that address the last 768 bytes in each 1 kb block. in the opposite direction (secondary to primary), i/o transactions are forwarded if they address the last 768 bytes in each 1 kb block. 0 = forward downstream all i/o addresses in the address range defined by the i/o base and i/o limit registers 1 = forward upstream isa i/o addresses in the address range defined by the i/o base and i/o limit registers that are in the first 64 kb of pci i/o address space (top 768 bytes of each 1 kb block) 1 serr_en serr enable. controls the forwarding of s_serr assertion to the primary bus. the bridge asserts p_serr on the primary bus when all of the following are true: ? s_serr is asserted on the secondary interface. ? this bit is set. ? bit 8 (serr_enb) is set in the primary command register (offset 04h). 0 = the pci2060 bridge does not assert p_serr on the primary bus in response to the assertion of s_serr on the secondary bus 1 = the pci2060 bridge asserts p_serr on the primary bus in response to the assertion of s_serr on the secondary bus 0 perr_en parity error response enable. controls the bridge response to address and data parity errors on the secondary bus. 0 = the pci2060 bridge does not assert s_perr . bit 8 (datapar) in the secondary status register (offset 1eh) is not set. the pci2060 bridge also does not report any parity errors by asserting p_serr on the primary bus 1 = the pci2060 bridge asserts s_perr and conditionally sets bit 8 (datapar) in the secondary status register (offset 1eh) when a data parity error is detected on the secondary bus. this bit must be set to 1b in order for the pci2060 bridge to assert the p_serr assertion when parity errors are detected on the secondary interface extension registers 49 april 2005 scps096a 5 extension registers the ti extension registers are those registers that lie outside the standard pci-to-pci bridge device configuration space (that is, registers 40h?ffh in the pci configuration space in the pci2060 bridge). these registers can be accessed through configuration reads and writes. the ti extension registers add flexibility and performance benefits to the standard pci-to-pci bridge. mapping of the extension registers is contained in table 4?1. 5.1 chip control register (40h) the chip control register controls the functionality of certain pci transactions. see table 5?1 for a complete description of the register contents. bit number 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 0 0 0 table 5?1. chip control register bit field name description 7:6 rsvd reserved. returns 00b when read. 5 trans_ctrl transaction forwarding control for i/o and memory cycles. 0 = transaction forwarding is enabled and controlled by bits 0 (io_enb) and 1 (memory_enb) in the primary command register (offset 04h) 1 = transaction forwarding is disabled if gpio3 is driven high. bits 0 (io_enb), 1 (memory_enb), and 2 (master_enb) in the primary command register (offset 04h) are set to 000b 4 read_prefetch_dis memory read prefetch disable. when set, bit 4 disables read prefetching on upstream memory read commands. 0 = upstream memory read prefetch is enabled 1 = upstream memory reads prefetch is disabled 3:2 rsvd reserved. returns 00b when read. 1 mw_disconnect_crtl memory write disconnect control. this bit does not affect memory write-and-invalidate transactions. 0 = disconnects on queue full or 4-kb boundaries 1 = disconnects on queue full, 4-kb boundaries, and cache line boundaries 0 rsvd reserved. returns 0b when read. 5.2 extended diagnostic register (41h) bit 0 of the extended diagnostic register resets both the pci2060 bridge and the secondary bus. see t able 5?2 for a complete description of the register contents. bit number 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 0 0 0 table 5?2. extended diagnostic register bit field name description 7:1 rsvd reserved. returns 000 0000b when read. 0 chip_reset chip and secondary bus reset control. setting this bit to 1b causes the pci2060 bridge to perform a chip reset. data buffers, configuration registers, and both the primary and secondary interfaces are reset to their initial state. this bit is self-clearing. extension registers 50 april 2005 scps096a 5.3 arbiter control register (42h) the arbiter control register is used for the bridge internal arbiter. the arbitration scheme used is a two-tier rotational arbitration. the pci2060 bridge is the only secondary bus initiator that defaults to the higher priority arbitration tier. see table 5?3 for a complete description of the register contents. bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 table 5?3. arbiter control register bit field name description 15:10 rsvd reserved. returns 00 0000b when read. 9 bridge_tier_sel bridge tier select. this bit determines in which tier the pci2060 bridge is placed in the two-tier arbitration scheme. 0 = low priority tier 1 = high priority tier 8 gnt8_tier_sel s_gnt8 tier select. this bit determines in which tier the s_gnt8 is placed in the arbitration scheme. 0 = low priority tier 1 = high priority tier 7 gnt7_tier_sel s_gnt7 tier select. this bit determines in which tier the s_gnt7 is placed in the arbitration scheme. 0 = low priority tier 1 = high priority tier 6 gnt6_tier_sel s_gnt6 tier select. this bit determines in which tier the s_gnt6 is placed in the arbitration scheme. 0 = low priority tier 1 = high priority tier 5 gnt5_tier_sel s_gnt5 tier select. this bit determines in which tier the s_gnt5 is placed in the arbitration scheme. 0 = low priority tier 1 = high priority tier 4 gnt4_tier_sel s_gnt4 tier select. this bit determines in which tier the s_gnt4 is placed in the arbitration scheme. 0 = low priority tier 1 = high priority tier 3 gnt3_tier_sel s_gnt3 tier select. this bit determines in which tier the s_gnt3 is placed in the arbitration scheme. 0 = low priority tier 1 = high priority tier 2 gnt2_tier_sel s_gnt2 tier select. this bit determines in which tier the s_gnt2 is placed in the arbitration scheme. 0 = low priority tier 1 = high priority tier 1 gnt1_tier_sel s_gnt1 tier select. this bit determines in which tier the s_gnt1 is placed in the arbitration scheme. 0 = low priority tier 1 = high priority tier 0 gnt0_tier_sel s_gnt0 tier select. this bit determines in which tier the s_gnt0 is placed in the arbitration scheme. 0 = low priority tier 1 = high priority tier extension registers 51 april 2005 scps096a 5.4 p_serr event disable register (64h) the p_serr event disable register enables/disables the serr event on the primary interface. all events are enabled by default. see table 5?4 for a complete description of the register contents. bit number 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 0 0 0 table 5?4. p_serr event disable register bit field name description 7 rsvd reserved. returns 0b when read. 6 delayed_read_to master delayed read time-out. this bit controls the assertion of the p_serr when the pci2060 bridge is unable to transfer any read data from the target after 2 24 attempts. 0 = p_serr is asserted if this event occurs and bit 8 (serr_enb) in the primary command register (offset 04h) is set 1 = p_serr is not asserted if this event occurs 5 delayed_write_to master delayed write time-out. the bit controls the assertion of the p_serr when the pci2060 bridge is unable to deliver delayed write data after 2 24 attempts. 0 = p_serr is asserted if this event occurs and bit 8 (serr_enb) in the primary command register (offset 04h) is set 1 = p_serr is not asserted if this event occurs 4 master_abort_pw master abort on posted write transactions. this bit controls the assertion of the p_serr when the pci2060 bridge receives a master abort when attempting to deliver posted write data. 0 = p_serr is asserted if this event occurs and bit 8 (serr_enb) in the primary command register (offset 04h) is set 1 = p_serr is not asserted if this event occurs 3 target_abort_pw target abort on posted write transactions. this bit controls the assertion of p_serr when it receives a target abort when attempting to deliver posted write data. 0 = p_serr is asserted if this event occurs and bit 8 (serr_enb) in the primary command register (offset 04h) is set 1 = p_serr is not asserted if this event occurs 2 posted_write_to posted write time out. this bit controls the assertion of the p_serr when the pci2060 bridge is unable to deliver posted write data after 2 24 attempts. 0 = p_serr is asserted if this event occurs and bit 8 (serr_enb) in the primary command register (offset 04h) is set 1 = p_serr is not asserted if this event occurs 1 posted_write_perr posted write parity error. this bit controls the assertion of the p_serr when a parity error is detected on the target bus during a posted write transaction. 0 = p_serr is asserted if this event occurs and bit 8 (serr_enb) in the primary command register (offset 04h) is set 1 = p_serr is not asserted if this event occurs 0 rsvd reserved. returns 0b when read. extension registers 52 april 2005 scps096a 5.5 gpio output data register (65h) the gpio output data register controls the data driven on the gpio terminals configured as outputs. if both an output-high bit and an output-low bit are set for the same gpio terminal, then the output-low bit takes precedence. the output data bits have no effect on a gpio terminal that is programmed as an input. see table 5?5 for a complete description of the register contents. bit number 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 0 0 0 table 5?5. gpio output data register bit field name description 7:4 gpio output write_1_to_set the gpio [3:0] pin output data write 1 to set. writing a 1b to any of these bits drives the corresponding bit high on the gpio [3:0] bus if it is programmed as bidirectional. data is driven on the pci clock cycle following completion of the configuration write to this register. writing 0b to these bits has no effect. 3:0 gpio output write_1_to_clear the gpio [3:0] pin output data write 1 to clear. writing a 1b to any of these bits drives the corresponding bit low on the gpio [3:0] bus if it is programmed as bidirectional. data is driven on the pci clock cycle following completion of the configuration write to this register. writing 0b to these bits has no effect. 5.6 gpio output enable register (66h) the gpio output enable register controls the direction of the gpio signal. by default, all gpio terminals are inputs. if both an output-enable bit and an input-enable bit are set for the same gpio terminal, then the input-enable bit takes precedence. see table 5?6 for a complete description of the register contents. bit number 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 0 0 0 table 5?6. gpio output enable register bit field name description 7:4 gpio output enable write_1_to_set the gpio [3:0] output enable write 1 to set. writing a 1b to any of these bits configures the corresponding gpio [3:0] terminal, enables the output driver, and drives the value set in the output data register (65h). writing 0b to this register has no effect. 3:0 gpio output enable write_1_to_clear the gpio [3:0] output enable write 1 to clear. writing 1b to any of these bits configures the corresponding gpio [3:0] terminal as an input only. writing 0b to this register has no effect. 5.7 gpio input data register (67h) this register reads the current state of the gpio terminals. each gpio field in this register is updated on the rising edge of the pci clock following the change in the gpio terminals. see table 5?7 for a complete description of the register contents. bit number 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 0 0 0 table 5?7. gpio input data register bit field name description 7 gpio [3:0] input data gpio3?gpio0 input data. these four bits return the current state of the gpio terminals. each gpio field in this register is updated on the rising edge of the pci clock following the change in the gpio terminals. 3:0 rsvd reserved. returns 0h when read. extension registers 53 april 2005 scps096a 5.8 secondary clock control register (68h) the secondary clock control register controls the secondary clock outputs. see table 5?8 for a complete description of the register contents. bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 5?8. secondary clock control register bit field name description 15:14 rsvd reserved. returns 00b when read. 13 clkout9_disable s_clkout9 disable 0 = s_clkout9 enabled 1 = s_clkout9 disabled and driven low 12 clkout8_disable s_clkout8 disable 0 = s_clkout8 enabled 1 = s_clkout8 disabled and driven low 11 clkout7_disable s_clkout7 disable 0 = s_clkout7 enabled 1 = s_clkout7 disabled and driven low 10 clkout6_disable s_clkout6 disable 0 = s_clkout6 enabled 1 = s_clkout6 disabled and driven low 9 clkout5_disable s_clkout5 disable 0 = s_clkout5 enabled 1 = s_clkout6 disabled and driven low 8 clkout4_disable s_clkout4 disable 0 = s_clkout4 enabled 1 = s_clkout4 disabled and driven low 7:6 clkout3_disable s_clkout3 disable 00, 01, 10 = s_clkout3 enabled 11 = s_clkout3 disabled and driven low 5:4 clkout2_disable s_clkout2 disable 00, 01, 10 = s_clkout2 enabled 11 = s_clkout2 disabled and driven low 3:2 clkout1_disable s_clkout1 disable 00, 01, 10 = s_clkout1 enabled 11 = s_clkout1 disabled and driven low 1:0 clkout0_disable s_clkout0 disable 00, 01, 10 = s_clkout0 enabled 11 = s_clkout0 disabled and driven low extension registers 54 april 2005 scps096a 5.9 p_serr status register (6ah) the p_serr status register indicates the cause of p_serr assertion. see table 5?9 for a complete description of the register contents. bit number 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 0 0 0 table 5?9. p_serr status register bit field name description 7 rsvd reserved. returns 0b when read. 6 delayed_read_to master delayed read time-out. p_serr is asserted since the pci2060 bridge was unable to read data from the target after 2 24 attempts. 5 delayed_write_to master delayed write time-out. p_serr is asserted since the pci2060 bridge was unable to deliver delayed write data after 2 24 attempts. 4 master_abort_pw master abort on posted write transactions. p_serr is asserted since the pci2060 bridge received a master abort when attempting to deliver posted write data. 3 target_abort_pw target abort on posted writes. p_serr is asserted since the pci2060 bridge received a target abort when delivering posted write data. 2 posted_write_to master posted write time-out. p_serr is asserted since the pci2060 bridge was unable to deliver posted write data to the target after 2 24 attempts. 1 posted_write_perr posted write parity error. p_serr is asserted since a posted write data parity error was detected on the target bus. 0 rsvd reserved. returns 0b when read. 5.10 capability id register (dch) the capability id register identifies the linked list item as the register for pci power management. the capability id register is read-only and returns 01h when read, which is the unique id assigned by the pci sig for the pci location of the capabilities pointer and the value. bit number 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 0 0 1 5.11 next item pointer register (ddh) the next item pointer register indicates the next item in the linked list of pci power-management capabilities. the next-item pointer returns e4h in compactpci mode, indicating that the pci206 bridge supports more than one extended capability, but in all other modes returns 00h, indicating that only one extended capability is provided. bit number 7 6 5 4 3 2 1 0 reset state 1 1 1 0 0 1 0 0 extension registers 55 april 2005 scps096a 5.12 power-management capabilities register (deh) the power-management capabilities register contains information on the capabilities of the pci2060 functions related to power management. the pci2060 function supports d0, d1, d2, and d3 power states when ms1 is low. the pci2060 bridge does not support any power states when ms1 is high. see table 5?10 for a complete description of the register contents. bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 x x 0 0 0 0 0 0 0 x x table 5?10. power-management capabilities register bit field name description 15:11 pme_support pme support. this five-bit field is read-only and returns 00000b when read, indicating that the pci2060 bridge does not support the pme terminal. 10 d2_support d2 support. this bit returns 1b when ms0 is 0b, indicating that the bridge function supports the d2 device power state. this bit returns 0b when ms0 is 1b, indicating that the bridge function does not support the d2 device power state. 9 d1_support d1 support. this bit returns 1b when ms0 is 0b, indicating that the bridge function supports the d1 device power state. this bit returns 0b when ms0 is 1b, indicating that the bridge function does not support the d1 device power state. 8:6 aux_current 3.3 v aux auxiliary current requirements. this requirement is design-dependent. 5 dsi device specific initialization. this bit returns 0b when read, indicating that the pci2060 bridge does not require special initialization beyond the standard pci configuration header before a generic class driver is able to use it. 4 rsvd reserved. returns 0b when read. 3 pme_clk pme clock. this bit returns 0b indicating that the pci2060 bridge does not support the pme terminal. 2:0 pm_version version. this three-bit field returns the pci bus power management interface specification revision number. this three-bit field returns 001b when ms0 is 1b, indicating that the pci2060 bridge supports pci bus power management interface specification , revision 1.0. this three-bit field returns 010b when ms0 is 0b, indicating that the pci2060 bridge supports pci bus power management interface specification , revision 1.1. 5.13 power-management control/status register (e0h) this register determines and changes the current power state of the pci2060 bridge. the contents of this register are not affected by the internally generated reset caused by the transition from the d3 hot to d0 state in reverse mode. in forward mode, no internal reset is generated when transitioning from the d3 hot state to the d0 state. see table 5?11 for a complete description of the register contents. bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 5?11. power-management control/status register bit field name description 15 pme_stat pme status. this bit returns 0b when read since the pci2060 bridge does not support pme signaling. 14:13 data_scale data scale. this 2-bit field returns 00b when read since the data register is not implemented. 12:9 data_sel data select. this 4-bit field returns 0h when read since the data register is not implemented. 8 pme_en pme enable. this bit returns 0b when read since the pci2060 bridge does not support pme signaling. 7:2 rsvd reserved. returns 000000b when read. 1:0 pwr_state power state. this 2-bit field determines the current power state of the function and sets the function to a new power state. this field is encoded as follows: 00 = d0 01 = d1 10 = d2 11 = d3 hot extension registers 56 april 2005 scps096a 5.14 power-management bridge-support extension register (e2h) the power-management bridge-support extension register indicates to the host software the state of the secondary bus when the pci2060 bridge is placed in d3. see table 5?12 for a complete description of the register contents. bit number 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 0 0 0 table 5?12. power-management bridge-support extension register bit field name description 7 bpcce bus power/clock control enable. when the bpcce terminal is tied high, this bit reads 1b to indicate that the bus power/clock control mechanism is enabled, as described in bstate (bit 6). when the bpcce terminal is tied low, this bit reads 0b to indicate that the bus power/clock control mechanism is disabled (secondary clocks are not disabled when this device is placed in d3 hot ). 6 bstate b2_b3 support for d3 hot . when the bpcce bit (bit 7) reads 1b, this bit reads 1b to indicate that the secondary bus clock outputs are stopped and driven low when this device is placed in d3 hot . this bit is not defined when the bpcce bit reads 0b. 5:0 rsvd reserved 5.15 power-management data register (e3h) the data register is an optional, 8-bit, read-only register that provides a mechanism for the function to report state-dependent operating data such as power consumption or heat dissipation. the pci2060 bridge does not implement the power-management data register. this register returns 00h when read. bit number 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 0 0 0 5.16 hot-swap capability id register (e4h) the hot-swap capability id register identifies the linked list item as the register for cpci hot-swap capabilities. the register returns 06h when read, which is the unique id assigned by the picmg for pci location of the capabilities pointer and the value. in intel tm -compatible mode, this register is read-only and defaults to 00h. bit number 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 1 1 0 5.17 hot-swap next-item pointer register (e5h) the hot-swap next-item pointer register indicates the next item in the linked list of the pci extended capabilities. this register returns 00h indicating no additional capabilities are supported. bit number 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 0 0 0 extension registers 57 april 2005 scps096a 5.18 hot-swap control and status register (e6h) the compactpci hot-swap control and status register provides the control and status information about the compact pci hot-swap resources. see table 5?13 for a complete description of the register contents. bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 5?13. hot-swap control and status register (e6h) bit field name description 7 ins hs_enum insertion status. when set, the hs_enum output is driven by the pci2060 device. this bit defaults to 0b, and is set after a pci reset occurs, the preload of serial rom is complete, the ejector handle is closed (hs_switch low), and the ext bit is 0b. thus, this bit is set following an insertion when the board implementing the pci2060 bridge is ready for configuration. this bit cannot be set by software. 6 ext hs_enum extraction status. when set, the hs_enum output is driven by the pci2060 device. this bit defaults to 0b, and is set when the ejector handle is opened (hs_switch high) and ins bit is 0b. thus, this bit is set when the board implementing the pci2060 bridge is about to be removed. this bit cannot be set by software. 5:4 rsvd reserved. returns 00b when read. 3 loo led on/off. this bit defaults to 0b, and controls the external led indicator (hs_led) under normal conditions. however, for a duration following a pci_rst , the hsled output is driven high by the pci2060 bridge and this bit is ignored. 0 = led off (hs_led low) 1 = led on (hs_led high) following pci_rst , the hs_led output is driven high by the pci2060 bridge until both the secondary clock control register is loaded and the ejector handle is closed (hs_switch low). when these conditions are met, the hsled is under software control via the loo bit. 2 rsvd reserved. returns 0b when read. 1 eim hs_enum interrupt mask. this bit allows the hs_enum output to be masked by software. the ins and ext bits are set independently from the eim bit. 0 = enable hs_enum output 1 = mask hs_enum output 0 rsvd reserved. returns 0b when read. extension registers 58 april 2005 scps096a 5.19 ti diagnostic register (f0h) this register controls the behavior of write combining and memory write-and-invalidate commands. this register also limits burst size for both upstream and downstream transactions to 32 doublewords. see table 5?14 for a complete description of the register contents. bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset state 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 5?14. ti diagnostic register bit field name description 15:5 rsvd reserved. returns 000 0000 0000b when read. 4 down_flow_control downstream flow control. setting this bit to 1b causes the pci2060 bridge to limit all burst transactions (memory read, memory read line, memory read multiple, memory write, and memory write-and-invalidate) that are targeting the secondary bus to 32 doublewords. 0 = disable upstream flow control 1 = enable upstream flow control 3 rsvd reserved. returns 0b when read. 2 up_flow_control upstream flow control. setting this bit to 1b causes pci2060 bridge to limit all burst transactions (memory read, memory read line, memory read multiple, memory write, and memory write-and-invalidate) that are targeting the primary bus to 32 doublewords. 0 = disable upstream flow control 1 = enable upstream flow control 1 mwi_mw_conversion mwi/mw conversion. this bit causes all memory write-and-invalidate transactions to be converted to memory write transactions. 0 = mwi transactions are only converted to mw transactions if there is not enough space in the fifo for a cache line or data. 1 = all mwi transactions are converted to mw transactions. 0 pw_combining_dis disable posted write combining. 0 = enable posted write combining 1 = disable posted write combining electrical characteristics 59 april 2005 scps096a 6 electrical characteristics 6.1 absolute maximum ratings over operating temperature ranges ? supply voltage range: v cc ?0.5 v to 3.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p_v ccp ?0.5 v to 6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . s_v ccp ?0.5 v to 6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v i : cmos ? ?0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v i : pci ?0.5 v to 6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range, v o : cmos ? ?0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range, v o : pci ?0.5 v to 6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input clamp current, i ik (v i < 0 or v i > v cc ) (see note 1) 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output clamp current, i ok (v o < 0 or v o > v cc ) (see note 2) 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg ?65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . virtual junction temperature, t j 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not i mplied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ? cmos terminals are j6, j18, j19, k1, k2, k5, k6. k14, k17, k18, l1, l2, l5, l14, l15, l17, m1, m3, m6, n1, n2, n6, p1 for the ghk-pa ckaged device. all signal terminals other than cmos terminals are pci terminals. notes: 1. applies for external input and bidirectional buf fers. pci terminals are measured with respect to v ccp instead of v cc . the limit is specified for a dc condition. 2. applies for external input and bidirectional buffers. pci terminals are measured with respect to v ccp instead of v cc . the limit is specified for a dc condition. electrical characteristics 60 april 2005 scps096a 6.2 recommended operating conditions (see note 3) operation min nom max unit v cc supply voltage (core) commercial 3.3 v 3 3.3 3.6 v p_v ccp pci primary bus i/o clamping rail voltage commercial 3.3 v 3 3.3 3.6 v p_v ccp pci primary bus i/o clamping rail voltage commercial 5 v 4.75 5 5.25 v s_v ccp pci secondary bus i/o clamping rail voltage commercial 3.3 v 3 3.3 3.6 v s_v ccp pci secondary bus i/o clamping rail voltage commercial 5 v 4.75 5 5.25 v pci 3.3 v 0.5 v ccp v ccp pci 5 v 2 v ccp v ih ? high-level input voltage cmos 0.7 v cc v cc v v ih ? high-level input voltage clk ? 0.57 v ccp v ccp v p_rst_l 0.77 v ccp v ccp trst_l 0.9 v cc v cc pci 3.3 v 0 0.3 v ccp v il ? low-level input voltage pci 5 v 0 0.8 v v il ? low-level input voltage cmos 0 0.2 v cc v clk ? 0 0.2 v ccp v i input voltage pci 0 v ccp v v i input voltage cmos 0 v ccp v v o ? output voltage output voltage 0 v cc v t t input transition time (t r and t f ) pci 1 4 ns t t input transition time (t r and t f ) cmos 0 6 ns t a operating ambient temperature range pci2060 0 25 70 c t a operating ambient temperature range pci2060i ?40 25 85 c t j virtual junction temperature 0 25 115 c notes: 3. unused terminals (input or i/o) must be held high or low to prevent them from floating. ? applies to external input and bidirectional buffers without hysteresis ? applies to external output buffers these junction temperatures reflect simulation conditions. the customer is responsible for verifying junction temperature. ? clk includes p_clk and s_clk terminals. electrical characteristics 61 april 2005 scps096a 6.3 electrical characteristics over recommended operating conditions parameter terminals operation test conditions min max unit pci 3.3 v i oh = ?0.5 ma 0.9 v cc v oh high-level output voltage pci 5 v i oh = ?2 ma 2.4 v v oh high-level output voltage cmos1 ? i oh = ?4 ma 2.1 v cmos2 ? i oh = ?8 ma 2.1 pci 3.3 v i ol = 1.5 ma 0.1 v cc v ol low-level output voltage pci 5 v i oh = ?2 ma 0.55 v v ol low-level output voltage cmos1 ? i oh = 4 ma 0.5 v cmos2 ? i oh = 8 ma 0.5 i ih high-level input current input terminals v i = v ccp 10 a i ih high-level input current i/o terminals v i = v ccp 10 a i ih high-level input current i/o terminals v i = v ccp 10 a input terminals v i = gnd ?1 i il low-level input current i/o terminals v i = gnd ?10 a i il low-level input current pu terminals ? v i = gnd ?60 a i oz high-impedance output current output terminals v o = v ccp or gnd 10 a ? cmos1 includes terminals k1, k2, k5, k6 for the ghk-packaged device. ? cmos2 includes terminals k17, l1, l2, l5, l14, m1, m3, m6, n1, n2, n6, p1 for the ghk-packaged device. for i/o terminals, the input leakage current (i il and i ih ) includes the i oz leakage of the disabled output. ? pu terminals include tdi, tms, and trst_l. these are pulled up with internal resistors. electrical characteristics 62 april 2005 scps096a 6.4 66-mhz pci clock signal ac parameters note: v t(1) = 2.0 v for 5-v clocks; 0.5 v cc for 3.3-v clocks v t(2) = 1.5 v for 5-v clocks; 0.4 v cc for 3.3-v clocks v t(3) = 0.8 v for 5-v clocks; 0.3 v cc for 3.3-v clocks t (h) t c t (l) t (h) t (l) t r(sclk) t f(sclk) t c t s t s v t(1) v t(2) v t(3) v t(1) v t(2) v t(3) p_clk s_clk t r(sclk) t f(sclk) figure 6?1. pci clock signal ac parameter measurements parameter min max unit t c p_clk, s_clk cycle time 15 30 ns t (h) p_clk, s_clk high time 6 ns t (l) p_clk, s_clk low time 6 ns t (pss) p_clk, s_clk slew rate (0.2 v cc to 0.6 v cc ) 1.5 4 v/ns t d(sclk) delay from p_clk to s_clk 0 7 ns t r(sclk) p_clk rising to s_clk rising 0 7 ns t f(sclk) p_clk falling to s_clk falling 0 7 ns t d(skew) s_clk0 duty cycle skew from p_clk duty cycle 0.750 ns t sk s_clkx to sclky 0.500 ns electrical characteristics 63 april 2005 scps096a 6.5 66-mhz pci signal timing note: v test = 1.5 v for 5-v signals; 0.4 v cc for 3.3-v signals valid valid v test t v t (inval) t on t off t h t su clk output input figure 6?2. pci signal timing measurement conditions parameter min max unit t v(bus) clk to signal valid delay?bused signals (see notes 4, 5, and 6) 2 6 ns t v(ptp) clk to signal valid delay?point-to-point (see notes 4, 5, and 6) 2 6 ns t on float to active delay (see notes 4, 5, and 6) 2 ns t off active to float delay (see notes 4, 5, and 6) 14 ns t su(bus) input setup time to clk?bused signal (see notes 4, 5, and 6) 3 ns t su(ptp) input setup time to clk?point-to-point (see notes 4, 5, and 6) 5 ns t h input signal hold time from clk (see notes 4 and 5) 0 ns notes: 4. see figure 6?2 5. all primary interface signals are synchronized to p_clk and all secondary interface signals are synchronized to s_clk. 6. bused signals are as follows: p_ad, p_c/be , p_par, p_perr , p_serr , p_frame , p_irdy , p_trdy , p_lock , p_devsel , p_stop , p_idsel, s_ad, s_c/be , s_par, s_perr , s_serr , s_frame , s_irdy , s_trdy , s_lock , s_devsel , s_stop point-to-point signals are as follows: p_req , s_reqx , p_gnt , s_gntx electrical characteristics 64 april 2005 scps096a 6.6 parameter measurement information ? c load includes the typical load-circuit distributed capacitance. c load test point timing input (see note a ) out-of-phase output t pd 50% v cc 50% v cc v cc 0 v 0 v 0 v 0 v 0 v v ol t h t su v oh v oh v ol high-level input low-level input t w voltage waveforms propagation delay times load circuit voltage waveforms setup and hold times input rise and fall times voltage waveforms pulse duration t pd t pd t pd v load i oh i ol from output under test 90% v cc 10% v cc t f t r output control (low-level enabling) waveform 1 (see notes b and c) waveform 2 (see notes b and c) v ol v oh v oh ? 0.3 v t pzl t pzh t plz t phz voltage waveforms enable and disable times, 3-state outputs v ol + 0.3 v 0 v 0 v 50% v cc 50% v cc t en t dis t pd t pzh t pzl t phz t plz c load ? (pf) i ol (ma) timing parameter 50 8 ?8 0 3 1.5 ? 50 8 8 ?8 ?8 load circuit parameters = 50 ? , where v ol = 0.6 v, i ol = 8 ma i ol 50 ? v load ?v ol i oh (ma) v load (v) data input in-phase output input (see note a) v cc v cc v cc 50% v cc 50% v cc 50% v cc 50% v cc v cc v cc 50% v cc 50% v cc 50% v cc 50% v cc v cc 50% v cc 50% v cc 50% v cc 50% v cc 50% v cc 50% v cc notes: a. phase relationships between waveforms were chosen arbitrarily. all input pulses are supplied by pulse generators having the following characteristics: prr = 1 mhz, z o = 50 ? , t r 6 ns, t f 6 ns. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. for t plz and t phz , v ol and v oh are measured values. 50% v cc figure 6?3. load circuit and voltage waveforms electrical characteristics 65 april 2005 scps096a 6.7 pci bus parameter measurement information t w t su pclk rstin figure 6?4. rstin timing waveforms mechanical data 66 april 2005 scps096a 7 mechanical data the pci2060 device is available in the 257-terminal microstar bga ? package (ghk). the following figure shows the mechanical dimensions for the ghk package. |
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