the 56f802 is a member of the 56800 core-based family of hybrid controllers. it combines, on a single chip, the processing power of a dsp and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. because of its low cost, configuration flexibility, and compact program code, the 56f802 is well-suited for many applications. the 56800 core is based on a harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. the microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact code for both dsp and mcu applications. the instruction set is also highly efficient for c compilers to enable rapid development of optimized control applications. jtag/once pll power mgmt up to 4 gpio cop/watchdog 6-channel pwm dual adc with 5 channels sci data memory 56800 core 30/40 mips 2k boot flash 1k ram program memory 8k flash 1k ram 2k flash (2) 16-bit quad timers benefits ? on-board voltage regulator and power management is designed to reduce overall system cost by allowing for a single supply voltage ? internal relaxation oscillator for cost- sensitive applications by eliminating the need for an external crystal ? flash memory is engineered to provide reliable, non-volatile memory storage, eliminating the need for external storage devices ? easy to program with flexible application development tools ? simple updating of flash memory through sci or once?, using on-chip boot loader ? program can boot directly from flash ? supports multiple motors or multi-phase control ? patented distortion correction in pwm for lower-risk, better performing control ? pwm and adc modules are tightly coupled to reduce processing overhead ? internal low voltage interrupts ? simple interface with other asynchronous serial communication devices and off-chip ee memory 56f802 16-bit hybrid controller ? up to 40 mips operation at 80mhz core frequency ? dsp and mcu functionality in a unified, c-efficient architecture ? mcu-friendly instruction set supports both dsp and controller functions: mac, bit manipulation unit, 14 addressing modes ? 12k on-chip flash - 8k program flash - 2k data flash - 2k boot flash ? 1k program ram ? 1k data ram ? hardware do and rep loops ? 6-channel pwm module ?t wo 12-bit adcs (1 x 2 channel, 1 x 3 channel) ? serial communications interface (sci) ?t wo general purpose quad timers ?j t ag/once port for debugging ? on-chip relaxation oscillator ? 32-pin lqfp package ?4 shared gpio energy information ? fabricated in high-density cmos with 5v-tolerant, ttl-compatible digital inputs ? uses a single 3.3v power supply ? on-chip regulators for digital and analog circuitry to lower cost and reduce noise ? integrated power supervisor ?w ait and stop modes available t arget applications hybrid flash solution 56f802 16-bit hybrid controller ? home appliances ?hvac ? pumps ? industrial fans ? exercise equipment ? compressors ? noise cancellation ? remote monitoring ?t achometers ? cable test equipment ? general purpose devices ? switched-mode power supplies f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola and the stylized m logo are registered in the u.s. patent and trademark office. this product incorporates superflash ? technology licensed from sst. all other product or service names are the property of their respective owners. ? motorola, inc. 2003 DSP56F802PB/d rev 2 ordering information aw ard-winning development environment ? processor expert? (pe) technology provides a rapid application design (rad) tool that combines easy-to-use component-based software application creation with an expert knowledge system. ? the codewarrior? integrated development environment (ide) is a sophisticated tool for code navigation, compiling and debugging. a comprehensive set of evaluation modules (evms) and development system cards will support concurrent engineering. together, pe, the codewarrior tool suite and evms create a comprehensive, scalable tools solution for easy, fast and efficient development. hybrid flash solution 56f802 product documentation 56f802 peripheral circuit features ? pulse width modulator (pwm) with six pwm outputs with dead-time insertion; supports both center- and edge-aligned modes ?t wo 12-bit analog-to-digital converters (adcs), which support two simultaneous conversions; adc and pwm modules can be synchronized ?t wo general purpose quad timers ? serial communication interface (sci) ? four multiplexed general purpose i/o (gpio) pins ? computer operating properly (cop)/ w atchdog timer ? external reset pin for hardware reset ? on-chip relaxation oscillator ?jt ag/once? for unobtrusive, processor speed-independent debugging ? software-programmable, phase lock loop-based frequency synthesizer 56f802 memory features ? harvard architecture permits as many as three simultaneous accesses to program and data memory ? on-chip memory including a low-cost, high-volume flash solution - 12k on-chip flash - 8k program flash - 2k data flash - 2k boot flash - 1k program ram - 1k data ram ? programmable boot flash supports customized boot code and field upgrades of stored code through jtag interface 56800 core features ? efficient 16-bit 56800 family hybrid controller engine with dual harvard architecture ? as many as 40 million instructions per second (mips) at 80mhz core frequency ? single-cycle 16 x 16-bit parallel multiplier-accumulator (mac) ?t wo 36-bit accumulators including extension bits ? 16-bit bidirectional barrel shifter ? parallel instruction set with unique addressing modes ? hardware do and rep loops ? three internal address buses ? four internal data buses ? instruction set supports both dsp and controller functions ? controller-style addressing modes and instructions for compact code ? efficient c compiler and local variable support ? software subroutine and interrupt stack with depth limited only by memory ?jt ag/once debug programming interface dsp56800 detailed description of the 56800 family manual family architecture, and 16-bit dsp core processor and the instruction set order number: dsp56800fm/d dsp56f80x detailed description of memory, users manual peripherals, and interfaces of the 56f801, 56f802, 56f803, 56f805, and 56f807 order number: dsp56f801-7um/d dsp56f802 electrical and timing specifications, t echnical data pin descriptions, and package sheet descriptions order number: dsp56f802/d dsp56f802 summary description and block diagram product brief of the core, memory, peripherals and interfaces order number: DSP56F802PB/d p art supply p ackage type pin count frequency order number voltage (mhz) dsp56f802 3.0C3.6v low-profile quad flat pack (lqfp) 32 80 dsp56f802ta80 dsp56f802 3.0C3.6v low-profile quad flat pack (lqfp) 32 60 dsp56f802ta60 dsp56f802 3.0C3.6v low-profile quad flat pack (lqfp) 32 80 spak56f802ta80 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
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