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c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 5 - m a r . , 2 0 0 8 a p w 7 0 6 5 w w w . a n p e c . c o m . t w 1 a n p e c r e s e r v e s t h e r i g h t t o m a k e c h a n g e s t o i m p r o v e r e l i a b i l i t y o r m a n u f a c t u r a b i l i t y w i t h o u t n o t i c e , a n d a d v i s e c u s t o m e r s t o o b t a i n t h e l a t e s t v e r s i o n o f r e l e v a n t i n f o r m a t i o n t o v e r i f y b e f o r e p l a c i n g o r d e r s . s y n c h r o n o u s b u c k p w m c o n t r o l l e r single 12v power supply required fast transient response - 0~90% duty ratio 0.8v reference with 1% accuracy shutdown function by controlling comp pin voltage internal soft-start (3.4ms) function voltage mode pwm control design under-voltage protection o v e r - c u r r e n t p r o t e c t i o n - s e n s e l o w s i d e m o s f e t ? s r d s ( o n ) 300khz fixed switching frequency sop-8 package l e a d f r e e a n d g r e e n d e v i c e s a v a i l a b l e ( r o h s c o m p l i a n t ) f e a t u r e s a p p l i c a t i o n s g e n e r a l d e s c r i p t i o n the apw7065 uses fixed 300khz switching frequency, voltage mode, and synchronous pwm controller which drives dual n-channel mosfets. the device integrates the control, monitoring and protection functions into a single package, provides one controlled power output with under-voltage and over-current protections. the apw7065 provides excellent regulation for output load variation. the internal 0.8v temperature- compensated reference voltage is designed to meet the requirement of low output voltage applications. an built-in digital soft-start with fixed soft-start interval prevents the output voltage from overshoot as well as limiting the input current. the apw7065 with excellent protection functions: por, ocp and uvp. the power-on-reset (por) circuit can monitor vcc supply voltage exceeds its threshold voltage while the controller is running, and a built-in digital soft-start provides output with controlled voltage rise. the over-current protection (ocp) monitors the output current by using the voltage drop across the lower mosfet?s r ds(on) , comparing with internal v ocp (0.29v), when the output current reaches the trip point, the controller will run the soft-start function until the fault events are removed. the under - voltage protection (uvp) monitors the voltage of fb pin for short-circuit protection, when the v fb is less than 50% of v ref (0.4v), the controller will shutdown the ic directly. p i n c o n f i g u r a t i o n s o p - 8 graphics card mother board 1 2 3 4 8 7 6 5 phase comp fb vcc boot ugate gnd lgate (apw7065) s i m p l i f i e d a p p l i c a t i o n c i r c u i t v out 12v v in l apw7065
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 5 - m a r . , 2 0 0 8 a p w 7 0 6 5 w w w . a n p e c . c o m . t w 2 o r d e r i n g a n d m a r k i n g i n f o r m a t i o n b l o c k d i a g r a m n o t e : a n p e c l e a d - f r e e p r o d u c t s c o n t a i n m o l d i n g c o m p o u n d s / d i e a t t a c h m a t e r i a l s a n d 1 0 0 % m a t t e t i n p l a t e t e r m i n a t i o n f i n i s h ; w h i c h a r e f u l l y c o m p l i a n t w i t h r o h s . a n p e c l e a d - f r e e p r o d u c t s m e e t o r e x c e e d t h e l e a d - f r e e r e q u i r e m e n t s o f i p c / j e d e c j - s t d - 0 2 0 c f o r m s l c l a s s i f i c a t i o n a t l e a d - f r e e p e a k r e f l o w t e m p e r a t u r e . a n p e c d e f i n e s ? g r e e n ? t o m e a n l e a d - f r e e ( r o h s c o m p l i a n t ) a n d h a l o g e n f r e e ( b r o r c l d o e s n o t e x c e e d 9 0 0 p p m b y w e i g h t i n h o m o g e n e o u s m a t e r i a l a n d t o t a l o f b r a n d c l d o e s n o t e x c e e d 1 5 0 0 p p m b y w e i g h t ) . apw7065 handling code temp. range package code apw7065 k : apw7065 xxxxx xxxxx - date code assembly material package code k : sop-8 operating ambient temp. range e : -20 to 70 c handling code tr : tape & reel assembly material l : lead free device g : halogen and lead free device gate control oscillator digital soft start power- on- reset phase lgate fb gnd vcc boot ugate 50%v ref error amp pwm comparator u.v.p comparator sawtooth wave : 2 comp 0.29v o.c.p comparator v ref f osc 300khz sense low side
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 5 - m a r . , 2 0 0 8 a p w 7 0 6 5 w w w . a n p e c . c o m . t w 3 a p p l i c a t i o n c i r c u i t symbol parameter rating unit vcc vcc to gnd - 0.3 ~ 16 v boot boot to phase - 0.3 ~ 16 v ugate ugate to phase <400n s pulse width >400n s pulse width - 5 ~ boot+5 - 0.3 ~ boot+0.3 v lgate lgate to gnd <400n s pulse width >400n s pulse width - 5 ~ vcc+5 - 0 .3 ~ vcc+0.3 v phase phase to gnd < 200 n s pulse width > 200 n s pulse width - 10 ~ 30 - 0.3 ~ 16 v comp , fb comp , fb to gnd - 0.3 ~ 7 v t j junction temperature range - 20 ~ 150 o c t stg storage temperature - 65 ~ 150 o c t sdr maximum lead soldering tempe rature, 10 seconds 260 o c a b s o l u t e m a x i m u m r a t i n g s (note 1) v out 470 m fx2 vcc boot ugate phase lgate gnd fb 12v v in comp 0.1 m f apm2509 apm2506 1 m f 1 m f 1 m h 470 m f 1 m h 470 m fx2 2k 1k 18r 68nf 8.2nf 33nf 2.7k 1 2 3 4 5 6 7 8 2.2r 1n4148 2n7002 (12v) (1.2v) on/off q1 q2 q3 n o t e 1 : a b s o l u t e m a x i m u m r a t i n g s a r e t h o s e v a l u e s b e y o n d w h i c h t h e l i f e o f a d e v i c e m a y b e i m p a i r e d . e x p o s u r e t o a b s o l u t e m a x i m u m r a t i n g c o n d i t i o n s f o r e x t e n d e d p e r i o d s m a y a f f e c t d e v i c e r e l i a b i l i t y . t h e r m a l c h a r a c t e r i s t i c s symbol parameter value unit q ja junction - to - ambient thermal resistance in free air sop - 8 75 o c/w q jc junction - to - case thermal resistance sop - 8 28 o c/w
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 5 - m a r . , 2 0 0 8 a p w 7 0 6 5 w w w . a n p e c . c o m . t w 4 symbol parameter range unit v cc vcc supply voltage 10 .8 ~ 13.2 v v out converter output voltage 0.8 ~ 5 v v in converter input voltage 2.9 ~ 13.2 v i out converter output current 0 ~ 2 0 a t a ambient temperature range - 20 ~ 70 o c t j junction temper ature range - 20 ~ 125 o c r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s e l e c t r i c a l c h a r a c t e r i s t i c s u n l e s s o t h e r s w i s e s p e c i f i e d , t h e s e s p e c i f i c a t i o n s a p p l y o v e r v c c = 1 2 v , a n d t a = - 2 0 ~ 7 0 o c . t y p l c a l v a l u e s a r e a t t a = 2 5 o c . apw7 065 symbol parameter test conditions min typ max unit supply current i vcc vcc nominal supply current ugate and lgate open 5 10 ma vcc shutdown supply current ugate, lgate = gnd 1 2 ma power - on - reset rising vcc threshold 9 9.5 10 v fal ling vcc threshold 7.5 8 8.5 v comp shutdown threshold 1.2 v comp shutdown hysteresis 0.1 v oscillator f osc free running frequency 255 300 345 khz d v osc ramp amplitude 1. 6 v p - p reference voltage v ref reference voltage measured at fb pin 0.8 v accuracy t a = - 20~70 c - 1 .0 + 1 .0 % error amplifier gain open loop gain r l =10k, c l =10p f (note 2 ) 8 8 db gbwp open loop bandwidth r l =10k, c l =10p f (note 2 ) 15 mhz sr slew rate r l =10k, c l =10p f (note 2 ) 6 v/ m s fb input current v fb = 0.8v (not e 2 ) 0.1 1 m a v comp comp high voltage 5.5 v v comp comp low voltage 0 v
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 5 - m a r . , 2 0 0 8 a p w 7 0 6 5 w w w . a n p e c . c o m . t w 5 apw70 65 symbol parameter test conditions min typ max unit error amplifier (cont.) i comp comp source current v comp =2v 5 ma i comp comp sink current v comp =2v 5 ma gate drivers i ugate upper gate source current boot = 12 v, v ugate - v phase = 2 v 2.6 a i ugate upper gate s ink current boot = 12 v, v ugate - v phase = 2 v 1.05 a i l gate low er gate source current vcc = 12 v, v l gate = 2 v 4.9 a i lgate low er gate s ink current vcc = 12 v, v l gate = 2 v 1.4 a r ugate upper gate s ource impedance boot = 12v, i ug ate = 0. 1 a 2 3 w r ugate upper gate sink impedance boot = 12v, i ugate = 0. 1 a 1.6 2.4 w r l gate low er gate source impedance vcc = 12v, i l gate = 0. 1 a 1.3 1.95 w r lgate lower gate sink impedance vcc = 12v, i l gate = 0. 1 a 1.25 1.8 8 w t d dead time 20 ns protections v ocp over - current reference voltage t a = - 20~70 c 0. 2 7 0. 2 9 0. 3 1 v v uvp under - voltage threshold trip point percent of v ref 45 50 55 % soft - start t ss soft - start interval 2 3.4 5 m s e l e c t r i c a l c h a r a c t e r i s t i c s ( c o n t . ) u n l e s s o t h e r s w i s e s p e c i f i e d , t h e s e s p e c i f i c a t i o n s a p p l y o v e r v c c = 1 2 v a n d t a = - 2 0 ~ 7 0 o c . t y p l c a l v a l u e s a r e a t t a = 2 5 o c . f u n c t i o n a l p i n d e s c r i p t i o n b o o t ( p i n 1 ) a b o o t s t r a p c i r c u i t w i t h a d i o d e c o n n e c t e d t o v c c i s u s e d t o c r e a t e a v o l t a g e s u i t a b l e t o d r i v e a l o g i c - l e v e l n - c h a n n e l m o s f e t . u g a t e ( p i n 2 ) c o n n e c t t h i s p i n t o t h e h i g h - s i d e n - c h a n n e l m o s f e t ? s g a t e . t h i s p i n p r o v i d e s g a t e d r i v e f o r t h e h i g h - s i d e m o s f e t . g n d ( p i n 3 ) t h e g n d t e r m i n a l p r o v i d e s r e t u r n p a t h f o r t h e i c ? s b i a s c u r r e n t a n d t h e l o w - s i d e m o s f e t d r i v e r ? s p u l l - l o w c u r r e n t . c o n n e c t t h e p i n t o t h e s y s t e m g r o u n d v i a v e r y l o w i m p e d a n c e l a y o u t o n p c b s . l g a t e ( p i n 4 ) c o n n e c t t h i s p i n t o t h e l o w - s i d e n - c h a n n e l m o s f e t ? s g a t e . t h i s p i n p r o v i d e s g a t e d r i v e f o r t h e l o w - s i d e m o s f e t . n o t e 2 : g u a r a n t e e d b y d e s i g n .
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 5 - m a r . , 2 0 0 8 a p w 7 0 6 5 w w w . a n p e c . c o m . t w 6 f u n c t i o n a l p i n d e s c r i p t i o n ( c o n t . ) v c c ( p i n 5 ) c o n n e c t t h i s p i n t o a 1 2 v s u p p l y v o l t a g e . t h i s p i n p r o v i d e s b i a s s u p p l y f o r t h e c o n t r o l c i r c u i t r y a n d t h e l o w - s i d e m o s f e t d r i v e r . t h e v o l t a g e a t t h i s p i n i s m o n i t o r e d f o r t h e p o w e r - o n r e s e t ( p o r ) p u r p o s e . i t i s r e c o m m e n d e d t h a t a d e c o u p l i n g c a p a c i t o r ( 1 t o 1 0 u f ) b e c o n n e c t e d t o g n d f o r n o i s e d e c o u p l i n g . f b ( p i n 6 ) t h i s p i n i s t h e i n v e r t i n g i n p u t o f t h e i n t e r n a l e r r o r a m p l i f i e r . c o n n e c t t h i s p i n t o t h e o u t p u t ( v o u t ) o f t h e c o n v e r t e r v i a a n e x t e r n a l r e s i s t o r d i v i d e r f o r c l o s e d - l o o p o p e r a t i o n . t h e o u t p u t v o l t a g e s e t b y t h e r e s i s t o r d i v i d e r i s d e t e r m i n e d u s i n g t h e f o l l o w i n g f o r m u l a : w h e r e r 1 i s t h e r e s i s t o r c o n n e c t e d f r o m v o u t t o f b , a n d r 2 i s t h e r e s i s t o r c o n n e c t e d f r o m f b t o g n d . t h e f b p i n i s a l s o m o n i t o r e d f o r u n d e r v o l t a g e e v e n t s . c o m p ( p i n 7 ) t h i s p i n i s t h e o u t p u t o f p w m e r r o r a m p l i f i e r . i t i s u s e d t o s e t t h e c o m p e n s a t i o n c o m p o n e n t s . i n a d d i t i o n , i f t h e p i n i s p u l l e d b e l o w 1 . 2 v , i t w i l l d i s a b l e t h e d e v i c e . p h a s e ( p i n 8 ) t h i s p i n i s t h e r e t u r n p a t h f o r t h e u p p e r g a t e d r i v e r . c o n n e c t t h i s p i n t o t h e u p p e r m o s f e t s o u r c e . t h i s p i n i s a l s o u s e d t o m o n i t o r t h e v o l t a g e d r o p a c r o s s t h e m o s f e t f o r o v e r - c u r r e n t p r o t e c t i o n . t y p i c a l c h a r a c t e r i s t i c s p o w e r o n p o w e r o f f ch1 ch2 ch3 ch1 ch2 ch3 ch4 ch4 ? ? ? ? + = r2 r1 1 0.8 v out vcc=12v, vin =12v vo=1.2v, l=1uh vcc=12v, vin =12v vo=1.2v, l=1uh ch1: vcc (5v/div) ch2: v fb (1v/div) ch3: vo (1v/div) ch4: ug (20/vdiv) time: 10ms/div ch1: vcc (5v/div) ch2: v fb (1v/div) ch3: vo (1v/div) ch4: ug (20/vdiv) time: 10ms/div
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 5 - m a r . , 2 0 0 8 a p w 7 0 6 5 w w w . a n p e c . c o m . t w 7 t y p i c a l c h a r a c t e r i s t i c s ( c o n t . ) e n s h u t d o w n u g a t e r i s i n g u g a t e f a l l i n g ch1 ch2 ch3 ch1 ch2 ch3 ch1 ch2 ch3 ch1 ch2 ch3 ch4 ch4 ch1: ug (20v/div) ch2: lg (5v/div) ch3: phase (10v/div) time: 50ns/div vcc=12v, vin =12v vo=1.2v, l=1uh vcc=12v, vin =12v vo=1.2v, l=1uh vcc=12v, vin =12v vo=1.2v, l=1uh iout =5a vcc=12v, vin =12v vo=1.2v, l=1uh iout =5a ch1: v comp (2v/div) ch2: vo (1v/div) ch3: ug (20v/div) ch4: lg (10vdiv) time: 5ms/div ch1: v comp (2v/div) ch2: vo (1v/div) ch3: ug (20v/div) ch4: lg (10vdiv) time: 20us/div ch1: ug (20v/div) ch2: lg (5v/div) ch3: phase (10v/div) time: 50ns/div
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 5 - m a r . , 2 0 0 8 a p w 7 0 6 5 w w w . a n p e c . c o m . t w 8 0 t y p i c a l c h a r a c t e r i s t i c s ( c o n t . ) l o a d t r a n s i e n t r e s p o n s e u n d e r v o l t a g e p r o t e c t i o n o v e r c u r r e n t p r o t e c t i o n s h o r t t e s t ch1 ch2 ch1 ch2 ch3 ch1 ch2 ch3 ch1 ch2 ch3 ch4 vcc=12v, vin =12v vo=1.2v, l=4.7uh ch4 ch1: il (10a/div) ch2: vo (2v/div) ch3: ug (20v/div) ch4: lg (10v/div) time: 2ms/div ch4 ch1: il (10a/div) ch2: vo (2v/div) ch3: ug (20v/div) ch4: lg (10v/div) time: 5ms/div ch1: il (10a/div) ch2: vo (1v/div) ch3: ug (20v/div) ch4: lg (10v/div) time: 100us/div vcc=12v, vin =12v vo=1.2v, l=1uh ch1: vo (500mv/div,ac) ch2:io (5a/div) time: 1ms/div 1212 0 a 1 0 a vcc=12v, vin =12v,vo=1.2v, l=1uh, l_side: apm2023, rds(on )=17m [ vcc=12v, vin =12v vo=1.2v, l=1uh
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 5 - m a r . , 2 0 0 8 a p w 7 0 6 5 w w w . a n p e c . c o m . t w 9 0 0.5 1 1.5 2 2.5 3 3.5 0 2 4 6 8 10 12 0 0.5 1 1.5 2 2.5 3 0 2 4 6 8 10 12 0.792 0.794 0.796 0.798 0.8 0.802 0.804 -40 -20 0 20 40 60 80 100 120 275 280 285 290 295 300 305 310 -40 -20 0 20 40 60 80 100 120 t y p i c a l c h a r a c t e r i s t i c s ( c o n t . ) s w i t c h i n g f r e q u e n c y v s . j u n c t i o n t e m p e r a t u r e r e f e r e n c e v o l t a g e v s . j u n c t i o n t e m p e r a t u r e j u n c t i o n t e m p e r a t u r e ( c ) switching frequency(khz) j u n c t i o n t e m p e r a t u r e ( c ) reference voltage(v) u g a t e s o u r c e c u r r e n t v s . u g a t e v o l t a g e u g a t e s i n k c u r r e n t v s . u g a t e v o l t a g e u g a t e v o l t a g e ( v ) ugate source current (a) u g a t e v o l t a g e ( v ) ugate sink current (a) vboot=12v vboot=12v v c c = 1 2 v v c c = 1 2 v
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 5 - m a r . , 2 0 0 8 a p w 7 0 6 5 w w w . a n p e c . c o m . t w 1 0 0 0.5 1 1.5 2 2.5 3 3.5 0 2 4 6 8 10 12 0 1 2 3 4 5 6 0 2 4 6 8 10 12 f u n c t i o n d e s c r i p t i o n power-on-reset (por) the power-on-reset (por) function of apw7065 con- tinually monitors the input supply voltage (vcc) and the comp pin. the supply voltage (vcc) must exceed its rising por threshold voltage. the por function initiates soft-start operation after vcc and comp voltages exceed their por thresholds. for operation with a single +12v power source, v i n and vcc are equivalent and the +12v power source must exceed the rising vcc threshold. the por function inhibits operation at disabled status ( v c o m p is less than 1.2v). with both input supplies above their por thresholds, the device initiates a soft-start interval. soft-start the apw7065 has a built-in digital soft-start to con- trol the output voltage rise and limit the current surge during the start-up. in figure 1, when vcc exceeds rising por threshold voltage, it will delay 2048/fosc t y p i c a l c h a r a c t e r i s t i c s ( c o n t . ) l g a t e s o u r c e c u r r e n t v s . l g a t e v o l t a g e l g a t e s i n k c u r r e n t v s . l g a t e v o l t a g e l g a t e v o l t a g e ( v ) lgate source current (a) lgate sink current (a) l g a t e v o l t a g e ( v ) vcc=12v vcc=12v figure 2. shows more detail of the fb voltage ramp. the fb voltage soft-start ramp is formed with many small steps of voltage. the voltage of one step is about 12.5mv in fb, and the period of one step is about 16/ f osc . this method provides a controlled voltage rise ms 4 . 3 1024/f t t t osc 2 3 start soft = = - = - ms 8 . 6 /f 048 2 t t t osc 1 2 delay = = - = seconds and then begin soft start. during soft-start, an internal ramp connected to the one of the positive inputs of the gm amplifier rises up from 0v to 2v to replace the reference voltage (0.8v) until the ramp voltage reaches the reference voltage. t h e s o f t - s t a r t i n t e r v a l i s d e c i d e d b y t h e o s c i l l a t o r f r e q u e n c y ( 3 0 0 k h z ) . t h e f o r m u l a t i o n i s g i v e n b y :
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 5 - m a r . , 2 0 0 8 a p w 7 0 6 5 w w w . a n p e c . c o m . t w 1 1 f u n c t i o n d e s c r i p t i o n ( c o n t . ) soft-start (cont.) f i g u r e 2 . t h e c o n t r o l l e d s t e p p e d f b v o l t a g e voltage(v) fb 12.5mv 16/fosc time o v e r - c u r r e n t p r o t e c t i o n t h e o v e r - c u r r e n t p r o t e c t i o n m o n i t o r s t h e o u t p u t c u r r e n t b y u s i n g t h e v o l t a g e d r o p a c r o s s t h e l o w e r m o s f e t ? s r d s ( o n ) a n d t h i s v o l t a g e d r o p w i l l b e c o m p a r e d w i t h t h e i n t e r n a l 0 . 2 9 v r e f e r e n c e v o l t a g e . i f t h e v o l t a g e d r o p a c r o s s t h e l o w e r m o s f e t ? s r d s ( o n ) i s l a r g e r t h a n 0 . 2 9 v , a n o v e r - c u r r e n t c o n d i t i o n i s d e t e c t e d . t h e t h r e s h o l d o f t h e o v e r c u r r e n t l i m i t i s g i v e n b y : ) on ( ds limit r 29 . 0 i = f o r t h e o v e r - c u r r e n t i s n e v e r o c c u r r e d i n t h e n o r m a l o p e r a t i n g l o a d r a n g e ; t h e v a r i a t i o n o f a l l p a r a m e t e r s i n t h e a b o v e e q u a t i o n s h o u l d b e d e t e r m i n e d . and prevents the large peak current to charge output capacitor. t 1 t 2 voltage(v) time vcc v out t 3 - t h e m o s f e t ? s r d s ( o n ) i s v a r i e d b y t e m p e r a t u r e a n d g a t e t o s o u r c e v o l t a g e , t h e u s e r s h o u l d d e - t e r m i n e t h e m a x i m u m r d s ( o n ) i n m a n u f a c t u r e r ? s d a t a s h e e t . - t h e m i n i m u m v o c s e t s h o u l d b e u s e d i n t h e a b o v e e q u a t i o n . a p p l i c a t i o n i n f o r m a t i o n output voltage selection the output voltage can be programmed with a resistive divider. use 1% or better resistors for the resistive divider is recommended. the fb pin is the inverter input of the error amplifier , and the reference voltage is 0.8v . the output voltage is determined by: f i g u r e 1 . s o f t s t a r t i n t e r v a l - n o t e t h a t t h e i l i m i t i s t h e c u r r e n t f l o w t h r o u g h t h e l o w e r m o s f e t ; i l i m i t m u s t b e g r e a t e r t h a n m a x i - m u m o u t p u t c u r r e n t a d d t h e h a l f o f i n d u c t o r r i p p l e c u r r e n t . s h u t d o w n a n d e n a b l e p u l l i n g t h e c o m p v o l t a g e t o g n d b y a n o p e n d r a i n t r a n s i s t o r , s h o w n i n t y p i c a l a p p l i c a t i o n c i r c u i t , s h u t d o w n t h e a p w 7 0 6 5 p w m c o n t r o l l e r . i n s h u t d o w n m o d e , t h e u g a t e a n d l g a t e t u r n o f f a n d p u l l t o p h a s e a n d g n d r e s p e c t i v e l y . under voltage protection the fb pin is monitored during converter operation by the internal under voltage (uv) comparator. if the fb voltage drops below 50% of the reference voltage (50% of 0.8v = 0.4v), a fault signal is internally generated, and the device turns off both high-side and low-side mosfet and the converter?s output is latched to be floating. ? ? ? ? ? + = gnd out out r r 1 0.8 v where r out is the resistor connected from v out to fb and r gnd is the resistor connected from fb to gnd. d u r i n g s o f t s t a r t
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 5 - m a r . , 2 0 0 8 a p w 7 0 6 5 w w w . a n p e c . c o m . t w 1 2 a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) output inductor selection the inductor value determines the inductor ripple current and affects the load transient response. higher inductor value reduces the inductor?s ripple current and induces lower output ripple voltage. the ripple current and ripple voltage can be approximated by: in out s out in ripple v v l f v v i - = esr i v ripple out = d where f s is the switching frequency of the regulator. although increase of the inductor value reduces the ripple current and voltage, a tradeoff will exist between the inductor?s ripple current and the regulator load transient response time. a smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current. the maximum ripple current occurs at the maximum input voltage. a good starting point is to choose the ripple current to be approximately 30% of the maximum output current. once the inductance value has been chosen, select an inductor that is ca- pable of carrying the required peak current without going into saturation. in some types of inductors, es- pecially core that is made of ferrite, the ripple current will increase abruptly when it saturates. this will re- sult in a larger output ripple voltage. output capacitor selection higher capacitor value and lower esr reduce the output ripple and the load transient drop. therefore, selecting high performance low esr capacitors is intended for switching regulator applications. in some applications, multiple capacitors have to be paralleled to achieve the desired esr value. a small decoupling capacitor in parallel for bypassing the noise is also recommended, and the voltage rating of the output capacitors also must be considered. if tantalum capacitors are used, make sure they are surge tested by the manufactures. if in doubt, consult the capacitors manufacturer. input capacitor selection the input capacitor is chosen based on the voltage rating and the rms current rating. for reliable operation, select the capacitor voltage rating to be at least 1.3 times higher than the maximum input voltage. the maximum rms current rating requirement is approximately i out /2, where i out is the load current. during power up, the input capacitors have to handle large amount of surge current. if tantalum capacitors are used, make sure they are surge tested by the manufactures. if in doubt, consult the capacitors manufacturer. for high frequency decoupling, a ceramic capacitor 1uf can be connected between the drain of upper mosfet and the source of lower mosfet. mosfet selection the selection of the n-channel power mosfets are determined by the r ds(on) , reverse transfer capacitance (c rss ) and maximum output current requirement. there are two components of loss in the mosfets: conduction loss and transition loss. for the upper and lower mosfet, the losses are approximately given by the following: p upper = i out 2 (1+ tc)(r ds(on) )d + (0.5)( i out )(v in )( t sw )f s p lower = i out 2 (1+ tc)(r ds(on) )(1-d) where i out is the load current tc is the temperature dependency of r ds(on) f s is the switching frequency t sw is the switching interval d is the duty cycle note that both mosfets have conduction loss while the upper mosfet include an additional transition loss. the switching internal, t sw , is a function of the reverse transfer capacitance c rss . the (1+tc) term is
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 5 - m a r . , 2 0 0 8 a p w 7 0 6 5 w w w . a n p e c . c o m . t w 1 3 to factor in the temperature dependency of the r ds(on) and can be extracted from the ?r ds(on) vs tempera ture? curve of the power mosfet. pwm compensation the output lc filter of a step down converter introduces a double pole, which contributes with -40db/decade gain slope and 180 degrees phase shift in the control loop. a compensation network among comp, fb and v out should be added. the compensation network is shown in figure 6. the output lc filter consists of the output inductor and output capacitors. the transfer function of the lc filter is given by: a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) mosfet selection (cont.) the poles and zero of this transfer functions are: out lc c l 2 1 f p = out esr c esr 2 1 f p = the f lc is the double poles of the lc filter, and f esr is the zero introduced by the esr of the output capacitor. phase l output c out esr figure 3. the output lc filter f lc f esr -40db/dec -20db/dec frequency(hz) gain (db) the pwm modulator is shown in figure 5. the input is the output of the error amplifier and the output is the phase node. the transfer function of the pwm modulator is given by: figure 5. the pwm modulator output of error amplifier g v osc pwm comparator driver driver phase v in osc the compensation network is shown in figure 6. it provides a close loop transfer function with the highest zero crossover frequency and sufficient phase margin. the transfer function of error amplifier is given by: ? ? ? ? + ? ? ? ? + = = sc3 1 r3 r1// sc2 1 r2 // sc1 1 v v gain out comp amp osc in pwm v v gain d = 1 c esr s c l s c esr s 1 gain out out 2 out lc + + + = figure 4. the lc filter gain and frequency ( ) ? ? ? ? + ? ? ? ? + + ? ? ? ? ? + + ? ? ? ? + + = c3 r3 1 s c2 c1 r2 c2 c1 s s c3 r3 r1 1 s c2 r2 1 s c1 r3 r1 r3 r1
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 5 - m a r . , 2 0 0 8 a p w 7 0 6 5 w w w . a n p e c . c o m . t w 1 4 the poles and zeros of the transfer function are: c2 r2 2 1 f z1 p = ( ) c3 r3 r1 2 1 f z2 + p = ? ? ? ? + p = c2 c1 c2 c1 r2 2 1 f p1 c3 r3 2 1 f p2 p = a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) pwm compensation (cont.) the closed loop gain of the converter can be written as: gain lc x gain pwm x gain amp figure 7. shows the asymptotic plot of the closed loop converter gain, and the following guidelines will help to design the compensation network. using the below guidelines should give a compensation similar to the curve plotted. a stable closed loop has a -20db/ decade slope and a phase margin greater than 45 degree. 1.choose a value for r1, usually between 1k and 5k. 2.select the desired zero crossover frequency f o : (1/5 ~ 1/10) x f s >f o >f esr use the following equation to calculate r2: 3.place the first zero f z1 before the output lc filter double pole frequency f lc . f z1 = 0.75 x f lc 0.75 f r2 2 1 c2 lc p = 4.set the pole at the esr zero frequency f esr : f p1 = f esr calculate the c1 by the equation: 1 f c2 r2 2 c2 c1 esr - p = 5.set the second pole f p2 at the half of the switching frequency and also set the second zero f z2 at the output lc filter double pole f lc . the compensation gain should not exceed the error amplifier open loop gain, check the compensation gain at f p2 with the capabilities of the error amplifier. f p2 = 0.5 x f s f z2 = f lc combine the two equations will get the following component calculations: r1 f f v v r2 lc o in osc d = 1 f 2 f r1 r3 lc s - = s f r3 1 c3 p = f lc frequency(hz) g a i n ( d b ) 20log (r2/r1) 20log (v in / g v osc ) f z1 f z2 f p1 f p2 f esr pwm & filter gain converter gain compensation gain figure 7. converter gain and frequency v ref v out v comp r 1 r 3 c 3 r 2 c 2 c 1 fb figure 6. compensation network calculate the c2 by the equation:
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 5 - m a r . , 2 0 0 8 a p w 7 0 6 5 w w w . a n p e c . c o m . t w 1 5 layout consideration in any high switching frequency converter, a correct layout is important to ensure proper operation of the regulator. with power devices switching at 300khz, the resulting current transient will cause voltage spike across the interconnecting impedance and parasitic circuit elements. as an example, consider the turn-off transition of the pwm mosfet. before turn-off, the mosfet is carrying the full load current. during turn-off, current stops flowing in the mosfet and is free-wheeling by the lower mosfet and parasitic diode. any parasitic inductance of the circuit generates a large voltage spike during the switching interval. in general, using short and wide printed circuit traces should minimize interconnecting impedances and the magnitude of voltage spike. and signal and power grounds are to be kept separate till combined using ground plane construction or single point grounding. figure 8. illustrates the layout, with bold lines indicating high current paths; these traces must be short and wide. components along the bold lines should be placed lose together. below is a checklist for your layout: - keep the switching nodes (ugate, lgate and phase) away from sensitive small signal nodes since these nodes are fast moving signals. therefore, keep traces to these nodes as short as possible. - the traces from the gate drivers to the mosfets (ug, lg) should be short and wide. - place the source of the high-side mosfet and the drain of the low-side mosfet as close as possible. minimizing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node. - decoupling capacitor, compensation component, a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) figure 8.layout guidelines the resistor dividers, and boot capacitors should be close their pins. (for example, place the decoupling ceramic capacitor near the drain of the high-side mosfet as close as possible. the bulk capacitors are also placed near the drain). - the input capacitor should be near the drain of the upper mosfet; the output capacitor should be near the loads. the input capacitor gnd should be close to the output capacitor gnd and the lower mosfet gnd. - the drain of the mosfets (v in and phase nodes) should be a large plane for heat sinking. vcc boot phase ugate lgate v in v out l o a d apw7065
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 5 - m a r . , 2 0 0 8 a p w 7 0 6 5 w w w . a n p e c . c o m . t w 1 6 p a c k a g e i n f o r m a t i o n s o p - 8 s y m b o l min. max. 1.75 0.10 0.17 0.25 0.25 a a1 c d e e1 e h l millimeters b 0.31 0.51 sop-8 0.25 0.50 0.40 1.27 min. max. inches 0.069 0.004 0.012 0.020 0.007 0.010 0.010 0.020 0.016 0.050 0 0.010 1.27 bsc 0.050 bsc a2 1.25 0.049 0 8 0 8 d e e e 1 see view a c b h x 4 5 a a 1 a 2 l view a 0 . 2 5 seating plane gauge plane note: 1. follow jedec ms-012 aa. 2. dimension ? d ? does not include mold flash, protrusions or gate burrs. mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. dimension ? e ? does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 10 mil per side. 3.80 5.80 4.80 4.00 6.20 5.00 0.189 0.197 0.228 0.244 0.150 0.157
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 5 - m a r . , 2 0 0 8 a p w 7 0 6 5 w w w . a n p e c . c o m . t w 1 7 application a h t1 c d d w e1 f 330.0 ? 2.00 50 min. 12.4+2.00 - 0.00 13.0+0.50 - 0.20 1.5 min. 20.2 min. 12.0 ? 0.30 1.75 ? 0.10 5.5 ? 0.05 p 0 p1 p 2 d 0 d1 t a 0 b 0 k 0 sop - 8 4.0 ? 0.10 8.0 ? 0.10 2.0 ? 0.05 1.5+0.10 - 0.00 1.5 min. 0.6+0.00 - 0.40 6.40 ? 0.20 5.20 ? 0.20 2.10 ? 0.20 c a r r i e r t a p e & r e e l d i m e n s i o n s d e v i c e s p e r u n i t ( m m ) package type unit quantity sop - 8 tape & reel 2500 h t1 a d a e 1 a b w f t p0 od0 b a0 p2 k0 b 0 section b-b section a-a od1 p1
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 5 - m a r . , 2 0 0 8 a p w 7 0 6 5 w w w . a n p e c . c o m . t w 1 8 r e f l o w c o n d i t i o n ( i r / c o n v e c t i o n o r v p r r e f l o w ) c l a s s i f i c a t i o n r e f l o w p r o f i l e s profile feature sn - pb eutectic assembly pb - free assembly average ramp - up rate (t l to t p ) 3 c/second max. 3 c/second max. preheat - temperature min (tsmin) - temperature max (tsmax) - time (min to max) (ts) 100 c 150 c 60 - 120 seconds 150 c 200 c 60 - 180 seconds time maintained above: - temperature (t l ) - time (t l ) 183 c 60 - 150 seconds 217 c 60 - 150 seconds peak /classification temperature (tp) see table 1 see table 2 time within 5 c of actual peak temperature (tp) 10 - 30 seconds 20 - 40 seconds ramp - down rate 6 c/sec ond max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note: all temperatures refer to topside of the package. measured on the body surface. test item method description solderability mil - std - 883d - 2003 245 c, 5 sec holt mil - std - 883d - 1005.7 1000 hrs bias @125 c pct jesd - 22 - b, a102 168 hrs, 100 % rh, 121 c tst mil - std - 883d - 1011.9 - 65 c~150 c, 200 cycles esd mil - std - 883d - 3015.7 vhbm > 2kv, vmm > 200v latch - up jesd 78 10ms, 1 tr > 100ma r e l i a b i l i t y t e s t p r o g r a m t 25 c to peak tp ramp-up t l ramp-down ts preheat tsmax tsmin t l t p 25 t e m p e r a t u r e time critical zone t l to t p
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 5 - m a r . , 2 0 0 8 a p w 7 0 6 5 w w w . a n p e c . c o m . t w 1 9 table 2. pb - free process ? package classification reflow temperatures package thickness volume mm 3 <350 volume mm 3 350 - 2000 volume mm 3 >2000 <1.6 mm 260 +0 c* 260 +0 c* 260 +0 c* 1.6 mm ? 2.5 mm 260 +0 c* 250 +0 c* 245 +0 c* 3 2.5 mm 250 +0 c* 245 +0 c* 245 +0 c* *tolerance: the device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means peak reflow temperature +0 c. for example 260 c+0 c) at the rated msl level. table 1. snpb eutectic process ? package peak reflow temperature s package thickness volume mm 3 <350 volume mm 3 3 350 <2.5 mm 240 +0/ - 5 c 225 +0/ - 5 c 3 2.5 mm 225 +0/ - 5 c 225 +0/ - 5 c c l a s s i f i c a t i o n r e f l o w p r o f i l e s ( c o n t . ) c u s t o m e r s e r v i c e a n p e c e l e c t r o n i c s c o r p . head office : no.6, dusing 1st road, sbip, hsin-chu, taiwan tel : 886-3-5642000 fax : 886-3-5642050 t a i p e i b r a n c h : 2 f , n o . 1 1 , l a n e 2 1 8 , s e c 2 j h o n g s i n g r d . , s i n d i a n c i t y , t a i p e i c o u n t y 2 3 1 4 6 , t a i w a n t e l : 8 8 6 - 2 - 2 9 1 0 - 3 8 3 8 f a x : 8 8 6 - 2 - 2 9 1 7 - 3 8 3 8

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