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exar corporation, 48720 kato road, fremont, ca 94538 (510) 668-7000 fax (510) 668-7017 rev. p1.00 preliminary xrd64l44 dual 10-bit 50msps cmos adc march 2000-1 features 10-bit resolution two monolithic complete 10-bit adcs 50 msps conversion rate on-chip track-and-hold on-chip voltage reference low 5 pf input capacitance ttl/cmos outputs tri-state output buffers single +3v or +5v power supply operation low power dissipation: 250mw-typ @ 3.0v -40 c to +85 c operation temperature range applications medical ultrasound imaging i & q modems benefits reduction of components reduction of system cost high performance @ low power dissipation long term time and temperature stability general description the xrd64l44 is two 10-bit, monolithic, 50 msps adcs. manufactured using a standard cmos pro- cess, the xrd64l44 offers low power, low cost and excellent performance. the on-chip track-and-hold amplifier(t/h) and voltage reference (vref) eliminate the need for external active components, requiring only an external adc conversion clock for the application. the xrd64l44 analog input can be driven with ease due to the high input impedance of rin = 25kohms and cin = 5pf. the design architecture uses 17 time- interleaved 10- bit sar adcs in each converter to achieve high conversion rate of 50 msps minimum. in order to insure and maintain accurate 10-bit operation with respect to time and temperature, xrd64l44 incorpo- rates an auto-calibration circuit which continuously adjusts and matches the offset and linearity of each adc. this auto-calibration circuit is transparent to the user after the initial 3.4ms calibration (168,000 initial clock cycles). the power dissipation is only 250mw at 50 msps and 225mw at 40 msps with +3.0v power supply. the digital output data is straight binary format, and the tri-state disable function is provided for common bus interface. the xrd64l44 internal reference provides cost sav- ings and simplifies the design/development. the out- put voltage of the internal reference is set by two external resistors. the internal reference can be dis- abled if an external reference is used for a power savings of 50mw. ordering information part number package type temperature range XRD64L44AIV 64-lead tqfp -40c to +85c
xrd64l44 2 rev. p1.00 preliminary figure 1. xrd64l44 simplified block diagram db9 - db0, otrb da9 - da0, otra control logic bandgap + - vbg vfbk vrhf vrlf vinb+ vinb- tri_b a/d 1b a/d 17b adc b 10 bit a/d's 11 adc a a/d 1a a/d 17a 10 bit a/d's 11 clamp synco tri_a vina+ vina- k pd ckin diff vclmpa vclmpb + - vcmo
xrd64l44 3 rev. p1.00 preliminary vbg vfbk vrhf vrhf vrlf vrlf 1 2345678910111213141516 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 52 51 53 54 55 56 57 58 59 60 61 62 63 64 vclmpa dgnd dgnd pd dvdd tri_b diff clamp tri_a ckin synco db0 db1 db2 dognd dovdd dgnd db4 db9 db8 db7 db5 db6 db3 otrb da0 da1 da2 da3 da4 dovdd dognd dvdd dgnd da5 da6 da7 da8 da9 otra vcmo dgnd agnd avdd agnd agnd vinb- vinb+ agnd vina+ vina- agnd avdd avdd agnd agnd xrd64l44 64qfp vclmpb agnd
xrd64l44 4 rev. p1.00 preliminary pin description pin # symbol description 1 vbg bandgap voltage output 2 vfbk analog reference feedback 3 vrhf top voltage reference force 4 vrhf top voltage reference force 5 vrlf bottom voltage reference force 6 vrlf bottom voltage reference force 7 vclmpa analog input clamp a 8 vclmpb analog input clamp b 9 agnd analog ground 10 dgnd digital ground 11 dgnd digital ground 12 pd power down 13 dvdd digital supply voltage 14 tri_b tri-state for the b channel outputs 15 diff differential / single-ended input mode 16 clamp digital clamp control 17 tri_a tri-state for the a channel outputs 18 ckin clock input 19 synco data valid output 20 db0 digital output bit 0 (lsb) adc b 21 db1 digital output bit 1 adc b 22 db2 digital output bit 2 adc b 23 dognd digital output ground 24 dovdd digital output supply voltage 25 dgnd digital ground 26 db3 digital output bit 3 adc b 27 db4 digital output bit 4 adc b 28 db5 digital output bit 5 adc b 29 db6 digital output bit 6 adc b 30 db7 digital output bit 7 adc b 31 db8 digital output bit 8 adc b 32 db9 digital output bit 9 (msb) adc b 33 otrb over range digital output bit adc b 34 da0 digital output bit 0 (lsb) adc a 35 da1 digital output bit 1 adc a 36 da2 digital output bit 2 adc a 37 da3 digital output bit 3 adc a 38 da4 digital output bit 4 adc a 39 dovdd digital output supply voltage 40 dognd digital output ground 41 dvdd digital supply voltage
xrd64l44 5 rev. p1.00 preliminary pin # symbol description 42 dgnd digital ground 43 da5 digital output bit 5 adc a 44 da6 digital output bit 6 adc a 45 da7 digital output bit 7 adc a 46 da8 digital output bit 8 adc a 47 da9 digital output bit 9 adc a 48 otra over range digital output bit adc a 49 vcmo differential common mode voltage output 50 dgnd digital ground 51 agnd analog ground 52 avdd analog supply voltage 53 agnd analog ground 54 agnd analog ground 55 vinb- analog input b(-) 56 vinb+ analog input b(+) 57 agnd analog ground 58 vina+ analog input a(+) 59 vina- analog input a(-) 60 agnd analog ground 61 avdd analog supply voltage 62 avdd analog supply voltage 63 agnd analog ground 64 agnd analog ground pin description (cont'd)
xrd64l44 6 rev. p1.00 preliminary electrical characteristics table (cont'd) test conditions (unless otherwise specified) t a = 25 c av dd = dv dd = +3.3v, vin = gnd to +2.5v, v rlf = gnd, v rhf = +2.5v and fs = 50 msps, 50% duty cycle, differential input mode symbol parameter min. typ. max. unit conditions/comments dc accuracy dnl differential non-linearity -1.0 +/-0.4 1.0 lsb inl integral non-linearity +/-1.1 lsb mon monotonicity no missing codes guaranteed by test fse full scale error +10 mv f.s. = (vrhf - vrlf)x0.97 zse zero scale error 5 mv single ended mode analog input invr input voltage range 0 vrhfx0.97 v vrlf grounded inres input resistance 20 kohms incap input capacitance 5 pf inbw input bandwidth 400 mhz -1db small signal reference input, internal bandgap reference and reference buffer rlad ladder resistance 100 125 150 ohms rladtco ladder resistance tempco +0.8 ohms/c vbg bandgap output voltage range 1.25 v vbgtc bandgap reference tempco 30 ppm/c vrlf 0.0 2.0 v vrhf vrlf+1.0 avdd-0.6 v internal reference buffer vrhf external reference vrlf+1.0 avdd v external vrhf psrr internal reference buffer 6 mv/v conversion and timing characteristics (c l = 10pf) maxcon maximum conversion rate 50 60 msps mincon minimum conversion rate 100 ksps pdel pipeline delay(latency) 17 clk clock cycles digital data delay t ad aperture delay time 4 ns apjt aperture jitter time 12 ps peak-to peak t r digital output rise time 3 ns t f digital output fall time 3 ns t pd output data propagation delay 6 14 ns guaranteed by design t den output data enable delay 6 14 ns guaranteed by design t dis output data disable delay 5 ns clkdc clock duty cycle 40 50 60 % guaranteed by design
xrd64l44 7 rev. p1.00 preliminary dynamic performance fs = 40mhz snr signal-to-noise ratio not including harmonics fin = 1.0 mhz 60 db fin = 4.0 mhz 60 db sinad signal-to noise and distortion fin = 1.0 mhz 58 db fin = 4.0 mhz 58 db fin = 12.5 mhz 57 db enob effective number of bits fin = 1.0 mhz 9.5 bit fin = 4.0 mhz 9.5 bit fin = 12.5 mhz 9.3 bit sfdr spurious free dynamic range sfdr fin = 4.0 mhz 70 db crosstalk fin = 4.0 mhz 75 db electrical characteristics table (cont'd) test conditions (unless otherwise specified) t a = 25 c av dd = dv dd = +3.3v, vin = gnd to +2.5v, v rlf = gnd, v rhf = +2.5v, 50% duty cycle, differential input mode symbol parameter min. typ. max. unit conditions/comments
xrd64l44 8 rev. p1.00 preliminary dynamic performance fs = 50mhz snr signal-to-noise ratio not including harmonics fin = 1.0 mhz 56 58 db fin = 4.0 mhz 56 58 db sinad signal-to noise and distortion fin = 1.0 mhz 55 57 db fin = 4.0 mhz 54 57 db fin = 12.5 mhz 54 56 db enob effective number of bits fin = 1.0 mhz 9.0 9.3 bit fin = 4.0 mhz 9.0 9.3 bit fin = 12.5 mhz 8.8 9.1 bit sfdr spurious free dynamic range sfdr fin = 4.0 mhz 70 db crosstalk fin = 4.0 mhz 75 db electrical characteristics table (cont'd) test conditions (unless otherwise specified) t a = 25 c av dd = dv dd = +3.3v, vin = gnd to +2.5v, v rlf = gnd, v rhf = +2.5v, 50% duty cycle, differential input mode symbol parameter min. typ. max. unit conditions/comments
xrd64l44 9 rev. p1.00 preliminary digital outputs (cl = 10 pf) dohv digital output high voltage dvdd -0.4v dvdd-0.3v v ioh = 1.5 ma dolv digital output low voltage 0.3 0.4 v iol = 1.5 ma ioz high-z leakage -20 0.2 20 na power supplies `av dd analog power supply voltage 3.0 3.3 3.6 v dv dd digital power supply range av dd vdv dd = av dd fs = 40 mhz, avdd = dvdd = 3.0v, cl = 10pf, fin = 10mhz aidd analog supply current 37 ma didd digital supply current 15 ma doidd output driver current 15 ma vrhf top voltage ref force current 8 ma vrhf/125, vrhf = 1.0v pdiss power dissipation 225 mw fs = 50 mhz, avdd = dvdd = 3.0v, cl = 10pf, fin = 10mhz aidd analog supply current 38 ma didd digital supply current 19 ma doidd output driver current 18 ma vrhf top voltage ref force current 8 ma vrhf/125, vrhf = 1.0v pdiss power dissipation 250 mw digital inputs dvinh digital input high voltage 2.5 v dvinl digital input low voltage 0.5 v diinh digital input high current (the diff input has an internal pull-up resistor, tri_a and tri_b have internal pull-down resistors ckin clock input -5.0 0.05 5.0 na diff differential/single-ended input -1.0 -0.25 1.0 ua tri_a/tri_b a/b channel tri-state -125.0 -90.0 -50.0 ua diinl digital input low current (the diff input has an internal pull-up resistor, tri_a and tri_b have internal pull-down resistors ckin clock input -5.0 0.05 5.0 na diff differential/single-ended input 50.0 90.0 125.0 ua tri_a/tri_b a/b channel tri-state -1.0 0.25 1.0 ua dinc digital input capacitance 5 8 pf electrical characteristics table (cont'd) test conditions (unless otherwise specified) t a = 25 c av dd = dv dd = +3.3v, vin = gnd to +2.5v, v rlf = gnd, v rhf = +2.5v and fs = 50 msps, 50% duty cycle, differential input mode symbol parameter min. typ. max. unit conditions/comments
xrd64l44 10 rev. p1.00 preliminary notes: 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation at or above this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. 2 any input pin which can see a value outside the absolute maximum ratings should be protected by schottky diode clamps (hp5082-2835) from input pin to the supplies. all inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100ma for less than 100ms. 3v dd refers to av dd and dv dd . gnd refers to agnd and dgnd absolute maximum ratings (t a = +25 c unless otherwise noted) 1, 2, 3 v dd to gnd +7.0v v rt & v rb v dd +0.5 to gnd -0.5v v in v dd +0.5 to gnd -0.5v all inputs v dd +0.5 to gnd -0.5v all outputs v dd +0.5 to gnd -0.5v storage temperature -65 c to 150 c lead temperature (soldering 10 seconds) 300 c maximum junction temperature 150 c package power dissipation ratings (t a = +70 c) ssop q ja = 89.4 c/w esd 2000v min
xrd64l44 11 rev. p1.00 preliminary -120.00 -100.00 -80.00 -60.00 -40.00 -20.00 0.00 dc 4.0 8.1 12.1 16.1 frequenc y in mhz relative power in db 50 55 60 65 2.8v 3.0v 3.2v 3.4v 3.6v sinad in db 2.90mhz 6.90mhz 9.90mhz figure 2 - sinad vs. fin and vdd @fc = 40.0mhz, differential input mode 40.00 45.00 50.00 55.00 60.00 3.0v 3.2v 3.4v 3.6v sinad in db fclk = 50.0mhz fclk = 53.3mhz fclk = 56.7mhz fclk = 60.0mhz figure 3 - sinad vs. fclock and vdd differen- tial input mode figure 4 - fft spectrum @fclock = 40.0mhz, fin = 4.0mhz, differential input mode -120.00 -100.00 -80.00 -60.00 -40.00 -20.00 0.00 dc 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 frequency in mhz relative power in db figure 5 - fft spectrum @fclock = 40.0mhz, fin = 10.0mhz, differential input mode 40 45 50 55 60 2.8v 3.0v 3.2v 3.4v 3.6v sinad in db 2.90mhz 6.90mhz 9.90mhz figure 6 - sinad vs. fin and vdd @fc = 40.0mhz, single-ended input mode -120.00 -100.00 -80.00 -60.00 -40.00 -20.00 0.00 dc 4.0 8.1 12.1 16.1 frequency in mhz relative power in db figure 7 - fft spectrum @fclock = 40.0mhz, fin = 4.0mhz, single-ended input mode single tone 8192 point fft sfdr -72.66 sinad -57.97 single tone 8192 point fft sfdr -69.77 sinad -57.11 single tone 8192 point fft sfdr -62.57 sinad -55.25
xrd64l44 12 rev. p1.00 preliminary figure 8 - fft spectrum @fclock = 40.0mhz, fin = 10.0mhz, single-ended input mode 45.00 50.00 55.00 60.00 2.80v 3.00v 3.20v 3.40v 3.60v sinad in d b 2.90mhz 6.90mhz 9.90mhz figure 9 - sinad vs. fin and vdd @fc = 50.0mhz, differential input mode figure 10 - fft spectrum @fclock = 50.0mhz, fin = 4.0mhz, differential input mode -120.00 -100.00 -80.00 -60.00 -40.00 -20.00 0.00 dc 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 frequency in mhz relative power in db figure 11 - sinad @fclock = 50.0mhz, fin = 12.5mhz, differential input mode figure 12 - fft spectrum @fclock = 50.0mhz, fin = 24.1mhz, differential input mode 40.00 45.00 50.00 55.00 60.00 2.80v 3.00v 3.20v 3.40v 3.60v sinad in d b 2.90mhz 6.90mhz 9.90mhz figure 13 - sinad vs. fin and vdd @fc = 50.0mhz, single-ended input mode -120.00 -100.00 -80.00 -60.00 -40.00 -20.00 0.00 dc 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 frequency in mhz relative power in db -120.00 -100.00 -80.00 -60.00 -40.00 -20.00 0.00 dc 4.0 8.0 12.0 16.0 20.0 24.1 frequency in mhz relative power in db -120.00 -100.00 -80.00 -60.00 -40.00 -20.00 0.00 dc 1.5 3.0 4.5 6.0 7.5 9.0 10.5 12.1 13.6 15.1 16.6 18.1 19.6 21.1 22.6 24.1 frequenc y in mhz relative power in db single tone 8192 point fft sfdr -66.93 sinad -56.70 single tone 8192 point fft sfdr -60.95 sinad -54.48 single tone 8192 point fft sfdr -66.93 sinad -56.70 single tone 8192 point fft sfdr -64.15 sinad -50.91
xrd64l44 13 rev. p1.00 preliminary -120.00 -100.00 -80.00 -60.00 -40.00 -20.00 0.00 dc 4.0 8.0 12.0 16.0 20.0 24.0 frequency in mhz relative power in db figure 14 - sinad @fclock = 50.0mhz, fin = 4.0mhz, single-ended input mode -120.00 -100.00 -80.00 -60.00 -40.00 -20.00 0.00 dc 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 frequency in mhz relative power in d b figure 15 - fft spectrum @fclock = 50.0mhz, fin = 12.5mhz, single-ended input mode -120.00 -100.00 -80.00 -60.00 -40.00 -20.00 0.00 dc 3.0 6.0 9.0 12.1 15.1 18.1 21.1 24.1 frequency in mhz relative power in db figure 16 - sinad @fclock = 50.0mhz, fin = 24.1mhz, single-ended input mode single tone 8192 point fft sfdr -53.43 sinad -47.36 single tone 8192 point fft sfdr -54.01 sinad -51.75 single tone 8192 point fft sfdr -64.09 sinad -54.21
xrd64l44 14 rev. p1.00 preliminary notes
xrd64l44 15 rev. p1.00 preliminary notice exar corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration purposes and may vary depending upon a users specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for in accuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 1999 exar corporation datasheet february 1999 reproduction, in part or whole, without the prior written consent of exar corporation is prohibited.

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