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september 2003 1/60 VV6501 vga cmos color image sensor ? features n 640 x 480 vga resolution n 1/4 inch format lens compatible n on board 10 bit adc n on board voltage regulators n automatic dark calibration n on board audio amplifier n i 2 c interface n low power suspend mode n 4 or 5 wire nibble output n framegrabber signals: qck and fst description this image sensor based on stmicroelectronics cmos technology is bayer colorised. the sensor provides a raw digital video output which also contains embedded codes to facilitate external synchronisation. the sensor interfaces to a range of stmicroelectronics companion processors for applications such as usb webcams and digital stills cameras. an i 2 c interface allows an external processor to configure the device and control exposure and gain settings. a low-power pin-driven suspend mode simplifies usb-based designs. on board voltage regulators operate from a 5v usb supply and generate 3v3 and 1v8 power supplies for external processors. technical specifications ordering details image size 640 x 480 (vga) pixel size 5.6 m x 5.6 m array size 3.6 mm x 2.7 mm analogue gain x1 to x16 sensitivity (typ.) 2.05 v/lux-sec maximum frame rate 30 fps (with 24mhz clock) supply voltage 5v (usb) 3v3 direct drive power consumption active (30fps) < 30 ma suspend < 100 a operating temperature 0 o c - 40 o c package type 36 pin clcc part number description VV6501c001 36pin clcc, colorised sensor
VV6501 2/60 table of contents chapter 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1 sensor overview ............................................................................................................ ....... 4 1.2 typical application ........................................................................................................ ........ 5 chapter 2 device pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 2.1 pin position ............................................................................................................... ............ 6 2.2 pin description ............................................................................................................ .......... 7 chapter 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.1 video block ................................................................................................................ ........... 9 3.2 audio block ................................................................................................................ ......... 22 3.3 power management ........................................................................................................... 24 3.4 device operating modes .................................................................................................... 2 6 chapter 4 serial control bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 4.1 general description ........................................................................................................ .... 28 4.2 serial communication protocol ........................................................................................... 28 4.3 types of messages .......................................................................................................... .. 30 chapter 5 i2c registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.1 register map ............................................................................................................... ....... 32 5.2 register description ....................................................................................................... .... 34 chapter 6 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 6.1 absolute maximum ratings ................................................................................................. 43 6.2 operating conditions ....................................................................................................... ... 43 6.3 thermal data ............................................................................................................... ....... 43 6.4 dc electrical characteristics .............................................................................................. .44 6.5 ac electrical characteristics .............................................................................................. .47 chapter 7 optical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 7.1 optical characterisation methods ....................................................................................... 48 7.2 optical characterisation results .......................................................................................... 4 9 7.3 spectral response .......................................................................................................... .... 50 7.4 blooming ................................................................................................................... ......... 50
3/60 VV6501 chapter 8 defect categorisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 8.1 introduction ............................................................................................................... ......... 51 8.2 pixel defects .............................................................................................................. ......... 51 8.3 sensor array area definition ............................................................................................... 52 8.4 pixel fault definitions .................................................................................................... ...... 53 8.5 summary pass criteria ...................................................................................................... .54 8.6 physical aberrations ....................................................................................................... .... 55 chapter 9 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 chapter 10 design-in information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 10.1 basic support circuit ..................................................................................................... ...... 58 10.2 transistor choice ......................................................................................................... ....... 58 10.3 pin 1 and image orientation ............................................................................................... 58 chapter 11 evaluation kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
overview VV6501 4/60 1overview 1.1 sensor overview the VV6501 vga image sensor produces raw digital video data at up to 30 frames per second. the image data is digitised using an internal 10-bit column adc. the resulting 10-bit output data includes embedded codes for synchronization. the data is formatted as 5-bit nibbles. a separate data qualification clock (qck) and frame start (fst) signals are also provided. the sensor is fully configurable using an i 2 c interface. the sensor also contains an audio low-noise preamplifier for use with an external microphone. the sensor is optimized for usb applications and contains voltage regulators which drive external pass transistors to produce 3v3 and 1v8 supplies. these supplies may be used by external processors. a dedicated suspend input pin may be used to force the device into a low power state while maintaining the device configuration. a power-on reset signal (porb) may be used to reset external devices. figure 1: VV6501 block diagram scl sda aud3v3 audoutp micin micbias audoutn audref audvss audio amplifier clkin gnd fst qclk d0 d1 vdd gnd d2 d3 d4 vdd suspend test porb gnds vbase3v3 vdig3v3 vbase1v8 vdig1v8 1v8 digital pdvreg1v8 nc nc video3v3 videovss vbg video regulator audio regulator regulator regulator 3v3 digital v5v analog aud3v3 video3v3 digital interface video block 10-bit video data
5/60 VV6501 overview 1.2 typical application 1.2.1 usb webcam this sensor may be used in conjunction with the stmicroelectronics stv0676 co-processor to produce a low cost usb webcam. in this application the co-processor supplies the sensor clock and uses the embedded control sequences to synchronise with the frame and line level timings. it then performs the colour processing on the raw image data from the sensor before supplying the final image data to the host using the usb interface. the voltage regulators on-board the sensor are used to control external bipolar transistors to derive the supplies for the sensor and co-processor from the 5v usb supply. this approach eliminates the requirement for more costly external voltage regulation circuitry. figure 2 below illustrates a typical system using VV6501. the input usb supply is 5 v. the 3v3 digital regulator generates the supply for the sensor digital part and the co-processor ios. the 1v8 regulator generates the core supply for the co-processor. figure 2: usb camera system using stv0676 usb hub v5v usb - data i 2 c stv0676 gnd microphone video d[4:0] usb-power VV6501 3v3 usb webcam 1v8 suspend usb connector usb interface power management digital interface vga pixel array audio amplifier co-processor video processing
device pinout VV6501 6/60 2 device pinout 2.1 pin position figure 3: pin position 6 7 8 9 10 11 12 13 14 gnds porb suspend gnd vdd gnd sda scl clkin 15 16 17 18 19 20 21 22 23 fst qclk d0 d1 vdd gnd d2 d3 d4 24 25 26 27 28 29 30 31 32 nc nc aud3v3 audoutp micin micbias audoutn audref audvss 33 34 35 36 1 2 3 4 5 pdvreg1v8 vdig1v8 vbase1v8 vdig3v3 vbase3v3 v5v vbg videovss video3v3
7/60 VV6501 device pinout 2.2 pin description table 1: pin description pin number pin name pin type description digital regulators 1 vbase3v3 pwr 3.3 v digital regulator (connect to external pnp base) 2 vdig3v3 pwr 3.3 v digital regulator (connect to external pnp collector) 3 vbase1v8 pwr 1.8 v digital regulator (connect to external pnp base) 4 vdig1v8 pwr 1.8 v digital regulator (connect to external pnp collector) digital inputs/outputs 5 pdvreg1v8 pwr 1.8 v reg power down signal 1 - regulator powered down 0 - regulator powered up 6 gnds pwr connect to gnd 7 porb o power on reset signal (active low) 8 suspend i sensor suspend input signal (active high) with schmitt buffer 9 test i input pin with schmitt buffer. connect to gnd 10 vdd pwr digital io supply 3.3 v 11 gnd pwr digital ground 12 sda io bidirectional i 2 c pin 13 scl io bidirectional i 2 c pin. i 2 c clock line 14 clkin i input clock pin with schmitt buffer 15 fst o fst signal (active high). 2 ma output pad 16 qclk o sensor data qualifying clock. 4 ma output pad 17 d0 o d0 signal (data bus, bit 0). 4 ma output pad 18 d1 o d1 signal (data bus, bit 1). 4 ma output pad 19 vdd pwr digital io supply 3.3v 20 gnd pwr digital io/core source ground 21 d2 o d2 signal (data bus, bit 2). 4 ma output pad 22 d3 o d3 signal (data bus, bit 3). 4 ma output pad 23 d4 o d4 signal (data bus, bit 4). 4 ma output pad
device pinout VV6501 8/60 audio amplifier 24 audvss pwr audio ground 25 audref pwr audio reference voltage (requires external decoupling capacitor) 26 audoutn o audio negative output 27 micbias pwr audio microphone bias voltage 28 micin i audio microphone input signal 29 audoutp o audio positive output 30 aud3v3 pwr 3.3 v audio analogue supply (requires external decoupling capacitor) video regulator 33 video3v3 pwr analogue video 3.3 v 34 videovss pwr analogue video ground 35 vbg pwr 5 v bandgap voltage (requires external decoupling capacitor) 36 v5v pwr usb power supply (4 - 5.5 v) not connected 31,32 - - not connected table 1: pin description pin number pin name pin type description
9/60 VV6501 functional description 3 functional description the first three sections of this chapter detail the main blocks in the device: l video l audio l power management the final section describes the device level operating modes including suspend. 3.1 video block 3.1.1 overview the analog core of the video block contains a vga sized pixel array. the integration time and access for a row of pixels is controlled by the y-address block. the row of pixels being read is converted using a 10-bit in-column adc. the digitised data is readout into the digital block for formatting. the 10-b data is transferred to the co-processor over a 5-wire digital bus as two 5-b nibbles. the exposure or integration time for the pixel array is calculated by the external co-processor and delivered to the sensor using the i2c interface. data synchronization can be achieved either by using the embedded codes within the data stream or by making use of the dedicated fst and qck pins. figure 4: overview of video block column adc x-address sram line store vga photodiode array y address readout structure digital logic timing & control 10-b image data 10-b image data d[4:0] coprocessor i 2 c fst, qck
functional description VV6501 10/60 3.1.2 imaging array the physical pixel array is 656 x 496 pixels. the pixel size is 5.6 m m by 5.6 m m. the additional border columns and rows are included to enable complete color reconstruction of the final 640 by 480 sized array. microlens microlenses placed above the visible pixels improve light gathering capability hence improving sensitivity. 3.1.3 sensor data overview sensor data is output on a 5-wire bus. as well as pixel data there are embedded codes at the start and end of every video line. these codes are always preceded by an escape sequence which is guaranteed not to appear in the video data itself. figure 5: pixel array table 2: video data values read-out order progressive scan (non-interlaced) form of encoding uniformly quantized, pcm, 8/10 bits per sample 8 bit mode 10 bit mode video pixel range 1 to 254 1 to 1022 black level value 16 64 escape sequence ff, ff, 00 3fc, 3fc, 00 640 pixels 644 pixels 480 pixels 2 border rows 2 border rows 2 border columns 2 border columns visible array (640 x 480) 5.6 m x 5.6 m pixel (3.5840 mm x 2.6880 mm) 484 pixels
11/60 VV6501 functional description 3.1.4 digital data bus: d[4:0] sensor data may be either 8 or 10 bits per pixel and is transmitted as follows: l 10-bit data: a pair of 5-bit nibbles, most significant nibble first, on 5 wires. l 8-bit data: a pair of 4-bit nibbles, most significant nibble first, on 4 wires. in 5-wire mode, the embedded control codes occupy only the most significant 8-bits, the least significant 2-bits are always zero. output tri-state using sif register 23 bit[5] can be used to tri-state all 5 data lines, qck and fst. output pad drive strength the data and qck output pads are tri-stateable with 4 ma drive. 3.1.5 data qualification clock (qck) a data qualification clock (qck) is available and complements the embedded control sequences. this clock runs continuously when enabled and consists of: l fast qck : the falling edge of the clock qualifies every 5 or 4-bit data blocks that constitute a pixel value. l slow qck : the rising edge qualifies 1st, 3rd, 5th, etc. blocks of data that constitute a pixel value while the falling edge qualifies the 2nd, 4th, 6th etc. blocks of data. for example in 4-wire mode, the rising edge of the clock qualifies the most significant nibbles while the falling edge of the clock qualifies the least significant nibbles. figure 6: digital data output modes figure 7: qck modes d 7 ,d 6 ,d 5 ,d 4 d 3 ,d 2 ,d 1 ,d 0 d 3 ,d 2 ,d 1 ,d 0 d 7 ,d 6 ,d 5 ,d 4 10-bit pixel data d 9 ,d 8 ,d 7 ,d 6 ,d 5 d 4 ,d 3 ,d 2 ,d 1 ,d 0 d 4 ,d 3 ,d 2 ,d 1 ,d 0 d 9 ,d 8 ,d 7 ,d 6 ,d 5 8-bit pixel data 5-wire output mode 4-wire output mode qck (slow) qck (fast) d[4:0] < msb > < lsb > < msb > < lsb > < msb > < lsb >
functional description VV6501 12/60 3.1.6 line formats each line of data from the sensor starts with an escape sequence followed by a line code that identifies the line type. the line code is then followed by two bytes that contain a coded line number. each line is terminated with an end-of-line code followed by a line average. the one exception to this is the first line in the frame where the end of line code is followed by a frame count. the line code formats are detailed in figure 9 . figure 8: line data format start of active video (sav) line end of active video (eav) number sav line code escape/sync sequence line code escape/sync sequence n pixels 1n pixel number (unshuffled pixel data) null pixav video data y h d 1 d 0 d 3 d 2 p m p l p m p l 8 h 0 h x h 4/5-wire data bus 0 h f h 0 h f h f h d 1 d 0 d 3 d 2 line padding
13/60 VV6501 functional description the line code absolute value depends on whether 5-wire or 4-wire output mode has been selected, as shown in ta bl e 3 . figure 9: line code format table 3: line codes line code 5-b nibbles 4-b nibbles line codes at beginning of line start of frame 31c h (796 10 )c7 h (199 10 ) blank line (bl) 274 h (628 10 )9d h (157 10 ) black or dark line (bk) 2ac h (684 10 )ab h (171 10 ) visible line (vl) 2d8 h (728 10 )b6 h (182 10 ) last line in frame 368 h (872 10 )da h (218 10 ) line code at end of line end of line 200 h (512 10 )80 h (128 10 ) line code see ta b l e 3 supplementary data at start of line: line number (l 11 msb) odd word parity 0 1 2 3 4 5 6 7 bit l 11 0 l 10 l 9 l 7 l 8 l 6 p nibble d 2 nibble d 3 0 1 2 3 4 5 6 7 bit l 5 0 l 4 l 3 l 1 l 2 l 0 p nibble d 0 nibble d 1 4-wire output mode escape/sync sequence d 0 d 1 d 2 d 3 y h x h 0 h 0 h f h f h f h f h 5-wire output mode 00 h 00 h 1f h 1f h 1f h 1f h (ii) all other lines: line average (av 7 msb) nibble d 2 nibble d 3 = f h nibble d 0 nibble d 1 av 6 av 7 av 5 av 4 av 2 av 3 av 1 av 0 0 0 0 0 1 0 1 1 (i) first (start of frame) line: frame count (fc 7 : msb) nibble d 2 nibble d 3 = f h nibble d 0 nibble d 1 fc 6 fc 7 fc 5 fc 4 fc 2 fc 3 fc 1 fc 0 0 0 0 0 1 0 1 1 at the end of the lines there are 2 possibilities:
functional description VV6501 14/60 start of frame line format the start of frame line contains the contents of the first 16 serial interface registers rather than any video data. this information immediately follows the line code at the beginning of the line. the code 07 h is output after each serial interface value. it takes 32 pixel clock periods to output these 16 serial interface register values. the remaining pixel periods of the video portion of the line are padded out using 07 h values. the first two pixel locations are also padded with 07 h characters ( figure 10 ). if a serial interface register location is unused then the value from register 0 is output. following the escape sequence and line code at the end of active video, a frame count is output. active video line format all video data is contained on active video lines. the pixel data appears as a continuous stream of bytes within the active lines. black line format the black lines contain information from the sensor black lines (held in zero exposure). this information may be used by certain co-processors. dark line format the dark lines contain information from the sensor dark lines (shielded from light by metal). the information from these lines is used by the sensor to calculate a dark average offset value which is then applied to the video data to ensure a known black level for image data. blank line format to reduce the frame rate it is possible to extend the frame length by adding blank data lines. these contain no video or black line data. in default vga mode there are no blank lines. end of frame line format the end of frame line sole purpose is to indicate the end of a frame, it contains no video data. figure 10: start of frame line format start of active video end of active video serial interface register values 0 h 1 h 0 h 1 h f h f h 1 h 9 h (sav) (eav) c h 7 h 0 h 7 h 0 h 7 h 4 h 0 h 0 h 7 h 0 h 7 h 8 h 0 h 0 h 0 h d 1 d 0 d 3 d 2 f h frame count line number 0 deviceh (register 0) devicel (register 1) padding characters start of frame line codes data bus
15/60 VV6501 functional description line duration ta bl e 4 shows the image duration and interline intervals with default setup. extending line lengths the user can extend the line length by writing to serial registers 82 and 83. the line length padding is inserted after the eav sequence, ensuring that the distance between the sav and eav sequences remains constant. 3.1.7 frame format each video frame is composed of a sequence of data lines as illustrated in figure 11 . extending the inter-frame period the user may choose to extend the inter-frame period by increasing the frame length by writing to serial registers 97 and 98. in this event, the appropriate number of additional blank lines is inserted between the end of frame (eof) line and the start of frame (sof) line. this means that the distance between sof and eof remains constant. table 4: line timing sensor clock pixel clock image interline line total qcks s qcks s qcks s 24mhz 12mhz 644 53.6 118 9.8 762 63.5 figure 11: vga frame format 319 18 black lines start of frame line 6 dark lines 484 visible lines vga frame = 524 lines 1 0 2 24 507 506 25 523 510 19 26 end of frame line 509 508 14 black lines 18 start of frame line 0
functional description VV6501 16/60 timing of frame start signal (fst) the frame-level position of fst is illustrated in figure 12 . the fst pulse qualifies the status line information and is 648 qcks (slow) long. figure 12: fst timing overview figure 13: detailed fst timing start of frame black lines blanking lines start of frame black lines blanking lines visible lines end of frame blanking lines fst: 1 frame 0 h 1 h 0 h 1 h f h f h 1 h 9 h c h 7 h 0 h 7 h 0 h 7 h 4 h 0 h 0 h 7 h 0 h 7 h 8 h 0 h 0 h 0 h start of frame line code d 1 d 0 d 3 d 2 f h frame start pulse qualifies status line: 648 qcks 644 qcks 4 qcks data bus fst pin:
17/60 VV6501 functional description 3.1.8 image translations the imaging array can be readout with different modes as described here below: l shuffle horizontal readout, bit [7] of serial register [17]. even columns (2,4,6.) are readout first. l mirror horizontal readout, bit [3] of serial register [22]. columns are readout in reverse order. l mirror vertical readout, enabled by setting [4] of serial register [22]. rows are readout in reverse order. figure 14: image readout modes (a) standard image readout (b) horizontal shuffle enabled (c) horizontal mirror enabled (d) vertical mirror enabled
functional description VV6501 18/60 3.1.9 dark calibration in order to produce a high quality output image from the VV6501, it is necessary to accurately control the black level of the video signal. there are two main sources of error: l dark current l offsets in the output path. the black level is corrected by using dark pixel rows to learn the offset so that it can then be subtracted from the image data. dark rows have the same exposure setting as the visible lines but are shielded from incident light. for 10-b data the ideal black code is set to be 64 (when viewing 8-b data the black code should be 16). the aim of the dark calibration algorithm is to learn the offset required such that black image lines have code 64. figure 15: overview of dark offset cancellation figure 16: role of dark offset calibration dpix vpix column adc element + offset dpix vpix 10-b column adc element + offset 10-b normal pixel idark dark pixel ilight + idark offset cancellation learn offset + idark digital logic dark line typ. value = 400 image line typ. value: 400 - 1360 dark calibration dark offset = 336 dark line typ. value = 64 image line typ. value: 64-1024 processed image raw image
19/60 VV6501 functional description dark calibration algorithm the dark line monitoring logic accumulates a number of dark pixels, calculates an average and then compares this average with the appropriate black level. there is a bit in serial register 45 which determines whether the offset applied is the user-programmable value from serial register 44, or the value calculated by the offset cancellation processor. the dark offset cancellation algorithm accumulates data from the dark lines which is input to a leaky integrator and an appropriate offset is calculated. following an exposure/gain change, on power up or when going out of suspend mode, the history in the dark calibration leaky integrator is reset to the incoming value as the previously stored value will be out of date. user control the serial interface allows the user the following additional controls: l accumulate dark pixels, calculate dark pixel average and report, but do not apply anything to data stream l accumulate dark pixels, calculate dark pixel average, report and apply internally calculated offset to data stream l accumulate dark pixels, calculate dark pixel average and report, but apply a sif supplied offset 3.1.10 sensor clock and frame rate control the frame rate is determined by both the input sensor clock and some additional registers under user control. sensor clock the sensor requires a single-ended clock input. a 24mhz clock is required to generate 30 frames per second vga images. the results is a pixel rate of 12mhz. slower frame rates in order to achieve slower frame-rates the user has a number of options: l increase the inter-frame time by adding blank line (via sif register) l apply a slower external clock l divide down the external clock using the sensor internal clock divider (via sif register) clock divider the sensor contains a 4-bit register with which the user selects the clock divider setting (n). ta bl e 5 gives the mapping between the clk_div value and the divider ratio. table 5: user programmable clock divider values clk_div[3:0] divide by 0000 [default] 1 0001 2 001x 4 010x 6 011x 8 100x 10
functional description VV6501 20/60 3.1.11 exposure/gain control the sensor does not contain any form of automatic exposure or gain control. to produce a correctly exposed image, exposure and gain values must be calculated externally and written to the sensor via the serial interface. exposure calculation the exposure time for a pixel and the adc range (therefore the gain) are programmable via the serial interface. the explanation below assumes that the gain and exposure values are updated together as part of a 5 byte serial interface auto-increment sequence. exposure time combines coarse, fine exposure, pixel rate also related to frame and line lengths, all defined in ta bl e 6 . example of exposure calculation in default vga video mode coarse exposure = 522 fine exposure = 762 input clock frequency - fclkin = 24mhz, pixel period = 2/(24 x 10 6 ) = 8.33 x10 -8 s calculation : exposure time = 8.33 x10 -8 x [(522 x 762) +762] = 33.2 ms 101x 12 110x 14 111x 16 table 6: definitions related to exposure frame length number of lines per frame [default=524] the frame length may be increased to 1023 by writing to the frame length register. line length number of pixels in a line [default = 762] the line length may be increased to 1023 by writing to the line length register. exposure the pixel exposure time is determined by the course and fine exposure values coarse exposure value the number of lines a pixel exposes for. limited by frame length. coarse exposure value is in the range [0 - (frame length -2)]. fine exposure value number of additional pixel periods a pixel exposes for. limited by line length. fine exposure value is in the range [11 - (line length)]. pixel period determined by the input clock frequency (fclkin) and user clk_div setting. pixperiod=(2*n)/fclkin where n = clock divider ratio exposure time pixperiod x [(coarse num_lines x line_length num_pixels ) + fine pixels ] table 5: user programmable clock divider values clk_div[3:0] divide by
21/60 VV6501 functional description the available range of exposure (without using clock division) is shown in ta bl e 7 . 3.1.12 gain timing and exposure updates exposure and gain values are re-timed within the sensor to ensure that a new set of values is only applied to the sensor array at the start of each frame. bit 0 of the status register is set high when a new exposure value is written via the serial interface but has not yet been applied to the sensor array. there is a 1 frame latency between a new exposure value being applied to the sensor array and the results of the new exposure value being read-out. the same latency does not exist for the gain value. to ensure that the new exposure and gain values are aligned up correctly the sensor delays the application of the new gain value by one frame relative to the application of the new exposure value. to eliminate the possibility of the sensor array seeing only part of the new exposure and gain settings, if the serial interface communication extends over a frame boundary, the internal re-timing of exposure and gain data is disabled while writing data to any location in the exposure page of the serial interface register map. thus, if the 5 bytes of exposure and gain data is sent as an auto- increment sequence, it is not possible for the sensor to consume only part of the new exposure and gain data. table 7: exposure ranges [24mhz system clock] range coarse (no. lines) line length (no. pixels) fine (no. pixels) exposure no. pixels time min. 0 762 11 0 0.92 s max (default-vga) 522 762 762 400,050 33.2 ms max (available) 1023 1023 1023 1023 2 + 1023 87.3 ms
functional description VV6501 22/60 3.2 audio block the audio amplifier is designed to drive an external adc, possibly in the co-processor, with an amplified audio signal taken from a fet microphone input. the 3-bit gain control and power down for the reference are controlled via the i 2 c interface. 3.2.1 co-processor support for audio ta bl e 8 below summarizes the audio capability of the different co-processors the VV6501 is intended to work with. figure 17: VV6501 audio amplifier overview table 8: co-processor support for audio co-processor audio support comment stv0676 audio 8-b digital endpoint external adc needed stv0674 16 bit sigma-delta 501 audio output is directly ac coupled to stv0674 differential audio inputs. stv0674 includes digital alc and noise gate stv0680/1 successive approximation adc low quality audio recording support micro + - + - + - audio bandgap audref micin audgain[2:0] audoutp audoutn micbias pdaudref digital block x1 x1 aud3v3 power management audio amplifier
23/60 VV6501 functional description 3.2.2 audio amplifier key features l very high psrr micro bias reference due to bandgap from the 3.3v regulated supply, as well as rc network for lf filtering in the audio bandwidth. l fully differential low-noise amplifier with gain control via serial if (0db to +42db in 6db steps). up to 1.8vpp dynamic range on audoutp and audoutn figure 18: VV6501 audio amplifier in typical application electret mic cc 220nf cc 220nf x1.3 buffer 50k 50k differential adc audio regulator input stage stv0674 1 lna aud3v3 audref micbias micin gain[2:0] 0:42db pd v5v audoutp audoutn r cin 470nf aud3v3 100nf 2.2uf audio power management audio bandgap
functional description VV6501 24/60 3.3 power management 3.3.1 voltage regulators the power management block on the device avoids the requirement for any external system regulators in a 5 v based camera product. the scheme is shown in figure 19 . l digital regulator 1 - this 5 v to 3.3 v regulator uses an external bipolar transistor to supply loads up to 200 ma. it is typically used to power the sensor digital logic and may also be used to supply an external co-processor if required. this regulator is always on. l digital regulator2 - this 3.3 v to 1.8 v regulator uses an external bipolar transistor to supply loads up to 100 ma. this supply may be used for an external co-processor if required. this regulator is controlled by the pdreg1v8 pin and must be switched off if not required. l audio amp regulator - this 5 v to 3.3 v regulator supplies the audio amplifier and the buffer amplifier used to supply the reference to the microphone (load 5 ma). it should be externally decoupled with a 2.2 f capacitor. for applications without audio this regulator may be powered down via the sif registers. l video regulator - this 5 v to 3.3 v regulator supplies the analogue video circuitry. it should be externally decoupled with a 2.2 f capacitor. figure 19: voltage regulator bl ock diagram pdreg1v8 10f 5v co- vbg 5v vbg core (1v8) io (3v3) 1v8 3v3 dig reg1 5v bandgap + - vbase3v3 vdig3v3 v5v 4-5.5v ztx749 vbg vdd vdd 6.8nf 3v vbg dig reg2 + - pd pdreg2 vdig1v8 5v vbg vidreg + - pd vid3v3 pdvidreg pdaudreg 5v vbg audreg + - pd aud3v3 vbase1v8 10f 1 m f ztx749 VV6501 digital block audio amplifier voltage doubler video block power management block 2.2f 2.2f processor
25/60 VV6501 functional description 3.3.2 power-on reset cell the power-on reset cell generates a low going pulse whenever the digital power supplies are below their lower limits. the power-on reset signal resets the sensor internally and is also available on the porb pin and may be used to reset a co-processor. the porb cell monitors both the 3v3 and 1v8 supplies. if the 1v8 supply is not required then pdvreg1v8 must be tied high. figure 20: power-on reset block porb 0v 3v/1v8 porb clkin vdig3v3 vdig1v8 pdreg1v8 3v3 power-on reset cell porb block 1v8 power-on reset cell regulated supply threshold
functional description VV6501 26/60 3.4 device operating modes 3.4.1 power-up on power up the sensor is in low-power mode. all data bus lines drive high to indicate that the device is present. 3.4.2 waking up the sensor the sensor is made to exit low power mode by enabling the external clock and writing to sif register16 bit 0. the first frame output after exiting low-power mode does not contain any valid video data. 3.4.3 low power mode entering low-power mode during video streaming causes the analogue circuits to be powered down. the values of the serial interface registers is preserved. figure 21: exiting low-power mode 0 1 d[4:0] clkin frame number sda scl 2 start of frame line for the 1st frame of valid video data. valid video data. lp1 setup0[0] lp1 d[4:0] are set to f h and the sensor analogue circuitry is powered down. lp2-lp3 exit low power mode command. powers-up analogue circuits and initiates the 1 frame start-up sequence lp3-lp4 1 frame of alternating 9 h & 6 h data on d[4:0] the sensor is being initialized during this frame. one frame of 9 h & 6 h data. f h 9 h ,6 h ,9 h ,6 h ... lp2 lp3 lp4
27/60 VV6501 functional description 3.4.4 suspend mode suspend mode is the lowest possible power consumption mode with current < 100 a. in suspend mode the external clock is gated inside the device and the analogue blocks are powered down. the sensor is set into suspend mode by driving the suspend pin high. to achieve the lowest possible power consumption, the clock source should also be turned off for the duration of the suspend mode. 3.4.5 sensor soft reset all the serial interface registers may be reset to their default values by setting the soft reset bit (bit 2) of setup register 0. this causes the sensor to enter low power mode.
serial control bus VV6501 28/60 4 serial control bus 4.1 general description the 2-wire i2c serial interface bus is used to read and write the sensor control registers. some status registers are read-only. the main features of the serial interface include: l variable length read/write messages. l indexed addressing of information source or destination within the sensor. l automatic update of the index after a read or write message. l message abort with negative acknowledge from the master. l byte oriented messages. 4.2 serial communication protocol the co-processor must perform the role of communication master and the sensor acts as a slave. the communication from host to sensor takes the form of 8-bit data with a maximum serial clock frequency of 100 khz. since the serial clock is generated by the bus master it determines the data transfer rate. data transfer protocol on the bus is illustrated in figure 22 . 4.2.1 data format information is packed in 8-bit packets (bytes) always followed by an acknowledge bit. the internal data is produced by sampling sda at a rising edge of scl . the external data must be stable during the high period of scl . exceptions to this are start (s) or stop (p) conditions when sda falls or rises respectively, while scl is high. a message contains at least two bytes preceded by a start condition and followed by either a stop or repeated start, (sr) followed by another message. figure 22: serial interface data transfer protocol 12 7 8 a start condition stop condition sda scl acknowledge p s 3 4 56 address or data byte msb lsb
29/60 VV6501 serial control bus the first byte contains the device address byte which includes the data direction read, (r) , ~write , (~w), bit. the byte following the address byte contains the address of the first data byte (also referred to as the index ). the serial interface can address up to 128 byte registers. if the msb of the second byte is set, the automatic increment feature of the address index is selected. 4.2.2 message interpretation all serial interface communications with the sensor must begin with a start condition. if the start condition is followed by a valid address byte then further communications can take place. the sensor will acknowledge the receipt of a valid address by driving the sda wire low. the state of the read/~write bit (lsb of the address byte) is stored and the next byte of data, sampled from sda, can be interpreted. during a write sequence the second byte received is an address index and is used to point to one of the internal registers. the msb of the following byte is the index auto increment flag. if this flag is set then the serial interface will automatically increment the index address by one location after each slave acknowledge. the master can therefore send data bytes continuously to the slave until the slave fails to provide an acknowledge or the master terminates the write communication with a stop condition or sends a repeated start , (sr) . if the auto increment feature is used the master does not have to send indexes to accompany the data bytes. as data is received by the slave, it is written bit by bit to a serial/parallel register. after each data byte has been received by the slave, an acknowledge is generated, the data is then stored in the internal register addressed by the current index. during a read message, the current index is read out in the byte following the device address byte. the next byte read from the slave device are the contents of the register addressed by the current index. the contents of this register are then parallel loaded into the serial/parallel register and clocked out of the device by scl. at the end of each byte, in both read and write message sequences, an acknowledge is issued by the receiving device. although VV6501 is always considered to be a slave device, it acts as a transmitter when the bus master requests a read from the sensor. figure 23: VV6501 serial interface address figure 24: serial interface data format 0 0 1 0 0 0 0 r/w s address[7:1] r / w bit a data[7:0] a sensor acknowledges valid address acknowledge from slave index[6:0] inc p a a data[7:0] [0] address auto increment index bit
serial control bus VV6501 30/60 at the end of a sequence of incremental reads or writes, the terminal index value in the register will be one greater than the last location read from or written to. a subsequent read will use this index to begin retrieving data from the internal registers. a message can only be terminated by the bus master, either by issuing a stop condition, a repeated start condition or by a negative acknowledge after reading a complete byte during a read operation. 4.3 types of messages this section gives guidelines on the basic operations to read data from and write data to the serial interface. the serial interface supports variable length messages. a message may contain no data bytes, one data byte or many data bytes. this data can be written to or read from common or different locations within the sensor. the range of instructions available are detailed below. l write no data byte, only sets the index for a subsequent read message. l multiple location write (using auto increment index bit) for fast information transfers. examples of these operations are given below. a full description of the internal registers is given in the previous section. for all examples, the slave address used is 32 10 for writing and 33 10 for reading. the write address includes the read/write bit (the lsb) set to zero while this bit is set in the read address. 4.3.1 single location, single data write when a random value is written to the sensor, the message looks as shown in figure 25 . in this example, the fineh exposure register (index = 32 10 ) is set to 85 10 . the r/w bit is set to zero for writing and the inc. bit (msb of the index byte) is set to zero to disable automatic increment of the index after writing the value. the address index is preserved and may be used by a subsequent read. the write message is terminated with a stop condition from the master. 4.3.2 single location, single data read a read message always contains the index used to get the first byte. figure 25: single location, single write figure 26: single location, single read s 20 h a 0 32 h a 85 h a p start device ack address index data stop s 21 h a 0 32 h a 85 h a p start device ack address index data stop
31/60 VV6501 serial control bus this example assumes that a write message has already taken place and the residual index value is 32 10 . a value of 85 10 is read from the fineh exposure register. note that the read message is terminated with a negative acknowledge (a ) from the master: it is not guaranteed that the master will be able to issue a stop condition at any other time during a read message. this is because if the data sent by the slave is all zeros, the sda line cannot rise, which is part of the stop condition. 4.3.3 no data write followed by same location read when a location is to be read and the value of the stored index is not known, a write message with no data byte must be written first, specifying the index. the read message then completes the message sequence. to avoid relinquishing the serial to bus to another master, a repeated start condition is asserted between the write and read messages. in this example, the gain value (index = 36 10 ) is read as 15 10 (see figure 27 ). as mentioned in the previous example, the read message is terminated with a negative acknowledge (a ) from the master. 4.3.4 multiple location write if the automatic increment bit is set (msb of the index byte), it is possible to write data bytes to consecutive adjacent internal registers without having to send explicit indexes prior to sending each data byte. an auto-increment write to the exposure registers with their default values is shown in figure 28 . figure 27: no data write followed by same location read figure 28: multiple location write s a sr a a a p 21 h 36 h 21 h 36 h 15 h a 0 0 no data write read index and data sa 11 h a aa 20 h 10 h c1 h 1 incremental write p
i2c registers VV6501 32/60 5 i2c registers 5.1 register map sensor registers may be split into 5 main categories: l status registers (read only) l setup registers with bit significant functions l exposure parameters that influence output image brightness l video timing functions l audio functions any internal register that can be written to can also be read from. there are a number of read only registers that contain device status information, (for example design revision details). names that end with h or l denote the most or least significant part of the internal register. note that unused locations in the h byte are packed with zeroes. a detailed description of each register follows. the address indexes are shown as decimal numbers in brackets [ ]. note that there are many unused register locations.
33/60 VV6501 i2c registers table 9: serial interface address map index name length r/w default comments status registers 0x00 deviceh 8 ro 0x1f chip identification number including revision indicator (501 rev0). 0x01 devicel 8 ro 0x50 0x02 status0 8 ro 0x10 status information 0x09 dark_avgh 4 ro 0 this is the average pixel value returned from the dark line offset cancellation algorithm (2s complement notation) 0x0a dark_avgl 8 ro 0 0x0e frame counter 8 ro current frame count (0-255) setup registers 0x10 setup0 8 r/w 0x1 low-power and video timing 0x11 setup1 8 r/w 0x80 various parameters 0x14 fg_modes 8 r/w 0 fst and qck setup 0x15 pin_mapping 7 r/w 0 fst and qck mapping modes 0x16 vshuffle/mirrors 8 r/w 0 read-out order of data 0x17 op_format 7 r/w 0x18 output coding formats exposure registers 0x20 fineh 2 r/w 0 fine exposure 0x21 finel 8 r/w 0x22 coarseh 2 r/w 0x20a coarse exposure 0x23 coarsel 8 r/w 0x24 analogue gain 4 r/w 0 analogue gain setting 0x25 clk_div 4 r/w clock division 0x2c dark offseth 3 r/w 0 dark line offset cancellation value (2s complement notation) 0x2d dark offsetl 8 r/w 0x2e dark offset setup 3 r/w 0x61 dark line offset cancellation enable video timing registers 0x52 line_lengthh 2 r/w 0x2f9 line length (pixel clocks) 0x53 line_lengthl 8 r/w 0x54 frame_lengthh 2 r/w 0x20b frame length (lines) 0x55 frame_lengthl 8 r/w audio register 0x79 audio 4 r/w 0x9 audio setup register
i2c registers VV6501 34/60 5.2 register description 5.2.1 status registers [0x00-0x01] - deviceh and devicel these registers provide read only information to identify the sensor type that has been coded as a 12-bit number and a 4-bit mask set revision identifier. the device identification number for VV6501 is 501 equivalent to 0001 1111 0101 2 . the initial mask revision identifier is 0 equivalent to 0000 2 . [0x02] - status0 table 10: [0x00] - deviceh bits function default comment [7:0] device type identifier 0x1f most significant 8 bits of the 12 bit code identifying the chip type. table 11: [0x01] - devicel bits function default comment [7:4] device type identifier 0x5 least significant 4 bits of the 12 bit code identifying the chip type. [3:0] mask set revision identifier 0 bit function default comment 7 video timing parameter update pending flag 0 video timing parameters sent but not yet consumed by sensor [6:5] reserved 4 odd/even frame 0x1 the flag will toggle state on alternate frames 3 clock division update pending 0 clock divisor sent but not yet consumed by the sensor 2 gain value update pending 0 gain value sent but not yet consumed by the sensor 1 coarse exposure value update pending 0 coarse exposure value sent but not yet consumed by the sensor 0 fine exposure value update pending 0 fine exposure value sent but not yet consumed by the sensor
35/60 VV6501 i2c registers [0x09-0x0a] - dark_avg [0x0e] - frame counter 5.2.2 setup registers [0x10] - setup0 [0x11] - setup1 register index bits function default comment 10 [7:0] dark avg ls byte 0 the calculated pixel average over a series of dark lines. 9 [1:0] dark avg ms bits 0 register index bits function default comment 14 [7:0] frame count 0 increments by 1 at each frame bit function default comment [7:5] video timing mode 0x1 vga mode [4:3] reserved 2soft reset off / on 0 setting this bit resets the sensor to its power-up defaults. this bit is also reset. 1 reserved 0 low power mode: off / on 0x1 powers down the sensor array and audio. the output data bus goes to f h . on power-up the sensor enters low power mode. bit function default comment 7 pixel read-out order (hshuffle) unshuffled or shuffled 1 shuffle is enabled by default [6:5] reserved 4 enable immediate gain update. off /on 0 allow manual change to gain to be applied immediately 3 enable immediate clock division update. off /on 0 allow manual change to clock division to be applied immediately [2:0] reserved
i2c registers VV6501 36/60 [0x14] - fg_modes [0x15] - pin_mapping [0x16] - vshuffle/mirrors bit function default comment [7:6] fst mode 0 0 - off 1 - on - qualifies the status line [5:4] reserved [3:2] qck modes 0 00 - off 01 - free running 1x - valid during data period only 1 reserved 0 qclk type 0 0 - slow_qclk/ 1 - fast_qclk bit function default comment 7 reserved 6 reset_flag. 1 set to 1 by porb, reset_n soft_reset. the user can clear this bit by writing to sif. 5 reserved [4:3] reserved 2 forced value for fst pin 0 only when enabled by bit0 1 forced value for qclk pin 0 only when enabled by bit0 0 map serial interface register bits values on to the qck and fst pins. 0 select data to appear on fst and qck pins 0 - fst and qck signals (default) 1 - pin_mapping[2] and pin_mapping[1] bit function default comment [7:5] reserved 4 line read-out order (vmirror) normal or mirrored 0 3 pixel read-out order (hmirror) normal or mirrored 0 [2:0] reserved
37/60 VV6501 i2c registers [0x17] - op_format bit function default comment 7 reserved 6 re-time tri-state update. off / on 0 re-time new tri-state value to a frame boundary. 5 tri-state output data bus, fst & qclk outputs enabled / tri-state 0 on power up the data bus, qclk & fst pads are enabled by default. [4:3] reserved 2 embedded sav/eav escape sequences on / off 0 0 - insert embedded control sequences e.g start and end of active video into output video data 1 - pass-through mode. output video data equals adc data. note: also disables fst when sav/eav generation disabled. 1 reserved 0 data format select. 0 0 - 5 wire parallel output 1 - 4 wire parallel output
i2c registers VV6501 38/60 5.2.3 exposure control registers there is a set of programmable registers which control the sensor sensitivity. the registers are as follows: l fine exposure l coarse exposure time l analogue gain l clock division the gain parameter does not affect the integration period rather it amplifies the video signal at the output stage of the sensor core. note: the external exposure (coarse, fine, clock division or gain) values do not take effect immediately. data from the serial interface is read by the exposure algorithm at the start of a video frame. if the user reads an exposure value via the serial interface, then the value reported will be the data as yet unconsumed by the exposure algorithm, because the serial interface logic locally stores all the data written to the sensor. between the writing the of exposure data and the use of the data by the exposure logic, bit 0 of the status register is set. the gain value is updated a frame later than the coarse, fine and clock division parameters, since the gain is applied directly at the video output stage and does not require the long set up time of the coarse, fine exposure and of the clock division. to eliminate the possibility of the sensor array seeing only part of the new exposure and gain settings, if the serial interface communication extends over a frame boundary, the internal re-timing of exposure and gain data is disabled while writing data to any location in the exposure page of the serial interface register map. thus if the 5 bytes of exposure and gain data is sent as an auto- increment sequence, it is not possible for the sensor to consume only part of the new exposure and gain data. the range of some parameter values is limited and any value programmed out of the range is clipped to the maximum allowed. table 12: exposure, clock rate and gain registers register index bits function default comment 0x20 0 fine msb exposure value 0 line length dependent 0x21 [7:0] fine lsb exposure value 0x22 0 coarse msb exposure value 0x20a frame length dependent. maximum for default modes: vga = 522 0x23 [7:0] coarse lsb exposure value 0x24 [7:0] analogue gain value 0 bits[3:0] idac control 0x25 [3:0] clock divisor value 0 see [0x25] - clock divider setting for details 0x2c [1:0] dark offseth 0 dark offset manual settings 0x2d [7:0] dark offsetl 0 0x2e [7:0] dark offset control register 0
39/60 VV6501 i2c registers [0x20] - fine exposure msb [0x21] - fine exposure lsb [0x22] - coarse exposure msb [0x23] - coarse exposure lsb [0x24] - analogue gain/ offset bit function default comment [7:2] reserved [1:0] fine exposure [9:8] 0 bit function default comment [7:0] fine exposure [7:0] 0 bit function default comment [7:2] reserved [1:0] coarse exposure [9:8] 0x2 bit function default comment [7:0] coarse exposure [7:0] 0xa default = 522 bit function default comment [7:4] reserved [3:0] gain [3:0] 0 0000 = 1.0, min. gain = (0db) 0001 = 1.06 0010 = 1.14 0011 = 1.23 0100 = 1.33 0101 = 1.45 0110 = 1.60 0111 = 1.78 1000 = 2.0 1001 = 2.29 1010 = 2.67 1011 = 3.2 1100 = 4.0 1101 = 5.33 1110 = 8.0 1111 = 16, max gain = (24db)
i2c registers VV6501 40/60 [0x25] - clock divider setting [0x2c -0x2d] - dark line pixel offset [0x2e] - dark line offset cancellation setup register bit function default comment [7:4] reserved [3:0] clock divider setting 0 0000 - divide clock by 1 0001 - divide clock by 2 001x - divide clock by 4 010x - divide clock by 6 011x - divide clock by 8 100x - divide clock by 10 101x - divide clock by 12 110x - divide clock by 14 111x - divide clock by 16 bit function default comment [7:0] ls dark line pixel offset 0 this register contains a fixed offset that can be applied to the digitised pixels in the digital output coding block. the offset is a 2s complement number, giving an offset range -1024,+1023. [2:0] ms dark line pixel offset bit function default comment 7 reserved [6:4] reserved 3 dark leaky integrator time constant 00 - fast 1 - slow 2 reserved [1:0] dark line offset cancellation 01 00 - accumulate dark pixels, calculate dark pixel average and report, but dont apply anything to data stream 01 - accumulate dark pixels, calculate dark pixel average, report and apply internally calculated offset to data stream 11 - accumulate dark pixels, calculate dark pixel average and report, but apply an externally calculated offset
41/60 VV6501 i2c registers 5.2.4 video timing registers indexes in the range [0x52 - 0x62] control the line and frame length of the sensor. the registers are as follows: l line length l frame length the line length is specified in a number of pixel clocks, whereas the frame length is specified in a number of lines.the range of some parameter values is limited and any value programmed out of the range is clipped as follows: l values greater than the maximum are clipped to the maximum allowed. l values less than the default for a given mode are clipped to the default value. table 13: video timing registers register index bit function default comment 0x53 [7:0] line length lsb value 0xf9 0x52 [7:2] reserved [1:0] line length msb value 0x2 default = 761 maximum = 1023 (register value is line length - 1) 0x62 [7:0] frame length lsb value 0x0b 0x61 [7:2] reserved [1:0] frame length msb value 0x2 default = 523 maximum = 1023 (register value is frame length - 1)
i2c registers VV6501 42/60 5.2.5 audio setup register [0x79] - audio amplifier setup (at1) bit function default comments 7 retro gain mode select 0 0 - retro gain mode 1 - standard gain mode 6 power down audio ref. only 0 [5:4] reserved 3 power down amp. and ref. 0 0 - powered up 1 - power down [2:0] audio amplifier gain 1 table 14: audio gain options reg121[2:0] retro gain mode ([[7]=0) standard gain mode ([7]=1) gain audgain[2:0] gain audgain[2:0] 000 0db 000 0db 000 001 30db 101 6db 001 010 6db 001 12db 010 011 36db 110 18db 011 100 12db 010 24db 100 101 42db 111 30db 101 110 18db 011 36db 110 111 24db 100 42db 111
43/60 VV6501 electrical characteristics 6 electrical characteristics 6.1 absolute maximum ratings caution: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 6.2 operating conditions 6.3 thermal data table 15: absolute maximum ratings symbol parameter max. unit v dd regulator input power voltage -0.5 to 6.0 v v dd digital power supply -0.5 to 3.6 v v cc analogue power supply -0.5 to 3.6 v t sto storage temperature a a. a temperature below 0c can induce a slight humidity penetration into the package cavity. this humidity is easily removable by a short storage in standard climatic conditions (25c/50% relative humidity). -25 to + 85 o c t lead lead temperature (10 s) jdec moisture level 3 225 c table 16: operating conditions symbol parameter max. unit v dd supply voltage 4.1 to 5.5 v t a ambient temperature 0 to +40 c table 17: thermal data symbol parameter value unit rth(j-a) junction/ambient thermal resistance 45 c/w
electrical characteristics VV6501 44/60 6.4 dc electrical characteristics over operating conditions unless otherwise specified. 6.4.1 power supply 6.4.2 digital block table 18: power supply characteristics symbol parameter description min. typ. max. unit v bus power supply range of operation 4 5 5.5 v i vbus normal mode sensor current consumption (vga 30 fps - no load on digital regulators) 25 50 ma i susp current consumption in suspend mode (suspend pin high) and vdig1v8 disabled. 65 140 a table 19: digital block electrical characteristics symbol parameter description min. typ. max. unit cmos digital inputs v il low level input voltage 0.8 v v ih high level input voltage 2 v i il low level input current -1 a i ih high level input current 1 a cmos digital outputs v ol low level output voltage 0.2 v v oh high level output voltage 2.8 v serial interface f sif operating frequency range 0 100 khz
45/60 VV6501 electrical characteristics 6.4.3 regulators table 20: electrical characteristics of regulators symbol parameter description min. typ. max. unit 5v bandgap v bg bandgap voltage 1.08 1.2 1.38 v i bg bandgap current drive capability 10 a digital regulator 1 v dig3v3 regulated output voltage, (i load < 300 ma) 3.0 3.3 3.6 v i load output current drive capability 200 300 ma psrr 10 hz < freq <10 khz, c = 1 f, relative to vbus voltage swing over operating range 40 db digital regulator 2 v dig1v8 regulated output voltage (i load < 50 ma) 1.62 1.8 1.98 v i load output current drive capability - 100 200 ma psrr 10 hz < frequency <10 khz, c = 1 f, relative to vbus voltage swing over operating range 40 db audio and video regulators v video 3.3 v video regulator 3.0 3.3 3.4 v i video video current drive capability 10 ma v audio 3.3 v audio regulator 3.0 3.3 3.4 v i audio audio current drive capability 5 ma
electrical characteristics VV6501 46/60 6.4.4 audio amplifier table 21: audio amplifier electrical characteristics symbol parameter description min. typ. max. unit audio reference r audref output impedance of audio reference i load < 100 a 100 k w i audref audio reference drive capability 1 a microphone bias v micbias microphone bias voltage 1.4 1.6 1.8 v i micbias microphone bias drive capability 500 a r micbias micro biasing voltage output impedance (i micbias < 500 a) 100 w microphone input r micin microphone input impedance 40 k w v micin microphone input dc voltage 1.6 v amplifier gain overall gain (outp or outn) / micin according to i 2 c settings 0 42 db dynout output dynamic voltage swing (outp / outn) 1.8 vpp thd harmonic distortion on outp & outn 1khz, 1.8v pp output. 0.1 % dcout output dc common voltage 1.6 v r out output impedance (outp / outn) i load < 300 a 100 w en input equivalent noise bw 20 hz to 20 khz / source impedance = 2.2k w 1.5 uvrms psr (diff) voltage supply rejection (diff: outp - outn) 42db gain, +/-200mv ripple on aud3v3 @ 1 khz 40 db psr (single) voltage supply rejection (outp / outn) 42db gain, +/-200mv ripple on aud3v3 @ 1 khz 40 db lfc low cut-off frequency (c in = 2.2 f) 20 hz hfc high cut-off frequency 20 khz
47/60 VV6501 electrical characteristics 6.5 ac electrical characteristics table 22: serial interface timing symbol parameter max. unit f scl scl clock frequency 100 khz
optical characteristics VV6501 48/60 7 optical characteristics 7.1 optical characterisation methods the following measurements are made based on the pixel as summarized in ta bl e 2 3 . average sensitivity the average sensitivity is a measure of the image sensor response to a given light stimulus. the optical stimulus is a white light source with a color temperature of 3200k, producing uniform illumination at the surface of the sensor package. for a color sensor, an ir blocking filter, cm500, is added to the light source. the analog gain of the sensor is set to x1. the exposure time, d t , is set as 50% of maximum. the illuminance, i , is adjusted so the average sensor output code, xlight , is roughly mid-range equivalent to a saturation level of 50%. once xlight has been recorded the experiment is repeated with no illumination to give a value xdark. the sensitivity is then calculated as . the result is expressed in volts per lux-second. dark signal the dark signal is a measure of the effect of pixel leakage current on the sensor output. the measurement is performed without illumination. as the dark signal is small the analog gain, g , of the sensor is increased to x4. for the same reason the clock divisor is set to16. as the leakage is highly temperature dependent, measurement is done at a controlled temperature of 25 o c. the mean sensor output is then recorded at 2 exposure settings: xdark at the maximum exposure time; xblack at zero exposure. the dark signal is calculated as and is expressed in volts per second. temporal noise of pixel and readout a measure of the temporal noise is required to quantify the noise floor. as the signal is small the gain, g , is set to the maximum of x16. in order to remove fixed pattern noise sources it is calculated as the standard deviation, s black , of the difference of a pair of zero exposure and zero illumination images. random noise is expressed in mv. dynamic range the dynamic range is the measure of the maximum and minimum signal levels at which the sensor can be used. the figure for temporal noise is used to find the dynamic range as follows . table 23: VV6501 pixel overview parameter value unit size 5.6 x 5.6 m architecture 3t, dds saturation voltage at pixel, v sat (gain x1, 1024 codes) 1.2 v fd capacitance 3.0 ff xlight xdark C d ti --------------------------------------- x dark xblack C d tg ----------------------------------------- 20 gvsat s black -------------------- log
49/60 VV6501 optical characteristics sensor snr the snr measurement given here is based on the temporal noise. the snr is calculated as the pixel saturation voltage divided by the temporal noise at that saturation level. the optical setup is the same as for the measurement of average sensitivity. the sensor gain, g , is set to x1. the snr figure is then calculated as: . fixed pattern noise (fpn) the fpn of an image sensor is the average pixel non-temporal noise divided by the average pixel voltage. the illumination source is the same as for the average sensitivity measurement. the fpn is calculated at coarse exposure settings of 0,10,150,250 and 302 with a gain set to 1. 10 frames are grabbed and averaged to produce a temporally independent frame before each calculation. fpn is expressed in mv. vertical fixed pattern noise (vfpn) vfpn describes the spatial noise in an image sensor related to patterns with a vertical orientation. the vfpn is defined as the standard deviation over all columns of the average pixel voltage for each column determined at zero exposure and zero illumination. vfpn is expressed in mv. shading shading describes how average pixel values per block change across the image sensor array. for fine shading calculations, the image sensor array is split into 30 pixel by 30 pixel blocks. an average value is then calculated for each block, averages are then compared across the whole device. the blocks are increased in size to 60 pixels by 60 pixels for the gross shading calculation. shading is expressed in mv. 7.2 optical characterisation results table 24: optical characterization optical parameter red green blue unit average sensitivity - 2.05 - v/lux.s dark signal - 9.0 - mv/s temporal noise - 2.12 - mv dynamic range - 54 - db snr - 41 - db fixed pattern noise - 1.13 - mv vertical fixed pattern noise - 0.68 - mv shading (gross) 1.1 1.3 1.0 % 20 gvsat s signal -------------------- log
optical characteristics VV6501 50/60 7.3 spectral response the spectral response measurement is given below. 7.4 blooming we do not perform any test measurements for blooming. blooming is a phenomenon that does not affect cmos sensors the same way as ccd imagers are afflicted. ccd blooming can cause an entire column or set of columns to flood and saturate. figure 29: spectral response response (v/s) / (w/m 2 ) wavelength in nm 700 800 900 1000 red green1 green2 blue 2000 1500 1000 500 0 -500 400 500 600
51/60 VV6501 defect categorisation 8 defect categorisation 8.1 introduction two distinct categories of defects are discussed in this section: l pixel defects ( section 8.2 - section 8.5 ) l physical aberrations ( section 8.6 ) the two categories differ in terms of test methodology as explained below. 8.2 pixel defects all packaged cmos image sensors can contain impurities, either silicon faults, optical blemishes or external dirt particles which can be introduced in the product at various stages of the manufacturing process. these impurities can result in pixel defects, that is a pixel whose output is not consistent with the level of incident light falling on the image sensor. precise definitions of the type of pixel defect tested by stmicroelectronics are outlined below. the ability to identify and correct these defects is central to both the design requirements and quality certification, via test of stmicroelectronics sensor products. stmicroelectronics produces a number of hardware co-processors and software drivers that implement defect correction algorithms. the defect correction algorithms ensure that the VV6501 sensor in conjunction with a companion stmicroelectronics co-processor will produce a high quality final image.
defect categorisation VV6501 52/60 8.3 sensor array area definition for specific aspects (refer to couplet test, see section 8.4.3 ) of pixel defect testing, the image sensor array is subdivided into two regions as follows: the inner array in figure 30 above is centre justified, in the x and y axis, with respect to the outer array. the inner array is 50% of the full width and 50% of the full height of the larger outer array, therefore the inner array is one quarter of the area of the outer array. figure 30: VV6501 array 322 pixels 644 pixels 484 pixels 242 pixels inner area outer area
53/60 VV6501 defect categorisation 8.4 pixel fault definitions 8.4.1 pixel fault numbering convention please find the pixel notation described in figure 31 below. for test purpose, the 3x3 array describes 9 bayer pixels of a common color, that is all the pixels will either be red, green or blue. the pixel under test is x . 8.4.2 single pixel faults stmicroelectronics define a single pixel fail as a failing pixel with no adjacent failing neighbors of the same colour. a single pixel fail can be a stuck at white where the output of the pixel is permanently saturated regardless of the level of incident light and exposure level, a stuck at black where the pixel output is zero regardless of the level of incident light and exposure level or simply a pixel that differs from its immediate neighbors by more than the test threshold, that is differ by more than 8.0% from pixel average of color space neighbors. in the example below in figure 32 , we assume that the pixel x is a fail. this pixel is qualified as single pixel fail if the pixels at positions [0],[1],[2],[3],[4],[5],[6] and [7] are good pixels that pass the final test. the implemented test program qualifies a sensor with up to 120 single pixel faults. defect correction algorithms correct the single pixel faults in the final image. figure 31: pixel numbering notation figure 32: single pixel fault [0] [1] [2] [7] x [3] [6] [5] [4] [0] [1] [2] [7] x [3] [6] [5] [4]
defect categorisation VV6501 54/60 8.4.3 couplet definition a failing pixel at x with a failing pixel at position [0] or [1] or [2] or [3] or [4] or [5] or [6] or [7] such that there is a maximum of 2 failing pixels from the group of 9 pixels illustrated in figure 33 is described as a couplet fail. the example shown on the right in figure 33 has failing pixels at the centre location and at position [7]. the basic couplet definition is further subdivided into minor and major couplets. with respect to the example in figure 33 , a minor couplet is defined as a defect pixel pair where one pixel can be an extreme fail, that is a stuck at black or stuck at white, but the second pixel in the pair must differ from the local pixel average by less than 15% of that average value. if the second pixel in the couplet differs by more than 15% of the local pixel average value then this would be defined as a major couplet. note that the test program considers a couplet as 2 independent pixels. if the test identifies two independent pixel fails (pixels that differ by more than 15% from pixel average of neighbors) that form a couplet with 2 minor pixel fails within the inner area, the device fails the test and is rejected. if however the test identifies 2 couplets where the pixels span the border between the inner and outer areas and where only one of the pixels in the inner area is determined as a major fail and the other a minor fail, then this device passes the test. 8.4.4 cluster definition we define a cluster fail as a failing pixel with at least two adjacent failing pixels. in the example from figure 34 , there are additional pixel fails in positions [0] and [7]. this example constitutes a cluster. a sensor containing a cluster is always rejected. 8.5 summary pass criteria figure 33: general couplet examples figure 34: cluster example table 25: sensor pixel defect pass criteria single pixel fails minor couplet a a. test program will allow maximum of one minor couplet in inner zone of pixel array. test program will allow maximum of two minor couplets in outer zone of pixel array. major couplet b b. no major couplet allowed. clusters <=120 1 (2) 0 0 [0] [1] [2] [7] x [3] [6] [5] [4] [0] [1] [2] xx[3] [6] [5] [4] [ x ][1][2] [ x ]x[3] [6] [5] [4]
55/60 VV6501 defect categorisation 8.6 physical aberrations silicon surface irregularities and external marks, both pits and deposits, on the package glass lids can cause a deterioration in image quality. stmicroelectronics recognize that this could compromise the product quality and therefore have introduced a specific test algorithm to identify and reject samples that display these phenomena. the pass/fail criteria for this test are given in section 8.6.1 . 8.6.1 test details the test defines 2 areas: l a small area: 9 by 9 pixels with pixel under test at the centre of this area (shaded blue in figure 35 ) l a large region, 31 by 31 pixels (shaded red in figure 35 ) an average value is calculated for both the small and large areas.the areas then scan across the whole array so that every pixel is evaluated. due to the nature of the test, only the red pixels are used. the next stage of the test is the creation of a pixel map with the coordinates of the failing pixels. a pixel location is identified as a fail in the map if it satisfies the criteria outlined in table 26 below. figure 35: test area definition
defect categorisation VV6501 56/60 the contents of the fail map determine whether the sensor fails the physical aberration test. the fail criteria are given in ta bl e 2 7 below: table 26: criteria for pixel to be entered in failure map pixel location is a fail in map if small average < large average - (1.2% of large average) or small average > large average + (1.2% of large average) table 27: physical aberration test fail criteria fail physical aberration test if > 82 contiguous a pixel entries in the failure map a. an example of contiguous pixels entries is given in figure 36 figure 36: contiguous pixels example the group of pixels enclosed in the circle are contiguous, that is every pixel in the group is attached to at least one neighboring pixel. the other pixel entries shown in the figure are non contiguous as they have no touching neighbors.
57/60 VV6501 package mechanical data 9 package mechanical data notes: 1. gold plate 0.3 m minimum over 1.27 ~ 8.89 m nickel 2. seal area and die attach area shall not be without metallization 3. all tolerances are 0.13 unless otherwise specified option k option n a 1.549 0.161 1.54 0.16 b 0.571 0.05 (0.62) c 0.546 0.05 0.51 0.05 d 0.432 0.05 0.41 0.03 +0.20 10.67 - 0.13 no 1 no 36 (r0.30) [4x] (r0.30) [4x] [p = 1.016 x 8] 8.128 0.13 1.016 0.08 (r 0.15) [x 4] [36 x] 0.51 0.08 [4x] 0 .5 1 (0.51) no. 1 index [36x] 0.89 0.15 (r0.15) [36x] no 36 no1 1.910.15 0.08 0.08 a a [at s/r] 0.08 note 2 0.55 0.05 c b a d 8.64 0.13 7.37 0.13
design-in information VV6501 58/60 10 design-in information 10.1 basic support circuit 10.2 transistor choice the ztx749 has a high min. h fe (lower on-chip current). it is also inexpensive and has good heat dissipation. 10.3 pin 1 and image orientation please note that for the sensor array to produce a correctly aligned image, pin 1 should be located at the top rather than 180 degrees rotated at the bottom (see figure 3 ). figure 37 : basic support circuit VV6501 video audio digital 6 7 8 9 10 11 12 13 14 porb suspend clkin 15 16 17 18 19 20 21 22 23 fst qclk d0 d1 d2 d3 d4 24 25 26 27 28 29 30 31 32 n/c n/c audoutp audoutn 33 34 35 36 1 2 3 4 5 pdvreg1v8 6.8nf 10uf 10uf 2.2uf 470nf 100nf 2k2 2.2 uf 100nf 1uf 3v3 4k7 4k7 sda 1v8 3v3 5v0 scl stmicroelectronics advises the use of a grounding star point. all decoupling capacitors should be placed as close to sensor as possible. the support circuit outlined above describes a usb based system with a nominal 5v supplying the device. audref a suitable choice for the bipolar transistor would be a ztx749. it satisfies the technical specification and is very cost effective.
59/60 VV6501 evaluation kits 11 evaluation kits evaluation kits are available to demonstrate the VV6501 sensor technology. the sensor can be demonstrated using the pci card based standard evaluation kit stv-evk-e01. a daughter card kit is also available to purchase separately. the daughter card is a simple pcb on which the sensor is mounted. the daughter card can then be plugged into the main evaluation kit pcb. the evaluation kit is supplied with supporting software that enables the customer to program the sensor via an i 2 c interface. table 28: ordering details part number description stv-evk-e01 sensor only evaluation kit for VV6501c001 stv-6501c- d01 sensor daughter card for VV6501c001
60/60 VV6501 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this p ublication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicr oelectronics. the st logo is a registered trademark of stmicroelectronics ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies austalia - brazil - canada - china - finland - france - germany - hong kong - india - israel -italy - japan - malaysia - malta- morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com

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