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  1995 application note software basics m pd784026 subseries m pd784915 subseries document no. u10095ej1v0an00 (1st edition) date published november 1995 p printed in japan 78k/iv series 16-bit single-chip microcomputer
the information in this document is subject to change without notice. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: standard, special, and specific. the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices in standard unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact nec sales representative in advance. anti-radioactive design is not implemented in this product. m7 94.11 the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative.
preface target users this application note is for engineers who wish to understand 78k/iv series devices and design application programs using these devices. 78k/iv series ? m pd784026 subseries: m pd784020, 784021, 784025, 784026, 78p4026 ? m pd784915 subseries: m pd784915 note , 78p4916 note note under development objective the purpose of this application note is to use program examples to help users to understand the basic functions of 78k/iv series devices. the program and hardware structures published here are illustrative examples and are not designed for mass production. organization this application note describes the basic numeric operation programs. application area the 78k/iv series devices have a 1-mb program memory space and are capable of high-speed instruction execution and low-voltage operation, making them suitable for a wide range of applications, including the following: ? portable telephones ? vcrs ? cd-roms ? printers ? hdds ? audio systems, etc. ? cameras legend the symbols and notations used in this manual have the following meanings: significance of the data description: the left side is high-order data and the right side is low-order data. active-low description : xxx (line above pin and signal names) note : explanation of the note attached to the text caution : contents that should be read carefully remark : supplemental explanation of the text number descriptions : binary numbers ... xxxxxxxxb : decimal numbers ... xxxx : hexadecimal numbers ... xxxxh easily confused characters : 0 (zero), o (oh) : 1 (one), l (lowercase letter), i (uppercase letter)
special function register (sfr) description do not attempt to enter a combination of codes indicated in setting prohibited in the register charts provided throughout this document. example of special function register (sfr) description remark throughout this application note, those register bits that must be set are indicated by shading. when using a register, refer to the provided example as necessary. edc * * 10 xx * * 10 this bit is set according to the operationto be performed. set according to the function used. bits marked ** are set to either 0 or 1. set this bit to 1. set this bit to 0. this bit is 0 or 1 when read. set this bit to 0 or 1. operation is not affected regardless of whether this bit is set to 0 or 1. read operation write operation special function register name stbc stp hlt 01 10 00 11 ck1 ck0 00 01 10 11 selection of internal system clock example operation mode normal operation mode halt mode stop mode idle mode f xx /2 (12.5 mhz) f xx /4 (6.25 mhz) f xx /8 (3.125 mhz) f xx /16 (1.5625 mhz) (f xx = 25 mhz) 0 0 ck1 ck0 x 0 stp hlt 0001000 0 76543210
related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. ? documents common to 78k/iv series devices document name document number japanese english users manual, instruction ieu-844 ieu-1386 application note, software basics this manual instruction table iem-5580 instruction set iem-5572 78k series selection guide if-258 if-1141 development tool selection guide ef-219 ef-1111 ? individual documents m pd784026 subseries document name document number japanese english m pd784020, 784021 data sheet ic-8776 ip-3234 m pd784025, 784026 data sheet ic-8722 ip-3230 m pd78p4026 data sheet ic-8734 ip-3231 m pd784026 subseries special function register table iem-5579 m pd784026 subseries users manual, hardware ieu-850 ieu-1379 m pd784026 subseries application note, hardware basics in preparation m pd784915 subseries document name document number japanese english m pd784915 product information ip-9130 m pd78p4916 product information ip-9178 m pd784915 subseries special function register table iem-5602 m pd784915 subseries users manual, hardware ieu-850 caution the related documents described above may be changed without notice. always use the newest document when designing.
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- i - contents chapter 1 general .......................................................................................................................... 1 1.1 reading this document .................................................................................. 1 1.2 using application programs ....................................................................... 2 1.3 features of 78k/iv series devices ............................................................ 2 1.4 program ............................................................................................................... 3 chapter 2 binary operations .................................................................................................... 5 2.1 binary addition of signed 32 bits + 32 bits ............................................ 5 2.2 binary subtraction of signed 32 bits C 32 bits .................................. 10 2.3 binary multiplication of signed 32 bits x 32 bits ............................... 15 2.4 binary division of signed 32 bits/32 bits ................................................. 24 chapter 3 decimal operations .................................................................................................. 35 3.1 decimal addition of signed 8 digits + 8 digits .................................... 36 3.2 decimal subtraction of signed 8 digits C 8 digits ............................ 45 3.3 decimal multiplication of signed 8 digits x 8 digits ........................ 49 3.4 decimal division of signed 8 digits/8 digits .......................................... 56 chapter 4 shift processing ....................................................................................................... 65 4.1 shifting n-byte data 1 byte to the right .............................................. 65 4.2 shifting n-digit data 1 byte to the right (decimal 1/10 processing) ............................................................................. 68 chapter 5 block transfer processing ................................................................................ 71 5.1 block transfer processing of fixed byte data ............................... 71 5.2 block transfer processing of byte data ............................................ 73 5.3 block comparison (coincidence detection) of byte data ........... 75 chapter 6 data exchange processing .................................................................................. 77 6.1 converting a hexadecimal number (hex) to a decimal number (bcd) ..................................................................................... 77 6.2 converting a decimal number (bcd) to a hexadecimal number (hex) ............................................................................ 83 6.3 converting an ascii code to a hexadecimal code ........................... 89 6.4 converting a hexadecimal code to an ascii code ........................... 94 chapter 7 data processing ........................................................................................................ 99 7.1 sorting 1-byte data ........................................................................................ 99 7.2 searching for data ........................................................................................ 104
- ii - list of figures figure no. title page 2-1 expressing binary numbers .............................................................................................. 5 2-2 algorithm for binary multiplication .................................................................................... 16 2-3 algorithm for binary division ............................................................................................. 27 3-1 expressing decimal numbers ........................................................................................... 35
chapter 1 general 1.1 reading this document this application note introduces examples of programs for basic binary and decimal arithmetic operations, such as addition, subtraction, multiplication, and division, as well as data exchange and data transfer as subroutine programs. the algorithms of these programs are described so that they can be used as user programs. the program examples given in this document are presented in the following format: (1) outline of processing outlines the processing performed by the program. (2) ram area describes the ram area used by the program. note that if a work area is used as the ram area, its contents will be undefined after the program has been executed. (3) registers describes the registers used in the program. to protect the contents of registers that have already been used by another program, save the contents of those registers by switching the register bank before executing the described program. (4) input describes the arguments that must be input when executing the program. (5) output describes the arguments that are output after the program has been executed. (6) program description describes the algorithm on which the program is based. also refer to the flowchart and program listing. (7) flowchart illustrates the algorithm of the program by means of a flowchart. (8) program listing presents a listing of the program. all program listing are described as source programs. the address, therefore, differs depending on the link condition. the programs shown in this application note are provided only as examples and their actual operation is not guaranteed. 1
2 78k/iv series application note 1.2 using application programs basically, use the application programs presented in this document as specified in the description of each application program. some application programs call other application programs. in this case, link the programs by means of a linker (lk78k/iv) and by referring to the description. a work area may also be necessary. reserve a ram area according to the description and make a public declaration. 1.3 features of 78k/iv series devices as the functions of microcomputer-based products have improved and their cost fallen, the demand for microcomputers that can satisfy these mutually contradicting requirements more sophisticated functions at lower cost has steadily increased. in addition, with the explosive growth in portable systems such as cellular telephones, the demand for microcomputers that can operate at lower voltages while dissipating less power has also grown. necs 78k/iv series of 16-bit single-chip microcomputers was developed in response to these market demands. the features of the 78k/iv series of microcomputers are as follows: (1) compatibility with existing models the 78k/iv series microcomputers maintain, at source level, upward compatibility with the 8-bit models (78k/0, 78k/i, and 78k/ii series) and 16-bit models (78k/iii series) of the 78k series, thus protecting your investment in software. (2) wide linear memory space up to 1 mb of program memory and 16 mb of data memory are supported. (3) low voltage, low current dissipation the operating voltage ranges from 2.7 to 5.5 v, so that 78k/iv series devices can operate at very low voltages. in addition, three standby modes, stop, idle, and halt, and a function for dividing the clock to be supplied to the cpu are provided to enable power management according to the operating status. (4) high-speed multiplication and division instructions high-speed multiplication and division instructions are provided to support complicated control systems and high-accuracy control algorithms. 8 bits x 8 bits = 16 bits (unsigned) C> 0.69 m s 16 bits x 16 bits = 32 bits (unsigned) C> 0.94 m s 16 bits x 16 bits = 32 bits (signed) C> 0.88 m s 16 bits/8 bits = 16-bit quotient, 8-bit remainder (unsigned) C> 1.06 m s 32 bits/16 bits = 32-bit quotient, 16-bit remainder (unsigned) C> 1.94 m s (with internal 16-mhz clock)
3 chapter 1 general (5) powerful interrupt response for control applications, the way in which a microcomputer responds to an interrupt is particularly important. the 78k/iv series supports the following three interrupt functions: ? vector interrupt ? context switching ? macro service (6) support of high-level language (c) an enhanced instruction set for a c compiler, an efficient c compiler, and easy-to-use source debugging environments are supported. (7) easy-to-use tools easy-to-use tools, such as an assembler package, c compiler, in-circuit emulator, and integrated debugger are also supported. 1.4 program some example programs presented in this application note require that the results of operations and numeric data be written into ram. when referring to the programs in this application note, therefore, reserve the necessary amount of ram by using the program below. when using programs that perform binary division, decimal addition, decimal subtraction, and decimal division, add the processing to be performed in the case of an error, as necessary. public bmlcnd, bmlier, bufram, brslt ; binary multiply public dend, dvisor, drmnd ; binary division public dmlcnd, dmlier, drslt, carry ; decimal multiply public divsor, divind, rmind ; decimal division public sflag public errflag ; error flag bseg sflag dbit ; sin flag errflag dbit ; error flag workseg dseg saddr ;-------------------------------------------------------- ; binary multiply area ;-------------------------------------------------------- bmlcnd: ds 4 bmlier: ds 4 bufram: ds 15 brslt: ds 8
4 78k/iv series application note ;-------------------------------------------------------- ; binary division area ;-------------------------------------------------------- dend: ds 4 dvisor: ds 4 drmnd: ds 4 ;-------------------------------------------------------- ; decimal multiply area ;-------------------------------------------------------- dmlcnd: ds 4 dmlier: ds 4 drslt: ds 8 carry: ds 1 ;-------------------------------------------------------- ; decimal division ;-------------------------------------------------------- divsor: ds 4 divind: ds 4 rmind: ds 4 cseg ? ? bt errflag, $error ; if(error flag=1) then ? ; go to error ? error: ; error routine ? ? ; error processing. prepare as ; necessary.
chapter 2 binary operations in binary operations, the most significant bit is used as a sign bit, the remaining bits expressing a numeric value. negative numbers are expressed as a 2s complement. figure 2-1. expressing binary numbers for binary operations, the data storage area used for the operation and the area storing the result of the operation are located in ram. 2.1 binary addition of signed 32 bits + 32 bits (1) outline of processing this section presents an example program that adds a signed 32-bit augend to a 32-bit addend, then stores the result into a 32-bit result area (shared with the augend area). (2) ram area when the sign bit is (0): positive (00000000h through 7fffffffh) when the sign bit is (1): negative (ffffffffh through 80000000h) (3) registers ax, c, vp, tde, and whl registers msb lsb sign bit 1 byte + 32 bits 32 bits 32 bits whl lsb lsb tde whl+3 msb msb tde+3 addend area sign bit {0: positive, 1: negative} augend area, result area (shared) 5
6 78k/iv series application note (4) input set the following addresses in the whl and tde registers. whl: lowest address of the ram area containing the 32-bit augend tde : lowest address of the ram area containing the 32-bit addend (5) output the following contents are stored into the 4-byte ram area indicated by the whl register. whl to whl+3: stores the result of addition. (6) program description (a) sets the number of words to be manipulated in a counter (c register). (b) clears the carry flag (cy) to 0 in advance. (c) reads the 2 bytes from the addend area indicated by the addend address (tde register) into the ax register, and increments the added register (tde register). (d) adds the 2 bytes in the augend area, indicated by the augend register (whl register), into the ax register. (e) stores the value in the ax register into the ram area indicated by the augend address (whl register), and increments the augend address (whl register). (f) decrements the counter (c register). when the value of the counter reaches 0, ends addition processing. (g) if a carry has occurred as a result of the addition, reads the data of the high-order 2 bytes in the result area indicated by the next augend address (whl register) into the ax register, and adds the 1 of the carry. (h) stores the value in the ax register into the result area indicated by the augend address (whl register), then continues processing from step (c).
7 chapter 2 binary operations (7) flowchart bfxadd cy 8 78k/iv series application note (8) program listing ? description of the label used for executing of application routine augne: lowest address of the ram area containing the 32-bit augend that stores the 32-bit result (shared) adden: lowest address of the ram area containing the 32-bit addend ? example program listing for main routine ? ? movg whl, #augne ; movg tde, #adden ; call !bfxadd ; data a+b subrutin ? ? remark set the whl and tde registers as shown above, then call the subroutine.
9 chapter 2 binary operations ? program listing for this application routine name bfxadr ;******************************************************* ;* binary addition * ;* 32 bit 10 78k/iv series application note 2.2 binary subtraction of signed 32 bits C 32 bits (1) outline of processing this section presents an example program that subtracts a 32-bit subtrahend from a signed 32-bit minuend and stores the result into a 32-bit result area (shared with the minuend area). (2) ram area when the sign bit is (0): positive (00000000h through 7fffffffh) when the sign bit is (1): negative (ffffffffh through 80000000h) (3) registers ax, c, vp, tde, and whl registers (4) input set the following addresses in the whl and tde registers. whl: lowest address of the ram area containing the 32-bit minuend tde : lowest address of the ram area containing the 32-bit subtrahend (5) output the following contents are stored into the 4-byte ram area indicated by the whl register. whl to whl+3: stores the result of the subtraction. 32 bits 32 bits 32 bits whl lsb lsb tde whl+3 msb msb tde+3 subtrahend area sign bit {0: positive, 1: negative} minuend area, result area (shared)
11 chapter 2 binary operations (6) program description (a) sets the number of words to be manipulated in a counter (c register). (b) sets the data for subtraction in the subtrahend and minuend areas. (c) clears the carry flag (cy) to 0 in advance. (d) reads the 2 bytes from the subtrahend area indicated by the subtrahend address (tde register) into the ax register, and increments the subtrahend address (tde register). (e) subtracts the 2 bytes in the minuend area, indicated by the minuend address (whl register), from the ax register. (f) stores the value of the ax register into the result area indicated by the minuend address (whl register), and increments the minuend address (whl register). (g) decrements the counter (c register). when the value of the counter reaches 0, ends subtraction processing. (h) if a borrow has occurred as a result of the subtraction, reads the data of the high-order 2 bytes indicated by the next minuend address (whl register) into the ax register, and subtracts the 1 of the borrow. (i) stores the value in the ax register into the result area indicated by the minuend address (whl register), then continues processing from step (d).
12 78k/iv series application note (7) flowchart bfxsub cy 13 chapter 2 binary operations (8) program listing ? description of the label used for executing of application routine minu: lowest address of the ram area containing the 32-bit minuend that stores the 32-bit result (shared) subt: lowest address of the ram area containing the 32-bit subtrahend ? example of program listing for main routine ? ? movg whl, #minu ; movg tde, #subt ; call !bfxsub ; data aCb subrutin ? ? remark set the whl and tde registers as shown above, then call the subroutine.
14 78k/iv series application note ? program listing for this application routine name bfxsbr ;******************************************************* ;* binary subtraction * ;* 32 bit 15 chapter 2 binary operations 2.3 binary multiplication of signed 32 bits x 32 bits (1) outline of processing this section presents an example program that multiplies a signed 32-bit multiplicand by a 32-bit multiplier, and stores the result into a 64-bit result area. (2) ram area when the sign bit is (0): positive (00000000h through 7fffffffh) when the sign bit is (1): negative (ffffffffh through 80000000h) (3) registers a, x, b, c, vp, tde, whl, rp2, and r4 registers (4) input set the data necessary for the operation into the following 4-byte ram areas. bmlcnd to bmlcnd+3 : 32-bit multiplicand data bmlier to bmlier+3 : 32-bit multiplier data (5) output the following contents are stored into the following 8-byte ram area. brslt to brslt+7: result of multiplication x 64 bits 32 bits 32 bits msb lsb bmlcnd +3 bmlcnd +2 bmlcnd +1 bmlcnd +0 bmlier +3 msb lsb bmlier +2 bmlier +1 bmlier +0 bufram +4 bufram +f msb bufram +3 bufram +2 bufram +1 bufram +0 lsb lsb brslt +4 brslt +3 brslt +2 brslt +1 brslt +0 brslt +7 msb result area sign bit {0: positive, 1: negative} multiplicand area multiplier area work area sign bit {0: positive, 1: negative}
16 78k/iv series application note (6) program description figure 2-2 illustrates the algorithm for binary multiplication using the 16-bit multiplication instruction. figure 2-2. algorithm for binary multiplication remark cy: carry flag processing 4 adds the carry flag (cy) that has been generated as a result of the operation on the lower digit. (iv) (iii) (ii) (i) +3 +2 +1 +0 +3 +2 +1 +0 iv iii ii i gf e d cb a i cy + g = iv cy + d + e + f = iii cy + a + b + c = ii brslt result area (brslt) cy retained cy retained work area (bufram) processing 4 work area (bufram) values are exchanged processing 3 result of (ii) x (iv) ? result of (ii) x (iii) ? result of (i) x (iv) ? result of (i) x (iii) ? processing 2 multiplier area (bmlier) multiplicand area (bmlcmd) processing 1 <4> <3> <2> <1> <8> <7> <6> <5> <9> <12> <11> <10> <13> <16> <15> <14> <1> <4> <3> <2> <5> <8> <7> <6> <9> <12> <11> <10> <13> <16> <15> <14> <1> <4> <3> <2> <5> <10> <9> <6> <7> <12> <11> <8> <13> <16> <15> <14> +f +e +d +c +b +a +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +f +e +d +c +b +a +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +7 +6 +5 +4 +3 +2 +1 +0
17 chapter 2 binary operations the processing performed by this program is as follows: (a) takes the absolute values of the multiplier and multiplicand. if the signs of the multiplier and multiplicand differ, sets the sign identification flag (sflag) to 1. if the signs are the same, clears the flag to 0. (b) sets the multiplication end flag (lflag) to 1. (lflag = 1: multiplication does not end, lflag = 0: multiplication ends) (c) sets 0 to indicate the lowest address by using the b register as the address pointer to the multiplicand area. processing 1 (d) sets the lowest address of the work area in the tde register and the lowest address of the multiplier area in the whl register. (e) reads the 2-byte multiplier indicated by the whl register into the vp register, and saves its contents in preparation for the operation performed on the next digit. (f) reads the 2-byte multiplicand, indicated by the address pointer (b register) in the multiplicand area, into the ax register, multiplies it by the multiplier stored in the vp register, then stores the result into the work area indicated by the tde register, 4 bytes at a time. (g) adds 2 to the b register, and increments the address pointer of the multiplicand area by 2 bytes. (h) compares the value of the address pointer (b register) in the multiplicand area with the number of digits (4) in the multiplicand area to determine whether the two values are the same. processing 2 if the values are found to be different, restores the value of the multiplier saved to the vp register in step (e) to multiply the multiplicand of the next digit, and returns to step (g). steps (g) through (i) are repeated until the values are the same. (i) sets 0, to indicate the lowest address, into the address pointer (b register) of the multiplicand area. (j) judges whether all multiplications have been completed, by referencing the multipli- cation end flag (lflag). if multiplication has not yet been completed, clears the multiplication end flag (lflag) to 0, returns to step (e), then repeats the processing up to step (j). processing 3 (k) exchanges the contents of work areas bufram+6 and bufram+7, and bufram+8 and bufram+9, in which the multiplication result is stored. (l) stores the values of bufram+0 and bufram+1 into the first and second bytes of the result area (brslt). (m) adds the values of bufram+2 through bufram+7 with the carry flag (cy), 2 bytes at a time, then stores the result into the third and fourth bytes of the result area (brslt). (n) adds the values of bufram+8 through bufram+0dh with the carry flags (cy), 2 bytes at a time, then stores the result into the fifth and sixth bytes of the result area (brslt). processing 4 (o) adds the contents of bufram+0eh and bufram+0fh with the carry flags (cy), then stores the result into the seventh and eighth bytes of the result area (brslt). (p) if the sign identification flag (sflag) is 1, takes the 2s complement of the multipli- cation result as the result.
18 78k/iv series application note remark steps 1 through 4 correspond to the numbers shown in figure 2-2 . (7) flowchart bfmul no yes bfmul1: no yes yes no yes no bfmul2: bfmul3: bfmul4: clears multiplication end flag (lflag) to 0 clears sign identification flag (sflag) to 0 multiplicand < 0 multiplicand 19 chapter 2 binary operations bfmul6: bfmul7: bfmul8: no yes no yes no yes compl comp1 comp2: no yes ret exchanges bufram+6 and bufram+7, and bufram+8 and bufram+9 sets address of multiplication result work area bufram+2 in whl register sets address of multiplication result ram area brslt+2 in tde register initializes multiplication end flag (lflag) lflag 20 78k/iv series application note (8) program listing ? description of label used for executing the application routine bmlcnd : lowest address of the ram area containing the 32-bit multiplicand bmlier : lowest address of the ram area containing the 32-bit multiplier bufram : lowest address of the work area that temporarily contains the 15-byte multiplication result brslt : lowest address of the ram area that contains the final multiplication result sflag : sign identification flag sflag = 0 ... same signs sflag = 1 ... different signs lflag : multiplication end flag lflag = 0 ... multiplication has ended lflag = 1 ... multiplication has not ended ? example program listing for main routine ? ? movw bmlcnd , #02h movw bmlcnd+2 , #00h movw bmlier , #08h movw bmlier+2 , #15h ; call !bfmul ? ? remark set the multiplicand and multiplier as shown above, then call the subroutine.
21 chapter 2 binary operations ? program listing for this application routine name bfmulr ;********************************************************* ;* binary multiplication * ;* input condition * ;* multiplicand 22 78k/iv series application note ; *** word multiplication process *** ; bfmul2: set1 lflag ; mov b, #0 ; mult loop number clear movg tde, #bufram ; tde-reg. bufram+8, bufram+9 movg whl, #bufram+2 ; movg tde, #bmslt+2 ; set1 lflag ; movw rp2, #00h ; movw brslt, bufram ; answer of lower set bfmul6: movw vp, rp2 ; movw rp2, #0 ; mov b, #3 ; add number set
23 chapter 2 binary operations bfmul7: movw ax, [whl+] ; addw vp, ax ; add addc r4, #0 ; dbnz b, $bfmul7 ; xchw ax, vp ; bmslt+ 24 78k/iv series application note 2.4 binary division of signed 32 bits/32 bits (1) outline of processing this section presents an example program that divides a signed 32-bit dividend by a 32-bit divisor and stores the result into a 32-bit result area. (2) ram area when the sign bit is (0): positive (00000000h through 7fffffffh) when the sign bit is (1): negative (ffffffffh through 80000000h) caution the dividend and quotient (dend+3, ..., dend), and remainder (drmnd+3, ..., drmnd) areas must all be 8-byte contiguous ram areas. (3) registers a, x, b, c, tde, and whl registers (4) input set the data necessary for the operation into the following 4-byte ram areas. dend to dend+3 : 32-bit dividend data dvisor to dvisor+3 : 32-bit divisor data remainder quotient 32 bits 32 bits 32 bits 32 bits msb drmnd +3 drmnd +1 drmnd +0 msb dend +3 dend +1 dend +0 lsb lsb dvisor +0 dvisor +1 dvisor +3 msb lsb divisor area sign bit {0: positive, 1: negative} remainder area dividend area, quotient area (shared) sign bit {0: positive, 1: negative} sign bit {0: positive, 1: negative}
25 chapter 2 binary operations (5) output the status of the division processing is indicated by setting the following flag. errflag: error flag errflag = 0 ... no error has occurred (division has been completed normally) errflag = 1 ... an error has occurred (division cannot be executed because the divisor is 0) the 4-byte ram areas are used to store the results shown. dend to dend+3 : stores the quotient resulting from the division note drmnd to drmnd+3: stores the remainder resulting from the division note note the values before the operation are retained as these values if the error flag (errflag) = 1. remark the main routine checks the error flag (errflag). add error processing as necessary. (6) program description this program uses a subtract and return method as the algorithm for binary division. this algorithm is illustrated below. ? algorithm of division by subtract and return method <1> q y { x if x 3 0 then q q y { } in <3> through <6> is repeated n times. <8> as a result, the quotient is stored into q and the remainder is stored into x. remark the meanings of the above symbols are as follows. q: quotient area x : dividend area y : divisor area m: number of digits in dividend n : number of digits in divisor
26 78k/iv series application note ? example of binary division (4 bits/4 bits) using the subtract and return method example 14/3 = quotient: 4, remainder: 2 (the following expression is in binary.) 1110 11 ? 1 100 0010 11 100 11 + 010 11 1 11 + 10 because the result is negative, the number subtracted is added to restore the original number. remainder = 2 quotient = 4
27 chapter 2 binary operations ? algorithm for binary division (32 bits/32 bits) performed by this program figure 2-3. algorithm for binary division +3 +2 +1 +0 +3 +2 +1 +0 +3 +2 +1 +3 +0 processing 1 ? repeats above processing by 32 bits remainder area (drmnd) (ii) quotient area (dend) (i) if result of "remainder area (ii') - divisor area (iii)" is divisor area (dvisor) (iii) 1-bit shift dividend area, quotient area (dend) (i) remainder area (drmnd) (ii) ?clears remainder area to 0. ?shifts contents of remainder and dividend areas 1 bit to left, as shown below. processing 3 processing 2 (ii') (i') (iii) i + 1 ii' + iii ?positive: increments quotient area (i). ?negative: performs "remainder area (ii') + divisor area (iii)" to restore original value.
28 78k/iv series application note the processing performed by this programs is explained below. processing 1 C> (a) determines whether the value of the divisor area is 0. if 0, sets the error flag (errflag) to 1, then ends the operation, with only information indicating the occurrence of an error remaining. (errflag = 0 ... no error has occurred, errflag = 1 ... an error has occurred) (b) clears the remainder area to 0. (c) takes the absolute values of the dividend and divisor areas. if either of the values in the dividend and divisor areas is negative, sets the quotient sign flag (quoflag) to 1. (quoflag = 0 ... sign of quotient is positive, quoflag = 1 ... sign of quotient is negative) sets the remainder sign flag (remflag) to 1 if the value of the dividend area is negative. (remflag = 0 ... sign of remainder is positive, remflag = 1 ... sign of remainder is negative) (d) uses the b register as a bit counter that counts the number of bits in the dividend area, then sets the number of bits (32) in the dividend area in this counter. processing 2 C> (e) shifts the remainder area and dividend area (8-byte contiguous area) 1 bit to the left. processing 3 C> (f) executes remainder area 29 chapter 2 binary operations (7) flowchart bfdiv yes no ret coml 1 1 bfdiv5: no yes bfdiv8: no yes no yes compl bfdiv9: no yes compl bfdiv11: ret clears error flag (errflag) to 0 divisor = 0 clears remainder area (drmnd to drmnd+3) to 0 dividend 30 78k/iv series application note (8) program listing ? description of label used for execution of application routine dend : lowest address of the ram area containing the 32-bit dividend and 32-bit quotient (shared) drmnd : lowest address of the ram area containing the 32-bit remainder that results from division divsor : lowest address of the ram area containing the 32-bit divisor bytnum : number of bytes in the remainder area (used to clear the remainder area to 0) quoflag : quotient sign flag quoflag = 0 ... sign of quotient is positive quoflag = 1 ... sign of quotient is negative remflag : remainder flag remflag = 0 ... sign of remainder is positive remflag = 1 ... sign of remainder is negative errflag : error flag errflag = 0 ... an error has not occurred errflag = 1 ... an error has occurred ? example of program listing for main routine ? ? movw dend, #00 ; data a movw dend+2, #32 ; movw dvisor, #00 ; data b movw dvisor+2, #08 ; call !bfdiv ; data a/b subroutine bt errflag, $error ; br $$ ; error: clr1 errflag ; clear error flag ? ? remark set the dividend and divisor as shown above, then call the subroutine.
31 chapter 2 binary operations ? program listing for this application routine name bfdivr ;******************************************************* ;* binary division * ;* 32 bit 32 78k/iv series application note ; ; **** complement convert **** ; clr1 remflag ; clear remainder sign-flag clr1 quoflag ; clear quotient sign-flag bf dend+3.7, $bfdiv3 movg whl, #dend ; whl-register 33 chapter 2 binary operations ; ; **** if borrow divisor + dividend **** ; bfdiv7: movg tde, #dvisor ; tde 34 78k/iv series application note [memo]
lsb msb 1 digit of decimal number 1 byte sign bit chapter 3 decimal operations in decimal operations, the most significant bit is used as a sign bit, the remaining bits expressing a numeric value, as shown in figure 3-1. decimal numbers are expressed as bcd codes. figure 3-1. expressing decimal numbers for decimal operations, the data storage area used for the operation and the area storing the result of the operation are located in ram. 35
36 78k/iv series application note 3.1 decimal addition of signed 8 digits + 8 digits (1) outline of processing this section presents an example program that adds a signed 8-digit augend to an 8-digit addend, then stores the result into an 8-digit result area (shared with the augend area). (2) ram area when the sign bit is (0): positive (0 through 79999999) when the sign bit is (1): negative (C1 through C79999999) (3) registers a, c, b, tde, and whl registers (4) input set the following addresses in the whl and tde registers. whl: lowest address of the ram area containing the 8-digit (4-byte) augend tde : lowest address of the ram area containing the 8-digit (4-byte) addend (5) output the status of the division processing is indicated by the following flag. errflag: error flag errflag = 0 ... an error has not occurred (addition was completed normally) errflag = 1 ... an error has occurred (addition cannot be executed because an overflow or underflow occurred) + 8 digits 8 digits 8 digits whl lsb lsb tde whl+3 tde+3 msb msb sign bit {0: positive, 1: negative} addend area 1 digit of decimal number (4 bits) augend area, result area (shared) 1 byte
37 chapter 3 decimal operations the following contents are stored into the 4-byte ram area indicated by the whl register. whl to whl+3: stores the result of the addition note note when the error flag (errflag) = 1, the 4-byte value in the whl register will be undefined. remarks 1. the operation range is C79999999 to 79999999. 2. the error flag (errflag) is identified by the main routine. add error processing as necessary. (6) program description this program performs addition if the signs of the addend and augend are the same; if not, it performs subtraction. (a) sets the number of bytes for decimal addition in the c counter (c register). (b) if the signs of the addend and augend are different, jumps to step (o). (c) clears the carry flag (cy) and sign identification flag (sflag) to 0. (d) reads 1 byte of the augend area indicated by the augend address (whl register) into the a register. (e) adds the 1 byte of the addend area, indicated by the addend address (tde register), to the a register with the carry flag (cy), and increments the addend address (tde register). converts the result of the operation to a decimal number, stores it into the result area indicated by the augend address (whl register), then increments the augend address (whl register). (f) decrements the counter (b register), then repeats steps (d) through (e) until the value of the counter reaches 0. (g) reads 1 byte from the augend area indicated by the augend address (whl register) into the a register. (h) adds 1 byte of the addend area, indicated by the addend address (tde register) into the a register with the carry flag (cy). (i) jumps to step (k) if the carry flag (cy) is 0. (j) sets the sign identification flag (sflag) to 1, then clears the carry flag (cy) to 0. (k) converts the value of the a register to a decimal number. (l) if the carry flag (cy) is 1, or if the seventh bit of the a register is 1, an overflow occurs. in this case, sets the error flag (errflag) to 1 and terminates the operation. (m) sets the seventh bit of the a register into 1 if the sign identification flag (sflag) is 1. (n) stores the contents of the a register into the result area indicated by the augend address (whl register), then terminates the operation. (o) makes the subtrahend positive, then clears the sign identification flag (sflag) to 0. (p) if the minuend is negative, makes the minuend positive, then sets the sign identification flag to 1. (q) clears the carry flag (cy) to 0. (r) reads 1 byte in the minuend area, indicated by the minuend address (whl register), into the a register. (s) subtracts 1 byte in the subtrahend area, indicated by the subtrahend address (tde register), from the a register with the carry flag (cy), and increments the subtrahend address (tde register). converts the result of the operation to a decimal number, stores it into the result area indicated by the minuend address (whl register), then increments the minuend address (whl register).
38 78k/iv series application note (t) decrements the counter (c register), then repeats steps (r) and (s) until the value of the counter reaches 0. (u) jumps to step (w) if the carry flag (cy) is 0. (v) takes the 10s complement of the result and inverts the sign identification flag (sflag). (w) terminates the operation if the result is 0. (x) jumps to step (y) if the sign identification flag (sflag) is 1; if the flag is 0, terminates the operation. (y) sets the sign bit of the result to 1, then terminates the operation. remark for the decimal subtraction routine (steps (o) through (y)), the augend area is replaced by the minuend area, while the addend area is replaced by the subtrahend area. (7) flowchart bcdadd bcdad2 no yes dadds dsubs ret c 39 chapter 3 decimal operations dadds dadds1: no yes no yes dadds3: yes no yes no yes no dadds6: ret dsubs no yes dsubs1: dsubs2: no yes no yes dsubs5: yes no no yes dsubs6: ret cy = 1 a.7 = 1 cy = 1 cy = 1 c = 0 b = 0 sets error flag (errflag) to 1 appends negative sign to result sign identification flag (sflag) = 1 result = 0 converts result to decimal number and inverts sign identification flag (sflag) converts result to decimal num- ber and stores to result area c 40 78k/iv series application note (8) program listing ? description of label used for executing the application routine bcdaug : lowest address of the ram area containing the 8-digit (4-byte) augend and 8-digit result (shared) bcdade : lowest address of the ram area containing the 8-digit (4-byte) addend sflag : sign identification flag sflag = 0 ... same signs sflag = 1 ... different signs errflag: error flag errflag = 0 ... no error has occurred errflag = 1 ... an error occurred ? example of program listing for main routine ? ? movg whl, #bcdaug ; movg tde, #bcdade ; call !bcdadd ; bt errflag, $error ; br $$ ; error: clr1 errflag ; clear error flag ? ? remark set the whl and tde registers as shown above, then call the subroutine. prepare and add error processing as necessary.
41 chapter 3 decimal operations ? program listing for this application routine name bcdadr ;******************************************************* ;* decimal addition * ;* 8 digit 42 78k/iv series application note ;====================================================== ; ***** decimal addition subroutine ***** ;====================================================== dadds: clr1 cy clr1 sflag ; clear sign-flag dadds1: mov a, [whl] addc a, [tde+] adjba ; decimal adjust mov [whl+], a dbnz b, $dadds1 mov a, [whl] addc a, [tde] dadds2: bnc $dadds3 set1 sflag ; set sign-flag clr1 cy dadds3: adjba ; decimal adjust bnc $dadds4 br dadds7 dadds4: bf a.7, $dadds5 br dadds7 dadds5: bf sflag, $dadds6 set1 a.7 dadds6: mov [whl], a br edadds dadds7: set1 errflag ; set error flag edadds: ret
43 chapter 3 decimal operations ;====================================================== ; ***** decimal subtraction subroutine ***** ;====================================================== dsubs: push whl ; save whl-register clr1 sflag ; clear sign-flag mov a, [tde+bytnum-1] clr1 a.7 mov [tde+bytnum-1], a mov a, [whl+bytnum-1] bf a.7, $dsubs1 clr1 a.7 mov [whl+bytnum-1], a set1 sflag ; set sign-flag dsubs1: mov b, c ; save c-register clr1 cy dsubs2: mov a, [whl] subc a, [tde+] adjbs ; decimal adjust mov [whl+], a dbnz c, $dsubs2 bnc $dsubs5 pop whl ; load whl-register push whl ; save whl-register mov c, b ; load c-register dsubs3: mov a, #99h ; (whl) 44 78k/iv series application note ; ; **** check / result = 0 **** ; dsubs5: mov c, b ; load c-register pop whl ; load whl-register movg tde, whl mov a, #0 cmpme [tde+], a bz $edsubs bf sflag, $edsubs mov a, [whl+bytnum-1] set1 a.7 ; set sign mov [whl+bytnum-1], a edsubs: ret
45 chapter 3 decimal operations 3.2 decimal subtraction of signed 8 digits C 8 digits (1) outline of processing this section presents an example program that subtracts an 8-digit subtrahend from a signed 8-digit minuend then stores the result into an 8-digit result area (shared with the minuend area). (2) ram area when the sign bit is (0): positive (0 through 79999999) when the sign bit is (1): negative (C1 through C79999999) (3) registers a, b, c, tde, and whl registers (4) input set the following addresses in the whl and tde registers. whl: lowest address of the ram area containing the 8-digit (4-byte) minuend tde : lowest address of the ram area containing the 8-digit (4-byte) subtrahend 8 digits 8 digits 8 digits whl lsb lsb tde whl+3 tde+3 msb sign bit {0: positive, 1: negative} subtrahend area 1 digit of decimal number minuend area, result area (shared) 1 byte msb
46 78k/iv series application note (5) output the status of the subtraction processing is indicated by the following flag. errflag: error flag errflag = 0 ... no error has occurred (subtraction was completed normally) errflag = 1 ... an error occurred (subtraction cannot be executed because overflow or underflow occurs) the following contents are stored into the 4-byte ram area indicated by the whl register. whl to whl+3: stores the result of subtraction note note when the error flag (errflag) = 1, the 4-byte value indicated by the whl register will be undefined. remarks 1. the operation range is C79999999 to 79999999. 2. the error flag (errflag) is identified by the main routine. add error processing as necessary. (6) program description this program performs the processing of minuend C subtrahend by converting it into minuend + (Csubtrahend). (a) sets the number of bytes for decimal subtraction into the c counter (c register). (b) inverts the sign bit of the subtrahend area. (c) performs decimal addition by using the minuend and subtrahend areas as the augend and addend areas. remark for details of the bcdad2 subroutine (including the processing for setting the error flag (errflag) to 1), see section 3.1 . the operation error processing is included in the main routine. prepare and add error processing as necessary.
47 chapter 3 decimal operations (7) flowchart (8) program listing ? description of label used for executing the application routine bcdmin : lowest address of the ram area containing the 8-digit (4-byte) minuend and 8-digit result (shared) bcdsut: lowest address of the ram area containing the 8-digit (4-byte) subtrahend ? example program listing of main routine ? ? movg whl, #bcdmin movg tde, #bcdsut call !bcdsub bt errflag, $error ; br $$ ; error: clr1 errflag ; clear error flag ? ? remark set the whl and tde registers as shown above, then call the subroutine. prepare and add error processing as necessary. bcdad 2 bcdsub ret c 48 78k/iv series application note ? program listing for this application routine name bcdsur ;********************************************************* ;* decimal subtraction * ;* 8 digit 49 chapter 3 decimal operations 3.3 decimal multiplication of signed 8 digits x 8 digits (1) outline of processing this section presents an example program that multiplies a signed 8-digit multiplicand by an 8-digit multiplier, then stores the result into a 16-digit result area. (2) ram area when the sign bit is (0): positive (0 through 79999999) when the sign bit is (1): negative (C1 through C79999999) (3) registers a, x, b, c, tde, and whl registers (4) input set the data necessary for the operation into the following 4-byte ram areas. dmlcnd to dmlcnd+3: 8-digit multiplicand data dmlier to dmlier+3 : 8-digit multiplier data (5) output the following 8-byte ram area is used to store the contents shown. drslt to drslt+7: result of multiplication remark both the multiplier and multiplicand can be between C79999999 and 79999999. the operation result can be between C6399999840000001 and 6399999840000001. x 8 digits 16 digits 8 digits msb lsb dmlcnd +3 dmlcnd +2 dmlcnd +1 dmlcnd +0 dmlier +3 msb lsb dmlier +2 dmlier +1 dmlier +0 drslt +4 drslt +7 msb drslt +3 drslt +2 drslt +1 drslt +0 lsb carry sign bit {0: positive, 1: negative} number of carries work area result area multiplier area multiplicand area sign bit {0: positive, 1: negative}
50 78k/iv series application note (6) program description this program shifts the multiplier 1 digit (4 bits) to the right then loads the multiplicand into the addition counter, starting from the lowest digit, 1 digit at a time. using the addition counter, the result 51 chapter 3 decimal operations (7) flowchart bcdmlt rclr1 bcdml3: 1 bcdrs yes no bcdml5: no yes bcdml6: no yes bcdml7: bcdrs no yes yes no no yes ret b = 0 appends negative sign to result (drslt to drslt+7) to 0 conversion to absolute value multiplicand 52 78k/iv series application note (8) program listing ? description of label used for execution of application routine dmlcnd: lowest address of the ram area containing the 8-digit (4-byte) multiplicand dmlier : lowest address of the ram area containing the 8-digit (4-byte) multiplier carry : number of carries work area drslt : lowest address of the ram area used to contain the 16-digit (8-byte) result sflag : sign identification flag sflag = 0 ... same signs sflag = 1 ... different signs ? example program listing for main routine ? ? movw dmlcnd , #12h movw dmlcnd+2 , #00 movw dmlier , #54h movw dmlier+2 , #12h call !bcdmlt ? ? remark set the multiplicand and multiplier as shown above, then call the subroutine.
53 chapter 3 decimal operations ? program listing for this application routine name bcdmlr ;********************************************************* ;* decimal multiplication * ;* 16 digit 54 78k/iv series application note bcdml3: movg whl, #dmlier+3 mov c, #4 ; c-register 55 chapter 3 decimal operations ; dbnz b, $bcdml3 ; ; **** check / multiply = 0 **** ; movg tde, #drslt mov c, #8 mov a, #0 bcdml8: cmpme [tde+], a bz $bcdml9 ; ; **** check / sign-flag **** ; bf sflag, $bcdml9 movg whl, #drslt+7 mov a, [whl] set1 a.7 mov [whl], a bcdml9: ret
56 78k/iv series application note 3.4 decimal division of signed 8 digits/8 digits (1) outline of processing this section presents an example of a program that divides a signed 8-digit dividend by an 8-digit divisor, then stores the result into an 8-digit result area, and the remainder into an 8-digit remainder area. (2) ram area caution the dividend and quotient areas (divind, ..., divind+3) and remainder area (rmind, ..., rmind+3) must all be contiguous 8-byte ram areas. when the sign bit is (0): positive (0 through 79999999) when the sign bit is (1): negative (C1 through C79999999) (3) registers a, x, b, c, tde, and whl registers remark when the x register takes the absolute value of the dividend or divisor, the following bits of the register are used as flags. ? quoflag: bit 0 of x register is used as quotient sign flag ? remflag: bit 1 of x register is used as remainder sign flag (4) input set the data necessary for the operation into the following 4-byte ram areas. divind to divind+3 : 8-digit dividend data divsor to divsor+3: 8-digit divisor data remainder quotient 8 digits 8 digits 8 digits 8 digits msb lsb msb lsb lsb msb divsor +0 divsor +1 divsor +3 divind +0 divind +1 divind +3 rmind +0 rmind +1 rmind +3 sign bit {0: positive, 1: negative} remainder area dividend area, quotient area (shared) divisor area sign bit {0: positive, 1: negative} sign bit {0: positive, 1: negative}
57 chapter 3 decimal operations (5) output the status of the division processing is indicated by the following flag. errflag: error flag errflag = 0 ... no error has occurred (division was completed normally) errflag = 1 ... an error occurred (division cannot be executed because the divisor is 0) the following contents are stored into the following 4-byte ram areas. divind to divind+3 : quotient resulting from division operation note rmind to rmind+3 : remainder resulting from division operation note note these values will be the same as those before the operation if the error flag (errflag) is set to 1. remark the value of the error flag (errflag) is determined by the main routine. add error processing as necessary.
58 78k/iv series application note (6) program description this program uses contiguous 8-byte areas as the dividend and quotient (divind, ..., divind+3), and remainder (rmind, ..., rmind+3) areas. the highest digit of the dividend is transferred to the lowest area of the remainder by shifting the dividend and remainder 1 digit to the left, while the quotient is stored into the lowest area of the dividend, 1 digit at a time. each digit of the quotient indicates the number of times the operation must be repeated until the result of remainder C divisor becomes negative. (a) identifies whether the value of the divisor area is 0. if it is 0, sets the error flag (errflag) to 1, and terminates the operation with only information indicating the occurrence of an error remaining. (errflag = 0 ... no error has occurred, errflag = 1 ... an error occurred) (b) clears the remainder area to 0. (c) obtains the absolute values of the dividend and divisor areas. if either the dividend or divisor areas is negative, sets the quotient sign flag (quoflag) to 1. (quoflag = 0 ... sign of quotient is positive, quoflag = 1 ... sign of quotient is negative) if the dividend is negative, sets the remainder sign flag (remflag) to 1. (remflag = 0 ... sign of remainder is positive, remflag = 1 ... sign of remainder is negative) (d) sets the number of bits (8) in the dividend area by using the c register as a bit counter that counts the number of bits in the dividend area. (e) shifts the remainder and quotient areas (contiguous 8-byte areas) 4 bits to the left. (f) executes the remainder area 59 chapter 3 decimal operations (7) flowchart bcddiv yes no bcddv9 rclr 1 1 bcddv5: bcddv6: bcdsub yes no yes no bcdadd bcddv7: yes no no yes no no yes bcddv8: yes no no yes bcddv9: ret c = 0 sets sign bit of remainder area to 1 remainder sign flag (sf_rem) = 1 remainder = 0 sets sign bit of quotient area to 1 quotient sign flag (sf_quo) = 1 quotient = 0 error flag (errflag) = 1 remainder 60 78k/iv series application note (8) program listing ? description of label used for executing application routine divsor : lowest address of the ram area containing the 8-digit (4-byte) dividend and 8-digit quotient divind : lowest address of the area containing the 8-digit (4-byte) remainder resulting from division rmind : lowest address of the area containing 8-digit (4-byte) divisor quoflag: quotient sign flag quoflag = 0 ... sign of quotient is positive quoflag = 1 ... sign of quotient is negative remflag : remainder sign flag remflag = 0 ... sign of remainder is positive remflag = 1 ... sign of remainder is negative sflag : sign identification flag sflag = 0 ... same signs sflag = 1 ... different signs errflag : error flag errflag = 0 ... no error has occurred errflag = 1 ... an error occurred ? example of program listing for main routine ? ? movw divsor , #42h movw divsor+2 , #65h movw divind , #12h movw divind+2 , #34h call !bcddiv bt errflag, $error ; br $$ ; error: clr1 errflag ; clear error flag ? ? remark set the dividend and divisor as shown, then call the subroutine.
61 chapter 3 decimal operations ? program listing for this application routine name bcdivr ;********************************************************* ;* decimal division * ;* 8 digit 62 78k/iv series application note bf divind+3.7, $bcddv3 clr1 divind+3.7 set1 remflag ; set remainder sign-flag not1 quoflag ; not quotient sign-flag bcddv3: bf divsor+3.7, $bcddv4 clr1 divsor+3.7 not1 quoflag ; ; **** digit counter set **** ; bcddv4: mov c, #8 ; ; **** quotient, remind left shift **** ; bcddv5: push bc movg whl, #divind ; whl 63 chapter 3 decimal operations ; bcddv7: movg tde, #divsor ; tde 64 78k/iv series application note [memo]
chapter 4 shift processing the 78k/iv series devices support instructions that shift general registers (x, a, c, b, e, d, l, h, and r4 through r11) and general register pairs (ax, bc, de, hl, vp, up, rp2, and rp3) in 1-bit units, as well as 4-bit shift instructions ror4 and rol4. this chapter presents example programs featuring the following two types of shift instructions. (i) shifting in 1-byte units [xchm [tde+], a, xchm [tdeC], and a instructions] (ii) shifting in 4-bit units [ror4 mem and rol4 mem instructions] 4.1 shifting n-byte data 1 byte to the right (1) outline of processing this section presents an example program that shifts n-byte data 1 byte to the right by using the xchm instruction. when shifting n-byte data 1 byte to the right as shown below, set the values described in (4) in the appropriate registers, then execute this subroutine. (2) ram area (3) registers a, c, and tde registers (4) input load the following data into the a, c, and tde registers. a : value to be transferred to the highest address of the n-byte data c : number of bytes to be shifted (n) tde : highest address of the n-byte data to be shifted 0 12 345 6 01 234 5 6 tde msb msb lsb lsb (before execution) a register a register (after execution) n-byte data area, result area (shared) 65
66 78k/iv series application note (5) output the following contents are stored into the n-byte ram area indicated by the tde register. tde: contents of n-byte data, shifted 1 byte to the right (the value of the a register is loaded into the most significant byte position of the n-byte data.) (6) program description when the program is executed, the contents of the a register, specified as the input conditions, are exchanged with the contents of the ram area indicated by the tde register, after which the contents of the tde register are decremented. subsequently, the contents of the c register are decremented. this procedure is repeated until the contents of the c register are decremented to 0. as a result, the value set in the a register is stored into the most significant byte, and the contents of the least significant byte are output to the a register, shifting the 6-byte data 1 byte to the right. (7) flowchart none
67 chapter 4 shift processing (8) program listing ? labels used for execution of application routine aregdt : value to be transferred to the most significant address of the n-byte data bytnum: number of bytes to be shifted (n) r6sift : least significant address of the n-byte data ? example program listing for main routine the following shows an example of the setting necessary when 6-byte data is shifted. ? ? bytnum equ 6 ? ? mov a, #aregdt ; shift in data mov c, #bytnum ; shift byte number movg tde, #r6sift+5 ; call !bytrst ; right shift ? ? remark set the a, c, and tde registers as shown above, then call the subroutine. ? program listing for this application routine name bytrsr ;******************************************************* ;* 1_byte data right shift of 6-byte data * ;* input condition * ;* tde Cregister 68 78k/iv series application note lsd msb whl whl+(n/2?) n-digit data area, result area (shared) 4.2 shifting n-digit data 1 byte to the right (decimal 1/10 processing) (1) outline of processing this section presents an example program that shifts n-digit data 1 digit to the right by using a shift instruction in 4-bit units (ror4 mem or rol4 mem). when shifting n-digit data 1 digit (4 bits) to the right, set the values described in (4) into the appropriate registers, then execute this subroutine. (2) ram area (3) registers a, c, and whl registers (4) input set the following data into the whl and c registers. whl : highest address of the ram area into which n-digit data is to be stored c : number of bytes to be shifted (n/2) (5) output the following contents are stored into the n/2-byte ram area indicated by the tde register. tde : contents of n-digit data, shifted 1 digit (4 bits) to the right (0 is loaded into the most significant digit of the n-digit data.) (6) program description (a) set 0 into the a register. (b) rotate the contents of the ram area, indicated by the low-order 4 bits of the a register and whl register, to the right. (c) the c register is used as a counter that counts the number of times that data is shifted. the value of this counter is decremented. when the value of the shift counter (c register) reaches 0, the processing has been completed. otherwise, the processing returns to step (b). a register whl register higher lower lower higher
69 chapter 4 shift processing (7) flowchart none (8) program listing ? labels used for execution of application routine bytnum : number of bytes to be shifted (n/2) r4sift : lowest address of ram area containing n-digit data ? example program listing for main routine the following shows an example of setting 8-digit data. ? ? bytnum equ 4 ? ? mov c, #bytnum ; 8 digit / 2 movg whl, #r4sift+3 ; call !bcdrs ; right shift ? ? remark set the c and whl registers as shown above, then call the subroutine. ? program listing for this application routine name bcdrsr ;******************************************************* ;* n-digit data right shift * ;* input condition * ;* whl-register 70 78k/iv series application note [memo]
lsb msb tde+ne1 tde+0 transfer data storage area chapter 5 block transfer processing this chapter presents block transfer programs that use the string instructions that are unique to the 78k/iv series. 5.1 block transfer processing of fixed byte data (1) outline of processing this section presents an example program that stores 1-byte data into a specified n-byte ram area by using the movm instruction. this processing is effective for initializing a specific ram area. (2) ram area (3) registers a, c, and tde registers (4) input set the following data in the a, c, and tde registers. a : data to be transferred c : number of bytes to be transferred tde : lowest address of ram area containing n-byte transferred data (5) output the following contents are stored into the ram area, starting from the address indicated by the tde register. tde: the contents of the a register are stored into an n-byte ram area. (6) program description (a) sets the lowest address of the ram area containing n-byte transferred data into the tde register. (b) using the c register as a counter for counting the number of bytes transferred, sets the number of bytes transferred (bytnum). (c) writes the data to be transferred into the a register. (d) transfers the contents of the a register to the ram area specified by the tde register, then decrements the transfer counter (c register). when the value of the transfer counter (c register) reaches 0, the processing is terminated. 71
72 78k/iv series application note (7) flowchart none (8) program listing ? labels used for execution of application routine bytnum : number of bytes subject to block transfer (n) dataset : lowest address of ram area to which n-byte data is to be transferred ? program listing for this application routine the following shows an example of writing 0 to an entire 8-byte ram area. ? ? bytnum equ 8 ? ? movg tde, #dataset ; mov c, #bytnum ; c 73 chapter 5 block transfer processing 5.2 block transfer processing of byte data (1) outline of processing this section presents an example program that transfers the contents of an n-byte ram area indicated by the whl register to an n-byte ram area indicated by the tde register by using the movbk instruction (movbk [tde+], [whl+]). (2) ram area (3) registers a, c, tde, and whl registers (4) input set the following data in the tde, whl, and c registers. tde : lowest address of the ram area containing the transferred n-byte data whl : lowest address of the ram area containing the n-byte data to be transferred c : number of bytes to be transferred (5) output the following contents are stored into the ram area, starting from the address indicated by the tde register. tde: contents of an n-byte ram area indicated by the whl register (6) program description (a) sets the lowest address of the ram area containing the n-byte data to be transferred, into the whl register. (b) sets the lowest address of the ram area to which the n-byte data will be transferred, into the tde register. (c) by using the c register as a transfer counter that counts the number of bytes to be transferred, sets the number of bytes to be transferred (bytnum). (d) transfers the data in the ram area specified by the whl register into the ram area specified by the tde register, then decrements the value of the transfer counter (c register). when the value of the transfer counter (c register) reaches 0, processing ends. lsb msb tde+n? tde+0 lsb msb whl+n? whl+0 transfer data setting area transfer data storage area
74 78k/iv series application note (7) flowchart none (8) program listing ? labels used for execution of application routine bytnum : number of bytes subject to block transfer (n) tensodt : lowest address of the ram area containing the n-byte data to be transferred kakunou: lowest address of the ram area to which the n-byte data will be transferred ? program listing for this application routine the following shows an example of transferring the contents of an 8-byte ram area. ? ? bytnum equ 8 ? ? movg whl, #tensodt ; set address movg tde, #kakunou ; mov c, #bytnum ; c 75 chapter 5 block transfer processing 5.3 block comparison (coincidence detection) of byte data (1) outline of processing this section presents an example program that compares (detects any coincidence between) the contents of the n-byte ram area indicated by the whl register with the contents of the n-byte ram area indicated by the tde register by using the cmpbke instruction (cmpbke [tde+], [whl+]). (2) ram area (3) registers a, c, tde, and whl registers (4) input set the following data in the tde, whl, and c registers. tde : lowest address of the ram area (1) containing the n-byte data to be compared whl : lowest address of the ram area (2) containing the n-byte data to be compared c : number of bytes to be compared (5) output the result of the comparison (coincidence detection) is indicated by the z (zero) flag. z (zero flag) : z (zero flag) of psw (program status word) z = 0 no coincidence was detected z = 1 coincidence was detected whl+n? msb msb tde+n? lsb tde+0 lsb whl+0 compare compare data setting area (2) compare data setting area (1) compare compare compare compare
76 78k/iv series application note (6) program description (a) sets the lowest address of ram area (1) containing the n-byte data to be compared into the whl register. (b) sets the lowest address of ram area (2) containing the n-byte data to be compared into the tde register. (c) by using the c register as a comparison counter to count the number of bytes to be compared, sets the number of bytes to be compared (bytnum). (d) compares the data in the ram area specified by the whl register with the data in the ram area specified by the tde register, and decrements the value of the comparison counter (c register). if the data in the two ram areas does not coincide, or if the value of the comparison counter (c register) reaches 0, processing ends. (7) flowchart omitted because the number of program steps is minimal. (8) program listing ? labels used for execution of application routine compdta: lowest address of the ram area (1) containing the n-byte data to be compared compdtb: lowest address of the ram area (2) containing the n-byte data to be compared bytnum : number of bytes to be compared (n) ? program listing for this application routine the following shows an example of comparing the contents of 8-byte ram areas. ? ? bytnum equ 8 ? ? movg whl, #compdta ; movg tde, #compdtb ; mov c, #bytnum ; c chapter 6 data exchange processing this chapter presents example programs that convert the format of numeric data from hexadecimal to decimal and vice versa, as well as from hexadecimal to ascii and vice versa. 6.1 converting a hexadecimal number (hex) to a decimal number (bcd) (1) outline of processing this section presents an example program that converts 4-byte hexadecimal data into 8-digit decimal data. (2) ram area (3) registers a, x, d, e, up, and whl registers (4) input set the following address in the whl register. whl: lowest address of the ram area containing the 4-byte hexadecimal number to be converted (5) output the following flag indicates the status of the conversion processing. errflag: error flag errflag = 0 no error occurred (data conversion was completed normally) errflag = 1 an error occurred (data cannot be converted because it is outside the valid range) the following contents are stored into the 4-byte area indicated by the whl register. whl to whl+3: 8-digit decimal value resulting from conversion note note the value of the 4-byte data indicated by the whl register is undefined when the error flag (errflag) = 1. remarks 1. values between 00000000h (0) and 05f5e0ffh (99999999) can be converted. 2. the error flag (errflag) is read by the main routine. add error processing as necessary. msb lsb whl+3 whl+2 whl+1 whl 4-byte hexadecimal data setting area, 8-digit decimal data storage area (shared) 77
78 78k/iv series application note (6) program description (a) compares the 4-byte hexadecimal data indicated by the whl register with 05f5e0ffh. (b) if the value of the 4-byte hexadecimal data is greater than 05f5e0ffh, the error flag (errflag) is set to 1 and conversion ends because this value falls outside the supported conversion range. (c) sets the 4-byte hexadecimal data to be converted into the ax and de registers (the high-order 2 bytes are written into the ax register and the low-order 2 bytes are written into the de register). (d) writes the divisor (10) into the up register. (e) executes 4-byte hexadecimal data/divisor (the remainder is loaded into the up register). (f) stores the remainder into the low-order 4 bits of the 8-digit decimal data storage area indicated by the whl register. (g) compares the quotient in the ax and de register with the divisor. if the quotient is greater, jumps to step (h); otherwise, stores the quotient into the high-order 4 bits of the 8-digit decimal data storage area indicated by the whl register. (h) writes the divisor (10) into the up register. (i) executes input 2-byte hexadecimal data/divisor (the remainder is loaded into the up register). (j) stores the remainder into the high-order 4 bits of the 8-digit decimal data storage area indicated by the whl register, then increments the whl register. (k) compares the quotient stored in the ax and de register with the divisor. if the quotient is greater, returns to step (d); if not, stores the quotient into the low-order 4 bits of the 8-digit decimal data storage area indicated by the whl register. (l) clears the error flag (errflag) to 0 to indicate that conversion was completed without error, then terminates the conversion processing.
79 chapter 6 data exchange processing (7) flowchart thxbcd no yes error: ret thxbc2: no yes ret ax, de < 05f5e0ffh ax, de 80 78k/iv series application note (8) program listing ? labels/flags used for execution of application routine hexdat : lowest address of the ram area containing the 4-byte hexadecimal number to be converted errflag : error flag errflag = 0 ... no error occurred errflag = 1 an error occurred ? example program listing for main routine ? ? movg whl, #hexdat call !thxbcd bt errflag, $error br $$ error: clr1 errflag ; clear error flag ? ? remark set the whl register as shown above then call the subroutine. prepare and add error processing as necessary.
81 chapter 6 data exchange processing ? program listing for this application program name trbcdr ;******************************************************* ;* transform bcd (whl-whl+3) * ;* overflow ... cy = 1 * ;* hex data > 99999999 * ;******************************************************* public thxbcd extbit errflag ; ; cseg thxbcd: movw ax, [whl+0] ; movw de, ax ; movw ax, [whl+2] ; cmpw ax, #5f5h ; bc $thxbc2 ; bnz $erhxbcd ; movw de, ax ; movw ax, [whl+0] ; cmpw ax, #0e0ffh ; bc $thxbc1 ; bnz $erhxbcd ; thxbc1: xchw ax, de ; axde 82 78k/iv series application note ; thxbc3: movw up, #10 ; set divisor divux up ; axde / up push ax ; save ax-register movw ax, up ; rol x, 4 ; xch a, x ; or [whl+], a; pop ax ; load ax-register cmpw ax, #00 ; bnz $thxbc2 ; cmpw de, #10 ; bnc $thxbc2 ; xch a, e ; mov [whl], a; br henend1 ; henend: rol e, 4 ; xch a, e ; or [whl], a; henend1: clr1 errflag ; no error ret ; erhxbcd: set1 errflag ; set error ret end
83 chapter 6 data exchange processing 6.2 converting a decimal number (bcd) to a hexadecimal number (hex) (1) outline of processing this section presents an example program that converts a 4-digit decimal number to a 2-byte hexadecimal number. (2) ram area (3) registers a, x, b, c, de, and whl registers (4) input set the following address in the whl register. whl: lowest address of the ram area containing the 4-digit decimal number to be converted (5) output the following flag indicates the status of the conversion processing. errflag: error flag errflag = 0 no error occurred (data conversion was completed normally) errflag = 1 an error occurred (data could not be converted because it is not a decimal number) the following contents are stored into the 2-byte area indicated by the whl register. whl to whl+1: 4-digit hexadecimal number resulting from conversion note note the value of the 2-byte data indicated by the whl register is undefined when the error flag (errflag) = 1. remarks 1. values between 0 and 9999 can be converted. 2. the error flag (errflag) is read by the main routine. add error processing as necessary. msb lsb whl+1 whl 4-digit decimal data setting area, 2-byte hexadecimal data storage area (shared)
84 78k/iv series application note (6) program description this program shifts 4-digit decimal data 1 digit (4 bits) to the left, starting from the most significant digit. it then transfers the data to the a register, 1 digit at a time, and converts the decimal data to hexadecimal data by repeating the following processing four times: (storage area) 85 chapter 6 data exchange processing (7) flowchart tbcdhx bcdls1 tbcdh1: no yes ret tbcdh2: no yes tbcdh3: no yes ret a < 10 c = 0 b = 0 sets the number of bcd digits to be converted b 86 78k/iv series application note (8) program listing ? labels/flags used for execution of application routine bcddat : lowest address of the ram area containing the 4-digit decimal number to be converted errflag: error flag errflag = 0 no error occurred errflag = 1 an error occurred ? example program listing for main routine ? ? movg whl, #bcddat call !tbcdhx bt errflag, $error br $$ error: clr1 errflag ; clear error flag ? ? remark set the whl register as shown above then call the subroutine. prepare and add error processing as necessary.
87 chapter 6 data exchange processing ? program listing for this application routine name trhexr ;******************************************************* ;* transform hex (whl, whl+1) * ;* error ... cy = 1 * ;******************************************************* public tbcdhx extrn bcdls1 extbit errflag ; ; cseg tbcdhx: mov b, #4 ; bcd length movw de, #0 ; result work tbcdh1: push whl ; save pointer mov c, #2 ; shift counter mov a, #0 call !bcdls1 ; bcd left shift pop whl ; restore pointer cmp a, #10 ; error check not1 cy bc $erbcdhx ; error return mov c, b mov x, #0 xch a, x tbcdh2: dec c bz $tbcdh3 push bc ; ax 88 78k/iv series application note tbcdh3: addw ax, de ; result addition movw de, ax dbnz b, $tbcdh1 ; check length movw ax, de ; write result to memory xch a, x mov [whl+], a mov a, x mov [whl], a tbcdh4: clr1 errflag ; no error ret erbcdhx: set1 errflag ; set error ret
89 chapter 6 data exchange processing 6.3 converting an ascii code to a hexadecimal code (1) outline of processing this section introduces an example program that converts two (2-byte) ascii codes (30h through 39h and 41h through 46h) to two (1-byte) hexadecimal codes (00h through 0fh). the ascii codes and hexadecimal codes correspond as follows: ascii code 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h hexadecimal code 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h ascii code 41h 42h 43h 44h 45h 46h hexadecimal code ah bh ch dh eh fh (2) ram area (3) registers a, b, c, and whl registers (4) input set the following data in the bc and whl registers. bc : two ascii codes to be converted whl: address of the ram area into which the two hexadecimal codes resulting from the conversion will be stored (5) output the following flag indicates the status of the conversion processing. errflag: error flag errflag = 0 no error occurred (data conversion was completed normally) errflag = 1 an error occurred (data cannot be converted because it consists of other than ascii codes) whl two-hexadecimal-code storage area
90 78k/iv series application note the following contents are stored into the 1-byte ram area indicated by the whl register. whl: two hexadecimal codes resulting from the conversion note note the 1-byte value indicated by the whl register is undefined if the error flag (errflag) is 1. remark the error flag (errflag) is read by the main routine. prepare and add error processing as necessary. (6) program description (a) reads the first code (b register) of the ascii codes into the a register. (b) checks whether the contents of the a register are between 30h and 39h or between 41h and 46h. if not, sets the error flag (errflag) to 1 to indicate that conversion is impossible, then terminates the conversion processing. (c) subtracts 30h from the contents of the a register if the contents are between 30h and 39h. subtracts 37h from the contents of the a register if the contents are between 41h and 46h. (d) shifts the contents of the two-hexadecimal-code storage area, indicated by the whl register, 4 bits to the left, and stores the contents of the a register into the low-order 4 bits. (e) reads the second (c register) of the ascii codes into the a register, then performs steps (b) through (d).
91 chapter 6 data exchange processing (7) flowchart gethex shex shex ret no (0) yes (1) no (0) yes (1) shex ret < > < > sets error flag (errflag) to 1 clears error flag (errflag) to 0 shifts low-order 4 bits of [whl] to left low-order 4 bits of [whl] 92 78k/iv series application note (8) program listing ? labels/flags used for execution of application routine ascdat : highest address of the ram area containing the two ascii codes (2 bytes) to be converted hexdat : address of the ram area containing the two hexadecimal codes (1 byte) resulting from the conversion errflag : error flag errflag = 0 no error occurred errflag = 1 an error occurred ? example program listing for main routine ? ? movw bc, ascdat movg whl, #hexdat call !gethex bt errflag, $error br $$ error: clr1 errflag ; clear error flag ? ? remark set the whl register as shown above, then call the subroutine. prepare and add error processing as necessary.
93 chapter 6 data exchange processing ? program listing for this application routine name ghexr ;******************************************************* ;* transform hex 39h bnc $shex1 sub a, #30h br endshex shex1: cmp a, #a ; check / ascii < 41h bc $ershex cmp a,#f+1 ; check / ascii > 46h bnc $ershex sub a, #37h br endshex ershex: set1 cy ; set error (cy 94 78k/iv series application note 6.4 converting a hexadecimal code to an ascii code (1) outline of processing this section presents an example program that converts two (1-byte) hexadecimal codes (00h through 0fh) to two (2-byte) ascii codes (30h through 39h and 41h through 46h). the ascii codes and hexadecimal codes correspond as follows: hexadecimal code 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h ascii code 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h hexadecimal code ah bh ch dh eh fh ascii code 41h 42h 43h 44h 45h 46h (2) ram area (3) registers a, b, c, and whl registers (4) input set the following address in the whl register. whl: address of the ram area containing the two hexadecimal codes to be converted (5) output the following contents are stored into the bc register. bc: two ascii codes resulting from the conversion whl two-hexadecimal-code storage area
95 chapter 6 data exchange processing (6) program description (a) reads the first code (high-order 4 bits) of the two-hexadecimal-code storage area, indicated by register whl, into the a register. (b) checks whether the contents of the a register are greater than 10. if they are less than 10, proceeds to step (d). (c) adds 7 to the contents of the a register. (d) adds 30h to the contents of the a register. (e) stores the contents of the a register into the b register. (f) reads the second code (low-order 4 bits) in the two-hexadecimal-code storage area, indicated by the whl register, into the a register. (g) performs steps (b) and (c), then stores the contents of the a register into the c register.
96 78k/iv series application note (7) flowchart getasc sasc ret sasc ret a 97 chapter 6 data exchange processing (8) program listing ? labels/flags used for execution of application routine hexdat: address of the ram area containing the two hexadecimal codes (1-byte) to be converted ascdat: highest address of the ram area containing the two ascii codes (2-byte) resulting from the conversion ? example program listing for main routine ? ? movg whl, #hexdat call !getasc movw ascdat, bc bt errflag, $error br $$ error: clr1 errflag ; clear error flag ? ? remark set the whl register as shown above then call the subroutine. prepare and add error processing as necessary.
98 78k/iv series application note ? program listing for this application routine name ascii ;******************************************************* ;* transform ascii 9 bc $sasc1 add a, #07h ; bias (+7) sasc1: add a, #30h ; bias (+30h) ret
chapter 7 data processing as an illustration of data processing, this chapter presents example programs that sort and search for data. 7.1 sorting 1-byte data (1) outline of processing this section presents an example program that sorts the 1-byte data in a data file into ascending order. the bubble sort method is used to sort the data. bubble sort involves comparing data with the subsequent data in the series, starting from the first item of data, exchanging the two data items if they are not in order. once the last item of data in the series has been compared, processing returns to the first item of data. the procedure is repeated until no further exchange of data occurs. (2) ram area (3) registers a, bc, and whl registers (however, the whl register is reserved.) (4) input set the following data in the whl and bc registers. whl: address of the ram area into which the data is to be sorted bc : number of items of data (number of bytes) to be sorted (5) output the following contents are stored into the ram area indicated by the whl register. whl to whl+bcC1: data is sorted into ascending order whl whl+bc? sorted data storage area 99
100 78k/iv series application note (6) program description this program uses the bubble sort method to sort data. the processing procedure is as follows. (a) clears the exchange flag (chgflag) that indicates that exchange has been executed to 0. (b) by using the bc register as a byte counter to indicate the number of bytes of data to be sorted, decrements the byte counter. if the value of the byte counter is 0, terminates the sort processing. (c) saves the whl and bc registers. (d) compares the value in the sorted data storage area indicated by the whl register ([whl]) with the value in the sorted data storage area indicated by whl register + 1 ([whl+1]). if [whl] < [whl+1], jumps to step (e). if [whl] 3 [whl+1], jumps to step (f). (e) exchanges the contents of the sorted data storage area indicated by the whl register with the contents of the sorted data storage area indicated by the whl register + 1, then sets the exchange flag (chngfl) to 1. (f) increments the whl register indicating the address of the sorted data storage area, then decrements the byte counter (bc register). (g) if the value of the byte counter (bc register) is other than 0, repeats steps (d) through (f). (h) restores the data for sorting, saved in step (c), into the whl register that indicates the address of the sorted data storage area, and into the bc register indicating the number of bytes in the data arrangement. (i) repeats steps (a) through (h) if the exchange flag (chgflag) is set to 1. otherwise, ends the sorting processing.
101 chapter 7 data processing (7) flowchart sort yes no sort2 no yes sort3 no yes yes no ret restores bc, whl clears exchange flag chngfl [whl] bc = 0 bc 102 78k/iv series application note (8) program listing ? labels used for execution of application routine sortdat : first address of data array to be sorted bc register: number of data items to be sorted chgflag : flag indicating whether data items have been exchanged chgflag = 1 data items have been exchanged chgflag = 0 data items have not been exchanged ? example of program listing for main routine ? ? movw bc, #10h ; data length is 16 bytes movg whl, #sortdat call !sort ? ? remark set the bc and whl register as shown above, then call the subroutine.
103 chapter 7 data processing ? program listing for this application routine name sortr ;******************************************************* ;* bubble sort * ;* input condition * ;* bc-register 104 78k/iv series application note 7.2 searching for data (1) outline of processing this section presents an example program that searches for specific data and returns the corresponding storage address once that data has been found. binary search is used to search for data. binary search involves searching for a specified data string in a collection of data. in this example, a collection of data that has been sorted into ascending order is searched. the data to be searched is compared with the intermediate value for the collection of data, half the collection of data being deleted depending on which of the searched data or intermediate value is greater. by executing this operation repeatedly, the specified data can be located. (2) ram area (3) registers a, bc, whl, uup, and vvp registers (4) input set the following data in the a, whl, and bc registers. a : data to be searched whl : first address of the searched data storage area (in which data has already been sorted into ascending order) bc : amount of data (bytes) to be searched (5) output the following flag indicates the status of the search processing. cy: carry flag cy = 0 end of search cy = 1 specified data could not be found the following contents are stored into the whl register. whl register: address of the searched data note note if the specified data is not found, the value of the whl register will be undefined. whl whl+bc? searched data storage area
105 chapter 7 data processing (6) program description this program uses binary search. the processing procedure is described below. (a) writes the first address of the searched data storage area into the uup register, and the last address of the searched data storage area into the vvp register. (b) compares the first address of the searched data storage area (uup register) with the last address of the searched data storage area (vvp register). if uup register vvp register, proceeds to step (d). if uup register > vvp register, proceeds to step (c). (c) sets the carry flag (cy) to 1 then terminates the processing. (d) sets the intermediate address of the searched data storage area (intermediate address indicated by the uup and vvp registers) into the whl register. (e) compares the searched data with the contents of the intermediate address of the searched data storage area indicated by the whl register (intermediate address indicated by the uup and vvp registers). if the searched data coincides with the contents of the intermediate address (i.e., when the data has been found), ends the search processing. (f) if the carry flag (cy) is 1, executes vvp 106 78k/iv series application note (7) flowchart search searc1: yes no yes no ret a < [whl] a = [whl] yes no uup > vvp updates upper-limit address vvp 107 chapter 7 data processing (8) program listing ? labels used for execution of application routine sortdat: first address of data array to be sorted ? example program listing for main routine ? ? movw bc, #10h movg whl, #seachdat mov a, #0aah call !search ? ? remark set the bc, whl, and a registers as shown above, then call the subroutine.
108 78k/iv series application note ? program listing for this application routine name searcr ;******************************************************* ;* binary search * ;* input condition * ;* a-register


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