mds 722 a 1 revision 121404 integrated circuit systems 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com l ow c ost 27 mh z 3.3 v olt vcxo ics722 description the ics722 is a low cost, low-jitter, high-performance 3.3 volt vcxo designed to replace expensive discrete vcxos modules. the on-ch ip voltage controlled crystal oscillator accepts a 0 to 3.3 v input voltage to cause the output clocks to vary by over 100 ppm. using ics? patented vcxo techniques, the device uses an inexpensive external pullable crystal in the range of 16.2 to 28 mhz to produce a vcxo output clock at that same frequency. the frequency of the on-chip vcxo is adjusted by an external control voltage input into pin vin. because vin is a high-impedance input, it can be driven directly from an pwm rc integrator circuit. frequency output increases with vin voltage input. the usable range of vin is 0 to 3.3 v. ics manufactures the largest variety of set-top box and multimedia clock synthesizers for all applications. consult ics to eliminate vcxos, crystals, and oscillators from your board. features ? packaged in 8-pin soic ? operational frequency range of 16.2 mhz to 28 mhz ? uses an inexpensive external crystal ? on-chip patented vcxo with pull range of 230 ppm (minimum) ? vcxo tuning voltage of 0 to 3.3 v ? operating voltage of 3.3 v ? 12 ma output drive ca pability at ttl levels ? advanced, low-power, sub-micron cmos process block diagram x1 x2 voltage controlled crystal oscillator vin 16.2-28mhz pullable crystal 16.2-28mhz clock (refout) gnd vdd
l ow c ost 27 mh z 3.3 v olt vcxo mds 722 a 2 revision 121404 integrated circuit systems 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics722 pin assignment pin descriptions x1 vdd vin dc gnd refout dc x2 1 2 3 4 8 7 6 5 ics722 8-pin (150 mil) soic pin number pin name pin type pin description 1 xi input crystal connection. connect to the external pullable crystal. 2 vdd power connect to +3.3 v (0.01 f decoupling capacitor recommended). 3 vin input voltage input to vcxo. zero to 3.3 v signal which controls the vcxo frequency. 4 gnd power connect to ground. 5 refout output vcxo cmos level clock output matches the nominal frequency of the crystal. 6 dc ? do not connect anything to this pin. 7 dc ? do not connect anything to this pin. 8 x2 input crystal connection. connect to a external pullable crystal.
l ow c ost 27 mh z 3.3 v olt vcxo mds 722 a 3 revision 121404 integrated circuit systems 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics722 external component selection the ics722 requires a minimum number of external components for proper operation. decoupling capacitors a decoupling capacitor of 0.01 f should be connected between vdd and gnd on pins 2 and 4 as close to the ics722 as possible. for optimum device performance, the decoupling capacitor should be mounted on the component side of the pcb. avoid the use of vias in the decoupling circuit. series termination resistor when the pcb trace between the clock output and the load is over 1 inch, series termination should be used. to series terminate a 50 ? trace (a commonly used trace impedance), place a 33 ? resistor in series with the clock line, as close to the clock output pin as possible. the nominal impedance of the clock output is 20 ? . quartz crystal the ics722 vcxo function consists of the external crystal and the integrated vcxo oscillator circuit. to assure the best system performance (frequency pull range) and reliability, a crystal device with the recommended parameters (shown below) must be used, and the layout guidelines discussed in the following section shown must be followed. the oscillation frequency of a quartz crystal is determined by its ?cut? and by the load capacitors connected to it. the ics722 incorporates on-chip variable load capacitors that ?pull? (change) the frequency of the crystal. the crystal specified for use with the ics722 is designed to have zero frequency error when the total of on-chip + stray capacitance is 14 pf. recommended crystal parameters: initial accuracy at 25 c20 ppm temperature stability 30 ppm aging 20 ppm load capacitance 14 pf shunt capacitance, c0 7 pf max c0/c1 ratio 250 max equivalent series resistance 35 ? max the external crystal must be connected as close to the chip as possible and should be on the same side of the pcb as the ics722. there should be no via?s between the crystal pins and the x1 and x2 device pins. there should be no signal traces underneath or close to the crystal. see application note man05. crystal tuning load capacitors the crystal traces should include pads for small fixed capacitors, one between x1 and ground, and another between x2 and ground. stuffing of these capacitors on the pcb is optional. the need for these capacitors is determined at system prototype evaluation, and is influenced by the particular crystal used (manufacture and frequency) and by pcb layout. the typical required capacitor value is 1 to 4 pf. the procedure for determining the value of these capacitors can be found in application note man05.
l ow c ost 27 mh z 3.3 v olt vcxo mds 722 a 4 revision 121404 integrated circuit systems 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics722 absolute maximum ratings stresses above the ratings listed below can cause perma nent damage to the ics722. these ratings, which are standard values for ics commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. recommended operation conditions dc electrical characteristics vdd=3.3 v 5% , ambient temperature 0 to +70 c, unless stated otherwise item rating supply voltage, vdd 7 v all inputs and outputs -0.5 v to vdd+0.5 v ambient operating temperature 0 to +70 c storage temperature -65 to +150 c soldering temperature 260 c parameter min. typ. max. units ambient operating temperature 0 ? +70 c power supply voltage (measured in respect to gnd) +3.15 +3.45 v reference crystal parameters refer to page 3 parameter symbol conditions min. typ. max. units operating voltage vdd 3.15 3.45 v output high voltage v oh i oh = -12 ma 2.4 v output low voltage v ol i ol = 12 ma 0.4 v output high voltage (cmos level) v oh i oh = -4 ma vdd-0.4 v operating supply current idd no load 6 ma short circuit current i os 50 ma vin, vcxo control voltage v ia 03.3v
l ow c ost 27 mh z 3.3 v olt vcxo mds 722 a 5 revision 121404 integrated circuit systems 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics722 ac electrical characteristics vdd = 3.3 v 5% , ambient temperature 0 to +70 c, unless stated otherwise note 1: external crystal device must conform with pullable crystal specifications listed on page 3. thermal characteristics marking diagram (ics722m) mar king diagram (ICS722MLF) notes: 1. ###### is the lot number. 2. yyww is the last two digits of the year and week that the part was assembled. 3. ?lf? denotes pb (lead) free package. 4. bottom marking: (origin) origin = country of origin if not usa. parameter symbol conditions min. typ. max. units output frequency f o 16.2 28 mhz crystal pullability f p 0v< vin < 3.3 v, note 1 + 115 ppm vcxo gain vin = vdd/2 + 1 v, note 1 120 ppm/v output rise time t or 0.8 to 2.0 v, c l =15 pf 1.5 ns output fall time t of 2.0 to 0.8 v, c l =15 pf 1.5 ns output clock duty cycle t d measured at 1.4 v, c l =15 pf 40 50 60 % maximum output jitter, short term t j c l =15 pf 110 ps parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 150 c/w ja 1 m/s air flow 140 c/w ja 3 m/s air flow 120 c/w thermal resistance junction to case jc 40 c/w ics722m ###### yyww 14 5 8 722mlf ###### yyww 14 5 8
l ow c ost 27 mh z 3.3 v olt vcxo mds 722 a 6 revision 121404 integrated circuit systems 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics722 package outline and package dimensions (8-pin soic) package dimensions are kept current with jedec publication no. 95 ordering information ?lf? denotes pb (lead) free package. while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems (ics) assumes no responsibility for either its use or for the infringemen t of any patents or other rights of third parties, which wou ld result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring ex tended temperature range, high re liability, or other extraordina ry environmental requirements are not recomm ended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not authorize or warrant any ics product for use in life support devices o r critical medical instruments. part / order number marking shipping packaging package temperature ics722m see page 5 tubes 8-pin soic 0 to +70 c ics722mt tape and reel 8-pin soic 0 to +70 c ICS722MLF tubes 8-pin soic 0 to +70 c ICS722MLFt tape and reel 8-pin soic 0 to +70 c index area 1 2 8 d e seating plane a1 a e - c - b .10 (.004) c c l h h x 45 millimeters inches symbol min max min max a 1.35 1.75 0.0532 0.0688 a1 1.10 0.25 0.0040 0.0098 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.0075 0.0098 d 4.80 5.00 .1890 .1968 e 3.80 4.00 0.1497 0.1574 e 1.27 basic 0.050 basic h 5.80 6.20 0.2284 0.2440 h 0.25 0.50 0.010 0.020 l 0.40 1.27 0.016 0.050 a0 8 0 8
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