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| regarding the change of names mentioned in the document, such as hitachi electric and hitachi xx, to renesas technology corp. the semiconductor operations of mitsubishi electric and hitachi were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although hitachi, hitachi, ltd., hitachi semiconductors, and other hitachi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. renesas technology home page: http://www.renesas.com renesas technology corp. customer support dept. april 1, 2003 to all our customers
cautions keep safety first in your circuit designs! 1. renesas technology corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or an y other rights, belonging to renesas technology corporation or a third party. 2. renesas technology corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained i n these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by renesas technology corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact renesas technology corporation or an authorized renesas technology corporation product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corporation by various means, including the renesas technology corporation semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, an d algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact renesas technology corporation or an authorized renesas technology corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corporation is necessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a lice nse from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corporation for further details on these materials or the products contained therein. hitachi single-chip microcomputer h8/3024 series h8/3024 hd6433024f, hd6433024te, hd6433024fp h8/3026 hd6433026f, hd6433026te, hd6433026fp h8/3024f-ztat HD64F3024f, HD64F3024te, HD64F3024fp h8/3026f-ztat hd64f3026f, hd64f3026te, hd64f3026fp hardware manual ade-602-266 rev. 1.0 3/15/03 hitachi, ltd. cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products. preface the h8/3024 series is a high-performance single-chip microcomputer that integrates peripheral functions necessary for system configuration with an h8/300h cpu featuring a 32-bit internal architecture as its core. the on-chip peripheral functions include rom, ram, 16-bit timers, 8-bit timers, a programmable timing pattern controller (tpc), a watchdog timer (wdt), a serial communication interface (sci), a d/a converter, an a/d converter, and i/o ports, providing an ideal configuration as a microcomputer for embedding in sophisticated control systems. flash memory (f-ztat *) and mask rom are available as on-chip rom, enabling users to respond quickly and flexibly to changing application specifications and the demands of the transition from initial to full-fledged volume production. note: * f-ztat is a trademark of hitachi, ltd. intended readership: this manual is intended for users undertaking the design of an application system using the h8/3024 series. readers using this manual require a basic knowledge of electrical circuits, logic circuits, and microcomputers. purpose: the purpose of this manual is to give users an understanding of the hardware functions and electrical characteristics of the h8/3024 series. details of execution instructions can be found in the h8/300h series programming manual, which should be read in conjunction with the present manual. using this manual: ? for an overall understanding of the h8/3024 series's functions follow the table of contents. this manual is broadly divided into sections on the cpu, system control functions, peripheral functions, and electrical characteristics. ? for a detailed understanding of cpu functions refer to the separate publication h8/300h series programming manual. note on bit notation: bits are shown in high-to-low order from left to right. ? for a detailed understanding of a register when its name is known the addresses, bits, and initial values of the registers are summarized in appendix b, internal i/o registers. related material: the latest information is available at our web site. please make sure that you have the most up-to-date information available. (http://www.hitachisemiconductor.com/) user's manuals on the h8/3024: manual title ade no. h8/3024 hardware manual this manual h8/300h series programming manual ade-602-053 users manuals for development tools: manual title ade no. c/c++ compiler, assembler, optimizing linkage editor user? manual ade-702-247 h8s, h8/300 series simulator/debugger user? manual ade-702-037 hitachi embedded workshop user? manual ade-702-201 h8s, h8/300 series hitachi embedded workshop, hitachi debugging interface user? manual ade-702-231 application note: manual title ade no. h8/300h for cpu application note ade-502-033 h8/300h on-chip supporting modules application note ade-502-035 h8/300h technical q&a ade-502-038 comparison of h8/3024 series product specifications there are four members of the h8/3024 series: the h8/3024f-ztat and h8/3026f-ztat (all with on-chip flash memory), and the h8/3024 mask rom version and h8/3026 mask rom version. the specifications of these products are compared below. h8/3024f-ztat h8/3026f-ztat h8/3024 mask rom version h8/3026 mask rom version product specifications on-chip single-power-supply flash memory mask rom version product code HD64F3024 hd64f3026 hd6433024 hd6433026 pin arrange- ment see figures 1.2 and 1.3, pin arrangement, in section 1 ram size 4 kbytes 8 kbytes 4 kbytes 8 kbytes rom size 128 kbytes 256 kbytes 128 kbytes 256 kbytes address output functions address update mode 1 or 2 selectable see 6.3.5, address output method, in section 6 flash memory see section 18, flash memory see section 17, flash memory electrical characteristics (operating frequency) see section 21, electrical characteristics 2 to 25 mhz registers see table b.1, comparison of h8/3024 series internal i/o register specifications, in appendix b see appendix b.2, address list see appendix b.1, address list see appendix b.2, address list see appendix b.1, address list i contents section 1 overview ........................................................................................................... 1 1.1 overview................................................................................................................... ......... 1 1.2 block diagram.............................................................................................................. ..... 6 1.3 pin description ............................................................................................................ ...... 7 1.3.1 pin arrangement .................................................................................................. 7 1.3.2 pin functions........................................................................................................ 10 1.3.3 pin assignments in each mode............................................................................ 14 1.4 caution on crystal resonator connection ........................................................................ 18 section 2 cpu ..................................................................................................................... 19 2.1 overview................................................................................................................... ......... 19 2.1.1 features ................................................................................................................ 1 9 2.1.2 differences from h8/300 cpu............................................................................. 20 2.2 cpu operating modes ...................................................................................................... 20 2.3 address space.............................................................................................................. ...... 21 2.4 register configuration ..................................................................................................... .22 2.4.1 overview .............................................................................................................. 22 2.4.2 general registers.................................................................................................. 23 2.4.3 control registers.................................................................................................. 24 2.4.4 initial cpu register values ................................................................................. 25 2.5 data formats............................................................................................................... ....... 26 2.5.1 general register data formats ............................................................................ 26 2.5.2 memory data formats.......................................................................................... 27 2.6 instruction set............................................................................................................ ........ 29 2.6.1 instruction set overview...................................................................................... 29 2.6.2 instructions and addressing modes ..................................................................... 30 2.6.3 tables of instructions classified by function...................................................... 31 2.6.4 basic instruction formats..................................................................................... 40 2.6.5 notes on use of bit manipulation instructions.................................................... 41 2.7 addressing modes and effective address calculation ..................................................... 43 2.7.1 addressing modes................................................................................................ 43 2.7.2 effective address calculation.............................................................................. 45 2.8 processing states .......................................................................................................... ..... 49 2.8.1 overview .............................................................................................................. 49 2.8.2 program execution state ...................................................................................... 49 2.8.3 exception-handling state .................................................................................... 50 2.8.4 exception handling operation ............................................................................. 51 2.8.5 bus-released state ............................................................................................... 52 2.8.6 reset state ............................................................................................................ 52 ii 2.8.7 power-down state................................................................................................ 53 2.9 basic operational timing.................................................................................................. 5 3 2.9.1 overview .............................................................................................................. 53 2.9.2 on-chip memory access timing ........................................................................ 53 2.9.3 on-chip supporting module access timing....................................................... 54 2.9.4 access to external address space ....................................................................... 55 section 3 mcu operating modes ................................................................................ 57 3.1 overview................................................................................................................... ......... 57 3.1.1 operating mode selection.................................................................................... 57 3.1.2 register configuration ......................................................................................... 58 3.2 mode control register (mdcr) ....................................................................................... 58 3.3 system control register (syscr).................................................................................... 59 3.4 operating mode descriptions............................................................................................ 61 3.4.1 mode 1.................................................................................................................. 6 1 3.4.2 mode 2.................................................................................................................. 6 1 3.4.3 mode 3.................................................................................................................. 6 2 3.4.4 mode 4.................................................................................................................. 6 2 3.4.5 mode 5.................................................................................................................. 6 2 3.4.6 mode 6.................................................................................................................. 6 2 3.4.7 mode 7.................................................................................................................. 6 2 3.5 pin functions in each operating mode............................................................................. 63 3.6 memory map in each operating mode............................................................................. 64 3.6.1 comparison of h8/3024 series memory maps.................................................... 64 3.6.2 reserved areas..................................................................................................... 64 section 4 exception handling ........................................................................................ 69 4.1 overview................................................................................................................... ......... 69 4.1.1 exception handling types and priority ............................................................... 69 4.1.2 exception handling operation ............................................................................. 69 4.1.3 exception vector table........................................................................................ 70 4.2 reset ...................................................................................................................... ............ 72 4.2.1 overview .............................................................................................................. 72 4.2.2 reset sequence..................................................................................................... 72 4.2.3 interrupts after reset ............................................................................................ 75 4.3 interrupts................................................................................................................. ........... 76 4.4 trap instruction ........................................................................................................... ...... 76 4.5 stack status after exception handling .............................................................................. 77 4.6 notes on stack usage....................................................................................................... .78 section 5 interrupt controller ........................................................................................ 81 5.1 overview................................................................................................................... ......... 81 5.1.1 features ................................................................................................................ 8 1 iii 5.1.2 block diagram...................................................................................................... 82 5.1.3 pin configuration ................................................................................................. 83 5.1.4 register configuration ......................................................................................... 83 5.2 register descriptions...................................................................................................... ... 83 5.2.1 system control register (syscr) ...................................................................... 83 5.2.2 interrupt priority registers a and b (ipra, iprb) ............................................. 84 5.2.3 irq status register (isr) .................................................................................... 89 5.2.4 irq enable register (ier) .................................................................................. 90 5.2.5 irq sense control register (iscr)..................................................................... 91 5.3 interrupt sources.......................................................................................................... ...... 92 5.3.1 external interrupts................................................................................................ 92 5.3.2 internal interrupts ................................................................................................. 93 5.3.3 interrupt exception handling vector table ......................................................... 93 5.4 interrupt operation ........................................................................................................ .... 97 5.4.1 interrupt handling process ................................................................................... 97 5.4.2 interrupt exception handling sequence .............................................................. 102 5.4.3 interrupt response time ...................................................................................... 103 5.5 usage notes ................................................................................................................ ....... 104 5.5.1 contention between interrupt and interrupt-disabling instruction...................... 104 5.5.2 instructions that inhibit interrupts........................................................................ 105 5.5.3 interrupts during eepmov instruction execution .............................................. 105 section 6 bus controller .................................................................................................. 107 6.1 overview................................................................................................................... ......... 107 6.1.1 features ................................................................................................................ 1 07 6.1.2 block diagram...................................................................................................... 108 6.1.3 pin configuration ................................................................................................. 109 6.1.4 register configuration ......................................................................................... 110 6.2 register descriptions...................................................................................................... ... 110 6.2.1 bus width control register (abwcr) ............................................................... 110 6.2.2 access state control register (astcr).............................................................. 111 6.2.3 wait control registers h and l (wcrh, wcrl).............................................. 112 6.2.4 bus release control register (brcr) ................................................................ 116 6.2.5 bus control register (bcr) ................................................................................ 117 6.2.6 chip select control register (cscr).................................................................. 119 6.2.7 address control register (adrcr).................................................................... 120 6.3 operation .................................................................................................................. ......... 121 6.3.1 area division........................................................................................................ 121 6.3.2 bus specifications ................................................................................................ 124 6.3.3 memory interfaces................................................................................................ 125 6.3.4 chip select signals............................................................................................... 125 6.3.5 address output method ....................................................................................... 126 6.4 basic bus interface........................................................................................................ .... 127 iv 6.4.1 overview .............................................................................................................. 127 6.4.2 data size and data alignment ............................................................................. 127 6.4.3 valid strobes ........................................................................................................ 128 6.4.4 memory areas...................................................................................................... 129 6.4.5 basic bus control signal timing......................................................................... 130 6.4.6 wait control ......................................................................................................... 137 6.5 idle cycle................................................................................................................. .......... 139 6.5.1 operation .............................................................................................................. 13 9 6.5.2 pin states in idle cycle ........................................................................................ 141 6.6 bus arbiter ................................................................................................................ ........ 141 6.6.1 operation .............................................................................................................. 14 2 6.7 register and pin input timing .......................................................................................... 144 6.7.1 register write timing.......................................................................................... 144 6.7.2 breq pin input timing....................................................................................... 145 section 7 i/o ports ............................................................................................................ 147 7.1 overview................................................................................................................... ......... 147 7.2 port 1..................................................................................................................... ............. 151 7.2.1 overview .............................................................................................................. 151 7.2.2 register descriptions............................................................................................ 151 7.3 port 2..................................................................................................................... ............. 154 7.3.1 overview .............................................................................................................. 154 7.3.2 register descriptions............................................................................................ 155 7.4 port 3..................................................................................................................... ............. 158 7.4.1 overview .............................................................................................................. 158 7.4.2 register descriptions............................................................................................ 158 7.5 port 4..................................................................................................................... ............. 160 7.5.1 overview .............................................................................................................. 160 7.5.2 register descriptions............................................................................................ 161 7.6 port 5..................................................................................................................... ............. 163 7.6.1 overview .............................................................................................................. 163 7.6.2 register descriptions............................................................................................ 164 7.7 port 6..................................................................................................................... ............. 166 7.7.1 overview .............................................................................................................. 166 7.7.2 register descriptions............................................................................................ 167 7.8 port 7..................................................................................................................... ............. 170 7.8.1 overview .............................................................................................................. 170 7.8.2 register description ............................................................................................. 171 7.9 port 8..................................................................................................................... ............. 172 7.9.1 overview .............................................................................................................. 172 7.9.2 register descriptions............................................................................................ 173 7.10 port 9.................................................................................................................... .............. 177 7.10.1 overview .............................................................................................................. 17 7 v 7.10.2 register descriptions............................................................................................ 178 7.11 port a.................................................................................................................... ............. 182 7.11.1 overview .............................................................................................................. 18 2 7.11.2 register descriptions............................................................................................ 184 7.12 port b .................................................................................................................... ............. 194 7.12.1 overview .............................................................................................................. 19 4 7.12.2 register descriptions............................................................................................ 196 section 8 16-bit timer ..................................................................................................... 203 8.1 overview................................................................................................................... ......... 203 8.1.1 features ................................................................................................................ 2 03 8.1.2 block diagrams.................................................................................................... 205 8.1.3 pin configuration ................................................................................................. 208 8.1.4 register configuration.......................................................................................... 209 8.2 register descriptions...................................................................................................... ... 210 8.2.1 timer start register (tstr)................................................................................ 210 8.2.2 timer synchro register (tsnc).......................................................................... 211 8.2.3 timer mode register (tmdr) ............................................................................ 212 8.2.4 timer interrupt status register a (tisra) ......................................................... 215 8.2.5 timer interrupt status register b (tisrb).......................................................... 217 8.2.6 timer interrupt status register c (tisrc).......................................................... 220 8.2.7 timer counters (16tcnt)................................................................................... 222 8.2.8 general registers (gra, grb) ........................................................................... 223 8.2.9 timer control registers (16tcr)........................................................................ 224 8.2.10 timer i/o control register (tior) ..................................................................... 226 8.2.11 timer output level setting register c (tolr).................................................. 228 8.3 cpu interface .............................................................................................................. ...... 230 8.3.1 16-bit accessible registers.................................................................................. 230 8.3.2 8-bit accessible registers.................................................................................... 232 8.4 operation .................................................................................................................. ......... 233 8.4.1 overview .............................................................................................................. 233 8.4.2 basic functions .................................................................................................... 233 8.4.3 synchronization.................................................................................................... 241 8.4.4 pwm mode .......................................................................................................... 243 8.4.5 phase counting mode .......................................................................................... 247 8.4.6 16-bit timer output timing ................................................................................ 249 8.5 interrupts................................................................................................................. ........... 250 8.5.1 setting of status flags.......................................................................................... 250 8.5.2 timing of clearing of status flags ...................................................................... 252 8.5.3 interrupt sources .................................................................................................. 253 8.6 usage notes ................................................................................................................ ....... 254 vi section 9 8-bit timers ..................................................................................................... 267 9.1 overview................................................................................................................... ......... 267 9.1.1 features ................................................................................................................ 2 67 9.1.2 block diagram...................................................................................................... 269 9.1.3 pin configuration ................................................................................................. 270 9.1.4 register configuration ......................................................................................... 271 9.2 register descriptions...................................................................................................... ... 272 9.2.1 timer counters (8tcnt)..................................................................................... 272 9.2.2 time constant registers a (tcora) ................................................................. 273 9.2.3 time constant registers b (tcorb).................................................................. 274 9.2.4 timer control register (8tcr) ........................................................................... 275 9.2.5 timer control/status registers (8tcsr) ............................................................ 278 9.3 cpu interface .............................................................................................................. ...... 283 9.3.1 8-bit registers...................................................................................................... 283 9.4 operation .................................................................................................................. ......... 285 9.4.1 8tcnt count timing.......................................................................................... 285 9.4.2 compare match timing........................................................................................ 286 9.4.3 input capture signal timing................................................................................ 287 9.4.4 timing of status flag setting............................................................................... 288 9.4.5 operation with cascaded connection .................................................................. 289 9.4.6 input capture setting............................................................................................ 292 9.5 interrupt .................................................................................................................. ........... 293 9.5.1 interrupt sources .................................................................................................. 293 9.5.2 a/d converter activation .................................................................................... 294 9.6 8-bit timer application example ..................................................................................... 294 9.7 usage notes ................................................................................................................ ....... 295 9.7.1 contention between 8tcnt write and clear...................................................... 295 9.7.2 contention between 8tcnt write and increment .............................................. 296 9.7.3 contention between tcor write and compare match ...................................... 297 9.7.4 contention between tcor read and input capture ........................................... 298 9.7.5 contention between counter clearing by input capture and counter increment 299 9.7.6 contention between tcor write and input capture .......................................... 300 9.7.7 contention between 8tcnt byte write and increment in 16-bit count mode (cascaded connection) ........................................................................................ 301 9.7.8 contention between compare matches a and b ................................................. 302 9.7.9 8tcnt operation and internal clock source switchover .................................. 302 section 10 programmable timing pattern controller (tpc) .................................. 305 10.1 overview.................................................................................................................. .......... 305 10.1.1 features ................................................................................................................ 305 10.1.2 block diagram...................................................................................................... 306 10.1.3 pin configuration ................................................................................................. 307 10.1.4 register configuration ......................................................................................... 308 vii 10.2 register descriptions..................................................................................................... .... 309 10.2.1 port a data direction register (paddr) ........................................................... 309 10.2.2 port a data register (padr) .............................................................................. 309 10.2.3 port b data direction register (pbddr)............................................................ 310 10.2.4 port b data register (pbdr)............................................................................... 310 10.2.5 next data register a (ndra) ............................................................................ 311 10.2.6 next data register b (ndrb) ............................................................................. 313 10.2.7 next data enable register a (ndera).............................................................. 315 10.2.8 next data enable register b (nderb) .............................................................. 316 10.2.9 tpc output control register (tpcr) ................................................................. 317 10.2.10 tpc output mode register (tpmr) ................................................................... 319 10.3 operation ................................................................................................................. .......... 321 10.3.1 overview .............................................................................................................. 32 1 10.3.2 output timing ...................................................................................................... 322 10.3.3 normal tpc output ............................................................................................. 323 10.3.4 non-overlapping tpc output ............................................................................. 325 10.3.5 tpc output triggering by input capture ............................................................ 327 10.4 usage notes ............................................................................................................... ........ 328 10.4.1 operation of tpc output pins ............................................................................. 328 10.4.2 note on non-overlapping output........................................................................ 328 section 11 watchdog timer ............................................................................................. 331 11.1 overview.................................................................................................................. .......... 331 11.1.1 features ................................................................................................................ 331 11.1.2 block diagram...................................................................................................... 332 11.1.3 pin configuration ................................................................................................. 332 11.1.4 register configuration ......................................................................................... 333 11.2 register descriptions..................................................................................................... .... 333 11.2.1 timer counter (tcnt) ........................................................................................ 333 11.2.2 timer control/status register (tcsr) ................................................................ 334 11.2.3 reset control/status register (rstcsr) ............................................................ 336 11.2.4 notes on register access ..................................................................................... 337 11.3 operation ................................................................................................................. .......... 339 11.3.1 watchdog timer operation.................................................................................. 339 11.3.2 interval timer operation...................................................................................... 340 11.3.3 timing of setting of overflow flag (ovf) ......................................................... 340 11.3.4 timing of setting of watchdog timer reset bit (wrst) .................................. 341 11.4 interrupts................................................................................................................ ............ 342 11.5 usage notes ............................................................................................................... ........ 342 section 12 serial communication interface ................................................................ 343 12.1 overview.................................................................................................................. .......... 343 12.1.1 features ................................................................................................................ 343 viii 12.1.2 block diagram...................................................................................................... 345 12.1.3 pin configuration ................................................................................................. 346 12.1.4 register configuration ......................................................................................... 347 12.2 register descriptions..................................................................................................... .... 348 12.2.1 receive shift register (rsr)............................................................................... 348 12.2.2 receive data register (rdr) .............................................................................. 348 12.2.3 transmit shift register (tsr).............................................................................. 349 12.2.4 transmit data register (tdr) ............................................................................. 349 12.2.5 serial mode register (smr)................................................................................ 350 12.2.6 serial control register (scr).............................................................................. 353 12.2.7 serial status register (ssr)................................................................................. 357 12.2.8 bit rate register (brr)....................................................................................... 362 12.3 operation ................................................................................................................. .......... 370 12.3.1 overview .............................................................................................................. 37 0 12.3.2 operation in asynchronous mode........................................................................ 373 12.3.3 multiprocessor communication ........................................................................... 382 12.3.4 synchronous operation ........................................................................................ 389 12.4 sci interrupts ............................................................................................................ ........ 397 12.5 usage notes ............................................................................................................... ........ 398 12.5.1 notes on use of sci ............................................................................................. 398 section 13 smart card interface ...................................................................................... 403 13.1 overview.................................................................................................................. .......... 403 13.1.1 features ................................................................................................................ 403 13.1.2 block diagram...................................................................................................... 404 13.1.3 pin configuration ................................................................................................. 404 13.1.4 register configuration ......................................................................................... 405 13.2 register descriptions..................................................................................................... .... 406 13.2.1 smart card mode register (scmr) .................................................................... 406 13.2.2 serial status register (ssr)................................................................................. 408 13.2.3 serial mode register (smr)................................................................................ 409 13.2.4 serial control register (scr).............................................................................. 410 13.3 operation ................................................................................................................. .......... 411 13.3.1 overview .............................................................................................................. 41 1 13.3.2 pin connections.................................................................................................... 411 13.3.3 data format.......................................................................................................... 412 13.3.4 register settings................................................................................................... 414 13.3.5 clock ................................................................................................................... . 416 13.3.6 transmitting and receiving data......................................................................... 418 13.4 usage notes ............................................................................................................... ........ 425 section 14 a/d converter ................................................................................................. 429 14.1 overview.................................................................................................................. .......... 429 ix 14.1.1 features ................................................................................................................ 429 14.1.2 block diagram...................................................................................................... 430 14.1.3 pin configuration ................................................................................................. 431 14.1.4 register configuration.......................................................................................... 432 14.2 register descriptions..................................................................................................... .... 432 14.2.1 a/d data registers a to d (addra to addrd).............................................. 432 14.2.2 a/d control/status register (adcsr)................................................................ 433 14.2.3 a/d control register (adcr)............................................................................. 435 14.3 cpu interface ............................................................................................................. ....... 436 14.4 operation ................................................................................................................. .......... 438 14.4.1 single mode (scan = 0) ..................................................................................... 438 14.4.2 scan mode (scan = 1) ....................................................................................... 440 14.4.3 input sampling and a/d conversion time.......................................................... 442 14.4.4 external trigger input timing ............................................................................. 443 14.5 interrupts................................................................................................................ ............ 444 14.6 usage notes ............................................................................................................... ........ 444 section 15 d/a converter ................................................................................................. 449 15.1 overview.................................................................................................................. .......... 449 15.1.1 features................................................................................................................ . 449 15.1.2 block diagram...................................................................................................... 450 15.1.3 pin configuration ................................................................................................. 451 15.1.4 register configuration ......................................................................................... 451 15.2 register descriptions..................................................................................................... .... 452 15.2.1 d/a data registers 0 and 1 (dadr0, dadr1).................................................. 452 15.2.2 d/a control register (dacr)............................................................................. 452 15.2.3 d/a standby control register (dastcr) .......................................................... 454 15.3 operation ................................................................................................................. .......... 454 15.4 d/a output control ........................................................................................................ ... 456 section 16 ram ................................................................................................................... 457 16.1 overview.................................................................................................................. .......... 457 16.1.1 block diagram...................................................................................................... 458 16.1.2 register configuration ......................................................................................... 458 16.2 system control register (syscr).................................................................................... 459 16.3 operation ................................................................................................................. .......... 460 section 17 flash memory [h8/3026f-ztat version] ............................................ 461 17.1 overview.................................................................................................................. .......... 461 17.2 features.................................................................................................................. ............ 462 17.2.1 block diagram...................................................................................................... 463 17.2.2 pin configuration ................................................................................................. 464 17.2.3 register configuration ......................................................................................... 464 x 17.3 register descriptions..................................................................................................... .... 465 17.3.1 flash memory control register 1 (flmcr1)..................................................... 465 17.3.2 flash memory control register 2 (flmcr2)..................................................... 468 17.3.3 erase block register 1 (ebr1)............................................................................ 469 17.3.4 erase block register 2 (ebr2)............................................................................ 469 17.3.5 ram control register (ramcr) ....................................................................... 470 17.4 overview of operation ..................................................................................................... . 472 17.4.1 mode transitions.................................................................................................. 472 17.4.2 on-board programming modes ........................................................................... 474 17.4.3 flash memory emulation in ram....................................................................... 476 17.4.4 block configuration ............................................................................................. 477 17.5 on-board programming mode.......................................................................................... 478 17.5.1 boot mode............................................................................................................ 479 17.5.2 user program mode ............................................................................................. 484 17.6 flash memory programming/erasing................................................................................ 486 17.6.1 program mode...................................................................................................... 488 17.6.2 program-verify mode .......................................................................................... 489 17.6.3 erase mode........................................................................................................... 493 17.6.4 erase-verify mode ............................................................................................... 493 17.7 flash memory protection .................................................................................................. 4 95 17.7.1 hardware protection............................................................................................. 495 17.7.2 software protection .............................................................................................. 496 17.7.3 error protection .................................................................................................... 496 17.8 flash memory emulation in ram.................................................................................... 499 17.9 nmi input disabling conditions ....................................................................................... 501 17.10 flash memory prom mode ............................................................................................. 502 17.10.1 socket adapters and memory map...................................................................... 502 17.10.2 notes on use of prom mode.............................................................................. 503 17.11 flash memory programming and erasing precautions ..................................................... 503 17.12 mask rom (h8/3026 mask rom version) overview .................................................... 509 17.12.1 block diagram...................................................................................................... 509 17.13 notes on ordering mask rom version chips.................................................................. 510 17.14 notes when converting the f-ztat application software to the mask rom versions 511 section 18 flash memory [h8/3024f-ztat version] ............................................ 513 18.1 overview.................................................................................................................. .......... 513 18.2 features.................................................................................................................. ............ 514 18.2.1 block diagram...................................................................................................... 515 18.2.2 pin configuration ................................................................................................. 516 18.2.3 register configuration ......................................................................................... 516 18.3 register descriptions..................................................................................................... .... 517 18.3.1 flash memory control register 1 (flmcr1)..................................................... 517 18.3.2 flash memory control register 2 (flmcr2)..................................................... 520 xi 18.3.3 erase block register (ebr)................................................................................. 521 18.3.4 ram control register (ramcr) ....................................................................... 522 18.4 overview of operation ..................................................................................................... . 524 18.4.1 mode transitions.................................................................................................. 524 18.4.2 on-board programming modes ........................................................................... 526 18.4.3 flash memory emulation in ram....................................................................... 528 18.4.4 block configuration ............................................................................................. 529 18.5 on-board programming mode.......................................................................................... 530 18.5.1 boot mode............................................................................................................ 531 18.5.2 user program mode ............................................................................................. 536 18.6 flash memory programming/erasing................................................................................ 538 18.6.1 program mode...................................................................................................... 540 18.6.2 program-verify mode .......................................................................................... 541 18.6.3 erase mode........................................................................................................... 545 18.6.4 erase-verify mode ............................................................................................... 545 18.7 flash memory protection .................................................................................................. 5 47 18.7.1 hardware protection............................................................................................. 547 18.7.2 software protection .............................................................................................. 548 18.7.3 error protection .................................................................................................... 548 18.8 flash memory emulation in ram.................................................................................... 551 18.9 nmi input disabling conditions ....................................................................................... 552 18.10 flash memory prom mode ............................................................................................. 553 18.10.1 socket adapters and memory map...................................................................... 553 18.10.2 notes on use of prom mode.............................................................................. 554 18.11 flash memory programming and erasing precautions ..................................................... 555 18.12 notes when converting the f-ztat application software to the mask rom versions 561 section 19 clock pulse generator .................................................................................. 563 19.1 overview.................................................................................................................. .......... 563 19.1.1 block diagram...................................................................................................... 563 19.2 oscillator circuit ........................................................................................................ ....... 564 19.2.1 connecting a crystal resonator ........................................................................... 564 19.2.2 external clock input ............................................................................................ 566 19.3 duty adjustment circuit................................................................................................... . 568 19.4 prescalers ................................................................................................................ ........... 568 19.5 frequency divider ......................................................................................................... .... 568 19.5.1 register configuration ......................................................................................... 569 19.5.2 division control register (divcr) .................................................................... 569 19.5.3 usage notes.......................................................................................................... 570 section 20 power-down state .......................................................................................... 571 20.1 overview.................................................................................................................. .......... 571 20.2 register configuration .................................................................................................... .. 573 xii 20.2.1 system control register (syscr) ...................................................................... 573 20.2.2 module standby control register h (mstcrh)................................................ 575 20.2.3 module standby control register l (mstcrl)................................................. 576 20.3 sleep mode................................................................................................................ ........ 578 20.3.1 transition to sleep mode ..................................................................................... 578 20.3.2 exit from sleep mode .......................................................................................... 578 20.4 software standby mode .................................................................................................... 5 78 20.4.1 transition to software standby mode.................................................................. 578 20.4.2 exit from software standby mode....................................................................... 579 20.4.3 selection of waiting time for exit from software standby mode...................... 579 20.4.4 sample application of software standby mode.................................................. 581 20.4.5 usage notes.......................................................................................................... 581 20.5 hardware standby mode ................................................................................................... 58 2 20.5.1 transition to hardware standby mode ................................................................ 582 20.5.2 exit from hardware standby mode ..................................................................... 582 20.5.3 timing for hardware standby mode ................................................................... 582 20.6 module standby function.................................................................................................. 5 83 20.6.1 module standby timing....................................................................................... 583 20.6.2 read/write in module standby............................................................................ 583 20.6.3 usage notes.......................................................................................................... 583 20.7 system clock output disabling function ......................................................................... 584 section 21 electrical characteristics .............................................................................. 585 21.1 electrical characteristics of h8/3024 mask rom version and h8/3026 mask rom version ........................................................................................................................ ...... 585 21.1.1 absolute maximum ratings................................................................................. 585 21.1.2 dc characteristics................................................................................................ 586 21.1.3 ac characteristics................................................................................................ 591 21.1.4 a/d conversion characteristics ........................................................................... 595 21.1.5 d/a conversion characteristics ........................................................................... 596 21.2 electrical characteristics of h8/3024f-ztat version and h8/3026f-ztat version ... 597 21.2.1 absolute maximum ratings................................................................................. 597 21.2.2 dc characteristics................................................................................................ 598 21.2.3 ac characteristics................................................................................................ 603 21.2.4 a/d conversion characteristics ........................................................................... 607 21.2.5 d/a conversion characteristics ........................................................................... 608 21.2.6 flash memory characteristics.............................................................................. 609 21.3 operational timing........................................................................................................ .... 611 21.3.1 clock timing........................................................................................................ 611 21.3.2 control signal timing.......................................................................................... 612 21.3.3 bus timing ........................................................................................................... 614 21.3.4 tpc and i/o port timing ..................................................................................... 618 21.3.5 timer input/output timing.................................................................................. 618 xiii 21.3.6 sci input/output timing ..................................................................................... 619 appendix a instruction set .............................................................................................. 621 a.1 instruction list ........................................................................................................... ....... 621 a.2 operation code maps........................................................................................................ 636 a.3 number of states required for execution......................................................................... 639 appendix b internal i/o registers ................................................................................ 648 b.1 address list (h8/3026f-ztat, h8/3026 mask rom version)...................................... 649 b.2 address list (h8/3024f-ztat, h8/3024 mask rom version)...................................... 659 b.3 functions.................................................................................................................. .......... 669 appendix c i/o port block diagrams .......................................................................... 744 c.1 port 1 block diagram....................................................................................................... . 744 c.2 port 2 block diagram....................................................................................................... . 745 c.3 port 3 block diagram....................................................................................................... . 746 c.4 port 4 block diagram....................................................................................................... . 747 c.5 port 5 block diagram....................................................................................................... . 748 c.6 port 6 block diagrams ...................................................................................................... 749 c.7 port 7 block diagrams ...................................................................................................... 754 c.8 port 8 block diagrams ...................................................................................................... 755 c.9 port 9 block diagrams ...................................................................................................... 759 c.10 port a block diagrams..................................................................................................... . 765 c.11 port b block diagrams..................................................................................................... . 768 appendix d pin states ....................................................................................................... 774 d.1 port states in each mode .................................................................................................. 7 74 d.2 pin states at reset........................................................................................................ ...... 778 appendix e timing of transition to and recovery from hardware standby mode ............................................................... 781 appendix f product code lineup ................................................................................. 782 appendix g package dimensions .................................................................................. 783 appendix h comparison of h8/300h series product specifications ................. 786 h.1 comparison of pin functions of 100-pin package products (fp-100b, tfp-100b)........ 786 xiv figures figure 1.1 block diagram..................................................................................................... 6 figure 1.2 pin arrangement of h8/3024f-ztat, h8/3026f-ztat, h8/3024 mask rom version, and h8/3026 mask rom version (fp-100b or tfp-100b package, top view)...................................................... 8 figure 1.3 pin arrangement of h8/3024f-ztat, h8/3026f-ztat, h8/3024 mask rom version, and h8/3026 mask rom version (fp-100a package, top view)............................................................................ 9 figure 2.1 cpu operating modes ........................................................................................ 20 figure 2.2 memory map ....................................................................................................... 21 figure 2.3 cpu registers...................................................................................................... 22 figure 2.4 usage of general registers.................................................................................. 23 figure 2.5 stack ................................................................................................................ .... 24 figure 2.6 general register data formats............................................................................ 26 figure 2.7 general register data formats............................................................................ 27 figure 2.8 memory data formats......................................................................................... 28 figure 2.9 instruction formats.............................................................................................. 41 figure 2.10 memory-indirect branch address specification ................................................. 45 figure 2.11 processing states ................................................................................................. 49 figure 2.12 classification of exception sources.................................................................... 50 figure 2.13 state transitions .................................................................................................. 5 1 figure 2.14 stack structure after exception handling ........................................................... 52 figure 2.15 on-chip memory access cycle.......................................................................... 54 figure 2.16 pin states during on-chip memory access (address update mode 1) ............. 54 figure 2.17 access cycle for on-chip supporting modules ................................................. 55 figure 2.18 pin states during access to on-chip supporting modules................................. 55 figure 3.1 memory map of h8/3024f-ztat and h8/3024 mask rom version in each operating mode...................................................................................... 65 figure 3.2 memory map of h8/3026f-ztat and h8/3026 mask rom version in each operating mode...................................................................................... 67 figure 4.1 exception sources ............................................................................................... 70 figure 4.2 reset sequence (modes 1 and 3)......................................................................... 73 figure 4.3 reset sequence (modes 2 and 4)......................................................................... 74 figure 4.4 reset sequence (mode 6).................................................................................... 75 figure 4.5 interrupt sources and number of interrupts........................................................ 76 figure 4.6 stack after completion of exception handling................................................... 77 figure 4.7 operation when sp value is odd........................................................................ 79 figure 5.1 interrupt controller block diagram .................................................................... 82 figure 5.2 block diagram of interrupts irq 0 to irq 5 .......................................................... 92 figure 5.3 timing of setting of irqnf ................................................................................ 93 figure 5.4 process up to interrupt acceptance when ue = 1 .............................................. 98 figure 5.5 interrupt masking state transitions (example) .................................................. 100 figure 5.6 process up to interrupt acceptance when ue = 0 .............................................. 101 xv figure 5.7 interrupt exception handling sequence.............................................................. 102 figure 5.8 contention between interrupt and interrupt-disabling instruction ..................... 104 figure 6.1 block diagram of bus controller........................................................................ 108 figure 6.2 access area map for each operating mode....................................................... 121 figure 6.3 memory map in 16-mbyte mode (h8/3024f-ztat, h8/3024 mask rom verion) (1) ......................................... 122 figure 6.3 memory map in 16-mbyte mode (h8/3026f-ztat, h8/3026 mask rom verion) (2) ......................................... 123 figure 6.4 csn signal output timing (n = 0 to 7) ............................................................... 125 figure 6.5 sample address output in each address update mode (basic bus interface, 3-state space) ................................................................... 126 figure 6.6 access sizes and data alignment control (8-bit access area)......................... 127 figure 6.7 access sizes and data alignment control (16-bit access area)....................... 128 figure 6.8 bus control signal timing for 8-bit, three-state-access area......................... 130 figure 6.9 bus control signal timing for 8-bit, two-state-access area........................... 131 figure 6.10 bus control signal timing for 16-bit, three-state-access area (1) (byte access to even address) ........................................................................... 132 figure 6.11 bus control signal timing for 16-bit, three-state-access area (2) (byte access to odd address) ............................................................................ 133 figure 6.12 bus control signal timing for 16-bit, three-state-access area (3) (word access) ..................................................................................................... 134 figure 6.13 bus control signal timing for 16-bit, two-state-access area (1) (byte access to even address) ........................................................................... 135 figure 6.14 bus control signal timing for 16-bit, two-state-access area (2) (byte access to odd address) ............................................................................ 136 figure 6.15 bus control signal timing for 16-bit, two-state-access area (3) (word access) ..................................................................................................... 137 figure 6.16 example of wait state insertion timing ............................................................. 138 figure 6.17 example of idle cycle operation (icis1 = 1)..................................................... 139 figure 6.18 example of idle cycle operation (icis0 = 1)..................................................... 140 figure 6.19 example of idle cycle operation ........................................................................ 140 figure 6.20 example of external bus master operation........................................................ 143 figure 6.21 astcr write timing.......................................................................................... 144 figure 6.22 ddr write timing.............................................................................................. 144 figure 6.23 brcr write timing............................................................................................ 145 figure 7.1 port 1 pin configuration...................................................................................... 151 figure 7.2 port 2 pin configuration...................................................................................... 154 figure 7.3 port 3 pin configuration...................................................................................... 158 figure 7.4 port 4 pin configuration...................................................................................... 160 figure 7.5 port 5 pin configuration...................................................................................... 163 figure 7.6 port 6 pin configuration...................................................................................... 167 figure 7.7 port 7 pin configuration...................................................................................... 170 figure 7.8 port 8 pin configuration...................................................................................... 172 xvi figure 7.9 port 9 pin configuration...................................................................................... 177 figure 7.10 port a pin configuration ..................................................................................... 183 figure 7.11 port b pin configuration ..................................................................................... 195 figure 8.1 16-bit timer block diagram (overall) ................................................................. 205 figure 8.2 block diagram of channels 0 and 1.................................................................... 206 figure 8.3 block diagram of channel 2 ............................................................................... 207 figure 8.4 16tcnt access operation [cpu 16tcnt (word)] ..................................... 230 figure 8.5 access to timer counter (cpu reads 16tcnt, word) .................................... 230 figure 8.6 access to timer counter h (cpu writes to 16tcnth, upper byte) ............... 231 figure 8.7 access to timer counter l (cpu writes to 16tcntl, lower byte)................ 231 figure 8.8 access to timer counter h (cpu reads 16tcnth, upper byte) .................... 231 figure 8.9 access to timer counter l (cpu reads 16tcntl, lower byte) .................... 232 figure 8.10 16tcr access (cpu writes to 16tcr) ............................................................. 232 figure 8.11 16tcr access (cpu reads 16tcr) .................................................................. 232 figure 8.12 counter setup procedure (example) ................................................................... 234 figure 8.13 free-running counter operation ........................................................................ 235 figure 8.14 periodic counter operation ................................................................................. 235 figure 8.15 count timing for internal clock sources ........................................................... 236 figure 8.16 count timing for external clock sources (when both edges are detected) ..... 236 figure 8.17 setup procedure for waveform output by compare match (example) ............. 237 figure 8.18 0 and 1 output (toa = 1, tob = 0) ................................................................... 238 figure 8.19 toggle output (toa = 1, tob = 0) ................................................................... 238 figure 8.20 output compare output timing.......................................................................... 239 figure 8.21 setup procedure for input capture (example) .................................................... 240 figure 8.22 input capture (example) ..................................................................................... 240 figure 8.23 input capture signal timing ............................................................................... 241 figure 8.24 setup procedure for synchronization (example) ................................................ 242 figure 8.25 synchronization (example) ................................................................................. 243 figure 8.26 setup procedure for pwm mode (example) ...................................................... 244 figure 8.27 pwm mode (example 1) .................................................................................... 245 figure 8.28 pwm mode (example 2) .................................................................................... 246 figure 8.29 setup procedure for phase counting mode (example)....................................... 247 figure 8.30 operation in phase counting mode (example)................................................... 248 figure 8.31 phase difference, overlap, and pulse width in phase counting mode.............. 248 figure 8.32 timing for setting 16-bit timer output level by writing to tolr ................. 249 figure 8.33 timing of setting of imfa and imfb by compare match................................ 250 figure 8.34 timing of setting of imfa and imfb by input capture.................................... 251 figure 8.35 timing of setting of ovf.................................................................................... 252 figure 8.36 timing of clearing of status flags...................................................................... 252 figure 8.37 contention between 16tcnt write and clear ................................................... 254 figure 8.38 contention between 16tcnt word write and increment ................................. 255 figure 8.39 contention between 16tcnt byte write and increment ................................... 256 figure 8.40 contention between general register write and compare match ..................... 257 xvii figure 8.41 contention between 16tcnt write and overflow ............................................ 258 figure 8.42 contention between general register read and input capture.......................... 259 figure 8.43 contention between counter clearing by input capture and counter increment 260 figure 8.44 contention between general register write and input capture ......................... 261 figure 9.1 block diagram of 8-bit timer unit (two channels: group 0).......................... 269 figure 9.2 8tcnt access operation (cpu writes to 8tcnt, word)................................ 283 figure 9.3 8tcnt access operation (cpu reads 8tcnt, word)..................................... 283 figure 9.4 8tcnt0 access operation (cpu writes to 8tcnt0, upper byte) .................. 283 figure 9.5 8tcnt1 access operation (cpu writes to 8tcnt1, lower byte).................. 284 figure 9.6 8tcnt0 access operation (cpu reads 8tcnt0, upper byte) ....................... 284 figure 9.7 8tcnt1 access operation (cpu reads 8tcnt1, lower byte)....................... 284 figure 9.8 count timing for internal clock input................................................................ 285 figure 9.9 count timing for external clock input (both-edge detection)......................... 286 figure 9.10 timing of timer output ...................................................................................... 286 figure 9.11 timing of clear by compare match.................................................................... 287 figure 9.12 timing of clear by input capture ....................................................................... 287 figure 9.13 timing of input capture input signal ................................................................. 288 figure 9.14 cmf flag setting timing when compare match occurs................................... 288 figure 9.15 cmfb flag setting timing when input capture occurs.................................... 289 figure 9.16 timing of ovf setting........................................................................................ 289 figure 9.17 example of pulse output ..................................................................................... 294 figure 9.18 contention between 8tcnt write and clear ..................................................... 295 figure 9.19 contention between 8tcnt write and increment.............................................. 296 figure 9.20 contention between tcor write and compare match...................................... 297 figure 9.21 contention between tcor read and input capture .......................................... 298 figure 9.22 contention between counter clearing by input capture and counter increment 299 figure 9.23 contention between tcor write and input capture.......................................... 300 figure 9.24 contention between 8tcnt byte write and increment in 16-bit count mode 301 figure 10.1 tpc block diagram ............................................................................................ 306 figure 10.2 tpc output operation......................................................................................... 321 figure 10.3 timing of transfer of next data register contents and output (example) ...... 322 figure 10.4 setup procedure for normal tpc output (example).......................................... 323 figure 10.5 normal tpc output example (five-phase pulse output) .................................. 324 figure 10.6 setup procedure for non-overlapping tpc output (example).......................... 325 figure 10.7 non-overlapping tpc output example (four-phase complementary non-overlapping pulse output) .......................... 326 figure 10.8 tpc output triggering by input capture (example).......................................... 327 figure 10.9 non-overlapping tpc output ............................................................................ 328 figure 10.10 non-overlapping operation and ndr write timing ......................................... 329 figure 11.1 wdt block diagram .......................................................................................... 332 figure 11.2 format of data written to tcnt and tcsr ...................................................... 337 figure 11.3 format of data written to rstcsr.................................................................... 338 figure 11.4 operation in watchdog timer mode .................................................................. 339 xviii figure 11.5 interval timer operation ..................................................................................... 340 figure 11.6 timing of setting of ovf.................................................................................... 340 figure 11.7 timing of setting of wrst bit and internal reset ............................................ 341 figure 11.8 contention between tcnt write and count up ................................................. 342 figure 12.1 sci block diagram.............................................................................................. 345 figure 12.2 data format in asynchronous communication (example: 8-bit data with parity and 2 stop bits) ............................................. 373 figure 12.3 phase relationship between output clock and serial data (asynchronous mode) ......................................................................................... 375 figure 12.4 sample flowchart for sci initialization.............................................................. 376 figure 12.5 sample flowchart for transmitting serial data.................................................. 377 figure 12.6 example of sci transmit operation in asynchronous mode (8-bit data with parity and one stop bit) .......................................................... 378 figure 12.7 sample flowchart for receiving serial data ...................................................... 379 figure 12.8 example of sci receive operation (8-bit data with parity and one stop bit). 382 figure 12.9 example of communication among processors using multiprocessor format (sending data h'aa to receiving processor a)................................................. 383 figure 12.10 sample flowchart for transmitting multiprocessor serial data ........................ 384 figure 12.11 example of sci transmit operation (8-bit data with multiprocessor bit and one stop bit)...................................... 385 figure 12.12 sample flowchart for receiving multiprocessor serial data ............................. 386 figure 12.13 example of sci receive operation (8-bit data with multiprocessor bit and one stop bit)...................................... 388 figure 12.14 data format in synchronous communication .................................................... 389 figure 12.15 sample flowchart for sci initialization.............................................................. 390 figure 12.16 sample flowchart for serial transmitting .......................................................... 391 figure 12.17 example of sci transmit operation ................................................................... 392 figure 12.18 sample flowchart for serial receiving............................................................... 393 figure 12.19 example of sci receive operation .................................................................... 395 figure 12.20 sample flowchart for simultaneous serial transmitting and receiving............ 396 figure 12.21 receive data sampling timing in asynchronous mode .................................... 399 figure 12.22 example of synchronous transmission .............................................................. 400 figure 12.23 operation when switching from sck pin function to port pin function.......... 401 figure 12.24 operation when switching from sck pin function to port pin function (example of preventing low-level output)....................................................... 402 figure 13.1 block diagram of smart card interface.............................................................. 404 figure 13.2 smart card interface connection diagram ......................................................... 412 figure 13.3 smart card interface data format ...................................................................... 413 figure 13.4 timing of tend flag setting ............................................................................. 419 figure 13.5 sample transmission processing flowchart ....................................................... 420 figure 13.6 relation between transmit operation and internal registers ............................ 421 figure 13.7 timing of tend flag setting ............................................................................. 421 figure 13.8 sample reception processing flowchart ............................................................ 422 xix figure 13.9 timing for fixing cock output........................................................................... 423 figure 13.10 procedure for stopping and restarting the clock ............................................... 424 figure 13.11 receive data sampling timing in smart card interface mode.......................... 425 figure 13.12 retransmission in sci receive mode ................................................................. 427 figure 13.13 retransmission in sci transmit mode ............................................................... 427 figure 14.1 a/d converter block diagram............................................................................ 430 figure 14.2 a/d data register access operation (reading h'aa40)................................... 437 figure 14.3 example of a/d converter operation (single mode, channel 1 selected)........ 439 figure 14.4 example of a/d converter operation (scan mode, channels an 0 to an 2 selected) .............................................................................................................. 441 figure 14.5 a/d conversion timing ...................................................................................... 442 figure 14.6 external trigger input timing ............................................................................ 443 figure 14.7 example of analog input protection circuit ....................................................... 445 figure 14.8 analog input pin equivalent circuit ................................................................... 445 figure 14.9 a/d converter accuracy definitions (1) ............................................................ 446 figure 14.10 a/d converter accuracy definitions (2) ............................................................ 447 figure 14.11 analog input circuit (example).......................................................................... 448 figure 15.1 d/a converter block diagram............................................................................ 450 figure 15.2 example of d/a converter operation................................................................. 455 figure 16.1 ram block diagram .......................................................................................... 458 figure 17.1 block diagram of flash memory........................................................................ 463 figure 17.2 flash memory related state transitions ............................................................ 473 figure 17.3 reading overlap ram data in user mode/user program mode ...................... 476 figure 17.4 writing overlap ram data in user program mode .......................................... 477 figure 17.5 system configuration when using boot mode.................................................. 479 figure 17.6 boot mode execution procedure......................................................................... 480 figure 17.7 ram areas in boot mode .................................................................................. 482 figure 17.8 example of user program mode execution procedure ...................................... 485 figure 17.9 flmcr1 bit settings and state transitions ....................................................... 487 figure 17.10 program/program-verify flowchart (128-byte programming).......................... 492 figure 17.11 erase/erase-verify flowchart (single-block erasing) ....................................... 494 figure 17.12 flash memory state transitions (when high level is applied to fwe pin in mode 5 or 7 (on-chip rom enabled)) .......................................................... 498 figure 17.13 flowchart of flash memory emulation in ram ................................................ 499 figure 17.14 example of ram overlap operation.................................................................. 500 figure 17.15 memory map in prom mode ............................................................................ 502 figure 17.16 power-on/off timing (boot mode).................................................................... 506 figure 17.17 power-on/off timing (user program mode) ..................................................... 507 figure 17.18 mode transition timing (example: boot mode user mode ? user program mode).......................... 508 figure 17.19 rom block diagram (h8/3026 mask rom version) ....................................... 509 figure 17.20 mask rom addresses and data.......................................................................... 510 figure 18.1 block diagram of flash memory........................................................................ 515 xx figure 18.2 example of rom area/ram area overlap ....................................................... 523 figure 18.3 flash memory related state transitions ............................................................ 525 figure 18.4 reading overlap ram data in user mode/user program mode ...................... 528 figure 18.5 writing overlap ram data in user program mode .......................................... 529 figure 18.6 system configuration when using boot mode.................................................. 531 figure 18.7 boot mode execution procedure......................................................................... 532 figure 18.8 ram areas in boot mode .................................................................................. 534 figure 18.9 example of user program mode execution procedure ...................................... 537 figure 18.10 flmcr1 bit settings and state transitions ....................................................... 539 figure 18.11 program/program-verify flowchart (128-byte programming).......................... 544 figure 18.12 erase/erase-verify flowchart (single-block erasing) ....................................... 546 figure 18.13 flash memory state transitions (when high level is applied to fwe pin in mode 5 or 7 (on-chip rom enabled)) .......................................................... 550 figure 18.14 example of ram overlap operation.................................................................. 551 figure 18.15 memory map in prom mode ............................................................................ 554 figure 18.16 power-on/off timing (boot mode).................................................................... 558 figure 18.17 power-on/off timing (user program mode) ..................................................... 559 figure 18.18 mode transition timing (example: boot mode user mode ? user program mode).......................... 560 figure 19.1 block diagram of clock pulse generator ........................................................... 563 figure 19.2 connection of crystal resonator (example)....................................................... 564 figure 19.3 crystal resonator equivalent circuit.................................................................. 565 figure 19.4 oscillator circuit block board design precautions............................................ 565 figure 19.5 external clock input (examples) ........................................................................ 566 figure 19.6 external clock input timing ............................................................................... 568 figure 19.7 external clock output settling delay timing .................................................... 568 figure 20.1 nmi timing for software standby mode (example) ......................................... 581 figure 20.2 hardware standby mode timing ........................................................................ 582 figure 20.3 starting and stopping of system clock output .................................................. 584 figure 21.1 darlington pair drive circuit (example) ............................................................ 589 figure 21.2 sample led circuit ............................................................................................ 590 figure 21.3 output load circuit............................................................................................. 594 figure 21.4 darlington pair drive circuit (example) ............................................................ 601 figure 21.5 sample led circuit ............................................................................................ 602 figure 21.6 output load circuit............................................................................................. 606 figure 21.7 oscillator settling timing ................................................................................... 611 figure 21.8 reset input timing .............................................................................................. 612 figure 21.9 reset output timing*.......................................................................................... 612 figure 21.10 interrupt input timing ......................................................................................... 613 figure 21.11 basic bus cycle: two-state access.................................................................... 615 figure 21.12 basic bus cycle: three-state access.................................................................. 616 figure 21.13 basic bus cycle: three-state access with one wait state ................................ 617 figure 21.14 bus-release mode timing .................................................................................. 617 xxi figure 21.15 tpc and i/o port input/output timing............................................................... 618 figure 21.16 timer input/output timing ................................................................................. 618 figure 21.17 timer external clock input timing .................................................................... 619 figure 21.18 sci input clock timing ...................................................................................... 619 figure 21.19 sci input/output timing in synchronous mode ................................................ 619 figure c.1 port 1 block diagram.......................................................................................... 744 figure c.2 port 2 block diagram.......................................................................................... 745 figure c.3 port 3 block diagram.......................................................................................... 746 figure c.4 port 4 block diagram.......................................................................................... 747 figure c.5 port 5 block diagram.......................................................................................... 748 figure c.6 (a) port 6 block diagram (pin p6 0 )........................................................................... 749 figure c.6 (b) port 6 block diagram (pin p6 1 )........................................................................... 750 figure c.6 (c) port 6 block diagram (pin p6 2 )........................................................................... 751 figure c.6 (d) port 6 block diagram (pins p6 3 to p6 6 )............................................................... 752 figure c.6 (e) port 6 block diagram (pin p67).......................................................................... 753 figure c.7 (a) port 7 block diagram (pins p7 0 to p7 5 )............................................................... 754 figure c.7 (b) port 7 block diagram (pins p7 6 and p7 7 )............................................................ 754 figure c.8 (a) port 8 block diagram (pin p8 0 )........................................................................... 755 figure c.8 (b) port 8 block diagram (pins p8 1 and p8 2 )............................................................ 756 figure c.8 (c) port 8 block diagram (pin p8 3 )........................................................................... 757 figure c.8 (d) port 8 block diagram (pin p8 4 )........................................................................... 758 figure c.9 (a) port 9 block diagram (pin p9 0 )........................................................................... 759 figure c.9 (b) port 9 block diagram (pin p9 1 )........................................................................... 760 figure c.9 (c) port 9 block diagram (pin p9 2 )........................................................................... 761 figure c.9 (d) port 9 block diagram (pin p9 3 )........................................................................... 762 figure c.9 (e) port 9 block diagram (pin p9 4 )........................................................................... 763 figure c.9 (f) port 9 block diagram (pin p9 5 )........................................................................... 764 figure c.10 (a)port a block diagram (pins pa 0 and pa 1 ) ......................................................... 765 figure c.10 (b)port a block diagram (pins pa 2 and pa 3 ) ......................................................... 766 figure c.10 (c)port a block diagram (pins pa 4 to pa 7 )............................................................ 767 figure c.11 (a)port b block diagram (pins pb 0 and pb 2 ).......................................................... 768 figure c.11 (b)port b block diagram (pins pb 1 and pb 3 ).......................................................... 769 figure c.11 (c)port b block diagram (pin pb 4 ) ......................................................................... 770 figure c.11 (d)port b block diagram (pin pb 5 ) ......................................................................... 771 figure c.11 (e)port b block diagram (pin pb 6 ) ......................................................................... 772 figure c.11 (f) port b block diagram (pin pb 7 ) ......................................................................... 773 figure d.1 reset during memory access (modes 1 and 2) .................................................. 778 figure d.2 reset during memory access (modes 3 and 4) .................................................. 779 figure d.3 reset during memory access (mode 5).............................................................. 780 figure d.4 reset during operation (modes 6 and 7) ............................................................ 780 figure g.1 package dimensions (fp-100b).......................................................................... 783 figure g.2 package dimensions (tfp-100b) ....................................................................... 784 figure g.3 package dimensions (fp-100a).......................................................................... 785 xxii tables table 1.1 features ............................................................................................................. ... 2 table 1.2 comparison of h8/3024 series pin arrangements .............................................. 7 table 1.3 pin functions........................................................................................................ 10 table 1.4 pin assignments in each mode (fp-100b or tfp-100b, fp-100a) .................. 14 table 2.1 instruction classification...................................................................................... 29 table 2.2 instructions and addressing modes ..................................................................... 30 table 2.3 data transfer instructions .................................................................................... 32 table 2.4 arithmetic operation instructions........................................................................ 33 table 2.5 logic operation instructions................................................................................ 35 table 2.6 shift instructions .................................................................................................. 3 5 table 2.7 bit manipulation instructions............................................................................... 36 table 2.8 branching instructions.......................................................................................... 38 table 2.9 system control instructions ................................................................................. 39 table 2.10 block transfer instruction.................................................................................... 40 table 2.11 addressing modes................................................................................................ 43 table 2.12 absolute address access ranges ........................................................................ 44 table 2.13 effective address calculation.............................................................................. 46 table 2.14 exception handling types and priority ............................................................... 50 table 3.1 operating mode selection.................................................................................... 57 table 3.2 registers ............................................................................................................ ... 58 table 3.3 pin functions in each mode ................................................................................ 63 table 3.4 address maps in mode 5...................................................................................... 64 table 4.1 exception types and priority ............................................................................... 69 table 4.2 exception vector table........................................................................................ 71 table 5.1 interrupt pins ....................................................................................................... .83 table 5.2 interrupt controller registers............................................................................... 83 table 5.3 interrupt sources, vector addresses, and priority ............................................... 94 table 5.4 ue, i, and ui bit settings and interrupt handling ............................................... 97 table 5.5 interrupt response time ...................................................................................... 103 table 6.1 bus controller pins .............................................................................................. 109 table 6.2 bus controller registers ...................................................................................... 110 table 6.3 bus specifications for each area (basic bus interface)...................................... 124 table 6.4 data buses used and valid strobes ..................................................................... 128 table 6.5 pin states in idle cycle ........................................................................................ 141 table 7.1 port functions ...................................................................................................... 1 47 table 7.2 port 1 registers .................................................................................................... 1 51 table 7.3 port 2 registers .................................................................................................... 1 55 table 7.4 input pull-up transistor states (port 2)............................................................... 157 table 7.5 port 3 registers .................................................................................................... 1 58 table 7.6 port 4 registers .................................................................................................... 1 61 table 7.7 input pull-up transistor states (port 4)............................................................... 163 table 7.8 port 5 registers .................................................................................................... 1 64 xxiii table 7.9 input pull-up transistor states (port 5)............................................................... 166 table 7.10 port 6 registers .................................................................................................... 167 table 7.11 port 6 pin functions in modes 1 to 5 ................................................................... 169 table 7.12 port 7 data register.............................................................................................. 17 1 table 7.13 port 8 registers .................................................................................................... 173 table 7.14 port 8 pin functions in modes 1 to 5 ................................................................... 175 table 7.15 port 8 pin functions in modes 6 and 7 ................................................................ 176 table 7.16 port 9 registers .................................................................................................... 178 table 7.17 port 9 pin functions ............................................................................................. 180 table 7.18 port a registers.................................................................................................... 184 table 7.19 port a pin functions (modes 1, 2, 6, and 7) ........................................................ 186 table 7.20 port a pin functions (modes 3 to 5).................................................................... 188 table 7.21 port a pin functions (modes 1 to 7).................................................................... 191 table 7.22 port b registers.................................................................................................... 196 table 7.23 port b pin functions (modes 1 to 5).................................................................... 198 table 7.24 port b pin functions (modes 6 and 7) ................................................................. 200 table 8.1 16-bit timer functions .......................................................................................... 204 table 8.2 16-bit timer pins ................................................................................................... 2 08 table 8.3 16-bit timer registers ........................................................................................... 209 table 8.4 pwm output pins and registers.......................................................................... 243 table 8.5 up/down counting conditions............................................................................ 248 table 8.6 16-bit timer interrupt sources .............................................................................. 253 table 8.7 (a) 16-bit timer operating modes (channel 0) .......................................................... 263 table 8.7 (b) 16-bit timer operating modes (channel 1) .......................................................... 264 table 8.7 (c) 16-bit timer operating modes (channel 2) .......................................................... 265 table 9.1 8-bit timer pins ................................................................................................... 27 0 table 9.2 8-bit timer registers ........................................................................................... 271 table 9.3 operation of channels 0 and 1 when bit ice is set to 1 in 8tcsr1 register.... 281 table 9.4 operation of channels 2 and 3 when bit ice is set to 1 in 8tcsr3 register.... 281 table 9.5 types of 8-bit timer interrupt sources and priority order ................................. 293 table 9.6 8-bit timer interrupt sources .............................................................................. 293 table 9.7 timer output priority order ................................................................................ 302 table 9.8 internal clock switchover and 8tcnt operation .............................................. 303 table 10.1 tpc pins............................................................................................................ ... 307 table 10.2 tpc registers....................................................................................................... 308 table 10.3 tpc operating conditions ................................................................................... 321 table 11.1 wdt pin ............................................................................................................. . 332 table 11.2 wdt registers ..................................................................................................... 33 3 table 11.3 read addresses of tcnt, tcsr, and rstcsr ................................................. 338 table 12.1 sci pins............................................................................................................ .... 346 table 12.2 sci registers....................................................................................................... . 347 table 12.3 examples of bit rates and brr settings in asynchronous mode...................... 363 table 12.4 examples of bit rates and brr settings in synchronous mode ........................ 366 xxiv table 12.5 maximum bit rates for various frequencies (asynchronous mode)................. 368 table 12.6 maximum bit rates with external clock input (asynchronous mode).............. 369 table 12.7 maximum bit rates with external clock input (synchronous mode)................ 370 table 12.8 smr settings and serial communication formats.............................................. 372 table 12.9 smr and scr settings and sci clock source selection.................................... 372 table 12.10 serial communication formats (asynchronous mode)....................................... 374 table 12.11 receive error conditions ..................................................................................... 381 table 12.12 sci interrupt sources ........................................................................................... 397 table 12.13 ssr status flags and transfer of receive data .................................................. 398 table 13.1 smart card interface pins .................................................................................... 404 table 13.2 smart card interface registers ............................................................................ 405 table 13.3 smart card interface register settings ................................................................ 414 table 13.4 n-values of cks1 and cks0 settings ................................................................. 416 table 13.5 bit rates (bits/s) for various brr settings (when n = 0) .................................. 416 table 13.6 brr settings for typical bit rates (bits/s) (when n = 0) ................................... 417 table 13.7 maximum bit rates for various frequencies (smart card interface mode) ...... 417 table 13.8 smart card interface mode operating states and interrupt sources ................... 423 table 14.1 a/d converter pins .............................................................................................. 431 table 14.2 a/d converter registers ...................................................................................... 432 table 14.3 analog input channels and a/d data registers (addra to addrd)............. 433 table 14.4 a/d conversion time (single mode) .................................................................. 443 table 14.5 analog input pin ratings ..................................................................................... 445 table 15.1 d/a converter pins .............................................................................................. 451 table 15.2 d/a converter registers ...................................................................................... 451 table 16.1 h8/3024 series on-chip ram specifications .................................................... 457 table 16.2 system control register....................................................................................... 458 table 17.1 operating modes and rom ................................................................................. 461 table 17.2 flash memory pins............................................................................................... 464 table 17.3 flash memory registers....................................................................................... 464 table 17.4 flash memory erase blocks ................................................................................ 470 table 17.5 flash memory area divisions.............................................................................. 471 table 17.6 on-board programming mode settings............................................................... 478 table 17.7 system clock frequencies for which automatic adjustment of h8/3026f-ztat version bit rate is possible ................................................ 481 table 17.8 hardware protection............................................................................................. 495 table 17.9 software protection .............................................................................................. 496 table 17.10 h8/3026f-ztat version socket adapter product codes .................................. 502 table 18.1 operating modes and rom ................................................................................. 513 table 18.2 flash memory pins............................................................................................... 516 table 18.3 flash memory registers....................................................................................... 516 table 18.4 flash memory erase blocks ................................................................................ 522 table 18.5 ram area setting................................................................................................ 523 table 18.6 on-board programming mode settings............................................................... 530 xxv table 18.7 system clock frequencies for which automatic adjustment of h8/3024f-ztat version bit rate is possible ................................................ 533 table 18.8 hardware protection............................................................................................. 547 table 18.9 software protection .............................................................................................. 548 table 18.10 h8/3024f-ztat version socket adapter product codes .................................. 553 table 19.1 (1) damping resistance value .................................................................................. 564 table 19.1 (2) external capacitance values................................................................................ 564 table 19.2 crystal resonator parameters .............................................................................. 565 table 19.3 (1) clock timing for on-chip flash memory versions ........................................... 567 table 19.3 (2) clock timing for on-chip mask rom versions................................................ 567 table 19.4 frequency division register ................................................................................ 569 table 20.1 power-down state and module standby function .............................................. 572 table 20.2 control register.................................................................................................... 573 table 20.3 clock frequency and waiting time for clock to settle ...................................... 580 table 20.4 pin state in various operating states ............................................................... 584 table 21.1 absolute maximum ratings................................................................................. 585 table 21.2 dc characteristics................................................................................................ 58 6 table 21.3 permissible output currents ................................................................................ 589 table 21.4 clock timing........................................................................................................ 591 table 21.5 control signal timing.......................................................................................... 591 table 21.6 bus timing .......................................................................................................... . 592 table 21.7 timing of on-chip supporting modules ............................................................. 593 table 21.8 a/d conversion characteristics ........................................................................... 595 table 21.9 d/a conversion characteristics ........................................................................... 596 table 21.10 absolute maximum ratings................................................................................. 597 table 21.11 dc characteristics................................................................................................ 5 98 table 21.12 permissible output currents ................................................................................ 601 table 21.13 clock timing....................................................................................................... . 603 table 21.14 control signal timing.......................................................................................... 603 table 21.15 bus timing ......................................................................................................... .. 604 table 21.16 timing of on-chip supporting modules ............................................................. 605 table 21.17 a/d conversion characteristics ........................................................................... 607 table 21.18 d/a conversion characteristics ........................................................................... 608 table 21.19 flash memory characteristics.............................................................................. 609 table a.1 instruction set ...................................................................................................... 623 table a.2 operation code map (1) ...................................................................................... 636 table a.2 operation code map (2) ...................................................................................... 637 table a.2 operation code map (3) ...................................................................................... 638 table a.3 number of states per cycle.................................................................................. 640 table a.4 number of cycles per instruction ........................................................................ 641 table b.1 comparison of h8/3024 series internal i/o register specifications .................. 648 table d.1 port states.......................................................................................................... ... 774 xxvi table f.1 h8/3024 series ..................................................................................................... 78 2 table h.1 pin arrangement of each product (fp-100b, tfp-100b)................................... 786 1 section 1 overview 1.1 overview the h8/3024 series is a series of microcontrollers (mcus) that integrate system supporting functions together with an h8/300h cpu core having an original hitachi architecture. the h8/300h cpu has a 32-bit internal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set designed for speed. it can address a 16-mbyte linear address space. its instruction set is upward-compatible at the object-code level with the h8/300 cpu, enabling easy porting of software from the h8/300 series. the on-chip system supporting functions include rom, ram, a 16-bit timer, an 8-bit timer, a programmable timing pattern controller (tpc), a watchdog timer (wdt), a serial communication interface (sci), an a/d converter, a d/a converter, i/o ports, and other facilities. the four members of the h8/3024 series are the h8/3024f-ztat, h8/3026f-ztat, h8/3024 (mask rom version), and h8/3026 (mask rom version). seven mcu operating modes offer a choice of bus width and address space size. the modes (modes 1 to 7) include two single-chip modes and five expanded modes. in addition to its mask rom versions, the h8/3024 series has f-ztat * versions with on-chip flash memory that allows programs to be freely rewritten by the user. this version enables users to respond quickly and flexibly to changing application specifications, growing production volumes, and other conditions. table 1.1 summarizes the features of the h8/3024 series. note: * f-ztat tm (flexible ztat) is a trademark of hitachi, ltd. 2 table 1.1 features feature description cpu upward-compatible with the h8/300 cpu at the object-code level general-register machine ? maximum clock rate add/ subtract multiply/ divide h8/3024f-ztat h8/3026f-ztat h8/3024 (mask rom version) h8/3026 (mask rom version) 25 mhz 80 ns 560 ns 16-mbyte address space instruction features ? ? ? ? rom ram h8/3024f-ztat h8/3024 (mask rom version) 128 kbytes 4 kbytes h8/3026f-ztat h8/3026 (mask rom version) 256 kbytes 8 kbytes interrupt controller ? irq irq ? ? 3 feature description bus controller ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 4 feature description a/d converter ? ? ? ? ? ? ? ? ? ? mode address space address pins initial bus width max. bus width mode 1 1 mbyte a 19 to a 0 8 bits 16 bits mode 2 1 mbyte a 19 to a 0 16 bits 16 bits mode 3 16 mbytes a 23 to a 0 8 bits 16 bits mode 4 16 mbytes a 23 to a 0 16 bits 16 bits mode 5 16 mbytes a 23 to a 0 8 bits 16 bits mode 6 64 kbytes ? ? ? mode 7 1 mbyte ? ? ? ? ? ? ? ? ? ? ? 5 feature description product lineup product type model package (hitachi package code) h8/3024f-ztat 3.3 v operation HD64F3024f 100-pin qfp (fp-100b) HD64F3024te 100-pin tqfp (tfp-100b) HD64F3024fp 100-pin qfp (fp-100a) h8/3026f-ztat 3.3 v operation hd64f3026f 100-pin qfp (fp-100b) hd64f3026te 100-pin tqfp (tfp-100b) hd64f3026fp 100-pin qfp (fp-100a) h8/3024 mask 3.3 v operation hd6433024f 100-pin qfp (fp-100b) rom version hd6433024te 100-pin tqfp (tfp-100b) hd6433024fp 100-pin qfp (fp-100a) h8/3026 mask 3.3 v operation hd6433026f 100-pin qfp (fp-100b) rom version hd6433026te 100-pin tqfp (tfp-100b) hd6433026fp 100-pin qfp (fp-100a) 6 1.2 block diagram figure 1.1 shows an internal block diagram. v v v v v v v v v cc cc cc ss ss ss ss ss ss p3 /d p3 /d p3 /d p3 /d p3 /d p3 /d p3 /d p3 /d 7 6 5 4 3 2 1 0 p4 /d p4 /d p4 /d p4 /d p4 /d p4 /d p4 /d p4 /d 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 port 3 port 4 port 5 port 9 p5 /a p5 /a p5 /a p5 /a 3 2 1 0 19 18 17 16 p2 /a p2 /a p2 /a p2 /a p2 /a p2 /a p2 /a p2 /a 7 6 5 4 3 2 1 0 p9 /sck /irq p9 /sck /irq p9 /rxd p9 /rxd p9 /txd p9 /txd 5 4 3 2 1 0 1 0 1 0 1 0 5 4 da 1 /an 7 /p7 7 da 0 /an 6 /p7 6 an 5 /p7 5 an 4 /p7 4 an 3 /p7 3 an 2 /p7 2 an 1 /p7 1 an 0 /p7 0 port 7 a 20 /tiocb 2 /tp 7 /pa 7 a 21 /tioca 2 /tp 6 /pa 6 a 22 /tiocb 1 /tp 5 /pa 5 a 23 /tioca 1 /tp 4 /pa 4 tclkd/tiocb 0 /tp 3 /pa 3 tclkc/tioca 0 /tp 2 /pa 2 tclkb/tp 1 /pa 1 tclka/tp 0 /pa 0 port a tp 15 /pb 7 tp 14 /pb 6 tp 13 /pb 5 tp 12 /pb 4 cs 4 /tmio 3 /tp 11 /pb 3 cs 5 /tmo 2 /tp 10 /pb 2 cs 6 /tmio 1 /tp 9 /pb 1 cs 7 /tmo 0 /tp 8 /pb 0 port 8 cs 0 /p8 4 adtrg/cs 1 /irq 3 /p8 3 cs 2 /irq 2 /p8 2 cs 3 /irq 1 /p8 1 irq 0 /p8 0 md md md extal xtal stby res reso /fwe * nmi 2 1 0 h8/300h cpu clock pulse generator interrupt controller rom (mask rom or flash memory) serial communication interface (sci) 2 channels watchdog timer (wdt) 15 14 13 12 11 10 9 8 address bus data bus (upper) data bus (lower) 15 14 13 12 11 10 9 8 port 2 p1 /a p1 /a p1 /a p1 /a p1 /a p1 /a p1 /a p1 /a 7 6 5 4 3 2 1 0 port 1 7 6 5 4 3 2 1 0 /p6 7 lwr/p6 6 hwr/p6 5 rd/p6 4 as/p6 3 back/p6 2 breq/p6 1 wait/p6 0 ram 16-bit timer unit 8-bit timer unit a/d converter d/a converter port 6 bus controller programmable timing pattern controller (tpc) port b v ref av cc av ss note: * functions as reso in the mask rom versions, and as fwe in the on-chip flash memory versions. figure 1.1 block diagram 7 1.3 pin description 1.3.1 pin arrangement the pin arrangement of the h8/3024 series is shown in figures 1.2 to 1.5. differences in the h8/3024 series pin arrangements are shown in table 1.2. except for the differences shown in table 1.2, the pin arrangements are the same. table 1.2 comparison of h8/3024 series pin arrangements package pin number h8/3024f-ztat h8/3026f-ztat h8/3024 mask rom version h8/3026 mask rom version fp-100b (tfp-100b) 10 fwe fwe reso reso fp-100a 12 fwe fwe reso reso 8 v cc cs 7 /tmo 0 /tp 8 /pb 0 cs 6 / tmio 1 /tp 9 /pb 1 cs 5 /tmo 2 /tp 10 /pb 2 cs 4 / tmio 3 /tp 11 /pb 3 tp 12 /pb 4 tp 13 /pb 5 tp 14 /pb 6 tp 15 /pb 7 0 1 2 3 4 5 0 1 2 3 4 5 6 reso /fwe * v ss txd /p9 txd /p9 rxd /p9 rxd /p9 irq /sck /p9 irq /sck /p9 d /p4 d /p4 d /p4 d /p4 d /p4 d /p4 d /p4 md md md p6 /lwr p6 /hwr p6 /rd p6 /as v xtal extal v nmi res stby p6 7 / p6 /back p6 /breq p6 /wait v p5 /a p5 /a p5 /a p5 /a p2 /a p2 /a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 0 1 0 1 0 1 0 1 2 3 4 5 6 4 5 2 1 0 2 1 0 3 2 1 0 7 6 cs 2 /irq 2 /p8 2 adtrg/cs 1 /irq 3 /p8 3 cs 0 /p8 4 v ss tclka/tp 0 /pa 0 tclkb/tp 1 /pa 1 tclkc/tioca 0 /tp 2 /pa 2 tclkd/tiocb 0 /tp 3 /pa 3 a 23 /tioca 1 /tp 4 /pa 4 a 22 /tiocb 1 /tp 5 /pa 5 a 21 /tioca 2 /tp 6 /pa 6 a 20 /tiocb 2 /tp 7 /pa 7 /p8 /irq cs /p8 irq av p7 /an /da p7 /an /da p7 /an p7 /an p7 /an p7 /an p7 /an p7 /an v av 1 0 7 6 5 4 3 2 1 0 1 0 7 6 5 4 3 2 1 0 d 7 /p4 7 d 8 /p3 0 d 9 /p3 1 d 10 /p3 2 d 11 /p3 3 d 12 /p3 4 d 13 /p3 5 d 14 /p3 6 d 15 /p3 7 p1 0 /a 0 p1 1 /a 1 p1 2 /a 2 p1 3 /a 3 p1 4 /a 4 p1 5 /a 5 p1 6 /a 6 p1 7 /a 7 p2 0 /a 8 p2 1 /a 9 p2 2 /a 10 p2 3 /a 11 p2 4 /a 12 p2 5 /a 13 top view (fp-100b, tfp-100b) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 6 5 4 3 cc ss ss 19 18 17 16 15 14 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ss ref cc 1 0 v ss v cc v ss 3 note: * functions as the res0 pin in the mask rom version, and as the fwe pin in the f-ztat version. figure 1.2 pin arrangement of h8/3024f-ztat, h8/3026f-ztat, h8/3024 mask rom version, and h8/3026 mask rom version (fp-100b or tfp-100b package, top view) 9 p7 0 /an 0 v ref av cc md 2 md 1 md 0 p6 6 /lwr p6 5 /hwr p6 4 /rd p6 3 /as v cc xtal extal v ss nmi res stby p6 7 / p6 2 /back p6 1 /breq p6 0 /wait v ss p5 3 /a 19 p5 2 /a 18 p5 1 /a 17 p5 0 /a 16 p2 7 /a 15 p2 6 /a 14 p2 5 /a 13 p2 4 /a 12 a /tioca /tp /pa a /tiocb /tp /pa cs /tmo /tp /pb cs /tmio /tp /pb cs /tmo /tp /pb cs /tmio /tp /pb tp /pb tp /pb tp /pb tp /pb reso /fwe * txd /p9 txd /p9 rxd /p9 rxd /p9 irq /sck /p9 irq /sck /p9 d /p4 d /p4 d /p4 d /p4 d /p4 d /p4 d /p4 d /p4 d /p3 d /p3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 p7 1 /an 1 p7 2 /an 2 p7 3 /an 3 p7 4 /an 4 p7 5 /an 5 p7 6 /an 6 /da 0 p7 7 /an 7 /da 1 av ss p8 0 /irq 0 p8 1 /irq 1 /cs 3 p8 2 /irq 2 /cs 2 p8 3 /irq 3 /cs 1 /adtrg p8 4 /cs 0 v ss pa 0 /tp 0 /tclka pa 1 /tp 1 /tclkb pa 2 /tp 2 /tioca 0 /tclkc pa 3 /tp 3 /tiocb 0 /tclkd pa 4 /tp 4 /tioca 1 /a 23 pa 5 /tp 5 /tiocb 1 /a 22 21 26 6 20 27 7 08 0 19 1 11 3 4 3 15 7 4 12 5 13 6 14 7 210 2 5 6 ss 0 1 0 1 404 515 0 1 0 1 2 3 0 1 2 3 2 3 4 5 6 4 5 6 7 7 0 8 1 9 v ss p2 3 /a 11 p2 2 /a 10 p2 1 /a 9 p2 0 /a 8 p1 7 /a 7 p1 6 /a 6 p1 5 /a 5 p1 4 /a 4 p1 3 /a 3 p1 2 /a 2 p1 1 /a 1 p1 0 /a 0 d /p3 d /p3 d /p3 d /p3 d /p3 d /p3 10 2 11 3 12 4 13 5 15 14 6 v cc v ss 7 80 79 78 77 76 v top view (fp-100a) note: * functions as the res0 pin in the mask rom version, and as the fwe pin in the f-ztat version. v cc figure 1.3 pin arrangement of h8/3024f-ztat, h8/3026f-ztat, h8/3024 mask rom version, and h8/3026 mask rom version (fp-100a package, top view) 10 1.3.2 pin functions table 1.3 summarizes the pin functions. table 1.3 pin functions pin no. type symbol fp-100b tfp-100b fp-100a i/o name and function power v cc 1, 35, 68 3, 37, 70 input power: for connection to the power supply. connect all v cc pins to the system power supply. v ss 11, 22, 44, 57, 65, 92 13, 24, 46, 59, 67, 94 input ground: for connection to ground (0 v). connect all v ss pins to the 0-v system power supply. clock xtal 67 69 input for connection to a crystal resonator. for examples of crystal resonator and external clock input, see section 19, clock pulse generator. extal 66 68 input for connection to a crystal resonator or input of an external clock signal. for examples of crystal resonator and external clock input, see section 19, clock pulse generator. 61 63 output system clock: supplies the system clock to external devices. operating mode control md 2 to md 0 75 to 73 77 to 75 input mode 2 to mode 0: for setting the operating mode, as follows. inputs at these pins must not be changed during operation. md 2 md 1 md 0 operating mode 0 0 0 setting prohibited 0 0 1 mode 1 0 1 0 mode 2 0 1 1 mode 3 1 0 0 mode 4 1 0 1 mode 5 1 1 0 mode 6 1 1 1 mode 7 11 pin no. type symbol fp-100b tfp-100b fp-100a i/o name and function system control res 63 65 input reset input: when driven low, this pin resets the chip. this pin must be driven low at power- up. reso 10 12 output reset output (on-chip mask rom versions): outputs the reset signal generated by the watchdog timer to external devices fwe 10 12 input write enable signal (on-chip flash memory versions): flash memory programming control signal stby 62 64 input standby: when driven low, this pin forces a transition to hardware standby mode breq 59 61 input bus request: used by an external bus master to request the bus right back 60 62 output bus request acknowledge: indicates that the bus has been granted to an external bus master interrupts nmi 64 66 input nonmaskable interrupt: requests a nonmaskable interrupt irq 5 to irq 0 17, 16, 90 to 87 19, 18, 92 to 89 input interrupt request 5 to 0: maskable interrupt request pins address bus a 23 to a 0 97 to 100, 56 to 45, 43 to 36 99, 100, 1, 2, 58 to 47, 45 to 38 output address bus: outputs address signals data bus d 15 to d 0 34 to 23, 21 to 18 36 to 25, 23 to 20 input/ output data bus: bidirectional data bus bus control cs 7 to cs 0 2 to 5, 88 to 91 4 to 7, 90 to 93 output chip select: select signals for areas 7 to 0 as 69 71 output address strobe: goes low to indicate valid address output on the address bus rd 70 72 output read: goes low to indicate reading from the external address space hwr 71 73 output high write: goes low to indicate writing to the external address space; indicates valid data on the upper data bus (d 15 to d 8 ). lwr 72 74 output low write: goes low to indicate writing to the external address space; indicates valid data on the lower data bus (d 7 to d 0 ). wait 58 60 input wait: requests insertion of wait states in bus cycles during access to the external address space 12 pin no. type symbol fp-100b tfp-100b fp-100a i/o name and function 16-bit timer tclkd to tclka 96 to 93 98 to 95 input clock input d to a: external clock inputs tioca 2 to tioca 0 99, 97, 95 1, 99, 97 input/ output input capture/output compare a2 to a0: gra2 to gra0 output compare or input capture, or pwm output tiocb 2 to tiocb 0 100, 98, 96 2, 100, 98 input/ output input capture/output compare b2 to b0: grb2 to grb0 output compare or input capture 8-bit timer tmo 0 , tmo 2 2, 4 4, 6 output compare match output: compare match output pins tmio 1 , tmio 3 3, 5 5, 7 input/ output input capture input/compare match output: input capture input or compare match output pins tclkd to tclka 96 to 93 98 to 95 input counter external clock input: these pins input an external clock to the counters. program- mable timing pattern controller (tpc) tp 15 to tp 0 9 to 2, 100 to 93 11 to 4, 2, 1, 100 to 95 output tpc output 15 to 0: pulse output serial communi- txd 1 , txd 0 13, 12 15, 14 output transmit data (channels 0, 1): sci data output cation interface (sci) rxd 1 , rxd 0 15, 14 17, 16 input receive data (channels 0, 1): sci data input sck 1 , sck 0 17, 16 19, 18 input/ output serial clock (channels 0, 1): sci clock input/output a/d converter an 7 to an 0 85 to 78 87 to 80 input analog 7 to 0: analog input pins adtrg 90 92 input a/d conversion external trigger input: external trigger input for starting a/d conversion d/a converter da 1 , da 0 85, 84 87, 86 output analog output: analog output from the d/a converter analog power supply av cc 76 78 input power supply pin for the a/d and d/a converters. connect to the system power supply when not using the a/d and d/a converters. 13 pin no. type symbol fp-100b tfp-100b fp-100a i/o name and function analog power av ss 86 88 input ground pin for the a/d and d/a converters. connect to system ground (0 v). supply v ref 77 79 input reference voltage input pin for the a/d and d/a converters. connect to the system power supply when not using the a/d and d/a converters. i/o ports p1 7 to p1 0 43 to 36 45 to 38 input/ output port 1: eight input/output pins. the direction of each pin can be selected in the port 1 data direction register (p1ddr). p2 7 to p2 0 52 to 45 54 to 47 input/ output port 2: eight input/output pins. the direction of each pin can be selected in the port 2 data direction register (p2ddr). p3 7 to p3 0 34 to 27 36 to 29 input/ output port 3: eight input/output pins. the direction of each pin can be selected in the port 3 data direction register (p3ddr). p4 7 to p4 0 26 to 23, 21 to 18 28 to 25, 23 to 20 input/ output port 4: eight input/output pins. the direction of each pin can be selected in the port 4 data direction register (p4ddr). p5 3 to p5 0 56 to 53 58 to 55 input/ output port 5: four input/output pins. the direction of each pin can be selected in the port 5 data direction register (p5ddr). p6 7 to p6 0 61, 72 to 69, 60 to 58 63, 74 to 71, 62 to 60 input/ output port 6: eight input/output pins. the direction of each pin can be selected in the port 6 data direction register (p6ddr). p7 7 to p7 0 85 to 78 87 to 80 input port 7: eight input pins p8 4 to p8 0 91 to 87 93 to 89 input/ output port 8: five input/output pins. the direction of each pin can be selected in the port 8 data direction register (p8ddr). p9 5 to p9 0 17 to 12 19 to 14 input/ output port 9: six input/output pins. the direction of each pin can be selected in the port 9 data direction register (p9ddr). pa 7 to pa 0 100 to 93 2, 1, 100 to 95 input/ output port a: eight input/output pins. the direction of each pin can be selected in the port a data direction register (paddr). pb 7 to pb 0 9 to 2 11 to 4 input/ output port b: eight input/output pins. the direction of each pin can be selected in the port b data direction register (pbddr). 14 1.3.3 pin assignments in each mode table 1.4 lists the pin assignments in each mode. table 1.4 pin assignments in each mode (fp-100b or tfp-100b, fp-100a) pin no. pin name fp-100b tfp-100b fp-100a mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 13v cc v cc v cc v cc v cc v cc v cc 24pb 0 /tp 8 / tmo 0 / cs 7 pb 0 /tp 8 / tmo 0 / cs 7 pb 0 /tp 8 / tmo 0 / cs 7 pb 0 /tp 8 / tmo 0 / cs 7 pb 0 /tp 8 / tmo 0 / cs 7 pb 0 /tp 8 / tmo 0 pb 0 /tp 8 / tmo 0 35pb 1 /tp 9 / tmio 1 / cs 6 pb 1 /tp 9 / tmio 1 / cs 6 pb 1 /tp 9 / tmio 1 / cs 6 pb 1 /tp 9 / tmio 1 / cs 6 pb 1 /tp 9 / tmio 1 / cs 6 pb 1 /tp 9 / tmio 1 pb 1 /tp 9 / tmio 1 46pb 2 /tp 10 / tmo 2 / cs 5 pb 2 /tp 10 / tmo 2 / cs 5 pb 2 /tp 10 / tmo 2 / cs 5 pb 2 /tp 10 / tmo 2 / cs 5 pb 2 /tp 10 / tmo 2 / cs 5 pb 2 /tp 10 / tmo 2 pb 2 /tp 10 / tmo 2 57pb 3 /tp 11 / tmio 3 / cs 4 pb 3 /tp 11 / tmio 3 / cs 4 pb 3 /tp 11 / tmio 3 / cs 4 pb 3 /tp 11 / tmio 3 / cs 4 pb 3 /tp 11 / tmio 3 / cs 4 pb 3 /tp 11 / tmio 3 pb 3 /tp 11 / tmio 3 68pb 4 /tp 12 pb 4 /tp 12 pb 4 /tp 12 pb 4 /tp 12 pb 4 /tp 12 pb 4 /tp 12 pb 4 /tp 12 79pb 5 /tp 13 pb 5 /tp 13 pb 5 /tp 13 pb 5 /tp 13 pb 5 /tp 13 pb 5 /tp 13 pb 5 /tp 13 810pb 6 /tp 14 pb 6 /tp 14 pb 6 /tp 14 pb 6 /tp 14 pb 6 /tp 14 pb 6 /tp 14 pb 6 /tp 14 911pb 7 /tp 15 pb 7 /tp 15 pb 7 /tp 15 pb 7 /tp 15 pb 7 /tp 15 pb 7 /tp 15 pb 7 /tp 15 10 12 reso / fwe* 3 reso / fwe* 3 reso / fwe* 3 reso / fwe* 3 reso / fwe* 3 reso / fwe* 3 reso / fwe* 3 11 13 v ss v ss v ss v ss v ss v ss v ss 12 14 p9 0 /txd 0 p9 0 /txd 0 p9 0 /txd 0 p9 0 /txd 0 p9 0 /txd 0 p9 0 /txd 0 p9 0 /txd 0 13 15 p9 1 /txd 1 p9 1 /txd 1 p9 1 /txd 1 p9 1 /txd 1 p9 1 /txd 1 p9 1 /txd 1 p9 1 /txd 1 14 16 p9 2 /rxd 0 p9 2 /rxd 0 p9 2 /rxd 0 p9 2 /rxd 0 p9 2 /rxd 0 p9 2 /rxd 0 p9 2 /rxd 0 15 17 p9 3 /rxd 1 p9 3 /rxd 1 p9 3 /rxd 1 p9 3 /rxd 1 p9 3 /rxd 1 p9 3 /rxd 1 p9 3 /rxd 1 16 18 p9 4 /sck 0 / irq 4 p9 4 /sck 0 / irq 4 p9 4 /sck 0 / irq 4 p9 4 /sck 0 / irq 4 p9 4 /sck 0 / irq 4 p9 4 /sck 0 / irq 4 p9 4 /sck 0 / irq 4 17 19 p9 5 /sck 1 / irq 5 p9 5 /sck 1 / irq 5 p9 5 /sck 1 / irq 5 p9 5 /sck 1 / irq 5 p9 5 /sck 1 / irq 5 p9 5 /sck 1 / irq 5 p9 5 /sck 1 / irq 5 18 20 p4 0 /d 0 * 1 p4 0 /d 0 * 2 p4 0 /d 0 * 1 p4 0 /d 0 * 2 p4 0 /d 0 * 1 p4 0 p4 0 19 21 p4 1 /d 1 * 1 p4 1 /d 1 * 2 p4 1 /d 1 * 1 p4 1 /d 1 * 2 p4 1 /d 1 * 1 p4 1 p4 1 20 22 p4 2 /d 2 * 1 p4 2 /d 2 * 2 p4 2 /d 2 * 1 p4 2 /d 2 * 2 p4 2 /d 2 * 1 p4 2 p4 2 21 23 p4 3 /d 3 * 1 p4 3 /d 3 * 2 p4 3 /d 3 * 1 p4 3 /d 3 * 2 p4 3 /d 3 * 1 p4 3 p4 3 22 24 v ss v ss v ss v ss v ss v ss v ss 23 25 p4 4 /d 4 * 1 p4 4 /d 4 * 2 p4 4 /d 4 * 1 p4 4 /d 4 * 2 p4 4 /d 4 * 1 p4 4 p4 4 24 26 p4 5 /d 5 * 1 p4 5 /d 5 * 2 p4 5 /d 5 * 1 p4 5 /d 5 * 2 p4 5 /d 5 * 1 p4 5 p4 5 15 pin no. pin name fp-100b tfp-100b fp-100a mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 25 27 p4 6 /d 6 * 1 p4 6 /d 6 * 2 p4 6 /d 6 * 1 p4 6 /d 6 * 2 p4 6 /d 6 * 1 p4 6 p4 6 26 28 p4 7 /d 7 * 1 p4 7 /d 7 * 2 p4 7 /d 7 * 1 p4 7 /d 7 * 2 p4 7 /d 7 * 1 p4 7 p4 7 27 29 d 8 d 8 d 8 d 8 d 8 p3 0 p3 0 28 30 d 9 d 9 d 9 d 9 d 9 p3 1 p3 1 29 31 d 10 d 10 d 10 d 10 d 10 p3 2 p3 2 30 32 d 11 d 11 d 11 d 11 d 11 p3 3 p3 3 31 33 d 12 d 12 d 12 d 12 d 12 p3 4 p3 4 32 34 d 13 d 13 d 13 d 13 d 13 p3 5 p3 5 33 35 d 14 d 14 d 14 d 14 d 14 p3 6 p3 6 34 36 d 15 d 15 d 15 d 15 d 15 p3 7 p3 7 35 37 v cc v cc v cc v cc v cc v cc v cc 36 38 a 0 a 0 a 0 a 0 p1 0 /a 0 p1 0 p1 0 37 39 a 1 a 1 a 1 a 1 p1 1 /a 1 p1 1 p1 1 38 40 a 2 a 2 a 2 a 2 p1 2 /a 2 p1 2 p1 2 39 41 a 3 a 3 a 3 a 3 p1 3 /a 3 p1 3 p1 3 40 42 a 4 a 4 a 4 a 4 p1 4 /a 4 p1 4 p1 4 41 43 a 5 a 5 a 5 a 5 p1 5 /a 5 p1 5 p1 5 42 44 a 6 a 6 a 6 a 6 p1 6 /a 6 p1 6 p1 6 43 45 a 7 a 7 a 7 a 7 p1 7 /a 7 p1 7 p1 7 44 46 v ss v ss v ss v ss v ss v ss v ss 45 47 a 8 a 8 a 8 a 8 p2 0 /a 8 p2 0 p2 0 46 48 a 9 a 9 a 9 a 9 p2 1 /a 9 p2 1 p2 1 47 49 a 10 a 10 a 10 a 10 p2 2 /a 10 p2 2 p2 2 48 50 a 11 a 11 a 11 a 11 p2 3 /a 11 p2 3 p2 3 49 51 a 12 a 12 a 12 a 12 p2 4 /a 12 p2 4 p2 4 50 52 a 13 a 13 a 13 a 13 p2 5 /a 13 p2 5 p2 5 51 53 a 14 a 14 a 14 a 14 p2 6 /a 14 p2 6 p2 6 52 54 a 15 a 15 a 15 a 15 p2 7 /a 15 p2 7 p2 7 53 55 a 16 a 16 a 16 a 16 p5 0 /a 16 p5 0 p5 0 54 56 a 17 a 17 a 17 a 17 p5 1 /a 17 p5 1 p5 1 55 57 a 18 a 18 a 18 a 18 p5 2 /a 18 p5 2 p5 2 56 58 a 19 a 19 a 19 a 19 p5 3 /a 19 p5 3 p5 3 57 59 v ss v ss v ss v ss v ss v ss v ss 58 60 p6 0 / wait p6 0 / wait p6 0 / wait p6 0 / wait p6 0 / wait p6 0 p6 0 16 pin no. pin name fp-100b tfp-100b fp-100a mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 59 61 p6 1 / breq p6 1 / breq p6 1 / breq p6 1 / breq p6 1 / breq p6 1 p6 1 60 62 p6 2 / back p6 2 / back p6 2 / back p6 2 / back p6 2 / back p6 2 p6 2 61 63 ? ? p6 7 / p6 7 / p6 7 / 62 64 stby stby stby stby stby stby stby 63 65 res res res res res res res 64 66 nmi nmi nmi nmi nmi nmi nmi 65 67 v ss v ss v ss v ss v ss v ss v ss 66 68 extal extal extal extal extal extal extal 67 69 xtal xtal xtal xtal xtal xtal xtal 68 70 v cc v cc v cc v cc v cc v cc v cc 69 71 as as as as as p6 3 p6 3 70 72 rd rd rd rd rd p6 4 p6 4 71 73 hwr hwr hwr hwr hwr p6 5 p6 5 72 74 lwr lwr lwr lwr lwr p6 6 p6 6 73 75 md 0 md 0 md 0 md 0 md 0 md 0 md 0 74 76 md 1 md 1 md 1 md 1 md 1 md 1 md 1 75 77 md 2 md 2 md 2 md 2 md 2 md 2 md 2 76 78 av cc av cc av cc av cc av cc av cc av cc 77 79 v ref v ref v ref v ref v ref v ref v ref 78 80 p7 0 /an 0 p7 0 /an 0 p7 0 /an 0 p7 0 /an 0 p7 0 /an 0 p7 0 /an 0 p7 0 /an 0 79 81 p7 1 /an 1 p7 1 /an 1 p7 1 /an 1 p7 1 /an 1 p7 1 /an 1 p7 1 /an 1 p7 1 /an 1 80 82 p7 2 /an 2 p7 2 /an 2 p7 2 /an 2 p7 2 /an 2 p7 2 /an 2 p7 2 /an 2 p7 2 /an 2 81 83 p7 3 /an 3 p7 3 /an 3 p7 3 /an 3 p7 3 /an 3 p7 3 /an 3 p7 3 /an 3 p7 3 /an 3 82 84 p7 4 /an 4 p7 4 /an 4 p7 4 /an 4 p7 4 /an 4 p7 4 /an 4 p7 4 /an 4 p7 4 /an 4 83 85 p7 5 /an 5 p7 5 /an 5 p7 5 /an 5 p7 5 /an 5 p7 5 /an 5 p7 5 /an 5 p7 5 /an 5 84 86 p7 6 /an 6 /da 0 p7 6 /an 6 /da 0 p7 6 /an 6 /da 0 p7 6 /an 6 /da 0 p7 6 /an 6 /da 0 p7 6 /an 6 /da 0 p7 6 /an 6 /da 0 85 87 p7 7 /an 7 /da 1 p7 7 /an 7 /da 1 p7 7 /an 7 /da 1 p7 7 /an 7 /da 1 p7 7 /an 7 /da 1 p7 7 /an 7 /da 1 p7 7 /an 7 /da 1 86 88 av ss av ss av ss av ss av ss av ss av ss 87 89 p8 0 / irq 0 p8 0 / irq 0 p8 0 / irq 0 p8 0 / irq 0 p8 0 / irq 0 p8 0 / irq 0 p8 0 / irq 0 88 90 p8 1 / irq 1 / cs 3 p8 1 / irq 1 / cs 3 p8 1 / irq 1 / cs 3 p8 1 / irq 1 / cs 3 p8 1 / irq 1 / cs 3 p8 1 / irq 1 p8 1 / irq 1 89 91 p8 2 / irq 2 / cs 2 p8 2 / irq 2 / cs 2 p8 2 / irq 2 / cs 2 p8 2 / irq 2 / cs 2 p8 2 / irq 2 / cs 2 p8 2 / irq 2 p8 2 / irq 2 17 pin no. pin name fp-100b tfp-100b fp-100a mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 90 92 p8 3 / irq 3 / cs 1 / adtrg p8 3 / irq 3 / cs 1 / adtrg p8 3 / irq 3 / cs 1 / adtrg p8 3 / irq 3 / cs 1 / adtrg p8 3 / irq 3 / cs 1 / adtrg p8 3 / irq 3 / adtrg p8 3 / irq 3 / adtrg 91 93 p8 4 / cs 0 p8 4 / cs 0 p8 4 / cs 0 p8 4 / cs 0 p8 4 / cs 0 p8 4 p8 4 92 94 v ss v ss v ss v ss v ss v ss v ss 93 95 pa 0 /tp 0 / tclka pa 0 /tp 0 / tclka pa 0 /tp 0 / tclka pa 0 /tp 0 / tclka pa 0 /tp 0 / tclka pa 0 /tp 0 / tclka pa 0 /tp 0 / tclka 94 96 pa 1 /tp 1 / tclkb pa 1 /tp 1 / tclkb pa 1 /tp 1 /tclkb pa 1 /tp 1 / tclkb pa 1 /tp 1 / tclkb pa 1 /tp 1 / tclkb pa 1 /tp 1 / tclkb 95 97 pa 2 /tp 2 / tioca 0 / tclkc pa 2 /tp 2 / tioca 0 / tclkc pa 2 /tp 2 / tioca 0 / tclkc pa 2 /tp 2 / tioca 0 / tclkc pa 2 /tp 2 / tioca 0 / tclkc pa 2 /tp 2 / tioca 0 / tclkc pa 2 /tp 2 / tioca 0 / tclkc 96 98 pa 3 /tp 3 / tiocb 0 / tclkd pa 3 /tp 3 / tiocb 0 / tclkd pa 3 /tp 3 / tiocb 0 / tclkd pa 3 /tp 3 / tiocb 0 / tclkd pa 3 /tp 3 / tiocb 0 / tclkd pa 3 /tp 3 / tiocb 0 / tclkd pa 3 /tp 3 / tiocb 0 / tclkd 97 99 pa 4 /tp 4 / tioca 1 pa 4 /tp 4 / tioca 1 pa 4 /tp 4 / tioca 1 /a 23 pa 4 /tp 4 / tioca 1 /a 23 pa 4 /tp 4 / tioca 1 /a 23 pa 4 /tp 4 / tioca 1 pa 4 /tp 4 / tioca 1 98 100 pa 5 /tp 5 / tiocb 1 pa 5 /tp 5 / tiocb 1 pa 5 /tp 5 / tiocb 1 /a 22 pa 5 /tp 5 / tiocb 1 /a 22 pa 5 /tp 5 / tiocb 1 /a 22 pa 5 /tp 5 / tiocb 1 pa 5 /tp 5 / tiocb 1 99 1 pa 6 /tp 6 / tioca 2 pa 6 /tp 6 / tioca 2 pa 6 /tp 6 / tioca 2 /a 21 pa 6 /tp 6 / tioca 2 /a 21 pa 6 /tp 6 / tioca 2 /a 21 pa 6 /tp 6 / tioca 2 pa 6 /tp 6 / tioca 2 100 2 pa 7 /tp 7 / tiocb 2 pa 7 /tp 7 / tiocb 2 a 20 a 20 pa 7 /tp 7 / tiocb 2 /a 20 pa 7 /tp 7 / tiocb 2 pa 7 /tp 7 / tiocb 2 notes: *1 in modes 1, 3, and 5 the p4 0 to p4 7 functions of pins p4 0 /d 0 to p4 7 /d 7 are selected after a reset, but they can be changed by software. *2 in modes 2 and 4 the d 0 to d 7 functions of pins p4 0 /d 0 to p4 7 /d 7 are selected after a reset, but they can be changed by software. *3 functions as reso in the mask rom versions, and as fwe in the on-chip flash memory versions. functions as the programming control signal in modes 5 and 7. 18 1.4 caution on crystal resonator connection the h8/3024 series support an operating frequency of up to 25 mhz. if a crystal resonator with a frequency higher than 20 mhz is connected, attention must be paid to circuit constants such as external load capacitance values. for details see section 19.2.1, connecting a crystal resonator. 19 section 2 cpu 2.1 overview the h8/300h cpu is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the h8/300 cpu. the h8/300h cpu has sixteen 16-bit general registers, can address a 16-mbyte linear address space, and is ideal for realtime control. 2.1.1 features the h8/300h cpu has the following features. ? upward compatibility with h8/300 cpu can execute h8/300 series object programs ? general-register architecture sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) ? 64 basic instructions ? 8/16/32-bit arithmetic and logic instructions ? multiply and divide instructions ? powerful bit-manipulation instructions ? eight addressing modes ? register direct [rn] ? register indirect [@ern] ? register indirect with displacement [@(d:16, ern) or @(d:24, ern)] ? register indirect with post-increment or pre-decrement [@ern+ or @?rn] ? absolute address [@aa:8, @aa:16, or @aa:24] ? immediate [#xx:8, #xx:16, or #xx:32] ? program-counter relative [@(d:8, pc) or @(d:16, pc)] ? memory indirect [@@aa:8] ? 16-mbyte linear address space ? high-speed operation ? all frequently-used instructions execute in two to four states ? maximum clock frequency: 25 mhz ? 8/16/32-bit register-register add/subtract: 80 ns@25 mhz ? 8 8-bit register-register multiply: 560 ns@25 mhz ? 16 ?8-bit register-register divide: 560 ns@25 mhz ? 16 16-bit register-register multiply: 0.88 s@25 mhz ? 32 ?16-bit register-register divide: 0.88 s@25 mhz 20 ? two cpu operating modes ? normal mode ? advanced mode ? low-power mode transition to power-down state by sleep instruction 2.1.2 differences from h8/300 cpu in comparison to the h8/300 cpu, the h8/300h has the following enhancements. ? more general registers eight 16-bit registers have been added. ? expanded address space ? advanced mode supports a maximum 16-mbyte address space. ? normal mode supports the same 64-kbyte address space as the h8/300 cpu. ? enhanced addressing the addressing modes have been enhanced to make effective use of the 16-mbyte address space. ? enhanced instructions ? data transfer, arithmetic, and logic instructions can operate on 32-bit data. ? signed multiply/divide instructions and other instructions have been added. 2.2 cpu operating modes the h8/300h cpu has two operating modes: normal and advanced. normal mode supports a maximum 64-kbyte address space. advanced mode supports up to 16 mbytes. cpu operating modes normal mode advanced mode maximum 64 kbytes, program and data areas combined maximum 16 mbytes, program and data areas combined figure 2.1 cpu operating modes 21 2.3 address space figure 2.2 shows a simple memory map for the h8/3024 series. the h8/300h cpu can address a linear address space with a maximum size of 64 kbytes in normal mode, and 16 mbytes in advanced mode. for further details see section 3.6, memory map in each operating mode. the 1-mbyte operating modes use 20-bit addressing. the upper 4 bits of effective addresses are ignored. h'00000 h'fffff h'000000 h'ffffff a. 1-mbyte mode b. 16-mbyte mode h'0000 h'ffff advanced mode normal mode figure 2.2 memory map 22 2.4 register configuration 2.4.1 overview the h8/300h cpu has the internal registers shown in figure 2.3. there are two types of registers: general registers and control registers. er0 er1 er2 er3 er4 er5 er6 er7 e0 e1 e2 e3 e4 e5 e6 e7 r0h r1h r2h r3h r4h r5h r6h r7h r0l r1l r2l r3l r4l r5l r6l r7l 0 7 0 7 0 15 (sp) 23 0 pc 7 ccr 6543210 iuihunzvc general registers (ern) control registers (cr) legend: sp: pc: ccr: i: ui: h: u: n: z: v: c: stack pointer program counter condition code register interrupt mask bit user bit or interrupt mask bit half-carry flag user bit negative flag zero flag overflow flag carry flag figure 2.3 cpu registers 23 2.4.2 general registers the h8/300h cpu has eight 32-bit general registers. these general registers are all functionally alike and can be used without distinction between data registers and address registers. when a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. when the general registers are used as 32-bit registers or as address registers, they are designated by the letters er (er0 to er7). the er registers divide into 16-bit general registers designated by the letters e (e0 to e7) and r (r0 to r7). these registers are functionally equivalent, providing a maximum sixteen 16-bit registers. the e registers (e0 to e7) are also referred to as extended registers. the r registers divide into 8-bit general registers designated by the letters rh (r0h to r7h) and rl (r0l to r7l). these registers are functionally equivalent, providing a maximum sixteen 8-bit registers. figure 2.4 illustrates the usage of the general registers. the usage of each register can be selected independently. ? address registers ? 32-bit registers ? 16-bit registers ? 8-bit registers er registers er0 to er7 e registers (extended registers) e0 to e7 r registers r0 to r7 rh registers r0h to r7h rl registers r0l to r7l figure 2.4 usage of general registers general register er7 has the function of stack pointer (sp) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. figure 2.5 shows the stack. 24 free area stack area sp (er7) figure 2.5 stack 2.4.3 control registers the control registers are the 24-bit program counter (pc) and the 8-bit condition code register (ccr). program counter (pc): this 24-bit counter indicates the address of the next instruction the cpu will execute. the length of all cpu instructions is 2 bytes (one word), so the least significant pc bit is ignored. when an instruction is fetched, the least significant pc bit is regarded as 0. condition code register (ccr): this 8-bit register contains internal cpu status information, including the interrupt mask bit (i) and half-carry (h), negative (n), zero (z), overflow (v), and carry (c) flags. bit 7?nterrupt mask bit (i): masks interrupts other than nmi when set to 1. nmi is accepted regardless of the i bit setting. the i bit is set to 1 at the start of an exception-handling sequence. bit 6?ser bit or interrupt mask bit (ui): can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. this bit can also be used as an interrupt mask bit. for details see section 5, interrupt controller. bit 5?alf-carry flag (h): when the add.b, addx.b, sub.b, subx.b, cmp.b, or neg.b instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. when the add.w, sub.w, cmp.w, or neg.w instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. when the add.l, sub.l, cmp.l, or neg.l instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. bit 4?ser bit (u): can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. bit 3?egative flag (n): stores the value of the most significant bit of data, regarded as the sign bit. bit 2?ero flag (z): set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. 25 bit 1?verflow flag (v): set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. bit 0?arry flag (c): set to 1 when a carry is generated by execution of an operation, and cleared to 0 otherwise. used by: ? add instructions, to indicate a carry ? subtract instructions, to indicate a borrow ? shift and rotate instructions the carry flag is also used as a bit accumulator by bit manipulation instructions. some instructions leave flag bits unchanged. operations can be performed on ccr by the ldc, stc, andc, orc, and xorc instructions. the n, z, v, and c flags are used by conditional branch (bcc) instructions. for the action of each instruction on the flag bits, see appendix a.1, instruction list. for the i and ui bits, see section 5, interrupt controller. 2.4.4 initial cpu register values in reset exception handling, pc is initialized to a value loaded from the vector table, and the i bit in ccr is set to 1. the other ccr bits and the general registers are not initialized. in particular, the initial value of the stack pointer (er7) is also undefined. the stack pointer (er7) must therefore be initialized by an mov.l instruction executed immediately after a reset. 26 2.5 data formats the h8/300h cpu can process 1-bit, 4-bit (bcd), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ? 7) of byte operand data. the daa and das decimal-adjust instructions treat byte data as two digits of 4-bit bcd data. 2.5.1 general register data formats figures 2.6 and 2.7 show the data formats in general registers. 7 rnh rnl rnh rnl rnh rnl 1-bit data 1-bit data 4-bit bcd data 4-bit bcd data byte data byte data 6543210 70 don ? t care 76543210 70 don ? t care don ? t care 70 43 lower digit upper digit 7 43 lower digit upper digit don ? t care 0 70 don ? t care msb lsb don ? t care 70 msb lsb data type data format general register legend: rnh: general register rh rnl: general register rl figure 2.6 general register data formats 27 rn en ern word data word data longword data 15 0 msb lsb general register data type data format 15 0 msb lsb 31 16 msb 15 0 lsb legend: ern: en: rn: msb: lsb: general register general register e general register r most significant bit least significant bit figure 2.7 general register data formats 2.5.2 memory data formats figure 2.8 shows the data formats on memory. the h8/300h cpu can access word data and longword data on memory, but word or longword data must begin at an even address. if an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. this also applies to instruction fetches. 28 76543210 address l address l lsb msb msb lsb 70 msb lsb 1-bit data byte data word data longword data address data type data format address 2m address 2m + 1 address 2n address 2n + 1 address 2n + 2 address 2n + 3 figure 2.8 memory data formats when er7 (sp) is used as an address register to access the stack, the operand size should be word size or longword size. 29 2.6 instruction set 2.6.1 instruction set overview the h8/300h cpu has 64 types of instructions, which are classified in table 2.1. table 2.1 instruction classification function instruction types data transfer mov, push* 1 , pop* 1 , movtpe* 2 , movfpe* 2 5 arithmetic operations add, sub, addx, subx, inc, dec, adds, subs, daa, das, mulxu, mulxs, divxu, divxs, cmp, neg, exts, extu 18 logic operations and, or, xor, not 4 shift operations shal, shar, shll, shlr, rotl, rotr, rotxl, rotxr 8 bit manipulation bset, bclr, bnot, btst, band, biand, bor, bior, bxor, bixor, bld, bild, bst, bist 14 branch bcc* 3 , jmp, bsr, jsr, rts 5 system control trapa, rte, sleep, ldc, stc, andc, orc, xorc, nop 9 block data transfer eepmov 1 total 64 types notes: *1 pop.w rn is identical to mov.w @sp+, rn. push.w rn is identical to mov.w rn, @ e sp. pop.l ern is identical to mov.l @sp+, rn. push.l ern is identical to mov.l rn, @ e sp. *2 not available in the h8/3024 series. *3 bcc is a generic branching instruction. 30 2.6.2 instructions and addressing modes table 2.2 indicates the instructions available in the h8/300h cpu. table 2.2 instructions and addressing modes addressing modes function instruction #xx rn @ern @ (d:16, ern) @ (d:24, ern) @ern+/ @?rn @ aa:8 @ aa:16 @ aa:24 @ (d:8, pc) @ (d:16, pc) @@ aa:8 data mov bwl bwl bwl bwl bwl bwl b bwl bwl ???? transfer pop, push ??? ??? ?????? wl movfpe, ??? ??? ??????? movtpe arithmetic add, cmp bwl bwl ? ??? ??????? operations sub wl bwl ? ??? ??????? addx, subx b b ? ??? ??????? adds, subs ? l ? ??? ??????? inc, dec ? bwl ? ??? ??????? daa, das ? b ? ??? ??????? mulxu, ? bw ? ??? ??????? mulxs, divxu, divxs neg ? bwl ? ??? ??????? extu, exts ? wl ? ??? ??????? logic operations and, or, xor ? bwl ? ??? ??????? not ? bwl ? ??? ??????? shift instructions ? bwl ? ??? ??????? bit manipulation ? bb ?? ? b ?????? branch bcc, bsr ??? ??? ??????? jmp, jsr ?? ??? ??? ?? rts ??? ??? ?? ?? ? system trapa ??? ??? ?????? control rte ??? ??? ?????? sleep ??? ??? ?????? ldc b b w w w w ? ww ??? stc ? bwwww ? ww ???? andc, orc, xorc b ?? ??? ??????? nop ??? ??? ?????? block data transfer ??? ??? ?????? bw notes: b: byte, w: word, l: longword 31 2.6.3 tables of instructions classified by function tables 2.3 to 2.10 summarize the instructions in each functional category. the operation notation used in these tables is defined next. operation notation rd general register (destination)* rs general register (source)* rn general register* ern general register (32-bit register or address register)* (ead) destination operand (eas) source operand ccr condition code register n n (negative) flag of ccr z z (zero) flag of ccr v v (overflow) flag of ccr c c (carry) flag of ccr pc program counter sp stack pointer #imm immediate data disp displacement + addition e subtraction multiplication division and logical or logical exclusive or logical move a not (logical complement) :3/:8/:16/:24 3-, 8-, 16-, or 24-bit length note: * general registers include 8-bit registers (r0h to r7h, r0l to r7l), 16-bit registers (r0 to r7, e0 to e7), and 32-bit data or address registers (er0 to er7). 32 table 2.3 data transfer instructions instruction size* function mov b/w/l (eas) rd, rs (ead) moves data between two general registers or between a general register and memory, or moves immediate data to a general register. movfpe b (eas) rd cannot be used in this lsi. movtpe b rs (eas) cannot be used in this lsi. pop w/l @sp+ rn pops a general register from the stack. pop.w rn is identical to mov.w @sp+, rn. similarly, pop.l ern is identical to mov.l @sp+, ern. push w/l rn @ e sp pushes a general register onto the stack. push.w rn is identical to mov.w rn, @ e sp. similarly, push.l ern is identical to mov.l ern, @ e sp. note: * size refers to the operand size. b: byte w: word l: longword 33 table 2.4 arithmetic operation instructions instruction size* function add,sub b/w/l rd rs rd, rd #imm rd performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (immediate byte data cannot be subtracted from data in a general register. use the subx or add instruction.) addx, subx b rd rs c rd, rd #imm c rd performs addition or subtraction with carry or borrow on data in two general registers, or on immediate data and data in a general register. inc, dec b/w/l rd 1 rd, rd 2 rd increments or decrements a general register by 1 or 2. (byte operands can be incremented or decremented by 1 only.) adds, subs l rd 1 rd, rd 2 rd, rd 4 rd adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. daa, das b rd decimal adjust rd decimal-adjusts an addition or subtraction result in a general register by referring to ccr to produce 4-bit bcd data. mulxu b/w rd rs rd performs unsigned multiplication on data in two general registers: either 8 bits 8 bits 16 bits or 16 bits 16 bits 32 bits. mulxs b/w rd rs rd performs signed multiplication on data in two general registers: either 8 bits 8 bits 16 bits or 16 bits 16 bits 32 bits. 34 instruction size* function divxu b/w rd ? rs rd performs unsigned division on data in two general registers: either 16 bits ? 8 bits 8-bit quotient and 8-bit remainder or 32 bits ? 16 bits 16-bit quotient and 16-bit remainder divxs b/w rd ? rs rd performs signed division on data in two general registers: either 16 bits ? 8 bits 8-bit quotient and 8-bit remainder, or 32 bits ? 16 bits 16-bit quotient and 16-bit remainder cmp b/w/l rd e rs, rd e #imm compares data in a general register with data in another general register or with immediate data, and sets ccr according to the result. neg b/w/l 0 e rd rd takes the two ? s complement (arithmetic complement) of data in a general register. exts w/l rd (sign extension) rd extends byte data in the lower 8 bits of a 16-bit register to word data, or extends word data in the lower 16 bits of a 32-bit register to longword data, by extending the sign bit. extu w/l rd (zero extension) rd extends byte data in the lower 8 bits of a 16-bit register to word data, or extends word data in the lower 16 bits of a 32-bit register to longword data, by padding with zeros. note: * size refers to the operand size. b: byte w: word l: longword 35 table 2.5 logic operation instructions instruction size* function and b/w/l rd rs rd, rd #imm rd performs a logical and operation on a general register and another general register or immediate data. or b/w/l rd rs rd, rd #imm rd performs a logical or operation on a general register and another general register or immediate data. xor b/w/l rd rs rd, rd #imm rd performs a logical exclusive or operation on a general register and another general register or immediate data. not b/w/l a rd rd takes the one ? s complement (logical complement) of general register contents. note: * size refers to the operand size. b: byte w: word l: longword table 2.6 shift instructions instruction size* function shal, shar b/w/l rd (shift) rd performs an arithmetic shift on general register contents. shll, shlr b/w/l rd (shift) rd performs a logical shift on general register contents. rotl, rotr b/w/l rd (rotate) rd rotates general register contents. rotxl, rotxr b/w/l rd (rotate) rd rotates general register contents, including the carry bit. note: * size refers to the operand size. b: byte w: word l: longword 36 table 2.7 bit manipulation instructions instruction size* function bset b 1 ( 37 instruction size* function bor b c ( 38 table 2.8 branching instructions instruction size function bcc ? branches to a specified address if address specified condition is met. the branching conditions are listed below. mnemonic description condition bra (bt) always (true) always brn (bf) never (false) never bhi high c z = 0 bls low or same c z = 1 bcc (bhs) carry clear (high or same) c = 0 bcs (blo) carry set (low) c = 1 bne not equal z = 0 beq equal z = 1 bvc overflow clear v = 0 bvs overflow set v = 1 bpl plus n = 0 bmi minus n = 1 bge greater or equal n v = 0 blt less than n v = 1 bgt greater than z (n v) = 0 ble less or equal z (n v) = 1 jmp ? branches unconditionally to a specified address bsr ? branches to a subroutine at a specified address jsr ? branches to a subroutine at a specified address rts ? returns from a subroutine 39 table 2.9 system control instructions instruction size* function trapa ? starts trap-instruction exception handling rte ? returns from an exception-handling routine sleep ? causes a transition to the power-down state ldc b/w (eas) ccr moves the source operand contents to the condition code register. the condition code register size is one byte, but in transfer from memory, data is read by word access. stc b/w ccr (ead) transfers the ccr contents to a destination location. the condition code register size is one byte, but in transfer to memory, data is written by word access. andc b ccr #imm ccr logically ands the condition code register with immediate data. orc b ccr #imm ccr logically ors the condition code register with immediate data. xorc b ccr #imm ccr logically exclusive-ors the condition code register with immediate data. nop ? pc + 2 pc only increments the program counter. note: * size refers to the operand size. b: byte w: word 40 table 2.10 block transfer instruction instruction size function eepmov.b ? if r4l 0 then repeat @er5+ @er6+, r4l e 1 r4l until r4l = 0 else next; eepmov.w ? if r4 0 then repeat @er5+ @er6+, r4 e 1 r4 until r4 = 0 else next; block transfer instruction. this instruction transfers the number of data bytes specified by r4l or r4, starting from the address indicated by er5, to the location starting at the address indicated by er6. at the end of the transfer, the next instruction is executed. 2.6.4 basic instruction formats the h8/300h instructions consist of 2-byte (word) units. an instruction consists of an operation field (op field), a register field (r field), an effective address extension (ea field), and a condition field (cc). operation field: indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. the operation field always includes the first 4 bits of the instruction. some instructions have two operation fields. register field: specifies a general register. address registers are specified by 3 bits, data registers by 3 bits or 4 bits. some instructions have two register fields. some have no register field. effective address extension: eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. a 24-bit address or displacement is treated as 32-bit data in which the first 8 bits are 0 (h'00). condition field: specifies the branching condition of bcc instructions. figure 2.9 shows examples of instruction formats. 41 op nop, rts, etc. op rn rm op rn rm ea (disp) operation field only add.b rn, rm, etc. operation field and register fields mov.b @(d:16, rn), rm operation field, register fields, and effective address extension bra d:8 operation field, effective address extension, and condition field op cc ea (disp) figure 2.9 instruction formats 2.6.5 notes on use of bit manipulation instructions the bset, bclr, bnot, bst, and bist instructions read a byte of data, modify a bit in the byte, then write the byte back. care is required when these instructions are used to access registers with write-only bits, or to access ports. step description 1 read read one data byte at the specified address 2 modify modify one bit in the data byte 3 write write the modified data byte back to the specified address example 1: bclr is executed to clear bit 0 in the port 4 data direction register (p4ddr) under the following conditions. p4 7 , p4 6 : input pins p4 5 ?p4 0 : output pins the intended purpose of this bclr instruction is to switch p4 0 from output to input. 42 before execution of bclr instruction p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 p4 0 input/output input input output output output output output output ddr 00111111 execution of bclr instruction bclr #0, p4ddr ; execute bclr instruction on ddr after execution of bclr instruction p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 p4 0 input/output output output output output output output output input ddr 11111110 explanation: to execute the bclr instruction, the cpu begins by reading p4ddr. since p4ddr is a write-only register, it is read as h'ff, even though its true value is h'3f. next the cpu clears bit 0 of the read data, changing the value to h'fe. finally, the cpu writes this value (h'fe) back to p4ddr to complete the bclr instruction. as a result, p4 0 ddr is cleared to 0, making p4 0 an input pin. in addition, p4 7 ddr and p4 6 ddr are set to 1, making p4 7 and p4 6 output pins. the bclr instruction can be used to clear flags in the on-chip registers to 0. in the case of the irq status register (isr), for example, a flag must be read as a condition for clearing it, but when using the bclr instruction, if it is known that a flag has been set to 1 in an interrupt-handling routine, for instance, it is not necessary to read the flag ahead of time. 43 2.7 addressing modes and effective address calculation 2.7.1 addressing modes the h8/300h cpu supports the eight addressing modes listed in table 2.11. each instruction uses a subset of these addressing modes. arithmetic and logic instructions can use the register direct and immediate modes. data transfer instructions can use all addressing modes except program- counter relative and memory indirect. bit manipulation instructions use register direct, register indirect, or absolute (@aa:8) addressing mode to specify an operand, and register direct (bset, bclr, bnot, and btst instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. table 2.11 addressing modes no. addressing mode symbol 1 register direct rn 2 register indirect @ern 3 register indirect with displacement @(d:16, ern)/@(d:24, ern) 4 register indirect with post-increment register indirect with pre-decrement @ern+ @ e ern 5 absolute address @aa:8/@aa:16/@aa:24 6 immediate #xx:8/#xx:16/#xx:32 7 program-counter relative @(d:8, pc)/@(d:16, pc) 8 memory indirect @@aa:8 1 register direct?n: the register field of the instruction code specifies an 8-, 16-, or 32-bit register containing the operand. r0h to r7h and r0l to r7l can be specified as 8-bit registers. r0 to r7 and e0 to e7 can be specified as 16-bit registers. er0 to er7 can be specified as 32-bit registers. 2 register indirect?ern: the register field of the instruction code specifies an address register (ern), the lower 24 bits of which contain the address of the operand. 3 register indirect with displacement?(d:16, ern) or @(d:24, ern): a 16-bit or 24-bit displacement contained in the instruction code is added to the contents of an address register (ern) specified by the register field of the instruction, and the lower 24 bits of the sum specify the address of a memory operand. a 16-bit displacement is sign-extended when added. 44 4 register indirect with post-increment or pre-decrement?ern+ or @?rn: ? register indirect with post-increment?ern+ the register field of the instruction code specifies an address register (ern) the lower 24 bits of which contain the address of a memory operand. after the operand is accessed, 1, 2, or 4 is added to the address register contents (32 bits) and the sum is stored in the address register. the value added is 1 for byte access, 2 for word access, or 4 for longword access. for word or longword access, the register value should be even. ? register indirect with pre-decrement??rn the value 1, 2, or 4 is subtracted from an address register (ern) specified by the register field in the instruction code, and the lower 24 bits of the result become the address of a memory operand. the result is also stored in the address register. the value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. for word or longword access, the resulting register value should be even. 5 absolute address?aa:8, @aa:16, or @aa:24: the instruction code contains the absolute address of a memory operand. the absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), or 24 bits long (@aa:24). for an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (h'ffff). for a 16-bit absolute address the upper 8 bits are a sign extension. a 24-bit absolute address can access the entire address space. table 2.12 indicates the accessible address ranges. table 2.12 absolute address access ranges absolute address 1-mbyte modes 16-mbyte modes 8 bits (@aa:8) h'fff00 to h'fffff (1048320 to 1048575) h'ffff00 to h'ffffff (16776960 to 16777215) 16 bits (@aa:16) h'00000 to h'07fff, h'f8000 to h'fffff (0 to 32767, 1015808 to 1048575) h'000000 to h'007fff, h'ff8000 to h'ffffff (0 to 32767, 16744448 to 16777215) 24 bits (@aa:24) h'00000 to h'fffff (0 to 1048575) h'000000 to h'ffffff (0 to 16777215) 6 immediate?xx:8, #xx:16, or #xx:32: the instruction code contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. the instruction codes of the adds, subs, inc, and dec instructions contain immediate data implicitly. the instruction codes of some bit manipulation instructions contain 3-bit immediate data specifying a bit number. the trapa instruction code contains 2-bit immediate data specifying a vector address. 7 program-counter relative?(d:8, pc) or @(d:16, pc): this mode is used in the bcc and bsr instructions. an 8-bit or 16-bit displacement contained in the instruction code is sign- 45 extended to 24 bits and added to the 24-bit pc contents to generate a 24-bit branch address. the pc value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is ?26 to +128 bytes (?3 to +64 words) or ?2766 to +32768 bytes (?6383 to +16384 words) from the branch instruction. the resulting value should be an even number. 8 memory indirect?@aa:8: this mode can be used by the jmp and jsr instructions. the instruction code contains an 8-bit absolute address specifying a memory operand. this memory operand contains a branch address. the memory operand is accessed by longword access. the first byte of the memory operand is ignored, generating a 24-bit branch address. see figure 2.10. the upper bits of the 8-bit absolute address are assumed to be 0 (h'0000), so the address range is 0 to 255 (h'000000 to h'0000ff). note that the first part of this range is also the exception vector area. for further details see section 5, interrupt controller. specified by @aa:8 reserved branch address figure 2.10 memory-indirect branch address specification when a word-size or longword-size memory operand is specified, or when a branch address is specified, if the specified memory address is odd, the least significant bit is regarded as 0. the accessed data or instruction code therefore begins at the preceding address. see section 2.5.2, memory data formats. 2.7.2 effective address calculation table 2.13 explains how an effective address is calculated in each addressing mode. in the 1-mbyte operating modes the upper 4 bits of the calculated address are ignored in order to generate a 20-bit effective address. 46 table 2.13 effective address calculation addressing mode and instruction format no. effective address calculation effective address register direct (rn) 1 operand is general register contents op rm rn register indirect (@ern) 2 op r general register contents 31 0 23 0 register indirect with displacement @(d:16, ern)/@(d:24, ern) 3 op r general register contents 31 0 23 0 sign extension disp register indirect with post-increment or pre-decrement 4 general register contents 31 0 23 0 1, 2, or 4 op r general register contents 31 0 23 0 1, 2, or 4 op r register indirect with post-increment @ern+ register indirect with pre-decrement @ e ern 1 for a byte operand, 2 for a word operand, 4 for a longword operand 47 addressing mode and instruction format no. effective address calculation effective address absolute address @aa:8 5 op program-counter relative @(d:8, pc) or @(d:16, pc) 7 0 23 0 abs 23 0 87 @aa:16 @aa:24 op abs 23 0 16 15 h'ffff sign extension op 23 0 abs immediate #xx:8, #xx:16, or #xx:32 6 operand is immediate data op disp 23 0 pc contents disp op imm sign extension 48 addressing mode and instruction format no. effective address calculation effective address 8 legend: r, rm, rn: op: disp: imm: abs: register field operation field displacement immediate data absolute address memory indirect @@aa:8 8 op 23 0 abs 23 0 87 h'0000 15 0 abs 16 15 normal mode op 23 0 abs 23 0 87 h'0000 0 abs advanced mode 31 h'00 memory contents memory contents 49 2.8 processing states 2.8.1 overview the h8/300h cpu has five processing states: the program execution state, exception-handling state, power-down state, reset state, and bus-released state. the power-down state includes sleep mode, software standby mode, and hardware standby mode. figure 2.11 classifies the processing states. figure 2.13 indicates the state transitions. processing states program execution state bus-released state reset state power-down state the cpu executes program instructions in sequence a transient state in which the cpu executes a hardware sequence (saving pc and ccr, fetching a vector, etc.) in response to a reset, interrupt, or other exception the external bus has been released in response to a bus request signal from a bus master other than the cpu the cpu and all on-chip supporting modules are initialized and halted the cpu is halted to conserve power sleep mode software standby mode hardware standby mode exception-handling state figure 2.11 processing states 2.8.2 program execution state in this state the cpu executes program instructions in normal sequence. 50 2.8.3 exception-handling state the exception-handling state is a transient state that occurs when the cpu alters the normal program flow due to a reset, interrupt, or trap instruction. the cpu fetches a starting address from the exception vector table and branches to that address. in interrupt and trap exception handling the cpu references the stack pointer (er7) and saves the program counter and condition code register. types of exception handling and their priority: exception handling is performed for resets, interrupts, and trap instructions. table 2.14 indicates the types of exception handling and their priority. trap instruction exceptions are accepted at all times in the program execution state. table 2.14 exception handling types and priority priority type of exception detection timing start of exception handling high reset synchronized with clock exception handling starts immediately when res changes from low to high interrupt end of instruction execution or end of exception handling* when an interrupt is requested, exception handling starts at the end of the current instruction or current exception-handling sequence low trap instruction when trapa instruction is executed exception handling starts when a trap (trapa) instruction is executed note: * interrupts are not detected at the end of the andc, orc, xorc, and ldc instructions, or immediately after reset exception handling. figure 2.12 classifies the exception sources. for further details about exception sources, vector numbers, and vector addresses, see section 4, exception handling, and section 5, interrupt controller. e xception s ources reset interrupt trap instruction external interrupts internal interrupts (from on-chip supporting modules) figure 2.12 classification of exception sources 51 bus-released state exception-handling state reset state program execution state sleep mode software standby mode hardware standby mode power-down state bus request end of bus release end of bus release bus request end of exception handling exception handling source interrupt source sleep instruction with ssby = 0 sleep instruction with ssby = 1 nmi, irq , irq , or irq interrupt stby="high", res ="low" res = "high" 01 2 *1 *2 notes: *1 *2 from any state except hardware standby mode, a transition to the reset state occurs whenever res goes low. from any state, a transition to hardware standby mode occurs when stby goes low. figure 2.13 state transitions 2.8.4 exception handling operation reset exception handling: reset exception handling has the highest priority. the reset state is entered when the res signal goes low. reset exception handling starts after that, when res changes from low to high. when reset exception handling starts the cpu fetches a start address from the exception vector table and starts program execution from that address. all interrupts, including nmi, are disabled during the reset exception-handling sequence and immediately after it ends. interrupt exception handling and trap instruction exception handling: when these exception-handling sequences begin, the cpu references the stack pointer (er7) and pushes the program counter and condition code register on the stack. next, if the ue bit in the system control register (syscr) is set to 1, the cpu sets the i bit in the condition code register to 1. if the ue bit is cleared to 0, the cpu sets both the i bit and the ui bit in the condition code register to 1. then the cpu fetches a start address from the exception vector table and execution branches to that address. 52 figure 2.14 shows the stack after the exception-handling sequence. sp e 4 sp e 3 sp e 2 sp e 1 sp (er7) before exception handling starts sp (er7) sp+1 sp+2 sp+3 sp+4 after exception handling ends stack area ccr pc even address pushed on stack legend: ccr: sp: condition code register stack pointer notes: 1. 2. pc is the address of the first instruction executed after the return from the exception-handling routine. registers must be saved and restored by word access or longword access, starting at an even address. figure 2.14 stack structure after exception handling 2.8.5 bus-released state in this state the bus is released to a bus master other than the cpu, in response to a bus request. the bus masters other than the cpu is an external bus master. while the bus is released, the cpu halts except for internal operations. interrupt requests are not accepted. for details see section 6.6, bus arbiter. 2.8.6 reset state when the res input goes low all current processing stops and the cpu enters the reset state. the i bit in the condition code register is set to 1 by a reset. all interrupts are masked in the reset state. reset exception handling starts when the res signal changes from low to high. the reset state can also be entered by a watchdog timer overflow. for details see section 11, watchdog timer. 53 2.8.7 power-down state in the power-down state the cpu stops operating to conserve power. there are three modes: sleep mode, software standby mode, and hardware standby mode. sleep mode: a transition to sleep mode is made if the sleep instruction is executed while the ssby bit is cleared to 0 in the system control register (syscr). cpu operations stop immediately after execution of the sleep instruction, but the contents of cpu registers are retained. software standby mode: a transition to software standby mode is made if the sleep instruction is executed while the ssby bit is set to 1 in syscr. the cpu and clock halt and all on-chip supporting modules stop operating. the on-chip supporting modules are reset, but as long as a specified voltage is supplied the contents of cpu registers and on-chip ram are retained. the i/o ports also remain in their existing states. hardware standby mode: a transition to hardware standby mode is made when the stby input goes low. as in software standby mode, the cpu and all clocks halt and the on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip ram contents are retained. for further information see section 20, power-down state. 2.9 basic operational timing 2.9.1 overview the h8/300h cpu operates according to the system clock (?. the interval from one rise of the system clock to the next rise is referred to as a ?tate.? a memory cycle or bus cycle consists of two or three states. the cpu uses different methods to access on-chip memory, the on-chip supporting modules, and the external address space. access to the external address space can be controlled by the bus controller. 2.9.2 on-chip memory access timing on-chip memory is accessed in two states. the data bus is 16 bits wide, permitting both byte and word access. figure 2.15 shows the on-chip memory access cycle. figure 2.16 indicates the pin states. all h8/3024 series models have a function for changing the method of outputting addresses from the address pins. for details see section 6.3.5, address output method. 54 t state bus cycle internal address bus internal read signal internal data bus (read access) internal write signal internal data bus (write access) 1 t state 2 read data address write data figure 2.15 on-chip memory access cycle t , , , as 1 t 2 address bus d to d 15 0 rd hwr lwr high address high impedance figure 2.16 pin states during on-chip memory access (address update mode 1) 2.9.3 on-chip supporting module access timing the on-chip supporting modules are accessed in three states. the data bus is 8 or 16 bits wide, depending on the internal i/o register being accessed. figure 2.17 shows the on-chip supporting module access timing. figure 2.18 indicates the pin states. 55 address bus internal read signal internal data bus internal write signal address internal data bus t state bus cycle 1 t state 2 t state 3 read access write access write data read data figure 2.17 access cycle for on-chip supporting modules t , , , as 1 t 2 address bus d to d 15 0 rd hwr lwr high high impedance t 3 address figure 2.18 pin states during access to on-chip supporting modules 2.9.4 access to external address space the external address space is divided into eight areas (areas 0 to 7). bus-controller settings determine whether each area is accessed via an 8-bit or 16-bit data bus, and whether it is accessed in two or three states. for details see section 6, bus controller. 56 57 section 3 mcu operating modes 3.1 overview 3.1.1 operating mode selection the h8/3024 series has seven operating modes (modes 1 to 7) that are selected by the mode pins (md 2 to md 0 ) as indicated in table 3.1. the input at these pins determines the size of the address space and the initial bus mode. table 3.1 operating mode selection description operating mode pins initial bus on-chip on-chip mode md 2 md 1 md 0 address space mode* 1 rom ram ? 0 0 0 setting prohibited setting prohibited setting prohibited setting prohibited mode 1 0 0 1 expanded mode 8 bits disabled enabled* 2 mode 2 0 1 0 expanded mode 16 bits disabled enabled* 2 mode 3 0 1 1 expanded mode 8 bits disabled enabled* 2 mode 4 1 0 0 expanded mode 16 bits disabled enabled* 2 mode 5 1 0 1 expanded mode 8 bits enabled enabled* 2 mode 6 1 1 0 single-chip normal mode ? enabled enabled mode 7 1 1 1 single-chip advanced mode ? enabled enabled notes: *1 in modes 1 to 5, an 8-bit or 16-bit data bus can be selected on a per-area basis by settings made in the area bus width control register (abwcr). for details see section 6, bus controller. *2 if the rame bit in syscr is cleared to 0, these addresses become external addresses. for the address space size there are three choices: 64 kbytes, 1 mbyte, or 16 mbyte. the external data bus is either 8 or 16 bits wide depending on abwcr settings. 8-bit bus mode is used only if 8-bit access is selected for all areas. for details see section 6, bus controller. modes 1 to 4 are externally expanded modes that enable access to external memory and peripheral devices and disable access to the on-chip rom. modes 1 and 2 support a maximum address space of 1 mbyte. modes 3 and 4 support a maximum address space of 16 mbytes. 58 mode 5 is an externally expanded mode that enables access to external memory and peripheral devices and also enables access to the on-chip rom. mode 5 supports a maximum address space of 16 mbytes. modes 6 and 7 are single-chip modes in which the chip operates using only the on-chip rom, ram, and i/o registers. all ports are available in these modes. mode 6 supports a maximum address space of 64 kbytes. mode 7 supports a maximum address space of 1 mbyte. the h8/3024 series can be used only in modes 1 to 7. the inputs at the mode pins must select one of these seven modes. the inputs at the mode pins must not be changed during operation. set the reset state before changing the inputs at these pins. 3.1.2 register configuration the h8/3024 series has a mode control register (mdcr) that indicates the inputs at the mode pins (md 2 to md 0 ), and a system control register (syscr). table 3.2 summarizes these registers. table 3.2 registers address* name abbreviation r/w initial value h'ee011 mode control register mdcr r undetermined h'ee012 system control register syscr r/w h'09 note: * lower 20 bits of the address in advanced mode. 3.2 mode control register (mdcr) mdcr is an 8-bit read-only register that indicates the current operating mode of the h8/3024 series. bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 0 ? 4 ? 0 ? 3 ? 0 ? 0 mds0 ? r * 2 mds2 ? r 1 mds1 ? r ** mode select 2 to 0 bits indicating the current operating mode reserved bits note: determined by pins md to md . * 20 59 bits 7 and 6?eserved: these bits can not be modified and are always read as 1. bits 5 to 3?eserved: these bits can not be modified and are always read as 0. bits 2 to 0?ode select 2 to 0 (mds2 to mds0): these bits indicate the logic levels at pins md 2 to md 0 (the current operating mode). mds2 to mds0 correspond to md 2 to md 0 . mds2 to mds0 are read-only bits. the mode pin (md 2 to md 0 ) levels are latched into these bits when mdcr is read. note: the versions with on-chip flash memory have a boot mode in which flash memory can be programmed. in boot mode, the mds2 bit value is the inverse of the level at the md 2 pin. 3.3 system control register (syscr) syscr is an 8-bit register that controls the operation of the h8/3024 series. bit initial value read/write 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 4 sts0 0 r/w 3 ue 1 r/w 0 rame 1 r/w 2 nmieg 0 r/w 1 ssoe 0 r/w software standby enables transition to software standby mode user bit enable selects whether to use the ui bit in ccr as a user bit or an interrupt mask bit nmi edge select selects the valid edge of the nmi input ram enable enables or disables on-chip ram standby timer select 2 to 0 these bits select the waiting time at recovery from software standby mode selects the output state of the address bus and bus control signals in software standby mode software standby output port enable 60 bit 7?oftware standby (ssby): enables transition to software standby mode. (for further information about software standby mode see section 20, power-down state.) when software standby mode is exited by an external interrupt, and a transition is made to normal operation, this bit remains set to 1. to clear this bit, write 0. bit 7 ssby description 0 sleep instruction causes transition to sleep mode (initial value) 1 sleep instruction causes transition to software standby mode bits 6 to 4?tandby timer select 2 to 0 (sts2 to sts0): these bits select the length of time the cpu and on-chip supporting modules wait for the internal clock oscillator to settle when software standby mode is exited by an external interrupt. when using a crystal oscillator, set these bits so that the waiting time will be at least 7 ms at the system clock rate. for further information about waiting time selection, see section 20.4.3, selection of waiting time for exit from software standby mode. bit 6 sts2 bit 5 sts1 bit 4 sts0 description 0 0 0 waiting time = 8,192 states (initial value) 0 0 1 waiting time = 16,384 states 0 1 0 waiting time = 32,768 states 0 1 1 waiting time = 65,536 states 1 0 0 waiting time = 131,072 states 1 0 1 waiting time = 262,144 states 1 1 0 waiting time = 1,024 states 1 1 1 illegal setting bit 3?ser bit enable (ue): selects whether to use the ui bit in the condition code register as a user bit or an interrupt mask bit. bit 3 ue description 0 ui bit in ccr is used as an interrupt mask bit 1 ui bit in ccr is used as a user bit (initial value) 61 bit 2?mi edge select (nmieg): selects the valid edge of the nmi input. bit 2 nmieg description 0 an interrupt is requested at the falling edge of nmi (initial value) 1 an interrupt is requested at the rising edge of nmi bit 1?oftware standby output port enable (ssoe): specifies whether the address bus and bus control signals ( cs 0 to cs 7 , as , rd , hwr , lwr ) are kept as outputs or fixed high, or placed in the high-impedance state in software standby mode. bit 1 ssoe description 0 in software standby mode, the address bus and bus control signals are all high- impedance (initial value) 1 in software standby mode, the address bus retains its output state and bus control signals are fixed high bit 0?am enable (rame): enables or disables the on-chip ram. the rame bit is initialized by the rising edge of the res signal. it is not initialized in software standby mode. bit 0 rame description 0 on-chip ram is disabled 1 on-chip ram is enabled (initial value) 3.4 operating mode descriptions 3.4.1 mode 1 ports 1, 2, and 5 function as address pins a 19 to a 0 , permitting access to a maximum 1-mbyte address space. the initial bus mode after a reset is 8 bits, with 8-bit access to all areas. if at least one area is designated for 16-bit access in abwcr, the bus mode switches to 16 bits. 3.4.2 mode 2 ports 1, 2, and 5 function as address pins a 19 to a 0 , permitting access to a maximum 1-mbyte address space. the initial bus mode after a reset is 16 bits, with 16-bit access to all areas. if all areas are designated for 8-bit access in abwcr, the bus mode switches to 8 bits. 62 3.4.3 mode 3 ports 1, 2, and 5 and part of port a function as address pins a 23 to a 0 , permitting access to a maximum 16-mbyte address space. the initial bus mode after a reset is 8 bits, with 8-bit access to all areas. if at least one area is designated for 16-bit access in abwcr, the bus mode switches to 16 bits. a 23 to a 21 are valid when 0 is written in bits 7 to 5 of the bus release control register (brcr). (in this mode a 20 is always used for address output.) 3.4.4 mode 4 ports 1, 2, and 5 and part of port a function as address pins a 23 to a 0 , permitting access to a maximum 16-mbyte address space. the initial bus mode after a reset is 16 bits, with 16-bit access to all areas. if all areas are designated for 8-bit access in abwcr, the bus mode switches to 8 bits. a 23 to a 21 are valid when 0 is written in bits 7 to 5 of brcr. (in this mode a 20 is always used for address output.) 3.4.5 mode 5 ports 1, 2, and 5 and part of port a can function as address pins a 23 to a 0 , permitting access to a maximum 16-mbyte address space, but following a reset they are input ports. to use ports 1, 2, and 5 as an address bus, the corresponding bits in their data direction registers (p1ddr, p2ddr, and p5ddr) must be set to 1, setting ports 1, 2, and 5 to output mode. for a 23 to a 20 output, write 0 in bits 7 to 4 of brcr. the versions with on-chip flash memory support an on-board programming mode in which the flash memory can be programmed. the initial bus mode after a reset is 8 bits, with 8-bit access to all areas. if at least one area is designated for 16-bit access in abwcr, the bus mode switches to 16 bits. 3.4.6 mode 6 this mode operates using the on-chip rom, ram, and registers. all i/o ports are available. mode 6 supports a maximum address space of 64 kbytes. 3.4.7 mode 7 this mode operates using the on-chip rom, ram, and registers. all i/o ports are available. mode 7 supports a 1-mbyte address space. the versions with on-chip flash memory support an on-board programming mode in which the flash memory can be programmed. 63 3.5 pin functions in each operating mode the pin functions of ports 1 to 5 and port a vary depending on the operating mode. table 3.3 indicates their functions in each operating mode. table 3.3 pin functions in each mode port mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 port 1 a 7 to a 0 a 7 to a 0 a 7 to a 0 a 7 to a 0 p1 7 to p1 0 * 2 p1 7 to p1 0 p1 7 to p1 0 port 2 a 15 to a 8 a 15 to a 8 a 15 to a 8 a 15 to a 8 p2 7 to p2 0 * 2 p2 7 to p2 0 p2 7 to p2 0 port 3 d 15 to d 8 d 15 to d 8 d 15 to d 8 d 15 to d 8 d 15 to d 8 p3 7 to p3 0 p3 7 to p3 0 port 4 p4 7 to p4 0 * 1 d 7 to d 0 * 1 p4 7 to p4 0 * 1 d 7 to d 0 * 1 p4 7 to p4 0 * 1 p4 7 to p4 0 p4 7 to p4 0 port 5 a 19 to a 16 a 19 to a 16 a 19 to a 16 a 19 to a 16 p5 3 to p5 0 * 2 p5 3 to p5 0 p5 3 to p5 0 port a pa 7 to pa 4 pa 7 to pa 4 pa 6 to pa 4 , a 20 * 3 pa 6 to pa 4 , a 20 * 3 pa 7 to pa 4 * 4 pa 7 to pa 4 pa 7 to pa 4 notes: *1 initial state. the bus mode can be switched by settings in abwcr. these pins function as p4 7 to p4 0 in 8-bit bus mode, and as d 7 to d 0 in 16-bit bus mode. *2 initial state. these pins become address output pins when the corresponding bits in the data direction registers (p1ddr, p2ddr, p5ddr) are set to 1. *3 initial state. a 20 is always an address output pin. pa 6 to pa 4 are switched over to a 23 to a 21 output by writing 0 in bits 7 to 5 of brcr. *4 initial state. pa 7 to pa 4 are switched over to a 23 to a 20 output by writing 0 in bits 7 to 4 of brcr. 64 3.6 memory map in each operating mode figures 3.1 to 3.2 show memory maps of the h8/3024 series. in the expanded modes, the address space is divided into eight areas. the initial bus mode differs between modes 1 and 2, and also between modes 3 and 4. the address locations of the on-chip ram and on-chip registers differ between the 64-kbyte mode (mode 6), the 1-mbyte modes (modes 1, 2, and 7), and the 16-mbyte modes (modes 3, 4, and 5). the address range specifiable by the cpu in the 8- and 16-bit absolute addressing modes (@aa:8 and @aa:16) also differs. 3.6.1 comparison of h8/3024 series memory maps in the h8/3024 series, the address maps vary according to the size of the on-chip rom and ram. the internal i/o register space is the same in all models. table 3.4 shows the various address maps in mode 5. table 3.4 address maps in mode 5 h8/3024f-ztat h8/3026f-ztat h8/3024 mask rom version h8/3026 mask rom version on-chip rom size 128 kbytes 256 kbytes 128 kbytes 256 kbytes address area h'000000 to h'01ffff h'000000 to h'03ffff h'000000 to h'01ffff h'000000 to h'03ffff on-chip ram size 4 kbytes 8 kbytes 4 kbytes 8 kbytes address area h'ffef20 to h'ffff1f h'ffdf20 to h'ffff1f h'ffef20 to h'ffff1f h'ffdf20 to h'ffff1f 3.6.2 reserved areas the h8/3024 series memory map includes reserved areas to which access (reading or writing) is prohibited. normal operation cannot be guaranteed if the following reserved areas are accessed. reserved area in internal i/o register space: the h8/3024 series internal i/o register space includes a reserved area to which access is prohibited. for details see appendix b, internal i/o registers. 65 h'00000 h'000ff h'07fff memory-indirect branch addresses 16-bit absolute addresses modes 1 and 2 (1-mbyte expanded modes with on-chip rom disabled) h'1ffff h'20000 h'3ffff h'40000 h'5ffff h'60000 h'7ffff h'80000 h'9ffff h'a0000 h'bffff h'c0000 h'dffff h'e0000 area 0 area 1 area 2 area 3 area 4 area 5 area 6 area 7 external address space external address space vector area on-chip ram* on-chip ram* 8-bit absolute addresses 16-bit absolute addresses h'f8000 h'fef1f h'fef20 h'fff00 h'fff1f h'fff20 h'fffe9 h'fffea h'fffff modes 3 and 4 (16-mbyte expanded modes with on-chip rom disabled) h'000000 h'0000ff h'007fff memory-indirect branch addresses 16-bit absolute addresses h'1fffff h'200000 area 0 area 1 area 2 area 3 area 4 area 5 area 6 area 7 external address space vector area external address space 8-bit absolute addresses 16-bit absolute addresses h'ff8000 h'ffef1f h'ffef20 h'ffff1f h'ffff20 h'ffff00 h'ffffe9 h'ffffea h'ffffff h'3fffff h'400000 h'5fffff h'600000 h'7fffff h'800000 h'9fffff h'a00000 h'bfffff h'c00000 h'dfffff h'e00000 h'fee000 h'fee0ff note: * external addresses can be accessed by disabling on-chip ram. internal i/o registers (1) internal i/o registers (1) internal i/o registers (2) internal i/o registers (2) external address space h'ee000 h'ee0ff external address space figure 3.1 memory map of h8/3024f-ztat and h8/3024 mask rom version in each operating mode 66 h'000000 h'0000ff h'007fff memory-indirect branch addresses 16-bit absolute addresses mode 5 (16-mbyte expanded mode with on-chip rom enabled) mode 6 (single-chip normal mode) mode 7 (single-chip advanced mode) h'01ffff h'020000 h'1fffff h'200000 h'3fffff h'400000 h'5fffff h'600000 h'7fffff h'800000 h'9fffff h'a00000 h'bfffff h'c00000 h'dfffff h'e00000 area 0 area 1 area 2 area 3 area 4 area 5 area 6 area 7 external address space external address space vector area on-chip rom on-chip ram* external address space internal i/o registers (1) internal i/o registers (1) internal i/o registers (2) 8-bit absolute addresses 16-bit absolute addresses h'fee000 h'fee0ff h'ff8000 h'ffef1f h'ffef20 h'ffff00 h'ffff1f h'ffff20 h'ffffe9 h'ffffea h'ffffff h'00000 h'000ff memory-indirect branch addresses 16-bit absolute addresses vector area on-chip rom on-chip ram internal i/o registers (2) 8-bit absolute addresses 16-bit absolute addresses h'ee000 h'ee0ff h'fff1f h'fff20 h'fef20 h'fffe9 h'fffff h'fff00 h'07fff h'1ffff h'f8000 note: * external addresses can be accessed by disabling on-chip ram. h'0000 h'00ff h'dfff h'e000 memory-indirect branch addresses vector area internal i/o registers (2) internal i/o registers (1) 8-bit absolute addresses h'ef20 h'e0ff h'ff00 h'ff1f h'ff20 h'ffff h'ffe9 on-chip ram on-chip rom figure 3.1 memory map of h8/3024f-ztat and h8/3024 mask rom version in each operating mode (cont) 67 h'00000 h'000ff h'07fff memory-indirect branch addresses 16-bit absolute addresses modes 1 and 2 (1-mbyte expanded modes with on-chip rom disabled) h'1ffff h'20000 h'3ffff h'40000 h'5ffff h'60000 h'7ffff h'80000 h'9ffff h'a0000 h'bffff h'c0000 h'dffff h'e0000 area 0 area 1 area 2 area 3 area 4 area 5 area 6 area 7 external address space external address space vector area on-chip ram* on-chip ram* 8-bit absolute addresses 16-bit absolute addresses h'f8000 h'fdf1f h'fdf20 h'fff00 h'fff1f h'fff20 h'fffe9 h'fffea h'fffff modes 3 and 4 (16-mbyte expanded modes with on-chip rom disabled) h'000000 h'0000ff h'007fff memory-indirect branch addresses 16-bit absolute addresses h'1fffff h'200000 area 0 area 1 area 2 area 3 area 4 area 5 area 6 area 7 external address space vector area external address space 8-bit absolute addresses 16-bit absolute addresses h'ff8000 h'ffdf1f h'ffdf20 h'ffff1f h'ffff20 h'ffff00 h'ffffe9 h'ffffea h'ffffff h'3fffff h'400000 h'5fffff h'600000 h'7fffff h'800000 h'9fffff h'a00000 h'bfffff h'c00000 h'dfffff h'e00000 h'fee000 h'fee0ff note: * external addresses can be accessed by disabling on-chip ram. internal i/o registers (1) internal i/o registers (1) internal i/o registers (2) internal i/o registers (2) external address space h'ee000 h'ee0ff external address space figure 3.2 memory map of h8/3026f-ztat and h8/3026 mask rom version in each operating mode 68 h'000000 h'0000ff h'007fff memory-indirect branch addresses 16-bit absolute addresses mode 5 (16-mbyte expanded mode with on-chip rom enabled) mode 6 (single-chip normal mode) mode 7 (single-chip advanced mode) h'03ffff h'040000 h'1fffff h'200000 h'3fffff h'400000 h'5fffff h'600000 h'7fffff h'800000 h'9fffff h'a00000 h'bfffff h'c00000 h'dfffff h'e00000 area 0 area 1 area 2 area 3 area 4 area 5 area 6 area 7 external address space external address space vector area on-chip rom (flash memory) on-chip ram* external address space internal i/o registers (1) internal i/o registers (1) internal i/o registers (2) 8-bit absolute addresses 16-bit absolute addresses h'fee000 h'fee0ff h'ff8000 h'ffdf1f h'ffdf20 h'ffff00 h'ffff1f h'ffff20 h'ffffe9 h'ffffea h'ffffff h'00000 h'000ff memory-indirect branch addresses 16-bit absolute addresses vector area on-chip rom (flash memory) on-chip ram internal i/o registers(2) 8-bit absolute addresses 16-bit absolute addresses h'ee000 h'ee0ff h'fff1f h'fff20 h'fdf20 h'fffe9 h'fffff h'fff00 h'07fff h'3ffff h'f8000 note: * external addresses can be accessed by disabling on-chip ram. h'0000 h'00ff h'dfff h'e000 memory-indirect branch addresses vector area internal i/o registers (2) internal i/o registers (1) 8-bit absolute addresses h'e720 h'e0ff h'ff00 h'ff1f h'ff20 h'ffff h'ffe9 on-chip ram on-chip rom (flash memory) figure 3.2 memory map of h8/3026f-ztat and h8/3026 mask rom version in each operating mode (cont) 69 section 4 exception handling 4.1 overview 4.1.1 exception handling types and priority as table 4.1 indicates, exception handling may be caused by a reset, interrupt, or trap instruction. exception handling is prioritized as shown in table 4.1. if two or more exceptions occur simultaneously, they are accepted and processed in priority order. trap instruction exceptions are accepted at all times in the program execution state. table 4.1 exception types and priority priority exception type start of exception handling high reset starts immediately after a low-to-high transition at the res 4.1.2 exception handling operation exceptions originate from various sources. trap instructions and interrupts are handled as follows. 1. the program counter (pc) and condition code register (ccr) are pushed onto the stack. 2. the ccr interrupt mask bit is set to 1. 3. a vector address corresponding to the exception source is generated, and program execution starts from that address. note: for a reset exception, steps 2 and 3 above are carried out. 70 4.1.3 exception vector table the exception sources are classified as shown in figure 4.1. different vectors are assigned to different exception sources. table 4.2 lists the exception sources and their vector addresses. exception sources ? reset ? interrupts ? trap instruction external interrupts: internal interrupts: nmi, irq to irq 27 interrupts from on-chip supporting modules 0 5 figure 4.1 exception sources 71 table 4.2 exception vector table vector address* 1 exception source vector number advanced mode normal mode reset 0 h'0000 to h'0003 h'0000 to h'0001 reserved for system use 1 h'0004 to h'0007 h'0002 to h'0003 2 h'0008 to h'000b h'0004 to h'0005 3 h'000c to h'000f h'0006 to h'0007 4 h'0010 to h'0013 h'0008 to h'0009 5 h'0014 to h'0017 h'000a to h'000b 6 h'0018 to h'001b h'000c to h'000d external interrupt (nmi) 7 h'001c to h'001f h'000e to h'000f trap instruction (4 sources) 8 h'0020 to h'0023 h'0010 to h'0011 9 h'0024 to h'0027 h'0012 to h'0013 10 h'0028 to h'002b h'0014 to h'0015 11 h'002c to h'002f h'0016 to h'0017 external interrupt irq 0 12 h'0030 to h'0033 h'0018 to h'0019 external interrupt irq 1 13 h'0034 to h'0037 h'001a to h'001b external interrupt irq 2 14 h'0038 to h'003b h'001c to h'001d external interrupt irq 3 15 h'003c to h'003f h'001e to h'001f external interrupt irq 4 16 h'0040 to h'0043 h'0020 to h'0021 external interrupt irq 5 17 h'0044 to h'0047 h'0022 to h'0023 reserved for system use 18 h'0048 to h'004b h'0024 to h'0025 19 h'004c to h'004f h'0026 to h'0027 internal interrupts* 2 20 to 63 h'0050 to h'0053 to h'00fc to h'00ff h'0028 to h'0029 to h'007e to h'007f notes: *1 lower 16 bits of the address. *2 for the internal interrupt vectors, see section 5.3.3, interrupt exception handling vector table. 72 4.2 reset 4.2.1 overview a reset is the highest-priority exception. when the res pin goes low, all processing halts and the chip enters the reset state. a reset initializes the internal state of the cpu and the registers of the on-chip supporting modules. reset exception handling begins when the res pin changes from low to high. the chip can also be reset by overflow of the watchdog timer. for details see section 11, watchdog timer. 4.2.2 reset sequence the chip enters the reset state when the res pin goes low. to ensure that the chip is reset, hold the res pin low for at least 20 ms at power-up. to reset the chip during operation, hold the res pin low for at least 10 system clock (? cycles. in the versions with on-chip flash memory, the res pin must be held low for at least 20 system clock cycles. see appendix d.2, pin states at reset, for the states of the pins in the reset state. when the res pin goes high after being held low for the necessary time, the chip starts reset exception handling as follows. ? the internal state of the cpu and the registers of the on-chip supporting modules are initialized, and the i bit is set to 1 in ccr. ? the contents of the reset vector address (h'0000 to h'0003 in advanced mode, h'0000 to h'0001 in normal mode) are read, and program execution starts from the address indicated in the vector address. figure 4.2 shows the reset sequence in modes 1 and 3. figure 4.3 shows the reset sequence in modes 2 and 4. figure 4.4 shows the reset sequence in mode 6. 73 address bus res rd hwr d to d 15 8 vector fetch internal processing prefetch of first program instruction (1), (3), (5), (7) (2), (4), (6), (8) (9) (10) note: after a reset, the wait-state controller inserts three wait states in every bus cycle. address of reset exception handling vector: (1) = h'000000, (3) = h'000001, (5) = h'000002, (7) = h'000003 start address (contents of reset exception handling vector address) start address first instruction of program high (1) (3) (5) (7) (9) (2) (4) (6) (8) (10) lwr , figure 4.2 reset sequence (modes 1 and 3) 74 address bus res rd hwr d to d 15 0 vector fetch internal processing prefetch of first program instruction (1), (3) (2), (4) (5) (6) note: after a reset, the wait-state controller inserts three wait states in every bus cycle. high lwr , address of reset exception handling vector: (1) = h'000000, (3) = h'000002 start address (contents of reset exception handling vector address) start address first instruction of program (2) (4) (3) (1) (5) (6) figure 4.3 reset sequence (modes 2 and 4) 75 vector fetch internal processing prefetch of first program instruction internal address bus res internal read signal internal write signal internal data bus (16 bits wide) (1) (2) (2) (3) (1) address of reset exception handling vector (h'0000) (2) start address (contents of reset exception handling vector address) (3) first instruction of program figure 4.4 reset sequence (mode 6) 4.2.3 interrupts after reset if an interrupt is accepted after a reset but before the stack pointer (sp) is initialized, pc and ccr will not be saved correctly, leading to a program crash. to prevent this, all interrupt requests, including nmi, are disabled immediately after a reset exception handling. the first instruction of the program is always executed immediately after the reset state ends. this instruction should initialize the stack pointer (example: mov.l #xx:32, sp). 76 4.3 interrupts interrupt exception handling can be requested by seven external sources (nmi, irq 0 to irq 5 ), and 27 internal sources in the on-chip supporting modules. figure 4.5 classifies the interrupt sources and indicates the number of interrupts of each type. the on-chip supporting modules that can request interrupts are the watchdog timer (wdt), 16-bit timer, 8-bit timer, serial communication interface (sci), and a/d converter. each interrupt source has a separate vector address. nmi is the highest-priority interrupt and is always accepted*. interrupts are controlled by the interrupt controller. the interrupt controller can assign interrupts other than nmi to two priority levels, and arbitrate between simultaneous interrupts. interrupt priorities are assigned in interrupt priority registers a and b (ipra and iprb) in the interrupt controller. for details on interrupts see section 5, interrupt controller. interrupts external interrupts internal interrupts nmi (1) irq to irq (6) wdt * (1) 16-bit timer (9) 8-bit timer (8) sci (8) a/d converter (1) note: numbers in parentheses are the number of interrupt sources. * when the watchdog timer is used as an interval timer, it generates an interrupt request at every counter overflow. 0 5 figure 4.5 interrupt sources and number of interrupts note: * in the versions with on-chip flash memory, nmi input is sometimes disabled. for details see 17.9, nmi input disabling conditions. 4.4 trap instruction trap instruction exception handling starts when a trapa instruction is executed. if the ue bit is set to 1 in the system control register (syscr), the exception handling sequence sets the i bit to 1 in ccr. if the ue bit is 0, the i and ui bits are both set to 1 in ccr. the trapa instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, which is specified in the instruction code. 77 4.5 stack status after exception handling figure 4.6 shows the stack after completion of trap instruction exception handling and interrupt exception handling. sp e 4 sp e 3 sp e 2 sp e 1 sp (er7) sp (er7) sp+1 sp+2 sp+3 sp+4 sp e 4 sp e 3 sp e 2 sp e 1 sp (er7) sp (er7) sp+1 sp+2 sp+3 sp+4 before exception handling before exception handling after exception handling stack area stack area ccr ccr pc pc ccr pc pc pc h l e h l * after exception handling even address even address pushed on stack pushed on stack a. normal mode b. advanced mode legend pc e : pc h : pc l : ccr: sp: notes: pc indicates the address of the first instruction that will be executed after return. registers must be saved in word or longword size at even addresses. ignored at return. 1. 2. * bits 23 to 16 of program counter (pc) bits 15 to 8 of program counter (pc) bits 7 to 0 of program counter (pc) condition code register stack pointer figure 4.6 stack after completion of exception handling 78 4.6 notes on stack usage when accessing word data or longword data, the h8/3024 series regards the lowest address bit as 0. the stack should always be accessed by word access or longword access, and the value of the stack pointer (sp:er7) should always be kept even. use the following instructions to save registers: push.w rn (or mov.w rn, @ sp) push.l ern (or mov.l ern, @ sp) use the following instructions to restore registers: pop.w rn (or mov.w @sp+, rn) pop.l ern (or mov.l @sp+, ern) setting sp to an odd value may lead to a malfunction. figure 4.7 shows an example of what happens when the sp value is odd. 79 trapa instruction executed ccr legend ccr: pc: r1l: sp: sp pc r1l pc sp sp mov. b r1l, @-er7 sp set to h'fffeff data saved above sp ccr contents lost condition code register program counter general register r1l stack pointer note: the diagram illustrates modes 3 to 5. h'fffefa h'fffefb h'fffefc h'fffefd h'fffefe h'fffeff figure 4.7 operation when sp value is odd 80 81 section 5 interrupt controller 5.1 overview 5.1.1 features the interrupt controller has the following features: ? interrupt priority registers (iprs) for setting interrupt priorities interrupts other than nmi can be assigned to two priority levels on a module-by-module basis in interrupt priority registers a and b (ipra and iprb). ? three-level enabling/disabling by the i and ui bits in the cpu? condition code register (ccr) and the ue bit in the system control register (syscr) ? seven external interrupt pins nmi has the highest priority and is always accepted*; either the rising or falling edge can be selected. for each of irq 0 to irq 5 , sensing of the falling edge or level sensing can be selected independently. note: * in the versions with on-chip flash memory, nmi input is sometimes disabled. for details see 17.9, nmi input disabling conditions. 82 5.1.2 block diagram figure 5.1 shows a block diagram of the interrupt controller. iscr ier ipra, iprb . . . ovf tme tei teie . . . . . . . cpu ccr i ui ue syscr nmi input irq input irq input section isr interrupt controller priority decision logic interrupt request vector number irq sense control register irq enable register irq status register interrupt priority register a interrupt priority register b system control register legend: iscr: ier: isr: ipra: iprb: syscr: figure 5.1 interrupt controller block diagram 83 5.1.3 pin configuration table 5.1 lists the interrupt pins. table 5.1 interrupt pins name abbreviation i/o function nonmaskable interrupt nmi input nonmaskable interrupt*, rising edge or falling edge selectable external interrupt request 5 to 0 irq irq 5.1.4 register configuration table 5.2 lists the registers of the interrupt controller. table 5.2 interrupt controller registers address* 1 name abbreviation r/w initial value h'ee012 system control register syscr r/w h'09 h'ee014 irq sense control register iscr r/w h'00 h'ee015 irq enable register ier r/w h'00 h'ee016 irq status register isr r/(w)* 2 h'00 h'ee018 interrupt priority register a ipra r/w h'00 h'ee019 interrupt priority register b iprb r/w h'00 notes: *1 lower 20 bits of the address in advanced mode. *2 only 0 can be written, to clear flags. 5.2 register descriptions 5.2.1 system control register (syscr) syscr is an 8-bit readable/writable register that controls software standby mode, selects the action of the ui bit in ccr, selects the nmi edge, and enables or disables the on-chip ram. only bits 3 and 2 are described here. for the other bits, see section 3.3, system control register (syscr). 84 syscr is initialized to h'09 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit initial value read/write 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 4 sts0 0 r/w 3 ue 1 r/w 0 rame 1 r/w 2 nmieg 0 r/w 1 ssoe 0 r/w software standby standby timer select 2 to 0 user bit enable selects whether to use the ui bit in ccr as a user bit or interrupt mask bit nmi edge select selects the nmi input edge software standby output port enable ram enable bit 3?ser bit enable (ue): selects whether to use the ui bit in ccr as a user bit or an interrupt mask bit. bit 3 ue description 0 ui bit in ccr is used as interrupt mask bit 1 ui bit in ccr is used as user bit (initial value) bit 2?mi edge select (nmieg): selects the nmi input edge. bit 2 nmieg description 0 interrupt is requested at falling edge of nmi input (initial value) 1 interrupt is requested at rising edge of nmi input 5.2.2 interrupt priority registers a and b (ipra, iprb) ipra and iprb are 8-bit readable/writable registers that control interrupt priority. 85 interrupt priority register a (ipra): ipra is an 8-bit readable/writable register in which interrupt priority levels can be set. bit initial value read/write 7 ipra7 0 r/w 6 ipra6 0 r/w 5 ipra5 0 r/w 4 ipra4 0 r/w 3 ipra3 0 r/w 0 ipra0 0 r/w 2 ipra2 0 r/w 1 ipra1 0 r/w priority level a7 selects the priority level of irq interrupt requests priority level a3 selects the priority level of wdt, and a/d converter interrupt requests priority level a2 selects the priority level of 16-bit timer channel 0 interrupt requests priority level a1 selects the priority level of 16-bit timer channel 1 interrupt requests priority level a0 selects the priority level of 16-bit timer channel 2 interrupt requests selects the priority level of irq interrupt requests priority level a6 selects the priority level of irq and irq interrupt requests priority level a5 selects the priority level of irq and irq interrupt requests priority level a4 0 1 23 45 ipra is initialized to h'00 by a reset and in hardware standby mode. 86 bit 7?riority level a7 (ipra7): selects the priority level of irq 0 interrupt requests. bit 7 ipra7 description 0 irq 0 interrupt requests have priority level 0 (low priority) (initial value) 1 irq 0 interrupt requests have priority level 1 (high priority) bit 6?riority level a6 (ipra6): selects the priority level of irq 1 interrupt requests. bit 6 ipra6 description 0 irq 1 interrupt requests have priority level 0 (low priority) (initial value) 1 irq 1 interrupt requests have priority level 1 (high priority) bit 5?riority level a5 (ipra5): selects the priority level of irq 2 and irq 3 interrupt requests. bit 5 ipra5 description 0 irq 2 and irq 3 interrupt requests have priority level 0 (low priority) (initial value) 1 irq 2 and irq 3 interrupt requests have priority level 1 (high priority) bit 4?riority level a4 (ipra4): selects the priority level of irq 4 and irq 5 interrupt requests. bit 4 ipra4 description 0 irq 4 and irq 5 interrupt requests have priority level 0 (low priority) (initial value) 1 irq 4 and irq 5 interrupt requests have priority level 1 (high priority) bit 3?riority level a3 (ipra3): selects the priority level of wdt, and a/d converter interrupt requests. bit 3 ipra3 description 0 wdt, and a/d converter interrupt requests have priority level 0 (low priority) (initial value) 1 wdt, and a/d converter interrupt requests have priority level 1 (high priority) 87 bit 2?riority level a2 (ipra2): selects the priority level of 16-bit timer channel 0 interrupt requests. bit 2 ipra2 description 0 16-bit timer channel 0 interrupt requests have priority level 0 (low priority) (initial value) 1 16-bit timer channel 0 interrupt requests have priority level 1 (high priority) bit 1?riority level a1 (ipra1): selects the priority level of 16-bit timer channel 1 interrupt requests. bit 1 ipra1 description 0 16-bit timer channel 1 interrupt requests have priority level 0 (low priority) (initial value) 1 16-bit timer channel 1 interrupt requests have priority level 1 (high priority) bit 0?riority level a0 (ipra0): selects the priority level of 16-bit timer channel 2 interrupt requests. bit 0 ipra0 description 0 16-bit timer channel 2 interrupt requests have priority level 0 (low priority) (initial value) 1 16-bit timer channel 2 interrupt requests have priority level 1 (high priority) 88 interrupt priority register b (iprb): iprb is an 8-bit readable/writable register in which interrupt priority levels can be set. bit initial value read/write 7 iprb7 0 r/w 6 iprb6 0 r/w 5 0 r/w 4 0 r/w 3 iprb3 0 r/w 0 0 r/w 2 iprb2 0 r/w 1 0 r/w priority level b7 selects the priority level of 8-bit timer channel 0, 1 interrupt requests priority level b3 selects the priority level of sci channel 0 interrupt requests priority level b2 selects the priority level of sci channel 1 interrupt requests reserved bit reserved bit selects the priority level of 8-bit timer channel 2, 3 interrupt requests priority level b6 iprb is initialized to h'00 by a reset and in hardware standby mode. bit 7?riority level b7 (iprb7): selects the priority level of 8-bit timer channel 0, 1 interrupt requests. bit 7 iprb7 description 0 8-bit timer channel 0 and 1 interrupt requests have priority level 0 (low priority) (initial value) 1 8-bit timer channel 0 and 1 interrupt requests have priority level 1 (high priority) 89 bit 6?riority level b6 (iprb6): selects the priority level of 8-bit timer channel 2, 3 interrupt requests. bit 6 iprb6 description 0 8-bit timer channel 2 and 3 interrupt requests have priority level 0 (low priority) (initial value) 1 8-bit timer channel 2 and 3 interrupt requests have priority level 1 (high priority) bits 5 and 4?eserved: this bit can be written and read, but it does not affect interrupt priority. bit 3?riority level b3 (iprb3): selects the priority level of sci channel 0 interrupt requests. bit 3 iprb3 description 0 sci0 channel 0 interrupt requests have priority level 0 (low priority) (initial value) 1 sci0 channel 0 interrupt requests have priority level 1 (high priority) bit 2?riority level b2 (iprb2): selects the priority level of sci channel 1 interrupt requests. bit 2 iprb2 description 0 sci1 channel 1 interrupt requests have priority level 0 (low priority) (initial value) 1 sci1 channel 1 interrupt requests have priority level 1 (high priority) bits 1 and 0?eserved: this bit can be written and read, but it does not affect interrupt priority. 5.2.3 irq status register (isr) isr is an 8-bit readable/writable register that indicates the status of irq 0 to irq 5 interrupt requests. 90 bit initial value read/write 7 ? 0 ? these bits indicate irq to irq flag interrupt request status note: only 0 can be written, to clear flags. * 6 ? 0 ? 5 irq5f 0 r/(w) * 4 irq4f 0 r/(w) * 3 irq3f 0 r/(w) * 2 irq2f 0 r/(w) * 1 irq1f 0 r/(w) * 0 irq0f 0 r/(w) * 50 irq to irq flags 50 reserved bits isr is initialized to h'00 by a reset and in hardware standby mode. bits 7 and 6?eserved: these bits can not be modified and are always read as 0. bits 5 to 0?rq 5 to irq 0 flags (irq5f to irq0f): these bits indicate the status of irq 5 to irq 0 interrupt requests. bits 5 to 0 irq5f to irq0f description 0 [clearing conditions] (initial value) 0 is written in irqnf after reading the irqnf flag when irqnf = 1. irqnsc = 0, irqn irqn irqn 5.2.4 irq enable register (ier) ier is an 8-bit readable/writable register that enables or disables irq 5 to irq 0 interrupt requests. bit initial value read/write 7 ? 0 r/w these bits enable or disable irq to irq interrupts 6 ? 0 r/w 5 irq5e 0 r/w 4 irq4e 0 r/w 3 irq3e 0 r/w 2 irq2e 0 r/w 1 irq1e 0 r/w 0 irq0e 0 r/w 50 irq to irq enable 50 reserved bits ier is initialized to h'00 by a reset and in hardware standby mode. 91 bits 7 and 6?eserved: these bits can be written and read, but they do not enable or disable interrupts. bits 5 to 0?rq 5 to irq 0 enable (irq5e to irq0e): these bits enable or disable irq 5 to irq 0 interrupts. bits 5 to 0 irq5e to irq0e description 0 irq 5 to irq 0 interrupts are disabled (initial value) 1 irq 5 to irq 0 interrupts are enabled 5.2.5 irq sense control register (iscr) iscr is an 8-bit readable/writable register that selects level sensing or falling-edge sensing of the inputs at pins irq 5 to irq 0 . bit initial value read/write 7 ? 0 r/w these bits select level sensing or falling-edge sensing for irq to irq interrupts 6 ? 0 r/w 5 irq5sc 0 r/w 4 irq4sc 0 r/w 3 irq3sc 0 r/w 2 irq2sc 0 r/w 1 irq1sc 0 r/w 0 irq0sc 0 r/w 50 irq to irq sense control 50 reserved bits iscr is initialized to h'00 by a reset and in hardware standby mode. bits 7 and 6?eserved: these bits can be written and read, but they do not select level or falling-edge sensing. bits 5 to 0?rq 5 to irq 0 sense control (irq5sc to irq0sc): these bits select whether interrupts irq 5 to irq 0 are requested by level sensing of pins irq 5 to irq 0 , or by falling-edge sensing. bits 5 to 0 irq5sc to irq0sc description 0 interrupts are requested when irq irq irq irq 92 5.3 interrupt sources the interrupt sources include external interrupts (nmi, irq 0 to irq 5 ) and 27 internal interrupts. 5.3.1 external interrupts there are seven external interrupts: nmi, and irq 0 to irq 5 . of these, nmi, irq 0 , irq 1 , and irq 2 can be used to exit software standby mode. nmi: nmi is the highest-priority interrupt and is always accepted, regardless of the states of the i and ui bits in ccr*. the nmieg bit in syscr selects whether an interrupt is requested by the rising or falling edge of the input at the nmi pin. nmi interrupt exception handling has vector number 7. note: * in the versions with on-chip flash memory, nmi input is sometimes disabled. for details see 17.9, nmi input disabling conditions. irq 0 to irq 5 interrupts: these interrupts are requested by input signals at pins irq 0 to irq 5 . the irq 0 to irq 5 interrupts have the following features. ? iscr settings can select whether an interrupt is requested by the low level of the input at pins irq 0 to irq 5 , or by the falling edge. ? ier settings can enable or disable the irq 0 to irq 5 interrupts. interrupt priority levels can be assigned by four bits in ipra (ipra7 to ipra4). ? the status of irq 0 to irq 5 interrupt requests is indicated in isr. the isr flags can be cleared to 0 by software. figure 5.2 shows a block diagram of interrupts irq 0 to irq 5 . input edge/level sense circuit irqnsc irqnf s r q irqne irqn interrupt request clear signal irqn figure 5.2 block diagram of interrupts irq 0 to irq 5 93 figure 5.3 shows the timing of the setting of the interrupt flags (irqnf). irqn figure 5.3 timing of setting of irqnf interrupts irq 0 to irq 5 have vector numbers 12 to 17. these interrupts are detected regardless of whether the corresponding pin is set for input or output. when using a pin for external interrupt input, clear its ddr bit to 0 and do not use the pin for chip select output, sci input/output, or a/d external trigger input. 5.3.2 internal interrupts twenty-seven internal interrupts are requested from the on-chip supporting modules. ? each on-chip supporting module has status flags for indicating interrupt status, and enable bits for enabling or disabling interrupts. ? interrupt priority levels can be assigned in ipra and iprb. 5.3.3 interrupt exception handling vector table table 5.3 lists the interrupt exception handling sources, their vector addresses, and their default priority order. in the default priority order, smaller vector numbers have higher priority. the priority of interrupts other than nmi can be changed in ipra and iprb. the priority order after a reset is the default order shown in table 5.3. 94 table 5.3 interrupt sources, vector addresses, and priority vector vector address* interrupt source origin number advanced mode normal mode ipr priority nmi external 7 h'001c to h'001f h'000e to h'000f ? high irq 0 pins 12 h'0030 to h'0033 h'0018 to h'0019 ipra7 irq 1 13 h'0034 to h0037 h'001a to h'001b ipra6 irq 2 irq 3 14 15 h'0038 to h'003b h'003c to h'003f h'001c to h'001d h'001e to h'001f ipra5 irq 4 irq 5 16 17 h'0040 to h'0043 h'0044 to h'0047 h'0020 to h'0021 h'0022 to h'0023 ipra4 reserved ? 18 19 h'0048 to h'004b h'004c to h'004f h'0024 to h'0025 h'0026 to h'0027 wovi (interval timer) watchdog timer 20 h'0050 to h'0053 h'0028 to h'0029 ipra3 reserved ? 21 h'0054 to h'0057 h'002a to h'002b 22 h'0058 to h'005b h'002c to h'002d adi (a/d end) a/d 23 h'005c to h'005f h'002e to h'002f imia0 (compare match/ input capture a0) imib0 (compare match/ input capture b0) ovi0 (overflow 0) 16-bit timer channel 0 24 25 26 h'0060 to h'0063 h'0064 to h'0067 h'0068 to h'006b h'0030 to h'0031 h'0032 to h'0033 h'0034 to h'0035 ipra2 reserved ? 27 h'006c to h'006f h'0036 to h'0037 imia1 (compare match/ inputcapture a1) imib1 (compare match/ input capture b1) ovi1 (overflow 1) 16-bit timer channel 1 28 29 30 h'0070 to h'0073 h'0074 to h'0077 h'0078 to h'007b h'0038 to h'0039 h'003a to h'003b h'003c to h'003d ipra1 reserved ? 31 h'007c to h'007f h'003e to h'003f low 95 vector vector address* interrupt source origin number advanced mode normal mode ipr priority imia2 (compare match/ input capture a2) imib2 (compare match/ input capture b2) ovi2 (overflow 2) 16-bit timer channel 2 32 33 34 h'0080 to h'0083 h'0084 to h'0087 h'0088 to h'008b h'0040 to h'0041 h'0042 to h'0043 h'0044 to h'0045 ipra0 high reserved ? 35 h'008c to h'008f h'0046 to h'0047 cmia0 (compare match a0) cmib0 (compare match b0) cmia1/cmib1 (compare match a1/b1) tovi0/tovi1 (overflow 0/1) 8-bit timer channel 0/1 36 37 38 39 h'0090 to h'0093 h'0094 to h'0097 h'0098 to h'009b h'009c to h'009f h'0048 to h'0049 h'004a to h'004b h'004c to h'004d h'004e to h'004f iprb7 cmia2 (compare match a2) cmib2 (compare match b2) cmia3/cmib3 (compare match a3/b3) tovi2/tovi3 (overflow 2/3) 8-bit timer channel 2/3 40 41 42 43 h'00a0 to h'00a3 h'00a4 to h'00a7 h'00a8 to h'00ab h'00ac to h'00af h'0050 to h'0051 h'0052 to h'0053 h'0054 to h'0055 h'0056 to h'0057 iprb6 reserved ? 44 45 46 47 h'00b0 to h'00b3 h'00b4 to h'00b7 h'00b8 to h'00bb h'00bc to h'00bf h'0058 to h'0059 h'005a to h'005b h'005c to h'005d h'005e to h'005f ? 48 49 50 51 h'00c0 to h'00c3 h'00c4 to h'00c7 h'00c8 to h'00cb h'00cc to h'00cf h'0060 to h'0061 h'0062 to h'0063 h'0064 to h'0065 h'0066 to h'0067 low 96 vector vector address* interrupt source origin number advanced mode normal mode ipr priority eri0 (receive error 0) rxi0 (receive data full 0) txi0 (transmit data empty 0) tei0 (transmit end 0) sci channel 0 52 53 54 55 h'00d0 to h'00d3 h'00d4 to h'00d7 h'00d8 to h'00db h'00dc to h'00df h'0068 to h'0069 h'006a to h'006b h'006c to h'006d h'006e to h'006f iprb3 high eri1 (receive error 1) rxi1 (receive data full 1) txi1 (transmit data empty 1) tei1 (transmit end 1) sci channel 1 56 57 58 59 h'00e0 to h'00e3 h'00e4 to h'00e7 h'00e8 to h'00eb h'00ec to h'00ef h'0070 to h'0071 h'0072 to h'0073 h'0074 to h'0075 h'0076 to h'0077 iprb2 reserved ? 60 61 62 63 h'00f0 to h'00f3 h'00f4 to h'00f7 h'00f8 to h'00fb h'00fc to h'00ff h'0078 to h'0079 h'007a to h'007b h'007c to h'007d h'007e to h'007f ? low note: * lower 16 bits of the address. 97 5.4 interrupt operation 5.4.1 interrupt handling process the h8/3024 series handles interrupts differently depending on the setting of the ue bit. when ue = 1, interrupts are controlled by the i bit. when ue = 0, interrupts are controlled by the i and ui bits. table 5.4 indicates how interrupts are handled for all setting combinations of the ue, i, and ui bits. nmi interrupts are always accepted except in the reset and hardware standby states*. irq interrupts and interrupts from the on-chip supporting modules have their own enable bits. interrupt requests are ignored when the enable bits are cleared to 0. note: * in the versions with on-chip flash memory, nmi input is sometimes disabled. for details see 17.9, nmi input disabling conditions. table 5.4 ue, i, and ui bit settings and interrupt handling syscr ccr ue i ui description 10 ? all interrupts are accepted. interrupts with priority level 1 have higher priority. 1 ? no interrupts are accepted except nmi. 00 ? all interrupts are accepted. interrupts with priority level 1 have higher priority. 1 0 nmi and interrupts with priority level 1 are accepted. 1 no interrupts are accepted except nmi. ue = 1: interrupts irq 0 to irq 5 and interrupts from the on-chip supporting modules can all be masked by the i bit in the cpu s ccr. interrupts are masked when the i bit is set to 1, and unmasked when the i bit is cleared to 0. interrupts with priority level 1 have higher priority. figure 5.4 is a flowchart showing how interrupts are accepted when ue = 1. 98 program execution state interrupt requested? nmi no yes no yes no priority level 1? no irq 0 yes no irq 1 yes tei1 yes no irq 0 yes no irq 1 yes tei1 yes no i = 0 yes save pc and ccr i 1 branch to interrupt service routine figure 5.4 process up to interrupt acceptance when ue = 1 99 ? if an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. ? when the interrupt controller receives one or more interrupt requests, it selects the highest- priority request, following the ipr interrupt priority settings, and holds other requests pending. if two or more interrupts with the same ipr setting are requested simultaneously, the interrupt controller follows the priority order shown in table 5.3. ? the interrupt controller checks the i bit. if the i bit is cleared to 0, the selected interrupt request is accepted. if the i bit is set to 1, only nmi is accepted; other interrupt requests are held pending. ? when an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. ? in interrupt exception handling, pc and ccr are saved to the stack area. the pc value that is saved indicates the address of the first instruction that will be executed after the return from the interrupt service routine. ? next the i bit is set to 1 in ccr, masking all interrupts except nmi. ? the vector address of the accepted interrupt is generated, and the interrupt service routine starts executing from the address indicated by the contents of the vector address. ue = 0: the i and ui bits in the cpu s ccr and the ipr bits enable three-level masking of irq 0 to irq 5 interrupts and interrupts from the on-chip supporting modules. ? interrupt requests with priority level 0 are masked when the i bit is set to 1, and are unmasked when the i bit is cleared to 0. ? interrupt requests with priority level 1 are masked when the i and ui bits are both set to 1, and are unmasked when either the i bit or the ui bit is cleared to 0. for example, if the interrupt enable bits of all interrupt requests are set to 1, ipra is set to h'20, and iprb is set to h'00 (giving irq 2 and irq 3 interrupt requests priority over other interrupts), interrupts are masked as follows: a. if i = 0, all interrupts are unmasked (priority order: nmi > irq 2 > irq 3 >irq 0 ). b. if i = 1 and ui = 0, only nmi, irq 2 , and irq 3 are unmasked. c. if i = 1 and ui = 1, all interrupts are masked except nmi. figure 5.5 shows the transitions among the above states. 100 all interrupts are unmasked only nmi, irq , and irq are unmasked exception handling, or i 1, ui 1 a. b. 2 3 all interrupts are masked except nmi c. ui 0 i 0 exception handling, or ui 1 i 0 i 1, ui 0 figure 5.5 interrupt masking state transitions (example) figure 5.6 is a flowchart showing how interrupts are accepted when ue = 0. ? if an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. ? when the interrupt controller receives one or more interrupt requests, it selects the highest- priority request, following the ipr interrupt priority settings, and holds other requests pending. if two or more interrupts with the same ipr setting are requested simultaneously, the interrupt controller follows the priority order shown in table 5.3. ? the interrupt controller checks the i bit. if the i bit is cleared to 0, the selected interrupt request is accepted regardless of its ipr setting, and regardless of the ui bit. if the i bit is set to 1 and the ui bit is cleared to 0, only interrupts with priority level 1 are accepted; interrupt requests with priority level 0 are held pending. if the i bit and ui bit are both set to 1, all other interrupt requests are held pending. ? when an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. ? in interrupt exception handling, pc and ccr are saved to the stack area. the pc value that is saved indicates the address of the first instruction that will be executed after the return from the interrupt service routine. ? the i and ui bits are set to 1 in ccr, masking all interrupts except nmi. ? the vector address of the accepted interrupt is generated, and the interrupt service routine starts executing from the address indicated by the contents of the vector address. 101 program execution state interrupt requested? nmi no yes no yes no priority level 1? no irq 0 yes no irq 1 yes tei1 yes no irq 0 yes no irq 1 yes tei1 yes no i = 0 yes no i = 0 yes ui = 0 yes no save pc and ccr i 1, ui 1 figure 5.6 process up to interrupt acceptance when ue = 0 102 5.4.2 interrupt exception handling sequence figure 5.7 shows the interrupt exception handling sequence in mode 2 when the program code and stack are in an external memory area accessed in two states via a 16-bit bus. rd hwr lwr figure 5.7 interrupt exception handling sequence 103 5.4.3 interrupt response time table 5.5 indicates the interrupt response time from the occurrence of an interrupt request until the first instruction of the interrupt service routine is executed. table 5.5 interrupt response time external memory on-chip 8-bit bus 16-bit bus no. item memory 2 states 3 states 2 states 3 states 1 interrupt priority decision 2* 1 2* 1 2* 1 2* 1 2* 1 2 maximum number of states until end of current instruction 1 to 23 1 to 27 1 to 31* 4 1 to 23 1 to 25* 4 3 saving pc and ccr to stack 4 8 12* 4 46* 4 4 vector fetch 4 8 12* 4 46* 4 5 instruction fetch* 2 4 8 12* 4 46* 4 6 internal processing* 3 44 4 4 4 total 19 to 41 31 to 57 43 to 73 19 to 41 25 to 49 notes: *1 1 state for internal interrupts. *2 prefetch after the interrupt is accepted and prefetch of the first instruction in the interrupt service routine. *3 internal processing after the interrupt is accepted and internal processing after vector fetch. *4 the number of states increases if wait states are inserted in external memory access. 104 5.5 usage notes 5.5.1 contention between interrupt and interrupt-disabling instruction when an instruction clears an interrupt enable bit to 0 to disable the interrupt, the interrupt is not disabled until after execution of the instruction is completed. if an interrupt occurs while a bclr, mov, or other instruction is being executed to clear its interrupt enable bit to 0, at the instant when execution of the instruction ends the interrupt is still enabled, so its interrupt exception handling is carried out. if a higher-priority interrupt is also requested, however, interrupt exception handling for the higher-priority interrupt is carried out, and the lower-priority interrupt is ignored. this also applies to the clearing of an interrupt flag to 0. figure 5.8 shows an example in which an imiea bit is cleared to 0 in the 16-bit timer s tisra register. imia exception handling tisra write cycle by cpu figure 5.8 contention between interrupt and interrupt-disabling instruction this type of contention will not occur if the interrupt is masked when the interrupt enable bit or flag is cleared to 0. 105 5.5.2 instructions that inhibit interrupts the ldc, andc, orc, and xorc instructions inhibit interrupts. when an interrupt occurs, after determining the interrupt priority, the interrupt controller requests a cpu interrupt. if the cpu is currently executing one of these interrupt-inhibiting instructions, however, when the instruction is completed the cpu always continues by executing the next instruction. 5.5.3 interrupts during eepmov instruction execution the eepmov.b and eepmov.w instructions differ in their reaction to interrupt requests. when the eepmov.b instruction is executing a transfer, no interrupts are accepted until the transfer is completed, not even nmi. when the eepmov.w instruction is executing a transfer, interrupt requests other than nmi are not accepted until the transfer is completed. if nmi is requested, nmi exception handling starts at a transfer cycle boundary. the pc value saved on the stack is the address of the next instruction. programs should be coded as follows to allow for nmi interrupts during eepmov.w execution: l1: eepmov.w mov.w r4,r4 bne l1 106 107 section 6 bus controller 6.1 overview the h8/3024 series has an on-chip bus controller (bsc) that manages the external address space divided into eight areas. the bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily. the bus controller also has a bus arbitration function that controls the operation of the internal bus masters?he cpu can release the bus to an external device. 6.1.1 features the features of the bus controller are listed below. ? manages external address space in area units ? manages the external space as eight areas (0 to 7) of 128 kbytes in 1m-byte modes, or 2 mbytes in 16-mbyte modes ? bus specifications can be set independently for each area ? basic bus interface ? chip select ( cs 0 to cs 7 ) can be output for areas 0 to 7 ? 8-bit access or 16-bit access can be selected for each area ? two-state access or three-state access can be selected for each area ? program wait states can be inserted for each area ? pin wait insertion capability is provided ? idle cycle insertion ? an idle cycle can be inserted in case of an external read cycle between different areas ? an idle cycle can be inserted when an external read cycle is immediately followed by an external write cycle ? bus arbitration function ? a built-in bus arbiter grants the bus right to the cpu, or an external bus master ? other features ? choice of two address update modes 108 6.1.2 block diagram figure 6.1 shows a block diagram of the bus controller. internal address bus abwcr astcr bcr cscr adrcr area decoder chip select control signals cs 0 to cs 7 bus control circuit wcrh wcrl brcr legend: wait state controller wait back breq internal data bus cpu bus request signal cpu bus acknowledge signal bus arbiter bus mode control signal internal signals internal signals bus size control signal access state control signal wait request signal bus width control register access state control register wait control register h wait control register l bus release control register chip select control register astcr: wcrh: wcrl: brcr: cscr: address control register adrcr: abwcr: bcr: bus control register figure 6.1 block diagram of bus controller 109 6.1.3 pin configuration table 6.1 summarizes the input/output pins of the bus controller. table 6.1 bus controller pins name abbreviation i/o function chip select 0 to 7 cs cs as rd hwr lwr wait breq back 110 6.1.4 register configuration table 6.2 summarizes the bus controller? registers. table 6.2 bus controller registers address* 1 name abbreviation r/w initial value h'ee020 bus width control register abwcr r/w h'ff* 2 h'ee021 access state control register astcr r/w h'ff h'ee022 wait control register h wcrh r/w h'ff h'ee023 wait control register l wcrl r/w h'ff h'ee013 bus release control register brcr r/w h'fe* 3 h'ee01f chip select control register cscr r/w h'0f h'ee01e address control register adrcr r/w h'ff h'ee024 bus control register bcr r/w h'c6 notes: *1 lower 20 bits of the address in advanced mode. *2 in modes 2 and 4, the initial value is h'00. *3 in modes 3 and 4, the initial value is h'ee. 6.2 register descriptions 6.2.1 bus width control register (abwcr) abwcr is an 8-bit readable/writable register that selects 8-bit or 16-bit access for each area. 7 abw7 1 r/w 0 r/w 6 abw6 1 r/w 0 r/w 5 abw5 1 r/w 0 r/w 4 abw4 1 r/w 0 r/w 3 abw3 1 r/w 0 r/w 2 abw2 1 r/w 0 r/w 1 abw1 1 r/w 0 r/w 0 abw0 1 r/w 0 r/w bit modes 1, 3, 5, 6, and 7 initial value read/write initial value read/write modes 2 and 4 when abwcr contains h'ff (selecting 8-bit access for all areas), the chip operates in 8-bit bus mode: the upper data bus (d 15 to d 8 ) is valid, and port 4 is an input/output port. when at least one bit is cleared to 0 in abwcr, the chip operates in 16-bit bus mode with a 16-bit data bus (d 15 to d 0 ). in modes 1, 3, 5, 6, and 7, abwcr is initialized to h'ff by a reset and in hardware standby mode. in modes 2 and 4, abwcr is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. 111 bits 7 to 0?rea 7 to 0 bus width control (abw7 to abw0): these bits select 8-bit access or 16-bit access for the corresponding areas. bits 7 to 0 abw7 to abw0 description 0 areas 7 to 0 are 16-bit access areas 1 areas 7 to 0 are 8-bit access areas abwcr specifies the data bus width of external memory areas. the data bus width of on-chip memory and registers is fixed, and does not depend on abwcr settings. these settings are therefore invalid in the single-chip modes (modes 6 and 7). 6.2.2 access state control register (astcr) astcr is an 8-bit readable/writable register that selects whether each area is accessed in two states or three states. ast3 ast2 ast1 ast0 1 initial value 1111111 read/write r/w r/w r/w r/w r/w r/w r/w r/w 76543210 bits selecting number of states for access to each area ast7 ast6 ast5 ast4 bit astcr is initialized to h'ff by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 7 to 0?rea 7 to 0 access state control (ast7 to ast0): these bits select whether the corresponding area is accessed in two or three states. bits 7 to 0 ast7 to ast0 description 0 areas 7 to 0 are accessed in two states 1 areas 7 to 0 are accessed in three states (initial value) astcr specifies the number of states in which external areas are accessed. on-chip memory and registers are accessed in a fixed number of states that does not depend on astcr settings. these settings are therefore meaningless in the single-chip modes (modes 6 and 7). 112 6.2.3 wait control registers h and l (wcrh, wcrl) wcrh and wcrl are 8-bit readable/writable registers that select the number of program wait states for each area. on-chip memory and registers are accessed in a fixed number of states that does not depend on wcrh/wcrl settings. wcrh and wcrl are initialized to h'ff by a reset and in hardware standby mode. they are not initialized in software standby mode. wcrh w51 w50 w41 w40 1 initial value 1111111 read/write r/w r/w r/w r/w r/w r/w r/w r/w 76543210 w71 w70 w61 w60 bit bits 7 and 6?rea 7 wait control 1 and 0 (w71, w70): these bits select the number of program wait states when area 7 in external space is accessed while the ast7 bit in astcr is set to 1. bit 7 w71 bit 6 w70 description 0 0 program wait not inserted when external space area 7 is accessed 1 1 program wait state inserted when external space area 7 is accessed 1 0 2 program wait states inserted when external space area 7 is accessed 1 3 program wait states inserted when external space area 7 is accessed (initial value) 113 bits 5 and 4?rea 6 wait control 1 and 0 (w61, w60): these bits select the number of program wait states when area 6 in external space is accessed while the ast6 bit in astcr is set to 1. bit 5 w61 bit 4 w60 description 0 0 program wait not inserted when external space area 6 is accessed 1 1 program wait state inserted when external space area 6 is accessed 1 0 2 program wait states inserted when external space area 6 is accessed 1 3 program wait states inserted when external space area 6 is accessed (initial value) bits 3 and 2?rea 5 wait control 1 and 0 (w51, w50): these bits select the number of program wait states when area 5 in external space is accessed while the ast5 bit in astcr is set to 1. bit 3 w51 bit 2 w50 description 0 0 program wait not inserted when external space area 5 is accessed 1 1 program wait state inserted when external space area 5 is accessed 1 0 2 program wait states inserted when external space area 5 is accessed 1 3 program wait states inserted when external space area 5 is accessed (initial value) bits 1 and 0?rea 4 wait control 1 and 0 (w41, w40): these bits select the number of program wait states when area 4 in external space is accessed while the ast4 bit in astcr is set to 1. bit 1 w41 bit 0 w40 description 0 0 program wait not inserted when external space area 4 is accessed 1 1 program wait state inserted when external space area 4 is accessed 1 0 2 program wait states inserted when external space area 4 is accessed 1 3 program wait states inserted when external space area 4 is accessed (initial value) 114 wcrl w11 w10 w01 w00 1 initial value 1111111 read/write r/w r/w r/w r/w r/w r/w r/w r/w 76543210 w31 w30 w21 w20 bit bits 7 and 6?rea 3 wait control 1 and 0 (w31, w30): these bits select the number of program wait states when area 3 in external space is accessed while the ast3 bit in astcr is set to 1. bit 7 w31 bit 6 w30 description 0 0 program wait not inserted when external space area 3 is accessed 1 1 program wait state inserted when external space area 3 is accessed 1 0 2 program wait states inserted when external space area 3 is accessed 1 3 program wait states inserted when external space area 3 is accessed (initial value) bits 5 and 4?rea 2 wait control 1 and 0 (w21, w20): these bits select the number of program wait states when area 2 in external space is accessed while the ast2 bit in astcr is set to 1. bit 5 w21 bit 4 w20 description 0 0 program wait not inserted when external space area 2 is accessed 1 1 program wait state inserted when external space area 2 is accessed 1 0 2 program wait states inserted when external space area 2 is accessed 1 3 program wait states inserted when external space area 2 is accessed (initial value) 115 bits 3 and 2?rea 1 wait control 1 and 0 (w11, w10): these bits select the number of program wait states when area 1 in external space is accessed while the ast1 bit in astcr is set to 1. bit 3 w11 bit 2 w10 description 0 0 program wait not inserted when external space area 1 is accessed 1 1 program wait state inserted when external space area 1 is accessed 1 0 2 program wait states inserted when external space area 1 is accessed 1 3 program wait states inserted when external space area 1 is accessed (initial value) bits 1 and 0?rea 0 wait control 1 and 0 (w01, w00): these bits select the number of program wait states when area 0 in external space is accessed while the ast0 bit in astcr is set to 1. bit 1 w01 bit 0 w00 description 0 0 program wait not inserted when external space area 0 is accessed 1 1 program wait state inserted when external space area 0 is accessed 1 0 2 program wait states inserted when external space area 0 is accessed 1 3 program wait states inserted when external space area 0 is accessed (initial value) 116 6.2.4 bus release control register (brcr) brcr is an 8-bit readable/writable register that enables address output on bus lines a 23 to a 20 and enables or disables release of the bus to an external device. 7 a23e 1 1 r/w 1 r/w address 23 to 20 enable these bits enable pa 7 to pa 4 to be used for a 23 to a 20 address output 6 a22e 1 ? 1 r/w 1 r/w 5 a21e 1 ? 1 r/w 1 r/w 4 a20e 1 ? 0 ? 1 r/w 3 ? 1 ? 1 ? 1 ? 2 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 0 brle 0 r/w 0 r/w 0 r/w bit modes 1, 2, 6, and 7 initial value read/write initial value read/write initial value read/write modes 3 and 4 mode 5 reserved bits bus release enable enables or disables release of the bus to an external device brcr is initialized to h'fe in modes 1, 2, 5, 6, and 7, and to h'ee in modes 3 and 4, by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 7?ddress 23 enable (a23e): enables pa 4 to be used as the a 23 address output pin. writing 0 in this bit enables a 23 output from pa 4 . in modes other than 3, 4, and 5, this bit cannot be modified and pa 4 has its ordinary port functions. bit 7 a23e description 0pa 4 is the a 23 address output pin 1pa 4 is an input/output pin (initial value) bit 6?ddress 22 enable (a22e): enables pa 5 to be used as the a 22 address output pin. writing 0 in this bit enables a 22 output from pa 5 . in modes other than 3, 4, and 5, this bit cannot be modified and pa 5 has its ordinary port functions. bit 6 a22e description 0pa 5 is the a 22 address output pin 1pa 5 is an input/output pin (initial value) 117 bit 5?ddress 21 enable (a21e): enables pa 6 to be used as the a 21 address output pin. writing 0 in this bit enables a 21 output from pa 6 . in modes other than 3, 4, and 5, this bit cannot be modified and pa 6 has its ordinary port functions. bit 5 a21e description 0pa 6 is the a 21 address output pin 1pa 6 is an input/output pin (initial value) bit 4?ddress 20 enable (a20e): enables pa 7 to be used as the a 20 address output pin. writing 0 in this bit enables a 20 output from pa 7 . this bit can only be modified in mode 5. bit 4 a20e description 0pa 7 is the a 20 address output pin (initial value when in mode 3 or 4) 1pa 7 is an input/output pin (initial value when in mode 1, 2, 5, 6 or 7) bits 3 to 1?eserved: these bits cannot be modified and are always read as 1. bit 0?us release enable (brle): enables or disables release of the bus to an external device. bit 0 brle description 0 the bus cannot be released to an external device breq back 6.2.5 bus control register (bcr) rdea waite 1 initial value 1 0 * 0 * 0 * 110 read/write ?? r/w r/w r/w r/w ?? 76543210 icis1 icis0 ?? bit note: * 1 must not be written in bits 5 to 3. bcr is an 8-bit readable/writable register that enables or disables idle cycle insertion, selects the area division unit, and enables or disables wait 118 bcr is initialized to h'c6 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 7?dle cycle insertion 1 (icis1): selects whether one idle cycle state is to be inserted between bus cycles in case of consecutive external read cycles for different areas. bit 7 icis1 description 0 no idle cycle inserted in case of consecutive external read cycles for different areas 1 idle cycle inserted in case of consecutive external read cycles for different areas (initial value) bit 6?dle cycle insertion 0 (icis0): selects whether one idle cycle state is to be inserted between bus cycles in case of consecutive external read and write cycles. bit 6 icis0 description 0 no idle cycle inserted in case of consecutive external read and write cycles 1 idle cycle inserted in case of consecutive external read and write cycles (initial value) bits 5 to 3?eserved (must not be set to 1): these bits can be read and written, but must not be set to 1. normal operation cannot be guaranteed if 1 is written in these bits. bit 2?eserved: read-only bit, always read as 1. bit 1?rea division unit select (rdea): selects the memory map area division units. this bit is valid in modes 3, 4, and 5, and is invalid in modes 1, 2, 6, and 7. bit 1 rdea description 0 area divisions are as follows: area 0: 2 mbytes area 4: 1.93 mbytes area 1: 2 mbytes area 5: 4 kbytes area 2: 8 mbytes area 6: 23.75 kbytes (19.75 kbytes) * area 3: 2 mbytes area 7: 22 bytes 1 areas 0 to 7 are the same size (2 mbytes) (initial value) note: * division in the h8/3024f-ztat and h8/3024 mask rom version. 119 bit 0?ait pin enable (waite): enables or disables wait insertion by means of the wait bit 0 waite description 0 wait pin wait input is disabled, and the wait pin can be used as an input/output port (initial value) 1 wait pin wait input is enabled 6.2.6 chip select control register (cscr) cscr is an 8-bit readable/writable register that enables or disables output of chip select signals ( cs cs cs cs cs cs 0 initial value 0001111 read/write ???? r/w r/w r/w r/w 76543210 reserved bits cs7e cs6e cs5e cs4e chip select 7 to 4 enable these bits enable or disable chip select signal output bit cscr is initialized to h'0f by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 7 to 4?hip select 7 to 4 enable (cs7e to cs4e): these bits enable or disable output of the corresponding chip select signal. bit n csne description 0 output of chip select signal csn is disabled (initial value) 1 output of chip select signal csn is enabled note: n = 7 to 4 bits 3 to 0?eserved: these bits cannot be modified and are always read as 1. 120 6.2.7 address control register (adrcr) adrcr is an 8-bit readable/writable register that selects either address update mode 1 or address update mode 2 as the address output method. adrctl 1 initial value 1111111 read/write ??? r/w ???? 76543210 reserved bits ???? address control selects address update mode 1 or address update mode 2 bit adrcr is initialized to h'ff by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 7 to 1?eserved: read-only bits, always read as 1. bit 0?ddress control (adrctl): selects the address output method. bit 0 adrctl description 0 address update mode 2 is selected 1 address update mode 1 is selected (initial value) 121 6.3 operation 6.3.1 area division the external address space is divided into areas 0 to 7. each area has a size of 128 kbytes in the 1- mbyte modes, or 2 mbytes in the 16-mbyte modes. figure 6.2 shows a general view of the memory map. h' 00000 h' 1ffff h' 20000 h' 3ffff h' 40000 h' 5ffff h' 60000 h' 7ffff h' 80000 h' 9ffff h' a0000 h' bffff h' c0000 h' dffff h' e0000 h' fffff area 0 (128 kbytes) area 1 (128 kbytes) area 2 (128 kbytes) area 3 (128 kbytes) area 4 (128 kbytes) area 5 (128 kbytes) area 6 (128 kbytes) area 7 (128 mbytes) h' 000000 h' 1fffff h' 200000 h' 3fffff h' 400000 h' 5fffff h' 600000 h' 7fffff h' 800000 h' 9fffff h' a00000 h' bfffff h' c00000 h' dfffff h' e00000 h' ffffff area 0 (2 mbytes) area 1 (2 mbytes) area 2 (2 mbytes) area 3 (2 mbytes) area 4 (2 mbytes) area 5 (2 mbytes) area 6 (2 mbytes) area 7 (2 mbytes) (a) 1-mbyte modes (modes 1 and 2) (b) 16-mbyte modes (modes 3 to 5) figure 6.2 access area map for each operating mode chip select signals ( cs cs 122 h'000000 h'1fffff h'200000 h'3fffff h'400000 h'5fffff h'600000 h'7fffff h'800000 h'9fffff h'a00000 h'bfffff h'c00000 h'dfffff h'e00000 h'fee000 h'fee0ff h'fee100 h'ff7fff h'ff8000 h'ff8fff h'ff9000 h'ffef1f h'ffef20 h'fffeff h'ffff00 h'ffff1f h'ffff20 h'ffffe9 h'ffffea h'ffffff area 0 2 mbytes area 1 2 mbytes area 2 2 mbytes area 3 2 mbytes area 4 2 mbytes area 5 2 mbytes area 6 2 mbytes area 7 1.93 mbytes internal i/o registers (1) area 7 67.5 kbytes on-chip ram 4 kbytes internal i/o registers (2) area 7 22 bytes area 0 2 mbytes area 1 2 mbytes area 2 8 mbytes area 3 2 mbytes area 4 1.93 mbytes area 5 4 kbytes on-chip ram 4 kbytes * internal i/o registers (2) area 7 22 bytes area 6 23.75 kbytes internal i/o registers (1) 2 mbytes 2 mbytes 2 mbytes 2 mbytes 2 mbytes 2 mbytes 2 mbytes 2 mbytes absolute address 16 bits absolute address 8 bits (a) memory map when rdea = 1 note: * area 6 when the rame bit is cleared. (b) memory map when rdea = 0 reserved 39.75 kbytes figure 6.3 memory map in 16-mbyte mode (h8/3024f-ztat, h8/3024 mask rom verion) (1) 123 h'000000 h'1fffff h'200000 h'3fffff h'400000 h'5fffff h'600000 h'7fffff h'800000 h'9fffff h'a00000 h'bfffff h'c00000 h'dfffff h'e00000 h'fee000 h'fee0ff h'fee100 h'ff7fff h'ff8000 h'ff8fff h'ff9000 h'ffdf1f h'ffdf20 h'fffeff h'ffff00 h'ffff1f h'ffff20 h'ffffe9 h'ffffea h'ffffff area 0 2 mbytes area 1 2 mbytes area 2 2 mbytes area 3 2 mbytes area 4 2 mbytes area 5 2 mbytes area 6 2 mbytes area 7 1.93 mbytes internal i/o registers (1) area 7 63.5 kbytes on-chip ram 8 kbytes internal i/o registers (2) area 7 22 bytes area 0 2 mbytes area 1 2 mbytes area 2 8 mbytes area 3 2 mbytes area 4 1.93 mbytes area 5 4 kbytes on-chip ram 8 kbytes * internal i/o registers (2) area 7 22 bytes area 6 19.75 kbytes internal i/o registers (1) 2 mbytes 2 mbytes 2 mbytes 2 mbytes 2 mbytes 2 mbytes 2 mbytes 2 mbytes absolute address 16 bits absolute address 8 bits (a) memory map when rdea = 1 note: * area 6 when the rame bit is cleared. (b) memory map when rdea = 0 reserved 39.75 kbytes figure 6.3 memory map in 16-mbyte mode (h8/3026f-ztat, h8/3026 mask rom verion) (2) 124 6.3.2 bus specifications the external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. the bus width and number of access states for on-chip memory and registers are fixed, and are not affected by the bus controller. bus width: a bus width of 8 or 16 bits can be selected with abwcr. an area for which an 8-bit bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected functions as a16-bit access space. if all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16- bit access, 16-bit bus mode is set. number of access states: two or three access states can be selected with astcr. an area for which two-state access is selected functions as a two-state access space, and an area for which three-state access is selected functions as a three-state access space. when two-state access space is designated, wait insertion is disabled. number of program wait states: when three-state access space is designated in astcr, the number of program wait states to be inserted automatically is selected with wcrh and wcrl. from 0 to 3 program wait states can be selected. table 6.3 shows the bus specifications for each basic bus interface area. table 6.3 bus specifications for each area (basic bus interface) abwcr astcr wcrh/wcrl bus specifications (basic bus interface) abwn astn wn1 wn0 bus width access states program wait states 00 ?? 16 2 0 10 0 3 0 11 10 2 13 10 ?? 82 0 10 0 3 0 11 10 2 13 note: n = 0 to 7 125 6.3.3 memory interfaces as its memory interface, the h8/3024 series has only a basic bus interface that allows direct connection of rom, sram, and so on. it is not possible to select a dram interface that allows direct connection of dram, or a burst rom interface that allows direct connection of burst rom. 6.3.4 chip select signals for each of areas 0 to 7, the h8/3024 series can output a chip select signal ( cs cs cs output of cs 0 to cs 3 : output of cs cs cs cs cs cs cs cs cs cs cs output of cs 4 to cs 7 : output of cs cs cs cs cs cs address bus external address in area n cs n figure 6.4 cs n signal output timing (n = 0 to 7) when the on-chip rom, on-chip ram, and internal i/o registers are accessed, cs cs cs 126 6.3.5 address output method the h8/3024 series provides a choice of two address update methods: either the same method as in the previous h8/300h series (address update mode 1), or a method in which address updating is restricted to external space accesses (address update mode 2). figure 6.5 shows examples of address output in these two update modes. on-chip memory cycle on-chip memory cycle external read cycle on-chip memory cycle external read cycle address bus (address update mode 1) address bus (address update mode 2) rd figure 6.5 sample address output in each address update mode (basic bus interface, 3-state space) address update mode 1: address update mode 1 is compatible with the previous h8/300h series. addresses are always updated between bus cycles. address update mode 2: in address update mode 2, address updating is performed only in external space accesses. in this mode, the address can be retained between an external space read cycle and an instruction fetch cycle (on-chip memory) by placing the program in on-chip memory. address update mode 2 is therefore useful when connecting a device that requires address hold time with respect to the rise of the rd 127 6.4 basic bus interface 6.4.1 overview the basic bus interface enables direct connection of rom, sram, and so on. the bus specifications can be selected with abwcr, astcr, wcrh, and wcrl (see table 6.3). 6.4.2 data size and data alignment data sizes for the cpu and other internal bus masters are byte, word, and longword. the bus controller has a data alignment function, and when accessing external space, controls whether the upper data bus (d 15 to d 8 ) or lower data bus (d 7 to d 0 ) is used according to the bus specifications for the area being accessed (8-bit access area or 16-bit access area) and the data size. 8-bit access areas: figure 6.6 illustrates data alignment control for 8-bit access space. with 8- bit access space, the upper data bus (d 15 to d 8 ) is always used for accesses. the amount of data that can be accessed at one time is one byte: a word access is performed as two byte accesses, and a longword access, as four byte accesses. d 15 d 8 d 7 d 0 upper data bus lower data bus 1st bus cycle 2nd bus cycle 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle byte size word size longword size figure 6.6 access sizes and data alignment control (8-bit access area) 16-bit access areas: figure 6.7 illustrates data alignment control for 16-bit access areas. with 16-bit access areas, the upper data bus (d 15 to d 8 ) and lower data bus (d 7 to d 0 ) are used for accesses. the amount of data that can be accessed at one time is one byte or one word, and a longword access is executed as two word accesses. 128 in byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. the upper data bus is used for an even address, and the lower data bus for an odd address. d 15 d 8 d 7 d 0 upper data bus lower data bus 1st bus cycle 2nd bus cycle byte size longword size even address odd address word size byte size figure 6.7 access sizes and data alignment control (16-bit access area) 6.4.3 valid strobes table 6.4 shows the data buses used, and the valid strobes, for the access spaces. in a read, the rd hwr lwr table 6.4 data buses used and valid strobes area access size read/ write address valid strobe upper data bus (d 15 to d 8 ) lower data bus (d 7 to d 0 ) 8-bit access byte read ? rd valid invalid area write ? hwr undetermined data 16-bit access byte read even rd valid invalid area odd invalid valid write even hwr valid undetermined data odd lwr undetermined data valid word read ? rd valid valid write ? hwr , lwr valid valid notes: 1. undetermined data means that unpredictable data is output. 2. invalid means that the bus is in the input state and the input is ignored. 129 6.4.4 memory areas the initial state of each area is basic bus interface, three-state access space. the initial bus width is selected according to the operating mode. area 0: area 0 includes on-chip rom, and in rom-disabled expansion mode, all of area 0 is external space. in rom-enabled expansion mode, the space excluding on-chip rom is external space. when area 0 external space is accessed, the cs areas 1 to 6: in external expansion mode, areas 1 to 6 are entirely external space. when area 1 to 6 external space is accessed, the cs cs area 7: area 7 includes the on-chip ram and registers. in external expansion mode, the space excluding the on-chip ram and registers is external space. the on-chip ram is enabled when the rame bit in the system control register (syscr) is set to 1; when the rame bit is cleared to 0, the on-chip ram is disabled and the corresponding space becomes external space . when area 7 external space is accessed, the cs 130 6.4.5 basic bus control signal timing 8-bit, three-state-access areas: figure 6.8 shows the timing of bus control signals for an 8-bit, three-state-access area. the upper data bus (d 15 to d 8 ) is used in accesses to these areas. the lwr bus cycle external address in area n valid invalid valid undetermined data high address bus cs n as rd d 15 to d 8 d 7 to d 0 hwr lwr d 15 to d 8 d 7 to d 0 read access write access note: n = 7 to 0 t 1 t 2 t 3 figure 6.8 bus control signal timing for 8-bit, three-state-access area 131 8-bit, two-state-access areas: figure 6.9 shows the timing of bus control signals for an 8-bit, two-state-access area. the upper data bus (d 15 to d 8 ) is used in accesses to these areas. the lwr bus cycle external address in area n valid invalid valid undetermined data high address bus cs n as rd d 15 to d 8 d 7 to d 0 hwr lwr d 15 to d 8 d 7 to d 0 read access write access note: n = 7 to 0 t 1 t 2 figure 6.9 bus control signal timing for 8-bit, two-state-access area 132 16-bit, three-state-access areas: figures 6.10 to 6.12 show the timing of bus control signals for a 16-bit, three-state-access area. in these areas, the upper data bus (d 15 to d 8 ) is used in accesses to even addresses and the lower data bus (d 7 to d 0 ) in accesses to odd addresses. wait states can be inserted. bus cycle even external address in area n valid invalid valid high address bus cs n as rd d 15 to d 8 d 7 to d 0 hwr lwr d 15 to d 8 d 7 to d 0 read access write access note: n = 7 to 0 t 1 t 2 t 3 undetermined data figure 6.10 bus control signal timing for 16-bit, three-state-access area (1) (byte access to even address) 133 bus cycle odd external address in area n valid invalid valid address bus cs n as rd d 15 to d 8 d 7 to d 0 hwr lwr d 15 to d 8 d 7 to d 0 read access write access note: n = 7 to 0 t 1 t 2 t 3 high undetermined data figure 6.11 bus control signal timing for 16-bit, three-state-access area (2) (byte access to odd address) 134 bus cycle external address in area n valid valid address bus cs n as rd d 15 to d 8 d 7 to d 0 hwr lwr d 15 to d 8 d 7 to d 0 read access write access note: n = 7 to 0 t 1 t 2 t 3 valid valid figure 6.12 bus control signal timing for 16-bit, three-state-access area (3) (word access) 135 16-bit, two-state-access areas: figures 6.13 to 6.15 show the timing of bus control signals for a 16-bit, two-state-access area. in these areas, the upper data bus (d 15 to d 8 ) is used in accesses to even addresses and the lower data bus (d 7 to d 0 ) in accesses to odd addresses. wait states cannot be inserted. bus cycle even external address in area n valid invalid valid high address bus cs n as rd d 15 to d 8 d 7 to d 0 hwr lwr d 15 to d 8 d 7 to d 0 read access write access note: n = 7 to 0 t 1 t 2 undetermined data figure 6.13 bus control signal timing for 16-bit, two-state-access area (1) (byte access to even address) 136 bus cycle odd external address in area n valid invalid valid high address bus cs n as rd d 15 to d 8 d 7 to d 0 hwr lwr d 15 to d 8 d 7 to d 0 read access write access note: n = 7 to 0 t 1 t 2 undetermined data figure 6.14 bus control signal timing for 16-bit, two-state-access area (2) (byte access to odd address) 137 bus cycle external address in area n valid valid address bus cs n as rd d 15 to d 8 d 7 to d 0 hwr lwr d 15 to d 8 d 7 to d 0 read access write access note: n = 7 to 0 t 1 t 2 valid valid figure 6.15 bus control signal timing for 16-bit, two-state-access area (3) (word access) 6.4.6 wait control when accessing external space, the h8/3024 series can extend the bus cycle by inserting wait states (t w ). there are two ways of inserting wait states: program wait insertion and pin wait insertion using the wait program wait insertion: from 0 to 3 wait states can be inserted automatically between the t 2 state and t 3 state on an individual area basis in three-state access space, according to the settings of wcrh and wcrl. 138 pin wait insertion: setting the waite bit in bcr to 1 enables wait insertion by means of the wait wait wait wait address bus data bus read access write access data bus as rd t 1 t 2 t w t w t w t 3 hwr , lwr note: indicates the timing of wait pin sampling. inserted by program wait inserted by wait pin read data write data figure 6.16 example of wait state insertion timing 139 6.5 idle cycle 6.5.1 operation when the h8/3024 series chip accesses external space, it can insert a 1-state idle cycle (t i ) between bus cycles in the following cases: when read accesses between different areas occur consecutively, and when a write cycle occurs immediately after a read cycle. by inserting an idle cycle it is possible, for example, to avoid data collisions between rom, which has a long output floating time, and high-speed memory, i/o interfaces, and so on. the initial value of the icis1 and icis0 bits in bcr is 1, so that idle cycle insertion is performed in the initial state. if there are no data collisions, the icis bits can be cleared. consecutive reads between different areas: if consecutive reads between different areas occur while the icis1 bit is set to 1 in bcr, an idle cycle is inserted at the start of the second read cycle. figure 6.17 shows an example of the operation in this case. in this example, bus cycle a is a read cycle from rom with a long output floating time, and bus cycle b is a read cycle from sram, each being located in a different area. in (a), an idle cycle is not inserted, and a collision occurs in bus cycle b between the read data from rom and that from sram. in (b), an idle cycle is inserted, and a data collision is prevented. t 1 t 2 t 3 rd t 1 t 2 t 1 t 2 t 3 t i t 2 t 1 address bus data bus rd address bus data bus bus cycle a bus cycle b bus cycle a bus cycle b data collision long buffer-off time (a) idle cycle not inserted (b) idle cycle inserted figure 6.17 example of idle cycle operation (icis1 = 1) write after read: if an external write occurs after an external read while the icis0 bit is set to 1 in bcr, an idle cycle is inserted at the start of the write cycle. figure 6.18 shows an example of the operation in this case. in this example, bus cycle a is a read cycle from rom with a long output floating time, and bus cycle b is a cpu write cycle. in (a), an idle cycle is not inserted, and a collision occurs in bus cycle b between the read data from rom and the cpu write data. in (b), an idle cycle is inserted, and a data collision is prevented. 140 t 1 t 2 t 3 rd address bus data bus t 1 t 2 t 1 t 2 t 3 t i t 2 t 1 hwr rd address bus data bus hwr bus cycle a bus cycle b bus cycle a bus cycle b long buffer-off time data collision (a) idle cycle not inserted (b) idle cycle inserted figure 6.18 example of idle cycle operation (icis0 = 1) usage note: when non-insertion of an idle cycle is specified, the rise (negation) of rd cs rd cs rd cs rd cs t 1 t 2 t 3 rd address bus t 1 t 2 t 1 t 2 t 3 t i t 2 t 1 cs n rd address bus cs n bus cycle a bus cycle b bus cycle a bus cycle b simultaneous change of rd and cs n: possibility of mutual overlap (a) idle cycle not inserted (b) idle cycle inserted figure 6.19 example of idle cycle operation 141 6.5.2 pin states in idle cycle table 6.5 shows the pin states in an idle cycle. table 6.5 pin states in idle cycle pins pin state a 23 to a 0 next cycle address value d 15 to d 0 high impedance cs n high as high rd high hwr high lwr high 6.6 bus arbiter the bus controller has a built-in bus arbiter that arbitrates between different bus masters. the bus master can be either the cpu or an external bus master. when a bus master has the bus right it can carry out read and write operations. each bus master uses a bus request signal to request the bus right. at fixed times the bus arbiter determines priority and uses a bus acknowledge signal to grant the bus to a bus master, which can the operate using the bus. the bus arbiter checks whether the bus request signal from a bus master is active or inactive, and returns an acknowledge signal to the bus master. when two or more bus masters request the bus, the highest-priority bus master receives an acknowledge signal. the bus master that receives an acknowledge signal can continue to use the bus until the acknowledge signal is deactivated. the bus master priority order is: (high) external bus master > cpu (low) the bus arbiter samples the bus request signals and determines priority at all times, but it does not always grant the bus immediately, even when it receives a bus request from a bus master with higher priority than the current bus master. each bus master has certain times at which it can release the bus to a higher-priority bus master. 142 6.6.1 operation cpu: the cpu is the lowest-priority bus master. if an external bus master requests the bus while the cpu has the bus right, the bus arbiter transfers the bus right to the bus master that requested it. the bus right is transferred at the following times: ? ? ? external bus master: when the brle bit is set to 1 in brcr, the bus can be released to an external bus master. the external bus master has highest priority, and requests the bus right from the bus arbiter driving the breq breq as rd hwr lwr cs back breq breq breq back breq back breq 143 rd back (1) (2) (3) (4) (5) (6) breq hwr , lwr t 0 t 1 t 2 as data bus address bus cpu cycles cpu cycles external bus released high address minimum 3 cycles high-impedance high-impedance high-impedance high-impedance high-impedance figure 6.20 example of external bus master operation when making a transition to software standby mode, if there is contention with a bus request from an external bus master, the back 144 6.7 register and pin input timing 6.7.1 register write timing abwcr, astcr, wcrh, and wcrl write timing: data written to abwcr, astcr, wcrh, and wcrl takes effect starting from the next bus cycle. figure 6.21 shows the timing when an instruction fetched from area 0 changes area 0 from three-state access to two-state access. t 1 t 2 t 3 t 1 t 2 t 3 t 1 t 2 address bus 3-state access to area 0 2-state access to area 0 astcr address figure 6.21 astcr write timing ddr and cscr write timing: data written to ddr or cscr for the port corresponding to the cs cs cs cs t 1 t 2 t 3 cs 1 address bus high-impedance p8ddr address figure 6.22 ddr write timing brcr write timing: data written to brcr to switch between a 23 , a 22 , a 21 , or a 20 output and generic input or output takes effect starting from the t 3 state of the brcr write cycle. figure 6.23 shows the timing when a pin is changed from generic input to a 23 , a 22 , a 21 , or a 20 output. 145 t 1 t 2 t 3 pa 7 to pa 4 ( a 23 to a 20 ) address bus brcr address high-impedance figure 6.23 brcr write timing 6.7.2 breq pin input timing after driving the breq back breq back breq breq 146 147 section 7 i/o ports 7.1 overview the h8/3024 series has 10 input/output ports (ports 1, 2, 3, 4, 5, 6, 8, 9, a, and b) and one input- only port (port 7). table 7.1 summarizes the port functions. the pins in each port are multiplexed as shown in table 7.1. each port has a data direction register (ddr) for selecting input or output, and a data register (dr) for storing output data. in addition to these registers, ports 2, 4, and 5 have an input pull-up control register (pcr) for switching input pull-up transistors on and off. ports 1 to 6 and port 8 can drive one ttl load and a 90-pf capacitive load. ports 9, a, and b can drive one ttl load and a 30-pf capacitive load. ports 1 to 6 and 8 to b can drive a darlington pair. ports 1, 2, and 5 can drive leds (with 10-ma current sink). pins p8 2 to p8 0 , pa 7 to pa 0 have schmitt-trigger input circuits. for block diagrams of the ports see appendix c, i/o port block diagrams. table 7.1 port functions expanded modes single-chip modes port description pins mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 port 1 ? ? ? ? ? ? 148 expanded modes single-chip modes port description pins mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 port 4 ? ? ? ? ? ? lwr hwr rd as lwr hwr rd as back breq wait back breq wait ? ? ? cs cs cs irq cs adtrg irq cs adtrg cs irq adtrg 149 expanded modes single-chip modes port description pins mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 port 8 ? ? irq cs irq cs irq irq cs cs cs cs irq irq irq irq ? irq irq irq irq ? ? 150 expanded modes single-chip modes port description pins mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 port b ? cs cs cs cs cs cs 151 7.2 port 1 7.2.1 overview port 1 is an 8-bit input/output port also used for address output, with the pin configuration shown in figure 7.1. the pin functions differ according to the operating mode. in modes 1 to 4 (expanded modes with on-chip rom disabled), they are address bus output pins (a 7 to a 0 ). in mode 5 (expanded modes with on-chip rom enabled), settings in the port 1 data direction register (p1ddr) can designate pins for address bus output (a 7 to a 0 ) or generic input. in modes 6 and 7 (single-chip mode), port 1 is a generic input/output port. pins in port 1 can drive one ttl load and a 90-pf capacitive load. they can also drive an led or a darlington transistor pair. port 1 p1 /a p1 /a p1 /a p1 /a p1 /a p1 /a p1 /a p1 /a 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 p1 (input/output) p1 (input/output) p1 (input/output) p1 (input/output) p1 (input/output) p1 (input/output) p1 (input/output) p1 (input/output) 7 6 5 4 3 2 1 0 a (output) a (output) a (output) a (output) a (output) a (output) a (output) a (output) 7 6 5 4 3 2 1 0 port 1 pins modes 6 and 7 modes 1 to 4 p1 (input)/a (output) p1 (input)/a (output) p1 (input)/a (output) p1 (input)/a (output) p1 (input)/a (output) p1 (input)/a (output) p1 (input)/a (output) p1 (input)/a (output) 7 6 5 4 3 2 1 0 mode 5 7 6 5 4 3 2 1 0 figure 7.1 port 1 pin configuration 7.2.2 register descriptions table 7.2 summarizes the registers of port 1. table 7.2 port 1 registers initial value address* name abbreviation r/w modes 1 to 4 modes 5 to 7 h'ee000 port 1 data direction register p1ddr w h'ff h'00 h'fffd0 port 1 data register p1dr r/w h'00 h'00 note: * lower 20 bits of the address in advanced mode. 152 port 1 data direction register (p1ddr): p1ddr is an 8-bit write-only register that can select input or output for each pin in port 1. bit modes 1 to 4 initial value read/write initial value read/write modes 5 to 7 7 p1 ddr 1 0 w 7 6 p1 ddr 1 0 w 6 5 p1 ddr 1 0 w 5 4 p1 ddr 1 0 w 4 3 p1 ddr 1 0 w 3 2 p1 ddr 1 0 w 2 1 p1 ddr 1 0 w 1 0 p1 ddr 1 0 w 0 port 1 data direction 7 to 0 these bits select input or output for port 1 pins ? modes 1 to 4 (expanded modes with on-chip rom disabled) p1ddr values are fixed at 1. port 1 functions as an address bus. ? mode 5 (expanded modes with on-chip rom enabled) after a reset, port 1 functions as an input port. a pin in port 1 becomes an address output pin if the corresponding p1ddr bit is set to 1, and a generic input pin if this bit is cleared to 0. ? modes 6 and 7 (single-chip mode) port 1 functions as an input/output port. a pin in port 1 becomes an output port if the corresponding p1ddr bit is set to 1, and an input port if this bit is cleared to 0. in modes 1 to 4, p1ddr bits are always read as 1, and cannot be modified. in modes 5 to 7, p1ddr is a write-only register. its value cannot be read. all bits return 1 when read. p1ddr is initialized to h'ff in modes 1 to 4, and to h'00 in modes 5 to 7, by a reset and in hardware standby mode. in sofware standby mode it retains its previous setting. therefore, if a transition is made to software standby mode while port 1 is functioning as an input/output port and a p1ddr bit is set to 1, the corresponding pin maintains its output state. 153 port 1 data register (p1dr): p1dr is an 8-bit readable/writable register that stores port 1 output data. when port 1 functions as an output port, the value of this register is output. when this register is read, the pin logic level is read for bits for which the p1ddr setting is 0, and the p1dr value is read for bits for which the p1ddr setting is 1. bit initial value read/write 7 p1 0 r/w port 1 data 7 to 0 these bits store data for port 1 pins 7 6 p1 0 r/w 6 5 p1 0 r/w 5 4 p1 0 r/w 4 3 p1 0 r/w 3 2 p1 0 r/w 2 1 p1 0 r/w 1 0 p1 0 r/w 0 p1dr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. 154 7.3 port 2 7.3.1 overview port 2 is an 8-bit input/output port which also has an address output function. it? pin configuration is shown in figure 7.2. the pin functions differ according to the operating mode. in modes 1 to 4 (expanded modes with on-chip rom disabled), port 2 consists of address bus output pins (a 15 to a 8 ). in mode 5 (expanded modes with on-chip rom enabled), settings in the port 2 data direction register (p2ddr) can designate pins for address bus output (a 15 to a 8 ) or generic input. in modes 6 and 7 (single-chip mode), port 2 is a generic input/output port. port 2 has software-programmable built-in pull-up transistors. pins in port 2 can drive one ttl load and a 90-pf capacitive load. they can also drive an led or a darlington transistor pair. port 2 p2 /a p2 /a p2 /a p2 /a p2 /a p2 /a p2 /a p2 /a 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 p2 (input/output) p2 (input/output) p2 (input/output) p2 (input/output) p2 (input/output) p2 (input/output) p2 (input/output) p2 (input/output) 7 6 5 4 3 2 1 0 a (output) a (output) a (output) a (output) a (output) a (output) a (output) a (output) 15 14 13 12 11 10 9 8 port 2 pins modes 6 and 7 modes 1 to 4 p2 (input)/a (output) p2 (input)/a (output) p2 (input)/a (output) p2 (input)/a (output) p2 (input)/a (output) p2 (input)/a (output) p2 (input)/a (output) p2 (input)/a (output) 7 6 5 4 3 2 1 0 mode 5 15 14 13 12 11 10 9 8 figure 7.2 port 2 pin configuration 155 7.3.2 register descriptions table 7.3 summarizes the registers of port 2. table 7.3 port 2 registers initial value address* name abbreviation r/w modes 1 to 4 modes 5 to 7 h'ee001 port 2 data direction register p2ddr w h'ff h'00 h'fffd1 port 2 data register p2dr r/w h'00 h'00 h'ee03c port 2 input pull-up mos control register p2pcr r/w h'00 h'00 note: * lower 20 bits of the address in advanced mode. port 2 data direction register (p2ddr): p2ddr is an 8-bit write-only register that can select input or output for each pin in port 2. bit modes 1 to 4 initial value read/write initial value read/write modes 5 to 7 7 p2 ddr 1 ? 0 w 7 6 p2 ddr 1 ? 0 w 6 5 p2 ddr 1 ? 0 w 5 4 p2 ddr 1 ? 0 w 4 3 p2 ddr 1 ? 0 w 3 2 p2 ddr 1 ? 0 w 2 1 p2 ddr 1 ? 0 w 1 0 p2 ddr 1 ? 0 w 0 port 2 data direction 7 to 0 these bits select input or output for port 2 pins ? modes 1 to 4 (expanded modes with on-chip rom disabled) p2ddr values are fixed at 1. port 2 functions as an address bus. ? mode 5 (expanded modes with on-chip rom enabled) following a reset, port 2 is an input port. a pin in port 2 becomes an address output pin if the corresponding p2ddr bit is set to 1, and a generic input port if this bit is cleared to 0. ? modes 6 and 7 (single-chip mode) port 2 functions as an input/output port. a pin in port 2 becomes an output port if the corresponding p2ddr bit is set to 1, and an input port if this bit is cleared to 0. in modes 1 to 4, p2ddr bits are always read as 1, and cannot be modified. 156 in modes 5 to 7, p2ddr is a write-only register. its value cannot be read. all bits return 1 when read. p2ddr is initialized to h'ff in modes 1 to 4, and to h'00 in modes 5 to 7, by a reset and in hardware standby mode. in software standby mode it retains its previous setting. therefore, if a transition is made to software standby mode while port 2 is functioning as an input/output port and a p2ddr bit is set to 1, the corresponding pin maintains its output state. port 2 data register (p2dr): p2dr is an 8-bit readable/writable register that stores output data for port 2. when port 2 functions as an output port, the value of this register is output. when a bit in p2ddr is set to 1, if port 2 is read the value of the corresponding p2dr bit is returned. when a bit in p2ddr is cleared to 0, if port 2 is read the corresponding pin logic level is read. bit initial value read/write 7 p2 0 r/w port 2 data 7 to 0 these bits store data for port 2 pins 7 6 p2 0 r/w 6 5 p2 0 r/w 5 4 p2 0 r/w 4 3 p2 0 r/w 3 2 p2 0 r/w 2 1 p2 0 r/w 1 0 p2 0 r/w 0 p2dr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. port 2 input pull-up mos control register (p2pcr): p2pcr is an 8-bit readable/writable register that controls the mos input pull-up transistors in port 2. bit initial value read/write 7 p2 pcr 0 r/w port 2 input pull-up mos control 7 to 0 these bits control input pull-up transistors built into port 2 7 6 p2 pcr 0 r/w 6 5 p2 pcr 0 r/w 5 4 p2 pcr 0 r/w 4 3 p2 pcr 0 r/w 3 2 p2 pcr 0 r/w 2 1 p2 pcr 0 r/w 1 0 p2 pcr 0 r/w 0 in modes 5 to 7, when a p2ddr bit is cleared to 0 (selecting generic input), if the corresponding bit in p2pcr is set to 1, the input pull-up transistor is turned on. p2pcr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. 157 table 7.4 summarizes the states of the input pull-ups in each mode. table 7.4 input pull-up transistor states (port 2) mode reset hardware standby mode software standby mode other modes 1 2 3 4 off off off off 5 6 7 off off on/off on/off legend off: the input pull-up transistor is always off. on/off: the input pull-up transistor is on if p2pcr = 1 and p2ddr = 0. otherwise, it is off. 158 7.4 port 3 7.4.1 overview port 3 is an 8-bit input/output port which also functions as a data bus. it? pin configuration is shown in figure 7.3. port 3 is a data bus in modes 1 to 5 (expanded modes) and a generic input/output port in modes 6 and 7 (single-chip mode). pins in port 3 can drive one ttl load and a 90-pf capacitive load. they can also drive a darlington transistor pair. port 3 p3 /d p3 /d p3 /d p3 /d p3 /d p3 /d p3 /d p3 /d 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 p3 (input/output) p3 (input/output) p3 (input/output) p3 (input/output) p3 (input/output) p3 (input/output) p3 (input/output) p3 (input/output) 7 6 5 4 3 2 1 0 d (input/output) d (input/output) d (input/output) d (input/output) d (input/output) d (input/output) d (input/output) d (input/output) 15 14 13 12 11 10 9 8 port 3 pins modes 6 and 7 modes 1 to 5 figure 7.3 port 3 pin configuration 7.4.2 register descriptions table 7.5 summarizes the registers of port 3. table 7.5 port 3 registers address* name abbreviation r/w initial value h'ee002 port 3 data direction register p3ddr w h'00 h'fffd2 port 3 data register p3dr r/w h'00 note: * lower 20 bits of the address in advanced mode. 159 port 3 data direction register (p3ddr): p3ddr is an 8-bit write-only register that can select input or output for each pin in port 3. bit initial value read/write 7 p3 ddr 0 w port 3 data direction 7 to 0 these bits select input or output for port 3 pins 7 6 p3 ddr 0 w 6 5 p3 ddr 0 w 5 4 p3 ddr 0 w 4 3 p3 ddr 0 w 3 2 p3 ddr 0 w 2 1 p3 ddr 0 w 1 0 p3 ddr 0 w 0 ? modes 1 to 5 (expanded modes) port 3 functions as a data bus, regardless of the p3ddr settings. ? modes 6 and 7 (single-chip mode) port 3 functions as an input/output port. a pin in port 3 becomes an output port if the corresponding p3ddr bit is set to 1, and an input port if this bit is cleared to 0. p3ddr is a write-only register. its value cannot be read. all bits return 1 when read. p3ddr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. therefore, if a transition is made to software standby mode while port 3 is functioning as an input/output port and a p3ddr bit is set to 1, the corresponding pin maintains its output state. port 3 data register (p3dr): p3dr is an 8-bit readable/writable register that stores output data for port 3. when port 3 functions as an output port, the value of this register is output. when a bit in p3ddr is set to 1, if port 3 is read the value of the corresponding p3dr bit is returned. when a bit in p3ddr is cleared to 0, if port 3 is read the corresponding pin logic level is read. bit initial value read/write 7 p3 0 r/w port 3 data 7 to 0 these bits store data for port 3 pins 7 6 p3 0 r/w 6 5 p3 0 r/w 5 4 p3 0 r/w 4 3 p3 0 r/w 3 2 p3 0 r/w 2 1 p3 0 r/w 1 0 p3 0 r/w 0 p3dr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. 160 7.5 port 4 7.5.1 overview port 4 is an 8-bit input/output port which also functions as a data bus. it? pin configuration is shown in figure 7.4. the pin functions differ depending on the operating mode. in modes 1 to 5 (expanded modes), when the bus width control register (abwcr) designates areas 0 to 7 all as 8-bit-access areas, the chip operates in 8-bit bus mode and port 4 is a generic input/output port. when at least one of areas 0 to 7 is designated as a 16-bit-access area, the chip operates in 16-bit bus mode and port 4 becomes part of the data bus. in modes 6 and 7 (single-chip mode), port 4 is a generic input/output port. port 4 has software-programmable built-in pull-up transistors. pins in port 4 can drive one ttl load and a 90-pf capacitive load. they can also drive a darlington transistor pair. port 4 p4 /d p4 /d p4 /d p4 /d p4 /d p4 /d p4 /d p4 /d 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 p4 (input/output)/d 7 (input/output) p4 (input/output)/d 6 (input/output) p4 (input/output)/d 5 (input/output) p4 (input/output)/d 4 (input/output) p4 (input/output)/d 3 (input/output) p4 (input/output)/d 2 (input/output) p4 (input/output)/d 1 (input/output) p4 (input/output)/d 0 (input/output) 7 6 5 4 3 2 1 0 port 4 pins modes 1 to 5 p4 (input/output) p4 (input/output) p4 (input/output) p4 (input/output) p4 (input/output) p4 (input/output) p4 (input/output) p4 (input/output) 7 6 5 4 3 2 1 0 modes 6 and 7 figure 7.4 port 4 pin configuration 161 7.5.2 register descriptions table 7.6 summarizes the registers of port 4. table 7.6 port 4 registers address* name abbreviation r/w initial value h'ee003 port 4 data direction register p4ddr w h'00 h'fffd3 port 4 data register p4dr r/w h'00 h'ee03e port 4 input pull-up mos control register p4pcr r/w h'00 note: * lower 20 bits of the address in advanced mode. port 4 data direction register (p4ddr): p4ddr is an 8-bit write-only register that can select input or output for each pin in port 4. bit initial value read/write 7 p4 ddr 0 w port 4 data direction 7 to 0 these bits select input or output for port 4 pins 7 6 p4 ddr 0 w 6 5 p4 ddr 0 w 5 4 p4 ddr 0 w 4 3 p4 ddr 0 w 3 2 p4 ddr 0 w 2 1 p4 ddr 0 w 1 0 p4 ddr 0 w 0 ? modes 1 to 5 (expanded modes) when all areas are designated as 8-bit-access areas by the bus controller? bus width control register (abwcr), selecting 8-bit bus mode, port 4 functions as an input/output port. in this case, a pin in port 4 becomes an output port if the corresponding p4ddr bit is set to 1, and an input port if this bit is cleared to 0. when at least one area is designated as a 16-bit-access area, selecting 16-bit bus mode, port 4 functions as part of the data bus, regardless of the p4ddr settings. ? modes 6 and 7 (single-chip mode) port 4 functions as an input/output port. a pin in port 4 becomes an output port if the corresponding p4ddr bit is set to 1, and an input port if this bit is cleared to 0. p4ddr is a write-only register. its value cannot be read. all bits return 1 when read. p4ddr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. 162 abwcr and p4ddr are not initialized in software standby mode. therefore, if a transition is made to software standby mode while port 4 is functioning as an input/output port and a p4ddr bit is set to 1, the corresponding pin maintains its output state. port 4 data register (p4dr): p4dr is an 8-bit readable/writable register that stores output data for port 4. when port 4 functions as an output port, the value of this register is output. when a bit in p4ddr is set to 1, if port 4 is read the value of the corresponding p4dr bit is returned. when a bit in p4ddr is cleared to 0, if port 4 is read the corresponding pin logic level is read. bit initial value read/write 7 p4 0 r/w port 4 data 7 to 0 these bits store data for port 4 pins 7 6 p4 0 r/w 6 5 p4 0 r/w 5 4 p4 0 r/w 4 3 p4 0 r/w 3 2 p4 0 r/w 2 1 p4 0 r/w 1 0 p4 0 r/w 0 p4dr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. port 4 input pull-up mos control register (p4pcr): p4pcr is an 8-bit readable/writable register that controls the mos input pull-up transistors in port 4. bit initial value read/write 7 p4 pcr 0 r/w port 4 input pull-up mos control 7 to 0 these bits control input pull-up transistors built into port 4 7 6 p4 pcr 0 r/w 6 5 p4 pcr 0 r/w 5 4 p4 pcr 0 r/w 4 3 p4 pcr 0 r/w 3 2 p4 pcr 0 r/w 2 1 p4 pcr 0 r/w 1 0 p4 pcr 0 r/w 0 in modes 6 and 7 (single-chip mode), and in 8-bit bus mode in modes 1 to 5 (expanded modes), when a p4ddr bit is cleared to 0 (selecting generic input), if the corresponding p4pcr bit is set to 1, the input pull-up transistor is turned on. p4pcr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. table 7.7 summarizes the states of the input pull-up mos in each operating mode. 163 table 7.7 input pull-up transistor states (port 4) mode reset hardware standby mode software standby mode other modes 1 to 5 8-bit bus mode off off on/off on/off 16-bit bus mode off off 6 and 7 on/off on/off legend off: the input pull-up transistor is always off. on/off: the input pull-up transistor is on if p4pcr = 1 and p4ddr = 0. otherwise, it is off. 7.6 port 5 7.6.1 overview port 5 is a 4-bit input/output port which also has an address output function. it? pin configuration is shown in figure 7.5. the pin functions differ depending on the operating mode. in modes 1 to 4 (expanded modes with on-chip rom disabled), port 5 consists of address output pins (a 19 to a 16 ). in mode 5 (expanded modes with on-chip rom enabled), settings in the port 5 data direction register (p5ddr) designate pins for address bus output (a 19 to a 16 ) or generic input. in modes 6 and 7 (single-chip mode), port 5 is a generic input/output port. port 5 has software-programmable built-in pull-up transistors. pins in port 5 can drive one ttl load and a 90-pf capacitive load. they can also drive an led or a darlington transistor pair. port 5 p5 /a p5 /a p5 /a p5 /a 3 2 1 0 19 18 17 16 a (output) a (output) a (output) a (output) 19 18 17 16 p5 (input)/a (output) p5 (input)/a (output) p5 (input)/a (output) p5 (input)/a (output) 3 2 1 0 port 5 pins modes 1 to 4 mode 5 p5 (input/output) p5 (input/output) p5 (input/output) p5 (input/output) 3 2 1 0 modes 6 and 7 19 18 17 16 figure 7.5 port 5 pin configuration 164 7.6.2 register descriptions table 7.8 summarizes the registers of port 5. table 7.8 port 5 registers initial value address* name abbreviation r/w modes 1 to 4 modes 5 to 7 h'ee004 port 5 data direction register p5ddr w h'ff h'f0 h'fffd4 port 5 data register p5dr r/w h'f0 h'f0 h'ee03f port 5 input pull-up mos control register p5pcr r/w h'f0 h'f0 note: * lower 20 bits of the address in advanced mode. port 5 data direction register (p5ddr): p5ddr is an 8-bit write-only register that can select input or output for each pin in port 5. bits 7 to 4 are reserved. they are fixed at 1, and cannot be modified. bit modes 1 to 4 initial value read/write initial value read/write modes 5 to 7 7 ? 1 ? 1 ? 6 ? 1 ? 1 ? 5 ? 1 ? 1 ? 4 ? 1 ? 1 ? 3 p5 ddr 1 ? 0 w 3 2 p5 ddr 1 ? 0 w 2 1 p5 ddr 1 ? 0 w 1 0 p5 ddr 1 ? 0 w 0 reserved bits port 5 data direction 3 to 0 these bits select input or output for port 5 pins ? modes 1 to 4 (expanded modes with on-chip rom disabled) p5ddr values are fixed at 1. port 5 functions as an address bus output. ? mode 5 (expanded modes with on-chip rom enabled) following a reset, port 5 is an input port. a pin in port 5 becomes an address output pin if the corresponding p5ddr bit is set to 1, and an input port if this bit is cleared to 0. ? modes 6 and 7 (single-chip mode) port 5 functions as an input/output port. a pin in port 5 becomes an output port if the corresponding p5ddr bit is set to 1, and an input port if this bit is cleared to 0. in modes 1 to 4, p5ddr bits are always read as 1, and cannot be modified. 165 in modes 5 to 7, p5ddr is a write-only register. its value cannot be read. all bits return 1 when read. p5ddr is initialized to h'ff in modes 1 to 4, and to h'f0 in modes 5 to 7, by a reset and in hardware standby mode. in software standby mode it retains its previous setting. therefore, if a transition is made to software standby mode while port 5 is functioning as an input/output port and a p5ddr bit is set to 1, the corresponding pin maintains its output state. port 5 data register (p5dr): p5dr is an 8-bit readable/writable register that stores output data for port 5. when port 5 functions as an output port, the value of this register is output. when a bit in p5ddr is set to 1, if port 5 is read the value of the corresponding p5dr bit is returned. when a bit in p5ddr is cleared to 0, if port 5 is read the corresponding pin logic level is read. bits 7 to 4 are reserved. they are fixed at 1, and cannot be modified. bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 p5 0 r/w 3 2 p5 0 r/w 2 1 p5 0 r/w 1 0 p5 0 r/w 0 reserved bits these bits store data for port 5 pins port 5 data 3 to 0 p5dr is initialized to h'f0 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. port 5 input pull-up mos control register (p5pcr): p5pcr is an 8-bit readable/writable register that controls the mos input pull-up transistors in port 5. bits 7 to 4 are reserved. they are fixed at 1, and cannot be modified. bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 p5 pcr 0 r/w 3 2 p5 pcr 0 r/w 2 1 p5 pcr 0 r/w 1 0 p5 pcr 0 r/w 0 reserved bits these bits control input pull-up transistors built into port 5 port 5 input pull-up mos control 3 to 0 in modes 5 to 7, when a p5ddr bit is cleared to 0 (selecting generic input), if the corresponding bit in p5pcr is set to 1, the input pull-up transistor is turned on. 166 p5pcr is initialized to h'f0 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. table 7.9 summarizes the states of the input pull-ups in each mode. table 7.9 input pull-up transistor states (port 5) mode reset hardware standby mode software standby mode other modes 1 2 3 4 off off off off 5 6 7 off off on/off on/off legend off: the input pull-up transistor is always off. on/off: the input pull-up transistor is on if p5pcr = 1 and p5ddr = 0. otherwise, it is off. 7.7 port 6 7.7.1 overview port 6 is an 8-bit input/output port that is also used for input and output of bus control signals ( lwr , hwr , rd , as , back , breq , wait ) and for clock ( ) output. the port 6 pin configuration is shown in figure 7.6. see table 7.11 for the selection of the pin functions. pins in port 6 can drive one ttl load and a 90-pf capacitive load. they can also drive a darlington transistor pair. 167 port 6 p6 / p6 / p6 / p6 / p6 / p6 / p6 / p6 / 7 6 5 4 3 2 1 0 lwr hwr rd as back breq wait port 6 pins lwr hwr rd as back breq wait modes 1 to 5 (expanded modes) (output) (output) (output) (output) (output) (output) (input) (input) p6 p6 p6 p6 p6 p6 p6 p6 7 6 5 4 3 2 1 0 modes 6 and 7 (single-chip mode) (input) / (output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) p6 7 (input)/ p6 2 (input/output) p6 1 (input/output)/ p6 0 (input/output)/ figure 7.6 port 6 pin configuration 7.7.2 register descriptions table 7.10 summarizes the registers of port 6. table 7.10 port 6 registers address* name abbreviation r/w initial value h'ee005 port 6 data direction register p6ddr w h'80 h'fffd5 port 6 data register p6dr r/w h'80 note: * lower 20 bits of the address in advanced mode. port 6 data direction register (p6ddr): p6ddr is an 8-bit write-only register that can select input or output for each pin in port 6. bit 7 is reserved. it is fixed at 1, and cannot be modified. bit initial value read/write 7 ? 1 ? 6 p6 ddr 0 w 6 5 p6 ddr 0 w 5 4 p6 ddr 0 w 4 3 p6 ddr 0 w 3 2 p6 ddr 0 w 2 1 p6 ddr 0 w 1 0 p6 ddr 0 w 0 port 6 data direction 6 to 0 these bits select input or output for port 6 pins reserved bit 168 ? modes 1 to 5 (expanded modes) p6 7 functions as the clock output pin ( ) or an input port. p6 7 is the clock output pin (? if the pstop bit in mstrch is cleared to 0 (initial value), and an input port if this bit is set to 1. p6 6 to p6 3 function as bus control output pins ( lwr , hwr , rd , and as ), regardless of the settings of bits p6 6 ddr to p6 3 ddr. p6 2 to p6 0 function as bus control input/output pins ( back , breq , and wait ) or input/output ports. for the method of selecting the pin functions, see table 7.11. when p6 2 to p6 0 function as input/output ports, the pin becomes an output port if the corresponding p6ddr bit is set to 1, and an input port if this bit is cleared to 0. ? modes 6 and 7 (single-chip mode) p6 7 functions as the clock output pin ( ) or an input port. p6 6 to p6 0 function as generic input/output ports. p6 7 is the clock output pin ( ) if the pstop bit in mstcrh is cleared to 0 (initial value), and an input port if this bit is set to 1. a pin in port 6 becomes an output port if the corresponding bit of p6 6 ddr to p6 0 ddr is set to 1, and an input port if this pin is cleared to 0. p6ddr is a write-only register. its value cannot be read. all bits return 1 when read. p6ddr is initialized to h'80 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. therefore, if a transition is made to software standby mode while port 6 is functioning as an input/output port and a p6ddr bit is set to 1, the corresponding pin maintains its output state. port 6 data register (p6dr): p6dr is an 8-bit readable/writable register that stores output data for port 6. when port 6 functions as an output port, the value of this register is output. for bit 7, a value of 1 is returned if the bit is read while the pstop bit in mstcrh is cleared to 0, and the p6 7 pin logic level is returned if the bit is read while the pstop bit is set to 1. bit 7 cannot be modified. for bits 6 to 0, the pin logic level is returned if the bit is read while the corresponding bit in p6ddr is cleared to 0, and the p6dr value is returned if the bit is read while the corresponding bit in p6ddr is set to 1. bit initial value read/write 7 p6 7 1 r 6 p6 0 r/w 6 5 p6 0 r/w 5 4 p6 0 r/w 4 3 p6 0 r/w 3 2 p6 0 r/w 2 1 p6 0 r/w 1 0 p6 0 r/w 0 port 6 data 7 to 0 these bits store data for port 6 pins p6dr is initialized to h'80 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. 169 table 7.11 port 6 pin functions in modes 1 to 5 pin pin functions and selection method p6 7 / bit pstop in mstcrh selects the pin function. pstop 0 1 pin function output p6 7 input lwr functions as lwr regardless of the setting of bit p6 6 ddr p6 6 ddr 0 1 pin function lwr output hwr functions as hwr regardless of the setting of bit p6 5 ddr p6 5 ddr 0 1 pin function hwr output rd functions as rd regardless of the setting of bit p6 4 ddr p6 4 ddr 0 1 pin function rd output as functions as as regardless of the setting of bit p6 3 ddr p6 3 ddr 0 1 pin function as output p6 2 / back bit brle in brcr and bit p6 2 ddr select the pin function as follows. brle 0 1 p6 2 ddr 0 1 ? pin function p6 2 input p6 2 output back output p6 1 / breq bit brle in brcr and bit p6 1 ddr select the pin function as follows. brle 0 1 p6 1 ddr 0 1 ? pin function p6 1 input p6 1 output breq input 170 pin pin functions and selection method p6 0 / wait bit waite in bcr and bit p6 0 ddr select the pin function as follows. waite 0 1 p6 0 ddr 0 1 0* pin function p6 0 input p6 0 output wait input note: * do not set bit p6 0 ddr to 1. 7.8 port 7 7.8.1 overview port 7 is an 8-bit input port that is also used for analog input to the a/d converter and analog output from the d/a converter. the pin functions are the same in all operating modes. figure 7.7 shows the pin configuration of port 7. see section 14, a/d converter, for details of the a/d converter analog input pins, and section 15, d/a converter, for details of the d/a converter analog output pins. port 7 p7 (input)/an (input)/da (output) p7 (input)/an (input)/da (output) p7 (input)/an (input) p7 (input)/an (input) p7 (input)/an (input) p7 (input)/an (input) p7 (input)/an (input) p7 (input)/an (input) 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 port 7 pins 1 0 figure 7.7 port 7 pin configuration 171 7.8.2 register description table 7.12 summarizes the port 7 register. port 7 is an input port, and port 7 has no data direction register. table 7.12 port 7 data register address* name abbreviation r/w initial value h'fffd6 port 7 data register p7dr r undetermined note: * lower 20 bits of the address in advanced mode. port 7 data register (p7dr) bit initial value read/write 0 p7 ? r * note: * 0 1 p7 ? r * 1 2 p7 ? r * 2 3 p7 ? r * 3 4 p7 ? r * 4 5 p7 ? r * 5 6 p7 ? r * 6 7 p7 ? r * 7 70 determined by pins p7 to p7 . when port 7 is read, the pin logic levels are always read. p7dr cannot be modified. 172 7.9 port 8 7.9.1 overview port 8 is a 5-bit input/output port that is also used for cs cs irq irq adtrg cs cs irq irq adtrg irq irq adtrg s adtrg irq irq port 8 p8 / p8 / / p8 / / p8 / / p8 / 4 3 2 1 0 0 1 2 3 port 8 pins cs cs cs cs 3 2 1 irq / adtrg irq irq irq 0 p8 (input)/ (output) p8 (input)/ (output)/ (input) / adtrg (input) p8 (input)/ (output)/ (input) p8 (input)/ (output)/ (input) p8 (input/output)/ (input) 4 3 2 1 0 pin functions in modes 1 to 5 (expanded modes) 0 1 2 3 cs cs cs cs 3 2 1 irq irq irq irq 0 p8 /(input/output) p8 /(input/output)/ (input) / p8 /(input/output)/ (input) p8 /(input/output)/ (input) p8 /(input/output)/ (input) 4 3 2 1 0 pin functions in modes 6 and 7 (single-chip mode) irq irq irq irq adtrg (input) 3 2 1 0 figure 7.8 port 8 pin configuration 173 7.9.2 register descriptions table 7.13 summarizes the registers of port 8. table 7.13 port 8 registers initial value address* name abbreviation r/w modes 1 to 4 modes 5 to 7 h'ee007 port 8 data direction register p8ddr w h'f0 h'e0 h'fffd7 port 8 data register p8dr r/w h'e0 h'e0 note: * lower 20 bits of the address in advanced mode. port 8 data direction register (p8ddr): p8ddr is an 8-bit write-only register that can select input or output for each pin in port 8. bits 7 to 5 are reserved. they are fixed at 1, and cannot be modified. 7 ? 1 ? 1 ? 6 ? 1 ? 1 ? 5 ? 1 ? 1 ? 4 p8 ddr 1 w 0 w 4 3 p8 ddr 0 w 0 w 3 2 p8 ddr 0 w 0 w 2 1 p8 ddr 0 w 0 w 1 0 p8 ddr 0 w 0 w 0 reserved bits port 8 data direction 4 to 0 these bits select input or output for port 8 pins bit modes 1 to 4 initial value read/write initial value read/write modes 5 to 7 ? cs cs cs cs cs cs cs ? 174 p8ddr is initialized to h'f0 in modes 1 to 4, and to h'e0 in modes 5 to 7, by a reset and in hardware standby mode. in software standby mode p8ddr retains its previous setting. therefore, if a transition is made to software standby mode while port 8 is functioning as an input/output port and a p8ddr bit is set to 1, the corresponding pin maintains its output state. port 8 data register (p8dr): p8dr is an 8-bit readable/writable register that stores output data for port 8. when port 8 functions as an output port, the value of this register is output. when a bit in p8ddr is set to 1, if port 8 is read the value of the corresponding p8dr bit is returned. when a bit in p8ddr is cleared to 0, if port 8 is read the corresponding pin logic level is read. bits 7 to 5 are reserved. they are fixed at 1, and cannot be modified. bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 p8 0 r/w 4 3 p8 0 r/w 3 2 p8 0 r/w 2 1 p8 0 r/w 1 0 p8 0 r/w 0 reserved bits port 8 data 4 to 0 these bits store data for port 8 pins p8dr is initialized to h'e0 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. 175 table 7.14 port 8 pin functions in modes 1 to 5 pin pin functions and selection method p8 4 / cs 0 bit p8 4 ddr selects the pin function as follows. p8 4 ddr 0 1 pin function p8 4 input cs 0 output p8 3 / cs 1 / irq 3 / bit p8 3 ddr selects the pin function as follows adtrg p8 3 ddr 0 1 pin function p8 3 input cs 1 output irq 3 input adtrg input p8 2 / cs 2 / irq 2 bit p8 2 ddr selects the pin function as follows. p8 2 ddr 0 1 pin function p8 2 input cs 2 output irq 2 input p8 1 / cs 3 / irq 1 bit p8 1 ddr selects the pin function as follows. p8 1 ddr 0 1 pin function p8 1 input cs 3 output irq 1 input p8 0 / irq 0 bit p8 0 ddr selects the pin function as follows. p8 0 ddr 0 1 pin function p8 0 input p8 0 output irq 0 input 176 table 7.15 port 8 pin functions in modes 6 and 7 pin pin functions and selection method p8 4 bit p8 4 ddr selects the pin function as follows. p8 4 ddr 0 1 pin function p8 4 input p8 4 output p8 3 / irq 3 / adtrg bit p8 3 ddr selects the pin function as follows. p8 3 ddr 0 1 pin function p8 3 input p8 3 output irq 3 input adtrg input p8 2 / irq 2 bit p8 2 ddr selects the pin function as follows. p8 2 ddr 0 1 pin function p8 2 input p8 2 output irq 2 input p8 1 / irq 1 bit p8 1 ddr selects the pin function as follows. p8 1 ddr 0 1 pin function p8 1 input p8 1 output irq 1 input p8 0 / irq 0 bit p8 0 ddr select the pin function as follows. p8 0 ddr 0 1 pin function p8 0 input p8 0 output irq 0 input 177 7.10 port 9 7.10.1 overview port 9 is a 6-bit input/output port that is also used for input and output (txd 0 , txd 1 , rxd 0 , rxd 1 , sck 0 , sck 1 ) by serial communication interface channels 0 and 1 (sci0 and sci1), and for irq irq irq irq port 9 p9 (input/output)/sck p9 (input/output)/sck p9 (input/output)/rxd (input) p9 (input/output)/rxd (input) p9 (input/output)/txd (output) p9 (input/output)/txd (output) 5 4 3 2 1 0 port 9 pins 1 0 (input/output)/irq (input) (input/output)/irq (input) 5 4 1 0 1 0 figure 7.9 port 9 pin configuration 178 7.10.2 register descriptions table 7.16 summarizes the registers of port 9. table 7.16 port 9 registers address* name abbreviation r/w initial value h'ee008 port 9 data direction register p9ddr w h'c0 h'fffd8 port 9 data register p9dr r/w h'c0 note: * lower 20 bits of the address in advanced mode. port 9 data direction register (p9ddr): p9ddr is an 8-bit write-only register that can select input or output for each pin in port 9. bits 7 and 6 are reserved. they are fixed at 1, and cannot be modified. bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 p9 ddr 0 w 5 4 p9 ddr 0 w 4 3 p9 ddr 0 w 3 2 p9 ddr 0 w 2 1 p9 ddr 0 w 1 0 p9 ddr 0 w 0 reserved bits port 9 data direction 5 to 0 these bits select input or output for port 9 pins when port 9 functions as an input/output port, a pin in port 9 becomes an output port if the corresponding p9ddr bit is set to 1, and an input port if this bit is cleared to 0. for the method of selecting the pin functions, see table 7.17. p9ddr is a write-only register. its value cannot be read. all bits return 1 when read. p9ddr is initialized to h'c0 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. therefore, if a transition is made to software standby mode while port 9 is functioning as an input/output port and a p9ddr bit is set to 1, the corresponding pin maintains its output state. 179 port 9 data register (p9dr): p9dr is an 8-bit readable/writable register that stores output data for port 9. when port 9 functions as an output port, the value of this register is output. when a bit in p9ddr is set to 1, if port 9 is read the value of the corresponding p9dr bit is returned. when a bit in p9ddr is cleared to 0, if port 9 is read the corresponding pin logic level is read. bits 7 and 6 are reserved. they are fixed at 1, and cannot be modified. bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 p9 0 r/w 4 p9 0 r/w 4 3 p9 0 r/w 3 2 p9 0 r/w 2 1 p9 0 r/w 1 0 p9 0 r/w 0 reserved bits port 9 data 5 to 0 these bits store data for port 9 pins 5 p9dr is initialized to h'c0 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. 180 table 7.17 port 9 pin functions pin pin functions and selection method p9 5 /sck 1 / irq 5 bit c/ a in smr of sci1, bits cke0 and cke1 in scr, and bit p9 5 ddr select the pin function as follows. cke1 0 1 c/ a 01 ? cke0 0 1 ?? p9 5 ddr 0 1 ?? ? pin function p9 5 input p9 5 output sck 1 output sck 1 output sck 1 input irq 5 input p9 4 /sck 0 / irq 4 bit c/ a in smr of sci0, bits cke0 and cke1 in scr, and bit p9 4 ddr select the pin function as follows. cke1 0 1 c/ a 01 ? cke0 0 1 ?? p9 4 ddr 0 1 ?? ? pin function p9 4 input p9 4 output sck 0 output sck 0 output sck 0 input irq 4 input p9 3 /rxd 1 bit re in scr of sci1, bit smif in scmr, and bit p9 3 ddr select the pin function as follows. smif 0 1 re 0 1 ? p9 3 ddr 0 1 ?? pin function p9 3 input p9 3 output rxd 1 input rxd 1 input p9 2 /rxd 0 bit re in scr of sci0, bit smif in scmr, and bit p9 2 ddr select the pin function as follows. smif 0 1 re 0 1 ? p9 2 ddr 0 1 ?? pin function p9 2 input p9 2 output rxd 0 input rxd 0 input 181 pin pin functions and selection method p9 1 /txd 1 bit te in scr of sci1, bit smif in scmr, and bit p9 1 ddr select the pin function as follows. smif 0 1 te 0 1 ? p9 1 ddr 0 1 ?? pin function p9 1 input p9 1 output txd 1 output txd 1 output* note: * functions as the txd 1 output pin, but there are two states: one in which the pin is driven, and another in which the pin is at high- impedance. p9 0 /txd 0 bit te in scr of sci0, bit smif in scmr, and bit p9 0 ddr select the pin function as follows. smif 0 1 te 0 1 ? p9 0 ddr 0 1 ?? pin function p9 0 input p9 0 output txd 0 output txd 0 output* note: * functions as the txd 0 output pin, but there are two states: one in which the pin is driven, and another in which the pin is at high- impedance. 182 7.11 port a 7.11.1 overview port a is an 8-bit input/output port that is also used for output (tp 7 to tp 0 ) from the programmable timing pattern controller (tpc), input and output (tiocb 2 , tioca 2 , tiocb 1 , tioca 1 , tiocb 0 , tioca 0 , tclkd, tclkc, tclkb, tclka) by the 16-bit timer, clock input (tclkd, tclkc, tclkb, tclka) to the 8-bit timer, and address output (a 23 to a 20 ). a reset or hardware standby transition leaves port a as an input port, except that in modes 3 and 4, one pin is always used for a 20 output. see table 7.19 to 7.21 for the selection of pin functions. usage of pins for tpc, 16-bit timer, and 8-bit timer input and output is described in the sections on those modules. for output of address bits a 23 to a 20 in modes 3, 4, and 5, see section 6.2.4, bus release control register (brcr). pins not assigned to any of these functions are available for generic input/output. figure 7.10 shows the pin configuration of port a. pins in port a can drive one ttl load and a 30-pf capacitive load. they can also drive a darlington transistor pair. port a has schmitt-trigger inputs. 183 port a pa /tp /tiocb /a pa /tp /tioca /a 21 pa /tp /tiocb /a 22 pa /tp /tioca /a 23 pa /tp /tiocb /tclkd pa /tp /tioca /tclkc pa /tp /tclkb pa /tp /tclka 7 6 5 4 3 2 1 0 port a pins 7 6 5 4 3 2 1 0 2 2 1 1 0 0 pa (input/output)/tp (output)/tiocb (input/output) pa (input/output)/tp (output)/tioca (input/output) pa (input/output)/tp (output)/tiocb (input/output) pa (input/output)/tp (output)/tioca (input/output) 7 6 5 4 3 2 1 0 pin functions in modes 1, 2, 6 and 7 pa (input/output)/tp (output)/tiocb (input/output)/tclkd (input) pa (input/output)/tp (output)/tioca (input/output)/tclkc (input) pa (input/output)/tp (output)/tclkb (input) pa (input/output)/tp (output)/tclka (input) pin functions in mode 5 7 6 5 4 3 2 1 0 2 2 1 1 0 0 a (output) 20 pa (input/output)/tp (output)/tioca (input/output)/a (output) pa (input/output)/tp (output)/tiocb (input/output)/a (output) pa (input/output)/tp (output)/tioca (input/output)/a (output) 6 5 4 3 2 1 0 pin functions in modes 3 and 4 6 5 4 3 2 1 0 2 1 1 0 0 pa (input/output)/tp (output)/tclka (input) pa (input/output)/tp (output)/tiocb (input/output)/tclkd (input) pa (input/output)/tp (output)/tioca (input/output)/tclkc (input) pa (input/output)/tp (output)/tclkb (input) pa 7 (input/output)/tp 7 (output)/tiocb 2 (input/output)/a (output) pa 6 (input/output)/tp 6 (output)/tioca 2 (input/output)/a (output) pa 5 (input/output)/tp 5 (output)/tiocb 1 (input/output)/a (output) pa 4 (input/output)/tp 4 (output)/tioca 1 (input/output)/a (output) pa 3 (input/output)/tp 3 (output)/tiocb 0 (input/output)/tclkd (input) pa 2 (input/output)/tp 2 (output)/tioca 0 (input/output)/tclkc (input) pa 1 (input/output)/tp 1 (output)/tclkb (input) pa 0 (input/output)/tp 0 (output)/tclka (input) 20 21 22 23 20 21 22 23 figure 7.10 port a pin configuration 184 7.11.2 register descriptions table 7.18 summarizes the registers of port a. table 7.18 port a registers initial value address* name r/w modes 1, 2, 5, 6 and 7 modes 3, 4 h'ee009 port a data direction register paddr w h'00 h'80 h'fffd9 port a data register padr r/w h'00 h'00 note: * lower 20 bits of the address in advanced mode. port a data direction register (paddr): paddr is an 8-bit write-only register that can select input or output for each pin in port a. when pins are used for tpc output, the corresponding paddr bits must also be set. 7 pa ddr 1 ? 0 w port a data direction 7 to 0 these bits select input or output for port a pins 7 6 pa ddr 0 w 0 w 6 5 pa ddr 0 w 0 w 5 4 pa ddr 0 w 0 w 4 3 pa ddr 0 w 0 w 3 2 pa ddr 0 w 0 w 2 1 pa ddr 0 w 0 w 1 0 pa ddr 0 w 0 w 0 bit modes 3 and 4 initial value read/write initial value read/write modes 1, 2, 5, 6 and 7 the pin functions that can be selected for pins pa 7 to pa 4 differ between modes 1, 2, 6, and 7, and modes 3 to 5. for the method of selecting the pin functions, see tables 7.19 and 7.20. the pin functions that can be selected for pins pa 3 to pa 0 are the same in modes 1 to 7. for the method of selecting the pin functions, see table 7.21. when port a functions as an input/output port, a pin in port a becomes an output port if the corresponding paddr bit is set to 1, and an input port if this bit is cleared to 0. in modes 3 and 4, pa 7 ddr is fixed at 1 and pa 7 functions as the a 20 address output pin. paddr is a write-only register. its value cannot be read. all bits return 1 when read. paddr is initialized to h'00 by a reset and in hardware standby mode in modes 1, 2, 5, 6, and 7. it is initialized to h'80 by a reset and in hardware standby mode in modes 3 and 4. in software standby mode it retains its previous setting. therefore, if a transition is made to software standby 185 mode while port a is functioning as an input/output port and a paddr bit is set to 1, the corresponding pin maintains its output state. port a data register (padr): padr is an 8-bit readable/writable register that stores output data for port a. when port a functions as an output port, the value of this register is output. when a bit in paddr is set to 1, if port a is read the value of the corresponding padr bit is returned. when a bit in paddr is cleared to 0, if port a is read the corresponding pin logic level is read. bit initial value read/write 0 pa 0 r/w 0 1 pa 0 r/w 1 2 pa 0 r/w 2 3 pa 0 r/w 3 4 pa 0 r/w 4 5 pa 0 r/w 5 6 pa 0 r/w 6 7 pa 0 r/w 7 port a data 7 to 0 these bits store data for port a pins padr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. 186 table 7.19 port a pin functions (modes 1, 2, 6, and 7) pin pin functions and selection method pa 7 /tp 7 / tiocb 2 bit pwm2 in tmdr, bits iob2 to iob0 in tior2, bit nder7 in ndera, and bit pa 7 ddr select the pin function as follows. 16-bit timer channel 2 settings (1) in table below (2) in table below pa 7 ddr ? 01 1 nder7 ?? 01 pin function tiocb 2 output pa 7 input pa 7 output tp 7 output tiocb 2 input* note: * tiocb 2 input when iob2 = 1 and pwm2 = 0. 16-bit timer channel 2 settings (2) (1) (2) iob2 0 1 iob1 0 0 1 ? iob0 0 1 ?? pa 6 /tp 6 / tioca 2 bit pwm2 in tmdr, bits ioa2 to ioa0 in tior2, bit nder6 in ndera, and bit pa 6 ddr select the pin function as follows. 16-bit timer channel 2 settings (1) in table below (2) in table below pa 6 ddr ? 01 1 nder6 ?? 01 pin function tioca 2 output pa 6 input pa 6 output tp 6 output tioca 2 input* note: * tioca 2 input when ioa2 = 1. 16-bit timer channel 2 settings (2) (1) (2) (1) pwm2 0 1 ioa2 0 1 ? ioa1 0 0 1 ?? ioa0 0 1 ?? ? 187 pin pin functions and selection method pa 5 /tp 5 / tiocb 1 bit pwm1 in tmdr, bits iob2 to iob0 in tior1, bit nder5 in ndera, and bit pa 5 ddr select the pin function as follows. 16-bit timer channel 1 settings (1) in table below (2) in table below pa 5 ddr ? 01 1 nder5 ?? 01 pin function tiocb 1 output pa 5 input pa 5 output tp 5 output tiocb 1 input* note: * tiocb 1 input when iob2 = 1 and pwm1 = 0. 16-bit timer channel 1 settings (2) (1) (2) iob2 0 1 iob1 0 0 1 ? iob0 0 1 ?? pa 4 /tp 4 / tioca 1 bit pwm1 in tmdr, bits ioa2 to ioa0 in tior1, bit nder4 in ndera, and bit pa 4 ddr select the pin function as follows. 16-bit timer channel 1 settings (1) in table below (2) in table below pa 4 ddr ? 01 1 nder4 ?? 01 pin function tioca 1 output pa 4 input pa 4 output tp 4 output tioca 1 input* note: * tioca 1 input when ioa2 = 1. 16-bit timer channel 1 settings (2) (1) (2) (1) pwm1 0 1 ioa2 0 1 ? ioa1 0 0 1 ?? ioa0 0 1 ?? ? 188 table 7.20 port a pin functions (modes 3 to 5) pin pin functions and selection method pa 7 /tp 7 / modes 3 and 4: always used as a 20 output. tiocb 2 / a 20 pin function a 20 output mode 5: bit pwm2 in tmdr, bits iob2 to iob0 in tior2, bit nder7 in ndera, bit a20e in brcr, and bit pa 7 ddr select the pin function as follows. a20e 1 0 16-bit timer channel 2 settings (1) in table below (2) in table below ? pa 7 ddr ? 011 ? nder7 ?? 01 ? pin function tiocb 2 output pa 7 input pa 7 output tp 7 output a 20 output tiocb 2 input* note: * tiocb 2 input when iob2 = 1 and pwm2 = 0. 16-bit timer channel 2 settings (2) (1) (2) iob2 0 1 iob1 0 0 1 ? iob0 0 1 ?? 189 pin pin functions and selection method pa 6 /tp 6 / tioca 2 /a 21 bit pwm2 in tmdr, bits ioa2 to ioa0 in tior2, bit nder6 in ndera, bit a21e in brcr, and bit pa 6 ddr select the pin function as follows. a21e 1 0 16-bit timer channel 2 settings (1) in table below (2) in table below ? pa 6 ddr ? 011 ? nder6 ?? 01 ? pin function tioca 2 output pa 6 input pa 6 output tp 6 output a 21 output tioca 2 input* note: * tioca 2 input when ioa2 = 1. 16-bit timer channel 2 settings (2) (1) (2) (1) pwm2 0 1 ioa2 0 1 ? ioa1 0 0 1 ?? ioa0 0 1 ??? pa 5 /tp 5 / tiocb 1 /a 22 bit pwm1 in tmdr, bits iob2 to iob0 in tior1, bit nder5 in ndera, bit a22e in brcr, and bit pa 5 ddr select the pin function as follows. a22e 1 0 16-bit timer channel 1 settings (1) in table below (2) in table below ? pa 5 ddr ? 011 ? nder5 ?? 01 ? pin function tiocb 1 output pa 5 input pa 5 output tp 5 output a 22 output tiocb 1 input* note: * tiocb 1 input when iob2 = 1 and pwm1 = 0. 16-bit timer channel 1 settings (2) (1) (2) iob2 0 1 iob1 0 0 1 ? iob0 0 1 ?? 190 pin pin functions and selection method pa 4 /tp 4 / tioca 1 /a 23 bit pwm1 in tmdr, bits ioa2 to ioa0 in tior1, bit nder4 in ndera, bit a23e in brcr, and bit pa 4 ddr select the pin function as follows. a23e 1 0 16-bit timer channel 1 settings (1) in table below (2) in table below ? pa 4 ddr ? 011 ? nder4 ?? 01 ? pin function tioca 1 output pa 4 input pa 4 output tp 4 output a 23 output tioca 1 input* note: * tioca 1 input when ioa2 = 1. 16-bit timer channel 1 settings (2) (1) (2) (1) pwm1 0 1 ioa2 0 1 ? ioa1 0 0 1 ?? ioa0 0 1 ?? ? 191 table 7.21 port a pin functions (modes 1 to 7) pin pin functions and selection method pa 3 /tp 3 / tiocb 0 / tclkd bit pwm0 in tmdr, bits iob2 to iob0 in tior0, bits tpsc2 to tpsc0 in 16tcr2 to 16tcr0 of the 16-bit timer, bits cks2 to cks0 in 8tcr2 of the 8-bit timer, bit nder3 in ndera, and bit pa 3 ddr select the pin function as follows. 16-bit timer channel 0 settings (1) in table below (2) in table below pa 3 ddr ? 011 nder3 ?? 01 pin function tiocb 0 output pa 3 input pa 3 output tp 3 output tiocb 0 input* 1 tclkd input* 2 notes: *1 tiocb 0 input when iob2 = 1 and pwm0 = 0. *2 tclkd input when tpsc2 = tpsc1 = tpsc0 = 1 in any of 16tcr2 to 16tcr0, or bits cks2 to cks0 in 8tcr2 are as shown in (3) in the table below. 16-bit timer channel 0 settings (2) (1) (2) iob2 0 1 iob1 0 0 1 ? iob0 0 1 ?? 8-bit timer channel 2 settings (4) (3) cks2 0 1 cks1 ? 01 cks0 ? 01 ? 192 pin pin functions and selection method pa 2 /tp 2 / tioca 0 / tclkc bit pwm0 in tmdr, bits ioa2 to ioa0 in tior0, bits tpsc2 to tpsc0 in 16tcr2 to 16tcr0 of the 16-bit timer, bits cks2 to cks0 in 8tcr0 of the 8-bit timer, bit nder2 in ndera, and bit pa 2 ddr select the pin function as follows. 16-bit timer channel 0 settings (1) in table below (2) in table below pa 2 ddr ? 01 1 nder2 ?? 01 pin function tioca 0 output pa 2 input pa 2 output tp 2 output tioca 0 input* 1 tclkc input* 2 notes: *1 tioca 0 input when ioa2 = 1. *2 tclkc input when tpsc2 = tpsc1 = 1 and tpsc0 = 0 in any of 16tcr2 to 16tcr0, or bits cks2 to cks0 in 8tcr0 are as shown in (3) in the table below. 16-bit timer channel 0 settings (2) (1) (2) (1) pwm0 0 1 ioa2 0 1 ? ioa1 0 0 1 ?? ioa0 0 1 ?? ? 8-bit timer channel 0 settings (4) (3) cks2 0 1 cks1 ? 01 cks0 ? 01 ? 193 pin pin functions and selection method pa 1 /tp 1 / tclkb bit mdf in tmdr, bits tpsc2 to tpsc0 in 16tcr2 to 16tcr0 of the 16-bit timer, bits cks2 to cks0 in 8tcr3 of the 8-bit timer, bit nder1 in ndera, and bit pa 1 ddr select the pin function as follows. pa 1 ddr 0 1 1 nder1 ? 01 pin function pa 1 input pa 1 output tp 1 output tclkb input* note: * clkb input when mdf = 1 in tmdr, or tpsc2 = 1, tpsc1 = 0, and tpsc0 = 1 in any of 16tcr2 to 16tcr0, or bits cks2 to cks0 in 8tcr3 are as shown in (1) in the table below. 8-bit timer channel 3 settings (2) (1) cks2 0 1 cks1 ? 01 cks0 ? 01 ? pa 0 /tp 0 / tclka bit mdf in tmdr, bits tpsc2 to tpsc0 in 16tcr2 to 16tcr0 of the 16-bit timer, bits cks2 to cks0 in 8tcr1 of the 8-bit timer, bit nder0 in ndera, and bit pa 0 ddr select the pin function as follows. pa 0 ddr 0 1 nder0 ? 01 pin function pa 0 input pa 0 output tp 0 output tclka input* note: * tclka input when mdf = 1 in tmdr, or tpsc2 = 1 and tpsc1 = 0, and tpsc0 = 0 in any of 16tcr2 to 16tcr0, or bits cks2 to cks0 in 8tcr1 are as shown in (1) in the table below. 8-bit timer channel 1 settings (2) (1) cks2 0 1 cks1 ? 01 cks0 ? 01 ? 194 7.12 port b 7.12.1 overview port b is an 8-bit input/output port that is also used for output (tp 15 to tp 8 ) from the programmable timing pattern controller (tpc), input/output (tmio 3 , tmo 2 , tmio 1 , tmo 0 ) by the 8-bit timer, and cs cs cs cs 195 port b pb 7 /tp 15 pb 6 /tp 14 pb 5 /tp 13 pb 4 /tp 12 pb 3 /tp /tmio 3 / cs 4 11 pb 2 /tp /tmo 2 / cs 5 10 pb 1 /tp /tmio 1 / cs 6 9 pb 0 /tp /tmo 0 / cs 7 8 port b pins pb 7 (input/output)/tp 15 (output) pb 6 (input/output)/tp 14 (output) pb 5 (input/output)/tp 13 (output) pb 4 (input/output)/tp 12 (output) pb 3 (input/output)/tp 11 (output) /tmio 3 (input/output) / cs 4 (output) pb 2 (input/output)/tp 10 (output) /tmo 2 (output) / cs 5 (output) pb 1 (input/output)/tp 9 (output) /tmio 1 (input/output) / cs 6 (output) pb 0 (input/output)/tp 8 (output) /tmo 0 (output) / cs 7 (output) pin functions in modes 1 to 5 pb 7 (input/output)/tp 15 (output) pb 6 (input/output)/tp 14 (output) pb 5 (input/output)/tp 13 (output) pb 4 (input/output)/tp 12 (output) pb 3 (input/output)/tp 11 (output) /tmio 3 (input/output) pb 2 (input/output)/tp 10 (output) /tmo 2 (output) pb 1 (input/output)/tp 9 (output) /tmio 1 (input/output) pb 0 (input/output)/tp 8 (output) /tmo 0 (output) pin functions in modes 6 and 7 figure 7.11 port b pin configuration 196 7.12.2 register descriptions table 7.22 summarizes the registers of port b. table 7.22 port b registers address* name abbreviation r/w initial value h'ee00a port b data direction register pbddr w h'00 h'fffda port b data register pbdr r/w h'00 note: * lower 20 bits of the address in advanced mode. port b data direction register (pbddr): pbddr is an 8-bit write-only register that can select input or output for each pin in port b. when pins are used for tpc output, the corresponding pbddr bits must also be set. bit initial value read/write 7 pb ddr 0 w port b data direction 7 to 0 these bits select input or output for port b pins 7 6 pb ddr 0 w 6 5 pb ddr 0 w 5 4 pb ddr 0 w 4 3 pb ddr 0 w 3 2 pb ddr 0 w 2 1 pb ddr 0 w 1 0 pb ddr 0 w 0 the pin functions that can be selected for port b differ between modes 1 to 5, and modes 6 and 7. for the method of selecting the pin functions, see tables 7.23 and 7.24. when port b functions as an input/output port, a pin in port b becomes an output port if the corresponding pbddr bit is set to 1, and an input port if this bit is cleared to 0. pbddr is a write-only register. its value cannot be read. all bits return 1 when read. pbddr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. therefore, if a transition is made to software standby mode while port b is functioning as an input/output port and a pbddr bit is set to 1, the corresponding pin maintains its output state. 197 port b data register (pbdr): pbdr is an 8-bit readable/writable register that stores output data for pins port b. when port b functions as an output port, the value of this register is output. when a bit in pbddr is set to 1, if port b is read the value of the corresponding pbdr bit is returned. when a bit in pbddr is cleared to 0, if port b is read the corresponding pin logic level is read. bit initial value read/write 0 pb 0 r/w 0 1 pb 0 r/w 1 2 pb 0 r/w 2 3 pb 0 r/w 3 4 pb 0 r/w 4 5 pb 0 r/w 5 6 pb 0 r/w 6 7 pb 0 r/w 7 port b data 7 to 0 these bits store data for port b pins pbdr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. 198 table 7.23 port b pin functions (modes 1 to 5) pin pin functions and selection method pb 7 /tp 15 bit nder15 in nderb and bit pb 7 ddr select the pin function as follows. pb 7 ddr 0 1 1 nder15 ? 01 pin function pb 7 input pb 7 output tp 15 output pb 6 /tp 14 bit nder14 in nderb and bit pb 6 ddr select the pin function as follows. pb 6 ddr 0 1 1 nder14 ? 01 pin function pb 6 input pb 6 output tp 14 output pb 5 /tp 13 bit nder13 in nderb and bit pb 5 ddr select the pin function as follows. pb 5 ddr 0 1 1 nder13 ? 01 pin function pb 5 input pb 5 output tp 13 output pb 4 /tp 12 bit nder12 in nderb and bit pb 4 ddr select the pin function as follows. pb 4 ddr 0 1 1 nder12 ? 01 pin function pb 4 input pb 4 output tp 12 output pb 3 /tp 11 / tmio 3 / cs 4 bits ois3/2 and os1/0 in 8tcsr3, bits cclr1/0 in 8tcr3, bit cs4e in cscr, bit nder11 in nderb, and bit pb 3 ddr select the pin function as follows. ois3/2 and os1/0 all 0 not all 0 cs4e 0 1 ? pb 3 ddr 0 1 1 ?? nder11 ? 01 ?? pin function pb 3 input pb 3 output tp 11 output cs 4 output tmio 3 output tmio 3 input* note: * tmio 3 input when bit ice = 1 in 8tcsr3. 199 pin pin functions and selection method pb 2 /tp 10 / tmo 2 / cs 5 bits ois3/2 and os1/0 in 8tcsr2, bit cs5e in cscr, bit nder10 in nderb, and bit pb 2 ddr select the pin function as follows. ois3/2 and os1/0 all 0 not all 0 cs5e 0 1 ? pb 2 ddr 0 1 1 ?? nder10 ? 01 ?? pin function pb 2 input pb 2 output tp 10 output cs 5 output tmio 2 output pb 1 /tp 9 / tmio 1 / cs 6 bits ois3/2 and os1/0 in 8tcsr1, bits cclr1/0 in 8tcr1, bit cs6e in cscr, bit nder9 in nderb, and bit pb 1 ddr select the pin function as follows. ois3/2 and os1/0 all 0 not all 0 cs6e 0 1 ? pb 1 ddr 0 1 1 ?? nder9 ? 01 ?? pin function pb 1 input pb 1 output tp 9 output cs 6 output tmio 1 output tmio 1 input* note: * tmio 1 input when bit ice = 1 in 8tcsr1. pb 0 /tp 8 / tmo 0 / cs 7 bits ois3/2 and os1/0 in 8tcsr0, bit cs7e in cscr, bit nder8 in nderb, and bit pb 0 ddr select the pin function as follows. ois3/2 and os1/0 all 0 not all 0 cs7e 0 1 ? pb 0 ddr 0 1 1 ?? nder8 ? 01 ?? pin function pb 0 input pb 0 output tp 8 output cs 7 output tmo 0 output 200 table 7.24 port b pin functions (modes 6 and 7) pin pin functions and selection method pb 7 /tp 15 bit nder15 in nderb and bit pb 7 ddr select the pin function as follows. pb 7 ddr 0 1 1 nder15 ? 01 pin function pb 7 input pb 7 output tp 15 output pb 6 /tp 14 bit nder14 in nderb and bit pb 6 ddr select the pin function as follows. pb 6 ddr 0 1 1 nder14 ? 01 pin function pb 6 input pb 6 output tp 14 output pb 5 /tp 13 bit nder13 in nderb and bit pb 5 ddr select the pin function as follows. pb 5 ddr 0 1 1 nder13 ? 01 pin function pb 5 input pb 5 output tp 13 output pb 4 /tp 12 bit nder12 in nderb and bit pb 4 ddr select the pin function as follows. pb 4 ddr 0 1 1 nder12 ? 01 pin function pb 4 input pb 4 output tp 12 output pb 3 /tp 11 / tmio 3 bits ois3/2 and os1/0 in 8tcsr3, bits cclr1/0 in 8tcr3, bit nder11 in nderb, and bit pb 3 ddr select the pin function as follows. ois3/2 and os1/0 all 0 not all 0 pb 3 ddr 0 1 1 ? nder11 ? 01 ? pin function pb 3 input pb 3 output tp 11 output tmio 3 output tmio 3 input* note: * tmio 3 input when bit ice = 1 in 8tcsr3. 201 pin pin functions and selection method pb 2 /tp 10 / tmo 2 bits ois3/2 and os1/0 in 8tcsr2, bit nder10 in nderb, and bit pb 2 ddr select the pin function as follows. ois3/2 and os1/0 all 0 not all 0 pb 2 ddr 0 1 1 ? nder10 ? 01 ? pin function pb 2 input pb 2 output tp 10 output tmo 2 output pb 1 /tp 9 / tmio 1 bits ois3/2 and os1/0 in 8tcsr1, bits cclr1 and cclr0 in 8tcr0, bit nder9 in nderb, and bit pb 1 ddr select the pin function as follows. ois3/2 and os1/0 all 0 not all 0 pb 1 ddr 0 1 1 ? nder9 ? 01 ? pin function pb 1 input pb 1 output tp 9 output tmio 1 output tmio 1 input* note: * tmio 1 input when bit ice = 1 in 8tcsr1. pb 2 /tp 8 / tmo 0 bits ois3/2 and os1/0 in 8tcsr0, bit nder8 in nderb, and bit pb 0 ddr select the pin function as follows. ois3/2 and os1/0 all 0 not all 0 pb 2 ddr 0 1 1 ? nder8 ? 01 ? pin function pb 0 input pb 0 output tp 8 output tmo 0 output 202 203 section 8 16-bit timer 8.1 overview the h8/3024 series has built-in 16-bit timer module with three 16-bit counter channels. 8.1.1 features 16-bit timer features are listed below. ? capability to process up to 6 pulse outputs or 6 pulse inputs ? six general registers (grs, two per channel) with independently-assignable output compare or input capture functions ? selection of eight counter clock sources for each channel: internal clocks: , /2, /4, /8 external clocks: tclka, tclkb, tclkc, tclkd ? five operating modes selectable in all channels: ? waveform output by compare match selection of 0 output, 1 output, or toggle output (only 0 or 1 output in channel 2) ? input capture function rising edge, falling edge, or both edges (selectable) ? counter clearing function counters can be cleared by compare match or input capture ? synchronization two or more timer counters (16tcnts) can be preset simultaneously, or cleared simultaneously by compare match or input capture. counter synchronization enables synchronous register input and output. ? pwm mode pwm output can be provided with an arbitrary duty cycle. with synchronization, up to three-phase pwm output is possible ? phase counting mode selectable in channel 2 two-phase encoder output can be counted automatically. ? high-speed access via internal 16-bit bus the 16tcnts and grs can be accessed at high speed via a 16-bit bus. ? any initial timer output value can be set ? nine interrupt sources each channel has two compare match/input capture interrupts and an overflow interrupt. all interrupts can be requested independently. 204 ? output triggering of programmable timing pattern controller (tpc) compare match/input capture signals from channels 0 to 2 can be used as tpc output triggers. table 8.1 summarizes the 16-bit timer functions. table 8.1 16-bit timer functions item channel 0 channel 1 channel 2 clock sources internal clocks: ? ? ? ? ? ? ? ? ? 205 8.1.2 block diagrams 16-bit timer block diagram (overall): figure 8.1 is a block diagram of the 16-bit timer. 16-bit timer channel 2 16-bit timer channel 1 16-bit timer channel 0 module data bus bus interface on-chip data bus imia0 to imia2 imib0 to imib2 ovi0 to ovi2 tclka to tclkd figure 8.1 16-bit timer block diagram (overall) 206 block diagram of channels 0 and 1: 16-bit timer channels 0 and 1 are functionally identical. both have the structure shown in figure 8.2. clock selector comparator control logic tclka to tclkd figure 8.2 block diagram of channels 0 and 1 207 block diagram of channel 2: figure 8.3 is a block diagram of channel 2 clock selector comparator control logic tclka to tclkd figure 8.3 block diagram of channel 2 208 8.1.3 pin configuration table 8.2 summarizes the 16-bit timer pins. table 8.2 16-bit timer pins channel name abbre- viation input/ output function common clock input a tclka input external clock a input pin (phase-a input pin in phase counting mode) clock input b tclkb input external clock b input pin (phase-b input pin in phase counting mode) clock input c tclkc input external clock c input pin clock input d tclkd input external clock d input pin 0 input capture/output compare a0 tioca 0 input/ output gra0 output compare or input capture pin pwm output pin in pwm mode input capture/output compare b0 tiocb 0 input/ output grb0 output compare or input capture pin 1 input capture/output compare a1 tioca 1 input/ output gra1 output compare or input capture pin pwm output pin in pwm mode input capture/output compare b1 tiocb 1 input/ output grb1 output compare or input capture pin 2 input capture/output compare a2 tioca 2 input/ output gra2 output compare or input capture pin pwm output pin in pwm mode input capture/output compare b2 tiocb 2 input/ output grb2 output compare or input capture pin 209 8.1.4 register configuration table 8.3 summarizes the 16-bit timer registers. table 8.3 16-bit timer registers channel address* 1 name abbre- viation r/w initial value common h'fff60 timer start register tstr r/w h'f8 h'fff61 timer synchro register tsnc r/w h'f8 h'fff62 timer mode register tmdr r/w h'98 h'fff63 timer output level setting register tolr w h'c0 h'fff64 timer interrupt status register a tisra r/(w) * 2 h'88 h'fff65 timer interrupt status register b tisrb r/(w) * 2 h'88 h'fff66 timer interrupt status register c tisrc r/(w) * 2 h'88 0 h'fff68 timer control register 0 16tcr0 r/w h'80 h'fff69 timer i/o control register 0 tior0 r/w h'88 h'fff6a timer counter 0h 16tcnt0h r/w h'00 h'fff6b timer counter 0l 16tcnt0l r/w h'00 h'fff6c general register a0h gra0h r/w h'ff h'fff6d general register a0l gra0l r/w h'ff h'fff6e general register b0h grb0h r/w h'ff h'fff6f general register b0l grb0l r/w h'ff 1 h'fff70 timer control register 1 16tcr1 r/w h'80 h'fff71 timer i/o control register 1 tior1 r/w h'88 h'fff72 timer counter 1h 16tcnt1h r/w h'00 h'fff73 timer counter 1l 16tcnt1l r/w h'00 h'fff74 general register a1h gra1h r/w h'ff h'fff75 general register a1l gra1l r/w h'ff h'fff76 general register b1h grb1h r/w h'ff h'fff77 general register b1l grb1l r/w h'ff 210 channel address* 1 name abbre- viation r/w initial value 2 h'fff78 timer control register 2 16tcr2 r/w h'80 h'fff79 timer i/o control register 2 tior2 r/w h'88 h'fff7a timer counter 2h 16tcnt2h r/w h'00 h'fff7b timer counter 2l 16tcnt2l r/w h'00 h'fff7c general register a2h gra2h r/w h'ff h'fff7d general register a2l gra2l r/w h'ff h'fff7e general register b2h grb2h r/w h'ff h'fff7f general register b2l grb2l r/w h'ff notes: *1 the lower 20 bits of the address in advanced mode are indicated. *2 only 0 can be written in bits 3 to 0, to clear the flags. 8.2 register descriptions 8.2.1 timer start register (tstr) tstr is an 8-bit readable/writable register that starts and stops the timer counter (16tcnt) in channels 0 to 2. bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 2 str2 0 r/w 1 str1 0 r/w 0 str0 0 r/w reserved bits counter start 2 to 0 these bits start and stop 16tcnt2 to 16tcnt0 tstr is initialized to h'f8 by a reset and in standby mode. bits 7 to 3?eserved: these bits cannot be modified and are always read as 1. bit 2?ounter start 2 (str2): starts and stops timer counter 2 (16tcnt2). bit 2 str2 description 0 16tcnt2 is halted (initial value) 1 16tcnt2 is counting 211 bit 1?ounter start 1 (str1): starts and stops timer counter 1 (16tcnt1). bit 1 str1 description 0 16tcnt1 is halted (initial value) 1 16tcnt1 is counting bit 0?ounter start 0 (str0): starts and stops timer counter 0 (16tcnt0). bit 0 str0 description 0 16tcnt0 is halted (initial value) 1 16tcnt0 is counting 8.2.2 timer synchro register (tsnc) tsnc is an 8-bit readable/writable register that selects whether channels 0 to 2 operate independently or synchronously. channels are synchronized by setting the corresponding bits to 1. bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 2 sync2 0 r/w 1 sync1 0 r/w 0 sync0 0 r/w reserved bits timer sync 2 to 0 these bits synchronize channels 2 to 0 tsnc is initialized to h'f8 by a reset and in standby mode. bits 7 to 3?eserved: these bits cannot be modified and are always read as 1. bit 2?imer sync 2 (sync2): selects whether channel 2 operates independently or synchronously. bit 2 sync2 description 0 channel 2 ? s timer counter (16tcnt2) operates independently (initial value) 16tcnt2 is preset and cleared independently of other channels 1 channel 2 operates synchronously 16tcnt2 can be synchronously preset and cleared 212 bit 1?imer sync 1 (sync1): selects whether channel 1 operates independently or synchronously. bit 1 sync1 description 0 channel 1 ? s timer counter (16tcnt1) operates independently (initial value) 16tcnt1 is preset and cleared independently of other channels 1 channel 1 operates synchronously 16tcnt1 can be synchronously preset and cleared bit 0?imer sync 0 (sync0): selects whether channel 0 operates independently or synchronously. bit 0 sync0 description 0 channel 0 ? s timer counter (16tcnt0) operates independently (initial value) 16tcnt0 is preset and cleared independently of other channels 1 channel 0 operates synchronously 16tcnt0 can be synchronously preset and cleared 8.2.3 timer mode register (tmdr) tmdr is an 8-bit readable/writable register that selects pwm mode for channels 0 to 2. it also selects phase counting mode and the overflow flag (ovf) setting conditions for channel 2. bit initial value read/write 7 ? 1 ? 6 mdf 0 r/w 5 fdir 0 r/w 4 ? 1 ? 3 ? 1 ? 0 pwm0 0 r/w 2 pwm2 0 r/w 1 pwm1 0 r/w reserved bit reserved bit pwm modes 2 to 0 these bits select pwm mode for channels 2 to 0 phase counting mode flag selects phase counting mode for channel 2 flag direction selects the setting condition for the overflow flag (ovf) in tisrc tmdr is initialized to h'98 by a reset and in standby mode. 213 bit 7?eserved: this bit cannot be modified and is always read as 1. bit 6?hase counting mode flag (mdf): selects whether channel 2 operates normally or in phase counting mode. bit 6 mdf description 0 channel 2 operates normally (initial value) 1 channel 2 operates in phase counting mode when mdf is set to 1 to select phase counting mode, 16tcnt2 operates as an up/down-counter and pins tclka and tclkb become counter clock input pins. 16tcnt2 counts both rising and falling edges of tclka and tclkb, and counts up or down as follows. counting direction down-counting up-counting tclka pin high low low high tclkb pin low high high low in phase counting mode, external clock edge selection by bits ckeg1 and ckeg0 in 16tcr2 and counter clock selection by bits tpsc2 to tpsc0 are invalid, and the above phase counting mode operations take precedence. the counter clearing condition selected by the cclr1 and cclr0 bits in 16tcr2 and the compare match/input capture settings and interrupt functions of tior2, tisra, tisrb, tisrc remain effective in phase counting mode. bit 5?lag direction (fdir): designates the setting condition for the ovf flag in tisrc. the fdir designation is valid in all modes in channel 2. bit 5 fdir description 0 ovf is set to 1 in tisrc when 16tcnt2 overflows or underflows (initial value) 1 ovf is set to 1 in tisrc when 16tcnt2 overflows bits 4 and 3?eserved: these bits cannot be modified and are always read as 1. 214 bit 2?wm mode 2 (pwm2): selects whether channel 2 operates normally or in pwm mode. bit 2 pwm2 description 0 channel 2 operates normally (initial value) 1 channel 2 operates in pwm mode when bit pwm2 is set to 1 to select pwm mode, pin tioca 2 becomes a pwm output pin. the output goes to 1 at compare match with gra2, and to 0 at compare match with grb2. bit 1?wm mode 1 (pwm1): selects whether channel 1 operates normally or in pwm mode. bit 1 pwm1 description 0 channel 1 operates normally (initial value) 1 channel 1 operates in pwm mode when bit pwm1 is set to 1 to select pwm mode, pin tioca 1 becomes a pwm output pin. the output goes to 1 at compare match with gra1, and to 0 at compare match with grb1. bit 0?wm mode 0 (pwm0): selects whether channel 0 operates normally or in pwm mode. bit 0 pwm0 description 0 channel 0 operates normally (initial value) 1 channel 0 operates in pwm mode when bit pwm0 is set to 1 to select pwm mode, pin tioca 0 becomes a pwm output pin. the output goes to 1 at compare match with gra0, and to 0 at compare match with grb0. 215 8.2.4 timer interrupt status register a (tisra) tisra is an 8-bit readable/writable register that indicates gra compare match or input capture and enables or disables gra compare match and input capture interrupt requests. 7 ? 1 ? bit initial value read/write 6 imiea2 0 r/w 5 imiea1 0 r/w 4 imiea0 0 r/w 3 ? 1 ? 2 imfa2 0 r/(w)* 1 imfa1 0 r/(w)* 0 imfa0 0 r/(w)* reserved bit reserved bit input capture/compare match interrupt enable a2 to a0 these bits enable or disable interrupts by the imfa flags input capture/compare match flags a2 to a0 status flags indicating gra compare match or input capture note: * only 0 can be written, to clear the flag. tisra is initialized to h'88 by a reset and in standby mode. bit 7?eserved: this bit cannot be modified and is always read as 1. bit 6?nput capture/compare match interrupt enable a2 (imiea2): enables or disables the interrupt requested by the imfa2 when imfa2 flag is set to 1. bit 6 imiea2 description 0 imia2 interrupt requested by imfa2 flag is disabled (initial value) 1 imia2 interrupt requested by imfa2 flag is enabled bit 5?nput capture/compare match interrupt enable a1 (imiea1): enables or disables the interrupt requested by the imfa1 flag when imfa1 is set to 1. 216 bit 5 imiea1 description 0 imia1 interrupt requested by imfa1 flag is disabled (initial value) 1 imia1 interrupt requested by imfa1 flag is enabled bit 4?nput capture/compare match interrupt enable a0 (imiea0): enables or disables the interrupt requested by the imfa0 flag when imfa0 is set to 1. bit 4 imiea0 description 0 imia0 interrupt requested by imfa0 flag is disabled (initial value) 1 imia0 interrupt requested by imfa0 flag is enabled bit 3?eserved: this bit cannot be modified and is always read as 1. bit 2?nput capture/compare match flag a2 (imfa2): this status flag indicates gra2 compare match or input capture events. bit 2 imfa2 description 0 [clearing condition] (initial value) read imfa2 flag when imfa2 =1, then write 0 in imfa2 flag 1 [setting conditions] ? 16tcnt2 = gra2 when gra2 functions as an output compare register ? 16tcnt2 value is transferred to gra2 by an input capture signal when gra2 functions as an input capture register bit 1?nput capture/compare match flag a1 (imfa1): this status flag indicates gra1 compare match or input capture events. bit 1 imfa1 description 0 [clearing condition] (initial value) read imfa1 flag when imfa1 =1, then write 0 in imfa1 flag 1 [setting conditions] ? 16tcnt1 = gra1 when gra1 functions as an output compare register ? 16tcnt1 value is transferred to gra1 by an input capture signal when gra1 functions as an input capture register 217 bit 0?nput capture/compare match flag a0 (imfa0): this status flag indicates gra0 compare match or input capture events. bit 0 imfa0 description 0 [clearing condition] (initial value) read imfa0 flag when imfa0 =1, then write 0 in imfa0 flag 1 [setting conditions] ? 16tcnt0 = gra0 when gra0 functions as an output compare register ? 16tcnt0 value is transferred to gra0 by an input capture signal when gra0 functions as an input capture register 8.2.5 timer interrupt status register b (tisrb) tisrb is an 8-bit readable/writable register that indicates grb compare match or input capture and enables or disables grb compare match and input capture interrupt requests. 7 ? 1 ? bit initial value read/write 6 imieb2 0 r/w 5 imieb1 0 r/w 4 imieb0 0 r/w 3 ? 1 ? 2 imfb2 0 r/(w)* 1 imfb1 0 r/(w)* 0 imfb0 0 r/(w)* reserved bit reserved bit input capture/compare match interrupt enable b2 to b0 these bits enable or disable interrupts by the imfb flags input capture/compare match flags b2 to b0 status flags indicating grb compare match or input capture note: * only 0 can be written, to clear the flag. tisrb is initialized to h'88 by a reset and in standby mode. 218 bit 7?eserved: this bit cannot be modified and is always read as 1. bit 6?nput capture/compare match interrupt enable b2 (imieb2): enables or disables the interrupt requested by the imfb2 when imfb2 flag is set to 1. bit 6 imieb2 description 0 imib2 interrupt requested by imfb2 flag is disabled (initial value) 1 imib2 interrupt requested by imfb2 flag is enabled bit 5?nput capture/compare match interrupt enable b1 (imieb1): enables or disables the interrupt requested by the imfb1 when imfb1 flag is set to 1. bit 5 imieb1 description 0 imib1 interrupt requested by imfb1 flag is disabled (initial value) 1 imib1 interrupt requested by imfb1 flag is enabled bit 4?nput capture/compare match interrupt enable b0 (imieb0): enables or disables the interrupt requested by the imfb0 when imfb0 flag is set to 1. bit 4 imieb0 description 0 imib0 interrupt requested by imfb0 flag is disabled (initial value) 1 imib0 interrupt requested by imfb0 flag is enabled bit 3?eserved: this bit cannot be modified and is always read as 1. bit 2?nput capture/compare match flag b2 (imfb2): this status flag indicates grb2 compare match or input capture events. bit 2 imfb2 description 0 [clearing condition] (initial value) read imfb2 flag when imfb2 =1, then write 0 in imfb2 flag 1 [setting conditions] ? 16tcnt2 = grb2 when grb2 functions as an output compare register ? 16tcnt2 value is transferred to grb2 by an input capture signal when grb2 functions as an input capture register 219 bit 1?nput capture/compare match flag b1 (imfb1): this status flag indicates grb1 compare match or input capture events. bit 1 imfb1 description 0 [clearing condition] (initial value) read imfb1 flag when imfb1 =1, then write 0 in imfb1 flag 1 [setting conditions] ? 16tcnt1 = grb1 when grb1 functions as an output compare register ? 16tcnt1 value is transferred to grb1 by an input capture signal when grb1 functions as an input capture register bit 0?nput capture/compare match flag b0 (imfb0): this status flag indicates grb0 compare match or input capture events. bit 0 imfb0 description 0 [clearing condition] (initial value) read imfb0 flag when imfb0 =1, then write 0 in imfb0 flag 1 [setting conditions] ? 16tcnt0 = grb0 when grb0 functions as an output compare register ? 16tcnt0 value is transferred to grb0 by an input capture signal when grb0 functions as an input capture register 220 8.2.6 timer interrupt status register c (tisrc) tisrc is an 8-bit readable/writable register that indicates 16tcnt overflow or underflow and enables or disables overflow interrupt requests. 7 ? 1 ? bit initial value read/write 6 ovie2 0 r/w 5 ovie1 0 r/w 4 ovie0 0 r/w 3 ? 1 ? 2 ovf2 0 r/(w)* 1 ovf1 0 r/(w)* 0 ovf0 0 r/(w)* reserved bit reserved bit overflow interrupt enable 2 to 0 these bits enable or disable interrupts by the ovf flags overflow flags 2 to 0 status flags indicating interrupts by ovf flags note: * only 0 can be written, to clear the flag. tisrc is initialized to h'88 by a reset and in standby mode. bit 7?eserved: this bit cannot be modified and is always read as 1. bit 6?verflow interrupt enable 2 (ovie2): enables or disables the interrupt requested by the ovf2 when ovf2 flag is set to 1. bit 6 ovie2 description 0 ovi2 interrupt requested by ovf2 flag is disabled (initial value) 1 ovi2 interrupt requested by ovf2 flag is enabled bit 5?verflow interrupt enable 1 (ovie1): enables or disables the interrupt requested by the ovf1 when ovf1 flag is set to 1. bit 5 ovie1 description 0 ovi1 interrupt requested by ovf1 flag is disabled (initial value) 1 ovi1 interrupt requested by ovf1 flag is enabled 221 bit 4?verflow interrupt enable 0 (ovie0): enables or disables the interrupt requested by the ovf0 when ovf0 flag is set to 1. bit 4 ovie0 description 0 ovi0 interrupt requested by ovf0 flag is disabled (initial value) 1 ovi0 interrupt requested by ovf0 flag is enabled bit 3?eserved: this bit cannot be modified and is always read as 1. bit 2?verflow flag 2 (ovf2): this status flag indicates 16tcnt2 overflow. bit 2 ovf2 description 0 [clearing condition] (initial value) read ovf2 flag when ovf2 =1, then write 0 in ovf2 flag 1 [setting condition] 16tcnt2 overflowed from h'ffff to h'0000, or underflowed from h'0000 to h'ffff note: 16tcnt underflow occurs when 16tcnt operates as an up/down-counter. underflow occurs only when channel 2 operates in phase counting mode (mdf = 1 in tmdr). bit 1?verflow flag 1 (ovf1): this status flag indicates 16tcnt1 overflow. bit 1 ovf1 description 0 [clearing condition] (initial value) read ovf1 flag when ovf1 =1, then write 0 in ovf1 flag 1 [setting condition] 16tcnt1 overflowed from h'ffff to h'0000 bit 0?verflow flag 0 (ovf0): this status flag indicates 16tcnt0 overflow. bit 0 ovf0 description 0 [clearing condition] (initial value) read ovf0 flag when ovf0 =1, then write 0 in ovf0 flag 1 [setting condition] 16tcnt0 overflowed from h'ffff to h'0000 222 8.2.7 timer counters (16tcnt) 16tcnt is a 16-bit counter. the 16-bit timer has three 16tcnts, one for each channel. channel abbreviation function 0 16tcnt0 up-counter 1 16tcnt1 2 16tcnt2 phase counting mode: up/down-counter other modes: up-counter bit initial value read/write 14 0 r/w 12 0 r/w 10 0 r/w 8 0 r/w 6 0 r/w 0 0 r/w 4 0 r/w 2 0 r/w 15 0 r/w 13 0 r/w 11 0 r/w 9 0 r/w 7 0 r/w 1 0 r/w 5 0 r/w 3 0 r/w each 16tcnt is a 16-bit readable/writable register that counts pulse inputs from a clock source. the clock source is selected by bits tpsc2 to tpsc0 in 16tcr. 16tcnt0 and 16tcnt1 are up-counters. 16tcnt2 is an up/down-counter in phase counting mode and an up-counter in other modes. 16tcnt can be cleared to h'0000 by compare match with gra or grb or by input capture to gra or grb (counter clearing function). when 16tcnt overflows (changes from h'ffff to h'0000), the ovf flag is set to 1 in tisrc of the corresponding channel. when 16tcnt underflows (changes from h'0000 to h'ffff), the ovf flag is set to 1 in tisrc of the corresponding channel. the 16tcnts are linked to the cpu by an internal 16-bit bus and can be written or read by either word access or byte access. each 16tcnt is initialized to h'0000 by a reset and in standby mode. 223 8.2.8 general registers (gra, grb) the general registers are 16-bit registers. the 16-bit timer has 6 general registers, two in each channel. channel abbreviation function 0 gra0, grb0 output compare/input capture register 1 gra1, grb1 2 gra2, grb2 bit initial value read/write 14 1 r/w 12 1 r/w 10 1 r/w 8 1 r/w 6 1 r/w 0 1 r/w 4 1 r/w 2 1 r/w 15 1 r/w 13 1 r/w 11 1 r/w 9 1 r/w 7 1 r/w 1 1 r/w 5 1 r/w 3 1 r/w a general register is a 16-bit readable/writable register that can function as either an output compare register or an input capture register. the function is selected by settings in tior. when a general register is used as an output compare register, its value is constantly compared with the 16tcnt value. when the two values match (compare match), the imfa or imfb flag is set to 1 in tisra/tisrb. compare match output can be selected in tior. when a general register is used as an input capture register, an external input capture signal are detected and the current 16tcnt value is stored in the general register. the corresponding imfa or imfb flag in tisra/tisrb is set to 1 at the same time. the edges of the input capture signal are selected in tior. tior settings are ignored in pwm mode. general registers are linked to the cpu by an internal 16-bit bus and can be written or read by either word access or byte access. general registers are set as output compare registers (with no pin output) and initialized to h'ffff by a reset and in standby mode. 224 8.2.9 timer control registers (16tcr) 16tcr is an 8-bit register. the 16-bit timer has three 16tcrs, one in each channel. channel abbreviation function 0 1 2 16tcr0 16tcr1 16tcr2 16tcr controls the timer counter. the 16tcrs in all channels are functionally identical. when phase counting mode is selected in channel 2, the settings of bits ckeg1 and ckeg0 and tpsc2 to tpsc0 in 16tcr2 are ignored. bit initial value read/write 7 ? 1 ? 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w timer prescaler 2 to 0 these bits select the timer counter clock reserved bit clock edge 1/0 these bits select external clock edges counter clear 1/0 these bits select the counter clear source each 16tcr is an 8-bit readable/writable register that selects the timer counter clock source, selects the edge or edges of external clock sources, and selects how the counter is cleared. 16tcr is initialized to h'80 by a reset and in standby mode. bit 7?eserved: this bit cannot be modified and is always read as 1. 225 bits 6 and 5?ounter clear 1 and 0 (cclr1, cclr0): these bits select how 16tcnt is cleared. bit 6 cclr1 bit 5 cclr0 description 0 0 16tcnt is not cleared (initial value) 1 16tcnt is cleared by gra compare match or input capture* 1 1 0 16tcnt is cleared by grb compare match or input capture* 1 1 synchronous clear: 16tcnt is cleared in synchronization with other synchronized timers* 2 notes: *1 16tcnt is cleared by compare match when the general register functions as an output compare register, and by input capture when the general register functions as an input capture register. *2 selected in tsnc. bits 4 and 3?lock edge 1 and 0 (ckeg1, ckeg0): these bits select external clock input edges when an external clock source is used. bit 4 ckeg1 bit 3 ckeg0 description 0 0 count rising edges (initial value) 1 count falling edges 1 ? count both edges when channel 2 is set to phase counting mode, bits ckeg1 and ckeg0 in 16tcr2 are ignored. phase counting takes precedence. bits 2 to 0?imer prescaler 2 to 0 (tpsc2 to tpsc0): these bits select the counter clock source. bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 function 0 0 0 internal clock: (initial value) 1 internal clock: /2 1 0 internal clock: /4 1 internal clock: /8 1 0 0 external clock a: tclka input 1 external clock b: tclkb input 1 0 external clock c: tclkc input 1 external clock d: tclkd input 226 when bit tpsc2 is cleared to 0 an internal clock source is selected, and the timer counts only falling edges. when bit tpsc2 is set to 1 an external clock source is selected, and the timer counts the edges selected by bits ckeg1 and ckeg0. when channel 2 is set to phase counting mode (mdf = 1 in tmdr), the settings of bits tpsc2 to tpsc0 in 16tcr2 are ignored. phase counting takes precedence. 8.2.10 timer i/o control register (tior) tior is an 8-bit register. the 16-bit timer has three tiors, one in each channel. channel abbreviation function 0 tior0 tior controls the general registers. some functions differ in pwm 1 tior1 mode. 2 tior2 bit initial value read/write 7 ? 1 ? 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ? 1 ? 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w i/o control a2 to a0 these bits select gra functions reserved bit i/o control b2 to b0 these bits select grb functions reserved bit each tior is an 8-bit readable/writable register that selects the output compare or input capture function for gra and grb, and specifies the functions of the tiora and tiorb pins. if the output compare function is selected, tior also selects the type of output. if input capture is selected, tior also selects the edges of the input capture signal. tior is initialized to h'88 by a reset and in standby mode. bit 7?eserved: this bit cannot be modified and is always read as 1. 227 bits 6 to 4?/o control b2 to b0 (iob2 to iob0): these bits select the grb function. bit 6 iob2 bit 5 iob1 bit 4 iob0 function 0 0 0 grb is an output no output at compare match (initial value) 1 compare register 0 output at grb compare match* 1 1 0 1 output at grb compare match* 1 1 output toggles at grb compare match (1 output in channel 2)* 1, * 2 1 0 0 grb is an input grb captures rising edge of input 1 compare register grb captures falling edge of input 1 0 grb captures both edges of input 1 notes: *1 after a reset, the output conforms to the tolr setting until the first compare match. *2 channel 2 output cannot be toggled by compare match. when this setting is made, 1 output is selected automatically. bit 3?eserved: this bit cannot be modified and is always read as 1. bits 2 to 0?/o control a2 to a0 (ioa2 to ioa0): these bits select the gra function. bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 function 0 0 0 gra is an output no output at compare match (initial value) 1 compare register 0 output at gra compare match* 1 1 0 1 output at gra compare match* 1 1 output toggles at gra compare match (1 output in channel 2)* 1, * 2 1 0 0 gra is an input gra captures rising edge of input 1 compare register gra captures falling edge of input 1 0 gra captures both edges of input 1 notes: *1 after a reset, the output conforms to the tolr setting until the first compare match. *2 channel 2 output cannot be toggled by compare match. when this setting is made, 1 output is selected automatically. 228 8.2.11 timer output level setting register c (tolr) tolr is an 8-bit write-only register that selects the timer output level for channels 0 to 2. 7 ? 1 ? bit initial value read/write 6 ? 1 ? 5 tob2 0 w 4 toa2 0 w 3 tob1 0 w 2 toa1 0 w 1 tob0 0 w 0 toa0 0 w reserved bits output level setting a2 to a0, b2 to b0 these bits set the levels of the timer outputs (tioca 2 to tioca 0 , and tiocb 2 to tiocb 0 ) a tolr setting can only be made when the corresponding bit in tstr is 0. tolr is a write-only register, and cannot be read. if it is read, all bits will return a value of 1. tolr is initialized to h'c0 by a reset and in standby mode. bits 7 and 6?eserved: these bits cannot be modified. bit 5?utput level setting b2 (tob2): sets the value of timer output tiocb 2 . bit 5 tob2 description 0 tiocb 2 is 0 (initial value) 1 tiocb 2 is 1 bit 4?utput level setting a2 (toa2): sets the value of timer output tioca 2 . bit 4 toa2 description 0 tioca 2 is 0 (initial value) 1 tioca 2 is 1 229 bit 3?utput level setting b1 (tob1): sets the value of timer output tiocb 1 . bit 3 tob1 description 0 tiocb 1 is 0 (initial value) 1 tiocb 1 is 1 bit 2?utput level setting a1 (toa1): sets the value of timer output tioca 1 . bit 2 toa1 description 0 tioca 1 is 0 (initial value) 1 tioca 1 is 1 bit 1?utput level setting b0 (tob0): sets the value of timer output tiocb 0 . bit 0 tob0 description 0 tiocb 0 is 0 (initial value) 1 tiocb 0 is 1 bit 0?utput level setting a0 (toa0): sets the value of timer output tioca 0 . bit 0 toa0 description 0 tioca 0 is 0 (initial value) 1 tioca 0 is 1 230 8.3 cpu interface 8.3.1 16-bit accessible registers the timer counters (16tcnts), general registers a and b (gras and grbs) are 16-bit registers, and are linked to the cpu by an internal 16-bit data bus. these registers can be written or read a word at a time, or a byte at a time. figures 8.4 and 8.5 show examples of word read/write access to a timer counter (16tcnt). figures 8.6 to 8.9 show examples of byte read/write access to 16tcnth and 16tcntl. on-chip data bus cpu h l bus interface h l module data bus 16tcnth 16tcntl figure 8.4 16tcnt access operation [cpu 16tcnt (word)] on-chip data bus cpu h l bus interface h l module data bus 16tcnth 16tcntl figure 8.5 access to timer counter (cpu reads 16tcnt, word) 231 on-chip data bus cpu h l bus interface h l module data bus 16tcnth 16tcntl figure 8.6 access to timer counter h (cpu writes to 16tcnth, upper byte) on-chip data bus cpu h l bus interface h l module data bus 16tcnth 16tcntl figure 8.7 access to timer counter l (cpu writes to 16tcntl, lower byte) on-chip data bus cpu h l bus interface h l module data bus 16tcnth 16tcntl figure 8.8 access to timer counter h (cpu reads 16tcnth, upper byte) 232 on-chip data bus cpu h l bus interface h l module data bus 16tcnth 16tcntl figure 8.9 access to timer counter l (cpu reads 16tcntl, lower byte) 8.3.2 8-bit accessible registers the registers other than the timer counters and general registers are 8-bit registers. these registers are linked to the cpu by an internal 8-bit data bus. figures 8.10 and 8.11 show examples of byte read and write access to a 16tcr. if a word-size data transfer instruction is executed, two byte transfers are performed. on-chip data bus cpu h l bus interface h l module data bus 16tcr figure 8.10 16tcr access (cpu writes to 16tcr) on-chip data bus cpu h l bus interface h l module data bus 16tcr figure 8.11 16tcr access (cpu reads 16tcr) 233 8.4 operation 8.4.1 overview a summary of operations in the various modes is given below. normal operation: each channel has a timer counter and general registers. the timer counter counts up, and can operate as a free-running counter, periodic counter, or external event counter. gra and grb can be used for input capture or output compare. synchronous operation: the timer counters in designated channels are preset synchronously. data written to the timer counter in any one of these channels is simultaneously written to the timer counters in the other channels as well. the timer counters can also be cleared synchronously if so designated by the cclr1 and cclr0 bits in the tcrs. pwm mode: a pwm waveform is output from the tioca pin. the output goes to 1 at compare match a and to 0 at compare match b. the duty cycle can be varied from 0% to 100% depending on the settings of gra and grb. when a channel is set to pwm mode, its gra and grb automatically become output compare registers. phase counting mode: the phase relationship between two clock signals input at tclka and tclkb is detected and 16tcnt2 counts up or down accordingly. when phase counting mode is selected tclka and tclkb become clock input pins and 16tcnt2 operates as an up/down- counter. 8.4.2 basic functions counter operation: when one of bits str0 to str2 is set to 1 in the timer start register (tstr), the timer counter (16tcnt) in the corresponding channel starts counting. the counting can be free-running or periodic. ? sample setup procedure for counter figure 8.12 shows a sample procedure for setting up a counter. 234 counter setup select counter clock count operation periodic counting select counter clear source select output compare register function set period start counter free-running counting start counter periodic counter free-running counter 1 ye s no 2 3 4 55 figure 8.12 counter setup procedure (example) 1. set bits tpsc2 to tpsc0 in 16tcr to select the counter clock source. if an external clock source is selected, set bits ckeg1 and ckeg0 in 16tcr to select the desired edge(s) of the external clock signal. 2. for periodic counting, set cclr1 and cclr0 in 16tcr to have 16tcnt cleared at gra compare match or grb compare match. 3. set tior to select the output compare function of gra or grb, whichever was selected in step 2. 4. write the count period in gra or grb, whichever was selected in step 2. 5. set the str bit to 1 in tstr to start the timer counter. 235 ? free-running and periodic counter operation a reset leaves the counters (16tcnts) in 16-bit timer channels 0 to 2 all set as free-running counters. a free-running counter starts counting up when the corresponding bit in tstr is set to 1. when the count overflows from h'ffff to h'0000, the ovf flag is set to 1 in tisrc. after the overflow, the counter continues counting up from h'0000. figure 8.13 illustrates free-running counting. 16tcnt value h'ffff h'0000 str0 to str2 bit ovf time figure 8.13 free-running counter operation when a channel is set to have its counter cleared by compare match, in that channel 16tcnt operates as a periodic counter. select the output compare function of gra or grb, set bit cclr1 or cclr0 in 16tcr to have the counter cleared by compare match, and set the count period in gra or grb. after these settings, the counter starts counting up as a periodic counter when the corresponding bit is set to 1 in tstr. when the count matches gra or grb, the imfa or imfb flag is set to 1 in tisra/tisrb and the counter is cleared to h'0000. if the corresponding imiea or imieb bit is set to 1 in tisra/tisrb, a cpu interrupt is requested at this time. after the compare match, 16tcnt continues counting up from h'0000. figure 8.14 illustrates periodic counting. 16tcnt value gr h'0000 str bit imf time counter cleared by general register compare match figure 8.14 periodic counter operation 236 ? 16tcnt count timing ? internal clock source bits tpsc2 to tpsc0 in 16tcr select the system clock ( ) or one of three internal clock sources obtained by prescaling the system clock ( /2, /4, /8). figure 8.15 shows the timing. internal clock 16tcnt input clock 16tcnt n e 1 n n + 1 figure 8.15 count timing for internal clock sources ? external clock source the external clock pin (tclka to tclkd) can be selected by bits tpsc2 to tpsc0 in 16tcr, and the detected edge by bits ckeg1 and ckeg0. the rising edge, falling edge, or both edges can be selected. the pulse width of the external clock signal must be at least 1.5 system clocks when a single edge is selected, and at least 2.5 system clocks when both edges are selected. shorter pulses will not be counted correctly. figure 8.16 shows the timing when both edges are detected. e xternal c lock input 1 6tcnt input c lock 1 6tcnt n e 1 n n + 1 figure 8.16 count timing for external clock sources (when both edges are detected) 237 waveform output by compare match: in 16-bit timer channels 0, 1 compare match a or b can cause the output at the tioca or tiocb pin to go to 0, go to 1, or toggle. in channel 2 the output can only go to 0 or go to 1. ? sample setup procedure for waveform output by compare match figure 8.17 shows an example of the setup procedure for waveform output by compare match. output setup select waveform output mode set output timing start counter waveform output select the compare match output mode (0, 1, or toggle) in tior. when a waveform output mode is selected, the pin switches from its generic input/ output function to the output compare function (tioca or tiocb). an output compare pin outputs the value set in tolr until the first compare match occurs. set a value in gra or grb to designate the compare match timing. set the str bit to 1 in tstr to start the timer counter. 1 2 3 1. 2. 3. figure 8.17 setup procedure for waveform output by compare match (example) 238 ? examples of waveform output figure 8.18 shows examples of 0 and 1 output. 16tcnt operates as a free-running counter, 0 output is selected for compare match a, and 1 output is selected for compare match b. when the pin is already at the selected output level, the pin level does not change. time h 'ffff g rb t iocb t ioca g ra no change no change no change no change 1 output 0 output 16tcnt value h'0000 figure 8.18 0 and 1 output (toa = 1, tob = 0) figure 8.19 shows examples of toggle output. 16tcnt operates as a periodic counter, cleared by compare match b. toggle output is selected for both compare match a and b. grb tiocb tioca gra 16tcnt value time counter cleared by compare match with grb toggle output toggle output h'0000 figure 8.19 toggle output (toa = 1, tob = 0) 239 ? output compare output timing the compare match signal is generated in the last state in which 16tcnt and the general register match (when 16tcnt changes from the matching value to the next value). when the compare match signal is generated, the output value selected in tior is output at the output compare pin (tioca or tiocb). when 16tcnt matches a general register, the compare match signal is not generated until the next counter clock pulse. figure 8.20 shows the output compare timing. n + 1 n n 16tcnt input clock 16tcnt gr compare match signal tioca, tiocb figure 8.20 output compare output timing input capture function: the 16tcnt value can be transferred to a general register when an input edge is detected at an input capture input/output compare pin (tioca or tiocb). rising- edge, falling-edge, or both-edge detection can be selected. the input capture function can be used to measure pulse width or period. 240 ? sample setup procedure for input capture figure 8.21 shows a sample procedure for setting up input capture. input selection select input-capture input start counter input capture set tior to select the input capture function of a general register and the rising edge, falling edge, or both edges of the input capture signal. clear the ddr bit to 0 before making these tior settings. set the str bit to 1 in tstr to start the timer counter. 1 2 1. 2. figure 8.21 setup procedure for input capture (example) ? examples of input capture figure 8.22 illustrates input capture when the falling edge of tiocb and both edges of tioca are selected as capture edges. 16tcnt is cleared by input capture into grb. h'0005 h'0180 h'0180 h'0160 h'0005 h'0000 tiocb tioca gra grb 16tcnt value h'0160 figure 8.22 input capture (example) 241 ? input capture signal timing input capture on the rising edge, falling edge, or both edges can be selected by settings in tior. figure 8.23 shows the timing when the rising edge is selected. the pulse width of the input capture signal must be at least 1.5 system clocks for single-edge capture, and 2.5 system clocks for capture of both edges. n n input-capture input input capture signal 16tcnt gra, grb figure 8.23 input capture signal timing 8.4.3 synchronization the synchronization function enables two or more timer counters to be synchronized by writing the same data to them simultaneously (synchronous preset). with appropriate 16tcr settings, two or more timer counters can also be cleared simultaneously (synchronous clear). synchronization enables additional general registers to be associated with a single time base. synchronization can be selected for all channels (0 to 2). sample setup procedure for synchronization: figure 8.24 shows a sample procedure for setting up synchronization. 242 setup for synchronization synchronous preset set the sync bits to 1 in tsnc for the channels to be synchronized. when a value is written in 16tcnt in one of the synchronized channels, the same value is simultaneously written in 16tcnt in the other channels. set the cclr1 or cclr0 bit in 16tcr to have the counter cleared by compare match or input capture. set the cclr1 and cclr0 bits in 16tcr to have the counter cleared synchronously. set the str bits in tstr to 1 to start the synchronized counters. 1. 2. 3. 4. 5. 2 3 1 5 4 5 select synchronization synchronous preset write to 16tcnt synchronous clear clearing synchronized to this channel? select counter clear source start counter counter clear synchronous clear start counter select counter clear source ye s no figure 8.24 setup procedure for synchronization (example) example of synchronization: figure 8.25 shows an example of synchronization. channels 0, 1, and 2 are synchronized, and are set to operate in pwm mode. channel 0 is set for counter clearing by compare match with grb0. channels 1 and 2 are set for synchronous counter clearing. the timer counters in channels 0, 1, and 2 are synchronously preset, and are synchronously cleared by compare match with grb0. a three-phase pwm waveform is output from pins tioca 0 , tioca 1 , and tioca 2 . for further information on pwm mode, see section 8.4.4, pwm mode. 243 tioca 2 tioca 1 tioca 0 gra2 gra1 grb2 gra0 grb1 grb0 value of 16tcnt0 to 16tcnt2 cleared by compare match with grb0 h'0000 figure 8.25 synchronization (example) 8.4.4 pwm mode in pwm mode gra and grb are paired and a pwm waveform is output from the tioca pin. gra specifies the time at which the pwm output changes to 1. grb specifies the time at which the pwm output changes to 0. if either gra or grb compare match is selected as the counter clear source, a pwm waveform with a duty cycle from 0% to 100% is output at the tioca pin. pwm mode can be selected in all channels (0 to 2). table 8.4 summarizes the pwm output pins and corresponding registers. if the same value is set in gra and grb, the output does not change when compare match occurs. table 8.4 pwm output pins and registers channel output pin 1 output 0 output 0 tioca 0 gra0 grb0 1 tioca 1 gra1 grb1 2 tioca 2 gra2 grb2 244 sample setup procedure for pwm mode: figure 8.26 shows a sample procedure for setting up pwm mode. pwm mode 1. 2. 3. 4. 5. 6. set bits tpsc2 to tpsc0 in 16tcr to select the counter clock source. if an external clock source is selected, set bits ckeg1 and ckeg0 in 16tcr to select the desired edge(s) of the external clock signal. set bits cclr1 and cclr0 in 16tcr to select the counter clear source. set the time at which the pwm waveform should go to 1 in gra. set the time at which the pwm waveform should go to 0 in grb. set the pwm bit in tmdr to select pwm mode. when pwm mode is selected, regardless of the tior contents, gra and grb become output compare registers specifying the times at which the pwm output goes to 1 and 0. the tioca pin automatically becomes the pwm output pin. the tiocb pin conforms to the settings of bits iob1 and iob0 in tior. if tiocb output is not desired, clear both iob1 and iob0 to 0. set the str bit to 1 in tstr to start the timer counter. pwm mode select counter clock 1 select counter clear source 2 set gra 3 set grb 4 select pwm mode 5 start counter 6 figure 8.26 setup procedure for pwm mode (example) 245 examples of pwm mode: figure 8.27 shows examples of operation in pwm mode. in pwm mode tioca becomes an output pin. the output goes to 1 at compare match with gra, and to 0 at compare match with grb. in the examples shown, 16tcnt is cleared by compare match with gra or grb. synchronized operation and free-running counting are also possible. 16tcnt value counter cleared by compare match a time gra grb tioca a. counter cleared by gra (toa = 1) 16tcnt value counter cleared by compare match b time grb gra tioca b. counter cleared by grb (toa = 0) h'0000 h'0000 figure 8.27 pwm mode (example 1) 246 figure 8.28 shows examples of the output of pwm waveforms with duty cycles of 0% and 100%. if the counter is cleared by compare match with grb, and gra is set to a higher value than grb, the duty cycle is 0%. if the counter is cleared by compare match with gra, and grb is set to a higher value than gra, the duty cycle is 100%. 16tcnt value counter cleared by compare match b time grb gra tioca a. 0% duty cycle (toa=0) 16tcnt value counter cleared by compare match a time gra grb tioca b. 100% duty cycle (toa=1) write to gra write to gra write to grb write to grb h'0000 h'0000 figure 8.28 pwm mode (example 2) 247 8.4.5 phase counting mode in phase counting mode the phase difference between two external clock inputs (at the tclka and tclkb pins) is detected, and 16tcnt2 counts up or down accordingly. in phase counting mode, the tclka and tclkb pins automatically function as external clock input pins and 16tcnt2 becomes an up/down-counter, regardless of the settings of bits tpsc2 to tpsc0, ckeg1, and ckeg0 in 16tcr2. settings of bits cclr1, cclr0 in 16tcr2, and settings in tior2, tisra, tisrb, tisrc, setting of str2 bit in tstr, gra2, and grb2 are valid. the input capture and output compare functions can be used, and interrupts can be generated. phase counting is available only in channel 2. sample setup procedure for phase counting mode: figure 8.29 shows a sample procedure for setting up phase counting mode. phase counting mode select phase counting mode select flag setting condition start counter 1 2 3 phase counting mode 1. 2. 3. set the mdf bit in tmdr to 1 to select phase counting mode. select the flag setting condition with the fdir bit in tmdr. set the str2 bit to 1 in tstr to start the timer counter. figure 8.29 setup procedure for phase counting mode (example) 248 example of phase counting mode: figure 8.30 shows an example of operations in phase counting mode. table 8.5 lists the up-counting and down-counting conditions for 16tcnt2. in phase counting mode both the rising and falling edges of tclka and tclkb are counted. the phase difference between tclka and tclkb must be at least 1.5 states, the phase overlap must also be at least 1.5 states, and the pulse width must be at least 2.5 states. 16tcnt2 value counting up counting down tclkb tclka figure 8.30 operation in phase counting mode (example) table 8.5 up/down counting conditions counting direction up-counting down-counting tclkb pin high high low low tclka pin low high high low t clka t clkb phase difference phase difference pulse width pulse width overlap overlap phase difference and overlap: pulse width: at least 1.5 states at least 2.5 states figure 8.31 phase difference, overlap, and pulse width in phase counting mode 249 8.4.6 16-bit timer output timing the initial value of 16-bit timer output when a timer count operation begins can be specified arbitrarily by making a setting in tolr. figure 8.32 shows the timing for setting the initial value with tolr. only write to tolr when the corresponding bit in tstr is cleared to 0. t 1 tolr address n n t 2 t 3 address bus tolr 16-bit timer output pin figure 8.32 timing for setting 16-bit timer output level by writing to tolr 250 8.5 interrupts the 16-bit timer has two types of interrupts: input capture/compare match interrupts, and overflow interrupts. 8.5.1 setting of status flags timing of setting of imfa and imfb at compare match: imfa and imfb are set to 1 by a compare match signal generated when 16tcnt matches a general register (gr). the compare match signal is generated in the last state in which the values match (when 16tcnt is updated from the matching count to the next count). therefore, when 16tcnt matches a general register, the compare match signal is not generated until the next 16tcnt clock input. figure 8.33 shows the timing of the setting of imfa and imfb. 16tcnt gr imf imi 16tcnt input clock compare match signal n n + 1 n figure 8.33 timing of setting of imfa and imfb by compare match 251 timing of setting of imfa and imfb by input capture: imfa and imfb are set to 1 by an input capture signal. the 16tcnt contents are simultaneously transferred to the corresponding general register. figure 8.34 shows the timing. input capture signal n n imf 16tcnt gr imi figure 8.34 timing of setting of imfa and imfb by input capture 252 timing of setting of overflow flag (ovf): ovf is set to 1 when 16tcnt overflows from h'ffff to h'0000 or underflows from h'0000 to h'ffff. figure 8.35 shows the timing. overflow signal 16tcnt ovf ovi figure 8.35 timing of setting of ovf 8.5.2 timing of clearing of status flags if the cpu reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is cleared. figure 8.36 shows the timing. a ddress i mf, ovf tisr write cycle tisr address t 1 t 2 t 3 figure 8.36 timing of clearing of status flags 253 8.5.3 interrupt sources each 16-bit timer channel can generate a compare match/input capture a interrupt, a compare match/input capture b interrupt, and an overflow interrupt. in total there are nine interrupt sources of three kinds, all independently vectored. an interrupt is requested when the interrupt request flag are set to 1. the priority order of the channels can be modified in interrupt priority registers a (ipra). for details see section 5, interrupt controller. table 8.6 lists the interrupt sources. table 8.6 16-bit timer interrupt sources channel interrupt source description priority* 0 imia0 imib0 ovi0 compare match/input capture a0 compare match/input capture b0 overflow 0 high 1 imia1 imib1 ovi1 compare match/input capture a1 compare match/input capture b1 overflow 1 2 imia2 imib2 ovi2 compare match/input capture a2 compare match/input capture b2 overflow 2 low note: * the priority immediately after a reset is indicated. inter-channel priorities can be changed by settings in ipra. 254 8.6 usage notes this section describes contention and other matters requiring special attention during 16-bit timer operations. contention between 16tcnt write and clear: if a counter clear signal occurs in the t 3 state of a 16tcnt write cycle, clearing of the counter takes priority and the write is not performed. see figure 8.37. address bus internal write signal counter clear signal 16tcnt 16tcnt write cycle 16tcnt address n h'0000 t 1 t 2 t 3 figure 8.37 contention between 16tcnt write and clear 255 contention between 16tcnt word write and increment: if an increment pulse occurs in the t 3 state of a 16tcnt word write cycle, writing takes priority and 16tcnt is not incremented. figure 8.38 shows the timing in this case. address bus internal write signal 16tcnt input clock 16tcnt n 16tcnt address m 16tcnt write data 16tcnt word write cycle t 1 t 2 t 3 figure 8.38 contention between 16tcnt word write and increment 256 contention between 16tcnt byte write and increment: if an increment pulse occurs in the t 2 or t 3 state of a 16tcnt byte write cycle, writing takes priority and 16tcnt is not incremented. the byte data for which a write was not performed is not incremented, and retains its pre-write value. see figure 8.39, which shows an increment pulse occurring in the t 2 state of a byte write to 16tcnth. address bus internal write signal 16tcnt input clock 16tcnth 16tcntl 16tcnth byte write cycle t 1 t 2 t 3 n 16tcnth address m 16tcnt write data xx x + 1 figure 8.39 contention between 16tcnt byte write and increment 257 contention between general register write and compare match: if a compare match occurs in the t 3 state of a general register write cycle, writing takes priority and the compare match signal is inhibited. see figure 8.40. address bus internal write signal 16tcnt gr compare match signal general register write cycle t 1 t 2 t 3 n gr address m n n + 1 general register write data inhibited figure 8.40 contention between general register write and compare match 258 contention between 16tcnt write and overflow or underflow: if an overflow occurs in the t 3 state of a 16tcnt write cycle, writing takes priority and the counter is not incremented. ovf is set to 1.the same holds for underflow. see figure 8.41. address bus internal write signal 16tcnt input clock overflow signal 16tcnt ovf h'ffff 16tcnt address m 16tcnt write data 16tcnt write cycle t 1 t 2 t 3 figure 8.41 contention between 16tcnt write and overflow 259 contention between general register read and input capture: if an input capture signal occurs during the t 3 state of a general register read cycle, the value before input capture is read. see figure 8.42. address bus internal read signal input capture signal gr internal data bus gr address x general register read cycle t 1 t 2 t 3 xm figure 8.42 contention between general register read and input capture 260 contention between counter clearing by input capture and counter increment: if an input capture signal and counter increment signal occur simultaneously, the counter is cleared according to the input capture signal. the counter is not incremented by the increment signal. the value before the counter is cleared is transferred to the general register. see figure 8.43. input capture signal counter clear signal 16tcnt input clock 16tcnt gr n n h'0000 figure 8.43 contention between counter clearing by input capture and counter increment 261 contention between general register write and input capture: if an input capture signal occurs in the t 3 state of a general register write cycle, input capture takes priority and the write to the general register is not performed. see figure 8.44. address bus internal write signal input capture signal 16tcnt gr m gr address general register write cycle t 1 t 2 t 3 m figure 8.44 contention between general register write and input capture 262 note on waveform period setting: when a counter is cleared by compare match, the counter is cleared in the last state at which the 16tcnt value matches the general register value, at the time when this value would normally be updated to the next count. the actual counter frequency is therefore given by the following formula: f = (n+1) (f: counter frequency. : system clock frequency. n: value set in general register.) note on writes in synchronized operation: when channels are synchronized, if a 16tcnt value is modified by byte write access, all 16 bits of all synchronized counters assume the same value as the counter that was addressed. (example) when channels 1 and 2 are synchronized byte write to channel 1 or byte write to channel 2 16tcnt1 16tcnt2 w y x z 16tcnt1 16tcnt2 a a x x 16tcnt1 16tcnt2 y y a a 16tcnt1 16tcnt2 w y x z 16tcnt1 16tcnt2 a a b b word write to channel 1 or word write to channel 2 upper byte lower byte upper byte lower byte upper byte lower byte upper byte lower byte upper byte lower byte write a to upper byte of channel 1 write a to lower byte of channel 2 write ab word to channel 1 or 2 263 16-bit timer operating modes table 8.7 (a) 16-bit timer operating modes (channel 0) register settings tsnc tmdr tior0 16tcr0 synchro- clear clock operating mode nization mdf fdir pwm ioa iob select select synchronous preset sync0 = 1 ?? pwm mode ?? pwm0 = 1 ? * output compare a ?? pwm0 = 0 ioa2 = 0 other bits unrestricted output compare b ?? iob2 = 0 other bits unrestricted input capture a ?? pwm0 = 0 ioa2 = 1 other bits unrestricted input capture b ?? pwm0 = 0 iob2 = 1 other bits unrestricted counter by compare ?? cclr1 = 0 clearing match/input cclr0 = 1 capture a by compare ?? cclr1 = 1 match/input cclr0 = 0 capture b syn- sync0 = 1 ?? cclr1 = 1 chronous cclr0 = 1 clear legend: setting available (valid). ? setting does not affect this mode. note: * the input capture function cannot be used in pwm mode. if compare match a and compare match b occur simultaneously, the compare match signal is inhibited. 264 table 8.7 (b) 16-bit timer operating modes (channel 1) register settings tsnc tmdr tior1 16tcr1 synchro- clear clock operating mode nization mdf fdir pwm ioa iob select select synchronous preset sync1 = 1 ?? pwm mode ?? pwm1 = 1 ? output compare a ?? pwm1 = 0 ioa2 = 0 other bits unrestricted output compare b ?? iob2 = 0 other bits unrestricted input capture a ?? pwm1 = 0 ioa2 = 1 other bits unrestricted input capture b ?? pwm1 = 0 iob2 = 1 other bits unrestricted counter by compare ?? cclr1 = 0 clearing match/input cclr0 = 1 capture a by compare ?? cclr1 = 1 match/input cclr0 = 0 capture b syn- sync1 = 1 ?? cclr1 = 1 chronous cclr0 = 1 clear legend: setting available (valid). ? setting does not affect this mode. note: the input capture function cannot be used in pwm mode. if compare match a and compare match b occur simultaneously, the compare match signal is inhibited. * * 265 table 8.7 (c) 16-bit timer operating modes (channel 2) register settings tsnc tmdr tior2 16tcr2 synchro- clear clock operating mode nization mdf fdir pwm ioa iob select select synchronous preset sync2 = 1 ? pwm mode ? pwm2 = 1 ? * output compare a ? pwm2 = 0 ioa2 = 0 other bits unrestricted output compare b ? iob2 = 0 other bits unrestricted input capture a ? pwm2 = 0 ioa2 = 1 other bits unrestricted input capture b ? pwm2 = 0 iob2 = 1 other bits unrestricted counter by compare ? cclr1 = 0 clearing match/input cclr0 = 1 capture a by compare ? cclr1 = 1 match/input cclr0 = 0 capture b syn- sync2 = 1 ? cclr1 = 1 chronous cclr0 = 1 clear phase counting mdf = 1 ? mode legend: setting available (valid). ? setting does not affect this mode. note: * the input capture function cannot be used in pwm mode. if compare match a and compare match b occur simultaneously, the compare match signal is inhibited. 266 267 section 9 8-bit timers 9.1 overview the h8/3024 series has a built-in 8-bit timer module with four channels (tmr0, tmr1, tmr2, and tmr3), based on 8-bit counters. each channel has an 8-bit timer counter (8tcnt) and two 8-bit time constant registers (tcora and tcorb) that are constantly compared with the 8tcnt value to detect compare match events. the timers can be used as multifunctional timers in a variety of applications, including the generation of a rectangular-wave output with an arbitrary duty cycle. 9.1.1 features the features of the 8-bit timer module are listed below. ? selection of four clock sources the counters can be driven by one of three internal clock signals ( /8, /64, or /8192) or an external clock input (enabling use as an external event counter). ? selection of three ways to clear the counters the counters can be cleared on compare match a or b, or input capture b. ? timer output controlled by two compare match signals the timer output signal in each channel is controlled by two independent compare match signals, enabling the timer to generate output waveforms with an arbitrary duty cycle or pwm output. ? a/d converter can be activated by a compare match ? two channels can be cascaded ? channels 0 and 1 can be operated as the upper and lower halves of a 16-bit timer (16-bit count mode). ? channels 2 and 3 can be operated as the upper and lower halves of a 16-bit timer (16-bit count mode). ? channel 1 can count channel 0 compare match events (compare match count mode). ? channel 3 can count channel 2 compare match events (compare match count mode). ? input capture function can be set 8-bit or 16-bit input capture operation is available. 268 ? twelve interrupt sources there are twelve interrupt sources: four compare match sources, four compare match/input capture sources, four overflow sources. two of the compare match sources and two of the combined compare match/input capture sources each have an independent interrupt vector. the remaining compare match interrupts, combined compare match/input capture interrupts, and overflow interrupts have one interrupt vector for two sources. 269 9.1.2 block diagram the 8-bit timers are divided into two groups of two channels each: group 0 comprising channels 0 and 1, and group 1 comprising channels 2 and 3. figure 9.1 shows a block diagram of 8-bit timer group 0. figure 9.1 block diagram of 8-bit timer unit (two channels: group 0) 270 9.1.3 pin configuration table 9.1 summarizes the input/output pins of the 8-bit timer module. table 9.1 8-bit timer pins group channel name abbreviation i/o function 0 0 timer output tmo 0 output compare match output timer clock input tclkc input counter external clock input 1 timer input/output tmio 1 i/o compare match output/input capture input timer clock input tclka input counter external clock input 1 2 timer output tmo 2 output compare match output timer clock input tclkd input counter external clock input 3 timer input/output tmio 3 i/o compare match output/input capture input timer clock input tclkb input counter external clock input 271 9.1.4 register configuration table 9.2 summarizes the registers of the 8-bit timer module. table 9.2 8-bit timer registers channel address* 1 name abbreviation r/w initial value 0 h'fff80 timer control register 0 8tcr0 r/w h'00 h'fff82 timer control/status register 0 8tcsr0 r/(w)* 2 h'00 h'fff84 time constant register a0 tcora0 r/w h'ff h'fff86 time constant register b0 tcorb0 r/w h'ff h'fff88 timer counter 0 8tcnt0 r/w h'00 1 h'fff81 timer control register 1 8tcr1 r/w h'00 h'fff83 timer control/status register 1 8tcsr1 r/(w)* 2 h'00 h'fff85 time constant register a1 tcora1 r/w h'ff h'fff87 time constant register b1 tcorb1 r/w h'ff h'fff89 timer counter 1 8tcnt1 r/w h'00 2 h'fff90 timer control register 2 8tcr2 r/w h'00 h'fff92 timer control/status register 2 8tcsr2 r/(w)* 2 h'10 h'fff94 time constant register a2 tcora2 r/w h'ff h'fff96 time constant register b2 tcorb2 r/w h'ff h'fff98 timer counter 2 8tcnt2 r/w h'00 3 h'fff91 timer control register 3 8tcr3 r/w h'00 h'fff93 timer control/status register 3 8tcsr3 r/(w)* 2 h'00 h'fff95 time constant register a3 tcora3 r/w h'ff h'fff97 time constant register b3 tcorb3 r/w h'ff h'fff99 timer counter 3 8tcnt3 r/w h'00 notes: *1 indicates the lower 20 bits of the address in advanced mode. *2 only 0 can be written to bits 7 to 5, to clear these flags. each pair of registers for channel 0 and channel 1 comprises a 16-bit register with the channel 0 register as the upper 8 bits and the channel 1 register as the lower 8 bits, so they can be accessed together by word access. similarly, each pair of registers for channel 2 and channel 3 comprises a 16-bit register with the channel 2 register as the upper 8 bits and the channel 3 register as the lower 8 bits, so they can be accessed together by word access. 272 9.2 register descriptions 9.2.1 timer counters (8tcnt) 15 0 r/w bit initial value read/write 14 0 r/w bit initial value read/write 13 0 r/w 12 0 r/w 11 0 r/w 10 0 r/w 9 0 r/w 8 0 r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w 8tcnt0 8tcnt1 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 10 0 r/w 9 0 r/w 8 0 r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w 8tcnt2 8tcnt3 the timer counters (8tcnt) are 8-bit readable/writable up-counters that increment on pulses generated from an internal or external clock source. the clock source is selected by clock select bits 2 to 0 (cks2 to cks0) in the timer control register (8tcr). the cpu can always read or write to the timer counters. the 8tcnt0 and 8tcnt1 pair, and the 8tcnt2 and 8tcnt3 pair, can each be accessed as a 16-bit register by word access. 8tcnt can be cleared by an input capture signal or compare match signal. counter clear bits 1 and 0 (cclr1 and cclr0) in 8tcr select the method of clearing. when 8tcnt overflows from h'ff to h'00, the overflow flag (ovf) in the timer control/status register (8tcsr) is set to 1. each 8tcnt is initialized to h'00 by a reset and in standby mode. 273 9.2.2 time constant registers a (tcora) tcora0 to tcora3 are 8-bit readable/writable registers. 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w tcora0 tcora1 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w tcora2 tcora3 bit initial value read/write bit initial value read/write the tcora0 and tcora1 pair, and the tcora2 and tcora3 pair, can each be accessed as a 16-bit register by word access. the tcora value is constantly compared with the 8tcnt value. when a match is detected, the corresponding compare match flag a (cmfa) is set to 1 in 8tcsr. the timer output can be freely controlled by these compare match signals and the settings of output select bits 1 and 0 (os1, os0) in 8tcsr. each tcora register is initialized to h'ff by a reset and in standby mode. 274 9.2.3 time constant registers b (tcorb) 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w tcorb0 tcorb1 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w tcorb2 tcorb3 bit initial value read/write bit initial value read/write tcorb0 to tcorb3 are 8-bit readable/writable registers. the tcorb0 and tcorb1 pair, and the tcorb2 and tcorb3 pair, can each be accessed as a 16-bit register by word access. the tcorb value is constantly compared with the 8tcnt value. when a match is detected, the corresponding compare match flag b (cmfb) is set to 1 in 8tcsr*. the timer output can be freely controlled by these compare match signals and the settings of output/input capture edge select bits 3 and 2 (ois3, ois2) in 8tcsr. when tcorb is used for input capture, it stores the 8tcnt value on detection of an external input capture signal. at this time, the cmfb flag is set to 1 in the corresponding 8tcsr register. the detected edge of the input capture signal is set in 8tcsr. each tcorb register is initialized to h'ff by a reset and in standby mode. note: * when channel 1 and channel 3 are designated for tcorb input capture, the cmfb flag is not set by a channel 0 or channel 2 compare match b. 275 9.2.4 timer control register (8tcr) 7 cmieb 0 r/w 6 cmiea 0 r/w 5 ovie 0 r/w 4 cclr1 0 r/w 3 cclr0 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w bit initial value read/write 8tcr is an 8-bit readable/writable register that selects the 8tcnt input clock, gives the 8tcnt clearing specification, and enables interrupt requests. 8tcr is initialized to h'00 by a reset and in standby mode. for the timing, see section 9.4, operation. bit 7?ompare match interrupt enable b (cmieb): enables or disables the cmib interrupt request when the cmfb flag is set to 1 in 8tcsr. bit 7 cmieb description 0 cmib interrupt requested by cmfb is disabled (initial value) 1 cmib interrupt requested by cmfb is enabled bit 6?ompare match interrupt enable a (cmiea): enables or disables the cmia interrupt request when the cmfa flag is set to 1 in 8tcsr. bit 6 cmiea description 0 cmia interrupt requested by cmfa is disabled (initial value) 1 cmia interrupt requested by cmfa is enabled bit 5?imer overflow interrupt enable (ovie): enables or disables the ovi interrupt request when the ovf flag is set to 1 in 8tcsr. bit 5 ovie description 0 ovi interrupt requested by ovf is disabled (initial value) 1 ovi interrupt requested by ovf is enabled 276 bits 4 and 3?ounter clear 1 and 0 (cclr1, cclr0): these bits specify the 8tcnt clearing source. compare match a or b, or input capture b, can be selected as the clearing source. bit 4 cclr1 bit 3 cclr0 description 0 0 clearing is disabled (initial value) 1 cleared by compare match a 1 0 cleared by compare match b/input capture b 1 cleared by input capture b note: when input capture b is set as the 8tcnt1 and 8tcnt3 counter clear source, 8tcnt0 and 8tcnt2 are not cleared by compare match b. bits 2 to 0?lock select 2 to 0 (csk2 to csk0): these bits select whether the clock input to 8tcnt is an internal or external clock. three internal clocks can be selected, all divided from the system clock ( ): /8, /64, and /8192. the rising edge of the selected internal clock triggers the count. when use of an external clock is selected, three types of count can be selected: at the rising edge, the falling edge, and both rising and falling edges. when cks2, cks1, cks0 = 1, 0, 0, channels 0 and 1 and channels 2 and 3 are cascaded. the incrementing clock source is different when 8tcr0 and 8tcr2 are set, and when 8tcr1 and 8tcr3 are set. 277 bit 2 csk2 bit 1 csk1 bit 0 csk0 description 0 0 0 clock input disabled (initial value) 1 internal clock, counted on falling edge of 278 9.2.5 timer control/status registers (8tcsr) 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/(w) * 4 ? 1 ? 3 ois3 0 r/w 0 os0 0 r/w 2 ois2 0 r/w 1 os1 0 r/w 8tcsr2 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/(w) * 4 0 r/w 3 ois3 0 r/w 0 os0 0 r/w 2 ois2 0 r/w 1 os1 0 r/w 8tcsr0 adte bit initial value read/write bit initial value read/write 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/(w) * 4 ice 0 r/w 3 ois3 0 r/w 0 os0 0 r/w 2 ois2 0 r/w 1 os1 0 r/w 8tcsr1, 8tcsr3 note: * only 0 can be written to bits 7 to 5, to clear these flags. bit initial value read/write the timer control/status registers 8tcsr are 8-bit registers that indicate compare match/input capture and overflow statuses, and control compare match output/input capture edge selection. 8tcsr2 is initialized to h'10, and 8tcsr0, 8tcsr1, and 8tcsr3 to h'00, by a reset and in standby mode. 279 bit 7?ompare match/input capture flag b (cmfb): status flag that indicates the occurrence of a tcorb compare match or input capture. bit 7 cmfb description 0 [clearing condition] (initial value) read cmfb when cmfb = 1, then write 0 in cmfb 1 [setting conditions] ? ? bit 6?ompare match flag a (cmfa): status flag that indicates the occurrence of a tcora compare match. bit 6 cmfa description 0 [clearing condition] (initial value) read cmfa when cmfa = 1, then write 0 in cmfa 1 [setting condition] 8tcnt = tcora bit 5?imer overflow flag (ovf): status flag that indicates that the 8tcnt has overflowed from h'ff to h'00. bit 5 ovf description 0 [clearing condition] (initial value) read ovf when ovf = 1, then write 0 in ovf 1 [setting condition] 8tcnt overflows from h'ff to h'00 280 bit 4?/d trigger enable (adte) (in 8tcsr0): in combination with trge in the a/d control register (adcr), enables or disables a/d converter start requests by compare match a or an external trigger. trge* bit 4 adte description 0 0 a/d converter start requests by compare match a or external trigger pin ( adtrg adtrg adtrg adtrg bit 4?eserved (in 8tcsr1): this bit is a reserved bit, but can be read and written. bit 4?nput capture enable (ice) (in 8tcsr1 and 8tcsr3): selects the function of tcorb1 and tcorb3. bit 4 ice description 0 tcorb1 and tcorb3 are compare match registers (initial value) 1 tcorb1 and tcorb3 are input capture registers when bit ice is set to 1 in 8tcsr1 or 8tcsr3, the operation of the tcora and tcorb registers in channels 0 to 3 is as shown in the tables below. 281 table 9.3 operation of channels 0 and 1 when bit ice is set to 1 in 8tcsr1 register register register function status flag change timer output capture input interrupt request tcora0 compare match operation cmfa changed from 0 to 1 in 8tcsr0 by compare match tmo 0 output controllable cmia0 interrupt request generated by compare match tcorb0 compare match operation cmfb not changed from 0 to 1 in 8tcsr0 by compare match no output from tmo 0 cmib0 interrupt request not generated by compare match tcora1 compare match operation cmfa changed from 0 to 1 in 8tcsr1 by compare match tmio 1 is dedicated input capture pin cmia1 interrupt request generated by compare match tcorb1 input capture operation cmfb changed from 0 to 1 in 8tcsr1 by input capture tmio 1 is dedicated input capture pin cmib1 interrupt request generated by input capture table 9.4 operation of channels 2 and 3 when bit ice is set to 1 in 8tcsr3 register register register function status flag change timer output capture input interrupt request tcora2 compare match operation cmfa changed from 0 to 1 in 8tcsr2 by compare match tmo 2 output controllable cmia2 interrupt request generated by compare match tcorb2 compare match operation cmfb not changed from 0 to 1 in 8tcsr2 by compare match no output from tmo 2 cmib2 interrupt request not generated by compare match tcora3 compare match operation cmfa changed from 0 to 1 in 8tcsr3 by compare match tmio 3 is dedicated input capture pin cmia3 interrupt request generated by compare match tcorb3 input capture operation cmfb changed from 0 to 1 in 8tcsr3 by input capture tmio 3 is dedicated input capture pin cmib3 interrupt request generated by input capture 282 bits 3 and 2?utput/input capture edge select b3 and b2 (ois3, ois2): in combination with the ice bit in 8tcsr1 (8tcsr3), these bits select the compare match b output level or the input capture input detected edge. the function of tcorb1 (tcorb3) depends on the setting of bit 4 of 8tcsr1 (8tcsr3). ice bit in 8tcsr1 (8tcsr3) bit 3 ois3 bit 2 ois2 description 0 0 0 no change when compare match b occurs (initial value) 1 0 is output when compare match b occurs 1 0 1 is output when compare match b occurs 1 output is inverted when compare match b occurs (toggle output) 1 0 0 tcorb input capture on rising edge 1 tcorb input capture on falling edge 1 0 tcorb input capture on both rising and falling edges 1 ? when the compare match register function is used, the timer output priority order is: toggle output > 1 output > 0 output. ? if compare match a and b occur simultaneously, the output changes in accordance with the higher-priority compare match. ? when bits ois3, ois2, os1, and os0 are all cleared to 0, timer output is disabled. bits 1 and 0?utput select a1 and a0 (os1, os0): these bits select the compare match a output level. bit 1 os1 bit 0 os0 description 0 0 no change when compare match a occurs (initial value) 1 0 is output when compare match a occurs 1 0 1 is output when compare match a occurs 1 output is inverted when compare match a occurs (toggle output) ? when the compare match register function is used, the timer output priority order is: toggle output > 1 output > 0 output. ? if compare match a and b occur simultaneously, the output changes in accordance with the higher-priority compare match. ? when bits ois3, ois2, os1, and os0 are all cleared to 0, timer output is disabled. 283 9.3 cpu interface 9.3.1 8-bit registers 8tcnt, tcora, tcorb, 8tcr, and 8tcsr are 8-bit registers. these registers are connected to the cpu by an internal 16-bit data bus and can be read and written a word at a time or a byte at a time. figures 9.2 and 9.3 show the operation in word read and write accesses to 8tcnt. figures 9.4 to 9.7 show the operation in byte read and write accesses to 8tcnt0 and 8tcnt1. 8tcnt0 8tcnt1 h l h l c p u internal data bus bus interface module data bus figure 9.2 8tcnt access operation (cpu writes to 8tcnt, word) 8tcnt0 8tcnt1 h l h l c p u internal data bus bus interface module data bus figure 9.3 8tcnt access operation (cpu reads 8tcnt, word) 8tcnth0 8tcntl1 h l h l c p u internal data bus bus interface module data bus figure 9.4 8tcnt0 access operation (cpu writes to 8tcnt0, upper byte) 284 8tcnth0 8tcntl1 h l h l c p u internal data bus bus interface module data bus figure 9.5 8tcnt1 access operation (cpu writes to 8tcnt1, lower byte) 8tcnt0 8tcnt1 h l h l c p u internal data bus bus interface module data bus figure 9.6 8tcnt0 access operation (cpu reads 8tcnt0, upper byte) 8tcnt0 8tcnt1 h l h l c p u internal data bus bus interface module data bus figure 9.7 8tcnt1 access operation (cpu reads 8tcnt1, lower byte) 285 9.4 operation 9.4.1 8tcnt count timing 8tcnt is incremented by input clock pulses (either internal or external). internal clock: three different internal clock signals ( /8, /64, or /8192) divided from the system clock ( ) can be selected, by setting bits cks2 to cks0 in 8tcr. figure 9.8 shows the count timing. 8tcnt n e 1 n n+1 internal clock 8tcnt input clock note: even if the same internal clock is selected for the 16-bit timer and the 8-bit timer, the same operation will not be performed since the incrementing edge is different in each case. figure 9.8 count timing for internal clock input external clock: three incrementation methods can be selected by setting bits cks2 to cks0 in 8tcr: on the rising edge, the falling edge, and both rising and falling edges. the pulse width of the external clock signal must be at least 1.5 system clocks when a single edge is selected, and at least 2.5 system clocks when both edges are selected. shorter pulses will not be counted correctly. figure 9.9 shows the timing for incrementation on both edges of the external clock signal. 286 8tcnt n e 1 n n+1 external clock input 8tcnt input clock figure 9.9 count timing for external clock input (both-edge detection) 9.4.2 compare match timing timer output timing: when compare match a or b occurs, the timer output is as specified by the ois3, ois2, os1, and os0 bits in 8tcsr (unchanged, 0 output, 1 output, or toggle output). figure 9.10 shows the timing when the output is set to toggle on compare match a. compare match a signal timer output figure 9.10 timing of timer output 287 clear by compare match: depending on the setting of the cclr1 and cclr0 bits in 8tcr, 8tcnt can be cleared when compare match a or b occurs, figure 9.11 shows the timing of this operation. n h'00 8tcnt compare match signal figure 9.11 timing of clear by compare match clear by input capture: depending on the setting of the cclr1 and cclr0 bits in 8tcr, 8tcnt can be cleared when input capture b occurs. figure 9.12 shows the timing of this operation. input capture signal input capture input 8tcnt nh '00 figure 9.12 timing of clear by input capture 9.4.3 input capture signal timing input capture on the rising edge, falling edge, or both edges can be selected by settings in 8tcsr. figure 9.13 shows the timing when the rising edge is selected. the pulse width of the input capture input signal must be at least 1.5 system clocks when a single edge is selected, and at least 2.5 system clocks when both edges are selected. 288 input capture signal input capture input 8tcnt n tcorb n figure 9.13 timing of input capture input signal 9.4.4 timing of status flag setting timing of cmfa/cmfb flag setting when compare match occurs: the cmfa and cmfb flags in 8tcsr are set to 1 by the compare match signal output when the tcora or tcorb and 8tcnt values match. the compare match signal is generated in the last state of the match (when the matched 8tcnt count value is updated). therefore, after the 8tcnt and tcora or tcorb values match, the compare match signal is not generated until an incrementing clock pulse signal is generated. figure 9.14 shows the timing in this case. cmf compare match signal 8tcnt n n+1 n tcor figure 9.14 cmf flag setting timing when compare match occurs timing of cmfb flag setting when input capture occurs: on generation of an input capture signal, the cmfb flag is set to 1 and at the same time the 8tcnt value is transferred to tcorb. figure 9.15 shows the timing in this case. 289 cmfb input capture signal 8tcnt n n tcorb figure 9.15 cmfb flag setting timing when input capture occurs timing of overflow flag (ovf) setting: the ovf flag in 8tcsr is set to 1 by the overflow signal generated when 8tcnt overflows (from h'ff to h'00). figure 9.16 shows the timing in this case. ovf overflow signal 8tcnt h'ff h'00 figure 9.16 timing of ovf setting 9.4.5 operation with cascaded connection if bits cks2 to cks0 are set to (100) in either 8tcr0 or 8tcr1, the 8-bit timers of channels 0 and 1 are cascaded. with this configuration, the two timers can be used as a single 16-bit timer (16-bit timer mode), or channel 0 8-bit timer compare matches can be counted in channel 1 (compare match count mode). similarly, if bits cks2 to cks0 are set to (100) in either 8tcr2 or 8tcr3, the 8-bit timers of channels 2 and 3 are cascaded. with this configuration, the two timers can be used as a single 16-bit timer (16-bit timer mode),or channel 2 8-bit timer compare matches can be counted in channel 3 (compare match count mode). in this case, the timer operates as below. 290 16-bit count mode ? channels 0 and 1: when bits cks2 to cks0 are set to (100) in 8tcr0, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits. ? setting when compare match occurs ? the cmfa or cmfb flag is set to 1 in 8tcsr0 when a 16-bit compare match occurs. ? the cmfa or cmfb flag is set to 1 in 8tcsr1 when a lower 8-bit compare match occurs. ? tmo 0 pin output control by bits ois3, ois2, os1, and os0 in 8tcsr0 is in accordance with the 16-bit compare match conditions. ? tmio 1 pin output control by bits ois3, ois2, os1, and os0 in 8tcsr1 is in accordance with the lower 8-bit compare match conditions. ? setting when input capture occurs ? the cmfb flag is set to 1 in 8tcsr0 and 8tcsr1 when the ice bit is 1 in tcsr1 and input capture occurs. ? tmio 1 pin input capture input signal edge detection is selected by bits ois3 and ois2 in 8tcsr0. ? counter clear specification ? if counter clear on compare match or input capture has been selected by the cclr1 and cclr0 bits in 8tcr0, the 16-bit counter (both 8tcnt0 and 8tcnt1) is cleared. ? the settings of the cclr1 and cclr0 bits in 8tcr1 are ignored. the lower 8 bits cannot be cleared independently. ? ovf flag operation ? the ovf flag is set to 1 in 8tcsr0 when the 16-bit counter (8tcnt0 and 8tcnt1) overflows (from h'ffff to h'0000). ? the ovf flag is set to 1 in 8tcsr1 when the 8-bit counter (8tcnt1) overflows (from h'ff to h'00). ? channels 2 and 3: when bits cks2 to cks0 are set to (100) in 8tcr2, the timer functions as a single 16-bit timer with channel 2 occupying the upper 8 bits and channel 3 occupying the lower 8 bits. ? setting when compare match occurs ? the cmfa or cmfb flag is set to 1 in 8tcsr2 when a 16-bit compare match occurs. ? the cmfa or cmfb flag is set to 1 in 8tcsr3 when a lower 8-bit compare match occurs. ? tmo 2 pin output control by bits ois3, ois2, os1, and os0 in 8tcsr2 is in accordance with the 16-bit compare match conditions. ? tmio 3 pin output control by bits ois3, ois2, os1, and os0 in 8tcsr3 is in accordance with the lower 8-bit compare match conditions. 291 ? setting when input capture occurs ? the cmfb flag is set to 1 in 8tcsr2 and 8tcsr3 when the ice bit is 1 in tcsr3 and input capture occurs. ? tmio 3 pin input capture input signal edge detection is selected by bits ois3 and ois2 in 8tcsr2. ? counter clear specification ? if counter clear on compare match has been selected by the cclr1 and cclr0 bits in 8tcr2, the 16-bit counter (both 8tcnt2 and 8tcnt3) is cleared. ? the settings of the cclr1 and cclr0 bits in 8tcr3 are ignored. the lower 8 bits cannot be cleared independently. ? ovf flag operation ? the ovf flag is set to 1 in 8tcsr2 when the 16-bit counter (8tcnt2 and 8tcnt3) overflows (from h'ffff to h'0000). ? the ovf flag is set to 1 in 8tcsr3 when the 8-bit counter (8tcnt3) overflows (from h'ff to h'00). compare match count mode ? channels 0 and 1: when bits cks2 to cks0 are set to (100) in 8tcr1, 8tcnt1 counts channel 0 compare match a events. cmf flag setting, interrupt generation, tmo pin output, counter clearing, and so on, is in accordance with the settings for each channel. note: when bit ice = 1 in 8tcsr1, the compare match register function of tcorb0 in channel 0 cannot be used. ? channels 2 and 3: when bits cks2 to cks0 are set to (100) in 8tcr3, 8tcnt3 counts channel 2 compare match a events. cmf flag setting, interrupt generation, tmo pin output, counter clearing, and so on, is in accordance with the settings for each channel. note: when bit ice = 1 in 8tcsr3, the compare match register function of tcorb2 in channel 2 cannot be used. caution do not set 16-bit counter mode and compare match count mode simultaneously within the same group, as the 8tcnt input clock will not be generated and the counters will not operate. 292 9.4.6 input capture setting the 8tcnt value can be transferred to tcorb on detection of an input edge on the input capture/output compare pin (tmio 1 or tmio 3 ). rising edge, falling edge, or both edge detection can be selected. in 16-bit count mode, 16-bit input capture can be used. setting input capture operation in 8-bit timer mode (normal operation) ? channel 1: ? set tcorb1 as an 8-bit input capture register with the ice bit in 8tcsr1. ? select rising edge, falling edge, or both edges as the input edge(s) for the input capture signal (tmio 1 ) with bits ois3 and ois2 in 8tcsr1. ? select the input clock with bits cks2 to cks0 in 8tcr1, and start the 8tcnt count. ? channel 3: ? set tcorb3 as an 8-bit input capture register with the ice bit in 8tcsr3. ? select rising edge, falling edge, or both edges as the input edge(s) for the input capture signal (tmio 3 ) with bits ois3 and ois2 in 8tcsr3. ? select the input clock with bits cks2 to cks0 in 8tcr3, and start the 8tcnt count. note: when tcorb1 in channel 1 is used for input capture, tcorb0 in channel 0 cannot be used as a compare match register. similarly, when tcorb3 in channel 3 is used for input capture, tcorb2 in channel 2 cannot be used as a compare match register. setting input capture operation in 16-bit count mode ? channels 0 and 1: ? in 16-bit count mode, tcorb0 and tcorb1 function as a 16-bit input capture register when the ice bit is set to 1 in 8tcsr1. ? select rising edge, falling edge, or both edges as the input edge(s) for the input capture signal (tmio 1 ) with bits ois3 and ois2 in 8tcsr0. (in 16-bit count mode, the settings of bits ois3 and ois2 in 8tcsr1 are ignored.) ? select the input clock with bits cks2 to cks0 in 8tcr1, and start the 8tcnt count. ? channels 2 and 3: ? in 16-bit count mode, tcorb2 and tcorb3 function as a 16-bit input capture register when the ice bit is set to 1 in 8tcsr3. ? select rising edge, falling edge, or both edges as the input edge(s) for the input capture signal (tmio 3 ) with bits ois3 and ois2 in 8tcsr2. (in 16-bit count mode, the settings of bits ois3 and ois2 in 8tcsr3 are ignored.) ? select the input clock with bits cks2 to cks0 in 8tcr3, and start the 8tcnt count. 293 9.5 interrupt 9.5.1 interrupt sources the 8-bit timer unit can generate three types of interrupt: compare match a and b (cmia and cmib) and overflow (tovi). table 9.5 shows the interrupt sources and their priority order. each interrupt source is enabled or disabled by the corresponding interrupt enable bit in 8tcr. a separate interrupt request signal is sent to the interrupt controller by each interrupt source. table 9.5 types of 8-bit timer interrupt sources and priority order priority interrupt source description high cmia interrupt by cmfa cmib interrupt by cmfb tovi interrupt by ovf low for compare match interrupts cmia1/cmib1 and cmia3/cmib3 and the overflow interrupts (tovi0/tovi1 and tovi2/tovi3), one vector is shared by two interrupts. table 9.6 lists the interrupt sources. table 9.6 8-bit timer interrupt sources channel interrupt source description 0 cmia0 tcora0 compare match cmib0 tcorb0 compare match/input capture 1 cmia1/cmib1 tcora1 compare match, or tcorb1 compare match/input capture 0, 1 tovi0/tovi1 counter 0 or counter 1 overflow 2 cmia2 tcora2 compare match cmib2 tcorb2 compare match/input capture 3 cmia3/cmib3 tcora3 compare match, or tcorb3 compare match/input capture 2, 3 tovi2/tovi3 counter 2 or counter 3 overflow 294 9.5.2 a/d converter activation the a/d converter can only be activated by channel 0 compare match a. if the adte bit setting is 1 when the cmfa flag in 8tcsr0 is set to 1 by generation of channel 0 compare match a, an a/d conversion start request will be issued to the a/d converter. if the trge bit in adcr is 1 at this time, the a/d converter will be started. if the adte bit in 8tcsr0 is 1, a/d converter external trigger pin ( adtrg ) input is disabled. 9.6 8-bit timer application example figure 9.17 shows how the 8-bit timer module can be used to output pulses with any desired duty cycle. the settings for this example are as follows: ? clear the cclr1 bit to 0 and set the cclr0 bit to 1 in 8tcr so that 8tcnt is cleared by a tcora compare match. ? set bits ois3, ois2, os1, and os0 to (0110) in 8tcsr so that 1 is output on a tcora compare match and 0 is output on a tcorb compare match. the above settings enable a waveform with the cycle determined by tcora and the pulse width detected by tcorb to be output without software intervention. 8tcnt h'ff counter clear tcora tcorb h'00 tmo figure 9.17 example of pulse output 295 9.7 usage notes note that the following kinds of contention can occur in 8-bit timer operation. 9.7.1 contention between 8tcnt write and clear if a timer counter clear signal occurs in the t 3 state of a 8tcnt write cycle, clearing of the counter takes priority and the write is not performed. figure 9.18 shows the timing in this case. address bus 8tcnt address internal write signal counter clear signal 8tcnt n h'00 t 1 t 3 t 2 8tcnt write cycle figure 9.18 contention between 8tcnt write and clear 296 9.7.2 contention between 8tcnt write and increment if an increment pulse occurs in the t 3 state of a 8tcnt write cycle, writing takes priority and 8tcnt is not incremented. figure 9.19 shows the timing in this case. address bus 8 tcnt address internal write signal 8tcnt input clock 8tcnt nm t 1 t 3 t 2 8tcnt write cycle 8tcnt write data figure 9.19 contention between 8tcnt write and increment 297 9.7.3 contention between tcor write and compare match if a compare match occurs in the t 3 state of a tcor write cycle, writing takes priority and the compare match signal is inhibited. figure 9.20 shows the timing in this case. address bus tcor address internal write signal 8tcnt tcor nm t 1 t 3 t 2 tcor write cycle tcor write data n n+1 compare match signal inhibited figure 9.20 contention between tcor write and compare match 298 9.7.4 contention between tcor read and input capture if an input capture signal occurs in the t 3 state of a tcor read cycle, the value before input capture is read. figure 9.21 shows the timing in this case. address bus tcorb address internal read signal input capture signal tcorb nm t 1 t 3 t 2 tcorb read cycle internal data bus n figure 9.21 contention between tcor read and input capture 299 9.7.5 contention between counter clearing by input capture and counter increment if an input capture signal and counter increment signal occur simultaneously, counter clearing by the input capture signal takes priority and the counter is not incremented. the value before the counter is cleared is transferred to tcorb. figure 9.22 shows the timing in this case. counter clear signal 8tcnt internal clock 8tcnt n x h'00 t 1 t 3 t 2 input capture signal tcorb n figure 9.22 contention between counter clearing by input capture and counter increment 300 9.7.6 contention between tcor write and input capture if an input capture signal occurs in the t 3 state of a tcor write cycle, input capture takes priority and the write to tcor is not performed. figure 9.23 shows the timing in this case. address bus tcor address internal write signal input capture signal 8tcnt m t 1 t 3 t 2 tcor write cycle tcor m x figure 9.23 contention between tcor write and input capture 301 9.7.7 contention between 8tcnt byte write and increment in 16-bit count mode (cascaded connection) if an increment pulse occurs in the t 3 state of an 8tcnt byte write cycle in 16-bit count mode, the counter write takes priority and the byte data for which the write was performed is not incremented. the byte data for which a write was not performed is incremented. figure 9.24 shows the timing when an increment pulse occurs in the t 2 state of a byte write to 8tcnt (upper byte). if an increment pulse occurs in the t 2 state, on the other hand, the increment takes priority. address bus 8tcnth address internal write signal 8tcnt input clock 8tcnt (upper byte) n n+1 8tcnt write data t 1 t 3 t 2 8tcnt (upper byte) byte write cycle 8tcnt (lower byte) x+1 x figure 9.24 contention between 8tcnt byte write and increment in 16-bit count mode 302 9.7.8 contention between compare matches a and b if compare matches a and b occur at the same time, the 8-bit timer operates according to the relative priority of the output states set for compare match a and compare match b, as shown in table 9.7. table 9.7 timer output priority order priority output setting high toggle output 1 output 0 output no change low 9.7.9 8tcnt operation and internal clock source switchover switching internal clock sources may cause 8tcnt to increment, depending on the switchover timing. table 9.8 shows the relation between the time of the switchover (by writing to bits cks1 and cks0) and the operation of 8tcnt. the 8tcnt input clock is generated from the internal clock source by detecting the rising edge of the internal clock. if a switchover is made from a low clock source to a high clock source, as in case no. 3 in table 9.8, the switchover will be regarded as a falling edge, a 8tcnt clock pulse will be generated, and 8tcnt will be incremented. 8tcnt may also be incremented when switching between internal and external clocks. 303 table 9.8 internal clock switchover and 8tcnt operation no. cks1 and cks0 write timing 8tcnt operation 1 high high switchover* 1 old clock source new clock source 8tcnt clock 8tcnt cks bits rewritten n n+1 2 high low switchover* 2 old clock source new clock source 8tcnt clock 8tcnt cks bits rewritten n n+1 n+2 3 low high switchover* 3 old clock source new clock source 8tcnt clock 8tcnt cks bits rewritten n n+1 n+2 * 4 304 no. cks1 and cks0 write timing 8tcnt operation 4 low low switchover* 4 old clock source new clock source 8tcnt clock 8tcnt cks bits rewritten n n+1 n+2 notes: *1 including switchovers from the high level to the halted state, and from the halted state to the high level. *2 including switchover from the halted state to the low level. *3 including switchover from the low level to the halted state. *4 the switchover is regarded as a rising edge, causing 8tcnt to increment. 305 section 10 programmable timing pattern controller (tpc) 10.1 overview the h8/3024 series has a built-in programmable timing pattern controller (tpc) that provides pulse outputs by using the 16-bit timer as a time base. the tpc pulse outputs are divided into 4- bit groups (group 3 to group 0) that can operate simultaneously and independently. 10.1.1 features tpc features are listed below. ? 16-bit output data maximum 16-bit data can be output. tpc output can be enabled on a bit-by-bit basis. ? four output groups output trigger signals can be selected in 4-bit groups to provide up to four different 4-bit outputs. ? selectable output trigger signals ? output trigger signals can be selected for each group from the compare match signals of three 16-bit timer channels. ? non-overlap mode a non-overlap margin can be provided between pulse outputs. 306 10.1.2 block diagram figure 10.1 shows a block diagram of the tpc. paddr ndera tpmr pbddr nderb tpcr internal data bus tp tp tp tp tp tp 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 control logic 16-bit timer compare match signals pulse output pins, group 3 pbdr padr legend: tpmr: tpcr: nderb: ndera: pbddr: paddr: ndrb: ndra: pbdr: padr: pulse output pins, group 2 pulse output pins, group 1 pulse output pins, group 0 tpc output mode register tpc output control register next data enable register b next data enable register a port b data direction register port a data direction register next data register b next data register a port b data register port a data register ndrb ndra tp tp tp tp tp tp tp tp tp tp figure 10.1 tpc block diagram 307 10.1.3 pin configuration table 10.1 summarizes the tpc output pins. table 10.1 tpc pins name symbol i/o function tpc output 0 tp 0 output group 0 pulse output tpc output 1 tp 1 output tpc output 2 tp 2 output tpc output 3 tp 3 output tpc output 4 tp 4 output group 1 pulse output tpc output 5 tp 5 output tpc output 6 tp 6 output tpc output 7 tp 7 output tpc output 8 tp 8 output group 2 pulse output tpc output 9 tp 9 output tpc output 10 tp 10 output tpc output 11 tp 11 output tpc output 12 tp 12 output group 3 pulse output tpc output 13 tp 13 output tpc output 14 tp 14 output tpc output 15 tp 15 output 308 10.1.4 register configuration table 10.2 summarizes the tpc registers. table 10.2 tpc registers address* 1 name abbreviation r/w initial value h'ee009 port a data direction register paddr w h'00 h'fffd9 port a data register padr r/(w)* 2 h'00 h'ee00a port b data direction register pbddr w h'00 h'fffda port b data register pbdr r/(w)* 2 h'00 h'fffa0 tpc output mode register tpmr r/w h'f0 h'fffa1 tpc output control register tpcr r/w h'ff h'fffa2 next data enable register b nderb r/w h'00 h'fffa3 next data enable register a ndera r/w h'00 h'fffa5/ h'fffa7* 3 next data register a ndra r/w h'00 h'fffa4/ h'fffa6* 3 next data register b ndrb r/w h'00 notes: *1 lower 20 bits of the address in advanced mode. *2 bits used for tpc output cannot be written. *3 the ndra address is h'fffa5 when the same output trigger is selected for tpc output groups 0 and 1 by settings in tpcr. when the output triggers are different, the ndra address is h'fffa7 for group 0 and h'fffa5 for group 1. similarly, the address of ndrb is h'fffa4 when the same output trigger is selected for tpc output groups 2 and 3 by settings in tpcr. when the output triggers are different, the ndrb address is h'fffa6 for group 2 and h'fffa4 for group 3. 309 10.2 register descriptions 10.2.1 port a data direction register (paddr) paddr is an 8-bit write-only register that selects input or output for each pin in port a. bit initial value read/write 7 pa ddr 0 w port a data direction 7 to 0 these bits select input or output for port a pins 7 6 pa ddr 0 w 6 5 pa ddr 0 w 5 4 pa ddr 0 w 4 3 pa ddr 0 w 3 2 pa ddr 0 w 2 1 pa ddr 0 w 1 0 pa ddr 0 w 0 port a is multiplexed with pins tp 7 to tp 0 . bits corresponding to pins used for tpc output must be set to 1. for further information about paddr, see section 7.11, port a. 10.2.2 port a data register (padr) padr is an 8-bit readable/writable register that stores tpc output data for groups 0 and 1, when these tpc output groups are used. bit initial value read/write 0 pa 0 r/(w) 0 1 pa 0 r/(w) 1 2 pa 0 r/(w) 2 3 pa 0 r/(w) 3 4 pa 0 r/(w) 4 5 pa 0 r/(w) 5 6 pa 0 r/(w) 6 7 pa 0 r/(w) 7 port a data 7 to 0 these bits store output data for tpc output groups 0 and 1 ******** note: bits selected for tpc output by ndera settings become read-only bits. * for further information about padr, see section 7.11, port a. 310 10.2.3 port b data direction register (pbddr) pbddr is an 8-bit write-only register that selects input or output for each pin in port b. bit initial value read/write 7 pb ddr 0 w port b data direction 7 to 0 these bits select input or output for port b pins 7 6 pb ddr 0 w 6 5 pb ddr 0 w 5 4 pb ddr 0 w 4 3 pb ddr 0 w 3 2 pb ddr 0 w 2 1 pb ddr 0 w 1 0 pb ddr 0 w 0 port b is multiplexed with pins tp 15 to tp 8 . bits corresponding to pins used for tpc output must be set to 1. for further information about pbddr, see section 7.12, port b. 10.2.4 port b data register (pbdr) pbdr is an 8-bit readable/writable register that stores tpc output data for groups 2 and 3, when these tpc output groups are used. bit initial value read/write 0 pb 0 r/(w) 0 1 pb 0 r/(w) 1 2 pb 0 r/(w) 2 3 pb 0 r/(w) 3 4 pb 0 r/(w) 4 5 pb 0 r/(w) 5 6 pb 0 r/(w) 6 7 pb 0 r/(w) 7 port b data 7 to 0 these bits store output data for tpc output groups 2 and 3 ******** note: bits selected for tpc output by nderb settings become read-only bits. * for further information about pbdr, see section 7.12, port b. 311 10.2.5 next data register a (ndra) ndra is an 8-bit readable/writable register that stores the next output data for tpc output groups 1 and 0 (pins tp 7 to tp 0 ). during tpc output, when an 16-bit timer compare match event specified in tpcr occurs, ndra contents are transferred to the corresponding bits in padr. the address of ndra differs depending on whether tpc output groups 0 and 1 have the same output trigger or different output triggers. ndra is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. same trigger for tpc output groups 0 and 1: if tpc output groups 0 and 1 are triggered by the same compare match event, the ndra address is h'fffa5. the upper 4 bits belong to group 1 and the lower 4 bits to group 0. address h'fffa7 consists entirely of reserved bits that cannot be modified and always read 1. address h'fffa5 bit initial value read/write 0 ndr0 0 r/w 1 ndr1 0 r/w 2 ndr2 0 r/w 3 ndr3 0 r/w 4 ndr4 0 r/w 5 ndr5 0 r/w 6 ndr6 0 r/w 7 ndr7 0 r/w next data 7 to 4 these bits store the next output data for tpc output group 1 next data 3 to 0 these bits store the next output data for tpc output group 0 address h'fffa7 bit initial value read/write 0 ? 1 ? 1 ? 1 ? 2 ? 1 ? 3 ? 1 ? 4 ? 1 ? 5 ? 1 ? 6 ? 1 ? 7 ? 1 ? reserved bits 312 different triggers for tpc output groups 0 and 1: if tpc output groups 0 and 1 are triggered by different compare match events, the address of the upper 4 bits of ndra (group 1) is h'fffa5 and the address of the lower 4 bits (group 0) is h'fffa7. bits 3 to 0 of address h'fffa5 and bits 7 to 4 of address h'fffa7 are reserved bits that cannot be modified and always read 1. address h'fffa5 bit initial value read/write 0 ? 1 ? 1 ? 1 ? 2 ? 1 ? 3 ? 1 ? 4 ndr4 0 r/w 5 ndr5 0 r/w 6 ndr6 0 r/w 7 ndr7 0 r/w next data 7 to 4 these bits store the next output data for tpc output group 1 reserved bits address h'fffa7 bit initial value read/write 0 ndr0 0 r/w 1 ndr1 0 r/w 2 ndr2 0 r/w 3 ndr3 0 r/w 4 ? 1 ? 5 ? 1 ? 6 ? 1 ? 7 ? 1 ? reserved bits next data 3 to 0 these bits store the next output data for tpc output group 0 313 10.2.6 next data register b (ndrb) ndrb is an 8-bit readable/writable register that stores the next output data for tpc output groups 3 and 2 (pins tp 15 to tp 8 ). during tpc output, when an 16-bit timer compare match event specified in tpcr occurs, ndrb contents are transferred to the corresponding bits in pbdr. the address of ndrb differs depending on whether tpc output groups 2 and 3 have the same output trigger or different output triggers. ndrb is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. same trigger for tpc output groups 2 and 3: if tpc output groups 2 and 3 are triggered by the same compare match event, the ndrb address is h'fffa4. the upper 4 bits belong to group 3 and the lower 4 bits to group 2. address h'fffa6 consists entirely of reserved bits that cannot be modified and always read 1. address h'fffa4 bit initial value read/write 0 ndr8 0 r/w 1 ndr9 0 r/w 2 ndr10 0 r/w 3 ndr11 0 r/w 4 ndr12 0 r/w 5 ndr13 0 r/w 6 ndr14 0 r/w 7 ndr15 0 r/w next data 15 to 12 these bits store the next output data for tpc output group 3 next data 11 to 8 these bits store the next output data for tpc output group 2 address h'fffa6 bit initial value read/write 0 ? 1 ? 1 ? 1 ? 2 ? 1 ? 3 ? 1 ? 4 ? 1 ? 5 ? 1 ? 6 ? 1 ? 7 ? 1 ? reserved bits 314 different triggers for tpc output groups 2 and 3: if tpc output groups 2 and 3 are triggered by different compare match events, the address of the upper 4 bits of ndrb (group 3) is h'fffa4 and the address of the lower 4 bits (group 2) is h'fffa6. bits 3 to 0 of address h'fffa4 and bits 7 to 4 of address h'fffa6 are reserved bits that cannot be modified and always read 1. address h'fffa4 bit initial value read/write 0 ? 1 ? 1 ? 1 ? 2 ? 1 ? 3 ? 1 ? 4 ndr12 0 r/w 5 ndr13 0 r/w 6 ndr14 0 r/w 7 ndr15 0 r/w next data 15 to 12 these bits store the next output data for tpc output group 3 reserved bits address h'fffa6 bit initial value read/write 0 ndr8 0 r/w 1 ndr9 0 r/w 2 ndr10 0 r/w 3 ndr11 0 r/w 4 ? 1 ? 5 ? 1 ? 6 ? 1 ? 7 ? 1 ? reserved bits next data 11 to 8 these bits store the next output data for tpc output group 2 315 10.2.7 next data enable register a (ndera) ndera is an 8-bit readable/writable register that enables or disables tpc output groups 1 and 0 (tp 7 to tp 0 ) on a bit-by-bit basis. bit initial value read/write 0 nder0 0 r/w 1 nder1 0 r/w 2 nder2 0 r/w 3 nder3 0 r/w 4 nder4 0 r/w 5 nder5 0 r/w 6 nder6 0 r/w 7 nder7 0 r/w next data enable 7 to 0 these bits enable or disable tpc output groups 1 and 0 if a bit is enabled for tpc output by ndera, then when the 16-bit timer compare match event selected in the tpc output control register (tpcr) occurs, the ndra value is automatically transferred to the corresponding padr bit, updating the output value. if tpc output is disabled, the bit value is not transferred from ndra to padr and the output value does not change. ndera is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 7 to 0?ext data enable 7 to 0 (nder7 to nder0): these bits enable or disable tpc output groups 1 and 0 (tp 7 to tp 0 ) on a bit-by-bit basis. bits 7 to 0 nder7 to nder0 description 0 tpc outputs tp 7 to tp 0 are disabled (ndr7 to ndr0 are not transferred to pa 7 to pa 0 ) (initial value) 1 tpc outputs tp 7 to tp 0 are enabled (ndr7 to ndr0 are transferred to pa 7 to pa 0 ) 316 10.2.8 next data enable register b (nderb) nderb is an 8-bit readable/writable register that enables or disables tpc output groups 3 and 2 (tp 15 to tp 8 ) on a bit-by-bit basis. bit initial value read/write 0 nder8 0 r/w 1 nder9 0 r/w 2 nder10 0 r/w 3 nder11 0 r/w 4 nder12 0 r/w 5 nder13 0 r/w 6 nder14 0 r/w 7 nder15 0 r/w next data enable 15 to 8 these bits enable or disable tpc output groups 3 and 2 if a bit is enabled for tpc output by nderb, then when the 16-bit timer compare match event selected in the tpc output control register (tpcr) occurs, the ndrb value is automatically transferred to the corresponding pbdr bit, updating the output value. if tpc output is disabled, the bit value is not transferred from ndrb to pbdr and the output value does not change. nderb is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 7 to 0?ext data enable 15 to 8 (nder15 to nder8): these bits enable or disable tpc output groups 3 and 2 (tp 15 to tp 8 ) on a bit-by-bit basis. bits 7 to 0 nder15 to nder8 description 0 tpc outputs tp 15 to tp 8 are disabled (ndr15 to ndr8 are not transferred to pb 7 to pb 0 ) (initial value) 1 tpc outputs tp 15 to tp 8 are enabled (ndr15 to ndr8 are transferred to pb 7 to pb 0 ) 317 10.2.9 tpc output control register (tpcr) tpcr is an 8-bit readable/writable register that selects output trigger signals for tpc outputs on a group-by-group basis. bit initial value read/write 0 g0cms0 1 r/w 1 g0cms1 1 r/w 2 g1cms0 1 r/w 3 g1cms1 1 r/w 4 g2cms0 1 r/w 5 g2cms1 1 r/w 6 g3cms0 1 r/w 7 g3cms1 1 r/w group 3 compare match select 1 and 0 these bits select the compare match event that triggers tpc output group 3 (tp 15 to tp 12 ) group 2 compare match select 1 and 0 these bits select the compare match event that triggers tpc output group 2 (tp 11 to tp 8 ) group 1 compare match select 1 and 0 these bits select the compare match event that triggers tpc output group 1 (tp 7 to tp 4 ) group 0 compare match select 1 and 0 these bits select the compare match event that triggers tpc output group 0 (tp 3 to tp 0 ) tpcr is initialized to h'ff by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 7 and 6?roup 3 compare match select 1 and 0 (g3cms1, g3cms0): these bits select the compare match event that triggers tpc output group 3 (tp 15 to tp 12 ). bit 7 g3cms1 bit 6 g3cms0 description 0 0 tpc output group 3 (tp 15 to tp 12 ) is triggered by compare match in 16-bit timer channel 0 1 tpc output group 3 (tp 15 to tp 12 ) is triggered by compare match in 16-bit timer channel 1 1 0 tpc output group 3 (tp 15 to tp 12 ) is triggered by compare match in 16-bit timer channel 2 1 tpc output group 3 (tp 15 to tp 12 ) is triggered by compare match in 16-bit timer channel 2 (initial value) 318 bits 5 and 4?roup 2 compare match select 1 and 0 (g2cms1, g2cms0): these bits select the compare match event that triggers tpc output group 2 (tp 11 to tp 8 ). bit 5 g2cms1 bit 4 g2cms0 description 0 0 tpc output group 2 (tp 11 to tp 8 ) is triggered by compare match in 16-bit timer channel 0 1 tpc output group 2 (tp 11 to tp 8 ) is triggered by compare match in 16-bit timer channel 1 1 0 tpc output group 2 (tp 11 to tp 8 ) is triggered by compare match in 16-bit timer channel 2 1 tpc output group 2 (tp 11 to tp 8 ) is triggered by compare match in 16-bit timer channel 2 (initial value) bits 3 and 2?roup 1 compare match select 1 and 0 (g1cms1, g1cms0): these bits select the compare match event that triggers tpc output group 1 (tp 7 to tp 4 ). bit 3 g1cms1 bit 2 g1cms0 description 0 0 tpc output group 1 (tp 7 to tp 4 ) is triggered by compare match in 16-bit timer channel 0 1 tpc output group 1 (tp 7 to tp 4 ) is triggered by compare match in 16-bit timer channel 1 1 0 tpc output group 1 (tp 7 to tp 4 ) is triggered by compare match in 16-bit timer channel 2 1 tpc output group 1 (tp 7 to tp 4 ) is triggered by compare match in 16-bit timer channel 2 (initial value) bits 1 and 0?roup 0 compare match select 1 and 0 (g0cms1, g0cms0): these bits select the compare match event that triggers tpc output group 0 (tp 3 to tp 0 ). bit 1 g0cms1 bit 0 g0cms0 description 0 0 tpc output group 0 (tp 3 to tp 0 ) is triggered by compare match in 16-bit timer channel 0 1 tpc output group 0 (tp 3 to tp 0 ) is triggered by compare match in 16-bit timer channel 1 1 0 tpc output group 0 (tp 3 to tp 0 ) is triggered by compare match in 16-bit timer channel 2 1 tpc output group 0 (tp 3 to tp 0 ) is triggered by compare match in 16-bit timer channel 2 (initial value) 319 10.2.10 tpc output mode register (tpmr) tpmr is an 8-bit readable/writable register that selects normal or non-overlapping tpc output for each group. bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 g3nov 0 r/w 0 g0nov 0 r/w 2 g2nov 0 r/w 1 g1nov 0 r/w group 3 non-overlap selects non-overlapping tpc output for group 3 (tp to tp ) reserved bits group 2 non-overlap selects non-overlapping tpc output for group 2 (tp to tp ) group 1 non-overlap selects non-overlapping tpc output for group 1 (tp to tp ) group 0 non-overlap selects non-overlapping tpc output for group 0 (tp to tp ) 15 12 11 8 74 30 the output trigger period of a non-overlapping tpc output waveform is set in general register b (grb) in the 16-bit timer channel selected for output triggering. the non-overlap margin is set in general register a (gra). the output values change at compare match a and b. for details see section 10.3.4, non-overlapping tpc output. tpmr is initialized to h'f0 by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 7 to 4?eserved: these bits cannot be modified and are always read as 1. 320 bit 3?roup 3 non-overlap (g3nov): selects normal or non-overlapping tpc output for group 3 (tp 15 to tp 12 ). bit 3 g3nov description 0 normal tpc output in group 3 (output values change at compare match a in the selected 16-bit timer channel) (initial value) 1 non-overlapping tpc output in group 3 (independent 1 and 0 output at compare match a and b in the selected 16-bit timer channel) bit 2?roup 2 non-overlap (g2nov): selects normal or non-overlapping tpc output for group 2 (tp 11 to tp 8 ). bit 2 g2nov description 0 normal tpc output in group 2 (output values change at compare match a in the selected 16-bit timer channel) (initial value) 1 non-overlapping tpc output in group 2 (independent 1 and 0 output at compare match a and b in the selected 16-bit timer channel) bit 1?roup 1 non-overlap (g1nov): selects normal or non-overlapping tpc output for group 1 (tp 7 to tp 4 ). bit 1 g1nov description 0 normal tpc output in group 1 (output values change at compare match a in the selected 16-bit timer channel) (initial value) 1 non-overlapping tpc output in group 1 (independent 1 and 0 output at compare match a and b in the selected 16-bit timer channel) bit 0?roup 0 non-overlap (g0nov): selects normal or non-overlapping tpc output for group 0 (tp 3 to tp 0 ). bit 0 g0nov description 0 normal tpc output in group 0 (output values change at compare match a in the selected 16-bit timer channel) (initial value) 1 non-overlapping tpc output in group 0 (independent 1 and 0 output at compare match a and b in the selected 16-bit timer channel) 321 10.3 operation 10.3.1 overview when corresponding bits in paddr or pbddr and ndera or nderb are set to 1, tpc output is enabled. the tpc output initially consists of the corresponding padr or pbdr contents. when a compare-match event selected in tpcr occurs, the corresponding ndra or ndrb bit contents are transferred to padr or pbdr to update the output values. figure 10.2 illustrates the tpc output operation. table 10.3 summarizes the tpc operating conditions. ddr nder qq tpc output pin dr ndr c qd qd internal data bus output trigger signal figure 10.2 tpc output operation table 10.3 tpc operating conditions nder ddr pin function 0 0 generic input port 1 generic output port 1 0 generic input port (but the dr bit is a read-only bit, and when compare match occurs, the ndr bit value is transferred to the dr bit) 1 tpc pulse output sequential output of up to 16-bit patterns is possible by writing new output data to ndra and ndrb before the next compare match. for information on non-overlapping operation, see section 10.3.4, non-overlapping tpc output. 322 10.3.2 output timing if tpc output is enabled, ndra/ndrb contents are transferred to padr/pbdr and output when the selected compare match event occurs. figure 10.3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match a. t cnt g ra c ompare m atch a signal n drb p bdr t p to tp 815 n n n m m n + 1 n n figure 10.3 timing of transfer of next data register contents and output (example) 323 10.3.3 normal tpc output sample setup procedure for normal tpc output: figure 10.4 shows a sample procedure for setting up normal tpc output. normal tpc output set next tpc output data compare match? no ye s set next tpc output data 16-bit timer setup 16-bit timer setup port and tpc setup 10 11 9 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. set tior to make gra an output compare register (with output inhibited). set the tpc output trigger period. select the counter clock source with bits tpsc2 to tpsc0 in tcr. select the counter clear source with bits cclr1 and cclr0. enable the imfa interrupt in tisra. set the initial output values in the dr bits of the input/output port pins to be used for tpc output. set the ddr bits of the input/output port pins to be used for tpc output to 1. set the nder bits of the pins to be used for tpc output to 1. select the 16-bit timer compare match event to be used as the tpc output trigger in tpcr. set the next tpc output values in the ndr bits. set the str bit to 1 in tstr to start the timer counter. at each imfa interrupt, set the next output values in the ndr bits. 1 2 3 4 5 6 7 8 select gr functions set gra value select counting operation select interrupt request start counter set initial output data select port output enable tpc output select tpc output trigger figure 10.4 setup procedure for normal tpc output (example) 324 example of normal tpc output (example of five-phase pulse output): figure 10.5 shows an example in which the tpc is used for cyclic five-phase pulse output. gra h'0000 ndrb pbdr tp 15 tp 14 tp 13 tp 12 tp 11 1. 2. 3. 4. time 80 tcnt tcnt value c0 40 60 20 30 10 18 08 88 80 c0 compare match the 16-bit timer channel to be used as the output trigger channel is set up so that gra is an output compare register and the counter will be cleared by compare match a. the trigger period is set in gra. the imiea bit is set to 1 in tisra to enable the compare match a interrupt. h'f8 is written in pbddr and nderb, and bits g3cms1, g3cms0, g2cms1, and g2cms0 are set in tpcr to select compare match in the 16-bit timer channel set up in step 1 as the output trigger. output data h'80 is written in ndrb. the timer counter in this 16-bit timer channel is started. when compare match a occurs, the ndrb contents are transferred to pbdr and output. the compare match/input capture a (imfa) interrupt service routine writes the next output data (h'c0) in ndrb. five-phase overlapping pulse output (one or two phases active at a time) can be obtained by writing h'40, h'60, h'20, h'30, h'10, h'18, h'08, h'88 at successive imfa interrupts. 00 80 c0 40 60 20 30 10 18 08 88 80 c0 40 figure 10.5 normal tpc output example (five-phase pulse output) 325 10.3.4 non-overlapping tpc output sample setup procedure for non-overlapping tpc output: figure 10.6 shows a sample procedure for setting up non-overlapping tpc output. non-overlapping tpc output set next tpc output data compare match a? no yes set next tpc output data start counter 16-bit timer setup 16-bit timer setup port and tpc setup set initial output data set up tpc output enable tpc transfer select tpc transfer trigger select non-overlapping groups 1 2 3 4 12 10 11 5 6 7 8 9 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. set tior to make gra and grb output compare registers (with output inhibited). set the tpc output trigger period in grb and the non-overlap margin in gra. select the counter clock source with bits tpsc2 to tpsc0 in tcr. select the counter clear source with bits cclr1 and cclr0. enable the imfa interrupt in tisra. set the initial output values in the dr bits of the input/output port pins to be used for tpc output. set the ddr bits of the input/output port pins to be used for tpc output to 1. set the nder bits of the pins to be used for tpc output to 1. in tpcr, select the 16-bit timer compare match event to be used as the tpc output trigger. in tpmr, select the groups that will operate in non-overlap mode. set the next tpc output values in the ndr bits. set the str bit to 1 in tstr to start the timer counter. at each imfa interrupt, write the next output value in the ndr bits. select gr functions set gr values select counting operation select interrupt requests figure 10.6 setup procedure for non-overlapping tpc output (example) 326 example of non-overlapping tpc output (example of four-phase complementary non- overlapping output): figure 10.7 shows an example of the use of tpc output for four-phase complementary non-overlapping pulse output. grb h'0000 ndrb pbdr tp 15 tp 14 tp 13 tp 12 tp 11 tp 10 tp 9 tp 8 time 95 00 65 95 59 56 95 65 05 65 41 59 50 56 14 95 05 65 tcnt period is set in grb. the non-overlap margin is set in gra. the imiea bit is set to 1 in tisra to enable imfa interrupts. h'ff is written in pbddr and nderb, and bits g3cms1, g3cms0, g2cms1, and g2cms0 are set in tpcr to select compare match in the 16-bit timer channel set up in step 1 as the output trigger. bits g3nov and g2nov are set to 1 in tpmr to select non-overlapping output. output data h'95 is written in ndrb. tcnt value non-overlap margin the 16-bit timer channel to be used as the output trigger channel is set up so that gra and grb are output compare registers and the counter will be cleared by compare match b. the tpc output trigger 1. 2. 3. 4. the timer counter in this 16-bit timer channel is started. when compare match b occurs, outputs change from 1 to 0. when compare match a occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed by the value of gra). the imfa interrupt service routine writes the next output data (h'65) in ndrb. four-phase complementary non-overlapping pulse output can be obtained by writing h'59, h'56, h'95 at successive imfa interrupts. gra figure 10.7 non-overlapping tpc output example (four-phase complementary non-overlapping pulse output) 327 10.3.5 tpc output triggering by input capture tpc output can be triggered by 16-bit timer input capture as well as by compare match. if gra functions as an input capture register in the 16-bit timer channel selected in tpcr, tpc output will be triggered by the input capture signal. figure 10.8 shows the timing. tioc pin input capture signal ndr dr n n m figure 10.8 tpc output triggering by input capture (example) 328 10.4 usage notes 10.4.1 operation of tpc output pins tp 0 to tp 15 are multiplexed with 16-bit timer, address bus, and other pin functions. when 16-bit timer, or address bus output is enabled, the corresponding pins cannot be used for tpc output. the data transfer from ndr bits to dr bits takes place, however, regardless of the usage of the pin. pin functions should be changed only under conditions in which the output trigger event will not occur. 10.4.2 note on non-overlapping output during non-overlapping operation, the transfer of ndr bit values to dr bits takes place as follows. 1. ndr bits are always transferred to dr bits at compare match a. 2. at compare match b, ndr bits are transferred only if their value is 0. bits are not transferred if their value is 1. figure 10.9 illustrates the non-overlapping tpc output operation. ddr nder qq tpc output pin dr ndr c qd qd compare match a compare match b figure 10.9 non-overlapping tpc output 329 therefore, 0 data can be transferred ahead of 1 data by making compare match b occur before compare match a. ndr contents should not be altered during the interval from compare match b to compare match a (the non-overlap margin). this can be accomplished by having the imfa interrupt service routine write the next data in ndr. the next data must be written before the next compare match b occurs. figure 10.10 shows the timing relationships. compare match a compare match b ndr write ndr ndr write dr 0/1 output 0/1 output 0 output 0 output do not write to ndr in this interval do not write to ndr in this interval write to ndr in this interval write to ndr in this interval figure 10.10 non-overlapping operation and ndr write timing 330 331 section 11 watchdog timer 11.1 overview the h8/3024 series has an on-chip watchdog timer (wdt). the wdt has two selectable functions: it can operate as a watchdog timer to supervise system operation, or it can operate as an interval timer. as a watchdog timer, it generates a reset signal for the h8/3024 chip if a system crash allows the timer counter (tcnt) to overflow before being rewritten. in interval timer operation, an interval timer interrupt is requested at each tcnt overflow. 11.1.1 features wdt features are listed below. ? selection of eight counter clock sources /2, /32, /64, /128, /256, /512, /2048, or /4096 ? interval timer option ? timer counter overflow generates a reset signal or interrupt. the reset signal is generated in watchdog timer operation. an interval timer interrupt is generated in interval timer operation. ? watchdog timer reset signal resets the entire h8/3024 internally, and can also be output externally. the reset signal generated by timer counter overflow during watchdog timer operation resets the entire h8/3024 internally. an external reset signal can be output from the reso pin to reset other system devices simultaneously. in the versions with on-chip flash memory, the reso pin functions as the fwe pin, and therefore there is no function for outputting a reset signal externally. 332 11.1.2 block diagram figure 11.1 shows a block diagram of the wdt. figure 11.1 wdt block diagram 11.1.3 pin configuration table 11.1 describes the wdt output pin*. note: * not present in the versions with on-chip flash memory. table 11.1 wdt pin name abbreviation i/o function reset output reso 333 11.1.4 register configuration table 11.2 summarizes the wdt registers. table 11.2 wdt registers address* 1 write* 2 read name abbreviation r/w initial value h'fff8c h'fff8c timer control/status register tcsr r/(w)* 3 h'18 h'fff8d timer counter tcnt r/w h'00 h'fff8e h'fff8f reset control/status register rstcsr r/(w)* 3 h'3f notes: *1 lower 20 bits of the address in advanced mode. *2 write word data starting at this address. *3 only 0 can be written in bit 7, to clear the flag. 11.2 register descriptions 11.2.1 timer counter (tcnt) tcnt is an 8-bit readable and writable up-counter. bit initial value read/write 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w note: the method for writing to tcnt is different from that for general registers to prevent inadvertent overwriting. for details see section 11.2.4, notes on register access. when the tme bit is set to 1 in tcsr, tcnt starts counting pulses generated from an internal clock source selected by bits cks2 to cks0 in tcsr. when the count overflows (changes from h'ff to h'00), the ovf bit is set to 1 in tcsr. tcnt is initialized to h'00 by a reset and when the tme bit is cleared to 0. 334 11.2.2 timer control/status register (tcsr) tcsr is an 8-bit readable and writable register. its functions include selecting the timer mode and clock source. bit initial value read/write 7 ovf 0 r/(w) 6 wt/it 0 r/w 5 tme 0 r/w 4 1 3 1 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w overflow flag status flag indicating overflow clock select these bits select the tcnt clock source timer mode select selects the mode timer enable selects whether tcnt runs or halts reserved bits * notes: the method for writing to tcsr is different from that for general registers to prevent inadvertent overwriting. for details see section 11.2.4, notes on register access. * only 0 can be written, to clear the flag. bits 7 to 5 are initialized to 0 by a reset and in standby mode. bits 2 to 0 are initialized to 0 by a reset. in software standby mode bits 2 to 0 are not initialized, but retain their previous values. bit 7?verflow flag (ovf): this status flag indicates that the timer counter has overflowed from h'ff to h'00. bit 7 ovf description 0 [clearing condition] cleared by reading ovf when ovf = 1, then writing 0 in ovf (initial value) 1 [setting condition] set when tcnt changes from h'ff to h'00 335 bit 6?imer mode select (wt/ it ): selects whether to use the wdt as a watchdog timer or interval timer. if used as an interval timer, the wdt generates an interval timer interrupt request when tcnt overflows. if used as a watchdog timer, the wdt generates a reset signal when tcnt overflows. bit 6 wt/ it description 0 interval timer: requests interval timer interrupts (initial value) 1 watchdog timer: generates a reset signal bit 5?imer enable (tme): selects whether tcnt runs or is halted. when wt/ it = 1, clear the software standby bit (ssby) to 0 in syscr before setting tme. when setting ssby to 1, tme should be cleared to 0. bit 5 tme description 0 tcnt is initialized to h'00 and halted (initial value) 1 tcnt is counting bits 4 and 3?eserved: these bits cannot be modified and are always read as 1. bits 2 to 0?lock select 2 to 0 (cks2 to cks0): these bits select one of eight internal clock sources, obtained by prescaling the system clock ( ), for input to tcnt. bit 2 cks2 bit 1 cks1 bit 0 cks0 description 000 336 11.2.3 reset control/status register (rstcsr) rstcsr is an 8-bit readable and writable register that indicates when a reset signal has been generated by watchdog timer overflow, and controls external output of the reset signal. bit initial value read/write 7 wrst 0 r/(w) 6 rstoe 0 r/w 5 1 4 1 3 1 0 1 2 1 1 1 * watchdog timer reset indicates that a reset signal has been generated reserved bits reset output enable enables or disables external output of the reset signal notes: the method for writing to rstcsr is different from that for general registers to prevent inadvertent overwriting. for details see section 11.2.4, notes on register access. * only 0 can be written in bit 7, to clear the flag. bits 7 and 6 are initialized by input of a reset signal at the res pin. they are not initialized by reset signals generated by watchdog timer overflow. bit 7?atchdog timer reset (wrst): during watchdog timer operation, this bit indicates that tcnt has overflowed and generated a reset signal. this reset signal resets the entire h8/3024 chip internally. if bit rstoe is set to 1, this reset signal is also output (low) at the reso pin to initialize external system devices. note that there is no reso pin in the versions with on-chip flash memory. bit 7 wrst description 0 [clearing conditions] ? res ? 337 bit 6?eset output enable (rstoe): enables or disables external output at the reso pin of the reset signal generated if tcnt overflows during watchdog timer operation. note that there is no reso pin in the versions with on-chip flash memory. bit 6 rstoe description 0 reset signal is not output externally (initial value) 1 reset signal is output externally bits 5 to 0?eserved: these bits cannot be modified and are always read as 1. 11.2.4 notes on register access the watchdog timer? tcnt, tcsr, and rstcsr registers differ from other registers in being more difficult to write. the procedures for writing and reading these registers are given below. writing to tcnt and tcsr: these registers must be written by a word transfer instruction. they cannot be written by byte instructions. figure 11.2 shows the format of data written to tcnt and tcsr. tcnt and tcsr both have the same write address. the write data must be contained in the lower byte of the written word. the upper byte must contain h'5a (password for tcnt) or h'a5 (password for tcsr). this transfers the write data from the lower byte to tcnt or tcsr. 15 8 7 0 h'5a write data address h'fff8c * 15 8 7 0 h'a5 write data address h'fff8c * tcnt write tcsr write note: lower 20 bits of the address in advanced mode. * figure 11.2 format of data written to tcnt and tcsr 338 writing to rstcsr: rstcsr must be written by a word transfer instruction. it cannot be written by byte transfer instructions. figure 11.3 shows the format of data written to rstcsr. to write 0 in the wrst bit, the write data must have h'a5 in the upper byte and h'00 in the lower byte. the data (h'00) in the lower byte is written to rstcsr, clearing the wrst bit to 0. to write to the rstoe bit, the upper byte must contain h'5a and the lower byte must contain the write data. writing this word transfers a write data value into the rstoe bit. 15 8 7 0 h'a5 h'00 address h'fff8e* 15 8 7 0 h'5a write data address h'fff8e* writing 0 in wrst bit writing to rstoe bit note: lower 20 bits of the address in advanced mode. * figure 11.3 format of data written to rstcsr reading tcnt, tcsr, and rstcsr: for reads of tcnt, tcsr, and rstcsr, address h'fff8c is assigned to tcsr, address h'fff8d to tcnt, and address h'fff8f to rstcsr. these registers are therefore read like other registers. byte transfer instructions can be used for reading. table 11.3 lists the read addresses of tcnt, tcsr, and rstcsr. table 11.3 read addresses of tcnt, tcsr, and rstcsr address* register h'fff8c tcsr h'fff8d tcnt h'fff8f rstcsr note: * lower 20 bits of the address in advanced mode. 339 11.3 operation operations when the wdt is used as a watchdog timer and as an interval timer are described below. 11.3.1 watchdog timer operation figure 11.4 illustrates watchdog timer operation. to use the wdt as a watchdog timer, set the wt/ it and tme bits to 1 in tcsr. software must prevent tcnt overflow by rewriting the tcnt value (normally by writing h'00) before overflow occurs. if tcnt fails to be rewritten and overflows due to a system crash etc., the h8/3024 is internally reset for a duration of 518 states. the watchdog reset signal can be externally output from the reso pin to reset external system devices. the reset signal is output externally for 132 states. external output can be enabled or disabled by the rstoe bit in rstcsr. note that there is no reso pin in the versions with on- chip flash memory. a watchdog reset has the same vector as a reset generated by input at the res pin. software can distinguish a res reset from a watchdog reset by checking the wrst bit in rstcsr. if a res reset and a watchdog reset occur simultaneously, the res reset takes priority. h 'ff h '00 r eso figure 11.4 operation in watchdog timer mode 340 11.3.2 interval timer operation figure 11.5 illustrates interval timer operation. to use the wdt as an interval timer, clear bit wt/ it to 0 and set bit tme to 1 in tcsr. an interval timer interrupt request is generated at each tcnt overflow. this function can be used to generate interval timer interrupts at regular intervals. tcnt count value time t interval timer interrupt interval timer interrupt interval timer interrupt interval timer interrupt wt/ = 0 tme = 1 it figure 11.5 interval timer operation 11.3.3 timing of setting of overflow flag (ovf) figure 11.6 shows the timing of setting of the ovf flag. the ovf flag is set to 1 when tcnt overflows. at the same time, a reset signal is generated in watchdog timer operation, or an interval timer interrupt is generated in interval timer operation. figure 11.6 timing of setting of ovf 341 11.3.4 timing of setting of watchdog timer reset bit (wrst) the wrst bit in rstcsr is valid when bits wt/ it and tme are both set to 1 in tcsr. figure 11.7 shows the timing of setting of wrst and the internal reset timing. the wrst bit is set to 1 when tcnt overflows and ovf is set to 1. at the same time an internal reset signal is generated for the entire h8/3024 chip. this internal reset signal clears ovf to 0, but the wrst bit remains set to 1. the reset routine must therefore clear the wrst bit. figure 11.7 timing of setting of wrst bit and internal reset 342 11.4 interrupts during interval timer operation, an overflow generates an interval timer interrupt (wovi). the interval timer interrupt is requested whenever the ovf flag is set to 1 in tcsr. 11.5 usage notes contention between tcnt write and increment: if a timer counter clock pulse is generated during the t 3 state of a write cycle to tcnt, the write takes priority and the timer count is not incremented. see figure 11.8. figure 11.8 contention between tcnt write and count up changing cks2 to cks0 bit: halt tcnt by clearing the tme bit to 0 in tcsr before changing the values of bits cks2 to cks0. 343 section 12 serial communication interface 12.1 overview the h8/3024 series has a serial communication interface (sci) with two independent channels. the two channels have identical functions. the sci can communicate in both asynchronous and synchronous mode. it also has a multiprocessor communication function for serial communication among two or more processors. when the sci is not used, it can be halted to conserve power. each sci channel can be halted independently. for details, see section 20.6, module standby function. the sci also has a smart card interface function conforming to the iso/iec 7816-3 (identification card) standard. this function supports serial communication with a smart card. switching between the normal serial communication interface and the smart card interface is carried out by means of a register setting. 12.1.1 features sci features are listed below. ? selection of synchronous or asynchronous mode for serial communication asynchronous mode serial data communication is synchronized one character at a time. the sci can communicate with a universal asynchronous receiver/transmitter (uart), asynchronous communication interface adapter (acia), or other chip that employs standard asynchronous communication. it can also communicate with two or more other processors using the multiprocessor communication function. there are twelve selectable serial data transfer formats. ? data length: 7 or 8 bits ? stop bit length: 1 or 2 bits ? parity: even/odd/none ? multiprocessor bit: 1 or 0 ? receive error detection: parity, overrun, and framing errors ? break detection: by reading the rxd level directly when a framing error occurs synchronous mode serial data communication is synchronized with a clock signal. the sci can communicate with other chips having a synchronous communication function. there is a single serial data communication format. ? data length: 8 bits ? receive error detection: overrun errors 344 ? full-duplex communication the transmitting and receiving sections are independent, so the sci can transmit and receive simultaneously. the transmitting and receiving sections are both double-buffered, so serial data can be transmitted and received continuously. ? the following settings can be made for the serial data to be transferred: ? lsb-first or msb-first transfer ? inversion of data logic level ? built-in baud rate generator with selectable bit rates ? selectable transmit/receive clock sources: internal clock from baud rate generator, or external clock from the sck pin ? four types of interrupts transmit-data-empty, transmit-end, receive-data-full, and receive-error interrupts are requested independently. features of the smart card interface are listed below. ? asynchronous communication ? data length: 8 bits ? parity bits generated and checked ? error signal output in receive mode (parity error) ? error signal detect and automatic data retransmit in transmit mode ? supports both direct convention and inverse convention ? built-in baud rate generator with selectable bit rates ? three types of interrupts transmit-data-empty, receive-data-full, and transmit/receive-error interrupts are requested independently. 345 12.1.2 block diagram figure 12.1 shows a block diagram of the sci. rdr rsr tdr tsr ssr scr smr scmr brr figure 12.1 sci block diagram 346 12.1.3 pin configuration the sci has serial pins for each channel as listed in table 12.1. table 12.1 sci pins channel name abbreviation i/o function 0 serial clock pin sck 0 input/output sci 0 clock input/output receive data pin rxd 0 input sci 0 receive data input transmit data pin txd 0 output sci 0 transmit data output 1 serial clock pin sck 1 input/output sci 1 clock input/output receive data pin rxd 1 input sci 1 receive data input transmit data pin txd 1 output sci 1 transmit data output 347 12.1.4 register configuration the sci has internal registers as listed in table 12.2. these registers select asynchronous or synchronous mode, specify the data format and bit rate, control the transmitter and receiver sections, and specify switching between the serial communication interface and smart card interface. table 12.2 sci registers channel address* 1 name abbreviation r/w initial value 0 h?fffb0 serial mode register smr r/w h'00 h?fffb1 bit rate register brr r/w h'ff h?fffb2 serial control register scr r/w h'00 h?fffb3 transmit data register tdr r/w h'ff h?fffb4 serial status register ssr r/(w)* 2 h'84 h?fffb5 receive data register rdr r h'00 h?fffb6 smart card mode register scmr r/w h'f2 1 h?fffb8 serial mode register smr r/w h'00 h?fffb9 bit rate register brr r/w h'ff h?fffba serial control register scr r/w h'00 h?fffbb transmit data register tdr r/w h'ff h?fffbc serial status register ssr r/(w)* 2 h'84 h?fffbd receive data register rdr r h'00 h?fffbe smart card mode register scmr r/w h'f2 notes: *1 indicates the lower 20 bits of the address in advanced mode. *2 only 0 can be written, to clear flags. 348 12.2 register descriptions 12.2.1 receive shift register (rsr) rsr is the register that receives serial data. bit 7 6 5 4 3 2 1 0 read/write the sci loads serial data input at the rxd pin into rsr in the order received, lsb (bit 0) first, thereby converting the data to parallel data. when one byte of data has been received, it is automatically transferred to rdr. the cpu cannot read or write rsr directly. 12.2.2 receive data register (rdr) rdr is the register that stores received serial data. bit 7654321 0 initial value read/write r 0 0000 0 0 0 r r r r r r r when the sci has received one byte of serial data, it transfers the received data from rsr into rdr for storage, completing the receive operation. rsr is then ready to receive the next data. this double-buffering allows data to be received continuously. rdr is a read-only register. its contents cannot be modified by the cpu. rdr is initialized to h'00 by a reset and in standby mode. 349 12.2.3 transmit shift register (tsr) tsr is the register that transmits serial data. bit 7 6 5 4 3 2 1 0 read/write the sci loads transmit data from tdr to tsr, then transmits the data serially from the txd pin, lsb (bit 0) first. after transmitting one data byte, the sci automatically loads the next transmit data from tdr into tsr and starts transmitting it. if the tdre flag is set to 1 in ssr, however, the sci does not load the tdr contents into tsr. the cpu cannot read or write rsr directly. 12.2.4 transmit data register (tdr) tdr is an 8-bit register that stores data for serial transmission. bit 7 6 54 3 2 1 0 initial value read/write r/w 11 1111 11 r/w r/w r/w r/w r/w r/w r/w when the sci detects that tsr is empty, it moves transmit data written in tdr from tdr into tsr and starts serial transmission. continuous serial transmission is possible by writing the next transmit data in tdr during serial transmission from tsr. the cpu can always read and write tdr. tdr is initialized to h'ff by a reset and in standby mode. 350 12.2.5 serial mode register (smr) smr is an 8-bit register that specifies the sci's serial communication format and selects the clock source for the baud rate generator. c/ a e clock select 1/0 these bits select the baud rate generator's clock source communication mode selects asynchronous or synchronous mode character length selects character length in asynchronous mode parity enable selects whether a parity bit is added parity mode selects even or odd parity stop bit length selects the stop bit length multiprocessor mode selects the multiprocessor function the cpu can always read and write smr. smr is initialized to h'00 by a reset and in standby mode. bit 7?ommunication mode (c/ a )/gsm mode (gm): the function of this bit differs for the normal serial communication interface and for the smart card interface. its function is switched with the smif bit in scmr. for serial communication interface (smif bit in scmr cleared to 0): selects whether the sci operates in asynchronous or synchronous mode. 351 bit 7 c/ a description 0 asynchronous mode (initial value) 1 synchronous mode for smart card interface (smif bit in scmr set to 1): selects gsm mode for the smart card interface. bit 7 gm description 0 the tend flag is set 12.5 etu after the start bit (initial value) 1 the tend flag is set 11.0 etu after the start bit note: etu: elementary time unit (time required to transmit one bit) bit 6?haracter length (chr): selects 7-bit or 8-bits data length in asynchronous mode. in synchronous mode, the data length is 8 bits regardless of the chr setting. bit 6 chr description 0 8-bit data (initial value) 1 7-bit data* note: * when 7-bit data is selected, the msb (bit 7) of tdr is not transmitted. bit 5?arity enable (pe): in asynchronous mode, this bit enables or disables the addition of a parity bit to transmit data, and the checking of the parity bit in receive data. in synchronous mode, the parity bit is neither added nor checked, regardless of the pe bit setting. bit 5 pe description 0 parity bit not added or checked (initial value) 1 parity bit added and checked* note: * when pe bit is set to 1, an even or odd parity bit is added to transmit data according to the even or odd parity mode selection by the o/ e e bit 4?arity mode (o/ e ): specifies whether even parity or odd parity is used for parity addition and checking. the o/ e bit setting is only valid when the pe bit is set to 1, enabling parity bit addition and checking, in asynchronous mode. the o/ e bit setting is ignored in synchronous mode, or when parity addition and checking is disabled in asynchronous mode. 352 bit 4 o/ e description 0 even parity* 1 (initial value) 1 odd parity* 2 notes: *1 when even parity is selected, the parity bit added to transmit data makes an even number of 1s in the transmitted character and parity bit combined. receive data must have an even number of 1s in the received character and parity bit combined. *2 when odd parity is selected, the parity bit added to transmit data makes an odd number of 1s in the transmitted character and parity bit combined. receive data must have an odd number of 1s in the received character and parity bit combined. bit 3?top bit length (stop): selects one or two stop bits in asynchronous mode. this setting is used only in asynchronous mode. in synchronous mod no stop bit is added, so the stop bit setting is ignored. bit 3 stop description 0 1 stop bit* 1 (initial value) 1 2 stop bits* 2 notes: *1 one stop bit (with value 1) is added to the end of each transmitted character. *2 two stop bits (with value 1) are added to the end of each transmitted character. in receiving, only the first stop bit is checked, regardless of the stop bit setting. if the second stop bit is 1, it is treated as a stop bit. if the second stop bit is 0, it is treated as the start bit of the next incoming character. bit 2?ultiprocessor mode (mp): selects a multiprocessor format. when a multiprocessor format is selected, parity settings made by the pe and o/ e bits are ignored. the mp bit setting is valid only in asynchronous mode. it is ignored in synchronous mode. for further information on the multiprocessor communication function, see section 12.3.3, multiprocessor communication. bit 2 mp description 0 multiprocessor function disabled (initial value) 1 multiprocessor format selected bits 1 and 0?lock select 1 and 0 (cks1, cks0): these bits select the clock source for the on- chip baud rate generator. four clock sources can be selected by the cks1 and cks0 bits: ? ?4, ?16, and ?64. 353 for the relationship between the clock source, bit rate register setting, and baud rate, see section 12.2.8, bit rate register (brr). bit 1 cks1 bit 0 cks0 description 00 12.2.6 serial control register (scr) scr register enables or disables the sci transmitter and receiver, enables or disables serial clock output in asynchronous mode, enables or disables interrupts, and selects the transmit/receive clock source. bit 7 6 5 4 3210 tie rie te re mpie teie cke1 cke0 initial value read/write r/w 0 00000 0 0 r/w r/w r/w r/w r/w r/w r/w transmit-end interrupt enable enables or disables transmit-end interrupts (tei) multiprocessor interrupt enable enables or disables multiprocessor interrupts receive enable enables or disables the receiver transmit enable enables or disables the transmitter receive interrupt enable enables or disables receive-data-full interrupts (rxi) and receive-error interrupts (eri) transmit interrupt enable enables or disables transmit-data-empty interrupts (txi) clock enable 1/0 these bits select the sci clock source 354 the cpu can always read and write scr. scr is initialized to h'00 by a reset and in standby mode. bit 7?ransmit interrupt enable (tie): enables or disables the transmit-data-empty interrupt (txi) requested when the tdre flag in ssr is set to 1 due to transfer of serial transmit data from tdr to tsr. bit 7 tie description 0 transmit-data-empty interrupt request (txi) is disabled* (initial value) 1 transmit-data-empty interrupt request (txi) is enabled note: * txi interrupt requests can be cleared by reading the value 1 from the tdre flag, then clearing it to 0; or by clearing the tie bit to 0. bit 6?eceive interrupt enable (rie): enables or disables the receive-data-full interrupt (rxi) requested when the rdrf flag in ssr is set to 1 due to transfer of serial receive data from rsr to rdr; also enables or disables the receive-error interrupt (eri). bit 6 rie description 0 receive-data-full (rxi) and receive-error (eri) interrupt requests are disabled* (initial value) 1 receive-data-full (rxi) and receive-error (eri) interrupt requests are enabled note: * rxi and eri interrupt requests can be cleared by reading the value 1 from the rdrf, fer, per, or orer flag, then clearing the flag to 0; or by clearing the rie bit to 0. bit 5?ransmit enable (te): enables or disables the start of sci serial transmitting operations. bit 5 te description 0 transmitting disabled* 1 (initial value) 1 transmitting enabled* 2 notes: *1 the tdre flag is fixed at 1 in ssr. *2 in the enabled state, serial transmission starts when the tdre flag in ssr is cleared to 0 after writing of transmit data into tdr. select the transmit format in smr before setting the te bit to 1. bit 4?eceive enable (re): enables or disables the start of sci serial receiving operations. 355 bit 4 re description 0 receiving disabled* 1 (initial value) 1 receiving enabled* 2 notes: *1 clearing the re bit to 0 does not affect the rdrf, fer, per, and orer flags. these flags retain their previous values. *2 in the enabled state, serial receiving starts when a start bit is detected in asynchronous mode, or serial clock input is detected in synchronous mode. select the receive format in smr before setting the re bit to 1. bit 3?ultiprocessor interrupt enable (mpie): enables or disables multiprocessor interrupts. the mpie bit setting is valid only in asynchronous mode, and only if the mp bit is set to 1 in smr. the mpie bit setting is ignored in synchronous mode or when the mp bit is cleared to 0. bit 3 mpie description 0 multiprocessor interrupts are disabled (normal receive operation) (initial value) [clearing conditions] ? ? bit 2?ransmit-end interrupt enable (teie): enables or disables the transmit-end interrupt (tei) requested if tdr does not contain valid transmit data when the msb is transmitted. bit 2 teie description 0 transmit-end interrupt requests (tei) are disabled* (initial value) 1 transmit-end interrupt requests (tei) are enabled* note: * tei interrupt requests can be cleared by reading the value 1 from the tdre flag in ssr, then clearing the tdre flag to 0, thereby also clearing the tend flag to 0; or by clearing the teie bit to 0. bits 1 and 0?lock enable 1 and 0 (cke1, cke0): the function of these bits differs for the normal serial communication interface and for the smart card interface. their function is switched with the smif bit in scmr. 356 for serial communication interface (smif bit in scmr cleared to 0): these bits select the sci clock source and enable or disable clock output from the sck pin. depending on the settings of cke1 and cke0, the sck pin can be used for generic input/output, serial clock output, or serial clock input. the cke0 setting is valid only in asynchronous mode, and only when the sci is internally clocked (cke1 = 0). the cke0 setting is ignored in synchronous mode, or when an external clock source is selected (cke1 = 1). select the sci operating mode in smr before setting the cke1 and cke0 bits . for further details on selection of the sci clock source, see table 12.9 in section 12.3, operation. bit 1 cke1 bit 0 cke0 description 0 0 asynchronous mode internal clock, sck pin available for generic input/output* 1 synchronous mode internal clock, sck pin used for serial clock output* 1 0 1 asynchronous mode internal clock, sck pin used for clock output* 2 synchronous mode internal clock, sck pin used for serial clock output 1 0 asynchronous mode external clock, sck pin used for clock input* 3 synchronous mode external clock, sck pin used for serial clock input 1 1 asynchronous mode external clock, sck pin used for clock input* 3 synchronous mode external clock, sck pin used for serial clock input notes: *1 initial value *2 the output clock frequency is the same as the bit rate. *3 the input clock frequency is 16 times the bit rate. for smart card interface (smif bit in scmr set to 1): these bits, together with the gm bit in smr, determine whether the sck pin is used for generic input/output or as the serial clock output pin. smr gm bit 1 cke1 bit 0 cke0 description 0 0 0 sck pin available for generic input/output (initial value) 0 0 1 sck pin used for clock output 1 0 0 sck pin output fixed low 1 0 1 sck pin used for clock output 1 1 0 sck pin output fixed high 1 1 1 sck pin used for clock output 357 12.2.7 serial status register (ssr) ssr is an 8-bit register containing multiprocessor bit values, and status flags that indicate the operating status of the sci. initial value read/write r r/w 0 1000100 bit 76 54 32 1 0 multiprocessor bit transfer value of multiprocessor bit to be transmitted r/(w)* 1 r/(w)* 1 r/(w)* 1 r/(w)* 1 r/(w)* 1 r tdre rdrf orer fer/ers per tend mpb mpbt multiprocessor bit stores the received multiprocessor bit value transmit end * 2 status flag indicating end of transmission parity error status flag indicating detection of a receive parity error framing error (fer)/error signal status (ers) * 2 status flag indicating detection of a receive framing error, or flag indicating detection of an error signal overrun error status flag indicating detection of a receive overrun error receive data register full status flag indicating that data has been received and stored in rdr transmit data register empty status flag indicating that transmit data has been transferred from tdr into tsr and new data can be written in tdr notes: *1 only 0 can be written, to clear the flag. *2 function differs between the normal serial communication interface and the smart card interface. the cpu can always read and write ssr, but cannot write 1 in the tdre, rdrf, orer, per, and fer flags. these flags can be cleared to 0 only if they have first been read while set to 1. the tend and mpb flags are read-only bits that cannot be written. ssr is initialized to h'84 by a reset and in standby mode. 358 bit 7?ransmit data register empty (tdre): indicates that the sci has loaded transmit data from tdr into tsr and the next serial data can be written in tdr. bit 7 tdre description 0 tdr contains valid transmit data [clearing condition] read tdre when tdre = 1, then write 0 in tdre 1 tdr does not contain valid transmit data (initial value) [setting conditions] ? ? ? bit 6?eceive data register full (rdrf): indicates that rdr contains new receive data. bit 6 rdrf description 0 rdr does not contain new receive data (initial value) [clearing conditions] ? ? 359 bit 5?verrun error (orer): indicates that data reception ended abnormally due to an overrun error. bit 5 orer description 0 receiving is in progress or has ended normally* 1 (initial value) [clearing conditions] ? ? bit 4?raming error (fer)/error signal status (ers): the function of this bit differs for the normal serial communication interface and for the smart card interface. its function is switched with the smif bit in scmr. for serial communication interface (smif bit in scmr cleared to 0): indicates that data reception ended abnormally due to a framing error in asynchronous mode. bit 4 fer description 0 receiving is in progress or has ended normally* 1 (initial value) [clearing conditions] ? ? 360 for smart card interface (smif bit in scmr set to 1): indicates the status of the error signal sent back from the receiving side during transmission. framing errors are not detected in smart card interface mode. bit 4 ers description 0 normal reception, no error signal* (initial value) [clearing conditions] ? ? bit 3?arity error (per): indicates that reception of data with parity added ended abnormally due to a parity error in asynchronous mode. bit 3 per description 0 receiving is in progress or has ended normally* 1 (initial value) [clearing conditions] ? ? e bit 2?ransmit end (tend): the function of this bit differs for the normal serial communication interface and for the smart card interface. its function is switched with the smif bit in scmr. for serial communication interface (smif bit in scmr cleared to 0): indicates that when the last bit of a serial character was transmitted tdr did not contain valid transmit data, so transmission has ended. the tend flag is a read-only bit and cannot be written. 361 bit 2 tend description 0 transmission is in progress [clearing condition] read tdre when tdre = 1, then write 0 in tdre 1 end of transmission (initial value) [setting conditions] ? ? ? for smart card interface (smif bit in scmr set to 1): indicates that when the last bit of a serial character was transmitted tdr did not contain valid transmit data, so transmission has ended. the tend flag is a read-only bit and cannot be written. bit 2 tend description 0 transmission is in progress [clearing condition] read tdre when tdre = 1, then write 0 in tdre 1 end of transmission (initial value) [setting conditions] ? ? ? bit 1?ultiprocessor bit (mpb): stores the value of the multiprocessor bit in the receive data when a multiprocessor format is used in asynchronous mode. mpb is a read-only bit, and cannot be written. bit 1 mpb description 0 multiprocessor bit value in receive data is 0* (initial value) 1 multiprocessor bit value in receive data is 1 note: * if the re bit in scr is cleared to 0 when a multiprocessor format is selected, mpb retains its previous value. 362 bit 0?ultiprocessor bit transfer (mpbt): stores the value of the multiprocessor bit added to transmit data when a multiprocessor format in selected for transmitting in asynchronous mode. the mpbt bit setting is ignored in synchronous mode, when a multiprocessor format is not selected, or when the sci cannot transmit. bit 0 mpbt description 0 multiprocessor bit value in transmit data is 0 (initial value) 1 multiprocessor bit value in transmit data is 1 12.2.8 bit rate register (brr) brr is an 8-bit register that sets the serial transmit/receive bit rate in accordance with the baud rate generator operating clock selected by bits cks0 and cks1 in smr. bit initial value read/write 7 r/w r/w r/w r/w r/w r/w r/w r/w 6 1 11 1 11 11 5 4 32 1 0 brr can be read or written to by the cpu at all times. brr is initialized to h'ff by a reset and in standby mode. as baud rate generator control is performed independently for each channel, different values can be set for each channel. table 12.3 shows examples of brr settings in asynchronous mode. table 12.4 shows examples of brr settings in synchronous mode. 363 table 12.3 examples of bit rates and brr settings in asynchronous mode (mhz) bit rate 2 2.097152 2.4576 3 (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 1 141 0.03 1 148 -0.04 1 174 -0.26 1 212 0.03 150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16 300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16 600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16 1200 0 51 0.16 0 54 -0.70 0 63 0.00 0 77 0.16 2400 0 25 0.16 0 26 1.14 0 31 0.00 0 38 0.16 4800 0 12 0.16 0 13 -2.48 0 15 0.00 0 19 -2.34 9600 0 6 -6.99 0 6 -2.48 0 7 0.00 0 9 -2.34 19200 0 2 8.51 0 2 13.78 0 3 0.00 0 4 -2.34 31250 0 1 0.00 0 1 4.86 0 1 22.88 0 2 0.00 38400 0 1 -18.62 0 1 -14.67 0 1 0.00 ?? ? (mhz) bit rate 3.6864 4 4.9152 5 (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 -0.25 150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 -1.36 9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73 19200 0 5 0.00 0 6 -6.99 0 7 0.00 0 7 1.73 31250 ??? 0 3 0.00 0 4 -1.70 0 4 0.00 38400 0 2 0.00 0 2 8.51 0 3 0.00 0 3 1.73 364 (mhz) bit rate 6 6.144 7.3728 8 (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 106 -0.44 2 108 0.08 2 130 -0.07 2 141 0.03 150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16 300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16 600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16 1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16 2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16 4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16 9600 0 19 -2.34 0 19 0.00 0 23 0.00 0 25 0.16 19200 0 9 -2.34 0 9 0.00 0 11 0.00 0 12 0.16 31250 0 5 0.00 0 5 2.40 0 6 5.33 0 7 0.00 38400 0 4 -2.34 0 4 0.00 0 5 0.00 0 6 -6.99 (mhz) bit rate 9.8304 10 12 12.288 (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 174 -0.26 2 177 -0.25 2 212 0.03 2 217 0.08 150 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00 300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00 600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00 1200 0 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00 2400 0 127 0.00 0 129 0.16 0 155 0.16 0 159 0.00 4800 0 63 0.00 0 64 0.16 0 77 0.16 0 79 0.00 9600 0 31 0.00 0 32 -1.36 0 38 0.16 0 39 0.00 19200 0 15 0.00 0 15 1.73 0 19 -2.34 0 19 0.00 31250 0 9 -1.70 0 9 0.00 0 11 0.00 0 11 2.40 38400 0 7 0.00 0 7 1.73 0 9 -2.34 0 9 0.00 365 (mhz) bit rate 13 14 14.7456 16 (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 230 -0.08 2 248 -0.17 3 64 0.70 3 70 0.03 150 2 168 0.16 2 181 0.16 2 191 0.00 2 207 0.16 300 2 84 -0.43 2 90 0.16 2 95 0.00 2 103 0.16 600 1 168 0.16 1 181 0.16 1 191 0.00 1 207 0.16 1200 1 84 -0.43 1 90 0.16 1 95 0.00 1 103 0.16 2400 0 168 0.16 0 181 0.16 0 191 0.00 0 207 0.16 4800 0 84 -0.43 0 90 0.16 0 95 0.00 0 103 0.16 9600 0 41 0.76 0 45 -0.93 0 47 0.00 0 51 0.16 19200 0 20 0.76 0 22 -0.93 0 23 0.00 0 25 0.16 31250 0 12 0.00 0 13 0.00 0 14 -1.70 0 15 0.00 38400 0 10 -3.82 0 10 3.57 0 11 0.00 0 12 0.16 (mhz) bit rate 18 20 25 (bit/s) n n error (%) n n error (%) n n error (%) 110 3 79 -0.12 3 88 -0.25 3 110 -0.02 150 2 233 0.16 3 64 0.16 3 80 -0.47 300 2 116 0.16 2 129 0.16 2 162 0.15 600 1 233 0.16 2 64 0.16 2 80 -0.47 1200 1 116 0.16 1 129 0.16 1 162 0.15 2400 0 233 0.16 1 64 0.16 1 80 -0.47 4800 0 116 0.16 0 129 0.16 0 162 0.15 9600 0 58 -0.69 0 64 0.16 0 80 -0.47 19200 0 28 1.02 0 32 -1.36 0 40 -0.76 31250 0 17 0.00 0 19 0.00 0 24 0.00 38400 0 14 -2.34 0 15 1.73 0 19 1.73 366 table 12.4 examples of bit rates and brr settings in synchronous mode bit (mhz) rate 2 4 8 10 13 16 18 20 25 (bit/s) n n n n n n n n n n n n n n n n n n 110 3 70 ? ? ? ? ?? ?? ?? ?? ?? ? ? 250 2 124 2 249 3 124 ?? 3 202 3 249 ?? ?? ? ? 500 1 249 2 124 2 249 ?? 3 101 3 124 3 140 3 155 ?? 1k 1 124 1 249 2 124 ?? 2 202 2 249 3 69 3 77 3 97 2.5k 0 199 1 99 1 199 1 249 2 80 2 99 2 112 2 124 2 155 5k 0 99 0 199 1 99 1 124 1 162 1 199 1 224 1 249 2 77 10k 0 49 0 99 0 199 0 249 1 80 1 99 1 112 1 124 1 155 25k 0 19 0 39 0 79 0 99 0 129 0 159 0 179 0 199 0 249 50k 0 9 0 19 0 39 0 49 0 64 0 79 0 89 0 99 0 124 100k 0 4 0 9 0 19 0 24 ?? 0390440490 62 250k 0 1 0 3 0 7 0 9 0 12 0 15 0 17 0 19 0 24 500k 0 0* 0 1 0 3 0 4 ?? 07 08 09 ?? 1m 0 0* 0 1 ?? ?? 03 04 04 ?? 2m 0 0* ?? ?? 01 ?? ?? ? ? 2.5m ?? 00* ?? ?? ?? ?? ? ? 4m 0 0* ?? ?? ? ? note: settings with an error of 1% or less are recommended. legend blank: no setting available ? : setting possible, but error occurs *: continuous transmission/reception not possible 367 the brr setting is calculated as follows: asynchronous mode: n = 64 synchronous mode: n = 8 b: bit rate (bit/s) n: brr setting for baud rate generator (0 n 255) : system clock frequency (mhz) n: baud rate generator input clock (n = 0, 1, 2, 3) (for the clock sources and values of n, see the following table.) smr settings n clock source cks1 cks0 0 the bit rate error in asynchronous mode is calculated as follows: error (%) = (n + 1) 368 table 12.5 shows the maximum bit rates in asynchronous mode for various system clock frequencies. tables 12.6 and 12.7 show the maximum bit rates with external clock input. table 12.5 maximum bit rates for various frequencies (asynchronous mode) settings (mhz) maximum bit rate (bit/s) n n 2 62500 0 0 2.097152 65536 0 0 2.4576 76800 0 0 3 93750 0 0 3.6864 115200 0 0 4 125000 0 0 4.9152 153600 0 0 5 156250 0 0 6 187500 0 0 6.144 192000 0 0 7.3728 230400 0 0 8 250000 0 0 9.8304 307200 0 0 10 312500 0 0 12 375000 0 0 12.288 384000 0 0 14 437500 0 0 14.7456 460800 0 0 16 500000 0 0 17.2032 537600 0 0 18 562500 0 0 20 625000 0 0 25 781250 0 0 369 table 12.6 maximum bit rates with external clock input (asynchronous mode) (mhz) external input clock (mhz) maximum bit rate (bit/s) 2 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 3 0.7500 46875 3.6864 0.9216 57600 4 1.0000 62500 4.9152 1.2288 76800 5 1.2500 78125 6 1.5000 93750 6.144 1.5360 96000 7.3728 1.8432 115200 8 2.0000 125000 9.8304 2.4576 153600 10 2.5000 156250 12 3.0000 187500 12.288 3.0720 192000 14 3.5000 218750 14.7456 3.6864 230400 16 4.0000 250000 17.2032 4.3008 268800 18 4.5000 281250 20 5.0000 312500 25 6.2500 390625 370 table 12.7 maximum bit rates with external clock input (synchronous mode) (mhz) external input clock (mhz) maximum bit rate (bit/s) 2 0.3333 333333.3 4 0.6667 666666.7 6 1.0000 1000000.0 8 1.3333 1333333.3 10 1.6667 1666666.7 12 2.0000 2000000.0 14 2.3333 2333333.3 16 2.6667 2666666.7 18 3.0000 3000000.0 20 3.3333 3333333.3 25 4.1667 4166666.7 12.3 operation 12.3.1 overview the sci can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and synchronous mode in which synchronization is achieved with clock pulses. a smart card interface is also supported as a serial communication function for an ic card interface. selection of asynchronous or synchronous mode and the transmission format for the normal serial communication interface is made in smr, as shown in table 12.8. the sci clock source is selected by the c/ a bit in smr and the cke1 and cke0 bits in scr, as shown in table 12.9. for details of the procedures for switching between lsb-first and msb-first mode and inverting the data logic level, see section 13.2.1, smart card mode register (scmr). for selection of the smart card interface format, see section 13.3.3, data format. 371 asynchronous mode ? data length is selectable: 7 or 8 bits ? parity and multiprocessor bits are selectable, and so is the stop bit length (1 or 2 bits). these selections determine the communication format and character length. ? in receiving, it is possible to detect framing errors, parity errors, overrun errors, and the break state. ? an internal or external clock can be selected as the sci clock source. ? when an internal clock is selected, the sci operates using the on-chip baud rate generator, and can output a serial clock signal with a frequency matching the bit rate. ? when an external clock is selected, the external clock input must have a frequency 16 times the bit rate. (the on-chip baud rate generator is not used.) synchronous mode ? the communication format has a fixed 8-bit data length. ? in receiving, it is possible to detect overrun errors. ? an internal or external clock can be selected as the sci clock source. ? when an internal clock is selected, the sci operates using the on-chip baud rate generator, and can output a serial clock signal to external devices. ? when an external clock is selected, the sci operates on the input serial clock. the on-chip baud rate generator is not used. smart card interface ? one frame consists of 8-bit data and a parity bit. ? in transmitting, a guard time of at least two elementary time units (2 etu) is provided between the end of the parity bit and the start of he next frame. (an elementary time unit is the time required to transmit one bit.) ? in receiving, if a parity error is detected, a low error signal level is output for 1 etu, beginning 10.5 etu after the start bit.. ? in transmitting, if an error signal is received, the same data is automatically transmitted again after at least 2 etu. ? only asynchronous communication is supported. there is no synchronous communication function. for details of smart card interface operation, see section 13, smart card interface. 372 table 12.8 smr settings and serial communication formats smr settings sci communication format bit 7 c/ a bit 6 chr bit 2 mp bit 5 pe bit 3 stop mode data length multi- pro- cessor bit parity bit stop bit length 0 0 0 0 0 asyn- 8-bit data absent absent 1 bit 1 chronous 2 bits 10 mode present 1 bit 1 2 bits 1 0 0 7-bit data absent 1 bit 1 2 bits 1 0 present 1 bit 1 2 bits 01 ? 0 asyn- chronous 8-bit data present absent 1 bit ? 1 mode (multi- 2 bits 1 ? 0 processor 7-bit data 1 bit ? 1 format) 2 bits 1 ?? ?? syn- chronous mode 8-bit data absent none table 12.9 smr and scr settings and sci clock source selection smr scr setting sci transmit/receive clock bit 7 c/ a bit 1 cke1 bit 0 cke0 mode clock source sck pin function 0 0 0 asynchronous internal sci does not use the sck pin 1 mode outputs clock with frequency matching the bit rate 1 0 external inputs clock with frequency 16 times the bit 1 rate 1 0 0 synchronous internal outputs the serial clock 1 mode 1 0 external inputs the serial clock 1 373 12.3.2 operation in asynchronous mode in asynchronous mode, each transmitted or received character begins with a start bit and ends with one or two stop bits. serial communication is synchronized one character at a time. the transmitting and receiving sections of the sci are independent, so full-duplex communication is possible. the transmitter and the receiver are both double-buffered, so data can be written and read while transmitting and receiving are in progress, enabling continuous transmitting and receiving. figure 12.2 shows the general format of asynchronous serial communication. in asynchronous serial communication the communication line is normally held in the mark (high) state. the sci monitors the line and starts serial communication when the line goes to the space (low) state, indicating a start bit. one serial character consists of a start bit (low), data (lsb first), parity bit (high or low), and one or two stop bits (high), in that order. when receiving in asynchronous mode, the sci synchronizes at the falling edge of the start bit. the sci samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate. receive data is latched at the center of each bit. 1 d0 d1 d2 d3 d4 d5 d6 d7 0/1 1 idle (mark) state 1 (msb) (lsb) 0 1 serial data start bit 1 bit transmit or receive data 7 or 8 bits one unit of data (character or frame) 1 bit, or none parity bit 1 or 2 bits stop bit(s) figure 12.2 data format in asynchronous communication (example: 8-bit data with parity and 2 stop bits) communication formats: table 12.10 shows the 12 communication formats that can be selected in asynchronous mode. the format is selected by settings in smr. 374 table 12.10 serial communication formats (asynchronous mode) 7-bit data stop stop mpb stop mpb stop p stop stop p stop stop smr settings chr pe mp stop 00 0 0 00 0 1 01 0 0 01 0 1 10 0 0 10 0 1 11 0 0 11 0 1 0 10 0 11 1 10 1 11 serial communication format and frame length 123456789101112 stop 8-bit data s 8-bit data s stop p 8-bit data s 8-bit data s stop 7-bit data s 7-bit data s 7-bit data s s 8-bit data s stop stop mpb 8-bit data s 7-bit data s 7-bit data s p stop stop stop stop stop mpb legend: s: start bit stop: stop bit p: parity bit mpb: multiprocessor bit 375 clock: an internal clock generated by the on-chip baud rate generator or an external clock input from the sck pin can be selected as the sci transmit/receive clock. the clock source is selected by the c/ a bit in smr and bits cke1 and cke0 in scr. for details of sci clock source selection, see table 12.9. when an external clock is input at the sck pin, it must have a frequency 16 times the desired bit rate. when the sci is operated on an internal clock, it can output a clock signal at the sck pin. the frequency of this output clock is equal to the bit rate. the phase is aligned as shown in figure 12.3 so that the rising edge of the clock occurs at the center of each transmit data bit. d0 d1 d2 d3 d4 d5 d6 d7 0/1 1 1 0 1 frame figure 12.3 phase relationship between output clock and serial data (asynchronous mode) transmitting and receiving data: ? sci initialization (asynchronous mode): before transmitting or receiving data, clear the te and re bits to 0 in scr, then initialize the sci as follows. when changing the communication mode or format, always clear the te and re bits to 0 before following the procedure given below. clearing te to 0 sets the tdre flag to 1 and initializes tsr. clearing re to 0, however, does not initialize the rdrf, per, fer, and orer flags, or rdr, which retain their previous contents. when an external clock is used the clock should not be stopped during initialization or subsequent operation, since operation will be unreliable in this case. 376 figure 12.4 shows a sample flowchart for initializing the sci. start of initialization set value in brr select communication format in smr 1-bit interval elapsed? wait (4) (3) (2) (1) yes no 377 ? transmitting serial data (asynchronous mode): figure 12.5 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. yes yes 378 in transmitting serial data, the sci operates as follows: ? the sci monitors the tdre flag in ssr. when the tdre flag is cleared to 0, the sci recognizes that tdr contains new data, and loads this data from tdr into tsr. ? after loading the data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmitting. if the tie bit is set to 1 in scr, the sci requests a transmit-data-empty interrupt (txi) at this time. serial transmit data is transmitted in the following order from the txd pin: ? start bit: one 0 bit is output. ? transmit data: 7 or 8 bits are output, lsb first. ? parity bit or multiprocessor bit: one parity bit (even or odd parity),or one multiprocessor bit is output. formats in which neither a parity bit nor a multiprocessor bit is output can also be selected. ? stop bit(s): one or two 1 bits (stop bits) are output. ? mark state: output of 1 bits continues until the start bit of the next transmit data. ? the sci checks the tdre flag when it outputs the stop bit. if the tdre flag is 0, the sci loads new data from tdr into tsr, outputs the stop bit, then begins serial transmission of the next frame. if the tdre flag is 1, the sci sets the tend flag to 1 in ssr, outputs the stop bit, then continues output of 1 bits in the mark state. if the teie bit is set to 1 in scr, a transmit-end interrupt (tei) is requested at this time figure 12.6 shows an example of sci transmit operation in asynchronous mode. 0/1 d0 d1 d7 0/1 1 1 0 start bit 0d0d1 d7 1 1 data parity bit stop bit start bit data parity bit stop bit tdre tend idle state (mark state) tei interrupt request txi interrupt request txi interrupt handler writes data in tdr and clears tdre flag to 0 txi interrupt request 1 frame figure 12.6 example of sci transmit operation in asynchronous mode (8-bit data with parity and one stop bit) 379 ? receiving serial data (asynchronous mode): figure 12.7 shows a sample flowchart for receiving serial data and indicates the procedure to follow. yes yes no no 380 yes 381 in receiving, the sci operates as follows: ? the sci monitors the communication line. when it detects a start bit (0 bit), the sci synchronizes internally and starts receiving. ? receive data is stored in rsr in order from lsb to msb. ? the parity bit and stop bit are received. after receiving these bits, the sci carries out the following checks: ? parity check: the number of 1s in the receive data must match the even or odd parity setting of in the o/ e bit in smr. ? stop bit check: the stop bit value must be 1. if there are two stop bits, only the first is checked. ? status check: the rdrf flag must be 0, indicating that the receive data can be transferred from rsr into rdr. if these all checks pass, the rdrf flag is set to 1 and the received data is stored in rdr. if one of the checks fails (receive error*), the sci operates as shown in table 12.11. note: * when a receive error occurs, further receiving is disabled. in receiving, the rdrf flag is not set to 1. be sure to clear the error flags to 0. ? when the rdrf flag is set to 1, if the rie bit is set to 1 in scr, a receive-data-full interrupt (rxi) is requested. if the orer, per, or fer flag is set to 1 and the rie bit in scr is also set to 1, a receive-error interrupt (eri) is requested. table 12.11 receive error conditions receive error abbreviation condition data transfer overrun error orer receiving of next data ends while rdrf flag is still set to 1 in ssr receive data is not transferred from rsr to rdr framing error fer stop bit is 0 receive data is transferred from rsr to rdr parity error per parity of received data differs from even/odd parity setting in smr receive data is transferred from rsr to rdr 382 figure 12.8 shows an example of sci receive operation in asynchronous mode. 0/1 d0 d1 d7 0/1 1 1 0 start bit 0d0d1 d7 1 1 data data parity bit parity bit stop bit stop bit start bit rdrf fer idle (mark) state framing error, eri interrupt request rxi interrupt request rxi interrupt handler reads data in rdr and clears rdrf flag to 0 1 frame figure 12.8 example of sci receive operation (8-bit data with parity and one stop bit) 12.3.3 multiprocessor communication the multiprocessor communication function enables several processors to share a single serial communication line. the processors communicate in asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format). in multiprocessor communication, each receiving processor is addressed by an id. a serial communication cycle consists of an id-sending cycle that identifies the receiving processor, and a data-sending cycle. the multiprocessor bit distinguishes id-sending cycles from data-sending cycles. the transmitting processor starts by sending the id of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1. next the transmitting processor sends transmit data with the multiprocessor bit cleared to 0. receiving processors skip incoming data until they receive data with the multiprocessor bit set to 1. when they receive data with the multiprocessor bit set to 1, receiving processors compare the data with their ids. processors with ids not matching the received data skip further incoming data until they again receive data with the multiprocessor bit set to 1. multiple processors can send and receive data in this way. figure 12.9 shows an example of communication among different processors using a multiprocessor format. 383 communication formats: four formats are available. parity bit settings are ignored when a multiprocessor format is selected. for details see table 12.10. clock: see the description of asynchronous mode. (id=04) (id=01) (id=02) (id=03) transmitting processor receiving processor b receiving processor a receiving processor c receiving processor d h'01 (mpb=1) serial data h'aa (mpb=0) serial communication line id-sending cycle: receiving processor address data-sending cycle: data sent to receiving processor specified by id legend mpb : multiprocessor bit figure 12.9 example of communication among processors using multiprocessor format (sending data h'aa to receiving processor a) transmitting and receiving data: ? transmitting multiprocessor serial data: figure 12.10 shows a sample flowchart for transmitting multiprocessor serial data and indicates the procedure to follow. 384 tend= 1 no no read tend flag in ssr yes yes yes yes no no 385 in transmitting serial data, the sci operates as follows: ? the sci monitors the tdre flag in ssr. when the tdre flag is cleared to 0, the sci recognizes that tdr contains new data, and loads this data from tdr into tsr. ? after loading the data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmitting. if the tie bit is set to 1 in scr, the sci requests a transmit-data-empty interrupt (txi) at this time. serial transmit data is transmitted in the following order from the txd pin: ? start bit: one 0 bit is output. ? transmit data: 7 or 8 bits are output, lsb first. ? multiprocessor bit: one multiprocessor bit (mpbt value) is output. ? stop bit(s): one or two 1 bits (stop bits) are output. ? mark state: output of 1 bits continues until the start bit of the next transmit data. ? the sci checks the tdre flag when it outputs the stop bit. if the tdre flag is 0, the sci loads new data from tdr into tsr, outputs the stop bit, then begins serial transmission of the next frame. if the tdre flag is 1, the sci sets the tend flag to 1 in ssr, outputs the stop bit, then continues output of 1 bits in the mark state. if the teie bit is set to 1 in scr, a transmit-end interrupt (tei) is requested at this time figure 12.11 shows an example of sci transmit operation using a multiprocessor format. d0 d1 d7 0/1 1 1 0 start bit 0 d0 d1 d7 0/1 1 data multi- processor bit stop bit start bit data multi- processor bit stop bit tdre tend idle (mark) state tei interrupt request txi interrupt request txi interrupt handler writes data in tdr and clears tdre flag to 0 txi interrupt request 1 frame figure 12.11 example of sci transmit operation (8-bit data with multiprocessor bit and one stop bit) ? receiving multiprocessor serial data: figure 12.12 shows a sample flowchart for receiving multiprocessor serial data and indicates the procedure to follow. 386 read rdrf flag in ssr no yes yes yes no yes yes no no no read orer and fer flags in ssr (3) (1) (2) (4) (1) (2) (3) (4) (5) rdrf= 1 fer figure 12.12 sample flowchart for receiving multiprocessor serial data 387 yes yes no no 388 figure 12.13 shows an example of sci receive operation using a multiprocessor format. id2 data2 idle (mark) state not own id, so mpie bit is set to 1 again a. own id does not match data b. own id matches data d0 d1 d7 1 1 0 start bit start bit stop bit stop bit 0 d0 d1 d7 0 1 1 data (id1) data (data1) start bit stop bit stop bit data (data2) mpie idle (mark) state 1 mpb rdrf rdr value rdr value rxi interrupt request (multiprocessor interrupt) rxi interrupt handler reads rdr data and clears rdrf flag to 0 no rxi interrupt request, rdr not updated id1 mpb d0 d1 d7 1 1 0 start bit 0 d0 d1 d7 0 1 1 data (id2) mpie 1 mpb rdrf rxi interrupt request (multiprocessor interrupt) mpb detection mpie = 0 rxi interrupt handler reads rdr data and clears rdrf flag to 0 own id, so receiving continues, with data received by rxi interrupt handler mpb id1 mpie bit is set to 1 again mpb detection mpie = 0 figure 12.13 example of sci receive operation (8-bit data with multiprocessor bit and one stop bit) 389 12.3.4 synchronous operation in synchronous mode, the sci transmits and receives data in synchronization with clock pulses. this mode is suitable for high-speed serial communication. the sci transmitter and receiver share the same clock but are otherwise independent, so full- duplex communication is possible. the transmitter and the receiver are also double-buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. figure 12.14 shows the general format in synchronous serial communication. don't care one unit (character or frame) of transfer data msb bit 0 bit 1 bit 3 bit 2 bit 4 bit 5 bit 6 bit 7 lsb don't care serial clock serial data * * note: * high except in continuous transmitting or receiving figure 12.14 data format in synchronous communication in synchronous serial communication, each data bit is placed on the communication line from one falling edge of the serial clock to the next. data is guaranteed valid at the rise of the serial clock. in each character, the serial data bits are transferred in order from lsb (first) to msb (last). after output of the msb, the communication line remains in the state of the msb. in synchronous mode the sci receives data by synchronizing with the rise of the serial clock. communication format: the data length is fixed at 8 bits. no parity bit or multiprocessor bit can be added. clock: an internal clock generated by the on-chip baud rate generator or an external clock input from the sck pin can be selected by means of the c/ a bit in smr and the cke1 and cke0 bits in scr. see table 12.9 for details of sci clock source selection. when the sci operates on an internal clock, it outputs the clock source at the sck pin. eight clock pulses are output per transmitted or received character. when the sci is not transmitting or receiving, the clock signal remains in the high state. if receiving in single-character units is required, an external clock should be selected. 390 transmitting and receiving data: ? sci initialization (synchronous mode): before transmitting or receiving data, clear the te and re bits to 0 in scr, then initialize the sci as follows. when changing the communication mode or format, always clear the te and re bits to 0 before following the procedure given below. clearing te to 0 sets the tdre flag to 1 and initializes tsr. clearing re to 0, however, does not initialize the rdrf, per, fer, and orer flags, or rdr, which retain their previous contents. figure 12.15 shows a sample flowchart for initializing the sci. 391 ? figure 12.16 sample flowchart for serial transmitting 392 in transmitting serial data, the sci operates as follows. ? ? ? ? figure 12.17 example of sci transmit operation ? 393 yes yes no no 394 395 figure 12.19 shows an example of sci receive operation. serial clock serial data rxi interrupt handler reads data in rdr and clears rdrf flag to 0 rxi interrupt request rxi interrupt request overrun error, eri interrupt request orer rdrf bit 7 bit 0 bit 7 bit 0 bit 1 bit 6 bit 7 1 frame figure 12.19 example of sci receive operation 396 ? figure 12.20 sample flowchart for simultaneous serial transmitting and receiving 397 12.4 sci interrupts the sci has four interrupt request sources: transmit-end interrupt (tei), receive-error (eri), receive-data-full (rxi), and transmit-data-empty interrupt (txi). table 12.12 lists the interrupt sources and indicates their priority. these interrupts can be enabled or disabled by the tie, rie, and teie bits in scr. each interrupt request is sent separately to the interrupt controller. a txi interrupt is requested when the tdre flag is set to 1 in ssr. a tei interrupt is requested when the tend flag is set to 1 in ssr. an rxi interrupt is requested when the rdrf flag is set to 1 in ssr. an eri interrupt is requested when the orer, per, or fer flag is set to 1 in ssr. table 12.12 sci interrupt sources priority interrupt source description high eri receive error (orer, fer, or per) rxi receive data register full (rdrf) txi transmit data register empty (tdre) low transmit end (tend) tei 398 12.5 usage notes 12.5.1 notes on use of sci note the following points when using the sci. tdr write and tdre flag: the tdre flag in ssr is a status flag indicating the loading of transmit data from tdr to tsr. the sci sets the tdre flag to 1 when it transfers data from tdr to tsr. data can be written into tdr regardless of the state of the tdre flag. if new data is written in tdr when the tdre flag is 0, the old data stored in tdr will be lost because this data has not yet been transferred to tsr. before writing transmit data in tdr, be sure to check that the tdre flag is set to 1. simultaneous multiple receive errors: table 12.13 shows the state of the ssr status flags when multiple receive errors occur simultaneously. when an overrun error occurs the rsr contents are not transferred to rdr, so receive data is lost. table 12.13 ssr status flags and transfer of receive data ssr status flags receive data transfer rdrf orer fer per rsr rdr receive errors 11 0 0 399 break detection and processing: break signals can be detected by reading the rxd pin directly when a framing error (fer) is detected. in the break state the input from the rxd pin consists of all 0s, so the fer flag is set and the parity error flag (per) may also be set. in the break state the sci receiver continues to operate, so if the fer flag is cleared to 0 it will be set to 1 again. sending a break signal: the input/output condition and level of the txd pin are determined by dr and ddr bits. this feature can be used to send a break signal. after the serial transmitter is initialized, the dr value substitutes for the mark state until the te bit is set to 1 (the txd pin function is not selected until the te bit is set to 1). the ddr and dr bits should therefore be set to 1 beforehand. to send a break signal during serial transmission, clear the dr bit to 0 , then clear the te bit to 0. when the te bit is cleared to 0 the transmitter is initialized, regardless of its current state, so the txd pin becomes an input/output outputting the value 0. receive error flags and transmitter operation (synchronous mode only): when a receive error flag (orer, per, or fer) is set to 1 the sci will not start transmitting, even if the tdre flag is cleared to 0. be sure to clear the receive error flags to 0 when starting to transmit. note that clearing the re bit to 0 does not clear the receive error flags to 0. receive data sampling timing in asynchronous mode and receive margin: in asynchronous mode the sci operates on a base clock with 16 times the bit rate frequency. in receiving, the sci synchronizes internally with the fall of the start bit, which it samples on the base clock. receive data is latched at the rising edge of the eighth base clock pulse. see figure 12.21. 15 0 internal base clock 8 clocks 7 0 receive data (rxd) synchronization sampling timing data sampling timing 15 0 d 0 d 1 start bit 16 clocks 7 figure 12.21 receive data sampling timing in asynchronous mode 400 the receive margin in asynchronous mode can therefore be expressed as shown in equation (1). m = (0.5 e 1 2n d e 0.5 n ) e (l e 0.5) f e (1 + f) restrictions on use of an external clock source: ? figure 12.22 example of synchronous transmission 401 switching from sck pin function to port pin function: ? a a figure 12.23 operation when switching from sck pin function to port pin function 402 ? a a figure 12.24 operation when switching from sck pin function to port pin function (example of preventing low-level output) 403 section 13 smart card interface 13.1 overview the sci supports an ic card (smart card) interface handling iso/iec7816-3 (identification card) character transmission as a serial communication interface expansion function. switchover between the normal serial communication interface and the smart card interface is controlled by a register setting. 13.1.1 features features of the smart card interface supported by the h8/3024 series are listed below. ? asynchronous communication ? data length: 8 bits ? parity bit generation and checking ? transmission of error signal (parity error) in receive mode ? error signal detection and automatic data retransmission in transmit mode ? direct convention and inverse convention both supported ? built-in baud rate generator allows any bit rate to be selected ? three interrupt sources ? there are three interrupt sources?ransmit-data-empty, receive-data-full, and transmit/receive error?hat can issue requests independently. 404 13.1.2 block diagram figure 13.1 shows a block diagram of the smart card interface. bus interface tdr rsr rdr module data bus tsr scmr ssr scr transmission/ reception control brr baud rate generator internal data bus rxd txd sck parity generation parity check clock external clock figure 13.1 block diagram of smart card interface 13.1.3 pin configuration table 13.1 shows the smart card interface pins. table 13.1 smart card interface pins pin name abbreviation i/o function serial clock pin sck i/o clock input/output receive data pin rxd input receive data input transmit data pin txd output transmit data output 405 13.1.4 register configuration the smart card interface has the internal registers listed in table 13.2. the brr, tdr, and rdr registers have their normal serial communication interface functions, as described in section 12, serial communication interface. table 13.2 smart card interface registers channel address* 1 name abbreviation r/w initial value 0 h'fffb0 serial mode register smr r/w h'00 h'fffb1 bit rate register brr r/w h'ff h'fffb2 serial control register scr r/w h'00 h'fffb3 transmit data register tdr r/w h'ff h'fffb4 serial status register ssr r/(w)* 2 h'84 h'fffb5 receive data register rdr r h'00 h'fffb6 smart card mode register scmr r/w h'f2 1 h'fffb8 serial mode register smr r/w h'00 h'fffb9 bit rate register brr r/w h'ff h'fffba serial control register scr r/w h'00 h'fffbb transmit data register tdr r/w h'ff h'fffbc serial status register ssr r/(w)* 2 h'84 h'fffbd receive data register rdr r h'00 h'fffbe smart card mode register scmr r/w h'f2 notes: *1 lower 20 bits of the address in advanced mode. *2 only 0 can be written in bits 7 to 3, to clear the flags. 406 13.2 register descriptions this section describes the new or modified registers and bit functions in the smart card interface. 13.2.1 smart card mode register (scmr) scmr is an 8-bit readable/writable register that selects smart card interface functions. 7 1 6 1 5 1 4 1 3 sdir 0 r/w 0 smif 0 r/w 2 sinv 0 r/w 1 1 bit initial value read/write reserved bits reserved bit smart card interface mode select enables or disables the smart card interface function smart card data invert inverts data logic levels smart card data transfer direction selects the serial/parallel conversion format scmr is initialized to h'f2 by a reset and in standby mode. bits 7 to 4?eserved: read-only bits, always read as 1. bit 3?mart card data transfer direction (sdir): selects the serial/parallel conversion format.* 1 bit 3 sdir description 0 tdr contents are transmitted lsb-first (initial value) receive data is stored lsb-first in rdr 1 tdr contents are transmitted msb-first receive data is stored msb-first in rdr 407 bit 2?mart card data invert (sinv): specifies inversion of the data logic level. this function is used in combination with the sdir bit to communicate with inverse-convention cards.* 2 the sinv bit does not affect the logic level of the parity bit. for parity settings, see section 13.3.4, register settings. bit 2 sinv description 0 unmodified tdr contents are transmitted (initial value) receive data is stored unmodified in rdr 1 inverted tdr contents are transmitted receive data is inverted before storage in rdr bit 1?eserved: read-only bit, always read as 1. bit 0?mart card interface mode select (smif): enables the smart card interface function. bit 0 smif description 0 smart card interface function is disabled (initial value) 1 smart card interface function is enabled notes: *1 the function for switching between lsb-first and msb-first mode can also be used with the normal serial communication interface. note that when the communication format data length is set to 7 bits and msb-first mode is selected for the serial data to be transferred, bit 0 of tdr is not transmitted, and only bits 7 to 1 of the received data are valid. *2 the data logic level inversion function can also be used with the normal serial communication interface. note that, when inverting the serial data to be transferred, parity transmission and parity checking is based on the number of high-level periods at the serial data i/o pin, and not on the register value. 408 13.2.2 serial status register (ssr) the function of ssr bit 4 is modified in smart card interface mode. this change also causes a modification to the setting conditions for bit 2 (tend). 7 tdre 1 r/(w)* 6 rdrf 0 r/(w)* 5 orer 0 r/(w)* 4 ers 0 r/(w)* 3 per 0 r/(w)* 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r bit initial value read/write transmit end status flag indicating end of transmission error signal status (ers) status flag indicating that an error signal has been received note: * only 0 can be written, to clear the flag. bits 7 to 5: these bits operate as in normal serial communication. for details see section 12.2.7, serial status register (ssr). bit 4?rror signal status (ers): in smart card interface mode, this flag indicates the status of the error signal sent from the receiving device to the transmitting device. the smart card interface does not detection framing errors. bit 4 ers description 0 indicates normal transmission, with no error signal returned (initial value) [clearing conditions] ? the chip is reset, or enters standby mode or module stop mode ? software reads ers while it is set to 1, then writes 0. 1 indicates that the receiving device sent an error signal reporting a parity error [setting condition] a low error signal was sampled. note: clearing the te bit to 0 in scr does not affect the ers flag, which retains its previous value. 409 bits 3 to 0: these bits operate as in normal serial communication. for details see section 12.2.7, serial status register (ssr). the setting conditions for transmit end (tend), however, are modified as follows. bit 2 tend description 0 transmission is in progress [clearing condition] software reads tdre while it is set to 1, then writes 0 in the tdre flag. 1 end of transmission [setting conditions] (initial value) ? the chip is reset or enters standby mode. ? the te bit and fer/ers bit are both cleared to 0 in scr. ? tdre is 1 and fer/ers is 0 at a time 2.5 etu after the last bit of a 1-byte serial character is transmitted (normal transmission). note: an etu (elementary time unit) is the time needed to transmit one bit. 13.2.3 serial mode register (smr) the function of smr bit 7 is modified in smart card interface mode. this change also causes a modification to the function of bits 1 and 0 in the serial control register (scr). 7 gm 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 o/e 0 r/w 3 stop 0 r/w 0 cks0 0 r/w 2 mp 0 r/w 1 cks1 0 r/w bit initial value read/write bit 7?sm mode (gm): with the normal smart card interface, this bit is cleared to 0. setting this bit to 1 selects gsm mode, an additional mode for controlling the timing for setting the tend flag that indicates completion of transmission, and the type of clock output used. the details of the additional clock output control mode are specified by the cke1 and cke0 bits in the serial control register (scr). 410 bit 7 gm description 0 normal smart card interface mode operation ? the tend flag is set 12.5 etu after the beginning of the start bit. ? clock output on/off control only. (initial value) 1 gsm mode smart card interface mode operation ? the tend flag is set 11.0 etu after the beginning of the start bit. ? clock output on/off and fixed-high/fixed-low control. bits 6 to 0: these bits operate as in normal serial communication. for details see section 12.2.5, serial mode register (smr). 13.2.4 serial control register (scr) the function of scr bits 1 and 0 is modified in smart card interface mode. 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w bit initial value read/write bits 7 to 2: these bits operate as in normal serial communication. for details see section 12.2.6, serial control register (scr). bits 1 and 0?lock enable 1 and 0 (cke1, cke0): these bits select the sci clock source and enable or disable clock output from the sck pin. in smart card interface mode, it is possible to specify a fixed high level or fixed low level for the clock output, in addition to the usual switching between enabling and disabling of the clock output. bit 7 gm bit 1 cke1 bit 0 cke0 description 0 0 0 internal clock/sck pin is i/o port (initial value) 1 internal clock/sck pin is clock output 1 0 internal clock/sck pin is fixed at low output 1 internal clock/sck pin is clock output 1 0 internal clock/sck pin is fixed at high output 1 internal clock/sck pin is clock output 411 13.3 operation 13.3.1 overview the main features of the smart card interface are as follows. ? one frame consists of 8-bit data plus a parity bit. ? in transmission, a guard time of at least 2 etu (elementary time units: the time for transfer of one bit) is provided between the end of the parity bit and the start of the next frame. ? if a parity error is detected during reception, a low error signal level is output for 1 etu period 10.5 etu after the start bit. ? if an error signal is detected during transmission, the same data is transmitted automatically after the elapse of 2 etu or longer. ? only asynchronous communication is supported; there is no synchronous communication function. 13.3.2 pin connections figure 13.2 shows a pin connection diagram for the smart card interface. in communication with a smart card, since both transmission and reception are carried out on a single data transmission line, the txd pin and rxd pin should both be connected to this line. the data transmission line should be pulled up to v cc with a resistor. when the smart card uses the clock generated on the smart card interface, the sck pin output is input to the clk pin of the smart card. if the smart card uses an internal clock, this connection is unnecessary. the reset signal should be output from one of the h8/3024 series?generic ports. in addition to these pin connections. power and ground connections will normally also be necessary. 412 txd rxd sck px (port) h8/3024 series chip v cc i/o data line clock line reset line clk rst card-processing device smart card figure 13.2 smart card interface connection diagram note: setting both te and re to 1 without connecting a smart card enables closed transmission/reception, allowing self-diagnosis to be carried out. 13.3.3 data format figure 13.3 shows the smart card interface data format. in reception in this mode, a parity check is carried out on each frame, and if an error is detected an error signal is sent back to the transmitting device to request retransmission of the data. in transmission, the error signal is sampled and the same data is retransmitted. 413 ds d0 d1 d2 d3 d4 d5 d6 d7 dp no parity error output from transmitting device ds d0 d1 d2 d3 d4 d5 d6 d7 dp parity error output from transmitting device de output from receiving device legend ds: start bit d0 to d7: data bits dp: parity bit de: error signal figure 13.3 smart card interface data format the operating sequence is as follows. 1. when the data line is not in use it is in the high-impedance state, and is fixed high with a pull- up resistor. 2. the transmitting device starts transfer of one frame of data. the data frame starts with a start bit (ds, low-level), followed by 8 data bits (d0 to d7) and a parity bit (dp). 3. with the smart card interface, the data line then returns to the high-impedance state. the data line is pulled high with a pull-up resistor. 4. the receiving device carries out a parity check. if there is no parity error and the data is received normally, the receiving device waits for reception of the next data. if a parity error occurs, however, the receiving device outputs an error signal (de, low-level) to request retransmission of the data. after outputting the error signal for the prescribed length of time, the receiving device places the signal line in the high-impedance state again. the signal line is pulled high again by a pull-up resistor. 5. if the transmitting device does not receive an error signal, it proceeds to transmit the next data frame. if it receives an error signal, however, it returns to step 2 and transmits the same data again. 414 13.3.4 register settings table 13.3 shows a bit map of the registers used in the smart card interface. bits indicated as 0 or 1 must be set to the value shown. the setting of other bits is described in this section. table 13.3 smart card interface register settings bit register address* 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 smr h'fffb0 gm 0 1 o/ e 1 0 cks1 cks0 brr h'fffb1 brr7 brr6 brr5 brr4 brr3 brr2 brr1 brr0 scr h'fffb2 tie rie te re 0 0 cke1* 2 cke0 tdr h'fffb3 tdr7 tdr6 tdr5 tdr4 tdr3 tdr2 tdr1 tdr0 ssr h'fffb4 tdre rdrf orer ers per tend 0 0 rdr h'fffb5 rdr7 rdr6 rdr5 rdr4 rdr3 rdr2 rdr1 rdr0 scmr h'fffb6 ???? sdir sinv ? smif notes: ? unused bit. *1 lower 20 bits of the address in advanced mode. *2 when gm is cleared to 0 in smr, the cke1 bit must also be cleared to 0. serial mode register (smr) settings: clear the gm bit to 0 when using the normal smart card interface mode, or set to 1 when using gsm mode. clear the o/ e bit to 0 if the smart card is of the direct convention type, or set to 1 if of the inverse convention type. bits cks1 and cks0 select the clock source of the built-in baud rate generator. see section 13.3.5, clock. bit rate register (brr) settings: brr is used to set the bit rate. see section 13.3.5, clock, for the method of calculating the value to be set. serial control register (scr) settings: the tie, rie, te, and re bits have their normal serial communication functions. see section 12, serial communication interface, for details. the cke1 and cke0 bits specify clock output. to disable clock output, clear these bits to 00; to enable clock output, set these bits to 01. clock output is performed when the gm bit is set to 1 in smr. clock output can also be fixed low or high. smart card mode register (scmr) settings: clear both the sdir bit and sinv bit cleared to 0 if the smart card is of the direct convention type, and set both to 1 if of the inverse convention type. to use the smart card interface, set the smif bit to 1. 415 the register settings and examples of starting character waveforms are shown below for two smart cards, one following the direct convention and one the inverse convention. 1. direct convention (sdir = sinv = o/ e = 0) ds d0 d1 d2 d3 d4 d5 d6 d7 dp azzazzzaaz (z) (z) state with the direct convention type, the logic 1 level corresponds to state z and the logic 0 level to state a, and transfer is performed in lsb-first order. in the example above, the first character data is h'3b. the parity bit is 1, following the even parity rule designated for smart cards. 2. inverse convention (sdir = sinv = o/ e = 1) ds d7 d6 d5 d4 d3 d2 d1 d0 dp azzaaaaaaz (z) (z) state with the inverse convention type, the logic 1 level corresponds to state a and the logic 0 level to state z, and transfer is performed in msb-first order. in the example above, the first character data is h'3f. the parity bit is 0, corresponding to state z, following the even parity rule designated for smart cards. in the h8/3024 series, inversion specified by the sinv bit applies only to the data bits, d7 to d0. for parity bit inversion, the o/ e bit in smr must be set to odd parity mode. this applies to both transmission and reception. 416 13.3.5 clock only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock for the smart card interface. the bit rate is set with the bit rate register (brr) and the cks1 and cks0 bits in the serial mode register (smr). the equation for calculating the bit rate is shown below. table 13.5 shows some sample bit rates. if clock output is selected with cke0 set to 1, a clock with a frequency of 372 times the bit rate is output from the sck pin. b = 1488 2 2n e 1 (n + 1) 10 6 where, n: brr setting (0 n 255) b: bit rate (bit/s) : operating frequency (mhz) n: see table 13.4 table 13.4 n-values of cks1 and cks0 settings n cks1 cks0 00 0 11 21 0 31 note: if the gear function is used to divide the clock frequency, use the divided frequency to calculate the bit rate. the equation above applies directly to 1/1 frequency division. table 13.5 bit rates (bits/s) for various brr settings (when n = 0) (mhz) n 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 25.00 0 9600.0 13440.9 14400.0 17473.1 19200.0 21505.4 24193.5 33602.2 1 4800.0 6720.4 7200.0 8736.6 9600.0 10752.7 12096.8 16801.1 2 3200.0 4480.3 4800.0 5824.4 6400.0 7168.5 8064.5 11200.7 note: bit rates are rounded off to two decimal places. 417 the following equation calculates the bit rate register (brr) setting from the operating frequency and bit rate. n is an integer from 0 to 255, specifying the value with the smaller error. n = 1488 2 2n e 1 b 10 6 e 1 table 13.6 brr settings for typical bit rates (bits/s) (when n = 0) (mhz) 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 25.0 bit/s n error n error n error n error n error n error n error n error 9600 0 0.00 1 30 1 25 1 8.99 1 0.00 1 12.01 2 15.99 3 12.49 table 13.7 maximum bit rates for various frequencies (smart card interface mode) (mhz) maximum bit rate (bits/s) n n 7.1424 9600 0 0 10.00 13441 0 0 10.7136 14400 0 0 13.00 17473 0 0 14.2848 19200 0 0 16.00 21505 0 0 18.00 24194 0 0 20.00 26882 0 0 25.00 33602 0 0 the bit rate error is given by the following equation: error (%) = 1488 2 2n-1 b (n + 1) 10 6 e 1 100 418 13.3.6 transmitting and receiving data initialization: before transmitting or receiving data, the smart card interface must be initialized as described below. initialization is also necessary when switching from transmit mode to receive mode, or vice versa. 1. clear the te and re bits to 0 in the serial control register (scr). 2. clear error flags ers, per, and orer to 0 in the serial status register (ssr). 3. set the parity bit (o/ e ) and baud rate generator select bits (cks1 and cks0) in the serial mode register (smr). clear the c/ a , chr, and mp bits to 0, and set the stop and pe bits to 1. 4. set the smif, sdir, and sinv bits in the smart card mode register (scmr). when the smif bit is set to 1, the txd pin and rxd pin are both switched from port to sci pin functions and go to the high-impedance state. 5. set a value corresponding to the desired bit rate in the bit rate register (brr). 6. set the cke0 bit in scr. clear the tie, rie, te, re, mpie, teie, and cke1 bits to 0. if the cke0 bit is set to 1, the clock is output from the sck pin. 7. wait at least one bit interval, then set the tie, rie, te, and re bits in scr. do not set the te bit and re bit at the same time, except for self-diagnosis. transmitting serial data: as data transmission in smart card mode involves error signal sampling and retransmission processing, the processing procedure is different from that for the normal sci. figure 13.5 shows a sample transmission processing flowchart. 1. perform smart card interface mode initialization as described in initialization above. 2. check that the ers error flag is cleared to 0 in ssr. 3. repeat steps 2 and 3 until it can be confirmed that the tend flag is set to 1 in ssr. 4. write the transmit data in tdr, clear the tdre flag to 0, and perform the transmit operation. the tend flag is cleared to 0. 5. to continue transmitting data, go back to step 2. 6. to end transmission, clear the te bit to 0. the above processing may include interrupt handling. if transmission ends and the tend flag is set to 1 while the tie bit is set to 1 and interrupt requests are enabled, a transmit-data-empty interrupt (txi) will be requested. if an error occurs in transmission and the ers flag is set to 1 while the rie bit is set to 1 and interrupt requests are enabled, a transmit/receive-error interrupt (eri) will be requested. the timing of tend flag setting depends on the gm bit in smr. figure 13.4 shows timing of tend flag setting. 419 for details, see interrupt operations in this section. serial data (1) gm = 0 tend (2) gm = 1 tend ds dp de guard time 11.0 etu 12.5 etu figure 13.4 timing of tend flag setting 420 initialization no yes clear te bit to 0 start transmitting start no no no yes yes yes yes no end write transmit data in tdr, and clear tdre flag to 0 in ssr error handling error handling tend = 1? all data transmitted? tend = 1? fer/ers = 0? fer/ers = 0? figure 13.5 sample transmission processing flowchart 421 1. data write tdr tsr (shift register) data 1 2. transfer from tdr to tsr data 1 data 1 data remains in tdr data 1 3. serial data output note: when the ers flag is set, it should be cleared until transfer of the last bit (d7 in lsb-first transmission, d0 in msb-first transmission) of the retransmit data to be transmitted next has been completed. in case of normal transmission: tend flag is set in case of transmit error: ers flag is set steps 2 and 3 above are repeated until the tend flag is set. i/o signal output data 1 figure 13.6 relation between transmit operation and internal registers i/o data when gm = 0 guard time de ds da db dc dd de df dg dh dp 12.5 etu 11.0 etu when gm = 1 txi (tend interrupt) figure 13.7 timing of tend flag setting receiving serial data: data reception in smart card mode uses the same processing procedure as for the normal sci. figure 13.8 shows a sample reception processing flowchart. 1. perform smart card interface mode initialization as described in initialization above. 2. check that the orer flag and per flag are cleared to 0 in ssr. if either is set, perform the appropriate receive error handling, then clear both the orer and the per flag to 0. 3. repeat steps 2 and 3 until it can be confirmed that the rdrf flag is set to 1. 4. read the receive data from rdr. 5. to continue receiving data, clear the rdrf flag to 0 and go back to step 2. 6. to end reception, clear the re bit to 0. 422 initialization read rdr and clear rdrf flag to 0 in ssr clear re bit to 0 start receiving start error handling no no no yes yes orer = 0 and per = 0? rdrf = 1? all data received? yes figure 13.8 sample reception processing flowchart the above procedure may include interrupt handling. if reception ends and the rdrf flag is set to 1 while the rie bit is set to 1 and interrupt requests are enabled, a receive-data-full interrupt (rxi) will be requested. if an error occurs in reception and either the orer flag or the per flag is set to 1, a transmit/receive-error interrupt (eri) will be requested. for details, see interrupt operations in this section. if a parity error occurs during reception and the per flag is set to 1, the received data is transferred to rdr, so the erroneous data can be read. switching modes: when switching from receive mode to transmit mode, first confirm that the receive operation has been completed, then start from initialization, clearing re to 0 and setting te to 1. the rdrf, per, or orer flag can be used to check that the receive operation has been completed. 423 when switching from transmit mode to receive mode, first confirm that the transmit operation has been completed, then start from initialization, clearing te to 0 and setting re to 1. the tend flag can be used to check that the transmit operation has been completed. fixing clock output: when the gm bit is set to 1 in smr, clock output can be fixed by means of the cke1 and cke0 bits in scr. the minimum clock pulse width can be set to the specified width in this case. figure 13.9 shows the timing for fixing clock output. in this example, gm = 1, cke1 = 0, and the cke0 bit is controlled. specified pulse width cke1 value sck specified pulse width scr write (cke0 = 1) scr write (cke0 = 0) figure 13.9 timing for fixing cock output interrupt operations: the smart card interface has three interrupt sources: transmit-data-empty (txi), transmit/receive-error (eri), and receive-data-full (rxi). the transmit-end interrupt request (tei) is not available in smart card mode. a txi interrupt is requested when the tend flag is set to 1 in ssr. an rxi interrupt is requested when the rdrf flag is set to 1 in ssr. an eri interrupt is requested when the orer, per, or ers flag is set to 1 in ssr. these relationships are shown in table 13.8. table 13.8 smart card interface mode operating states and interrupt sources operating state flag enable bit interrupt source transmit mode normal operation tend tie txi error ers rie eri receive mode normal operation rdrf rie rxi error per, orer rie eri 424 examples of operation in gsm mode: when switching between smart card interface mode and software standby mode, use the following procedures to maintain the clock duty cycle. ? switching from smart card interface mode to software standby mode 1. set the p9 4 data register (dr) and data direction register (ddr) to the values for the fixed output state in software standby mode. 2. write 0 in the te and re bits in the serial control register (scr) to stop transmit/receive operations. at the same time, set the cke1 bit to the value for the fixed output state in software standby mode. 3. write 0 in the cke0 bit in scr to stop the clock. 4. wait for one serial clock cycle. during this period, the duty cycle is preserved and clock output is fixed at the specified level. 5. write h'00 in the serial mode register (smr) and smart card mode register (scmr). 6. make the transition to the software standby state. ? returning from software standby mode to smart card interface mode 1'. clear the software standby state. 2'. set the cke1 bit in scr to the value for the fixed output state at the start of software standby (the current p9 4 pin state). 3'. set smart card interface mode and output the clock. clock signal generation is started with the normal duty cycle. software standby normal operation normal operation 1 2 3 4 5 6 1' 2' 3' figure 13.10 procedure for stopping and restarting the clock use the following procedure to secure the clock duty cycle after powering on. 1. the initial state is port input and high impedance. use pull-up or pull-down resistors to fix the potential. 2. fix at the output specified by the cke1 bit in scr. 3. set smr and scmr, and switch to smart card interface mode operation. 4. set the cke0 bit to 1 in scr to start clock output. 425 13.4 usage notes the following points should be noted when using the sci as a smart card interface. receive data sampling timing and receive margin in smart card interface mode: in smart card interface mode, the sci operates on a base clock with a frequency of 372 times the transfer rate. in reception, the sci synchronizes internally with the fall of the start bit, which it samples on the base clock. receive data is latched at the rising edge of the 186th base clock pulse. the timing is shown in figure 13.11. internal base clock 372 clocks 186 clocks receive data (rxd) synchronization sampling timing d0 d1 data sampling timing 185 371 0 371 185 0 0 start bit figure 13.11 receive data sampling timing in smart card interface mode 426 the receive margin can therefore be expressed as follows. receive margin in smart card interface mode: m = (0.5 e 1 2n d e 0.5 n ) e (l e 0.5) f e (1 + f) 100% m: receive margin (%) n: ratio of clock frequency to bit rate (n = 372) d: clock duty cycle (l = 0 to 1.0) l: frame length (l =10) f: absolute deviation of clock frequency from the above equation, if f = 0 and d = 0.5, the receive margin is as follows. when d = 0.5 and f = 0: m = (0.5 e 1/2 372) 100% = 49.866% retransmission: retransmission is performed by the sci in receive mode and transmit mode as described below. ? retransmission when sci is in receive mode figure 13.12 illustrates retransmission when the sci is in receive mode. 1. if an error is found when the received parity bit is checked, the per bit is automatically set to 1. if the rie bit in scr is set to the enable state, an eri interrupt is requested. the per bit should be cleared to 0 in ssr before the next parity bit sampling timing. 2. the rdrf bit in ssr is not set for the frame in which the error has occurred. 3. if an error is found when the received parity bit is checked, the per bit is not set to 1 in ssr. 4. if no error is found when the received parity bit is checked, the receive operation is assumed to have been completed normally, and the rdrf bit is automatically set to 1 in ssr. if the rie bit in scr is set to the enable state, an rxi interrupt is requested. 5. when a normal frame is received, the data pin is held in three-state at the error signal transmission timing. 427 d0 d1 d2 d3 d4 d5 d6 d7 dp de ds d0 d1 d2 d3 d4 d5 d6 d7 dp (de) ds d0 d1 d2 d3 d4 ds frame n+1 retransmitted frame frame n rdrf [1] per [2] [3] [4] figure 13.12 retransmission in sci receive mode ? retransmission when sci is in transmit mode figure 13.13 illustrates retransmission when the sci is in transmit mode. 6. if an error signal is sent back from the receiving device after transmission of one frame is completed, the ers bit is set to 1 in ssr. if the rie bit in scr is set to the enable state, an eri interrupt is requested. the ers bit should be cleared to 0 in ssr before the next parity bit sampling timing. 7. the tend bit in ssr is not set for the frame for which the error signal was received. 8. if an error signal is not sent back from the receiving device, the ers flag is not set in ssr. 9. if an error signal is not sent back from the receiving device, transmission of one frame, including retransmission, is assumed to have been completed, and the tend bit is set to 1 in ssr. if the tie bit in scr is set to the enable state, a txi interrupt is requested. d0 d1 d2 d3 d4 d5 d6 d7 dp de ds d0 d1 d2 d3 d4 d5 d6 d7 dp (de) ds d0 d1 d2 d3 d4 ds frame n+1 retransmitted frame frame n tdre tend [6] ers transfer from tdr to tsr transfer from tdr to tsr transfer from tdr to tsr [7] [9] [8] figure 13.13 retransmission in sci transmit mode the smart card interface installed in the h8/3024 series supports an ic card (smart card) interface with provision for iso/iec7816-3 t=0 (character transmission). therefore, block transfer operations are not supported (error signal transmission, detection, and automatic data retransmission are not performed). 428 429 section 14 a/d converter 14.1 overview the h8/3024 series includes a 10-bit successive-approximations a/d converter with a selection of up to eight analog input channels. when the a/d converter is not used, it can be halted independently to conserve power. for details see section 20.6, module standby function. the h8/3024 series supports 70/134-state conversion as a high-speed conversion mode. note that it differs in this respect from the h8/3048 series, which supports 134/266-state conversion. 14.1.1 features a/d converter features are listed below. ? 10-bit resolution ? eight input channels ? selectable analog conversion voltage range the analog voltage conversion range can be programmed by input of an analog reference voltage at the v ref pin. ? high-speed conversion conversion time: minimum 5.36 ? per channel ? two conversion modes single mode: a/d conversion of one channel scan mode: continuous a/d conversion on one to four channels ? four 16-bit data registers a/d conversion results are transferred for storage into data registers corresponding to the channels. ? sample-and-hold function ? three conversion start sources the a/d converter can be activated by software, an external trigger, or an 8-bit timer compare match. ? a/d interrupt requested at end of conversion at the end of a/d conversion, an a/d end interrupt (adi) can be requested. 430 14.1.2 block diagram figure 14.1 shows a block diagram of the a/d converter. module data bus bus interface internal data bus addra addrb addrc addrd adcsr adcr successive- approximations register 10-bit d/a analog multi- plexer sample-and- hold circuit comparator + control circuit ?4 ?8 adi interrupt signal av v av cc ref ss an an an an an an an an 0 1 2 3 4 5 6 7 legend: adcr: adcsr: addra: addrb: addrc: addrd: a/d control register a/d control/status register a/d data register a a/d data register b a/d data register c a/d data register d adtrg figure 14.1 a/d converter block diagram 431 14.1.3 pin configuration table 14.1 summarizes the a/d converter? input pins. the eight analog input pins are divided into two groups: group 0 (an 0 to an 3 ), and group 1 (an 4 to an 7 ). av cc and av ss are the power supply for the analog circuits in the a/d converter. v ref is the a/d conversion reference voltage. table 14.1 a/d converter pins pin name abbrevi- ation i/o function analog power supply pin av cc input analog power supply analog ground pin av ss input analog ground and reference voltage reference voltage pin v ref input analog reference voltage analog input pin 0 an 0 input group 0 analog inputs analog input pin 1 an 1 input analog input pin 2 an 2 input analog input pin 3 an 3 input analog input pin 4 an 4 input group 1 analog inputs analog input pin 5 an 5 input analog input pin 6 an 6 input analog input pin 7 an 7 input a/d external trigger input pin adtrg 432 14.1.4 register configuration table 14.2 summarizes the a/d converter? registers. table 14.2 a/d converter registers address* 1 name abbreviation r/w initial value h'fffe0 a/d data register a h addrah r h'00 h'fffe1 a/d data register a l addral r h'00 h'fffe2 a/d data register b h addrbh r h'00 h'fffe3 a/d data register b l addrbl r h'00 h'fffe4 a/d data register c h addrch r h'00 h'fffe5 a/d data register c l addrcl r h'00 h'fffe6 a/d data register d h addrdh r h'00 h'fffe7 a/d data register d l addrdl r h'00 h'fffe8 a/d control/status register adcsr r/(w)* 2 h'00 h'fffe9 a/d control register adcr r/w h'7e notes: *1 lower 20 bits of the address in advanced mode. *2 only 0 can be written in bit 7, to clear the flag. 14.2 register descriptions 14.2.1 a/d data registers a to d (addra to addrd) bit addrn initial value 14 ad8 0 r 12 ad6 0 r 10 ad4 0 r 8 ad2 0 r 6 ad0 0 r 0 ? 0 r 4 ? 0 r 2 ? 0 r 15 ad9 0 r 13 ad7 0 r 11 ad5 0 r 9 ad3 0 r 7 ad1 0 r 1 ? 0 r 5 ? 0 r 3 ? 0 r a/d conversion data 10-bit data giving an a/d conversion result reserved bits read/write (n = a to d) the four a/d data registers (addra to addrd) are 16-bit read-only registers that store the results of a/d conversion. an a/d conversion produces 10-bit data, which is transferred for storage into the a/d data register corresponding to the selected channel. the upper 8 bits of the result are stored in the upper byte of the a/d data register. the lower 2 bits are stored in the lower byte. bits 5 to 0 of an a/d 433 data register are reserved bits that are always read as 0. table 14.3 indicates the pairings of analog input channels and a/d data registers. the cpu can always read and write the a/d data registers. the upper byte can be read directly, but the lower byte is read through a temporary register (temp). for details see section 14.3, cpu interface. the a/d data registers are initialized to h'0000 by a reset and in standby mode. table 14.3 analog input channels and a/d data registers (addra to addrd) analog input channel group 0 group 1 a/d data register an 0 an 4 addra an 1 an 5 addrb an 2 an 6 addrc an 3 an 7 addrd 14.2.2 a/d control/status register (adcsr) bit initial value read/write 7 adf 0 r/(w) 6 adie 0 r/w 5 adst 0 r/w 4 scan 0 r/w 3 cks 0 r/w 0 ch0 0 r/w 2 ch2 0 r/w 1 ch1 0 r/w * note: only 0 can be written, to clear the flag. * a/d end flag indicates end of a/d conversion a/d interrupt enable enables and disables a/d end interrupts a/d start starts or stops a/d conversion scan mode selects single mode or scan mode clock select selects the a/d conversion time channel select 2 to 0 these bits select analog input channels 434 adcsr is an 8-bit readable/writable register that selects the mode and controls the a/d converter. adcsr is initialized to h'00 by a reset and in standby mode. bit 7?/d end flag (adf): indicates the end of a/d conversion. bit 7 adf description 0 [clearing condition] read adf when adf =1, then write 0 in adf. (initial value) 1 [setting conditions] ? single mode: a/d conversion ends ? scan mode: a/d conversion ends in all selected channels bit 6?/d interrupt enable (adie): enables or disables the interrupt (adi) requested at the end of a/d conversion. bit 6 adie description 0 a/d end interrupt request (adi) is disabled (initial value) 1 a/d end interrupt request (adi) is enabled bit 5?/d start (adst): starts or stops a/d conversion. the adst bit remains set to 1 during a/d conversion. it can also be set to 1 by external trigger input at the adtrg bit 5 adst description 0 a/d conversion is stopped (initial value) 1 single mode: a/d conversion starts; adst is automatically cleared to 0 when conversion ends. scan mode: a/d conversion starts and continues, cycling among the selected channels, until adst is cleared to 0 by software, by a reset, or by a transition to standby mode. bit 4?can mode (scan): selects single mode or scan mode. for further information on operation in these modes, see section 14.4, operation. clear the adst bit to 0 before switching the conversion mode. bit 4 scan description 0 single mode (initial value) 1 scan mode 435 bit 3?lock select (cks): selects the a/d conversion time. clear the adst bit to 0 before switching the conversion time. bit 3 cks description 0 conversion time = 134 states (maximum) (initial value) 1 conversion time = 70 states (maximum) bits 2 to 0?hannel select 2 to 0 (ch2 to ch0): these bits and the scan bit select the analog input channels. clear the adst bit to 0 before changing the channel selection. group selection channel selection description ch2 ch1 ch0 single mode scan mode 000 an 0 (initial value) an 0 1an 1 an 0 , an 1 10 an 2 an 0 to an 2 1an 3 an 0 to an 3 100 an 4 an 4 1an 5 an 4 , an 5 10 an 6 an 4 to an 6 1an 7 an 4 to an 7 14.2.3 a/d control register (adcr) bit initial value read/write 7 trge 0 r/w 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 0 ? 0 r/w 2 ? 1 ? 1 ? 1 ? trigger enable enables or disables starting of a/d conversion by an external trigger or 8-bit timer compare match reserved bits adcr is an 8-bit readable/writable register that enables or disables starting of a/d conversion by external trigger input or an 8-bit timer compare match signal. adcr is initialized to h'7e by a reset and in standby mode. 436 bit 7?rigger enable (trge): enables or disables starting of a/d conversion by an external trigger or 8-bit timer compare match. bit 7 trge description 0 starting of a/d conversion by an external trigger or 8-bit timer compare match is disabled (initial value) 1 a/d conversion is started at the falling edge of the external trigger signal ( adtrg ) or by an 8-bit timer compare match external trigger pin and 8-bit timer selection is performed by the 8-bit timer. for details, see section 9, 8-bit timers. bits 6 to 1?eserved: these bits cannot be modified and are always read as 1. bit 0?eserved: this bit can be read or written, but must not be set to 1. 14.3 cpu interface addra to addrd are 16-bit registers, but they are connected to the cpu by an 8-bit data bus. therefore, although the upper byte can be be accessed directly by the cpu, the lower byte is read through an 8-bit temporary register (temp). an a/d data register is read as follows. when the upper byte is read, the upper-byte value is transferred directly to the cpu and the lower-byte value is transferred into temp. next, when the lower byte is read, the temp contents are transferred to the cpu. when reading an a/d data register, always read the upper byte before the lower byte. it is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. figure 14.2 shows the data flow for access to an a/d data register. 437 upper-byte read bus interface module data bus cpu (h'aa) addrnh (h'aa) addrnl (h'40) lower-byte read bus interface module data bus cpu (h'40) addrnh (h'aa) addrnl (h'40) temp (h'40) temp (h'40) (n = a to d) (n = a to d) figure 14.2 a/d data register access operation (reading h'aa40) 438 14.4 operation the a/d converter operates by successive approximations with 10-bit resolution. it has two operating modes: single mode and scan mode. 14.4.1 single mode (scan = 0) single mode should be selected when only one a/d conversion on one channel is required. a/d conversion starts when the adst bit is set to 1 by software, or by external trigger input. the adst bit remains set to 1 during a/d conversion and is automatically cleared to 0 when conversion ends. when conversion ends the adf flag is set to 1. if the adie bit is also set to 1, an adi interrupt is requested at this time. to clear the adf flag to 0, first read adcsr, then write 0 in adf. when the mode or analog input channel must be switched during analog conversion, to prevent incorrect operation, first clear the adst bit to 0 in adcsr to halt a/d conversion. after making the necessary changes, set the adst bit to 1 to start a/d conversion again. the adst bit can be set at the same time as the mode or channel is changed. typical operations when channel 1 (an 1 ) is selected in single mode are described next. figure 14.3 shows a timing diagram for this example. 1. single mode is selected (scan = 0), input channel an 1 is selected (ch2 = ch1 = 0, ch0 = 1), the a/d interrupt is enabled (adie = 1), and a/d conversion is started (adst = 1). 2. when a/d conversion is completed, the result is transferred into addrb. at the same time the adf flag is set to 1, the adst bit is cleared to 0, and the a/d converter becomes idle. 3. since adf = 1 and adie = 1, an adi interrupt is requested. 4. the a/d interrupt handling routine starts. 5. the routine reads adcsr, then writes 0 in the adf flag. 6. the routine reads and processes the conversion result (addrb). 7. execution of the a/d interrupt handling routine ends. after that, if the adst bit is set to 1, a/d conversion starts again and steps 2 to 7 are repeated. 439 adie adst adf state of channel 0 (an ) set set set clear clear idle idle idle idle a/d conversion (1) a/d conversion (2) idle read conversion result a/d conversion result (1) read conversion result a/d conversion result (2) note: vertical arrows ( ) indicate instructions executed by software. 0 1 2 3 a/d conversion starts * * * * * * addra addrb addrc addrd state of channel 1 (an ) state of channel 2 (an ) state of channel 3 (an ) idle figure 14.3 example of a/d converter operation (single mode, channel 1 selected) 440 14.4.2 scan mode (scan = 1) scan mode is useful for monitoring analog inputs in a group of one or more channels. when the adst bit is set to 1 by software or external trigger input, a/d conversion starts on the first channel in the group (an 0 when ch2 = 0, an 4 when ch2 = 1). when two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (an 1 or an 5 ) starts immediately. a/d conversion continues cyclically on the selected channels until the adst bit is cleared to 0. the conversion results are transferred for storage into the a/d data registers corresponding to the channels. when the mode or analog input channel selection must be changed during analog conversion, to prevent incorrect operation, first clear the adst bit to 0 in adcsr to halt a/d conversion. after making the necessary changes, set the adst bit to 1. a/d conversion will start again from the first channel in the group. the adst bit can be set at the same time as the mode or channel selection is changed. typical operations when three channels in group 0 (an 0 to an 2 ) are selected in scan mode are described next. figure 14.4 shows a timing diagram for this example. 1. scan mode is selected (scan = 1), scan group 0 is selected (ch2 = 0), analog input channels an 0 to an 2 are selected (ch1 = 1, ch0 = 0), and a/d conversion is started (adst = 1). 2. when a/d conversion of the first channel (an 0 ) is completed, the result is transferred into addra. next, conversion of the second channel (an 1 ) starts automatically. 3. conversion proceeds in the same way through the third channel (an 2 ). 4. when conversion of all selected channels (an 0 to an 2 ) is completed, the adf flag is set to 1 and conversion of the first channel (an 0 ) starts again. if the adie bit is set to 1, an adi interrupt is requested when a/d conversion ends. 5. steps 2 to 4 are repeated as long as the adst bit remains set to 1. when the adst bit is cleared to 0, a/d conversion stops. after that, if the adst bit is set to 1, a/d conversion starts again from the first channel (an 0 ). 441 adst adf state of channel 0 (an ) 0 1 2 3 continuous a/d conversion set clear *1 clear * 1 idle a/d conversion (1) idle idle idle a/d conversion (4) idle a/d conversion (2) idle a/d conversion (5) idle a/d conversion (3) idle idle transfer a/d conversion result (1) a/d conversion result (4) a/d conversion result (2) a/d conversion result (3) *1 *2 a/d conversion time notes: *2 *1 addra addrb addrc addrd state of channel 1 (an ) state of channel 2 (an ) state of channel 3 (an ) vertical arrows ( ) indicate instructions executed by software. data currently being converted is ignored. figure 14.4 example of a/d converter operation (scan mode, channels an 0 to an 2 selected) 442 14.4.3 input sampling and a/d conversion time the a/d converter has a built-in sample-and-hold circuit. the a/d converter samples the analog input at a time t d after the adst bit is set to 1, then starts conversion. figure 14.5 shows the a/d conversion timing. table 14.4 indicates the a/d conversion time. as indicated in figure 14.5, the a/d conversion time includes t d and the input sampling time. the length of t d varies depending on the timing of the write access to adcsr. the total conversion time therefore varies within the ranges indicated in table 14.4. in scan mode, the values given in table 14.4 apply to the first conversion. in the second and subsequent conversions the conversion time is fixed at 128 states when cks = 0 or 66 states when cks = 1. address bus write signal input sampling timing adf (1) (2) t d t spl t conv legend: (1): (2): t : t : t : d spl conv adcsr write cycle adcsr address synchronization delay input sampling time a/d conversion time figure 14.5 a/d conversion timing 443 table 14.4 a/d conversion time (single mode) cks = 0 cks = 1 symbol min typ max min typ max synchronization delay t d 6 ? 94 ? 5 input sampling time t spl ? 31 ?? 15 ? a/d conversion time t conv 131 ? 134 69 ? 70 note: values in the table are numbers of states. 14.4.4 external trigger input timing a/d conversion can be externally triggered when the trge bit is set to 1 in adcr and the 8-bit timer's adte bit is cleared to 0, external trigger input is enabled at the adtrg adtrg adtrg internal trigger signal adst a/d conversion figure 14.6 external trigger input timing 444 14.5 interrupts the a/d converter generates an interrupt (adi) at the end of a/d conversion. the adi interrupt request can be enabled or disabled by the adie bit in adcsr. 14.6 usage notes when using the a/d converter, note the following points: 1. analog input voltage range during a/d conversion, the voltages input to the analog input pins an n should be in the range av ss 445 av cc *1 *1 v ref an 0 to an 7 av ss notes: *1 *2 rin: input impedance rin *2 100 ? 0.1 f 0.01 f 10 f figure 14.7 example of analog input protection circuit table 14.5 analog input pin ratings item min max unit analog input capacitance ? 20 pf allowable signal-source impedance ? 10* k ? note: * when conversion time = 134 states, v cc = 4.0 v to 5.5 v, and 13 mhz. for details, see section 21, electrical characteristics. 20 pf to a/d converter an 0 to an 7 10 k ? figure 14.8 analog input pin equivalent circuit note: numeric values are approximate, except in table 14.5 446 6. a/d conversion accuracy definitions a/d conversion accuracy in the h8/3024 series is defined as follows: resolution digital output code length of a/d converter offset error deviation from ideal a/d conversion characteristic of analog input voltage required to raise digital output from minimum voltage value 0000000000 to 0000000001 (figure 14.10) full-scale error deviation from ideal a/d conversion characteristic of analog input voltage required to raise digital output from 1111111110 to 1111111111 (figure 14.10) quantization error intrinsic error of the a/d converter; 1/2 lsb (figure 14.9) nonlinearity error deviation from ideal a/d conversion characteristic in range from zero volts to full scale, exclusive of offset error, full-scale error, and quantization error. absolute accuracy deviation of digital value from analog input value, including offset error, full-scale error, quantization error, and nonlinearity error. 111 110 101 100 011 010 001 000 1/8 2/8 3/8 4/8 5/8 6/8 7/8 fs quantization error analog input voltage digital output ideal a/d conversion characteristic figure 14.9 a/d converter accuracy definitions (1) 447 fs offset error nonlinearity error actual a/d conversion characteristic analog input voltage digital output ideal a/d conversion characteristic full-scale error figure 14.10 a/d converter accuracy definitions (2) 7. allowable signal-source impedance the analog inputs of the h8/3024 series are designed to assure accurate conversion of input signals with a signal-source impedance not exceeding 10 k ? ? ? 448 equivalent circuit of a/d converter h8/3024 series 20 pf cin = 15 pf 10 k ? up to 10 k ? low-pass filter c up to 0.1 f sensor output impedance sensor input figure 14.11 analog input circuit (example) 449 section 15 d/a converter 15.1 overview the h8/3024 series includes a d/a converter with two channels. 15.1.1 features d/a converter features are listed below. ? eight-bit resolution ? two output channels ? conversion time: maximum 10 s (with 20-pf capacitive load) ? output voltage: 0 v to v ref ? d/a outputs can be sustained in software standby mode 450 15.1.2 block diagram figure 15.1 shows a block diagram of the d/a converter. dadr0 dadr1 dacr dastcr v av da da av ref cc ss 0 1 legend: dacr: dadr0: dadr1: dastcr: 8-bit d/a module data bus bus interface internal data bus control circuit d/a control register d/a data register 0 d/a data register 1 d/a standby control register figure 15.1 d/a converter block diagram 451 15.1.3 pin configuration table 15.1 summarizes the d/a converter's input and output pins. table 15.1 d/a converter pins pin name abbreviation i/o function analog power supply pin av ss input analog power supply and reference voltage analog ground pin av ss input analog ground and reference voltage analog output pin 0 da 0 output analog output, channel 0 analog output pin 1 da 1 output analog output, channel 1 reference voltage input pin v ref input analog reference voltage 15.1.4 register configuration table 15.2 summarizes the d/a converter's registers. table 15.2 d/a converter registers address* name abbreviation r/w initial value h'fff9c d/a data register 0 dadr0 r/w h'00 h'fff9d d/a data register 1 dadr1 r/w h'00 h'fff9e d/a control register dacr r/w h'1f h'ee01a d/a standby control register dastcr r/w h'fe note: * lower 20 bits of the address in advanced mode. 452 15.2 register descriptions 15.2.1 d/a data registers 0 and 1 (dadr0, dadr1) bit initial value read/write 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w the d/a data registers (dadr0 and dadr1) are 8-bit readable/writable registers that store the data to be converted. when analog output is enabled, the d/a data register values are constantly converted and output at the analog output pins. the d/a data registers are initialized to h'00 by a reset and in standby mode. when the daste bit is set to 1 in the d/a standby control register (dastcr), the d/a registers are not initialized in software standby mode. 15.2.2 d/a control register (dacr) bit initial value read/write 7 daoe1 0 r/w 6 daoe0 0 r/w 5 dae 0 r/w 4 1 3 1 2 1 1 1 0 1 d/a output enable 1 d/a output enable 0 d/a enable controls d/a conversion and analog output controls d/a conversion and analog output controls d/a conversion dacr is an 8-bit readable/writable register that controls the operation of the d/a converter. dacr is initialized to h'1f by a reset and in standby mode. when the daste bit is set to 1 in the d/a standby control register (dastcr), the d/a registers are not initialized in software standby mode. 453 bit 7?/a output enable 1 (daoe1): controls d/a conversion and analog output. bit 7 daoe1 description 0da 1 analog output is disabled 1 channel-1 d/a conversion and da 1 analog output are enabled bit 6?/a output enable 0 (daoe0): controls d/a conversion and analog output. bit 6 daoe0 description 0da 0 analog output is disabled 1 channel-0 d/a conversion and da 0 analog output are enabled bit 5?/a enable (dae): controls d/a conversion, together with bits daoe0 and daoe1. when the dae bit is cleared to 0, analog conversion is controlled independently in channels 0 and 1. when the dae bit is set to 1, analog conversion is controlled together in channels 0 and 1. output of the conversion results is always controlled independently by daoe0 and daoe1. bit 7 daoe1 bit 6 daoe0 bit 5 dae description 0 0 ? d/a conversion is disabled in channels 0 and 1 0 1 0 d/a conversion is enabled in channel 0 d/a conversion is disabled in channel 1 0 1 1 d/a conversion is enabled in channels 0 and 1 1 0 0 d/a conversion is disabled in channel 0 d/a conversion is enabled in channel 1 1 0 1 d/a conversion is enabled in channels 0 and 1 1 1 ? d/a conversion is enabled in channels 0 and 1 when the dae bit is set to 1, even if bits daoe0 and daoe1 in dacr and the adst bit in adcsr are cleared to 0, the same current is drawn from the analog power supply as during a/d and d/a conversion. bits 4 to 0?eserved: these bits cannot be modified and are always read as 1. 454 15.2.3 d/a standby control register (dastcr) dastcr is an 8-bit readable/writable register that enables or disables d/a output in software standby mode. bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 0 daste 0 r/w 2 ? 1 ? 1 ? 1 ? reserved bits d/a standby enable enables or disables d/a output in software standby mode dastcr is initialized to h'fe by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 7 to 1?eserved: these bits cannot be modified and are always read as 1. bit 0?/a standby enable (daste): enables or disables d/a output in software standby mode. bit 0 daste description 0 d/a output is disabled in software standby mode (initial value) 1 d/a output is enabled in software standby mode 15.3 operation the d/a converter has two built-in d/a conversion circuits that can perform conversion independently. d/a conversion is performed constantly while enabled in dacr. if the dadr0 or dadr1 value is modified, conversion of the new data begins immediately. the conversion results are output when bits daoe0 and daoe1 are set to 1. 455 an example of d/a conversion on channel 0 is given next. timing is indicated in figure 15.2. 1. data to be converted is written in dadr0. 2. bit daoe0 is set to 1 in dacr. d/a conversion starts and da 0 becomes an output pin. the converted result is output after the conversion time. v ref the output value is dadr contents 256 output of this conversion result continues until the value in dadr0 is modified or the daoe0 bit is cleared to 0. 3. if the dadr0 value is modified, conversion starts immediately, and the result is output after the conversion time. 4. when the daoe0 bit is cleared to 0, da0 becomes an input pin. dadr0 write cycle dacr write cycle dadr0 write cycle dacr write cycle address dadr0 daoe0 da 0 conversion data 1 conversion data 2 high-impedance state conversion result 1 conversion result 2 t dconv t dconv legend: t : d/a conversion time dconv figure 15.2 example of d/a converter operation 456 15.4 d/a output control in the h8/3024 series, d/a converter output can be enabled or disabled in software standby mode. when the daste bit is set to 1 in dastcr, d/a converter output is enabled in software standby mode. the d/a converter registers retain the values they held prior to the transition to software standby mode. when d/a output is enabled in software standby mode, the reference supply current is the same as during normal operation. 457 section 16 ram 16.1 overview the h8/3024 series has high-speed static ram on-chip. the ram is connected to the cpu by a 16-bit data bus. the cpu accesses both byte data and word data in two states, making the ram useful for rapid data transfer. the on-chip ram can be enabled or disabled with the ram enable bit (rame) in the system control register (syscr). when the on-chip ram is disabled, that area is assigned to external space in the expanded modes. the on-chip ram specifications for the product lineup are shown in table 16.1. table 16.1 h8/3024 series on-chip ram specifications h8/3024f-ztat h8/3024 mask rom version h8/3026f-ztat h8/3026 mask rom version ram size 4 kbytes 4 kbytes 8 kbytes 8 kbytes address assignment modes 1, 2, 7 h'fef20 to h'fff1f h'fef20 to h'fff1f h'fdf20 to h'fff1f h'fdf20 to h'fff1f modes 3, 4, 5 h'ffef20 to h'ffff1f h'ffef20 to h'ffff1f h'ffdf20 to h'ffff1f h'ffdf20 to h'ffff1f mode 6 h'fe20 to h'ff1f h'fe20 to h'ff1f h'fd20 to h'ff1f h'fd20 to h'ff1f 458 16.1.1 block diagram figure 16.1 shows a block diagram of the on-chip ram. h'fef20* h'fef22* h'fff1e* h'fef21* h'fef23* h'fff1f* internal data bus (upper 8 bits) internal data bus (lower 8 bits) bus interface syscr on-chip ram even addresses odd addresses legend: syscr: system control register note: * this example is of the h8/3024 mask rom version operating in mode 7. the lower 20 bits of the address are shown. figure 16.1 ram block diagram 16.1.2 register configuration the on-chip ram is controlled by syscr. table 16.2 gives the address and initial value of syscr. table 16.2 system control register address* name abbreviation r/w initial value h'ee012 system control register syscr r/w h'09 note: * lower 20 bits of the address in advanced mode. 459 16.2 system control register (syscr) bit initial value read/write 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 4 sts0 0 r/w 3 ue 1 r/w 2 nmieg 0 r/w 1 ssoe 0 r/w 0 rame 1 r/w software standby standby timer select 2 to 0 user bit enable nmi edge select software standby output port enable ram enable bit enables or disables on-chip ram one function of syscr is to enable or disable access to the on-chip ram. the on-chip ram is enabled or disabled by the rame bit in syscr. for details about the other bits, see section 3.3, system control register (syscr). bit 0?am enable (rame): enables or disables the on-chip ram. the rame bit is initialized at the rising edge of the input at the res pin. it is not initialized in software standby mode. bit 0 rame description 0 on-chip ram is disabled 1 on-chip ram is enabled (initial value) 460 16.3 operation when the rame bit is set to 1, the on-chip ram is enabled. accesses to the addresses shown in table 16.1 are directed to the on-chip ram. in modes 1 to 5 (expanded modes), when the rame bit is cleared to 0, the off-chip address space is accessed. in mode 6, 7 (single-chip mode), when the rame bit is cleared to 0, the on-chip ram is not accessed: read access always results in h'ff data, and write access is ignored. since the on-chip ram is connected to the cpu by an internal 16-bit data bus, it can be written and read by word access. it can also be written and read by byte access. byte data is accessed in two states using the upper 8 bits of the data bus. word data starting at an even address is accessed in two states using all 16 bits of the data bus. 461 section 17 flash memory [h8/3026f-ztat version] 17.1 overview the h8/3026f-ztat version has 256 kbytes of on-chip flash memory. the flash memory is connected to the cpu by a 16-bit data bus. the cpu accesses both byte data and word data in two states, enabling rapid data transfer. the on-chip rom is enabled and disabled by setting the mode pins (md 2 to md 0 ) as shown in table 17.1. the on-chip flash memory product (h8/3026f-ztat version) can be erased and programmed on- board, as well as with a special-purpose prom programmer. table 17.1 operating modes and rom mode pins mode md2 md1 md0 on-chip rom mode 1 (expanded 1-mbyte mode with on-chip rom disabled) 0 0 1 disabled (external address area) mode 2 (expanded 1-mbyte mode with on-chip rom disabled) 010 mode 3 (expanded 16-mbyte mode with on-chip rom disabled) 011 mode 4 (expanded 16-mbyte mode with on-chip rom disabled) 100 mode 5 (expanded 16-mbyte mode with on-chip rom enabled) 1 0 1 enabled mode 6 (single-chip normal mode) 1 1 0 mode 7 (single-chip advanced mode) 1 1 1 462 17.2 features the h8/3026f-ztat version has 256 kbytes of on-chip flash memory. the features of the flash memory are summarized below. ? four flash memory operating modes ? program mode ? erase mode ? program-verify mode ? erase-verify mode ? programming/erase methods the flash memory is programmed 128 bytes at a time. erasing is performed in block units. to erase the entire flash memory, each block must be erased in turn. in block erasing, 4-kbyte, 32- kbyte, and 64-kbyte blocks can be set arbitrarily. ? programming/erase times the flash memory programming time is 10 ms (typ.) for simultaneous 128-byte programming, equivalent approximately to 80 ? (typ.) per byte, and the erase time is 100 ms (typ.) per block. ? reprogramming capability the flash memory can be reprogrammed up to 100 times. ? on-board programming modes there are two modes in which flash memory can be programmed/erased/verified on-board: ? boot mode ? user program mode ? automatic bit rate adjustment for data transfer in boot mode, the h8/3026f-ztat version chip? bit rate can be automatically adjusted to match the transfer bit rate of the host. ? flash memory emulation in ram flash memory programming can be emulated in real time by overlapping a part of ram onto flash memory. ? protect modes there are three protect modes?ardware, software, and error?hich allow protected status to be designated for flash memory program/erase/verify operations ? prom mode flash memory can be programmed/erased in prom mode, using a prom programmer, as well as in on-board programming mode. 463 17.2.1 block diagram module bus bus interface/controller flash memory (256 kbytes) operating mode internal address bus internal data bus (16 bits) fwe pin mode pins flmcr2 legend flmcr1: flash memory control register 1 flmcr2: flash memory control register 2 ebr1: erase block register 1 ebr2: erase block register 2 ramcr: ram control register ebr1 ebr2 ramcr flmcr1 figure 17.1 block diagram of flash memory 464 17.2.2 pin configuration the flash memory is controlled by means of the pins shown in table 17.2. table 17.2 flash memory pins pin name abbreviation i/o function reset res 17.2.3 register configuration the registers used to control the on-chip flash memory when enabled are shown in table 17.3. table 17.3 flash memory registers register name abbreviation r/w initial value address* 1 flash memory control register 1 flmcr1 r/w h'00* 2 h'ee030 flash memory control register 2 flmcr2 r h'00 h'ee031 erase block register 1 ebr1 r/w h'00 h'ee032 erase block register 2 ebr2 r/w h'00 h'ee033 ram control register ramcr r/w h'f0 h'ee077 notes: flmcr1, flmcr2, ebr1, ebr2, and ramcr are 8-bit registers, and should be accessed by byte access . these registers are used only in the versions with on-chip flash memory, and are not provided in the versions with on-chip mask rom. reading the corresponding addresses in a mask rom version will always return 1s, and writes to these addresses are invalid. *1 lower 16 bits of address in advanced mode. *2 when a high level is input to the fwe pin, the initial value is h'80. 465 17.3 register descriptions 17.3.1 flash memory control register 1 (flmcr1) bit 76543210 fwe swe esu psu ev pv e p initial value ? 0 0 0 0 0 0 0 read/write r r/w r/w r/w r/w r/w r/w r/w note: * determined by the state of the fwe pin. flmcr1 is an 8-bit register used for flash memory operating mode control. program-verify mode or erase-verify mode for addresses h'00000 to h'3ffff is entered by setting the swe bit when fwe = 1, then setting the pv or ev bit. program mode for addresses h'00000 to h'3ffff is entered by setting the swe bit when fwe = 1, then setting the psu bit, and finally setting the p bit. erase mode for addresses h'00000 to h'3ffff is entered by setting the swe bit when fwe = 1, then setting the esu bit, and finally setting the e bit. flmcr1 is initialized by a reset, and in hardware standby mode and software standby mode. its initial value is h'80 when a high level is input to the fwe pin, and h'00 when a low level is input. in mode 6 the fwe pin must be fixed low since flash memory on-board programming modes are not supported. when the on-chip flash memory is disabled, a read access to this register will return h'00, and writes are invalid. when setting bits 6 to 0 in this register, one bit must be set one at a time. writes to the swe bit in flmcr1 are enabled only when fwe = 1; writes to bits esu, psu, ev, and pv only when fwe = 1 and swe = 1; writes to the e bit only when fwe = 1, swe = 1, and esu = 1; and writes to the p bit only when fwe = 1, swe = 1, and psu = 1. notes: 1. the programming and erase flowcharts must be followed when setting the bits in this register to prevent erroneous programming or erasing. 2. transitions are made to program mode, erase mode, program-verify mode, and erase- verify mode according to the settings in this register. when reading flash memory as normal on-chip rom, bits 6 to 0 in this register must be cleared. bit 7?lash write enable (fwe): sets hardware protection against flash memory programming/erasing. bit 7 fwe description 0 when a low level is input to the fwe pin (hardware-protected state) 1 when a high level is input to the fwe pin 466 bit 6?oftware write enable (swe): enables or disables flash memory programming and erasing. (this bit should be set when setting bits 5 to 0, ebr1 bits 7 to 0, and ebr2 bits 3 to 0.) bit 6 swe description 0 programming/erasing disabled (initial value) 1 programming/erasing enabled [setting condition] when fwe = 1 note: do not execute a sleep instruction while the swe bit is set to 1. bit 5?rase setup (esu): prepares for a transition to erase mode. set this bit to 1 before setting the e bit to 1 in flmcr1 (do not set the swe, psu, ev, pv, e, or p bit at the same time). bit 5 esu description 0 erase setup cleared (initial value) 1 erase setup [setting condition] when fwe = 1 and swe = 1 bit 4?rogram setup (psu): prepares for a transition to program mode. set this bit to 1 before setting the p bit to 1 in flmcr1 (do not set the swe, esu, ev, pv, e, or p bit at the same time). bit 4 psu description 0 program setup cleared (initial value) 1 program setup [setting condition] when fwe = 1 and swe = 1 bit 3?rase-verify mode (ev): selects erase-verify mode transition or clearing. (do not set the swe, esu, psu, pv, e, or p bit at the same time.) bit 3 ev description 0 erase-verify mode cleared (initial value) 1 transition to erase-verify mode [setting condition] when fwe = 1 and swe = 1 467 bit 2?rogram-verify mode (pv): selects program-verify mode transition or clearing. (do not set the swe, esu, psu, ev, e, or p bit at the same time.) bit 2 pv description 0 program-verify mode cleared (initial value) 1 transition to program-verify mode [setting condition] when fwe = 1 and swe = 1 bit 1?rase mode (e): selects erase mode transition or clearing. (do not set the swe, esu, psu, ev, pv, or p bit at the same time.) bit 1 e description 0 erase mode cleared (initial value) 1 transition to erase mode [setting condition] when fwe = 1, swe = 1, and esu = 1 note: do not access the flash memory while the e bit is set. bit 0?rogram (p): selects program mode transition or clearing. (do not set the swe, esu, psu, ev, pv, or e bit at the same time.) bit 0 p description 0 program mode cleared (initial value) 1 transition to program mode [setting condition] when fwe = 1, swe = 1, and psu = 1 note: do not access the flash memory while the p bit is set. 468 17.3.2 flash memory control register 2 (flmcr2) bit 76543210 fler initial value 0 0 0 0 0 0 0 0 read/write r r r r r r r r flmcr2 is an 8-bit register used for flash memory operating mode control. flmcr2 is initialized to h'00 by a reset, and in hardware standby mode and software standby mode. when the on-chip flash memory is disabled, a read will return h'00. note: flmcr2 is a read-only register, and should not be written to. bit 7?lash memory error (fler): indicates that an error has occurred during an operation on flash memory (programming or erasing). when fler is set to 1, flash memory goes to the error- protection state. bit 7 fler description 0 flash memory is operating normally flash memory program/erase protection (error protection) is disabled [clearing condition] reset ( res ? ? ? ? bits 6 to 0?eserved: these bits are always read as 0. 469 17.3.3 erase block register 1 (ebr1) bit 76543210 eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w ebr1 is an 8-bit register that specifies the flash memory erase area block by block. ebr1 is initialized to h'00 by a reset, in hardware standby mode and software standby mode, when a low level is input to the fwe pin, and when a high level is input to the fwe pin and the swe bit in flmcr1 is not set. when a bit in ebr1 is set to 1, the corresponding block can be erased. other blocks are erase-protected. only one bit can be set in ebr1 and ebr2 together; do not set two or more bits at the same time. when the on-chip flash memory is disabled, a read access to this register will return h'00, and erasing is disabled. the flash memory block configuration is shown in table 17.4. to erase the entire flash memory, each block must be erased in turn. as the h8/3026f-ztat version does not support on-board programming modes in mode 6, ebr1 register bits cannot be set to 1 in this mode. 17.3.4 erase block register 2 (ebr2) bit 76543210 eb11 eb10 eb9 eb8 initial value 0 0 0 0 0 0 0 0 read/write r r r r r/w r/w r/w r/w ebr2 is an 8-bit register that specifies the flash memory erase area block by block. ebr2 is initialized to h'00 by a reset, in hardware standby mode and software standby mode, and when a low level is input to the fwe pin. when a high level is input to the fwe pin and the swe bit in flmcr1 is not set, it is initialized to bit 0. when a bit in ebr2 is set to 1, the corresponding block can be erased. other blocks are erase-protected. only one bit can be set in ebr1 and ebr2 together; do not set two or more bits at the same time. when the on-chip flash memory is disabled, a read will return h'00, and erasing is disabled. the flash memory block configuration is shown in table 17.4. to erase the entire flash memory, each block must be erased in turn. as the h8/3026f-ztat version does not support on-board programming modes in mode 6, ebr2 register bits cannot be set to 1 in this mode. 470 note: bits 7 to 4 in this register are read-only. these bits must not be set to 1. if bits 7 to 4 are set when an ebr1/ebr2 bit is set, ebr1/ebr2 will be initialized to h'00. table 17.4 flash memory erase blocks block (size) addresses eb0 (4 kbytes) h'000000 to h'000fff eb1 (4 kbytes) h'001000 to h'001fff eb2 (4 kbytes) h'002000 to h'002fff eb3 (4 kbytes) h'003000 to h'003fff eb4 (4 kbytes) h'004000 to h'004fff eb5 (4 kbytes) h'005000 to h'005fff eb6 (4 kbytes) h'006000 to h'006fff eb7 (4 kbytes) h'007000 to h'007fff eb8 (32 kbytes) h'008000 to h'00ffff eb9 (64 kbytes) h'010000 to h'01ffff eb10 (64 kbytes) h'020000 to h'02ffff eb11 (64 kbytes) h'030000 to h'03ffff 17.3.5 ram control register (ramcr) bit 76543210 rams ram2 ram1 ram0 initial value 1 1 1 1 0 0 0 0 read/write r r r r r/w r/w r/w r/w ramcr specifies the area of flash memory to be overlapped with part of ram when emulating realtime flash memory programming. ramcr is initialized to h'00 by a reset and in hardware standby mode. ramcr settings should be made in user mode or user program mode. flash memory area divisions are shown in table 17.5. to ensure correct operation of the emulation function, the rom for which ram emulation is performed should not be accessed immediately after this register has been modified. normal execution of an access immediately after register modification is not guaranteed. bits 7 to 4?eserved: these bits cannot be modified and are always read as 1. 471 bit 3?am select (rams): specifies selection or non-selection of flash memory emulation in ram. when rams = 1, all flash memory blocks are program/erase-protected. bit 3 rams description 0 emulation not selected program/erase-protection of all flash memory blocks is disabled (initial value) 1 emulation selected program/erase-protection of all flash memory blocks is enabled bits 2 to 0?lash memory area selection (ram2 to ram0): these bits are used together with bit 3 to select the flash memory area to be overlapped with ram. (see table 17.5.) table 17.5 flash memory area divisions ram area block name rams ram2 ram1 ram0 h'ffe000 to h'ffefff 4-kbyte ram area 0 *** h'000000 to h'000fff eb0 (4 kbytes) 1000 h'001000 to h'001fff eb1 (4 kbytes) 1001 h'002000 to h'002fff eb2 (4 kbytes) 1010 h'003000 to h'003fff eb3 (4 kbytes) 1011 h'004000 to h'004fff eb4 (4 kbytes) 1100 h'005000 to h'005fff eb5 (4 kbytes) 1101 h'006000 to h'006fff eb6 (4 kbytes) 1110 h'007000 to h'007fff eb7 (4 kbytes) 1111 * : don? care note: flash memory emulation by ram is not supported in mode 6 (single-chip normal mode); therefore, although these bits can be written, they should not be set to 1. when performing flash memory emulation by ram, the rame bit in syscr must be set to 1. 472 17.4 overview of operation 17.4.1 mode transitions when the mode pins and the fwe pin are set in the reset state and a reset-start is executed, the h8/3026f-ztat version enters one of the operating modes shown in figure 17.2. in user mode, flash memory can be read but not programmed or erased. flash memory can be programmed and erased in boot mode, user program mode, and prom mode. boot mode and user program mode cannot be used in the h8/3026f-ztat version? mode 6 (normal mode with on-chip rom enabled). 473 boot mode on-board programming mode user program mode user mode with on-chip rom enabled reset state prom mode res = 0 fwe = 0 res = 0 res = 0 res = 0 * 1 * 1 * 3 * 2 * 4 * 5 * 4 notes: only make a transition between user mode and user program mode when the cpu is not accessing the flash memory. *1 ram emulation possible *2 the h8/3026f-ztat is placed in prom mode by means of a dedicated prom writer. *3 md 2 , md 1 , md 0 = (1, 0, 1) (1, 1, 0) (1, 1, 1) fwe = 0 *4 md 2 , md 1 , md 0 = (1, 0, 1) (1, 1, 1) fwe = 1 *5 md 2 , md 1 , md 0 (0, 0, 1) (0, 1, 1) fwe = 1 figure 17.2 flash memory related state transitions state transitions between the normal and user modes and on-board programming mode are performed by changing the fwe pin level from high to low or from low to high. to prevent misoperation (erroneous programming or erasing) in these cases, the bits in the flash memory control register (flmcr1) should be cleared to 0 before making such a transition. after the bits are cleared, a wait time is necessary. normal operation is not guaranteed if this wait time is insufficient. 474 17.4.2 on-board programming modes example of boot mode operation flash memory h8/3026f-ztat version ram host programming control program sci application program (old version) new application program flash memory h8/3026f-ztat version ram host sci application program (old version) boot program area new application program flash memory h8/3026f-ztat version ram host sci flash memory prewrite-erase boot program new application program flash memory h8/3026f-ztat version program execution state ram host sci new application program boot program programming control program boot program area 1. initial state the old program version or data remains written in the flash memory. the user should prepare the programming control program and new application program beforehand in the host. 2. programming control program transfer when boot mode is entered, the boot program in the h8/3026f-ztat version (originally incorporated in the chip) is started and the programming control program in the host is transferred to ram via sci communication. the boot program required for flash memory erasing is automatically transferred to the ram boot program area. 3. flash memory initialization the erase program in the boot program area (in ram) is executed, and the flash memory is initialized (to h'ff). in boot mode, total flash memory erasure is performed, without regard to blocks. 4. writing new application program the programming control program transferred from the host to ram is executed, and the new application program in the host is written into the flash memory. boot program boot program programming control program boot program area programming control program 475 example of user program mode operation flash memory h8/3026f-ztat version ram host programming/erase control program sci boot program new application program flash memory h8/3026f-ztat version ram host sci new application program flash memory h8/3026f-ztat version ram host sci flash memory erase boot program new application program flash memory h8/3026f-ztat version program execution state ram host sci boot program programming/erase control program boot program fwe assessment program transfer program application program (old version) application program (old version) fwe assessment program transfer program new application program fwe assessment program transfer program 1. initial state the fwe assessment program that confirms that user program mode has been entered, and the program that will transfer the programming/ erase control program from flash memory to on-chip ram should be written into the flash memory by the user beforehand. the programming/erase control program should be prepared in the host or in the flash memory. 3. flash memory initialization the programming/erase program in ram is executed, and the flash memory is initialized (to h'ff). erasing can be performed in block units, but not in byte units. 4. writing new application program next, the new application program in the host is written into the erased flash memory blocks. do not write to unerased blocks. 2. programming/erase control program transfer when user program mode is entered, user software recognizes this fact, executes the transfer program in the flash memory, and transfers the programming/erase control program to ram. fwe assessment program transfer program programming/erase control program programming/erase control program 476 17.4.3 flash memory emulation in ram in the h8/3026f-ztat version, flash memory programming can be emulated in real time by overlapping the flash memory with part of ram ( overlap ram ). when the emulation block set in ramcr is accessed while the emulation function is being executed, data written in the overlap ram is read. emulation should be performed in user mode or user program mode. application program execution state flash memory emulation block ram sci overlap ram (emulation is performed on data written in ram) figure 17.3 reading overlap ram data in user mode/user program mode when overlap ram data is confirmed, clear the rams bit to cancel ram overlap, and actually perform writes to the flash memory in user program mode. when the programming control program is transferred to ram in on-board programming mode, ensure that the transfer destination and the overlap ram do not overlap, as this will cause data in the overlap ram to be rewritten. 477 application program flash memory ram sci programming control program execution state overlap ram (program data) program data figure 17.4 writing overlap ram data in user program mode 17.4.4 block configuration the flash memory in the h8/3026f-ztat version is divided into three 64-kbyte blocks, one 32- kbyte block, and eight 4-kbyte blocks. erasing can be carried out in block units. address h'3ffff address h'00000 64 kbytes 32 kbytes 64 kbytes 64 kbytes 256 kbytes 4 kbytes 8 478 17.5 on-board programming mode when pins are set to on-board programming mode and a reset-start is executed, the chip enters the on-board programming state in which on-chip flash memory programming, erasing, and verifying can be carried out. there are two operating modes in this mode boot mode and user program mode. the pin settings for entering each mode are shown in table 17.6. for a diagram of the transitions to the various flash memory modes, see figure 17.2. boot mode and user program mode cannot be used in the h8/3026f-ztat version s mode 6 (on- chip rom enabled). table 17.6 on-board programming mode settings mode fwe md 2 md 1 md 0 boot mode mode 5 1* 1 0* 2 01 mode 7 0* 2 11 user program mode mode 5 1 0 1 mode 7 1 1 1 notes: *1 for the high level input timing, see items 6 and 7 of notes on using the boot mode. *2 in boot mode, the md 2 setting should be the inverse of the input. in the boot mode in the h8/3026f-ztat version, the levels of the mode pins (md 2 to md 0 ) are reflected in mode select bits 2 to 0 (mds2 to mds0) in the mode control register (mdcr). 479 17.5.1 boot mode when boot mode is used, a flash memory programming control program must be prepared beforehand in the host, and sci channel 1, which is to be used, must be set to asynchronous mode. when a reset-start is executed after setting the h8/3026f-ztat version s pins to boot mode, the boot program already incorporated in the mcu is activated, and the programming control program prepared beforehand in the host is transmitted sequentially to the h8/3026f-ztat version, using the sci. in the h8/3026f-ztat version, the programming control program received via the sci is written into the programming control program area in on-chip ram. after the transfer is completed, control branches to the start address (h'ffe720) of the programming control program area and the programming control program execution state is entered (flash memory programming/erasing can be performed). figure 17.5 shows a system configuration diagram when using boot mode, and figure 17.6 shows the boot program mode execution procedure. rxd1 txd1 sci1 h8/3026f-ztat version flash memory reception of programming data transmission of verify data host on-chip ram figure 17.5 system configuration when using boot mode 480 n = n? yes no set pins to boot program mode and execute reset-start n = 1 n + 1 n host transfers data (h'00) continuously at prescribed bit rate h8/3026f-ztat version measure low period of h'00 data transmitted by host after bit rate adjustment, h8/3026f-ztat version transmit one h'00 data byte to host to indicate end of adjustment host confirms normal reception of bit rate adjustment end indication (h'00), and transmits one h'55 data byte after receiving h'55, h8/3026f-ztat version transmit one h'aa byte to host host transmits number of programming control program bytes (n), upper byte followed by lower byte h8/3026f-ztat version transmit received number of bytes to host as verify data (echo-back) host transmits programming control program sequentially in byte units h8/3026f-ztat version transmit received programming control program to host as verify data (echo-back) transfer received programming control program to on-chip ram end of transmission check flash memory data, and if data has already been written, erase all blocks after confirming that all flash memory data has been erased, h8/3026f-ztat version transmit one h'aa byte to host execute programming control program transferred to on-chip ram start h8/3026f-ztat version calculate bit rate and sets value in bit rate register note: if a memory cell does not operate normally and cannot be erased, one h'ff byte is transmitted as an erase error indication, and the erase operation and subsequent operations are halted. figure 17.6 boot mode execution procedure 481 automatic sci bit rate adjustment: start bit stop bit d0 d1 d2 d3 d4 d5 d6 d7 low period (9 bits) measured (h'00 data) high period (1 or more bits) when boot mode is initiated, the h8/3026f-ztat version measure the low period of the asynchronous sci communication data (h'00) transmitted continuously from the host. the sci transmit/receive format should be set as 8-bit data, 1 stop bit, no parity. the h8/3026f-ztat version calculate the bit rate of the transmission from the host from the measured low period, and transmits one h'00 byte to the host to indicate the end of bit rate adjustment. the host should confirm that this adjustment end indication (h'00) has been received normally, and transmit one h'55 byte to the h8/3026f-ztat version. if reception cannot be performed normally, initiate boot mode again (reset), and repeat the above operations. depending on the host s transmission bit rate and the h8/3026f-ztat version s system clock frequency, there will be a discrepancy between the bit rates of the host and the h8/3026f-ztat version. to ensure correct sci operation, the host s transfer bit rate should be set to 4800, 9600, or 19,200 bps*. table 17.7 shows typical host transfer bit rates and system clock frequencies for which automatic adjustment of the h8/3026f-ztat version bit rate is possible. the boot program should be executed within this system clock range. table 17.7 system clock frequencies for which automatic adjustment of h8/3026f-ztat version bit rate is possible host bit rate (bps) system clock frequency for which automatic adjustment of h8/3026f-ztat version bit rate is possible (mhz) 19,200 16 to 25 9,600 8 to 25 4,800 4 to 25 note: * only use a setting of 4800, 9600, or 19200 bps for the host s bit rate. no other settings can be used. although the h8/3026f-ztat version may also perform automatic bit rate adjustment with bit rate and system clock combinations other than those shown in table 17.7, a degree of error will arise between the bit rates of the host and the h8/3026f-ztat version, and subsequent transfer will not be performed normally. therefore, only a combination of bit rate and system clock frequency within one of the ranges shown in table 17.7 can be used for boot mode execution. 482 on-chip ram area divisions in boot mode: in boot mode, the ram area is divided into an area used by the boot program and an area to which the user program is transferred via the sci, as shown in figure 17.7. the boot program area becomes available when a transition is made to the execution state for the user program transferred to ram. h'ffdf20 h'ffe71f h'ffe720 user program transfer area boot program area h'ffff1f note: the boot program area cannot be used until a transition is made to the execution state for the user program transferred to ram. note also that the boot program remains in this area in ram even after control branches to the user program. figure 17.7 ram areas in boot mode notes on use of boot mode: 1. when the h8/3026f-ztat version chip comes out of reset in boot mode, it measures the low period of the input at the sci s rxd 1 pin. the reset should end with rxd 1 high. after the reset ends, it takes about 100 states for the chip to get ready to measure the low period of the rxd 1 input. 2. in boot mode, if any data has been programmed into the flash memory (if all data is not 1), all flash memory blocks are erased. boot mode is for use when user program mode is unavailable, such as the first time on-board programming is performed, or if the program activated in user program mode is accidentally erased. 3. interrupts cannot be used while the flash memory is being programmed or erased. 4. the rxd 1 and txd 1 lines should be pulled up on the board. 5. before branching to the user program the h8/3026f-ztat version terminates transmit and receive operations by the on-chip sci (channel 1) (by clearing the re and te bits to 0 in the serial control register (scr)), but the adjusted bit rate value remains set in the bit rate register (brr). the transmit data output pin, txd 1 , goes to the high-level output state (p9 1 ddr = 1 in p9ddr, p9 1 dr = 1 in p9dr). 483 the contents of the cpu s internal general registers are undefined at this time, so these registers must be initialized immediately after branching to the user program. in particular, since the stack pointer (sp) is used implicitly in subroutine calls, etc., a stack area must be specified for use by the user program. the initial values of other on-chip registers are not changed. 6. boot mode can be entered by setting pins md 0 to md 2 and fwe in accordance with the mode setting conditions shown in table 17.6, and then executing a reset-start. a. when switching from boot mode to normal mode, the boot mode state within the chip must first be cleared by reset input via the res res res s internal state will not be cleared, and the on-chip boot program will be restarted regardless of the mode pin states. c. the fwe pin must not be driven low while the boot program is running or flash memory is being programmed or erased* 2 . 7. if the mode pin input levels are changed (for example, from low to high) during a reset, the state of ports with multiplexed address functions and bus control output signals ( csn as rd lwr hwr s operating mode. therefore, care must be taken to make pin settings to prevent these pins from being used directly as output signal pins during a reset, or to prevent collision with signals outside the mcu. h8/3026f-ztat version md2 md1 md0 fwe res csn system control unit external memory, etc. notes: *1 mode pin and fwe pin input must satisfy the mode programming setup time (t mds ) with respect to the reset release timing. *2 for further information on fwe application and disconnection, see section 17.11, flash memory programming and erasing precautions. 484 *3 see section 4.2.2, reset sequence, and section 17.11, flash memory programming and erasing precautions. the h8/3026f-ztat version requires a minimum of 20 system clock cycles for a reset during operation. 17.5.2 user program mode when set to user program mode, the h8/3026f-ztat version can program and erase its flash memory by executing a user program/erase control program. therefore, on-board reprogramming of the on-chip flash memory can be carried out by providing on-board means of fwe control and supply of programming data, and storing a program/erase control program in part of the program area as necessary. to select user program mode, select a mode that enables the on-chip rom (mode 5 or 7), and apply a high level to the fwe pin. in this mode, on-chip supporting modules other than flash memory operate as they normally would in modes 5 and 7. flash memory programming/erasing should not be carried out in mode 6. when mode 6 is set, the fwe pin must be driven low. the flash memory itself cannot be read while being programmed or erased, so the program that performs programming should be placed in external memory or transferred to ram and executed there. figure 17.8 shows the execution procedure when user program mode is entered during program execution in ram. it is also possible to start from user program mode in a reset-start. 485 md 2 e md 0 = 101 or 111 reset-start transfer programming/erase control program to ram branch to programming/erase control program in ram area fwe = high (user program mode) execute programming/erase control program in ram (flash memory rewriting) clear swe bit, then release fwe (user program mode clearing) branch to application program in flash memory write fwe assessment program and transfer program (and programming/erase control program if necessary) beforehand notes: 1. do not apply a constant high level to the fwe pin. a high level should be applied to the fwe pin only when programming or erasing flash memory (including execution of flash memory emulation by ram). also, while a high level is applied to the fwe pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. 2. for further information on fwe application and disconnection, see section 17.11, flash memory programming and erasing precautions. 3. in order to execute a normal read of flash memory in user program mode, the programming/erase program must not be executing. it is thus necessary to ensure that bits 6 to 0 in flmcr1 are cleared to 0. figure 17.8 example of user program mode execution procedure 486 17.6 flash memory programming/erasing a software method, using the cpu, is employed to program and erase flash memory in the on- board programming modes. there are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. transitions to these modes for addresses h'000000 to h'03ffff are made by setting the psu, esu, p, e, pv, and ev bits in flmcr1. the flash memory cannot be read while being programmed or erased. therefore, the program (user program) that controls flash memory programming/erasing should be located and executed in on-chip ram or external memory. see section 17.11, flash memory programming and erasing precautions, for points to be noted when programming or erasing the flash memory. in the following operation descriptions, wait times after setting or clearing individual bits in flmcr1 are given as parameters; for details of the wait times, see section 21.2.6, flash memory characteristics. notes: 1. operation is not guaranteed if setting/resetting of the swe, esu, psu, ev, pv, e, and p bits in flmcr1 is executed by a program in flash memory. 2. when programming or erasing, set fwe to 1 (programming/erasing will not be executed if fwe = 0). 3. programming must be executed in the erased state. do not perform additional programming on addresses that have already been programmed. 487 normal mode on-board programming mode software programming disable state erase setup state erase mode program mode erase-verify mode program setup state program-verify mode swe = 1 swe = 0 fwe = 1 fwe = 0 e = 1 e = 0 p = 1 p = 0 software programming enable state *1 *2 *3 *4 notes: in order to perform a normal read of flash memory, swe must be cleared to 0. also note that verify-reads can be performed during the programming/erasing process. *1 : normal mode : on-board programming mode *2 do not make a state transition by setting or clearing multiple bits simultaneously. *3 after a transition from erase mode to the erase setup state, do not enter erase mode without passing through the software programming enable state. *4 after a transition from program mode to the program setup state, do not enter program mode without passing through the software programming enable state. esu = 0 esu = 1 psu = 1 psu = 0 pv = 1 pv = 0 ev = 0 ev = 1 figure 17.9 flmcr1 bit settings and state transitions 488 17.6.1 program mode when writing data or programs to flash memory, the program/program-verify flowchart shown in figure 17.10 should be followed. performing programming operations according to this flowchart will enable data or programs to be written to flash memory without subjecting the device to voltage stress or sacrificing program data reliability. programming should be carried out 128 bytes at a time. the wait times after bits are set or cleared in the flash memory control register 1 (flmcr1) and the maximum number of programming operations (n) are shown in table 21.19 in section 21.2.6, flash memory characteristics. following the elapse of (t sswe ) ? or more after the swe bit is set to 1 in flmcr1, 128-byte data is written consecutively to the write addresses. the lower 8 bits of the first address written to must be h'00 and h'80, 128 consecutive byte data transfers are performed. the program address and program data are latched in the flash memory. a 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, h'ff data must be written to the extra addresses. next, the watchdog timer (wdt) is set to prevent overprogramming due to program runaway, etc. set a value greater than (t spsu + t sp + t cp + t cpsu ) ? as the wdt overflow period. preparation for entering program mode (program setup) is performed next by setting the psu bit in flmcr1. the operating mode is then switched to program mode by setting the p bit in flmcr1 after the elapse of at least (t spsu ) ?. the time during which the p bit is set is the flash memory programming time. make a program setting so that the time for one programming operation is within the range of (t sp ) ?. the wait time after p bit setting must be changed according to the degree of progress through the programming operation. for details see notes on program/program-verify mode. 489 17.6.2 program-verify mode in program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. after the elapse of the given programming time, clear the p bit in flmcr1, then wait for at least (t cp ) ? before clearing the psu bit to exit program mode. after exiting program mode, the watchdog timer setting is also cleared. the operating mode is then switched to program-verify mode by setting the pv bit in flmcr1. before reading in program-verify mode, a dummy write of h'ff data should be made to the addresses to be read. the dummy write should be executed after the elapse of (t spv ) ? or more. when the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. wait at least (t spvr ) ? after the dummy write before performing this read operation. next, the originally written data is compared with the verify data, and reprogram data is computed (see figure 17.10) and transferred to ram. after verification of 128 bytes of data has been completed, exit program-verify mode, wait for at least (t cpv ) ?, then clear the swe bit in flmcr1. if reprogramming is necessary, set program mode again, and repeat the program/program-verify sequence as before. the maximum number of repetitions of the program/program-verify sequence is indicated by the maximum programming count (n). leave a wait time of at least (t cswe ) ? after clearing swe. notes on program/program-verify procedure 1. the program/program-verify procedure for the h8/3026f-ztat version uses a 128-byte-unit programming algorithm. in order to perform 128-byte-unit programming, the lower 8 bits of the write start address must be h'00 or h'80. 2. when performing continuous writing of 128-byte data to flash memory, byte-unit transfer should be used. 128-byte data transfer is necessary even when writing fewer than 128 bytes of data. write h'ff data to the extra addresses. 3. verify data is read in word units. 4. the write pulse is applied and a flash memory write executed while the p bit in flmcr1 is set. in the h8/3026f-ztat version, write pulses should be applied as follows in the program/program-verify procedure to prevent voltage stress on the device and loss of write data reliability. a. after write pulse application, perform a verify-read in program-verify mode and apply a write pulse again for any bits read as 1 (reprogramming processing). when all the 0-write bits in the 128-byte write data are read as 0 in the verify-read operation, the program/program-verify procedure is completed. in the h8/3026f-ztat version, the number of loops in reprogramming processing is guaranteed not to exceed the maximum value of the maximum programming count (n). 490 b. after write pulse application, a verify-read is performed in program-verify mode, and programming is judged to have been completed for bits read as 0. the following processing is necessary for programmed bits. when programming is completed at an early stage in the program/program-verify procedure: if programming is completed in the 1st to 6th reprogramming processing loop, additional programming should be performed on the relevant bits. additional programming should only be performed on bits which first return 0 in a verify-read in certain reprogramming processing. when programming is completed at a late stage in the program/program-verify procedure: if programming is completed in the 7th or later reprogramming processing loop, additional programming is not necessary for the relevant bits. c. if programming of other bits is incomplete in the 128 bytes, reprogramming processing should be executed. if a bit for which programming has been judged to be completed is read as 1 in a subsequent verify-read, a write pulse should again be applied to that bit. 5. the period for which the p bit in flmcr1 is set (the write pulse width) should be changed according to the degree of progress through the program/program-verify procedure. for detailed wait time specifications, see section 21.2.6, flash memory characteristics. item symbol item symbol wait time after t sp when reprogramming loop count (n) is 1 to 6 t sp 30 p bit setting when reprogramming loop count (n) is 7 or more t sp 200 in case of additional programming processing* t sp 10 note: * additional programming processing is necessary only when the reprogramming loop count (n) is 1 to 6. 6. the program/program-verify flowchart for the h8/3026f-ztat version is shown in figure 17.10. to cover the points noted above, bits on which reprogramming processing is to be executed, and bits on which additional programming is to be executed, must be determined as shown below. since reprogram data and additional-programming data vary according to the progress of the programming procedure, it is recommended that the following data storage areas (128 bytes each) be provided in ram. 491 reprogram data computation table (d) result of verify-read after write pulse application (v) (x) result of operation comments 0 0 1 programming completed: reprogramming processing not to be executed 0 1 0 programming incomplete: reprogramming processing to be executed 10 1 ? 1 1 1 still in erased state: no action legend (d): source data of bits on which programming is executed (x): source data of bits on which reprogramming is executed additional-programming data computation table (x') result of verify-read after write pulse application (v) (y) result of operation comments 0 0 0 programming by write pulse application judged to be completed: additional programming processing to be executed 0 1 1 programming by write pulse application incomplete: additional programming processing not to be executed 1 0 1 programming already completed: additional programming processing not to be executed 1 1 1 still in erased state: no action legend (y): data of bits on which additional programming is executed (x'): data of bits on which reprogramming is executed in a certain reprogramming loop 7. it is necessary to execute additional programming processing during the course of the h8/3026f-ztat version program/program-verify procedure. however, once 128-byte-unit programming is finished, additional programming should not be carried out on the same address area. when executing reprogramming, an erase must be executed first. note that normal operation of reads, etc., is not guaranteed if additional programming is performed on addresses for which a program/program-verify operation has finished. 492 start end of programming set swe bit in flmcr1 start of programming write pulse application subroutine wait (t sswe ) s sub-routine write pulse end sub set psu bit in flmcr1 wdt enable disable wdt number of writes (n) 1 2 3 4 5 6 7 8 9 10 11 12 13 998 999 1000 note *6: write pulse width write time (tsp) s 30 30 30 30 30 30 200 200 200 200 200 200 200 200 200 200 wait (t spsu ) s set p bit in flmcr1 wait (t sp ) s clear p bit in flmcr1 wait (t cp ) s clear psu bit in flmcr1 wait (t cpsu ) s n= 1 m= 0 ng ng ng ng ok ok ok wait (t spv ) s wait (t spvr ) s * 2 * 7 * 7 * 4 * 7 * 7 start of programming programming halted * 5 * 7 * 7 * 7 * 1 wait (t cpv ) s write pulse sub-routine-call set pv bit in flmcr1 h'ff dummy write to verify address read verify data write data = verify data? * 4 * 3 * 7 * 7 * 7 * 1 transfer reprogram data to reprogram data area reprogram data computation * 4 transfer additional-programming data to additional-programming data area additional-programming data computation clear pv bit in flmcr1 clear swe bit in flmcr1 m = 1 reprogram see note *6 for pulse width m= 0 ? increment address programming failure ok clear swe bit in flmcr1 wait (t cswe ) s ng ok 6 n? ng ok 6 n ? wait (t cswe ) s n n? n n + 1 original data (d) verify data (v) reprogram data (x) comments programming completed still in erased state; no action programming incomplete; reprogram note: use a 10 s write pulse for additional programming. consecutively write 128-byte data in reprogram data area in ram to flash memory ram program data storage area (128 bytes) reprogram data storage area (128 bytes) additional-programming data storage area (128 bytes) store 128-byte program data in program data area and reprogram data area write pulse (additional programming) sub-routine-call 128-byte data verification completed? consecutively write 128-byte data in additional- programming data area in ram to flash memory reprogram data computation table reprogram data (x') verify data (v) additional- programming data (y) 1 1 1 1 0 1 0 0 0 0 1 1 comments additional programming to be executed additional programming not to be executed additional programming not to be executed additional programming not to be executed 0 1 1 1 0 1 0 1 0 0 1 1 additional-programming data computation table perform programming in the erased state. do not perform additional programming on previously programmed addresses. notes: *1 data transfer is performed by byte transfer. the lower 8 bits of the first address written to must be h'00 or h'80. a 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, h'ff data must be written to the extra addresses. *2 verify data is read in 16-bit (word) units. *3 reprogram data is determined by the operation shown in the table below (comparison between the data stored in the program dat a area and the verify data). bits for which the reprogram data is 0 are programmed in the next reprogramming loop. therefore, even bits for which programming has bee n completed will be subjected to programming once again if the result of the subsequent verify operation is ng. *4 a 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additio nal-programming data must be provided in ram. the contents of the reprogram data area and additional-programming data area are modified as programming proceeds. *5 a write pulse of 30 s or 200 s is applied according to the progress of the programming operation. see note 6 for details of the pulse widths. when writing o f additional-programming data is executed, a 10 s write pulse should be applied. reprogram data x' means reprogram data when the write pulse is applied. *7 the wait times and value of n are shown in section 21.2.6, flash memory characteristics. figure 17.10 program/program-verify flowchart (128-byte programming) 493 17.6.3 erase mode when erasing flash memory, the single-block erase flowchart shown in figure 17.11 should be followed. the wait times after bits are set or cleared in the flash memory control register 1 (flmcr1) and the maximum number of erase operations (n) are shown in table 21.19 in section 21.2.6, flash memory characteristics. to erase flash memory contents, make a 1-bit setting for the flash memory area to be erased in erase block register 1 and 2 (ebr1, ebr2) at least (t sswe ) ? after setting the swe bit to 1 in flmcr1. next, the watchdog timer (wdt) is set to prevent overerasing due to program runaway, etc. set a value greater than (t se ) ms + (t sesu + t ce + t cesu ) ? as the wdt overflow period. preparation for entering erase mode (erase setup) is performed next by setting the esu bit in flmcr1. the operating mode is then switched to erase mode by setting the e bit in flmcr1 after the elapse of at least (t sesu ) ?. the time during which the e bit is set is the flash memory erase time. ensure that the erase time does not exceed (t se ) ms. note: with flash memory erasing, preprogramming (setting all memory data in the memory to be erased to all 0) is not necessary before starting the erase procedure. 17.6.4 erase-verify mode in erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased. after the elapse of the fixed erase time, clear the e bit in flmcr1, then wait for at least (t ce ) ? before clearing the esu bit to exit erase mode. after exiting erase mode, the watchdog timer setting is also cleared. the operating mode is then switched to erase-verify mode by setting the ev bit in flmcr1. before reading in erase-verify mode, a dummy write of h'ff data should be made to the addresses to be read. the dummy write should be executed after the elapse of (t sev ) ? or more. when the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. wait at least (t sevr ) ? after the dummy write before performing this read operation. if the read data has been erased (all 1), a dummy write is performed to the next address, and erase-verify is performed. if the read data is unerased, set erase mode again, and repeat the erase/erase-verify sequence as before. the maximum number of repetitions of the erase/erase-verify sequence is indicated by the maximum erase count (n). when verification is completed, exit erase-verify mode, and wait for at least (t cev ) ?. if erasure has been completed on all the erase blocks, clear the swe bit in flmcr1, and leave a wait time of at least (t cswe ) ?. if erasing multiple blocks, set a single bit in ebr1/ebr2 for the next block to be erased, and repeat the erase/erase-verify sequence as before. 494 end of erasing start set swe bit in flmcr1 set esu bit in flmcr1 set e bit in flmcr1 wait (t sswe ) s wait (t sesu ) s n = 1 set ebr1 or ebr2 enable wdt * 3, * 4 * 5 * 5 * 5 * 5 * 5 * 5 * 5 * 5 * 5 * 5 * 5 * 5 wait (t se ) ms wait (t ce ) s wait (t cesu ) s wait (t sev ) s set block start address as verify address wait (t sevr ) s * 2 wait (t cev ) s start of erase clear e bit in flmcr1 clear esu bit in flmcr1 set ev bit in flmcr1 h'ff dummy write to verify address read verify data clear ev bit in flmcr1 wait (t cev ) s clear ev bit in flmcr1 re-erase clear swe bit in flmcr1 disable wdt end of erase * 1 verify data = all 1s? last address of block? erase failure clear swe bit in flmcr1 n n? no no no yes yes yes n n + 1 increment address wait (t cswe ) s wait (t cswe ) s notes: *1 prewriting (setting erase block data to all 0s) is not necessary. *2 verify data is read in 16-bit (word) units. *3 make only a single-bit specification in the erase block registers (ebr1 and ebr2). two or more bits must not be set simultane ously. *4 erasing is performed in block units. to erase multiple blocks, each block must be erased in turn. *5 the wait times and the value of n are shown in section 21.2.6, flash memory characteristics. perform erasing in block units. figure 17.11 erase/erase-verify flowchart (single-block erasing) 495 17.7 flash memory protection there are three kinds of flash memory program/erase protection: hardware, software, and error protection. 17.7.1 hardware protection hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. in this state, the settings in flash memory control register 1 (flmcr1) and erase block registers 1 and 2 (ebr1, ebr2) are reset. in the error protection state, the flmcr1, ebr1, and ebr2 settings are retained; the p bit and e bit can be set, but a transition is not made to program mode or erase mode. (see table 17.8.) table 17.8 hardware protection function item description program erase verify fwe pin protection ? when a low level is input to the fwe pin, flmcr1, ebr1, and ebr2 are initialized, and the program/erase-protected state is entered. not possible* 1 not possible* 3 not possible reset/ standby protection ? in a reset (including a wdt overflow reset) and in standby mode, flmcr1, flmcr2, ebr1, and ebr2 are initialized, and the program/erase-protected state is entered. ? in a reset via the res pin, the reset state is not entered unless the res pin is held low until oscillation stabilizes after powering on. in the case of a reset during operation, hold the res pin low for the res pulse width specified in the ac characteristics section.* 4 not possible not possible* 3 not possible error protection ? when a microcomputer operation error (error generation (fler = 1)) was detected while flash memory was being programmed/erased, error protection is enabled. at this time, the flmcr1, ebr1, and ebr2 settings are held, but programming/erasing is aborted at the time the error was generated. error protection is released only by a reset via the res pin or a wdt reset, or in the hardware standby mode. not possible not possible* 3 possible* 2 notes: *1 the ram area that overlapped flash memory is deleted. *2 it is possible to perform a program-verify operation on the 128 bytes being programmed, or an erase-verify operation on the block being erased. 496 *3 all blocks are unerasable and block-by-block specification is not possible. *4 see section 4.2.2, reset sequence, and section 17.11, flash memory programming and erasing precautions. the h8/3026f-ztat version requires a minimum of 20 system clock cycles for a reset during operation. 17.7.2 software protection software protection can be implemented by setting the erase block register 1 (ebr1), erase block register 2 (ebr2), and the rams bit in the ram control register (ramcr). with software protection, setting the p or e bit in the flash memory control register 1 (flmcr1) does not cause a transition to program mode or erase mode. (see table 17.9.) table 17.9 software protection functions item description program erase verify block protection ? erase protection can be set for individual blocks by settings in erase block register 1 (ebr1) and erase block register 2 (ebr2)* 2 . however, programming protection is disabled. ? setting ebr1 and ebr2 to h'00 places all blocks in the erase-protected state. ? not possible possible emulation protection ? setting the rams bit 1 in ramcr places all blocks in the program/erase-protected state. not possible* 1 not possible* 3 possible notes: *1 the ram area overlapping flash memory can be written to. *2 when not erasing, set ebr1 and ebr2 to h'00. *3 all blocks are unerasable and block-by-block specification is not possible. 17.7.3 error protection in error protection, an error is detected when mcu runaway occurs during flash memory programming/erasing* 1 , or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. if the mcu malfunctions during flash memory programming/erasing, the fler bit is set to 1 in the flash memory status register (flmsr2) and the error protection state is entered. flmcr1, flmcr2, ebr1, and ebr2 settings* 3 are retained, but program mode or erase mode is aborted at the point at which the error occurred. program mode or erase mode cannot be re-entered by re- 497 setting the p or e bit in flmcr. however, pv and ev bit setting is enabled, and a transition can be made to verify mode* 2 . fler bit setting conditions are as follows: 1. when flash memory is read during programming/erasing (including a vector read or instruction fetch) 2. immediately after the start of exception handling during programming/erasing (excluding reset, illegal instruction, trap instruction, and division-by-zero exception handling) 3. when a sleep instruction (including software standby) is executed during programming/erasing 4. when the bus is released during programming/erasing error protection is released only by a res 498 rd vf pr er fler = 0 error occurrence res = 0 or stby = 0 res = 0 or stby = 0 rd vf pr er init fler = 0 program mode erase mode reset or standby (hardware protection) rd vf pr er fler = 1 rd vf pr er init fler = 1 error protection mode error protection mode (software standby) software standby mode flmcr1, ebr1, ebr2 initialization state flmcr1, flmcr2, ebr1, ebr2 initialization state software standby mode release rd: memory read possible vf: verify-read possible pr: programming possible er: erasing possible rd : memory read not possible vf : verify-read not possible pr : programming not possible er : erasing not possible init: register initialization state res = 0 or stby = 0 error occurrence (software standby) figure 17.12 flash memory state transitions (when high level is applied to fwe pin in mode 5 or 7 (on-chip rom enabled)) the error protection function is invalid for abnormal operations other than the fler bit setting conditions. also, if a certain time has elapsed before this protection state is entered, damage may already have been caused to the flash memory. consequently, this function cannot provide complete protection against damage to flash memory. to prevent such abnormal operations, therefore, it is necessary to ensure correct operation in accordance with the program/erase algorithm, with the flash write enable (fwe) voltage applied, and to conduct constant monitoring for mcu errors, internally and externally, using the watchdog timer or other means. there may also be cases where the flash memory is in an erroneous programming or erroneous erasing state at the point of transition to this protection mode, or where programming or erasing is not properly carried out because of an abort. in cases such as these, a forced recovery (program rewrite) must be executed using boot mode. however, it may also happen that boot mode cannot be normally initiated because of overprogramming or overerasing. 499 17.8 flash memory emulation in ram making a setting in the ram control register (ramcr) enables part of ram to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in ram in real time. after the ramcr setting has been made, accesses can be made from the flash memory area or the ram area overlapping flash memory. emulation can be performed in user mode and user program mode. figure 17.13 shows an example of emulation of realtime flash memory programming. yes no set ramcr write tuning data to overlap ram execute application program tuning ok? clear ramcr write to flash memory emulation block start of emulation program end of emulation program figure 17.13 flowchart of flash memory emulation in ram 500 h'00000 h'01000 h'02000 h'03000 h'04000 h'05000 h'06000 h'07000 h'08000 h'3ffff flash memory eb8 to eb11 this area can be accessed from both the ram area and flash memory area eb0 eb1 eb2 eb3 eb4 eb5 eb6 eb7 h'ffe000 h'ffefff h'ffff1f on-chip ram figure 17.14 example of ram overlap operation example of flash memory block area eb0 overlapping 1. set bits rams and ram2 to ram0 in ramcr to 1,0, 0, 0, to overlap part of ram onto the area (eb0) for which realtime programming is required. 2. realtime programming is performed using the overlapping ram. 3. after the program data has been confirmed, the rams bit is cleared, releasing ram overlap. 4. the data written in the overlapping ram is written into the flash memory space (eb0). notes: 1. when the rams bit is set to 1, program/erase protection is enabled for all blocks regardless of the value of ram2 to ram0 (emulation protection). in this state, setting the p or e bit in flmcr1 will not cause a transition to program mode or erase mode. when actually programming or erasing a flash memory area, the rams bit should be cleared to 0. 2. a ram area cannot be erased by execution of software in accordance with the erase algorithm while flash memory emulation in ram is being used. 3. block area eb0 contains the vector table. when performing ram emulation, the vector table is needed in the overlap ram. 501 4. as in on-board programming mode, care is required when applying and releasing fwe to prevent erroneous programming or erasing. to prevent erroneous programming and erasing due to program runaway during fwe application, in particular, the watchdog timer should be set when the psu, p, esu, or e bit is set to 1 in flmcr1, even while the emulation function is being used. 5. when the emulation function is used, nmi input is prohibited when the p bit or e bit is set to 1 in flmcr1, in the same way as with normal programming and erasing. the p and e bits are cleared by a reset (including a watchdog timer reset), in standby mode, when a high level is not being input to the fwe pin, or when the swe bit in flmcr1 is 0 while a high level is being input to the fwe pin. 17.9 nmi input disabling conditions all interrupts, including nmi input, should be disabled while flash memory is being programmed or erased (while the p bit or e bit is set in flmcr1), and while the boot program is executing in boot mode* 1 , to give priority to the program or erase operation. there are three reasons for this: 1. nmi input during programming or erasing might cause a violation of the programming or erasing algorithm, with the result that normal operation could not be assured. 2. in the nmi exception handling sequence during programming or erasing, the vector would not be read correctly* 2 , possibly resulting in mcu runaway. 3. if nmi input occurred during boot program execution, it would not be possible to execute the normal boot mode sequence. for these reasons, in on-board programming mode alone there are conditions for disabling nmi input, as an exception to the general rule. however, this provision does not guarantee normal erasing and programming or mcu operation. all interrupt requests (exception handling and bus release), including nmi, must therefore be restricted inside and outside the mcu during fwe application. nmi input is also disabled in the error protection state and while the p or e bit remains set in flmcr1 during flash memory emulation in ram. notes: *1 this is the interval until a branch is made to the boot program area in the on-chip ram (this branch takes place immediately after transfer of the user program is completed). consequently, after the branch to the ram area, nmi input is enabled except during programming and erasing. interrupt requests must therefore be disabled inside and outside the mcu until the user program has completed initial programming (including the vector table and the nmi interrupt handling routine). *2 the vector may not be read correctly in this case for the following two reasons: if flash memory is read while being programmed or erased (while the p bit or e bit is set in flmcr1), correct read data will not be obtained (undetermined values will be returned). if the entry in the interrupt vector table has not been programmed yet, interrupt exception handling will not be executed correctly. 502 17.10 flash memory prom mode the h8/3026f-ztat version have a prom mode as well as the on-board programming modes for programming and erasing flash memory. in prom mode, the on-chip rom can be freely programmed using a general-purpose prom writer that supports the hitachi microcomputer device type with 256-kbyte on-chip flash memory. 17.10.1 socket adapters and memory map in prom mode using a prom writer, memory reading (verification) and writing and flash memory initialization (total erasure) can be performed. for these operations, a special socket adapter is mounted in the prom writer. the socket adapter product codes are given in table 17.10. in the h8/3026f-ztat version prom mode, only the socket adapters shown in this table should be used. table 17.10 h8/3026f-ztat version socket adapter product codes product code package socket adapter product code manufacturer hd64f3026f 100-pin qfp (fp-100b) tbd minato electronics inc. hd64f3026te 100-pin tqfp (tfp-100b) tbd hd64f3026fp 100-pin qfp (fp-100a) tbd hd64f3026f 100-pin qfp (fp-100b) tbd data i/o japan co. hd64f3026te 100-pin tqfp (tfp-100b) tbd hd64f3026fp 100-pin qfp (fp-100a) tbd figure 17.15 shows the memory map in prom mode. h8/3026f-ztat version h'000000 h'03ffff h'00000 h'3ffff mcu mode prom mode on-chip rom figure 17.15 memory map in prom mode 503 17.10.2 notes on use of prom mode 1. a write to a 128-byte programming unit in prom mode should be performed once only. erasing must be carried out before reprogramming an address that has already been programmed. 2. when using a prom writer to reprogram a device on which on-board programming/erasing has been performed, it is recommended that erasing be carried out before executing programming. 3. the memory is initially in the erased state when the device is shipped by hitachi. for samples for which the erasure history is unknown, it is recommended that erasing be executed to check and correct the initialization (erase) level. 4. the h8/3026f-ztat version does not support a product identification mode as used with general-purpose eproms, and therefore the device name cannot be set automatically in the prom writer. 5. refer to the instruction manual provided with the socket adapter, or other relevant documentation, for information on prom writers and associated program versions that are compatible with the prom mode of the h8/3026f-ztat version. 17.11 flash memory programming and erasing precautions precautions concerning the use of on-board programming mode, the ram emulation function, and prom mode are summarized below. 1. use the specified voltages and timing for programming and erasing. applied voltages in excess of the rating can permanently damage the device. use a prom programmer that supports the hitachi microcomputer device type with 256-kbyte on-chip flash memory. 2. powering on and off (see figures 17.16 to 17.18) do not apply a high level to the fwe pin until v cc has stabilized. also, drive the fwe pin low before turning off v cc . when applying or disconnecting v cc power, fix the fwe pin low and place the flash memory in the hardware protection state. the power-on and power-off timing requirements should also be satisfied in the event of a power failure and subsequent recovery. failure to do so may result in overprogramming or overerasing due to mcu runaway, and loss of normal memory cell operation. 3. fwe application/disconnection fwe application should be carried out when mcu operation is in a stable condition. if mcu operation is not stable, fix the fwe pin low and set the protection state. the following points must be observed concerning fwe application and disconnection to prevent unintentional programming or erasing of flash memory: 504 apply fwe when the v cc voltage has stabilized within its rated voltage range. if fwe is applied when the mcu s v cc power supply is not within its rated voltage range, mcu operation will be unstable and flash memory may be erroneously programmed or erased. apply fwe when oscillation has stabilized (after the elapse of the oscillation settling time). when v cc power is turned on, hold the res in boot mode, apply and disconnect fwe during a reset. in a transition to boot mode, fwe = 1 input and md 2 md 0 setting should be performed while the res md 0 pin input must satisfy the mode programming setup time (t mds ) with respect to the reset release timing. when making a transition from boot mode to another mode, also, a mode programming setup time is necessary with respect to the reset release timing. in a reset during operation, the res in user program mode, fwe can be switched between high and low level regardless of res do not apply fwe if program runaway has occurred. during fwe application, the program execution state must be monitored using the watchdog timer or some other means. disconnect fwe only when the swe, esu, psu, ev, pv, e, and p bits in flmcr1 are cleared. make sure that the swe, esu, psu, ev, pv, e, and p bits are not set by mistake when applying or disconnecting fwe. 4. do not apply a constant high level to the fwe pin. t prevent erroneous programming or erasing due to program runaway, etc., apply a high level to the fwe pin only when programming or erasing flash memory (including execution of flash memory emulation using ram). a system configuration in which a high level is constantly applied to the fwe pin should be avoided. also, while a high level is applied to the fwe pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. 5. use the recommended algorithm when programming and erasing flash memory. the recommended algorithm enables programming and erasing to be carried out without subjecting the device to voltage stress or sacrificing program data reliability. when setting the p or e bit in flmcr1, the watchdog timer should be set beforehand as a precaution against program runaway, etc. 505 also note that access to the flash memory space by means of a mov instruction, etc., is not permitted while the p bit or e bit is set. 6. do not set or clear the swe bit during execution of a program in flash memory. clear the swe bit before executing a program or reading data in flash memory. when the swe bit is set, data in flash memory can be rewritten, but flash memory should only be accessed for verify operations (verification during programming/erasing). similarly, when using the ram emulation function while a high level is being input to the fwe pin, the swe bit must be cleared before executing a program or reading data in flash memory. however, the ram area overlapping flash memory space can be read and written to regardless of whether the swe bit is set or cleared. a wait time is necessary after the swe bit is cleared. for details see table 21.19 in section 21.2.6, flash memory characteristics. 7. do not use interrupts while flash memory is being programmed or erased. all interrupt requests, including nmi, should be disabled during fwe application to give priority to program/erase operations (including emulation in ram). bus release must also be disabled. 8. do not perform additional programming. erase the memory before reprogramming. in on-board programming, perform only one programming operation on a 128-byte programming unit block. programming should be carried out with the entire programming unit block erased. 9. before programming, check that the chip is correctly mounted in the prom writer. overcurrent damage to the device can result if the index marks on the prom writer socket, socket adapter, and chip are not correctly aligned. 10. do not touch the socket adapter or chip during programming. touching either of these can cause contact faults and write errors. 11. a wait time of 100 ? or more is necessary when performing a read after a transition to normal mode from program, erase, or verify mode. 12. use byte access on the registers that control the flash memory (flmcr1, flmcr2, ebr1, ebr2, and ramcr). 506 period during which flash memory access is prohibited (x: wait time after setting swe bit, y: wait time after clearing swe bit) * 2 period during which flash memory can be programmed (execution of program in flash memory prohibited, and data reads other than verify operations prohibited) notes: *1 except when switching modes, the level of the mode pins (md 2 e md 0 ) must be fixed until power-off by pulling the pins up or down. *2 see section 21.2.6, flash memory characteristics. v cc fwe t osc1 min 0 s t mds t mds md 2 to md 0 * 1 res swe bit swe set swe cleared program- ming/ erasing possible wait time: x wait time: y min 0 s figure 17.16 power-on/off timing (boot mode) 507 period during which flash memory access is prohibited (x: wait time after setting swe bit, y: wait time after clearing swe bit) * 2 period during which flash memory can be programmed (execution of program in flash memory prohibited, and data reads other than verify operations prohibited) v cc fwe t osc1 min 0 s t mds md 2 to md 0 * 1 res swe bit swe set swe cleared program- ming/ erasing possible wait time: x wait time: y notes: *1 except when switching modes, the level of the mode pins (md 2 e md 0 ) must be fixed until power-off by pulling the pins up or down. *2 see section 21.2.6, flash memory characteristics. figure 17.17 power-on/off timing (user program mode) 508 period during which flash memory access is prohibited (x: wait time after setting swe bit, y: wait time after clearing swe bit) * 3 period during which flash memory can be programmed (execution of program in flash memory prohibited, and data reads other than verify operations prohibited) v cc fwe t osc1 min 0 s t mds t mds t mds t resw md 2 to md 0 res swe bit mode change * 1 user mode boot mode user program mode swe set swe cleared * 2 programming/ erasing possible wait time: x wait time: y programming/ erasing possible wait time: x wait time: y programming/ erasing possible wait time: x programming/ erasing possible wait time: x wait time: y mode change * 1 user mode user program mode notes: *1 when entering boot mode or making a transition from boot mode to another mode, mode switching must be carried out by means of res input. the state of ports with multiplexed address functions and bus control output pins ( csn , as , rd , wr ) will change during this switchover interval (the interval during which the res pin input is low), and therefore these pins should not be used as output signals during this time. *2 when making a transition from boot mode to another mode, the mode programming setup time t mds must be satisfied with respect to res clearance timing. *3 see section 21.2.6, flash memory characteristics. figure 17.18 mode transition timing (example: boot mode user mode ? ? ? ? user program mode) 509 17.12 mask rom (h8/3026 mask rom version) overview 17.12.1 block diagram figure 17.19 shows a block diagram of the rom. h'00000 h'00002 h'1fffe h'00001 h'00003 h'1ffff internal data bus (upper 8 bits) internal data bus (lower 8 bits) on-chip rom even addresses odd addresses figure 17.19 rom block diagram (h8/3026 mask rom version) 510 17.13 notes on ordering mask rom version chip when ordering h8/3026 with mask rom, note the following. 1. when ordering by means of an eprom, use a 512-kbyte one. 2. fill all unused addresses with h'ff as shown in figure 17.20 to make the rom data size 512- kbytes for the h8/3026 mask rom version. this applies to ordering by means of an eprom and by means of data transmission. h'00000 h'7ffff h'3ffff h'40000 hd6433026 (rom: 256 kbytes) addresses: h'00000 e 7ffff not used* note: * write h'ff in all addresses in these areas. figure 17.20 mask rom addresses and data 3. the flash memory control registers (flmcr, ebr, ramcr, flmsr, flmcr1, flmcr2, ebr1, and ebr2) used by the version with on-chip flash memory are not provided in the mask rom version. reading the corresponding addresses in a mask rom version will always return 1s, and writes to these addresses are disabled. this must be borne in mind when switching from a flash memory version to a mask rom version. 511 17.14 notes when converting the f-ztat application software to the mask rom versions please note the following when converting the f-ztat application software to the mask rom versions. the values read from the internal registers for the flash rom or the mask rom version and f-ztat version differ as follows. status register bit value f-ztat version mask rom version flmcr fwe 0 application software running ? (is not read out) 1 programming application software running (always read as 1) note: this difference applies to all the f-ztat versions and all the mask rom versions that have different rom size. 512 513 section 18 flash memory [h8/3024f-ztat version] 18.1 overview the h8/3024f-ztat version has 128 kbytes of on-chip flash memory. the flash memory is connected to the cpu by a 16-bit data bus. the cpu accesses both byte data and word data in two states, enabling rapid data transfer. the on-chip rom is enabled and disabled by setting the mode pins (md 2 to md 0 ) as shown in table 18.1. the on-chip flash memory product (h8/3024f-ztat version) can be erased and programmed on- board, as well as with a special-purpose prom programmer. table 18.1 operating modes and rom mode pins mode md2 md1 md0 on-chip rom mode 1 (expanded 1-mbyte mode with on-chip rom disabled) 0 0 1 disabled (external address area) mode 2 (expanded 1-mbyte mode with on-chip rom disabled) 010 mode 3 (expanded 16-mbyte mode with on-chip rom disabled) 011 mode 4 (expanded 16-mbyte mode with on-chip rom disabled) 100 mode 5 (expanded 16-mbyte mode with on-chip rom enabled) 1 0 1 enabled mode 6 (single-chip normal mode) 1 1 0 mode 7 (single-chip advanced mode) 1 1 1 514 18.2 features the h8/3024f-ztat version has 128 kbytes of on-chip flash memory. the features of the flash memory are summarized below. ? four flash memory operating modes ? program mode ? erase mode ? program-verify mode ? erase-verify mode ? programming/erase methods the flash memory is programmed 128 bytes at a time. erasing is performed in block units. to erase the entire flash memory, each block must be erased in turn. in block erasing, 1-kbyte, 28- kbyte, and 32-kbyte blocks can be set arbitrarily. ? programming/erase times the flash memory programming time is 10 ms (typ.) for simultaneous 128-byte programming, equivalent approximately to 80 ? (typ.) per byte, and the erase time is 100 ms (typ.) per block. ? reprogramming capability the flash memory can be reprogrammed up to 100 times. ? on-board programming modes there are two modes in which flash memory can be programmed/erased/verified on-board. a function is also provided specially in boot mode for identifying a program transferred from the host side.: ? boot mode ? user program mode ? automatic bit rate adjustment for data transfer in boot mode, the h8/3024f-ztat version chip? bit rate can be automatically adjusted to match the transfer bit rate of the host. ? flash memory emulation in ram flash memory programming can be emulated in real time by overlapping a part of ram onto flash memory. ? protect modes there are three protect modes?ardware, software, and error?hich allow protected status to be designated for flash memory program/erase/verify operations ? prom mode flash memory can be programmed/erased in prom mode, using a prom programmer, as well as in on-board programming mode. 515 18.2.1 block diagram module bus bus interface/controller flash memory (128 kbytes) operating mode internal address bus internal data bus (16 bits) fwe pin mode pins flmcr2 legend flmcr1: flash memory control register 1 flmcr2: flash memory control register 2 ebr: erase block register ramcr: ram control register ebr ramcr flmcr1 figure 18.1 block diagram of flash memory 516 18.2.2 pin configuration the flash memory is controlled by means of the pins shown in table 18.2. table 18.2 flash memory pins pin name abbreviation i/o function reset res 18.2.3 register configuration the registers used to control the on-chip flash memory when enabled are shown in table 18.3. table 18.3 flash memory registers register name abbreviation r/w initial value address* 1 flash memory control register 1 flmcr1 r/w h'00* 2 h'ee030 flash memory control register 2 flmcr2 r h'00 h'ee031 erase block register ebr r/w h'00 h'ee032 ram control register ramcr r/w h'f1 h'ee077 notes: flmcr1, flmcr2, ebr, and ramcr are 8-bit registers, and should be accessed by byte access. these registers are used only in the versions with on-chip flash memory, and are not provided in the versions with on-chip mask rom. reading the corresponding addresses in a mask rom version will always return 1s, and writes to these addresses are invalid. *1 lower 20 bits of address in advanced mode. *2 when a high level is input to the fwe pin, the initial value is h'80. 517 18.3 register descriptions 18.3.1 flash memory control register 1 (flmcr1) bit 76543210 fwe swe esu psu ev pv e p initial value ? 0 0 0 0 0 0 0 read/write r r/w r/w r/w r/w r/w r/w r/w note: * determined by the state of the fwe pin. flmcr1 is an 8-bit register used for flash memory operating mode control. program-verify mode or erase-verify mode for addresses h'00000 to h'1ffff is entered by setting the swe bit when fwe = 1, then setting the pv or ev bit. program mode for addresses h'00000 to h'1ffff is entered by setting the swe bit when fwe = 1, then setting the psu bit, and finally setting the p bit. erase mode for addresses h'00000 to h'1ffff is entered by setting the swe bit when fwe = 1, then setting the esu bit, and finally setting the e bit. flmcr1 is initialized by a reset, and in hardware standby mode and software standby mode. its initial value is h'80 when a high level is input to the fwe pin, and h'00 when a low level is input. in mode 6 the fwe pin must be fixed low since flash memory on-board programming modes are not supported. when the on-chip flash memory is disabled, a read access to this register will return h'00, and writes are invalid. when setting bits 6 to 0 in this register, one bit must be set one at a time. writes to the swe bit in flmcr1 are enabled only when fwe = 1; writes to bits esu, psu, ev, and pv only when fwe = 1 and swe = 1; writes to the e bit only when fwe = 1, swe = 1, and esu = 1; and writes to the p bit only when fwe = 1, swe = 1, and psu = 1. notes: 1. the programming and erase flowcharts must be followed when setting the bits in this register to prevent erroneous programming or erasing. 2. transitions are made to program mode, erase mode, program-verify mode, and erase- verify mode according to the settings in this register. when reading flash memory as normal on-chip rom, bits 6 to 0 in this register must be cleared. bit 7?lash write enable (fwe): sets hardware protection against flash memory programming/erasing. bit 7 fwe description 0 when a low level is input to the fwe pin (hardware-protected state) 1 when a high level is input to the fwe pin 518 bit 6?oftware write enable (swe): enables or disables flash memory programming and erasing. (this bit should be set when setting bits 5 to 0 and ebr bits 7 to 0.) bit 6 swe description 0 programming/erasing disabled (initial value) 1 programming/erasing enabled [setting condition] when fwe = 1 note: do not execute a sleep instruction while the swe bit is set to 1. bit 5?rase setup (esu): prepares for a transition to erase mode. set this bit to 1 before setting the e bit to 1 in flmcr1 (do not set the swe, psu, ev, pv, e, or p bit at the same time). bit 5 esu description 0 erase setup cleared (initial value) 1 erase setup [setting condition] when fwe = 1 and swe = 1 bit 4?rogram setup (psu): prepares for a transition to program mode. set this bit to 1 before setting the p bit to 1 in flmcr1 (do not set the swe, esu, ev, pv, e, or p bit at the same time). bit 4 psu description 0 program setup cleared (initial value) 1 program setup [setting condition] when fwe = 1 and swe = 1 bit 3?rase-verify mode (ev): selects erase-verify mode transition or clearing. (do not set the swe, esu, psu, pv, e, or p bit at the same time.) bit 3 ev description 0 erase-verify mode cleared (initial value) 1 transition to erase-verify mode [setting condition] when fwe = 1 and swe = 1 519 bit 2?rogram-verify mode (pv): selects program-verify mode transition or clearing. (do not set the swe, esu, psu, ev, e, or p bit at the same time.) bit 2 pv description 0 program-verify mode cleared (initial value) 1 transition to program-verify mode [setting condition] when fwe = 1 and swe = 1 bit 1?rase mode (e): selects erase mode transition or clearing. (do not set the swe, esu, psu, ev, pv, or p bit at the same time.) bit 1 e description 0 erase mode cleared (initial value) 1 transition to erase mode [setting condition] when fwe = 1, swe = 1, and esu = 1 note: do not access the flash memory while the e bit is set. bit 0?rogram (p): selects program mode transition or clearing. (do not set the swe, esu, psu, ev, pv, or e bit at the same time.) bit 0 p description 0 program mode cleared (initial value) 1 transition to program mode [setting condition] when fwe = 1, swe = 1, and psu = 1 note: do not access the flash memory while the p bit is set. 520 18.3.2 flash memory control register 2 (flmcr2) bit 76543210 fler initial value 0 0 0 0 0 0 0 0 read/write r r r r r r r r flmcr2 is an 8-bit register used for flash memory operating mode control. flmcr2 is initialized to h'00 by a reset, and in hardware standby mode and software standby mode. when the on-chip flash memory is disabled, a read will return h'00. note: flmcr2 is a read-only register, and should not be written to. bit 7?lash memory error (fler): indicates that an error has occurred during an operation on flash memory (programming or erasing). when fler is set to 1, flash memory goes to the error- protection state. bit 7 fler description 0 flash memory is operating normally flash memory program/erase protection (error protection) is disabled [clearing condition] reset ( res ? ? ? ? bits 6 to 0?eserved: these bits are always read as 0. 521 18.3.3 erase block register (ebr) ebr is an 8-bit register that designates the flash memory block for erasure. ebr is initialized to h'00 by a reset, in hardware standby mode or software standby mode, when a high level is not input to the fwe pin, or when the swe bit in flmcr1 is 0 when a high level is applied to the fwe pin. when a bit is set in ebr, the corresponding block can be erased. other blocks are erase- protected. the blocks are erased block by block. therefore, set only one bit in ebr; do not set bits in ebr to erase two or more blocks at the same time. each bit in ebr cannot be set until the swe bit in flmcr1 is set. the flash memory block configuration is shown in table 18.4. to erase all the blocks, erase each block sequentially. the h8/3024f-ztat version does not support the on-board programming mode in mode 6, so bits in this register cannot be set to 1 in mode 6. 7 eb7 0 r 6 eb6 0 r 5 eb5 0 r 4 eb4 0 r 3 eb3 0 r 0 eb0 0 r 2 eb2 0 r 1 eb1 0 r bit initial value read/write 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w initial value read/write modes 5 and 7 modes 1 to 4, and 6 bits 7 to 0?lock 7 to block 0 (eb7 to eb0): setting one of these bits specifies the corresponding block (eb7 to eb0) for erasure. bits 7? eb7?b0 description 0 corresponding block (eb7 to eb0) not selected (initial value) 1 corresponding block (eb7 to eb0) selected note: when not performing an erase, clear all ebr bits to 0. 522 table 18.4 flash memory erase blocks block (size) address eb0 (1 kbyte) h'000000 e h'0003ff eb1 (1 kbyte) h'000400 e h'0007ff eb2 (1 kbyte) h'000800 e h'000bff eb3 (1 kbyte) h'000c00 e h'000fff eb4 (28 kbytes) h'001000 e h'007fff eb5 (32 kbytes) h'008000 e h'00ffff eb6 (32 kbytes) h'010000 e h'017fff eb7 (32 kbytes) h'018000 e h'01ffff 18.3.4 ram control register (ramcr) ramcr selects the ram area to be used when emulating real-time flash memory programming. 1 ? 1 ? 1 ? 1 ? 0 r/w * 1 ? 0 r/w * 0 r/w * initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 rams 0 r 0 ? 1 ? 2 ram2 0 r 1 ram1 0 r bit initial value read/write reserved bits reserved bit ram2, ram1 used together with bit 3 to select a flash memory area ram select used together with bits 2 and 1 to select a flash memory area modes 5 to 7 modes 1 to 4 note: * cannot be set to 1 in mode 6. bits 7 to 4?eserved: read-only bits, always read as 1. bit 3?am select (rams): used with bits 2 to 1 to reassign an area to ram (see table 18.5). the initial setting for this bit is 0 in modes 5, 6, and 7 (internal flash memory enabled) and programming is enabled.* in modes other than 5 to 7, 0 is always read and writing is disabled. this bit is initialized by a reset and in hardware standby mode. it is not initialized in software standby mode. 523 when 1 is written to the rams bit, all flash memory blocks are protected from programming and erasing. bits 2 and 1?am2 and ram1: these bits are used with bit 3 to reassign an area to ram (see table 18.5). the initial setting for this bit is 0 in modes 5, 6, and 7 (internal flash memory enabled) and programming is enabled.* in modes other than 5 to 7, 0 is always read and writing is disabled. these bits are initialized by a reset and in hardware standby mode. they are not initialized in software standby mode. bit 0?eserved: this bit cannot be modified and is always read as 1. note: * flash memory emulation by ram is not supported for mode 6 (single chip normal mode), so programming is possible, but do not set 1. when performing flash memory emulation by ram, the rame bit in syscr must be set to 1. table 18.5 ram area setting bit 3 bit 2 bit 1 ram area rams ram2 ram1 ram emulation status h ? fff000 e h ? fff3ff 0 0/1 0/1 no emulation h ? 000000 e h ? 0003ff 1 0 0 mapping ram h ? 000400 e h ? 0007ff 1 0 1 h ? 000800 e h ? 000bff 1 1 0 h ? 000c00 e h ? 000fff 1 1 1 rom area ram area eb0 h'000000 h'0003ff h'000400 h'0007ff h'000800 h'000bff h'ffef20 h'ffefff h'fff000 h'fff3ff h'fff400 h'ffff1f h'000c00 h'000fff eb1 mapping ram eb2 eb3 actual ram ram overlap area (h'fff000 e h'fff3ff) rom blocks eb0 e eb3 (h'000000 e h'000fff) ram selection area rom selection area figure 18.2 example of rom area/ram area overlap 524 18.4 overview of operation 18.4.1 mode transitions when the mode pins and the fwe pin are set in the reset state and a reset-start is executed, the h8/3024f-ztat version enters one of the operating modes shown in figure 18.3. in user mode, flash memory can be read but not programmed or erased. flash memory can be programmed and erased in boot mode, user program mode, and prom mode. boot mode and user program mode cannot be used in the h8/3024f-ztat version s mode 6 (normal mode with on-chip rom enabled). 525 boot mode on-board programming mode user program mode user mode with on-chip rom enabled reset state prom mode res = 0 fwe = 0 res = 0 res = 0 res = 0 * 1 * 1 * 3 * 2 * 4 * 5 * 4 notes: only make a transition between user mode and user program mode when the cpu is not accessing the flash memory. *1 ram emulation possible *2 the h8/3024f-ztat version is placed in prom mode by means of a dedicated prom writer. *3 md 2 , md 1 , md 0 = (1, 0, 1) (1, 1, 0) (1, 1, 1) fwe = 0 *4 md 2 , md 1 , md 0 = (1, 0, 1) (1, 1, 1) fwe = 1 *5 md 2 , md 1 , md 0 (0, 0, 1) (0, 1, 1) fwe = 1 figure 18.3 flash memory related state transitions state transitions between the normal and user modes and on-board programming mode are performed by changing the fwe pin level from high to low or from low to high. to prevent misoperation (erroneous programming or erasing) in these cases, the bits in the flash memory control register (flmcr1) should be cleared to 0 before making such a transition. after the bits are cleared, a wait time is necessary. normal operation is not guaranteed if this wait time is insufficient. 526 18.4.2 on-board programming modes example of boot mode operation flash memory h8/3024f-ztat version ram host programming control program sci application program (old version) new application program flash memory h8/3024f-ztat version ram host sci application program (old version) boot program area new application program flash memory h8/3024f-ztat version ram host sci flash memory prewrite-erase boot program new application program flash memory h8/3024f-ztat version program execution state ram host sci new application program boot program programming control program boot program area 1. initial state the old program version or data remains written in the flash memory. the user should prepare the programming control program and new application program beforehand in the host. 2. programming control program transfer when boot mode is entered, the boot program in the h8/3024f-ztat version (originally incorporated in the chip) is started and the programming control program in the host is transferred to ram via sci communication. the boot program required for flash memory erasing is automatically transferred to the ram boot program area. 3. flash memory initialization the erase program in the boot program area (in ram) is executed, and the flash memory is initialized (to h'ff). in boot mode, total flash memory erasure is performed, without regard to blocks. 4. writing new application program an identification check is carried out to see if the programming control program is compatible with the h8/3024f-ztat version. the programming control program transferred from the host to ram is executed, and the new application program in the host is written into the flash memory. boot program boot program programming control program boot program area programming control program 527 example of user program mode operation flash memory h8/3024f-ztat version ram host programming/erase control program sci boot program new application program flash memory h8/3024f-ztat version ram host sci new application program flash memory h8/3024f-ztat version ram host sci flash memory erase boot program new application program flash memory h8/3024f-ztat version program execution state ram host sci boot program programming/erase control program boot program fwe assessment program transfer program application program (old version) application program (old version) fwe assessment program transfer program new application program fwe assessment program transfer program 1. initial state the fwe assessment program that confirms that user program mode has been entered, and the program that will transfer the programming/ erase control program from flash memory to on-chip ram should be written into the flash memory by the user beforehand. the programming/erase control program should be prepared in the host or in the flash memory. 3. flash memory initialization the programming/erase program in ram is executed, and the flash memory is initialized (to h'ff). erasing can be performed in block units, but not in byte units. 4. writing new application program next, the new application program in the host is written into the erased flash memory blocks. do not write to unerased blocks. 2. programming/erase control program transfer when user program mode is entered, user software recognizes this fact, executes the transfer program in the flash memory, and transfers the programming/erase control program to ram. fwe assessment program transfer program programming/erase control program programming/erase control program 528 18.4.3 flash memory emulation in ram in the h8/3024f-ztat version, flash memory programming can be emulated in real time by overlapping the flash memory with part of ram ( overlap ram ). when the emulation block set in ramcr is accessed while the emulation function is being executed, data written in the overlap ram is read. emulation should be performed in user mode or user program mode. application program execution state flash memory emulation block ram sci overlap ram (emulation is performed on data written in ram) figure 18.4 reading overlap ram data in user mode/user program mode when overlap ram data is confirmed, clear the rams bit to cancel ram overlap, and actually perform writes to the flash memory in user program mode. when the programming control program is transferred to ram in on-board programming mode, ensure that the transfer destination and the overlap ram do not overlap, as this will cause data in the overlap ram to be rewritten. 529 application program flash memory ram sci programming control program execution state overlap ram (program data) program data figure 18.5 writing overlap ram data in user program mode 18.4.4 block configuration the flash memory in the h8/3024f-ztat version is divided into three 32-kbyte blocks, one 28- kbyte block, and four 1-kbyte blocks. erasing can be carried out in block units. address h'1ffff address h'00000 32 kbytes 28 kbytes 32 kbytes 32 kbytes 128 kbytes 1 kbyte 4 530 18.5 on-board programming mode when pins are set to on-board programming mode and a reset-start is executed, the chip enters the on-board programming state in which on-chip flash memory programming, erasing, and verifying can be carried out. there are two operating modes in this mode boot mode and user program mode. the pin settings for entering each mode are shown in table 18.6. for a diagram of the transitions to the various flash memory modes, see figure 18.3. boot mode and user program mode cannot be used in the h8/3024f-ztat version s mode 6 (on- chip rom enabled). table 18.6 on-board programming mode settings mode fwe md 2 md 1 md 0 boot mode mode 5 1* 1 0* 2 01 mode 7 0* 2 11 user program mode mode 5 1 0 1 mode 7 1 1 1 notes: *1 for the high level input timing, see items 6 and 7 of notes on use of boot mode. *2 in boot mode, the md 2 setting should be the inverse of the input. in the boot mode in the h8/3024f-ztat version, the levels of the mode pins (md 2 to md 0 ) are reflected in mode select bits 2 to 0 (mds2 to mds0) in the mode control register (mdcr). 531 18.5.1 boot mode when boot mode is used, a flash memory programming control program must be prepared beforehand in the host, and sci channel 1, which is to be used, must be set to asynchronous mode. when a reset-start is executed after setting the h8/3024f-ztat version pins to boot mode, the boot program already incorporated in the mcu is activated, and the programming control program prepared beforehand in the host is transmitted sequentially to the h8/3024f-ztat version, using the sci. in the h8/3024f-ztat version, the programming control program received via the sci is written into the programming control program area in on-chip ram. after the transfer is completed, an identification check (id code check) is carried out to see if the programming control program is compatible with the h8/3024f-ztat version. if the id code matches, control branches to the start address (h'fff520) of the programming control program area and the programming control program execution state is entered (flash memory programming/erasing can be performed). figure 18.6 shows a system configuration diagram when using boot mode, and figure 18.7 shows the boot program mode execution procedure. rxd1 txd1 sci1 h8/3024f-ztat version flash memory reception of programming data transmission of verify data host on-chip ram figure 18.6 system configuration when using boot mode 532 n = n? yes no set pins to boot program mode and execute reset-start n = 1 n + 1 n transmit h'ff as error notification host transfers data (h'00) continuously at prescribed bit rate h8/3024f-ztat version measures low period of h'00 data transmitted by host after bit rate adjustment, h8/3024f-ztat version transmits one h'00 data byte to host to indicate end of adjustment host confirms normal reception of bit rate adjustment end indication (h'00), and transmits one h'55 data byte after receiving h'55, h8/3024f-ztat version transmits one h'aa byte to host host transmits number of programming control program bytes (n), upper byte followed by lower byte h8/3024f-ztat version transmits received number of bytes to host as verify data (echo-back) host transmits programming control program sequentially in byte units h8/3024f-ztat version transmits received programming control program to host as verify data (echo-back) transfer received programming control program to on-chip ram end of transmission check flash memory data, and if data has already been written, erase all blocks execute programming control program transferred to on-chip ram start h8/3024f-ztat version calculates bit rate and sets value in bit rate register confirm that all flash memory data has been erased check id code at beginning of user program transfer area transmit one h'aa byte to host (mismatch) (match) note: if a memory cell does not operate normally and cannot be erased, one h'ff byte is transmitted as an erase error indication, and the erase operation and subsequent operations are halted. figure 18.7 boot mode execution procedure 533 automatic sci bit rate adjustment: start bit stop bit d0 d1 d2 d3 d4 d5 d6 d7 low period (9 bits) measured (h'00 data) high period (1 or more bits) when boot mode is initiated, the h8/3024f-ztat version measures the low period of the asynchronous sci communication data (h'00) transmitted continuously from the host. the sci transmit/receive format should be set as 8-bit data, 1 stop bit, no parity. the h8/3024f-ztat version calculates the bit rate of the transmission from the host from the measured low period, and transmits one h'00 byte to the host to indicate the end of bit rate adjustment. the host should confirm that this adjustment end indication (h'00) has been received normally, and transmit one h'55 byte to the h8/3024f-ztat version. if reception cannot be performed normally, initiate boot mode again (reset), and repeat the above operations. depending on the host s transmission bit rate and the h8/3024f-ztat version s system clock frequency, there will be a discrepancy between the bit rates of the host and the h8/3024f-ztat version. to ensure correct sci operation, the host s transfer bit rate should be set to 4800, 9600, or 19,200 bps*. table 18.7 shows typical host transfer bit rates and system clock frequencies for which automatic adjustment of the h8/3024f-ztat version bit rate is possible. the boot program should be executed within this system clock range. table 18.7 system clock frequencies for which automatic adjustment of h8/3024f-ztat version bit rate is possible host bit rate (bps) system clock frequency for which automatic adjustment of h8/3024f-ztat version bit rate is possible (mhz) 19,200 16 to 25 9,600 8 to 25 4,800 4 to 25 note: * only use a setting of 4800, 9600, or 19200 for the host s bit rate. no other settings can be used. although the h8/3024f-ztat version may also perform automatic bit rate adjustment with bit rate and system clock combinations other than those shown in table 18.7, a degree of error will arise between the bit rates of the host and the mcu, and subsequent transfer will not be performed normally. therefore, only a combination of bit rate and system clock frequency within one of the ranges shown in table 18.7 can be used for boot mode execution. 534 on-chip ram area divisions in boot mode: in boot mode, the ram area is divided into an area used by the boot program and an area to which the user program is transferred via the sci, as shown in figure 18.8. the boot program area becomes available when a transition is made to the execution state for the user program transferred to ram. h'ffef20 h'fff51f user program transfer area boot program area h'ffff1f note: the boot program area cannot be used until a transition is made to the execution state for the user program transferred to ram. note also that the boot program remains in this area in ram even after control branches to the user program. figure 18.8 ram areas in boot mode notes on use of boot mode: 1. when the h8/3024f-ztat version chip comes out of reset in boot mode, it measures the low period of the input at the sci s rxd 1 pin. the reset should end with rxd 1 high. after the reset ends, it takes about 100 states for the chip to get ready to measure the low period of the rxd 1 input. 2. in boot mode, if any data has been programmed into the flash memory (if all data is not 1), all flash memory blocks are erased. boot mode is for use when user program mode is unavailable, such as the first time on-board programming is performed, or if the program activated in user program mode is accidentally erased. 3. interrupts cannot be used while the flash memory is being programmed or erased. 4. the rxd 1 and txd 1 lines should be pulled up on the board. 5. before branching to the user program the h8/3024f-ztat version terminates transmit and receive operations by the on-chip sci (channel 1) (by clearing the re and te bits to 0 in the serial control register (scr)), but the adjusted bit rate value remains set in the bit rate register (brr). the transmit data output pin, txd 1 , goes to the high-level output state (p9 1 ddr = 1 in p9ddr, p9 1 dr = 1 in p9dr). 535 the contents of the cpu s internal general registers are undefined at this time, so these registers must be initialized immediately after branching to the user program. in particular, since the stack pointer (sp) is used implicitly in subroutine calls, etc., a stack area must be specified for use by the user program. the initial values of other on-chip registers are not changed. 6. boot mode can be entered by setting pins md 0 to md 2 and fwe in accordance with the mode setting conditions shown in table 18.6, and then executing a reset-start. a. when switching from boot mode to normal mode, the boot mode state within the chip must first be cleared by reset input via the res res res s internal state will not be cleared, and the on-chip boot program will be restarted regardless of the mode pin states. c. the fwe pin must not be driven low while the boot program is running or flash memory is being programmed or erased.* 3 7. if the mode pin input levels are changed (for example, from low to high) during a reset, the state of ports with multiplexed address functions and bus control output signals ( csn as rd lwr hwr s operating mode. therefore, care must be taken to make pin settings to prevent these pins from being used directly as output signal pins during a reset, or to prevent collision with signals outside the mcu. h8/3024f-ztat version md2 md1 md0 fwe res csn system control unit external memory, etc. notes: *1 mode pin and fwe pin input must satisfy the mode programming setup time (t mds ) with respect to the reset release timing. 536 *2 see section 4.2.2, reset sequence, and section 18.11, flash memory programming and erasing precautions. the h8/3024f-ztat version requires a minimum of 20 system clock cycles for a reset during operation. *3 for further information on fwe application and disconnection, see section 18.11, flash memory programming and erasing precautions. 18.5.2 user program mode when set to user program mode, the h8/3024f-ztat version can program and erase its flash memory by executing a user program/erase control program. therefore, on-board reprogramming of the on-chip flash memory can be carried out by providing on-board means of fwe control and supply of programming data, and storing a program/erase control program in part of the program area as necessary. to select user program mode, select a mode that enables the on-chip rom (mode 5 or 7), and apply a high level to the fwe pin. in this mode, on-chip supporting modules other than flash memory operate as they normally would in modes 5 and 7. flash memory programming/erasing should not be carried out in mode 6. when mode 6 is set, the fwe pin must be driven low. the flash memory itself cannot be read while being programmed or erased, so the program that performs programming should be placed in external memory or transferred to ram and executed there. figure 18.9 shows the execution procedure when user program mode is entered during program execution in ram. it is also possible to start from user program mode in a reset-start. 537 md 2 e md 0 = 101 or 111 reset-start transfer programming/erase control program to ram branch to programming/erase control program in ram area fwe = high (user program mode) execute programming/erase control program in ram (flash memory rewriting) clear swe bit, then release fwe (user program mode clearing) branch to application program in flash memory write fwe assessment program and transfer program (and programming/erase control program if necessary) beforehand notes: 1. do not apply a constant high level to the fwe pin. a high level should be applied to the fwe pin only when programming or erasing flash memory (including execution of flash memory emulation by ram). also, while a high level is applied to the fwe pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. 2. for further information on fwe application and disconnection, see section 18.11, flash memory programming and erasing precautions. 3. in order to execute a normal read of flash memory in user program mode, the programming/erase program must not be executing. it is thus necessary to ensure that bits 6 to 0 in flmcr1 are cleared to 0. figure 18.9 example of user program mode execution procedure 538 18.6 flash memory programming/erasing a software method, using the cpu, is employed to program and erase flash memory in the on- board programming modes. there are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. transitions to these modes for addresses h'000000 to h'01ffff are made by setting the psu, esu, p, e, pv, and ev bits in flmcr1. the flash memory cannot be read while being programmed or erased. therefore, the program (user program) that controls flash memory programming/erasing should be located and executed in on-chip ram or external memory. see section 18.11, flash memory programming and erasing precautions, for points to be noted when programming or erasing the flash memory. in the following operation descriptions, wait times after setting or clearing individual bits in flmcr1 are given as parameters; for details of the wait times, see section 21.2.6, flash memory characteristics. notes: 1. operation is not guaranteed if setting/resetting of the swe, esu, psu, ev, pv, e, and p bits in flmcr1 is executed by a program in flash memory. 2. when programming or erasing, set fwe to 1 (programming/erasing will not be executed if fwe = 0). 3. programming must be executed in the erased state. do not perform additional programming on addresses that have already been programmed. 539 normal mode on-board programming mode software programming disable state erase setup state erase mode program mode erase-verify mode program setup state program-verify mode swe = 1 swe = 0 fwe = 1 fwe = 0 e = 1 e = 0 p = 1 p = 0 software programming enable state *1 *2 *3 *4 notes: in order to perform a normal read of flash memory, swe must be cleared to 0. also note that verify-reads can be performed during the programming/erasing process. *1 : normal mode : on-board programming mode *2 do not make a state transition by setting or clearing multiple bits simultaneously. *3 after a transition from erase mode to the erase setup state, do not enter erase mode without passing through the software programming enable state. *4 after a transition from program mode to the program setup state, do not enter program mode without passing through the software programming enable state. esu = 0 esu = 1 psu = 1 psu = 0 pv = 1 pv = 0 ev = 0 ev = 1 figure 18.10 flmcr1 bit settings and state transitions 540 18.6.1 program mode when writing data or programs to flash memory, the program/program-verify flowchart shown in figure 18.11 should be followed. performing programming operations according to this flowchart will enable data or programs to be written to flash memory without subjecting the device to voltage stress or sacrificing program data reliability. programming should be carried out 128 bytes at a time. the wait times after bits are set or cleared in the flash memory control register 1 (flmcr1) and the maximum number of programming operations (n) are shown in table 21.19 in section 21.2.6, flash memory characteristics. following the elapse of (t sswe ) ? or more after the swe bit is set to 1 in flmcr1, 128-byte data is written consecutively to the write addresses. the lower 8 bits of the first address written to must be h'00 and h'80, 128 consecutive byte data transfers are performed. the program address and program data are latched in the flash memory. a 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, h'ff data must be written to the extra addresses. next, the watchdog timer (wdt) is set to prevent overprogramming due to program runaway, etc. set a value greater than (t spsu + t sp + t cp + t cpsu ) ? as the wdt overflow period. preparation for entering program mode (program setup) is performed next by setting the psu bit in flmcr1. the operating mode is then switched to program mode by setting the p bit in flmcr1 after the elapse of at least (t spsu ) ?. the time during which the p bit is set is the flash memory programming time. make a program setting so that the time for one programming operation is within the range of (t sp ) ?. the wait time after p bit setting must be changed according to the degree of progress through the programming operation. for details see notes on program/program-verify procedure below. 541 18.6.2 program-verify mode in program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. after the elapse of the given programming time, clear the p bit in flmcr1, then wait for at least (t cp ) ? before clearing the psu bit to exit program mode. after exiting program mode, the watchdog timer setting is also cleared. the operating mode is then switched to program-verify mode by setting the pv bit in flmcr1. before reading in program-verify mode, a dummy write of h'ff data should be made to the addresses to be read. the dummy write should be executed after the elapse of (t spv ) ? or more. when the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. wait at least (t spvr ) ? after the dummy write before performing this read operation. next, the originally written data is compared with the verify data, and reprogram data is computed (see figure 18.11) and transferred to ram. after verification of 128 bytes of data has been completed, exit program-verify mode, wait for at least (t cpv ) ?, then clear the swe bit in flmcr1. if reprogramming is necessary, set program mode again, and repeat the program/program-verify sequence as before. the maximum number of repetitions of the program/program-verify sequence is indicated by the maximum programming count (n). leave a wait time of at least (t cswe ) ? after clearing swe. notes on program/program-verify procedure 1. the program/program-verify procedure for the h8/3024f-ztat version uses a 128-byte-unit programming algorithm. in order to perform 128-byte-unit programming, the lower 8 bits of the write start address must be h'00 or h'80. 2. when performing continuous writing of 128-byte data to flash memory, byte-unit transfer should be used. 128-byte data transfer is necessary even when writing fewer than 128 bytes of data. write h'ff data to the extra addresses. 3. verify data is read in word units. 4. the write pulse is applied and a flash memory write executed while the p bit in flmcr1 is set. in the h8/3024f-ztat version, write pulses should be applied as follows in the program/program-verify procedure to prevent voltage stress on the device and loss of write data reliability. a. after write pulse application, perform a verify-read in program-verify mode and apply a write pulse again for any bits read as 1 (reprogramming processing). when all the 0-write bits in the 128-byte write data are read as 0 in the verify-read operation, the program/program-verify procedure is completed. in the h8/3024f-ztat version, the number of loops in reprogramming processing is guaranteed not to exceed the maximum value of the maximum programming count (n). 542 b. after write pulse application, a verify-read is performed in program-verify mode, and programming is judged to have been completed for bits read as 0. the following processing is necessary for programmed bits. when programming is completed at an early stage in the program/program-verify procedure: if programming is completed in the 1st to 6th reprogramming processing loop, additional programming should be performed on the relevant bits. additional programming should only be performed on bits which first return 0 in a verify-read in certain reprogramming processing. when programming is completed at a late stage in the program/program-verify procedure: if programming is completed in the 7th or later reprogramming processing loop, additional programming is not necessary for the relevant bits. c. if programming of other bits is incomplete in the 128 bytes, reprogramming processing should be executed. if a bit for which programming has been judged to be completed is read as 1 in a subsequent verify-read, a write pulse should again be applied to that bit. 5. the period for which the p bit in flmcr1 is set (the write pulse width) should be changed according to the degree of progress through the program/program-verify procedure. for detailed wait time specifications, see section 21.2.6, flash memory characteristics. item symbol item symbol wait time after t sp when reprogramming loop count (n) is 1 to 6 t sp 30 p bit setting when reprogramming loop count (n) is 7 or more t sp 200 in case of additional programming processing* t sp 10 note: * additional programming processing is necessary only when the reprogramming loop count (n) is 1 to 6. 6. the program/program-verify flowchart for the h8/3024f-ztat version is shown in figure 18.11. to cover the points noted above, bits on which reprogramming processing is to be executed, and bits on which additional programming is to be executed, must be determined as shown below. since reprogram data and additional-programming data vary according to the progress of the programming procedure, it is recommended that the following data storage areas (128 bytes each) be provided in ram. 543 reprogram data computation table (d) result of verify-read after write pulse application (v) (x) result of operation comments 0 0 1 programming completed: reprogramming processing not to be executed 0 1 0 programming incomplete: reprogramming processing to be executed 10 1 ? 1 1 1 still in erased state: no action legend (d): source data of bits on which programming is executed (x): source data of bits on which reprogramming is executed additional-programming data computation table (x') result of verify-read after write pulse application (v) (y) result of operation comments 0 0 0 programming by write pulse application judged to be completed: additional programming processing to be executed 0 1 1 programming by write pulse application incomplete: additional programming processing not to be executed 1 0 1 programming already completed: additional programming processing not to be executed 1 1 1 still in erased state: no action legend (y): data of bits on which additional programming is executed (x'): data of bits on which reprogramming is executed in a certain reprogramming loop 7. it is necessary to execute additional programming processing during the course of the h8/3024f-ztat version program/program-verify procedure. however, once 128-byte-unit programming is finished, additional programming should not be carried out on the same address area. when executing reprogramming, an erase must be executed first. note that normal operation of reads, etc., is not guaranteed if additional programming is performed on addresses for which a program/program-verify operation has finished. 544 start end of programming set swe bit in flmcr1 start of programming write pulse application subroutine wait (t sswe ) s sub-routine write pulse end sub set psu in flmcr1 wdt enable disable wdt number of writes n 1 2 3 4 5 6 7 8 9 10 11 12 13 998 999 1000 note *6: write pulse width write time (tsp) sec 30 30 30 30 30 30 200 200 200 200 200 200 200 200 200 200 wait (t spsu ) s set p bit in flmcr1 wait (t sp ) s clear p bit in flmcr1 wait (t cp ) s clear psu bit in flmcr1 wait (t cpsu ) s n= 1 m= 0 ng ng ng ng ok ok ok wait (t spv ) s wait (t spvr ) s * 2 * 7 * 7 * 4 * 7 * 7 start of programming programming halted * 5 * 7 * 7 * 7 * 1 wait (t cpv ) s write pulse sub-routine-call set pv bit in flmcr1 h'ff dummy write to verify address read verify data write data = verify data? * 4 * 3 * 7 * 7 * 7 * 1 transfer reprogram data to reprogram data area reprogram data computation * 4 transfer additional-programming data to additional-programming data area additional-programming data computation clear pv bit in flmcr1 clear swe bit in flmcr1 m = 1 reprogram see note *6 for pulse width m= 0 ? increment address programming failure ok clear swe bit in flmcr1 wait (t cswe ) s ng ok 6 n? ng ok 6 n ? wait (t cswe ) s n n? n n + 1 original data (d) verify data (v) reprogram data (x) comments programming completed still in erased state; no action programming incomplete; reprogram note: use a 10 s write pulse for additional programming. write 128-byte data in ram reprogram data area consecutively to flash memory ram program data storage area (128 bytes) reprogram data storage area (128 bytes) additional-programming data storage area (128 bytes) store 128-byte program data in program data area and reprogram data area write pulse (additional programming) sub-routine-call 128-byte data verification completed? successively write 128-byte data from additional- programming data area in ram to flash memory reprogram data computation table reprogram data (x') verify data (v) additional- programming data (y) 1 1 1 1 0 1 0 0 0 0 1 1 comments additional programming to be executed additional programming not to be executed additional programming not to be executed additional programming not to be executed 0 1 1 1 0 1 0 1 0 0 1 1 additional-programming data computation table perform programming in the erased state. do not perform additional programming on previously programmed addresses. notes: *1 data transfer is performed by byte transfer. the lower 8 bits of the first address written to must be h'00 or h'80. a 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, h'ff data must be written to the extra addresses. *2 verify data is read in 16-bit (longword) units. *3 reprogram data is determined by the operation shown in the table below (comparison between the data stored in the program dat a area and the verify data). bits for which the reprogram data is 0 are programmed in the next reprogramming loop. therefore, even bits for which programming has bee n completed will be subjected to programming once again if the result of the subsequent verify operation is ng. *4 a 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additio nal data must be provided in ram. the contents of the reprogram data area and additional data area are modified as programming proceeds. *5 a write pulse of 30 s or 200 s is applied according to the progress of the programming operation. see note 6 for details of the pulse widths. when writing o f additional-programming data is executed, a 10 s write pulse should be applied. reprogram data x' means reprogram data when the write pulse is applied. *7 the wait times and value of n are shown in section 21.2.6, flash memory characteristics. figure 18.11 program/program-verify flowchart (128-byte programming) 545 18.6.3 erase mode when erasing flash memory, the single-block erase flowchart shown in figure 18.12 should be followed. the wait times after bits are set or cleared in the flash memory control register 1 (flmcr1) and the maximum number of erase operations (n) are shown in table 21.19 in section 21.2.6, flash memory characteristics. to erase flash memory contents, make a 1-bit setting for the flash memory area to be erased in erase block register (ebr) at least (t sswe ) ? after setting the swe bit to 1 in flmcr1. next, the watchdog timer (wdt) is set to prevent overerasing due to program runaway, etc. set a value greater than (t se ) ms + (t sesu + t ce + t cesu ) ? as the wdt overflow period. preparation for entering erase mode (erase setup) is performed next by setting the esu bit in flmcr1. the operating mode is then switched to erase mode by setting the e bit in flmcr1 after the elapse of at least (t sesu ) ?. the time during which the e bit is set is the flash memory erase time. ensure that the erase time does not exceed (t se ) ms. note: with flash memory erasing, preprogramming (setting all memory data in the memory to be erased to all 0) is not necessary before starting the erase procedure. 18.6.4 erase-verify mode in erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased. after the elapse of the fixed erase time, clear the e bit in flmcr1, then wait for at least (t ce ) ? before clearing the esu bit to exit erase mode. after exiting erase mode, the watchdog timer setting is also cleared. the operating mode is then switched to erase-verify mode by setting the ev bit in flmcr1. before reading in erase-verify mode, a dummy write of h'ff data should be made to the addresses to be read. the dummy write should be executed after the elapse of (t sev ) ? or more. when the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. wait at least (t sevr ) ? after the dummy write before performing this read operation. if the read data has been erased (all 1), a dummy write is performed to the next address, and erase-verify is performed. if the read data is unerased, set erase mode again, and repeat the erase/erase-verify sequence as before. the maximum number of repetitions of the erase/erase-verify sequence is indicated by the maximum erase count (n). when verification is completed, exit erase-verify mode, and wait for at least (t cev ) ?. if erasure has been completed on all the erase blocks, clear the swe bit in flmcr1, and leave a wait time of at least (t cswe ) ?. if erasing multiple blocks, set a single bit in ebr for the next block to be erased, and repeat the erase/erase-verify sequence as before. 546 end of erasing start set swe bit in flmcr1 set esu bit in flmcr1 set e bit in flmcr1 wait (t sswe ) s wait (t sesu ) s n = 1 set ebr enable wdt * 3, * 4 * 5 * 5 * 5 * 5 * 5 * 5 * 5 * 5 * 5 * 5 * 5 * 5 wait (t se ) ms wait (t ce ) s wait (t cesu ) s wait (t sev ) s set block start address as verify address wait (t sevr ) s * 2 wait (t cev ) s start of erase clear e bit in flmcr1 clear esu bit in flmcr1 set ev bit in flmcr1 h'ff dummy write to verify address read verify data clear ev bit in flmcr1 wait (t cev ) s clear ev bit in flmcr1 clear swe bit in flmcr1 disable wdt erase halted * 1 verify data = all 1s? last address of block? erase failure clear swe bit in flmcr1 n n? no no no yes yes yes n n + 1 increment address wait (t cswe ) s wait (t cswe ) s notes: *1 prewriting (setting erase block data to all 0s) is not necessary. *2 verify data is read in 16-bit (word) units. *3 make only a single-bit specification in the erase block register (ebr). two or more bits must not be set simultaneously. *4 erasing is performed in block units. to erase multiple blocks, each block must be erased in turn. *5 the wait times and the value of n are shown in section 21.2.6, flash memory characteristics. perform erasing in block units. figure 18.12 erase/erase-verify flowchart (single-block erasing) 547 18.7 flash memory protection there are three kinds of flash memory program/erase protection: hardware, software, and error protection. 18.7.1 hardware protection hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. in this state, the settings in flash memory control register 1 (flmcr1) and erase block register (ebr) are reset. in the error protection state, the flmcr1 and ebr settings are retained; the p bit and e bit can be set, but a transition is not made to program mode or erase mode. (see table 18.8.) table 18.8 hardware protection function item description program erase verify fwe pin protection ? when a low level is input to the fwe pin, flmcr1 and ebr are initialized, and the program/erase-protected state is entered. not possible* 1 not possible* 3 not possible reset/ standby protection ? in a reset (including a wdt overflow reset) and in standby mode, flmcr1, flmcr2, and ebr are initialized, and the program/erase- protected state is entered. ? in a reset via the res pin, the reset state is not entered unless the res pin is held low until oscillation stabilizes after powering on. in the case of a reset during operation, hold the res pin low for the res pulse width specified in the ac characteristics section.* 4 not possible not possible* 3 not possible error protection ? when a microcomputer operation error (error generation (fler = 1)) was detected while flash memory was being programmed/erased, error protection is enabled. at this time, the flmcr1 and ebr settings are held, but programming/erasing is aborted at the time the error was generated. error protection is released only by a reset via the res pin or a wdt reset, or in the hardware standby mode. not possible not possible* 3 possible* 2 notes: *1 the ram area that overlapped flash memory is deleted. *2 it is possible to perform a program-verify operation on the 128 bytes being programmed, or an erase-verify operation on the block being erased. 548 *3 all blocks are unerasable and block-by-block specification is not possible. *4 see section 4.2.2, reset sequence, and section 18.11, flash memory programming and erasing precautions. the h8/3024f-ztat version requires a minimum of 20 system clock cycles for a reset during operation. 18.7.2 software protection software protection can be implemented by setting the erase block register (ebr) and the rams bit in the ram control register (ramcr). with software protection, setting the p or e bit in the flash memory control register 1 (flmcr1) does not cause a transition to program mode or erase mode. (see table 18.9.) table 18.9 software protection functions item description program erase verify block protection ? erase protection can be set for individual blocks by settings in erase block register (ebr)* 2 . however, programming protection is disabled. ? setting ebr to h'00 places all blocks in the erase-protected state. ? not possible possible emulation protection ? setting the rams bit 1 in ramcr places all blocks in the program/erase-protected state. not possible* 1 not possible* 3 possible notes: *1 the ram area overlapping flash memory can be written to. *2 when not erasing, set ebr to h'00. *3 all blocks are unerasable and block-by-block specification is not possible. 18.7.3 error protection in error protection, an error is detected when mcu runaway occurs during flash memory programming/erasing* 1 , or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. if the mcu malfunctions during flash memory programming/erasing, the fler bit is set to 1 in the flash memory status register (flmsr2) and the error protection state is entered. flmcr1, flmcr2, and ebr settings* 3 are retained, but program mode or erase mode is aborted at the point at which the error occurred. program mode or erase mode cannot be re-entered by re-setting the p or e bit in flmcr. however, pv and ev bit setting is enabled, and a transition can be made to verify mode* 2 . 549 fler bit setting conditions are as follows: 1. when flash memory is read during programming/erasing (including a vector read or instruction fetch) 2. immediately after the start of exception handling during programming/erasing (excluding reset, illegal instruction, trap instruction, and division-by-zero exception handling) 3. when a sleep instruction (including software standby) is executed during programming/erasing 4. when the bus is released during programming/erasing error protection is released only by a res 550 rd vf pr er fler = 0 error occurrence res = 0 or stby = 0 res = 0 or stby = 0 rd vf pr er init fler = 0 program mode erase mode reset or standby (hardware protection) rd vf pr er fler = 1 rd vf pr er init fler = 1 error protection mode error protection mode (software standby) software standby mode flmcr1, ebr initialization state flmcr1, flmcr2, ebr1, ebr2 initialization state software standby mode release rd: memory read possible vf: verify-read possible pr: programming possible er: erasing possible rd : memory read not possible vf : verify-read not possible pr : programming not possible er : erasing not possible init: register initialization state res = 0 or stby = 0 error occurrence (software standby) figure 18.13 flash memory state transitions (when high level is applied to fwe pin in mode 5 or 7 (on-chip rom enabled)) the error protection function is invalid for abnormal operations other than the fler bit setting conditions. also, if a certain time has elapsed before this protection state is entered, damage may already have been caused to the flash memory. consequently, this function cannot provide complete protection against damage to flash memory. to prevent such abnormal operations, therefore, it is necessary to ensure correct operation in accordance with the program/erase algorithm, with the flash write enable (fwe) voltage applied, and to conduct constant monitoring for mcu errors, internally and externally, using the watchdog timer or other means. there may also be cases where the flash memory is in an erroneous programming or erroneous erasing state at the point of transition to this protection mode, or where programming or erasing is not properly carried out because of an abort. in cases such as these, a forced recovery (program rewrite) must be executed using boot mode. however, it may also happen that boot mode cannot be normally initiated because of overprogramming or overerasing. 551 18.8 flash memory emulation in ram as flash memory programming and erasing takes time, it may be difficult to carry out tuning by writing parameters and other data in real time. in this case, real-time programming of flash memory can be emulated by overlapping part of ram (h'fff000 h'fff3ff) onto a small block area in flash memory. this ram area change is executed by means of bits 3 to 1 in the ram control register (ramcr). after the ram area change, access is possible both from the area overlapped onto flash memory and from the original area (h'fff000 h'fff3ff). for details of ramcr and the ram area setting method, see section 18.3.4, ram control register (ramcr). example of emulation of real-time flash memory programming: in the following example, ram area h'fff000 h'fff3ff is overlapped onto flash memory area eb2 (h'000800 h'000bff). h'000000 h'000800 h'ffef20 h'fff000 h'ffefff h'fff3ff h'fff400 h'ffff1f h'000bff h'000fff eb2 area flash memory space on-chip ram area block area * (mapping ram area) overlapping ram (actual ram area) procedure: 1. part of ram (h'fff000 e h'fff3ff) is overlapped onto the area (eb2) requiring real-time programming. (ramcr bits 3 e 1 are set to 1, 1, 0, and the flash memory area to be overlapped (eb2) is selected.) 2. real-time programming is performed using the overlapping ram. 3. the programmed data is checked, then ram overlapping is cleared. (rams bit is cleared.) 4. the data written in ram area h'fff000 e h'fff3ff is written to flash memory space. note: * when part of ram (h'fff000 e h'fff3ff) is overlapped onto a flash memory small block area, the flash memory in the overlapped area cannot be accessed. it can be accessed when the overlapping is cleared. figure 18.14 example of ram overlap operation 552 notes on use of emulation in ram: 1. flash write enable (fwe) application and releasing as in on-board program mode, care is required when applying and releasing fwe to prevent erroneous programming or erasing. to prevent erroneous programming and erasing due to program runaway during fwe application, in particular, the watchdog timer should be set when the psu, p, esu, or e bit is set to 1 in flmcr1, even while the emulation function is being used. for details, see section 18.11, flash memory programming and erasing precautions. 2. nmi input disabling conditions when the emulation function is used, nmi input is disabled when the p bit or e bit is set to 1 in flmcr1, in the same way as with normal programming and erasing. the p and e bits are cleared by a reset (including a watchdog timer reset), in standby mode, when a high level is not being input to the fwe pin, or when the swe bit in flmcr1 is 0 while a high level is being input to the fwe pin. 3. when the rams bit is set to 1, program/erase protection is enabled for all blocks regardless of the value of ram2 to ram0 (emulation protection). in this state, setting the p or e bit in flmcr1 will not cause a transition to program mode or erase mode. when actually programming or erasing a flash memory area, the rams bit should be cleared to 0. 4. a ram area cannot be erased by execution of software in accordance with the erase algorithm while flash memory emulation in ram is being used. 5. block area eb0 contains the vector table. when performing ram emulation, the vector table is needed in the overlap ram. 18.9 nmi input disabling conditions all interrupts, including nmi input, should be disabled while flash memory is being programmed or erased (while the p bit or e bit is set in flmcr1), and while the boot program is executing in boot mode* 1 , to give priority to the program or erase operation. there are three reasons for this: 1. nmi input during programming or erasing might cause a violation of the programming or erasing algorithm, with the result that normal operation could not be assured. 2. in the nmi exception handling sequence during programming or erasing, the vector would not be read correctly* 2 , possibly resulting in mcu runaway. 3. if nmi input occurred during boot program execution, it would not be possible to execute the normal boot mode sequence. for these reasons, in on-board programming mode alone there are conditions for disabling nmi input, as an exception to the general rule. however, this provision does not guarantee normal erasing and programming or mcu operation. all interrupt requests (exception handling and bus release), including nmi, must therefore be restricted inside and outside the mcu during fwe 553 application. nmi input is also disabled in the error protection state and while the p or e bit remains set in flmcr1 during flash memory emulation in ram. notes: *1 this is the interval until a branch is made to the boot program area in the on-chip ram (this branch takes place immediately after transfer of the user program is completed). consequently, after the branch to the ram area, nmi input is enabled except during programming and erasing. interrupt requests must therefore be disabled inside and outside the mcu until the user program has completed initial programming (including the vector table and the nmi interrupt handling routine). *2 the vector may not be read correctly in this case for the following two reasons: if flash memory is read while being programmed or erased (while the p bit or e bit is set in flmcr1), correct read data will not be obtained (undetermined values will be returned). if the entry in the interrupt vector table has not been programmed yet, interrupt exception handling will not be executed correctly. 18.10 flash memory prom mode the h8/3024f-ztat version has a prom mode as well as the on-board programming modes for programming and erasing flash memory. in prom mode, the on-chip rom can be freely programmed using a general-purpose prom writer that supports the hitachi microcomputer device type with 128-kbyte on-chip flash memory. 18.10.1 socket adapters and memory map in prom mode using a prom writer, memory reading (verification) and writing and flash memory initialization (total erasure) can be performed. for these operations, a special socket adapter is mounted in the prom writer. the socket adapter product codes are given in table 18.10. in the h8/3024f-ztat version prom mode, only the socket adapters shown in this table should be used. table 18.10 h8/3024f-ztat version socket adapter product codes product code package socket adapter product code manufacturer HD64F3024f 100-pin qfp (fp-100b) tbd minato electronics HD64F3024te 100-pin tqfp (tfp-100b) tbd inc. HD64F3024fp 100-pin qfp (fp-100a) tbd HD64F3024f 100-pin qfp (fp-100b) tbd data i/o japan co. HD64F3024te 100-pin tqfp (tfp-100b) tbd HD64F3024fp 100-pin qfp (fp-100a) tbd 554 figure 18.15 shows the memory map in prom mode. h8/3024f-ztat version h'000000 h'01ffff h'00000 h'1ffff mcu mode prom mode on-chip rom figure 18.15 memory map in prom mode 18.10.2 notes on use of prom mode 1. a write to a 128-byte programming unit in prom mode should be performed once only. erasing must be carried out before reprogramming an address that has already been programmed. 2. when using a prom writer to reprogram a device on which on-board programming/erasing has been performed, it is recommended that erasing be carried out before executing programming. 3. the memory is initially in the erased state when the device is shipped by hitachi. for samples for which the erasure history is unknown, it is recommended that erasing be executed to check and correct the initialization (erase) level. 4. the h8/3024f-ztat version does not support a product identification mode as used with general-purpose eproms, and therefore the device name cannot be set automatically in the prom writer. 5. refer to the instruction manual provided with the socket adapter, or other relevant documentation, for information on prom writers and associated program versions that are compatible with the prom mode of the h8/3024f-ztat version. 555 18.11 flash memory programming and erasing precautions precautions concerning the use of on-board programming mode, the ram emulation function, and prom mode are summarized below. 1. use the specified voltages and timing for programming and erasing. applied voltages in excess of the rating can permanently damage the device. use a prom programmer that supports the hitachi microcomputer device type with 128-kbyte on-chip flash memory. 2. powering on and off (see figures 18.16 to 18.18) do not apply a high level to the fwe pin until v cc has stabilized. also, drive the fwe pin low before turning off v cc . when applying or disconnecting v cc power, fix the fwe pin low and place the flash memory in the hardware protection state. the power-on and power-off timing requirements should also be satisfied in the event of a power failure and subsequent recovery. failure to do so may result in overprogramming or overerasing due to mcu runaway, and loss of normal memory cell operation. 3. fwe application/disconnection fwe application should be carried out when mcu operation is in a stable condition. if mcu operation is not stable, fix the fwe pin low and set the protection state. the following points must be observed concerning fwe application and disconnection to prevent unintentional programming or erasing of flash memory: apply fwe when the v cc voltage has stabilized within its rated voltage range. if fwe is applied when the mcu s v cc power supply is not within its rated voltage range, mcu operation will be unstable and flash memory may be erroneously programmed or erased. apply fwe when oscillation has stabilized (after the elapse of the oscillation settling time). when v cc power is turned on, hold the res in boot mode, apply and disconnect fwe during a reset. in a transition to boot mode, fwe = 1 input and md 2 md 0 setting should be performed while the res md 0 pin input must satisfy the mode programming setup time (t mds ) with respect to the reset release timing. when making a transition from boot mode to another mode, also, a mode programming setup time is necessary with respect to the reset release timing. in a reset during operation, the res 556 in user program mode, fwe can be switched between high and low level regardless of res do not apply fwe if program runaway has occurred. during fwe application, the program execution state must be monitored using the watchdog timer or some other means. disconnect fwe only when the swe, esu, psu, ev, pv, e, and p bits in flmcr1 are cleared. make sure that the swe, esu, psu, ev, pv, e, and p bits are not set by mistake when applying or disconnecting fwe. 4. do not apply a constant high level to the fwe pin. t prevent erroneous programming or erasing due to program runaway, etc., apply a high level to the fwe pin only when programming or erasing flash memory (including execution of flash memory emulation using ram). a system configuration in which a high level is constantly applied to the fwe pin should be avoided. also, while a high level is applied to the fwe pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. 5. use the recommended algorithm when programming and erasing flash memory. the recommended algorithm enables programming and erasing to be carried out without subjecting the device to voltage stress or sacrificing program data reliability. when setting the p or e bit in flmcr1, the watchdog timer should be set beforehand as a precaution against program runaway, etc. also note that access to the flash memory space by means of a mov instruction, etc., is not permitted while the p bit or e bit is set. 6. do not set or clear the swe bit during execution of a program in flash memory. clear the swe bit before executing a program or reading data in flash memory. when the swe bit is set, data in flash memory can be rewritten, but flash memory should only be accessed for verify operations (verification during programming/erasing). similarly, when using the ram emulation function while a high level is being input to the fwe pin, the swe bit must be cleared before executing a program or reading data in flash memory. however, the ram area overlapping flash memory space can be read and written to regardless of whether the swe bit is set or cleared. a wait time is necessary after the swe bit is cleared. for details see table 21.19 in section 21.2.6, flash memory characteristics. 7. do not use interrupts while flash memory is being programmed or erased. all interrupt requests, including nmi, should be disabled during fwe application to give priority to program/erase operations (including emulation in ram). bus release must also be disabled. 557 8. do not perform additional programming. erase the memory before reprogramming. in on-board programming, perform only one programming operation on a 128-byte programming unit block. programming should be carried out with the entire programming unit block erased. 9. before programming, check that the chip is correctly mounted in the prom writer. overcurrent damage to the device can result if the index marks on the prom writer socket, socket adapter, and chip are not correctly aligned. 10. do not touch the socket adapter or chip during programming. touching either of these can cause contact faults and write errors. 11. a wait time of 100 ? or more is necessary when performing a read after a transition to normal mode from program, erase, or verify mode. 12. use byte access on the registers that control the flash memory (flmcr1, flmcr2, ebr, and ramcr). 558 period during which flash memory access is prohibited (x: wait time after setting swe bit, y: wait time after clearing swe bit) * 2 period during which flash memory can be programmed (execution of program in flash memory prohibited, and data reads other than verify operations prohibited) notes: *1 except when switching modes, the level of the mode pins (md 2 e md 0 ) must be fixed until power-off by pulling the pins up or down. *2 see section 21.2.6, flash memory characteristics. v cc fwe t osc1 min 0 s t mds t mds md 2 to md 0 * 1 res swe bit swe set swe cleared program- ming/ erasing possible wait time: x wait time: y min 0 s figure 18.16 power-on/off timing (boot mode) 559 period during which flash memory access is prohibited (x: wait time after setting swe bit, y: wait time after clearing swe bit) * 2 period during which flash memory can be programmed (execution of program in flash memory prohibited, and data reads other than verify operations prohibited) v cc fwe t osc1 min 0 s t mds md 2 to md 0 * 1 res swe bit swe set swe cleared program- ming/ erasing possible wait time: x wait time: y notes: *1 except when switching modes, the level of the mode pins (md 2 e md 0 ) must be fixed until power-off by pulling the pins up or down. *2 see section 21.2.6, flash memory characteristics. figure 18.17 power-on/off timing (user program mode) 560 period during which flash memory access is prohibited (x: wait time after setting swe bit, y: wait time after clearing swe bit) * 3 period during which flash memory can be programmed (execution of program in flash memory prohibited, and data reads other than verify operations prohibited) v cc fwe t osc1 min 0 s t mds t mds t mds t resw md 2 to md 0 res swe bit mode change * 1 user mode boot mode user program mode swe set swe cleared * 2 programming/ erasing possible wait time: x wait time: y programming/ erasing possible wait time: x wait time: y programming/ erasing possible wait time: x programming/ erasing possible wait time: x wait time: y mode change * 1 user mode user program mode notes: *1 when entering boot mode or making a transition from boot mode to another mode, mode switching must be carried out by means of res input. the state of ports with multiplexed address functions and bus control output pins ( csn , as , rd , wr ) will change during this switchover interval (the interval during which the res pin input is low), and therefore these pins should not be used as output signals during this time. *2 when making a transition from boot mode to another mode, the mode programming setup time t mds must be satisfied with respect to res clearance timing. *3 see section 21.2.6, flash memory characteristics. figure 18.18 mode transition timing (example: boot mode user mode ? ? ? ? user program mode) 561 18.12 notes when converting the f-ztat application software to the mask rom versions please note the following when converting the f-ztat application software to the mask rom versions. the values read from the internal registers for the flash rom or the mask rom version and f-ztat version differ as follows. status register bit value f-ztat version mask rom version flmcr1 fwe 0 application software running ? (is not read out) 1 programming application software running (always read as 1) note: this difference applies to all the f-ztat versions and all the mask rom versions that have different rom size. 562 563 section 19 clock pulse generator 19.1 overview the h8/3024 series has a built-in clock pulse generator (cpg) that generates the system clock ( ) and other internal clock signals ( /2 to /4096). after duty adjustment, a frequency divider divides the clock frequency to generate the system clock ( ). the system clock is output at the pin * 1 and furnished as a master clock to prescalers that supply clock signals to the on-chip supporting modules. frequency division ratios of 1/1, 1/2, 1/4, and 1/8 can be selected for the frequency divider by settings in a division control register (divcr) * 2 . power consumption in the chip is reduced in almost direct proportion to the frequency division ratio. notes: *1 usage of the pin differs depending on the chip operating mode and the pstop bit setting in the module standby control register (mstcr). for details, see section 20.7, system clock output disabling function. *2 the division ratio of the frequency divider can be changed dynamically during operation. the clock output at the pin also changes when the division ratio is changed. the frequency output at the pin is shown below. = extal n where, extal: frequency of crystal resonator or external clock signal n: frequency division ratio (n = 1/1, 1/2, 1/4, or 1/8) 19.1.1 block diagram figure 19.1 shows a block diagram of the clock pulse generator. xtal extal cpg figure 19.1 block diagram of clock pulse generator 564 19.2 oscillator circuit clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock signal. 19.2.1 connecting a crystal resonator circuit configuration: a crystal resonator can be connected as in the example in figure 19.2. damping resistance rd should be selected according to table 19.1 (1), and external capacitances c l1 and c l2 according to table 19.1 (2). an at-cut parallel-resonance crystal should be used. extal xtal c l1 c l2 rd figure 19.2 connection of crystal resonator (example) if a crystal resonator with a frequency higher than 20 mhz is connected, the external load capacitance values in table 19.1 (2) should not exceed 10 [pf]. also, in order to improve the accuracy of the oscillation frequency, a thorough study of oscillation matching evaluation, etc., should be carried out when deciding the circuit constants. table 19.1 (1) damping resistance value damping resistance frequency f (mhz) value 22 < < < < f 44 < < < < f 88 < < < < f 10 10 < < < < f 13 13 < < < < f 16 16 < < < < f 18 18 < < < < f 25 rd ( ? table 19.1 (2) external capacitance values external capacitance value 3.3 v version frequency f (mhz) 16 < < < < f 25 2 f 16 c l1 = c l2 (pf) 10 to 22 22 565 crystal resonator: figure 19.3 shows an equivalent circuit of the crystal resonator. the crystal resonator should have the characteristics listed in table 19.2. xtal lrs c l c 0 extal at-cut parallel-resonance type figure 19.3 crystal resonator equivalent circuit table 19.2 crystal resonator parameters frequency (mhz) 248101216182025 rs max ( ? use a crystal resonator with a frequency equal to the system clock frequency ( ). notes on board design: when a crystal resonator is connected, the following points should be noted: other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation. see figure 19.4. when the board is designed, the crystal resonator and its load capacitors should be placed as close as possible to the xtal and extal pins. xtal extal c l2 c l1 h8/3024 series avoid signal a signal b figure 19.4 oscillator circuit block board design precautions 566 19.2.2 external clock input circuit configuration: an external clock signal can be input as shown in the examples in figure 19.5. if the xtal pin is left open, the stray capacitance should not exceed 10 pf. if the stray capacitance at the xtal pin exceeds 10 pf in configuration a, use the connection shown in configuration b instead, and hold the external clock high in standby mode. extal xtal extal xtal external clock input open external clock input a. xtal pin left open b. complementary clock input at xtal pin figure 19.5 external clock input (examples) external clock: the external clock frequency should be equal to the system clock frequency when not divided by the on-chip frequency divider. table 19.3 shows the clock timing, figure 19.6 shows the external clock input timing, and figure 19.7 shows the external clock output settling delay timing. when the appropriate external clock is input via the extal pin, its waveform is corrected by the on-chip oscillator and duty adjustment circuit. when the appropriate external clock is input via the extal pin, its waveform is corrected by the on-chip oscillator and duty adjustment circuit. the resulting stable clock is output to external devices after the external clock settling time (t dext ) has passed after the clock input. the system must remain reset with the reset signal low during t dext , while the clock output is unstable. 567 table 19.3 (1) clock timing for on-chip flash memory versions v cc = 3.0 v to 3.6 v item symbol min max unit test conditions external clock input low t exl t cyc / 2 - 5 ? ns res table 19.3 (2) clock timing for on-chip mask rom versions v cc = 3.0 v to 3.6 v item symbol min max unit test conditions external clock input low t exl t cyc / 2 - 5 ? ns res 568 extal t exr t exf v cc 0.7 0.3 v t exh t exl v cc 0.5 figure 19.6 external clock input timing v cc stby extal (internal or external) res t dext v ih figure 19.7 external clock output settling delay timing 19.3 duty adjustment circuit when the oscillator frequency is 5 mhz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate . 19.4 prescalers the prescalers divide the system clock ( ) to generate internal clocks ( /2 to /4096). 19.5 frequency divider the frequency divider divides the duty-adjusted clock signal to generate the system clock ( ). the frequency division ratio can be changed dynamically by modifying the value in divcr, as described below. power consumption in the chip is reduced in almost direct proportion to the 569 frequency division ratio. the system clock generated by the frequency divider can be output at the pin. 19.5.1 register configuration table 19.4 summarizes the frequency division register. table 19.4 frequency division register address* name abbreviation r/w initial value h'ee01b division control register divcr r/w h'fc note: * lower 20 bits of the address in advanced mode. 19.5.2 division control register (divcr) divcr is an 8-bit readable/writable register that selects the division ratio of the frequency divider. bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 0 div0 0 r/w 2 ? 1 ? 1 div1 0 r/w reserved bits divide bits 1 and 0 these bits select the frequency division ratio divcr is initialized to h'fc by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 7 to 2?eserved: these bits cannot be modified and are always read as 1. bits 1 and 0?ivide (div1, div0): these bits select the frequency division ratio, as follows. bit 1 div1 bit 0 div0 frequency division ratio 0 0 1/1 (initial value) 0 1 1/2 1 0 1/4 1 1 1/8 570 19.5.3 usage notes the divcr setting changes the frequency, so note the following points. ? select a frequency division ratio that stays within the assured operation range specified for the clock cycle time t cyc in the ac electrical characteristics. note that min = lower limit of the operating frequency range. ensure that ?is not below this lower limit. ? all on-chip module operations are based on . note that the timing of timer operations, serial communication, and other time-dependent processing differs before and after any change in the division ratio. the waiting time for exit from software standby mode also changes when the division ratio is changed. for details, see section 20.4.3, selection of waiting time for exit from software standby mode. 571 section 20 power-down state 20.1 overview the h8/3024 series has a power-down state that greatly reduces power consumption by halting the cpu, and a module standby function that reduces power consumption by selectively halting on-chip modules. the power-down state includes the following three modes: ? sleep mode ? software standby mode ? hardware standby mode the module standby function can halt on-chip supporting modules independently of the power- down state. the modules that can be halted are the 16-bit timer, 8-bit timer, sci0, sci1, and a/d converter. table 20.1 indicates the methods of entering and exiting the power-down modes and module standby mode, and gives the status of the cpu and on-chip supporting modules in each mode. 572 table 20.1 power-down state and module standby function notes: *1 state in which the corresponding mstcr bit was set to 1. for details see section 20.2.2, module standby control regis ter h (mstcrh) and section 20.2.3, module standby control register l (mstcrl). *2 the rame bit must be cleared to 0 in syscr before the transition from the program execution state to hardware standby mode. *3 when p6 7 is used as the m ode s leep m ode s oftware s tandby m ode h ardware s tandby m ode m odule s tandby state entering conditions sleep instruc- tion executed while ssby = 0 in syscr sleep instruc- tion executed while ssby = 1 in syscr low input at stby clock active halted halted active cpu halted halted halted active cpu registers held held undeter- mined ? 16-bit timer active halted and reset halted and reset halted *1 and reset 8-bit timer active halted and reset halted and reset halted *1 and reset sci0 active halted and reset halted and reset halted *1 and reset sci1 active halted and reset halted and reset halted *1 and reset a/d active halted and reset halted and reset halted *1 and reset other modules active halted and reset halted and reset active ram held held held *2 ? clock output *3 i/o ports held held high impedance ? exiting conditions interrupt res stby irq irq res stby stby res stby res 573 20.2 register configuration the h8/3024 series has a system control register (syscr) that controls the power-down state, and module standby control registers h (mstcrh) and l (mstcrl) that control the module standby function. table 20.2 summarizes these registers. table 20.2 control register address* name abbreviation r/w initial value h'ee012 system control register syscr r/w h'09 h'ee01c module standby control register h mstcrh r/w h'78 h'ee01d module standby control register l mstcrl r/w h'00 note: * lower 20 bits of the address in advanced mode. 20.2.1 system control register (syscr) bit initial value read/write 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 4 sts0 0 r/w 3 ue 1 r/w 0 rame 1 r/w 2 nmieg 0 r/w 1 ssoe 0 r/w software standby enables transition to software standby mode ram enable standby timer select 2 to 0 these bits select the waiting time of the cpu and peripheral functions user bit enable nmi edge select software standby output port enable syscr is an 8-bit readable/writable register. bit 7 (ssby), bits 6 to 4 (sts2 to sts0), and bit 1 (ssoe) control the power-down state. for information on the other syscr bits, see section 3.3, system control register (syscr). 574 bit 7?oftware standby (ssby): enables transition to software standby mode. when software standby mode is exited by an external interrupt, this bit remains set to 1 after the return to normal operation. to clear this bit, write 0. bit 7 ssby description 0 sleep instruction causes transition to sleep mode (initial value) 1 sleep instruction causes transition to software standby mode bits 6 to 4?tandby timer select (sts2 to sts0): these bits select the length of time the cpu and on-chip supporting modules wait for the clock to settle when software standby mode is exited by an external interrupt. if the clock is generated by a crystal resonator, set these bits according to the clock frequency so that the waiting time will be at least 7 ms. see table 20.3. if an external clock is used, choose a setting, according to the operating frequency, that gives a wait time of at least 100 s. bit 6 sts2 bit 5 sts1 bit 4 sts0 description 0 0 0 waiting time = 8,192 states (initial value) 1 waiting time = 16,384 states 1 0 waiting time = 32,768 states 1 waiting time = 65,536 states 1 0 0 waiting time = 131,072 states 1 0 1 waiting time = 262,144 states 1 1 0 waiting time = 1,024 states 1 1 1 illegal setting bit 1?oftware standby output port enable (ssoe): specifies whether the address bus and bus control signals ( cs 0 to cs 7 , as , rd , hwr , and lwr ) are kept as outputs or fixed high, or placed in the high-impedance state in software standby mode. bit 1 ssoe description 0 in software standby mode, the address bus and bus control signals are all high-impedance (initial value) 1 in software standby mode, the address bus retains its output state and bus control signals are fixed high 575 20.2.2 module standby control register h (mstcrh) mstcrh is an 8-bit readable/writable register that controls output of the system clock ( ). it also controls the module standby function, which places individual on-chip supporting modules in the standby state. module standby can be designated for the sci0, sci1. bit initial value read/write 7 pstop 0 r/w 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 0 mstph0 0 r/w 2 ? 0 r/w 1 mstph1 0 r/w clock stop enables or disables output of the system clock module standby h1 to 0 these bits select modules to be placed in standby reserved bits mstcrh is initialized to h'78 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 7 clock stop (pstop): enables or disables output of the system clock ( ). bit 7 pstop description 0 system clock output is enabled (initial value) 1 system clock output is disabled bits 6 to 3?eserved: these bits cannot be modified and are always read as 1. bit 2?eserved: this bit can be written and read. bit 1?odule standby h1 (mstph1): selects whether to place the sci1 in standby. bit 1 mstph1 description 0 sci1 operates normally (initial value) 1 sci1 is in standby state 576 bit 0?odule standby h0 (mstph0): selects whether to place the sci0 in standby. bit 0 mstph0 description 0 sci0 operates normally (initial value) 1 sci0 is in standby state 20.2.3 module standby control register l (mstcrl) mstcrl is an 8-bit readable/writable register that controls the module standby function, which places individual on-chip supporting modules in the standby state. module standby can be designated for 16-bit timer, 8-bit timer, and a/d converter modules. 2 mstpl2 0 r/w 1 ? 0 r/w 0 mstpl0 0 r/w reserved bits module standby l4 to l2, l0 these bits select modules to be placed in standby bit initial value read/write 7 ? 0 r/w 6 ? 0 r/w 5 ? 0 r/w 4 mstpl4 0 r/w 3 mstpl3 0 r/w mstcrl is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 7 to 5?eserved: this bit can be written and read. bit 4?odule standby l4 (mstpl4): selects whether to place the 16-bit timer in standby. bit 4 mstpl4 description 0 16-bit timer operates normally (initial value) 1 16-bit timer is in standby state 577 bit 3?odule standby l3 (mstpl3): selects whether to place 8-bit timer channels 0 and 1 in standby. bit 3 mstpl3 description 0 8-bit timer channels 0 and 1 operate normally (initial value) 1 8-bit timer channels 0 and 1 are in standby state bit 2?odule standby l2 (mstpl2): selects whether to place 8-bit timer channels 2 and 3 in standby. bit 2 mstpl2 description 0 8-bit timer channels 2 and 3 operate normally (initial value) 1 8-bit timer channels 2 and 3 are in standby state bit 1?eserved: this bit can be written and read. bit 0?odule standby l0 (mstpl0): selects whether to place the a/d converter in standby. bit 0 mstpl0 description 0 a/d converter operates normally (initial value) 1 a/d converter is in standby state 578 20.3 sleep mode 20.3.1 transition to sleep mode when the ssby bit is cleared to 0 in syscr, execution of the sleep instruction causes a transition from the program execution state to sleep mode. immediately after executing the sleep instruction the cpu halts, but the contents of its internal registers are retained. on-chip supporting modules do not halt in sleep mode. modules which have been placed in standby by the module standby function, however, remain halted. 20.3.2 exit from sleep mode sleep mode is exited by an interrupt, or by input at the res or stby pin. exit by interrupt: an interrupt terminates sleep mode and causes a transition to the interrupt exception handling state. sleep mode is not exited by an interrupt source in an on-chip supporting module if the interrupt is disabled in the on-chip supporting module. sleep mode is not exited by an interrupt other than nmi if the interrupt is masked by interrupt priority settings and the settings of the i and ui bits in ccr, ipr. exit by res input: low input at the res pin exits from sleep mode to the reset state. exit by stby input: low input at the stby pin exits from sleep mode to hardware standby mode. 20.4 software standby mode 20.4.1 transition to software standby mode to enter software standby mode, execute the sleep instruction while the ssby bit is set to 1 in syscr. in software standby mode, current dissipation is reduced to an extremely low level because the cpu, clock, and on-chip supporting modules all halt. on-chip supporting modules are reset and halted. as long as the specified voltage is supplied, however, cpu register contents and on-chip ram data are retained. the settings of the i/o ports also held. when the wdt is used as a watchdog timer (wt/ it = 1), the tme bit must be cleared to 0 before setting ssby. also, when setting tme to 1, ssby should be cleared to 0. clear the brle bit in brcr (inhibiting bus release) before making a transition to software standby mode. 579 20.4.2 exit from software standby mode software standby mode can be exited by input of an external interrupt at the nmi, irq 0 , irq 1 , or irq 2 pin, or by input at the res or stby pin. exit by interrupt: when an nmi, irq 0 , irq 1 , or irq 2 interrupt request signal is received, the clock oscillator begins operating. after the oscillator settling time selected by bits sts2 to sts0 in syscr, stable clock signals are supplied to the entire chip, software standby mode ends, and interrupt exception handling begins. software standby mode is not exited if the interrupt enable bits of interrupts irq 0 , irq 1 , and irq 2 are cleared to 0, or if these interrupts are masked in the cpu. exit by res input: when the res input goes low, the clock oscillator starts and clock pulses are supplied immediately to the entire chip. the res signal must be held low long enough for the clock oscillator to stabilize. when res goes high, the cpu starts reset exception handling. exit by stby input: low input at the stby pin causes a transition to hardware standby mode. 20.4.3 selection of waiting time for exit from software standby mode bits sts2 to sts0 in syscr and bits div1 and div0 in divcr should be set as follows. crystal resonator: set sts2 to sts0, div1, and div0 so that the waiting time (for the clock to stabilize) is at least 7 ms. table 20.3 indicates the waiting times that are selected by sts2 to sts0, div1, and div0 settings at various system clock frequencies. when using an external clock: set bits sts2 to sts0 and bits div0 and div1 to give a wait time of at least 100 s. 580 table 20.3 clock frequency and waiting time for clock to settle div1 div0 sts2 sts1 sts0 waiting time 25 mhz 20 mhz 18 mhz 16 mhz 12 mhz 10 mhz 8 mhz 6 mhz 4 mhz 2 mhz 0 0 0 0 0 8192 states 0.3 0.4 0.46 0.51 0.65 0.8 1.0 1.3 2.0 4.1 0 0 1 16384 states 0.7 0.8 0.91 1.0 1.3 1.6 2.0 2.7 4.1 8.2* 0 1 0 32768 states 1.3 1.6 1.8 2.0 2.7 3.3 4.1 5.5 8.2* 16.4 0 1 1 65536 states 2.6 3.3 3.6 4.1 5.5 6.6 8.2* 10.9* 16.4 32.8 1 0 0 131072 states 5.2 6.6 7.3* 8.2* 10.9* 13.1* 16.4 21.8 32.8 65.5 1 0 1 262144 states 10.5* 13.1* 14.6 16.4 21.8 26.2 32.8 43.7 65.5 131.1 1 1 0 1024 states 0.04 0.05 0.057 0.064 0.085 0.10 0.13 0.17 0.26 0.51 1 1 1 illegal setting 0 1 0 0 0 8192 states 0.7 0.8 0.91 1.02 1.4 1.6 2.0 2.7 4.0 8.2* 0 0 1 16384 states 1.3 1.6 1.8 2.0 2.7 3.3 4.1 5.5 8.2* 16.4 0 1 0 32768 states 2.6 3.3 3.6 4.1 5.5 6.6 8.2* 10.9* 16.4 32.8 0 1 1 65536 states 5.2 6.6 7.3* 8.2* 10.9* 13.1* 16.4 21.8 32.8 65.5 1 0 0 131072 states 10.5* 13.1* 14.6 16.4 21.8 26.2 32.8 43.7 65.5 131.1 1 0 1 262144 states 21.0 26.2 29.1 32.8 43.7 52.4 65.5 87.4 131.1 262.1 1 1 0 1024 states 0.08 0.10 0.11 0.13 0.17 0.20 0.26 0.34 0.51 1.0 1 1 1 illegal setting 1 0 0 0 0 8192 states 1.3 1.6 1.8 2.0 2.7 3.3 4.1 5.5 8.2* 16.4* 0 0 1 16384 states 2.6 3.3 3.6 4.1 5.5 6.6 8.2* 10.9* 16.4 32.8 0 1 0 32768 states 5.2 6.6 7.3* 8.2* 10.9* 13.1* 16.4 21.8 32.8 65.5 0 1 1 65536 states 10.5* 13.1* 14.6 16.4 21.8 26.2 32.8 43.7 65.5 131.1 1 0 0 131072 states 21.0 26.2 29.1 32.8 43.7 52.4 65.5 87.4 131.1 262.1 1 0 1 262144 states 41.9 52.4 58.3 65.5 87.4 104.9 131.1 174.8 262.1 524.3 1 1 0 1024 states 0.16 0.20 0.23 0.26 0.34 0.41 0.51 0.68 1.02 2.0 1 1 1 illegal setting 1 1 0 0 0 8192 states 2.6 3.3 3.6 4.1 5.5 6.6 8.2* 10.9* 16.4* 32.8* 0 0 1 16384 states 5.2 6.6 7.3* 8.2* 10.9* 13.1* 16.4 21.8 32.8 65.5 0 1 0 32768 states 10.5 13.1* 14.6 16.4 21.8 26.2 32.8 43.7 65.5 131.1 0 1 1 65536 states 21.0* 26.2 29.1 32.8 43.7 52.4 65.5 87.4 131.1 262.1 1 0 0 131072 states 41.9 52.4 58.3 65.5 87.4 104.9 131.1 174.8 262.1 524.3 1 0 1 262144 states 83.9 104.9 116.5 131.1 174.8 209.7 262.1 349.5 524.3 1048.6 1 1 0 1024 states 0.33 0.41 0.46 0.51 0.68 0.82 1.0 1.4 2.0 4.1 1 1 1 illegal setting : recommended setting unit ms ms ms ms 581 20.4.4 sample application of software standby mode figure 20.1 shows an example in which software standby mode is entered at the fall of nmi and exited at the rise of nmi. with the nmi edge select bit (nmieg) cleared to 0 in syscr (selecting the falling edge), an nmi interrupt occurs. next the nmieg bit is set to 1 (selecting the rising edge) and the ssby bit is set to 1; then the sleep instruction is executed to enter software standby mode. software standby mode is exited at the next rising edge of the nmi signal. figure 20.1 nmi timing for software standby mode (example) 20.4.5 usage notes the i/o ports retain their existing states in software standby mode. if a port is in the high output state, its output current is not reduced. 582 20.5 hardware standby mode 20.5.1 transition to hardware standby mode regardless of its current state, the chip enters hardware standby mode whenever the stby pin goes low. hardware standby mode reduces power consumption drastically by halting all functions of the cpu, and on-chip supporting modules. all modules are reset except the on-chip ram. as long as the specified voltage is supplied, on-chip ram data is retained. i/o ports are placed in the high-impedance state. clear the rame bit to 0 in syscr before stby goes low to retain on-chip ram data. the inputs at the mode pins (md2 to md0) should not be changed during hardware standby mode. 20.5.2 exit from hardware standby mode hardware standby mode is exited by inputs at the stby and res pins. while res is low, when stby goes high, the clock oscillator starts running. res should be held low long enough for the clock oscillator to settle. when res goes high, reset exception handling begins, followed by a transition to the program execution state. 20.5.3 timing for hardware standby mode figure 20.2 shows the timing relationships for hardware standby mode. to enter hardware standby mode, first drive res low, then drive stby low. to exit hardware standby mode, first drive stby high, wait for the clock to settle, then bring res from low to high. res stby clock oscillator oscillator settling time reset exception handling figure 20.2 hardware standby mode timing 583 20.6 module standby function 20.6.1 module standby timing the module standby function can halt several of the on-chip supporting modules (sci1, sci0, 16- bit timer, 8-bit timer, and a/d converter) independently in the power-down state. this standby function is controlled by bits mstph2 to mstph0 in mstcrh and bits mstpl7 to mstpl0 in mstcrl. when one of these bits is set to 1, the corresponding on-chip supporting module is placed in standby and halts at the beginning of the next bus cycle after the mstcr write cycle. 20.6.2 read/write in module standby when an on-chip supporting module is in module standby, read/write access to its registers is disabled. read access always results in h'ff data. write access is ignored. 20.6.3 usage notes when using the module standby function, note the following points. on-chip supporting module interrupts: before setting a module standby bit, first disable interrupts by that module. when an on-chip supporting module is placed in standby by the module standby function, its registers are initialized, including registers with interrupt request flags. pin states: pins used by an on-chip supporting module lose their module functions when the module is placed in module standby. what happens after that depends on the particular pin. for details, see section 7, i/o ports. pins that change from the input to the output state require special care. for example, if sci1 is placed in module standby, the receive data pin loses its receive data function and becomes a port pin. if its port ddr bit is set to 1, the pin becomes a data output pin, and its output may collide with external sci transmit data. data collision should be prevented by clearing the port ddr bit to 0 or taking other appropriate action. register resetting: when an on-chip supporting module is halted by the module standby function, all its registers are initialized. to restart the module, after its mstcr bit is cleared to 0, its registers must be set up again. it is not possible to write to the registers while the mstcr bit is set to 1. 584 20.7 system clock output disabling function output of the system clock ( ) can be controlled by the pstop bit in mstcrh. when the pstop bit is set to 1, output of the system clock halts and the pin is placed in the high- impedance state. figure 20.3 shows the timing of the starting and stopping of system clock output. when the pstop bit is cleared to 0, output of the system clock is enabled. table 20.4 indicates the state of the pin in various operating states. t1 t2 (pstop = 1) t3 t1 t2 (pstop = 0) mstcrh write cycle mstcrh write cycle high impedance figure 20.3 starting and stopping of system clock output table 20.4 pin state in various operating states operating state pstop = 0 pstop = 1 hardware standby high impedance high impedance software standby always high high impedance sleep mode system clock output high impedance normal operation system clock output high impedance 585 section 21 electrical characteristics 21.1 electrical characteristics of h8/3024 mask rom version and h8/3026 mask rom version 21.1.1 absolute maximum ratings table 21.1 lists the absolute maximum ratings. table 21.1 absolute maximum ratings item symbol value unit power supply voltage v cc e0.3 to +4.6 v input voltage (except for port 7) v in e0.3 to v cc +0.3 v input voltage (port 7) v in e0.3 to av cc +0.3 v reference voltage v ref e0.3 to av cc +0.3 v analog power supply voltage av cc e0.3 to +4.6 v analog input voltage v an e0.3 to av cc +0.3 v operating temperature t opr regular specifications: e20 to +75 ?c wide-range specifications: e40 to +85 ?c storage temperature t stg e55 to +125 ?c caution: permanent damage to the chip may result if absolute maximum ratings are exceeded. 586 21.1.2 dc characteristics table 21.2 dc characteristics conditions: v cc = 3.0 to 3.6 v, av cc = 3.0 to 3.6 v, v ref = 3.0 v to av cc * 1 , v ss = av ss = 0 v* 1 , t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) item symbol min typ max unit test conditions schmitt trigger input voltages port a, p8 0 to p8 2 v t e v t + v t + e v t e v cc res stby res stby reso reso reso 587 item symbol min typ max unit test conditions input leakage current stby res reso < 588 *2 given current consumption values are when all the output pins are made to unloaded state and, furthermore, when the on-chip pull-up mos is turned off under conditions that v ih min = v cc e 0.5 v and v il max = 0.5 v. also, the aforesaid current consumption values are when v ih min = v cc 589 table 21.3 permissible output currents conditions: v cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) item symbol min typ max unit permissible output low current (per pin) ports 1, 2, and 5 other output pins i ol ? ? ? ? 10 2.0 ma ma permissible output low current (total) total of 20 pins in ports 1, 2, and 5 | h8/3024 mask rom version h8/3026 mask rom version port 2 k ? darlington pair figure 21.1 darlington pair drive circuit (example) 590 h8/3024 mask rom version h8/3026 mask rom version ports 1, 2, 5 led 600 ? figure 21.2 sample led circuit 591 21.1.3 ac characteristics clock timing parameters are listed in table 21.4, control signal timing parameters in table 21.5, and bus timing parameters in table 21.6. timing parameters of the on-chip supporting modules are listed in table 21.7. table 21.4 clock timing conditions: v cc = 3.0 to 3.6 v, av cc = 3.0 to 3.6 v, v ref = 3.0 to av cc , v ss = av ss = 0 v, t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) item symbol min max unit test conditions clock cycle time t cyc 40 500 ns figure 21.11 clock pulse low width t cl 10 ? ns clock pulse high width t ch 10 ? ns clock rise time t cr ? 10 ns clock fall time t cf ? 10 ns clock oscillator settling time at reset t osc1 20 ? ms figure 21.7 clock oscillator settling time in software standby t osc2 7 ? ms figure 20.1 table 21.5 control signal timing conditions: v cc = 3.0 to 3.6 v, av cc = 3.0 to 3.6 v, v ref = 3.0 to av cc , v ss = av ss = 0 v, t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) item symbol min max unit test conditions res setup time t ress 150 ? ns figure 21.8 res pulse width t resw 20 ? t cyc mode programming setup time t mds 200 ? ns reso output delay time t resd ? 50 ns figure 21.9 reso output pulse width t resow 132 ? t cyc nmi, irq setup time t nmis 150 ? ns figure 21.10 nmi, irq hold time t nmih 10 ? ns nmi, irq pulse width (in recovery from software standby mode) t nmiw 200 ? ns 592 table 21.6 bus timing conditions: v cc = 3.0 to 3.6 v, av cc = 3.0 to 3.6 v, v ref = 3.0 to av cc , v ss = av ss = 0 v, t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) item symbol min max unit test conditions address delay time t ad ? 25 ns figure 21.11, address hold time t ah 0.5 t cyc e 20 ? ns figure 21.12 read strobe delay time t rsd ? 25 ns address strobe delay time t asd ? 25 ns write strobe delay time t wsd ? 25 ns strobe delay time t sd ? 25 ns write strobe pulse width 1 t wsw1 1.0 t cyc e 25 ? ns write strobe pulse width 2 t wsw2 1.5 t cyc e 25 ? ns address setup time 1 t as1 0.5 t cyc e 20 ? ns address setup time 2 t as2 1.0 t cyc e 20 ? ns read data setup time t rds 25 ? ns read data hold time t rdh 0 ? ns write data delay time t wdd ? 35 ns write data setup time 1 t wds1 1.0 t cyc e 30 ? ns write data setup time 2 t wds2 2.0 t cyc e 30 ? ns write data hold time t wdh 0.5 t cyc e 15 ? ns read data access time 1 t acc1 ? 2.0 t cyc e 45 ns read data access time 2 t acc2 ? 3.0 t cyc e 45 ns read data access time 3 t acc3 ? 1.5 t cyc e 45 ns read data access time 4 t acc4 ? 2.5 t cyc e 45 ns precharge time 1 t pch1 1.0 t cyc e 20 ? ns precharge time 2 t pch2 0.5 t cyc e 20 ? ns wait setup time t wts 25 ? ns figure 21.13 wait hold time t wth 5 ? ns bus request setup time t brqs 25 ? ns figure 21.14 bus acknowledge delay time 1 t bacd1 ? 30 ns bus acknowledge delay time 2 t bacd2 ? 30 ns bus-floating time t bzd ? 30 ns note: in order to secure the address hold time relative to the rise of the rd strobe, address update mode 2 should be used. for details see section 6.3.5, address output method. 593 table 21.7 timing of on-chip supporting modules conditions: v cc = 3.0 to 3.6 v, av cc = 3.0 to 3.6 v, v ref = 3.0 to av cc , v ss = av ss = 0 v, t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) module item symbol min max unit test conditions ports and output data delay time t pwd ? 50 ns figure 21.15 tpc input data setup time t prs 50 ? ns input data hold time t prh 50 ? ns 16-bit timer timer output delay time t tocd ? 50 ns figure 21.16 timer input setup time t tics 50 ? ns timer clock input setup time t tcks 50 ? ns figure 21.17 timer clock single edge t tckwh 1.5 ? t cyc pulse width both edges t tckwl 2.5 ? t cyc 8-bit timer timer output delay time t tocd ? 50 ns figure 21.16 timer input setup time t tics 50 ? ns timer clock input setup time t tcks 50 ? ns figure 21.17 timer clock single edge t tckwh 1.5 ? t cyc pulse width both edges t tckwl 2.5 ? t cyc sci input clock asynchronous t scyc 4 ? t cyc figure 21.18 cycle synchronous 6 ? t cyc input clock rise time t sckr 1.5 ? t cyc input clock fall time t sckf 1.5 ? t cyc input clock pulse width t sckw 0.4 0.6 t scyc transmit data delay time t txd ? 100 ns figure 21.19 receive data setup time (synchronous) t rxs 100 ? ns receive data hold time clock input t rxh 100 ? ns (synchronous) clock output 0 ? ns 594 cr h r l chip output pin c = 90 pf: ports 1 to 6, 8 c = 30 pf: ports 9, a, b, reso input/output timing measurement levels low: 0.8 v high: 2.0 v r = 2.4 k r = 12 k l h ? ? figure 21.3 output load circuit 595 21.1.4 a/d conversion characteristics table 21.8 lists the a/d conversion characteristics. table 21.8 a/d conversion characteristics conditions: v cc = 3.0 to 3.6 v, av cc = 3.0 to 3.6 v, v ref = 3.0 to av cc , v ss = av ss = 0 v, fmax = 25 mhz, t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) item min typ max unit conversion time: resolution 10 10 10 bits 134 states conversion time (single mode) 5.36 ?? s analog input capacitance ?? 20 pf permissible signal- 13 mhz ?? 10 k ? source impedance > 13 mhz ?? 5k ? nonlinearity error ?? 3.5 lsb offset error ?? 3.5 lsb full-scale error ?? 3.5 lsb quantization error ?? 0.5 lsb absolute accuracy ?? 4.0 lsb conversion time: resolution 10 10 10 bits 70 states conversion time (single mode) 5.36 ?? s analog input capacitance ?? 20 pf permissible signal- 13 mhz ?? 5k ? source impedance > 13 mhz ?? 3k ? nonlinearity error ?? 7.5 lsb offset error ?? 7.5 lsb full-scale error ?? 7.5 lsb quantization error ?? 0.5 lsb absolute accuracy ?? 4.0 lsb 596 21.1.5 d/a conversion characteristics table 21.9 lists the d/a conversion characteristics. table 21.9 d/a conversion characteristics conditions: v cc = 3.0 to 3.6 v, av cc = 3.0 to 3.6 v, v ref = 3.0 to av cc , v ss = av ss = 0 v, fmax = 25 mhz, t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) item min typ max unit test conditions resolution 8 8 8 bits conversion time (centering time) ?? 10 s 20 pf capacitive load absolute accuracy ? 2.0 3.0 lsb 2 m ? resistive load ?? 2.0 lsb 4 m ? resistive load 597 21.2 electrical characteristics of h8/3024f-ztat version and h8/3026f-ztat version 21.2.1 absolute maximum ratings table 21.10 lists the absolute maximum ratings. table 21.10 absolute maximum ratings item symbol value unit power supply voltage v cc e 0.3 to +4.6 v input voltage (except for port 7) v in e 0.3 to v cc +0.3 v input voltage (port 7) v in e 0.3 to av cc +0.3 v reference voltage v ref e 0.3 to av cc +0.3 v analog power supply voltage av cc e 0.3 to +4.6 v analog input voltage v an e 0.3 to av cc +0.3 v operating temperature t opr regular specifications: e 20 to +75 ? c wide-range specifications: e 40 to +85 ? c storage temperature t stg e 55 to +125 ? c caution: permanent damage to the chip may result if absolute maximum ratings are exceeded. 598 21.2.2 dc characteristics table 21.11 dc characteristics conditions: v cc = 3.0 to 3.6 v, av cc = 3.0 to 3.6 v, v ref = 3.0 v to av cc * 1 , v ss = av ss = 0 v* 1 , t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) item symbol min typ max unit test conditions schmitt trigger input voltages port a, p8 0 to p8 2 v t e v t + v t + e v t e v cc 0.2 ? v cc 0.05 ? ? ? ? v cc 0.7 ? v v v input high voltage res , stby , nmi, md 2 to md 0 v ih v cc 0.9 ? v cc + 0.3 v extal v cc 0.7 ? v cc + 0.3 v port 7 v cc 0.7 ? av cc + 0.3 v ports 1 to 6 p8 3 , p8 4 , p9 0 to p9 5 , port b v cc 0.7 ? v cc + 0.3 v input low voltage res , stby , md 2 to md 0 v il e 0.3 ? v cc 0.1 v nmi, extal, ports 1 to 7 p8 3 , p8 4 , p9 0 to p9 5 , port b e 0.3 ? v cc 0.2 0.8 v v v cc < 4.0 v v cc = 4.0 to 5.5 v output high voltage all output pins (except reso ) v oh v cc e 0.5 ?? vi oh = e 200 a v cc e 1.0 ?? vi oh = e 1 ma output low voltage all output pins (except reso ) v ol ?? 0.4 v i ol = 1.6 ma ports 1, 2, and 5 ?? 1.0 v i ol = 5 ma (v cc < 4.0 v) i ol = 10 ma (v cc = 4.0 to 5.5 v) reso 0.4 v i ol = 1.6 ma 599 item symbol min typ max unit test conditions input leakage current stby , res , nmi, md 2 to md 0 |i in | ?? 1.0 a v in = 0.5 v to v cc e 0.5 v port 7 ?? 1.0 a v in = 0.5 v to av cc e 0.5 v three-state leakage current ports 1 to 6 ports 8 to b |i tsi | ?? 1.0 a v in = 0.5 v to v cc e 0.5 v reso 10.0 a v in = 0 v input pull-up mos current ports 2, 4, and 5 e i p 10 ? 300 a v in = 0 v input capacitance nmi all input pins except nmi c in ? ? ? ? 50 15 pf pf v in = 0 v f = f min t a = 25 ? c current dissipation* 2 normal operation i cc * 3 ? 37 (3.3 v) 58 ma f = 25 mhz sleep mode ? 29 (3.3 v) 47 ma f = 25 mhz module standby mode ? 21 (3.3 v) 37 ma f = 25 mhz standby mode ? 1.0 10.0 a t a 50 ? c ?? 20.0 a 50 ? c < t a analog power supply current during a/d conversion ai cc ? 0.6 1.5 ma av cc = 3.0 v during a/d and d/a conversion ? 0.6 1.5 ma av cc = 3.0 v idle ? 0.01 5.0 a daste = 0 reference current during a/d conversion ai cc ? 0.45 0.8 ma v ref = 3.0 v during a/d and d/a conversion ? 2.0 3.0 ma v ref = 3.0 v idle ? 0.01 5.0 a daste = 0 ram standby voltage v ram 2.0 ?? v notes: *1 do not open the pin connections of the av cc , v ref and av ss pins while the a/d converter is not in use. connect the av cc and v ref pins to the v cc and connect the av ss pin to the v ss , respectively. 600 *2 given current consumption values are when all the output pins are made to unloaded state and, furthermore, when the on-chip pull-up mos is turned off under conditions that v ih min = v cc e 0.5 v and v il max = 0.5 v. also, the aforesaid current consumption values are when v ih min = v cc 0.9 and v il max = 0.3 v under the condition of v ram v cc < 3.0 v. *3 i cc max. (under normal operations) = 3.0 (ma) + 0.61 (ma/(mhz v)) v cc f i cc max. (when using the sleeve) = 3.0 (ma) + 0.49 (ma/(mhz v)) v cc x f i cc max. (when the sleeve + module are standing by) = 3.0 (ma) + 0.38 (ma/(mhz v)) v cc f also, the typ. values for current dissipation are reference values. 601 table 21.12 permissible output currents conditions: v cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) item symbol min typ max unit permissible output low current (per pin) ports 1, 2, and 5 other output pins i ol ? ? ? ? 10 2.0 ma ma permissible output low current (total) total of 20 pins in ports 1, 2, and 5 i ol ?? 80 ma total of all output pins, including the above ?? 120 ma permissible output high current (per pin) all output pins | e i oh | ?? 2.0 ma permissible output high current (total) total of all output pins | i oh | ?? 40 ma notes: 1. to protect chip reliability, do not exceed the output current values in table 21.12. 2. when directly driving a darlington pair or led, always insert a current-limiting resistor in the output line, as shown in figures 21.4 and 21.5. h8/3024f-ztat version h8/3026f-ztat version port 2 k ? darlington pair figure 21.4 darlington pair drive circuit (example) 602 h8/3024f-ztat version h8/3026f-ztat version ports 1, 2, 5 led 600 ? figure 21.5 sample led circuit 603 21.2.3 ac characteristics clock timing parameters are listed in table 21.13, control signal timing parameters in table 21.14, and bus timing parameters in table 21.15. timing parameters of the on-chip supporting modules are listed in table 21.16. table 21.13 clock timing conditions: v cc = 3.0 to 3.6 v, av cc = 3.0 to 3.6 v, v ref = 3.0 to av cc , v ss = av ss = 0 v, t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) item symbol min max unit test conditions clock cycle time t cyc 40 500 ns figure 21.11 clock pulse low width t cl 10 ? ns clock pulse high width t ch 10 ? ns clock rise time t cr ? 10 ns clock fall time t cf ? 10 ns clock oscillator settling time at reset t osc1 20 ? ms figure 21.7 clock oscillator settling time in software standby t osc2 7 ? ms figure 20.1 table 21.14 control signal timing conditions: v cc = 3.0 to 3.6 v, av cc = 3.0 to 3.6 v, v ref = 3.0 to av cc , v ss = av ss = 0 v, t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) item symbol min max unit test conditions res setup time t ress 150 ? ns figure 21.8 res pulse width t resw 20 ? t cyc mode programming setup time t mds 200 ? ns reso output delay time t resd ? 50 ns figure 21.9 reso output pulse width t resow 132 ? t cyc nmi, irq setup time t nmis 150 ? ns figure 21.10 nmi, irq hold time t nmih 10 ? ns nmi, irq pulse width (in recovery from software standby mode) t nmiw 200 ? ns 604 table 21.15 bus timing conditions: v cc = 3.0 to 3.6 v, av cc = 3.0 to 3.6 v, v ref = 3.0 to av cc , v ss = av ss = 0 v, t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) item symbol min max unit test conditions address delay time t ad ? 25 ns figure 21.11, address hold time t ah 0.5 t cyc e 20 ? ns figure 21.12 read strobe delay time t rsd ? 25 ns address strobe delay time t asd ? 25 ns write strobe delay time t wsd ? 25 ns strobe delay time t sd ? 25 ns write strobe pulse width 1 t wsw1 1.0 t cyc e 25 ? ns write strobe pulse width 2 t wsw2 1.5 t cyc e 25 ? ns address setup time 1 t as1 0.5 t cyc e 20 ? ns address setup time 2 t as2 1.0 t cyc e 20 ? ns read data setup time t rds 40 ? ns read data hold time t rdh 0 ? ns write data delay time t wdd ? 35 ns write data setup time 1 t wds1 1.0 t cyc e 30 ? ns write data setup time 2 t wds2 2.0 t cyc e 30 ? ns write data hold time t wdh 0.5 t cyc e 15 ? ns read data access time 1 t acc1 ? 2.0 t cyc e 45 ns read data access time 2 t acc2 ? 3.0 t cyc e 45 ns read data access time 3 t acc3 ? 1.5 t cyc e 45 ns read data access time 4 t acc4 ? 2.5 t cyc e 45 ns precharge time 1 t pch1 1.0 t cyc e 20 ? ns precharge time 2 t pch2 0.5 t cyc e 20 ? ns wait setup time t wts 25 ? ns figure 21.13 wait hold time t wth 5 ? ns bus request setup time t brqs 25 ? ns figure 21.14 bus acknowledge delay time 1 t bacd1 ? 30 ns bus acknowledge delay time 2 t bacd2 ? 30 ns bus-floating time t bzd ? 30 ns note: in order to secure the address hold time relative to the rise of the rd strobe, address update mode 2 should be used. for details see section 6.3.5, address output method. 605 table 21.16 timing of on-chip supporting modules conditions: v cc = 3.0 to 3.6 v, av cc = 3.0 to 3.6 v, v ref = 3.0 to av cc , v ss = av ss = 0 v, t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) module item symbol min max unit test conditions ports and output data delay time t pwd ? 50 ns figure 21.15 tpc input data setup time t prs 50 ? ns input data hold time t prh 50 ? ns 16-bit timer timer output delay time t tocd ? 50 ns figure 21.16 timer input setup time t tics 50 ? ns timer clock input setup time t tcks 50 ? ns figure 21.17 timer clock single edge t tckwh 1.5 ? t cyc pulse width both edges t tckwl 2.5 ? t cyc 8-bit timer timer output delay time t tocd ? 50 ns figure 21.16 timer input setup time t tics 50 ? ns timer clock input setup time t tcks 50 ? ns figure 21.17 timer clock single edge t tckwh 1.5 ? t cyc pulse width both edges t tckwl 2.5 ? t cyc sci input clock asynchronous t scyc 4 ? t cyc figure 21.18 cycle synchronous 6 ? t cyc input clock rise time t sckr 1.5 ? t cyc input clock fall time t sckf 1.5 ? t cyc input clock pulse width t sckw 0.4 0.6 t scyc transmit data delay time t txd ? 100 ns figure 21.19 receive data setup time (synchronous) t rxs 100 ? ns receive data hold time clock input t rxh 100 ? ns (synchronous) clock output 0 ? ns 606 cr h r l chip output pin c = 90 pf: ports 1 to 6, 8 c = 30 pf: ports 9, a, b, reso input/output timing measurement levels low: 0.8 v high: 2.0 v r = 2.4 k r = 12 k l h ? ? figure 21.6 output load circuit 607 21.2.4 a/d conversion characteristics table 21.17 lists the a/d conversion characteristics. table 21.17 a/d conversion characteristics conditions: v cc = 3.0 to 3.6 v, av cc = 3.0 to 3.6 v, v ref = 3.0 to av cc , v ss = av ss = 0 v, fmax = 25 mhz, t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) item min typ max unit conversion time: resolution 10 10 10 bits 134 states conversion time (single mode) 5.36 ?? s analog input capacitance ?? 20 pf permissible signal- 13 mhz ?? 10 k ? source impedance > 13 mhz ?? 5k ? nonlinearity error ?? 3.5 lsb offset error ?? 3.5 lsb full-scale error ?? 3.5 lsb quantization error ?? 0.5 lsb absolute accuracy ?? 4.0 lsb conversion time: resolution 10 10 10 bits 70 states conversion time (single mode) 5.36 ?? s analog input capacitance ?? 20 pf permissible signal- 13 mhz ?? 5k ? source impedance > 13 mhz ?? 3k ? nonlinearity error ?? 7.5 lsb offset error ?? 7.5 lsb full-scale error ?? 7.5 lsb quantization error ?? 0.5 lsb absolute accuracy ?? 4.0 lsb 608 21.2.5 d/a conversion characteristics table 21.18 lists the d/a conversion characteristics. table 21.18 d/a conversion characteristics conditions: v cc = 3.0 to 3.6 v, av cc = 3.0 to 3.6 v, v ref = 3.0 to av cc , v ss = av ss = 0 v, fmax = 25 mhz, t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) item min typ max unit test conditions resolution 8 8 8 bits conversion time (centering time) ?? 10 s 20 pf capacitive load absolute accuracy ? 2.0 3.0 lsb 2 m ? resistive load ?? 2.0 lsb 4 m ? resistive load 609 21.2.6 flash memory characteristics table 21.19 shows the flash memory characteristics. table 21.19 flash memory characteristics conditions: v cc = 3.0 to 3.6 v, av cc = 3.0 to 3.6 v, v ss = av ss = 0 v, t a = 0? to +75? (operating temperature range for programming/erasing) item symbol min typ max unit notes programming time* 1, * 2, * 4 t p ? 10 200 ms/ 128 bytes erase time* 1, * 3, * 5 t e ? 100 1200 ms/block reprogramming count n wec ?? 100 times programming wait time after swe bit setting* 1 t sswe 11 ? s wait time after psu bit setting* 1 t spsu 50 50 ? s wait time after p bit setting* 1, * 4 t sp30 28 30 32 s programming time wait t sp200 198 200 202 s programming time wait t sp10 8 10 12 s additional- programming time wait wait time after p bit clear* 1 t cp 55 ? s wait time after psu bit clear* 1 t cpsu 55 ? s wait time after pv bit setting* 1 t spv 44 ? s wait time after h'ff dummy write* 1 t spvr 22 ? s wait time after pv bit clear* 1 t cpv 22 ? s wait time after swe bit clear* 1 t cswe 100 100 ? s maximum programming count* 1, * 4 n ?? 1000 times erase wait time after swe bit setting* 1 t sswe 11 ? s wait time after esu bit setting* 1 t sesu 100 100 ? s wait time after e bit setting* 1, * 5 t se 10 10 100 ms erase time wait wait time after e bit clear* 1 t ce 10 10 ? s wait time after esu bit clear* 1 t cesu 10 10 ? s wait time after ev bit setting* 1 t sev 20 20 ? s wait time after h'ff dummy write* 1 t sevr 22 ? s wait time after ev bit clear* 1 t cev 44 ? s wait time after swe bit clear* 1 t cswe 100 100 ? s maximum erase count* 1, * 5 n12 ? 120 times 610 notes: *1 make each time setting in accordance with the program/program-verify flowchart or erase/erase-verify flowchart. *2 programming time per 128 bytes (shows the total period for which the p-bit in the flash memory control register (flmcr) is set. it does not include the programming verification time.) *3 block erase time (shows the total period for which the e-bit in flmcr is set. it does not include the erase verification time.) *4 to specify the maximum programming time (t p (max)) in the 128-byte programming flowchart, set the maximum value (1000) for the maximum programming count (n). the wait time after p bit setting should be changed as follows according to the value of the programming counter (n). programming counter (n) = 1 to 6: t sp30 = 30 s programming counter (n) = 7 to 1000: t sp200 = 200 s programming counter (n) [in additional programming] = 1 to 6: t sp10 = 10 s *5 for the maximum erase time (t e (max)), the following relationship applies between the wait time after e bit setting (t se ) and the maximum erase count (n): t e (max) = wait time after e bit setting (t se ) maximum erase count (n) to set the maximum erase time, the values of t se and n should be set so as to satisfy the above formula. examples: when t se = 100 [ms], n = 12 times when t se = 10 [ms], n = 120 times 611 21.3 operational timing this section shows timing diagrams. 21.3.1 clock timing clock timing is shown as follows: ? oscillator settling timing figure 21.7 shows the oscillator settling timing. v cc stby res t osc1 t osc1 figure 21.7 oscillator settling timing 612 21.3.2 control signal timing control signal timing is shown as follows: ? reset input timing figure 21.8 shows the reset input timing. ? reset output timing* figure 21.9 shows the reset output timing. ? interrupt input timing figure 21.10 shows the interrupt input timing for nmi and irq 5 to irq 0 . t ress t ress t resw t mds res fwe md 2 to md 0 figure 21.8 reset input timing reso t resd t resow t resd figure 21.9 reset output timing* note: * this function is used only in mask rom models, and is not provided in flash memory models. 613 n mi i rq i rq e l t nmis t nmih t nmis t nmih t nmis t nmiw nmi irq j irq : edge-sensitive irq : level-sensitive irq (i = 0 to 5) e l i i irq (j = 0 to 5) figure 21.10 interrupt input timing 614 21.3.3 bus timing bus timing is shown as follows: ? basic bus cycle: two-state access figure 21.11 shows the timing of the external two-state access cycle. ? basic bus cycle: three-state access figure 21.12 shows the timing of the external three-state access cycle. ? basic bus cycle: three-state access with one wait state figure 21.13 shows the timing of the external three-state access cycle with one wait state inserted. ? bus-release mode timing figure 21.14 shows the bus-release mode timing. 615 t 1 t 2 t ch t ad t cl t cr t cf t asd t acc3 t as1 t cyc t cyc t sd t rds t ah t pch1 t pch2 t rdh * t pch1 t sd t ah t asd t acc3 t as1 t acc1 t asd t as1 t wsw1 t wds1 t wdh t wdd a 23 to a 0 , cs n as rd (read) d 15 to d 0 (read) hwr, lwr (write) d 15 to d 0 (write) note: * specification from the earliest negation timing of a 23 to a 0 , cs n , and rd . t rsd figure 21.11 basic bus cycle: two-state access 616 t 1 t 2 t 3 t acc4 t acc4 t as2 t wds2 t wsw2 t wsd t wdd t acc2 t rds a 23 to a 0 , cs n as rd (read) d 15 to d 0 (read) hwr, lwr (write) d 15 to d 0 (write) figure 21.12 basic bus cycle: three-state access 617 t 1 t 2 t w t 3 t wts t wts t wth as rd (read) d 15 to d 0 (read) hwr, lwr (write) d 15 to d 0 (write) wait t wth a 23 to a 0 , cs n figure 21.13 basic bus cycle: three-state access with one wait state breq back a 23 to a 0 , as, rd, hwr, lwr t brqs t brqs t bacd1 t bzd t bacd2 t bzd figure 21.14 bus-release mode timing 618 21.3.4 tpc and i/o port timing figure 21.15 shows the tpc and i/o port input/output timing. t 1 t 2 t 3 port 1 to b (read) port 1 to 6, 8 to b (write) t prs t prh t pwd figure 21.15 tpc and i/o port input/output timing 21.3.5 timer input/output timing 16-bit timer and 8-bit timer timing is shown below. ? timer input/output timing figure 21.16 shows the timer input/output timing. ? timer external clock input timing figure 21.17 shows the timer external clock input timing. output compare *1 input capture *2 t tocd t tics notes: *1 tioca0 to tioca2, tiocb0 to tiocb2, tmo0, tmo2, tmio1, tmio3 *2 tioca0 to tioca2, tiocb0 to tiocb2, tmio1, tmio3 figure 21.16 timer input/output timing 619 t tcks t tcks t tckwh t tckwl tclka to tclkd figure 21.17 timer external clock input timing 21.3.6 sci input/output timing sci timing is shown as follows: ? sci input clock timing figure 21.18 shows the sci input clock timing. ? sci input/output timing (synchronous mode) figure 21.19 shows the sci input/output timing in synchronous mode. sck 0 , sck 1 t sckw t scyc t sckr t sckf figure 21.18 sci input clock timing t scyc t txd t rxs t rxh sck 0 , sck 1 txd 0 , txd 1 (transmit data) rxd 0 , rxd 1 (receive data) figure 21.19 sci input/output timing in synchronous mode 620 621 appendix a instruction set a.1 instruction list operand notation symbol description rd general destination register rs general source register rn general register erd general destination register (address register or 32-bit register) ers general source register (address register or 32-bit register) ern general register (32-bit register) (ead) destination operand (eas) source operand pc program counter sp stack pointer ccr condition code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr disp displacement 622 condition code notation symbol description changed according to execution result * undetermined (no guaranteed value) 0 cleared to 0 1 set to 1 not affected by execution of the instruction ? 623 table a.1 instruction set 1. data transfer instructions mnemonic operation condition code operand size #xx rn @ern @(d, ern) @?rn/@ern+ @aa @(d, pc) @@aa addressing mode and instruction length (bytes) normal advanced no. of states* 1 ihnzvc mov.b #xx:8, rd mov.b rs, rd mov.b @ers, rd mov.b @(d:16, ers), rd mov.b @(d:24, ers), rd mov.b @ers+, rd mov.b @aa:8, rd mov.b @aa:16, rd mov.b @aa:24, rd mov.b rs, @erd mov.b rs, @(d:16, erd) mov.b rs, @(d:24, erd) mov.b rs, @ e erd mov.b rs, @aa:8 mov.b rs, @aa:16 mov.b rs, @aa:24 mov.w #xx:16, rd mov.w rs, rd mov.w @ers, rd mov.w @(d:16, ers), rd mov.w @(d:24, ers), rd mov.w @ers+, rd mov.w @aa:16, rd b b b b b b b b b b b b b b b b w w w w w w w 2 2 2 4 8 2 2 4 6 2 4 8 2 2 4 6 4 2 2 4 8 2 4 #xx:8 rd8 rs8 rd8 @ers rd8 @(d:16, ers) rd8 @(d:24, ers) rd8 @ers rd8 ers32+1 ers32 @aa:8 rd8 @aa:16 rd8 @aa:24 rd8 rs8 @erd rs8 @(d:16, erd) rs8 @(d:24, erd) erd32 e 1 erd32 rs8 @erd rs8 @aa:8 rs8 @aa:16 rs8 @aa:24 #xx:16 rd16 rs16 rd16 @ers rd16 @(d:16, ers) rd16 @(d:24, ers) rd16 @ers rd16 ers32+2 @erd32 @aa:16 rd16 2 2 4 6 10 6 4 6 8 4 6 10 6 4 6 8 4 2 4 6 10 6 6 ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 624 mnemonic operation condition code operand size #xx rn @ern @(d, ern) @ ern/@ern+ @aa @(d, pc) @@aa addressing mode and instruction length (bytes) normal advanced no. of states* 1 ihnzvc mov.w @aa:24, rd mov.w rs, @erd mov.w rs, @(d:16, erd) mov.w rs, @(d:24, erd) mov.w rs, @ e erd mov.w rs, @aa:16 mov.w rs, @aa:24 mov.l #xx:32, rd mov.l ers, erd mov.l @ers, erd mov.l @(d:16, ers), erd mov.l @(d:24, ers), erd mov.l @ers+, erd mov.l @aa:16, erd mov.l @aa:24, erd mov.l ers, @erd mov.l ers, @(d:16, erd) mov.l ers, @(d:24, erd) mov.l ers, @ e erd mov.l ers, @aa:16 mov.l ers, @aa:24 pop.w rn pop.l ern w w w w w w w l l l l l l l l l l l l l l w l 6 2 4 8 2 4 6 6 2 4 6 10 4 6 8 4 6 10 4 6 8 2 4 @aa:24 rd16 rs16 @erd rs16 @(d:16, erd) rs16 @(d:24, erd) erd32 e 2 erd32 rs16 @erd rs16 @aa:16 rs16 @aa:24 #xx:32 rd32 ers32 erd32 @ers erd32 @(d:16, ers) erd32 @(d:24, ers) erd32 @ers erd32 ers32+4 ers32 @aa:16 erd32 @aa:24 erd32 ers32 @erd ers32 @(d:16, erd) ers32 @(d:24, erd) erd32 e 4 erd32 ers32 @erd ers32 @aa:16 ers32 @aa:24 @sp rn16 sp+2 sp @sp ern32 sp+4 sp 8 4 6 10 6 6 8 6 2 8 10 14 10 10 12 8 10 14 10 10 12 6 10 ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 625 mnemonic operation condition code operand size #xx rn @ern @(d, ern) @ ern/@ern+ @aa @(d, pc) @@aa addressing mode and instruction length (bytes) normal advanced no. of states* 1 ihnzvc push.w rn push.l ern movfpe @aa:16, rd movtpe rs, @aa:16 w l b b 2 4 4 4 sp e 2 sp rn16 @sp sp e 4 sp ern32 @sp cannot be used in the h8/3024 series cannot be used in the h8/3024 series 6 10 ?? 0 ? ?? 0 ? cannot be used in the h8/3024 series cannot be used in the h8/3024 series ? ? ? ? 2. arithmetic instructions mnemonic operation condition code operand size #xx rn @ern @(d, ern) @ ern/@ern+ @aa @(d, pc) @@aa addressing mode and instruction length (bytes) normal advanced no. of states* 1 ihnzvc add.b #xx:8, rd add.b rs, rd add.w #xx:16, rd add.w rs, rd add.l #xx:32, erd add.l ers, erd addx.b #xx:8, rd addx.b rs, rd adds.l #1, erd adds.l #2, erd adds.l #4, erd inc.b rd inc.w #1, rd inc.w #2, rd b b w w l l b b l l l b w w 2 2 4 2 6 2 2 2 2 2 2 2 2 2 rd8+#xx:8 rd8 rd8+rs8 rd8 rd16+#xx:16 rd16 rd16+rs16 rd16 erd32+#xx:32 erd32 erd32+ers32 erd32 rd8+#xx:8 +c rd8 rd8+rs8 +c rd8 erd32+1 erd32 erd32+2 erd32 erd32+4 erd32 rd8+1 rd8 rd16+1 rd16 rd16+2 rd16 2 2 4 2 6 2 2 2 2 2 2 2 2 2 ? ? ? (1) ? (1) ? (2) ? (2) ? (3) ? (3) ?????? ?????? ?????? ?? ? ?? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 626 mnemonic operation condition code operand size #xx rn @ern @(d, ern) @ ern/@ern+ @aa @(d, pc) @@aa addressing mode and instruction length (bytes) normal advanced no. of states* 1 ihnzvc inc.l #1, erd inc.l #2, erd daa rd sub.b rs, rd sub.w #xx:16, rd sub.w rs, rd sub.l #xx:32, erd sub.l ers, erd subx.b #xx:8, rd subx.b rs, rd subs.l #1, erd subs.l #2, erd subs.l #4, erd dec.b rd dec.w #1, rd dec.w #2, rd dec.l #1, erd dec.l #2, erd das.rd mulxu. b rs, rd mulxu. w rs, erd mulxs. b rs, rd mulxs. w rs, erd divxu. b rs, rd l l b b w w l l b b l l l b w w l l b b w b w b 2 2 2 2 4 2 6 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4 4 2 erd32+1 erd32 erd32+2 erd32 rd8 decimal adjust rd8 rd8 e rs8 rd8 rd16 e #xx:16 rd16 rd16 e rs16 rd16 erd32 e #xx:32 erd32 erd32 e ers32 erd32 rd8 e #xx:8 e c rd8 rd8 e rs8 e c rd8 erd32 e 1 erd32 erd32 e 2 erd32 erd32 e 4 erd32 rd8 e 1 rd8 rd16 e 1 rd16 rd16 e 2 rd16 erd32 e 1 erd32 erd32 e 2 erd32 rd8 decimal adjust rd8 rd8 rs8 rd16 (unsigned multiplication) rd16 rs16 erd32 (unsigned multiplication) rd8 rs8 rd16 (signed multiplication) rd16 rs16 erd32 (signed multiplication) rd16 rs8 rd16 (rdh: remainder, rdl: quotient) (unsigned division) 2 2 2 2 4 2 6 2 2 2 2 2 2 2 2 2 2 2 2 14 22 16 24 14 ?? ? ?? ? ? ** ? ? ? (1) ? (1) ? (2) ? (2) ? (3) ? (3) ?????? ?????? ?????? ?? ? ?? ? ?? ? ?? ? ?? ? ? ** ? ?????? ? ????? ?? ?? ?? ?? ?? (6) (7) ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 627 mnemonic operation condition code operand size #xx rn @ern @(d, ern) @ ern/@ern+ @aa @(d, pc) @@aa addressing mode and instruction length (bytes) normal advanced no. of states* 1 ihnzvc divxu. w rs, erd divxs. b rs, rd divxs. w rs, erd cmp.b #xx:8, rd cmp.b rs, rd cmp.w #xx:16, rd cmp.w rs, rd cmp.l #xx:32, erd cmp.l ers, erd neg.b rd neg.w rd neg.l erd extu.w rd extu.l erd exts.w rd exts.l erd w b w b b w w l l b w l w l w l 2 4 4 2 2 4 2 6 2 2 2 2 2 2 2 2 erd32 rs16 erd32 (ed: remainder, rd: quotient) (unsigned division) rd16 rs8 rd16 (rdh: remainder, rdl: quotient) (signed division) erd32 rs16 erd32 (ed: remainder, rd: quotient) (signed division) rd8 e #xx:8 rd8 e rs8 rd16 e #xx:16 rd16 e rs16 erd32 e #xx:32 erd32 e ers32 0 e rd8 rd8 0 e rd16 rd16 0 e erd32 erd32 0 ( 628 3. logic instructions mnemonic operation condition code operand size #xx rn @ern @(d, ern) @ ern/@ern+ @aa @(d, pc) @@aa addressing mode and instruction length (bytes) normal advanced no. of states* 1 ihnzvc and.b #xx:8, rd and.b rs, rd and.w #xx:16, rd and.w rs, rd and.l #xx:32, erd and.l ers, erd or.b #xx:8, rd or.b rs, rd or.w #xx:16, rd or.w rs, rd or.l #xx:32, erd or.l ers, erd xor.b #xx:8, rd xor.b rs, rd xor.w #xx:16, rd xor.w rs, rd xor.l #xx:32, erd xor.l ers, erd not.b rd not.w rd not.l erd b b w w l l b b w w l l b b w w l l b w l 2 2 4 2 6 4 2 2 4 2 6 4 2 2 4 2 6 4 2 2 2 rd8 #xx:8 rd8 rd8 rs8 rd8 rd16 #xx:16 rd16 rd16 rs16 rd16 erd32 #xx:32 erd32 erd32 ers32 erd32 rd8 #xx:8 rd8 rd8 rs8 rd8 rd16 #xx:16 rd16 rd16 rs16 rd16 erd32 #xx:32 erd32 erd32 ers32 erd32 rd8 #xx:8 rd8 rd8 rs8 rd8 rd16 #xx:16 rd16 rd16 rs16 rd16 erd32 #xx:32 erd32 erd32 ers32 erd32 a rd8 rd8 a rd16 rd16 a rd32 rd32 2 2 4 2 6 4 2 2 4 2 6 4 2 2 4 2 6 4 2 2 2 ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ?? 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 629 4. shift instructions mnemonic operation condition code operand size #xx rn @ern @(d, ern) @ ern/@ern+ @aa @(d, pc) @@aa addressing mode and instruction length (bytes) normal advanced no. of states* 1 ihnzvc shal.b rd shal.w rd shal.l erd shar.b rd shar.w rd shar.l erd shll.b rd shll.w rd shll.l erd shlr.b rd shlr.w rd shlr.l erd rotxl.b rd rotxl.w rd rotxl.l erd rotxr.b rd rotxr.w rd rotxr.l erd rotl.b rd rotl.w rd rotl.l erd rotr.b rd rotr.w rd rotr.l erd b w l b w l b w l b w l b w l b w l b w l b w l 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ?? ?? ?? ?? 0 ?? 0 ?? 0 ?? 0 ?? 0 ?? 0 ?? 0 ?? 0 ?? 0 ?? 0 ?? 0 ?? 0 ?? 0 ?? 0 ?? 0 ?? 0 ?? 0 ?? 0 ?? 0 ?? 0 ?? 0 c msb lsb c msb lsb c msb lsb c msb lsb msb lsb 0 c msb lsb 0 c c msb lsb 0c msb lsb ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 630 5. bit manipulation instructions mnemonic operation condition code operand size #xx rn @ern @(d, ern) @ ern/@ern+ @aa @(d, pc) @@aa addressing mode and instruction length (bytes) normal advanced no. of states* 1 ihnzvc bset #xx:3, rd bset #xx:3, @erd bset #xx:3, @aa:8 bset rn, rd bset rn, @erd bset rn, @aa:8 bclr #xx:3, rd bclr #xx:3, @erd bclr #xx:3, @aa:8 bclr rn, rd bclr rn, @erd bclr rn, @aa:8 bnot #xx:3, rd bnot #xx:3, @erd bnot #xx:3, @aa:8 bnot rn, rd bnot rn, @erd bnot rn, @aa:8 btst #xx:3, rd btst #xx:3, @erd btst #xx:3, @aa:8 btst rn, rd btst rn, @erd btst rn, @aa:8 bld #xx:3, rd b b b b b b b b b b b b b b b b b b b b b b b b b 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 (#xx:3 of rd8) 1 (#xx:3 of @erd) 1 (#xx:3 of @aa:8) 1 (rn8 of rd8) 1 (rn8 of @erd) 1 (rn8 of @aa:8) 1 (#xx:3 of rd8) 0 (#xx:3 of @erd) 0 (#xx:3 of @aa:8) 0 (rn8 of rd8) 0 (rn8 of @erd) 0 (rn8 of @aa:8) 0 (#xx:3 of rd8) (#xx:3 of rd8) (#xx:3 of @erd) (#xx:3 of @erd) (#xx:3 of @aa:8) (#xx:3 of @aa:8) (rn8 of rd8) (rn8 of rd8) (rn8 of @erd) (rn8 of @erd) (rn8 of @aa:8) (rn8 of @aa:8) a (#xx:3 of rd8) z a (#xx:3 of @erd) z a (#xx:3 of @aa:8) z a (rn8 of @rd8) z a (rn8 of @erd) z a (rn8 of @aa:8) z (#xx:3 of rd8) c 2 8 8 2 8 8 2 8 8 2 8 8 2 8 8 2 8 8 2 6 6 2 6 6 2 ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ??? ?? ??? ?? ??? ?? ??? ?? ??? ?? ??? ?? ????? ? ? ? ? ? ? ? 631 mnemonic operation condition code operand size #xx rn @ern @(d, ern) @ ern/@ern+ @aa @(d, pc) @@aa addressing mode and instruction length (bytes) normal advanced no. of states* 1 ihnzvc bld #xx:3, @erd bld #xx:3, @aa:8 bild #xx:3, rd bild #xx:3, @erd bild #xx:3, @aa:8 bst #xx:3, rd bst #xx:3, @erd bst #xx:3, @aa:8 bist #xx:3, rd bist #xx:3, @erd bist #xx:3, @aa:8 band #xx:3, rd band #xx:3, @erd band #xx:3, @aa:8 biand #xx:3, rd biand #xx:3, @erd biand #xx:3, @aa:8 bor #xx:3, rd bor #xx:3, @erd bor #xx:3, @aa:8 bior #xx:3, rd bior #xx:3, @erd bior #xx:3, @aa:8 bxor #xx:3, rd bxor #xx:3, @erd bxor #xx:3, @aa:8 bixor #xx:3, rd bixor #xx:3, @erd bixor #xx:3, @aa:8 b b b b b b b b b b b b b b b b b b b b b b b b b b b b b 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 (#xx:3 of @erd) c (#xx:3 of @aa:8) c a (#xx:3 of rd8) c a (#xx:3 of @erd) c a (#xx:3 of @aa:8) c c (#xx:3 of rd8) c (#xx:3 of @erd24) c (#xx:3 of @aa:8) a c (#xx:3 of rd8) a c (#xx:3 of @erd24) a c (#xx:3 of @aa:8) c (#xx:3 of rd8) c c (#xx:3 of @erd24) c c (#xx:3 of @aa:8) c c (#xx:3 of rd8) c c (#xx:3 of @erd24) c c (#xx:3 of @aa:8) c c (#xx:3 of rd8) c c (#xx:3 of @erd24) c c (#xx:3 of @aa:8) c c (#xx:3 of rd8) c c (#xx:3 of @erd24) c c (#xx:3 of @aa:8) c c (#xx:3 of rd8) c c (#xx:3 of @erd24) c c (#xx:3 of @aa:8) c c (#xx:3 of rd8) c c (#xx:3 of @erd24) c c (#xx:3 of @aa:8) c 6 6 2 6 6 2 8 8 2 8 8 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 ????? ????? ????? ????? ????? ?????? ?????? ?????? ?????? ?????? ?????? ????? ????? ????? ????? ????? ????? ????? ????? ????? ????? ????? ????? ????? ????? ????? ????? ????? ????? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 632 6. branching instructions mnemonic operation branch condition condition code operand size #xx rn @ern @(d, ern) @ ern/@ern+ @aa @(d, pc) @@aa addressing mode and instruction length (bytes) normal advanced no. of states* 1 ihnzvc bra d:8 (bt d:8) bra d:16 (bt d:16) brn d:8 (bf d:8) brn d:16 (bf d:16) bhi d:8 bhi d:16 bls d:8 bls d:16 bcc d:8 (bhs d:8) bcc d:16 (bhs d:16) bcs d:8 (blo d:8) bcs d:16 (blo d:16) bne d:8 bne d:16 beq d:8 beq d:16 bvc d:8 bvc d:16 bvs d:8 bvs d:16 bpl d:8 bpl d:16 bmi d:8 bmi d:16 bge d:8 bge d:16 blt d:8 blt d:16 bgt d:8 bgt d:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 if condition is true then pc pc+d else next; 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? always never c z = 0 c z = 1 c = 0 c = 1 z = 0 z = 1 v = 0 v = 1 n = 0 n = 1 n v = 0 n v = 1 z (n v) = 0 633 mnemonic operation operation condition code operand size #xx rn @ern @(d, ern) @ ern/@ern+ @aa @(d, pc) @@aa addressing mode and instruction length (bytes) normal advanced no. of states* 1 ihnzvc ble d:8 ble d:16 jmp @ern jmp @aa:24 jmp @@aa:8 bsr d:8 bsr d:16 jsr @ern jsr @aa:24 jsr @@aa:8 ? ? ? ? ? ? ? ? ? ? ? 2 4 2 4 2 2 4 2 4 2 2 pc ern pc aa:24 pc @aa:8 pc @ e sp pc pc+d:8 pc @ e sp pc pc+d:16 pc @ e sp pc @ern pc @ e sp pc @aa:24 pc @ e sp pc @aa:8 pc @sp+ 4 6 4 6 8 6 8 6 8 8 8 10 8 10 8 10 12 10 ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? branch condition if condition is true then pc pc+d else next; z (n v) = 1 634 7. system control instructions mnemonic operation condition code operand size #xx rn @ern @(d, ern) @ ern/@ern+ @aa @(d, pc) @@aa addressing mode and instruction length (bytes) normal advanced no. of states* 1 ihnzvc trapa #x:2 rte sleep ldc #xx:8, ccr ldc rs, ccr ldc @ers, ccr ldc @(d:16, ers), ccr ldc @(d:24, ers), ccr ldc @ers+, ccr ldc @aa:16, ccr ldc @aa:24, ccr stc ccr, rd stc ccr, @erd stc ccr, @(d:16, erd) stc ccr, @(d:24, erd) stc ccr, @ e erd stc ccr, @aa:16 stc ccr, @aa:24 andc #xx:8, ccr orc #xx:8, ccr xorc #xx:8, ccr nop ? ? ? b b w w w w w w b w w w w w w b b b ? 2 2 2 4 6 10 4 6 8 2 4 6 10 4 6 8 2 2 2 2 pc @ e sp ccr @ e sp 635 8. block transfer instructions mnemonic operation condition code operand size #xx rn @ern @(d, ern) @ ern/@ern+ @aa @(d, pc) @@aa addressing mode and instruction length (bytes) normal advanced no. of states* 1 ihnzvc eepmov. b eepmov. w ? ? 4 4 if r4l 0 repeat @r5 @r6 r5+1 r5 r6+1 r6 r4l e 1 r4l until r4l=0 else next; if r4 0 repeat @r5 @r6 r5+1 r5 r6+1 r6 r4 e 1 r4 until r4l=0 else next; ?????? ?????? 8+4n* 2 8+4n* 2 notes: *1 the number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory. for other cases see section a.3, number of states required for execution. *2 n is the value set in register r4l or r4. (1) set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. (2) set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. (3) retains its previous value when the result is zero; otherwise cleared to 0. (4) set to 1 when the adjustment produces a carry; otherwise retains its previous value. (5) the number of states required for execution of an instruction that transfers data in synchronization with the e clock is variable. (6) set to 1 when the divisor is negative; otherwise cleared to 0. (7) set to 1 when the divisor is zero; otherwise cleared to 0. (8) set to 1 when the quotient is negative; otherwise cleared to 0. 636 a.2 operation code maps table a.2 operation code map (1) ah al 0123456789abcdef 0 1 2 3 4 5 6 7 8 9 a b c d e f nop bra mulxu bset brn divxu bnot stc bhi mulxu bclr ldc bls divxu btst orc or.b bcc rts or xorc xor.b bcs bsr xor bor bior bxor bixor band biand andc and.b bne rte and ldc bnq trapa bld bild bst bist bvc mov bpl jmp bmi addx subx bgt jsr ble mov add addx cmp subx or xor and mov instruction when most significant bit of bh is 0. instruction when most significant bit of bh is 1. instruction code: table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) bvs blt bge bsr table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (3) 1st byte 2nd byte ah bh al bl add sub mov cmp mov.b eepmov 637 table a.2 operation code map (2) ah al bh 0123456789abcdef 01 0a 0b 0f 10 11 12 13 17 1a 1b 1f 58 79 7a mov inc adds daa dec subs das bra mov mov bhi cmp cmp ldc/stc bcc or or bpl bgt instruction code: bvs sleep bvc bge table a.2 (3) table a.2 (3) table a.2 (3) bne and and inc extu dec beq inc extu dec bcs xor xor shll shlr rotxl rotxr not bls sub sub brn add add inc exts dec blt inc exts dec ble shal shar rotl rotr neg bmi 1st byte 2nd byte ah bh al bl subs adds add mov sub cmp shll shlr rotxl rotxr not shal shar rotl rotr neg 638 table a.2 operation code map (3) ah albh blch cl 0123456789abcdef 01406 01c05 01d05 01f06 7cr06 7cr07 7dr06 7dr07 7eaa6 7eaa7 7faa6 7faa7 mulxs bset bset bset bset divixs bnot bnot bnot bnot mulxs bclr bclr bclr bclr divxs btst btst btst btst or xor bor bior bxor bixor band biand and bld bild bst bist instruction when most significant bit of dh is 0. instruction when most significant bit of dh is 1. instruction code: * * * * * * * * 1 1 1 1 2 2 2 2 bor bior bxor bixor band biand bld bild bst bist notes: *1 r is the register designation field. *2 aa is the absolute address field. 1st byte 2nd byte ah bh al bl 3rd byte ch dh cl dl 4th byte ldc stc ldc ldc ldc stc stc stc 639 a.3 number of states required for execution the tables in this section can be used to calculate the number of states required for instruction execution by the h8/300h cpu. table a.4 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. table a.3 indicates the number of states required per cycle according to the bus size. the number of states required for execution of an instruction can be calculated from these two tables as follows: number of states = i s i + j s j + k s k + l s l + m s m + n s n examples of calculation of number of states required for execution examples: advanced mode, stack located in external address space, on-chip supporting modules accessed with 8-bit bus width, external devices accessed in three states with one wait state and 16-bit bus width. bset #0, @ffffc7:8 from table a.4, i = l = 2 and j = k = m = n = 0 from table a.3, s i = 4 and s l = 3 number of states = 2 4 + 2 3 = 14 jsr @@30 from table a.4, i = j = k = 2 and l = m = n = 0 from table a.3, s i = s j = s k = 4 number of states = 2 4 + 2 4 + 2 4 = 24 640 table a.3 number of states per cycle access conditions on-chip sup- external device porting module 8-bit bus 16-bit bus cycle on-chip memory 8-bit bus 16-bit bus 2-state access 3-state access 2-state access 3-state access instruction fetch s i 2 6346 + 2m23 + m branch address read s j stack operation s k byte data access s l 3 2 3 + m word data access s m 6 4 6 + 2m internal operation s n 1 legend m: number of wait states inserted into external device access 641 table a.4 number of cycles per instruction instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n add add.b #xx:8, rd add.b rs, rd add.w #xx:16, rd add.w rs, rd add.l #xx:32, erd add.l ers, erd 1 1 2 1 3 1 adds adds #1/2/4, erd 1 addx addx #xx:8, rd addx rs, rd 1 1 and and.b #xx:8, rd and.b rs, rd and.w #xx:16, rd and.w rs, rd and.l #xx:32, erd and.l ers, erd 1 1 2 1 3 2 andc andc #xx:8, ccr 1 band band #xx:3, rd band #xx:3, @erd band #xx:3, @aa:8 1 2 2 1 1 bcc bra d:8 (bt d:8) brn d:8 (bf d:8) bhi d:8 bls d:8 bcc d:8 (bhs d:8) bcs d:8 (blo d:8) bne d:8 beq d:8 bvc d:8 bvs d:8 bpl d:8 bmi d:8 bge d:8 blt d:8 bgt d:8 ble d:8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 642 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n bcc bra d:16 (bt d:16) brn d:16 (bf d:16) bhi d:16 bls d:16 bcc d:16 (bhs d:16) bcs d:16 (blo d:16) bne d:16 beq d:16 bvc d:16 bvs d:16 bpl d:16 bmi d:16 bge d:16 blt d:16 bgt d:16 ble d:16 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 bclr bclr #xx:3, rd bclr #xx:3, @erd bclr #xx:3, @aa:8 bclr rn, rd bclr rn, @erd bclr rn, @aa:8 1 2 2 1 2 2 2 2 2 2 biand biand #xx:3, rd biand #xx:3, @erd biand #xx:3, @aa:8 1 2 2 1 1 bild bild #xx:3, rd bild #xx:3, @erd bild #xx:3, @aa:8 1 2 2 1 1 bior bior #xx:8, rd bior #xx:8, @erd bior #xx:8, @aa:8 1 2 2 1 1 bist bist #xx:3, rd bist #xx:3, @erd bist #xx:3, @aa:8 1 2 2 2 2 bixor bixor #xx:3, rd bixor #xx:3, @erd bixor #xx:3, @aa:8 1 2 2 1 1 bld bld #xx:3, rd bld #xx:3, @erd bld #xx:3, @aa:8 1 2 2 1 1 643 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n bnot bnot #xx:3, rd bnot #xx:3, @erd bnot #xx:3, @aa:8 bnot rn, rd bnot rn, @erd bnot rn, @aa:8 1 2 2 1 2 2 2 2 2 2 bor bor #xx:3, rd bor #xx:3, @erd bor #xx:3, @aa:8 1 2 2 1 1 bset bset #xx:3, rd bset #xx:3, @erd bset #xx:3, @aa:8 bset rn, rd bset rn, @erd bset rn, @aa:8 1 2 2 1 2 2 2 2 2 2 bsr bsr d:8 normal 2 1 advanced 2 2 bsr d:16 normal 2 1 2 advanced 2 2 2 bst bst #xx:3, rd bst #xx:3, @erd bst #xx:3, @aa:8 1 2 2 2 2 btst btst #xx:3, rd btst #xx:3, @erd btst #xx:3, @aa:8 btst rn, rd btst rn, @erd btst rn, @aa:8 1 2 2 1 2 2 1 1 1 1 bxor bxor #xx:3, rd bxor #xx:3, @erd bxor #xx:3, @aa:8 1 2 2 1 1 cmp cmp.b #xx:8, rd cmp.b rs, rd cmp.w #xx:16, rd cmp.w rs, rd cmp.l #xx:32, erd cmp.l ers, erd 1 1 2 1 3 1 daa daa rd 1 das das rd 1 644 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n dec dec.b rd dec.w #1/2, rd dec.l #1/2, erd 1 1 1 divxs divxs.b rs, rd divxs.w rs, erd 2 2 12 20 divxu divxu.b rs, rd divxu.w rs, erd 1 1 12 20 eepmov eepmov.b eepmov.w 2 2 2n + 2* 1 2n + 2* 1 exts exts.w rd exts.l erd 1 1 extu extu.w rd extu.l erd 1 1 inc inc.b rd inc.w #1/2, rd inc.l #1/2, erd 1 1 1 jmp jmp @ern 2 jmp @aa:24 2 2 jmp @@aa:8 normal 2 1 2 advanced 2 2 2 jsr jsr @ern normal 2 1 advanced 2 2 jsr @aa:24 normal 2 1 2 advanced 2 2 2 jsr @@aa:8 normal 2 1 1 advanced 2 2 2 ldc ldc #xx:8, ccr ldc rs, ccr ldc @ers, ccr ldc @(d:16, ers), ccr ldc @(d:24, ers), ccr ldc @ers+, ccr ldc @aa:16, ccr ldc @aa:24, ccr 1 1 2 3 5 2 3 4 1 1 1 1 1 1 2 645 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n mov mov.b #xx:8, rd mov.b rs, rd mov.b @ers, rd mov.b @(d:16, ers), rd mov.b @(d:24, ers), rd mov.b @ers+, rd mov.b @aa:8, rd mov.b @aa:16, rd mov.b @aa:24, rd mov.b rs, @erd mov.b rs, @(d:16, erd) mov.b rs, @(d:24, erd) mov.b rs, @ e erd mov.b rs, @aa:8 mov.b rs, @aa:16 mov.b rs, @aa:24 mov.w #xx:16, rd mov.w rs, rd mov.w @ers, rd mov.w @(d:16, ers), rd mov.w @(d:24, ers), rd mov.w @ers+, rd mov.w @aa:16, rd mov.w @aa:24, rd mov.w rs, @erd mov.w rs, @(d:16, erd) mov.w rs, @(d:24, erd) mov.w rs, @ e erd mov.w rs, @aa:16 mov.w rs, @aa:24 1 1 1 2 4 1 1 2 3 1 2 4 1 1 2 3 2 1 1 2 4 1 2 3 1 2 4 1 2 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 mov.l #xx:32, erd mov.l ers, erd mov.l @ers, erd m ov.l @( d:16, ers) , er d m ov.l @( d:24, ers) , er d mov.l @ers+, erd mov.l @aa:16, erd mov.l @aa:24, erd mov.l ers, @erd m ov.l er s, @( d:16, er d) m ov.l er s, @( d:24, er d) mov.l ers, @ e erd mov.l ers, @aa:16 mov.l ers, @aa:24 3 1 2 3 5 2 3 4 2 3 5 2 3 4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 646 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n movfpe movfpe @aa:16, rd* 2 21 movtpe movtpe rs, @aa:16* 2 21 mulxs mulxs.b rs, rd mulxs.w rs, erd 2 2 12 20 mulxu mulxu.b rs, rd mulxu.w rs, erd 1 1 12 20 neg neg.b rd neg.w rd neg.l erd 1 1 1 nop nop 1 not not.b rd not.w rd not.l erd 1 1 1 or or.b #xx:8, rd or.b rs, rd or.w #xx:16, rd or.w rs, rd or.l #xx:32, erd or.l ers, erd 1 1 2 1 3 2 orc orc #xx:8, ccr 1 pop pop.w rn pop.l ern 1 2 1 2 2 2 push push.w rn push.l ern 1 2 1 2 2 2 rotl rotl.b rd rotl.w rd rotl.l erd 1 1 1 rotr rotr.b rd rotr.w rd rotr.l erd 1 1 1 rotxl rotxl.b rd rotxl.w rd rotxl.l erd 1 1 1 rotxr rotxr.b rd rotxr.w rd rotxr.l erd 1 1 1 rte rte 2 2 2 647 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n rts rts normal 2 1 2 advanced 2 2 2 shal shal.b rd shal.w rd shal.l erd 1 1 1 shar shar.b rd shar.w rd shar.l erd 1 1 1 shll shll.b rd shll.w rd shll.l erd 1 1 1 shlr shlr.b rd shlr.w rd shlr.l erd 1 1 1 sleep sleep 1 stc stc ccr, rd stc ccr, @erd st c c cr , @( d:16, er d) st c c cr , @( d:24, er d) stc ccr, @ e erd stc ccr, @aa:16 stc ccr, @aa:24 1 2 3 5 2 3 4 1 1 1 1 1 1 2 sub sub.b rs, rd sub.w #xx:16, rd sub.w rs, rd sub.l #xx:32, erd sub.l ers, erd 1 2 1 3 1 subs subs #1/2/4, erd 1 subx subx #xx:8, rd subx rs, rd 1 1 trapa trapa #x:2 normal 2 1 2 4 advanced 2 2 2 4 xor xor.b #xx:8, rd xor.b rs, rd xor.w #xx:16, rd xor.w rs, rd xor.l #xx:32, erd xor.l ers, erd 1 1 2 1 3 2 xorc xorc #xx:8, ccr 1 notes: *1 n is the value set in register r4l or r4. the source and destination are accessed n + 1 times each. *2 not available in the h8/3024 series. 648 appendix b internal i/o registers table b.1 comparison of h8/3024 series internal i/o register specifications address (low) h8/3024 mask rom, h8/3026 mask rom h8/3026f-ztat version h8/3024f-ztat version module h'ee01e adrcr adrcr adrcr bus controller h'ee030 ? flmcr1 flmcr1 flash memory h'ee031 ? flmcr2 flmcr2 h'ee032 ? ebr1 ebr h'ee033 ? ebr2 h'ee077 ? ramcr ramcr h'ee07d ? notes: 1. a dash (?) indicates that an access will always return 1s, and writes are invalid. 2. shading indicates that access is prohibited. normal operation is not guaranteed if these addresses are accessed. 649 b.1 address list (h8/3026f-ztat, h8/3026 mask rom version) data bit names address (low) register name bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'ee000 p1ddr 8 p1 7 ddr p1 6 ddr p1 5 ddr p1 4 ddr p1 3 ddr p1 2 ddr p1 1 ddr p1 0 ddr port 1 h'ee001 p2ddr 8 p2 7 ddr p2 6 ddr p2 5 ddr p2 4 ddr p2 3 ddr p2 2 ddr p2 1 ddr p2 0 ddr port 2 h'ee002 p3ddr 8 p3 7 ddr p3 6 ddr p3 5 ddr p3 4 ddr p3 3 ddr p3 2 ddr p3 1 ddr p3 0 ddr port 3 h'ee003 p4ddr 8 p4 7 ddr p4 6 ddr p4 5 ddr p4 4 ddr p4 3 ddr p4 2 ddr p4 1 ddr p4 0 ddr port 4 h'ee004 p5ddr 8 ????p5 3 ddr p5 2 ddr p5 1 ddr p5 0 ddr port 5 h'ee005 p6ddr 8 ? p6 6 ddr p6 5 ddr p6 4 ddr p6 3 ddr p6 2 ddr p6 1 ddr p6 0 ddr port 6 h'ee006 ? ???????? h'ee007 p8ddr 8 ???p8 4 ddr p8 3 ddr p8 2 ddr p8 1 ddr p8 0 ddr port 8 h'ee008 p9ddr 8 ? ? p9 5 ddr p9 4 ddr p9 3 ddr p9 2 ddr p9 1 ddr p9 0 ddr port 9 h'ee009 paddr 8 pa 7 ddr pa 6 ddr pa 5 ddr pa 4 ddr pa 3 ddr pa 2 ddr pa 1 ddr pa 0 ddr port a h'ee00a pbddr 8 pb 7 ddr pb 6 ddr pb 5 ddr pb 4 ddr pb 3 ddr pb 2 ddr pb 1 ddr pb 0 ddr port b h'ee00b ? ???????? h'ee00c ? ???????? h'ee00d ? ???????? h'ee00e ? ???????? h'ee00f ? ???????? h'ee010 ? ???????? h'ee011 mdcr 8 ????? mds2 mds1 mds0 system control h'ee012 syscr 8 ssby sts2 sts1 sts0 ue nmieg ssoe rame h'ee013 brcr 8 a23e a22e a21e a20e ? ? ? brle bus controller h'ee014 iscr 8 ? ? irq5sc irq4sc irq3sc irq2sc irq1sc irq0sc interrupt h'ee015 ier 8 ? ? irq5e irq4e irq3e irq2e irq1e irq0e controller h'ee016 isr 8 ? ? irq5f irq4f irq3f irq2f irq1f irq0f h'ee017 ? ???????? h'ee018 ipra 8 ipra7 ipra6 ipra5 ipra4 ipra3 ipra2 ipra1 ipra0 h'ee019 iprb 8 iprb7 iprb6 ? ? iprb3 iprb2 ? ? h'ee01a dastcr 8 ??????? daste d/a converter h'ee01b divcr 8 ?????? div1 div0 system control h'ee01c mstcrh 8 pstop ????? mstph1 mstph0 h'ee01d mstcrl 8 ? ? ? mstpl4 mstpl3 mstpl2 ? mstpl0 h'ee01e adrcr 8 ??????? adrctl bus controller h'ee01f cscr 8 cs7e cs6e cs5e cs4e ???? 650 data bit names address (low) register name bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'ee020 abwcr 8 abw7 abw6 abw5 abw4 abw3 abw2 abw1 abw0 bus controller h'ee021 astcr 8 ast7 ast6 ast5 ast4 ast3 ast2 ast1 ast0 h'ee022 wcrh 8 w71 w70 w61 w60 w51 w50 w41 w40 h'ee023 wcrl 8 w31 w30 w21 w20 w11 w10 w01 w00 h'ee024 bcr 8 icis1 icis0 ?* 2 ?* 2 ?* 2 ? rdea waite h'ee025 ? ???????? h'ee026 reserved area (access prohibited) h'ee027 h'ee028 h'ee029 h'ee02a h'ee02b h'ee02c h'ee02d h'ee02e h'ee02f h'ee030 flmcr1* 5 8 fwe swe esu psu ev pv e p flash memory h'ee031 flmcr2* 5 8 fler ?* 1 ?* 1 ?* 1 ?* 1 ?* 1 ?* 1 ?* 1 h'ee032 ebr1* 5 8 eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 h'ee033 ebr2* 5 8???? eb11 eb10 eb9 eb8 h'ee034 ? ???????? h'ee035 ? ???????? h'ee036 ? ???????? h'ee037 ? ???????? h'ee038 reserved area (access prohibited) h'ee039 h'ee03a h'ee03b h'ee03c p2pcr 8 p2 7 pcr p2 6 pcr p2 5 pcr p2 4 pcr p2 3 pcr p2 2 pcr p2 1 pcr p2 0 pcr port 2 h'ee03d ? ???????? h'ee03e p4pcr 8 p4 7 pcr p4 6 pcr p4 5 pcr p4 4 pcr p4 3 pcr p4 2 pcr p4 1 pcr p4 0 pcr port 4 h'ee03f p5pcr 8 ????p5 3 pcr p5 2 pcr p5 1 pcr p5 0 pcr port 5 h'ee040 ? ???????? h'ee041 ? ???????? h'ee042 ? ???????? h'ee043 ? ???????? 651 data bit names address (low) register name bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'ee044 ? ???????? h'ee045 ? ???????? h'ee046 ? ???????? h'ee047 ? ???????? h'ee048 ? ???????? h'ee049 ? ???????? h'ee04a ? ???????? h'ee04b ? ???????? h'ee04c ? ???????? h'ee04d ? ???????? h'ee04e ? ???????? h'ee04f ? ???????? h'ee050 ? ???????? h'ee051 ? ???????? h'ee052 ? ???????? h'ee053 ? ???????? h'ee054 ? ???????? h'ee055 ? ???????? h'ee056 ? ???????? h'ee057 ? ???????? h'ee058 ? ???????? h'ee059 ? ???????? h'ee05a ? ???????? h'ee05b ? ???????? h'ee05c ? ???????? h'ee05d ? ???????? h'ee05e ? ???????? h'ee05f ? ???????? h'ee060 ? ???????? h'ee061 ? ???????? h'ee062 ? ???????? h'ee063 ? ???????? h'ee064 ? ???????? h'ee065 ? ???????? h'ee066 ? ???????? h'ee067 ? ???????? 652 data bit names address (low) register name bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'ee068 ? ???????? h'ee069 ? ???????? h'ee06a ? ???????? h'ee06b ? ???????? h'ee06c ? ???????? h'ee06d ? ???????? h'ee06e ? ???????? h'ee06f ? ???????? h'ee070 ? ???????? h'ee071 ? ???????? h'ee072 ? ???????? h'ee073 ? ???????? h'ee074 reserved area (access prohibited) h'ee075 h'ee076 h'ee077 ramcr* 5 8???? rams ram2 ram1 ram0 flash memory h'ee078 reserved area (access prohibited) h'ee079 h'ee07a h'ee07b h'ee07c h'ee07d h'ee07e h'ee07f h'ee080 h'ee081 h'fff20 h'fff21 h'fff22 h'fff23 h'fff24 h'fff25 h'fff26 h'fff27 h'fff28 h'fff29 653 data bit names address (low) register name bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'fff2a reserved area (access prohibited) h'fff2b h'fff2c h'fff2d h'fff2e h'fff2f h'fff30 h'fff31 h'fff32 h'fff33 h'fff34 h'fff35 h'fff36 h'fff37 h'fff38 h'fff39 h'fff3a h'fff3b h'fff3c h'fff3d h'fff3e h'fff3f h'fff40 ? ???????? h'fff41 ? ???????? h'fff42 ? ???????? h'fff43 ? ???????? h'fff44 ? ???????? h'fff45 ? ???????? h'fff46 ? ???????? h'fff47 ? ???????? h'fff48 ? ???????? h'fff49 ? ???????? h'fff4a ? ???????? h'fff4b ? ???????? h'fff4c ? ???????? h'fff4d ? ???????? 654 data bit names address (low) register name bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'fff4e ? ???????? h'fff4f ? ???????? h'fff50 ? ???????? h'fff51 ? ???????? h'fff52 ? ???????? h'fff53 ? ???????? h'fff54 ? ???????? h'fff55 ? ???????? h'fff56 ? ???????? h'fff57 ? ???????? h'fff58 ? ???????? h'fff59 ? ???????? h'fff5a ? ???????? h'fff5b ? ???????? h'fff5c ? ???????? h'fff5d ? ???????? h'fff5e ? ???????? h'fff5f ? ???????? h'fff60 tstr 8 ????? str2 str1 str0 16-bit timer, h'fff61 tsnc 8 ????? sync2 sync1 sync0 (all channels) h'fff62 tmdr 8 ? mdf fdir ? ? pwm2 pwm1 pwm0 h'fff63 tolr 8 ? ? tob2 toa2 tob1 toa1 tob0 toa0 h'fff64 tisra 8 ? imiea2 imiea1 imiea0 ? imfa2 imfa1 imfa0 h'fff65 tisrb 8 ? imieb2 imieb1 imieb0 ? imfb2 imfb1 imfb0 h'fff66 tisrc 8 ? ovie2 ovie1 ovie0 ? ovf2 ovf1 ovf0 h'fff67 h'fff68 16tcr0 8 ? cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 16-bit timer h'fff69 tior0 8 ? iob2 iob1 iob0 ? ioa2 ioa1 ioa0 channel 0 h'fff6a 16tcnt0h 16 h'fff6b 16tcnt0l h'fff6c gra0h 16 h'fff6d gra0l h'fff6e grb0h 16 h'fff6f grb0l 655 data bit names address (low) register name bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'fff70 16tcr1 8 ? cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 16-bit timer h'fff71 tior1 8 ? iob2 iob1 iob0 ? ioa2 ioa1 ioa0 channel 1 h'fff72 16tcnt1h 16 h'fff73 16tcnt1l h'fff74 gra1h 16 h'fff75 gra1l h'fff76 grb1h 16 h'fff77 grb1l h'fff78 16tcr2 8 ? cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 16-bit timer h'fff79 tior2 8 ? iob2 iob1 iob0 ? ioa2 ioa1 ioa0 channel 2 h'fff7a 16tcnt2h 16 h'fff7b 16tcnt2l h'fff7c gra2h 16 h'fff7d gra2l h'fff7e grb2h 16 h'fff7f grb2l h'fff80 8tcr0 8 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 8-bit timer h'fff81 8tcr1 8 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 channels 0 and 1 h'fff82 8tcsr0 8 cmfb cmfa ovf adte ois3 ois2 os1 os0 h'fff83 8tcsr1 8 cmfb cmfa ovf ice ois3 ois2 os1 os0 h'fff84 tcora0 8 h'fff85 tcora1 8 h'fff86 tcorb0 8 h'fff87 tcorb1 8 h'fff88 8tcnt0 8 h'fff89 8tcnt1 8 h'fff8a ? ???????? h'fff8b ? ???????? h'fff8c tcsr* 3 8 ovf wt/ it tme ? ? cks2 cks1 cks0 wdt h'fff8d tcnt* 3 8 h'fff8e ? ???????? h'fff8f rstcsr* 3 8 wrst ??????? 656 data bit names address (low) register name bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'fff90 8tcr2 8 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 8-bit timer h'fff91 8tcr3 8 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 channels 2 and 3 h'fff92 8tcsr2 8 cmfb cmfa ovf ? ois3 ois2 os1 os0 h'fff93 8tcsr3 8 cmfb cmfa ovf ice ois3 ois2 os1 os0 h'fff94 tcora2 8 h'fff95 tcora3 8 h'fff96 tcorb2 8 h'fff97 tcorb3 8 h'fff98 8tcnt2 8 h'fff99 8tcnt3 8 h'fff9a ? ???????? h'fff9b ? ???????? h'fff9c dadr0 8 d/a converter h'fff9d dadr1 8 h'fff9e dacr 8 daoe1 daoe0 dae ????? h'fff9f reserved area (access prohibited) h'fffa0 tpmr 8 ???? g3nov g2nov g1nov g0nov tpc h'fffa1 tpcr 8 g3cms1 g3cms0 g2cms1 g2cms0 g1cms1 g1cms0 g0cms1 g0cms0 h'fffa2 nderb 8 nder15 nder14 nder13 nder12 nder11 nder10 nder9 nder8 h'fffa3 ndera 8 nder7 nder6 nder5 nder4 nder3 nder2 nder1 nder0 h'fffa4 ndrb* 4 8 ndr15 ndr14 ndr13 ndr12 ndr11 ndr10 ndr9 ndr8 ndr15 ndr14 ndr13 ndr12 ???? h'fffa5 ndra* 4 8 ndr7 ndr6 ndr5 ndr4 ndr3 ndr2 ndr1 ndr0 ndr7 ndr6 ndr5 ndr4 ???? h'fffa6 ndrb* 4 8???????? ???? ndr11 ndr10 ndr9 ndr8 h'fffa7 ndra* 4 8???????? ???? ndr3 ndr2 ndr1 ndr0 h'fffa8 ? ???????? h'fffa9 ? ???????? h'fffaa ? ???????? h'fffab ? ???????? h'fffac ? ???????? h'fffad ? ???????? h'fffae ? ???????? h'fffaf ? ???????? 657 data bit names address (low) register name bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'fffb0 smr 8 c/ a chr pe o/ e stop mp cks1 cks0 sci channel 0 h'fffb1 brr 8 h'fffb2 scr 8 tie rie te re mpie teie cke1 cke0 h'fffb3 tdr 8 h'fffb4 ssr 8 tdre rdrf orer fer/ ers per tend mpb mpbt h'fffb5 rdr 8 h'fffb6 scmr 8 ???? sdir sinv ? smif h'fffb7 reserved area (access prohibited) h'fffb8 smr 8 c/ a chr pe o/ e stop mp cks1 cks0 sci channel 1 h'fffb9 brr 8 h'fffba scr 8 tie rie te re mpie teie cke1 cke0 h'fffbb tdr 8 h'fffbc ssr 8 tdre rdrf orer fer/ ers per tend mpb mpbt h'fffbd rdr 8 h'fffbe scmr 8 ???? sdir sinv ? smif h'fffbf reserved area (access prohibited) h'fffc0 reserved area (access prohibited) h'fffc1 h'fffc2 h'fffc3 h'fffc4 h'fffc5 h'fffc6 h'fffc7 h'fffc8 ? ???????? h'fffc9 ? ???????? h'fffca ? ???????? h'fffcb ? ???????? h'fffcc ? ???????? h'fffcd ? ???????? h'fffce ? ???????? h'fffcf ? ???????? h'fffd0 p1dr 8 p1 7 p1 6 p1 5 p1 4 p1 3 p1 2 p1 1 p1 0 port 1 h'fffd1 p2dr 8 p2 7 p2 6 p2 5 p2 4 p2 3 p2 2 p2 1 p2 0 port 2 h'fffd2 p3dr 8 p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 port 3 658 data bit names address (low) register name bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'fffd3 p4dr 8 p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 p4 0 port 4 h'fffd4 p5dr 8 ????p5 3 p5 2 p5 1 p5 0 port 5 h'fffd5 p6dr 8 p6 7 p6 6 p6 5 p6 4 p6 3 p6 2 p6 1 p6 0 port 6 h'fffd6 p7dr 8 p7 7 p7 6 p7 5 p7 4 p7 3 p7 2 p7 1 p7 0 port 7 h'fffd7 p8dr 8 ???p8 4 p8 3 p8 2 p8 1 p8 0 port 8 h'fffd8 p9dr 8 ? ? p9 5 p9 4 p9 3 p9 2 p9 1 p9 0 port 9 h'fffd9 padr 8 pa 7 pa 6 pa 5 pa 4 pa 3 pa 2 pa 1 pa 0 port a h'fffda pbdr 8 pb 7 pb 6 pb 5 pb 4 pb 3 pb 2 pb 1 pb 0 port b h'fffdb ? ???????? h'fffdc ? ???????? h'fffdd ? ???????? h'fffde ? ???????? h'fffdf ? ???????? h'fffe0 addrah 8 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 a/d converter h'fffe1 addral 8 ad1 ad0 ?????? h'fffe2 addrbh 8 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'fffe3 addrbl 8 ad1 ad0 ?????? h'fffe4 addrch 8 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'fffe5 addrcl 8 ad1 ad0 ?????? h'fffe6 addrdh 8 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'fffe7 addrdl 8 ad1 ad0 ?????? h'fffe8 adcsr 8 adf adie adst scan cks ch2 ch1 ch0 h'fffe9 adcr 8 trge ??????? notes: *1 writing to bits 6 to 0 of flmcr2 is prohibited. *2 writing to bits 5 to 3 of bcr is prohibited. *3 for the procedure for writing to tcsr, tcnt, and rstcsr, see section 11.2.4, notes on register access. *4 the address depends on the output trigger setting. *5 use byte access on flmcr1, flmcr2, ebr1, ebr2, and ramcr. these registers are not available in a mask rom version. legend: wdt: watchdog timer tpc: programmable timing pattern controller sci: serial communication interface 659 b.2 address list (h8/3024f-ztat, h8/3024 mask rom version) data bit names address (low) register name bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'ee000 p1ddr 8 p1 7 ddr p1 6 ddr p1 5 ddr p1 4 ddr p1 3 ddr p1 2 ddr p1 1 ddr p1 0 ddr port 1 h'ee001 p2ddr 8 p2 7 ddr p2 6 ddr p2 5 ddr p2 4 ddr p2 3 ddr p2 2 ddr p2 1 ddr p2 0 ddr port 2 h'ee002 p3ddr 8 p3 7 ddr p3 6 ddr p3 5 ddr p3 4 ddr p3 3 ddr p3 2 ddr p3 1 ddr p3 0 ddr port 3 h'ee003 p4ddr 8 p4 7 ddr p4 6 ddr p4 5 ddr p4 4 ddr p4 3 ddr p4 2 ddr p4 1 ddr p4 0 ddr port 4 h'ee004 p5ddr 8 ????p5 3 ddr p5 2 ddr p5 1 ddr p5 0 ddr port 5 h'ee005 p6ddr 8 ? p6 6 ddr p6 5 ddr p6 4 ddr p6 3 ddr p6 2 ddr p6 1 ddr p6 0 ddr port 6 h'ee006 ? ???????? h'ee007 p8ddr 8 ???p8 4 ddr p8 3 ddr p8 2 ddr p8 1 ddr p8 0 ddr port 8 h'ee008 p9ddr 8 ? ? p9 5 ddr p9 4 ddr p9 3 ddr p9 2 ddr p9 1 ddr p9 0 ddr port 9 h'ee009 paddr 8 pa 7 ddr pa 6 ddr pa 5 ddr pa 4 ddr pa 3 ddr pa 2 ddr pa 1 ddr pa 0 ddr port a h'ee00a pbddr 8 pb 7 ddr pb 6 ddr pb 5 ddr pb 4 ddr pb 3 ddr pb 2 ddr pb 1 ddr pb 0 ddr port b h'ee00b ? ???????? h'ee00c ? ???????? h'ee00d ? ???????? h'ee00e ? ???????? h'ee00f ? ???????? h'ee010 ? ???????? h'ee011 mdcr 8 ????? mds2 mds1 mds0 system control h'ee012 syscr 8 ssby sts2 sts1 sts0 ue nmieg ssoe rame h'ee013 brcr 8 a23e a22e a21e a20e ? ? ? brle bus controller h'ee014 iscr 8 ? ? irq5sc irq4sc irq3sc irq2sc irq1sc irq0sc interrupt h'ee015 ier 8 ? ? irq5e irq4e irq3e irq2e irq1e irq0e controller h'ee016 isr 8 ? ? irq5f irq4f irq3f irq2f irq1f irq0f h'ee017 ? ???????? h'ee018 ipra 8 ipra7 ipra6 ipra5 ipra4 ipra3 ipra2 ipra1 ipra0 h'ee019 iprb 8 iprb7 iprb6 ? ? iprb3 iprb2 ? ? h'ee01a dastcr 8 ??????? daste d/a converter h'ee01b divcr 8 ?????? div1 div0 system control h'ee01c mstcrh 8 pstop ????? mstph1 mstph0 h'ee01d mstcrl 8 ? ? ? mstpl4 mstpl3 mstpl2 ? mstpl0 h'ee01e adrcr 8 ??????? adrctl bus controller h'ee01f cscr 8 cs7e cs6e cs5e cs4e ???? 660 data bit names address (low) register name bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'ee020 abwcr 8 abw7 abw6 abw5 abw4 abw3 abw2 abw1 abw0 bus controller h'ee021 astcr 8 ast7 ast6 ast5 ast4 ast3 ast2 ast1 ast0 h'ee022 wcrh 8 w71 w70 w61 w60 w51 w50 w41 w40 h'ee023 wcrl 8 w31 w30 w21 w20 w11 w10 w01 w00 h'ee024 bcr 8 icis1 icis0 ?* 2 ?* 2 ?* 2 ? rdea waite h'ee025 ? ???????? h'ee026 reserved area (access prohibited) h'ee027 h'ee028 h'ee029 h'ee02a h'ee02b h'ee02c h'ee02d h'ee02e h'ee02f h'ee030 flmcr1* 5 8 fwe swe esu psu ev pv e p flash memory h'ee031 flmcr2* 5 8 fler ?* 1 ?* 1 ?* 1 ?* 1 ?* 1 ?* 1 ?* 1 h'ee032 ebr* 5 8 eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 h'ee033 reserved area (access prohibited) h'ee034 ? ???????? h'ee035 ? ???????? h'ee036 ? ???????? h'ee037 ? ???????? h'ee038 reserved area (access prohibited) h'ee039 h'ee03a h'ee03b h'ee03c p2pcr 8 p2 7 pcr p2 6 pcr p2 5 pcr p2 4 pcr p2 3 pcr p2 2 pcr p2 1 pcr p2 0 pcr port 2 h'ee03d ? ???????? h'ee03e p4pcr 8 p4 7 pcr p4 6 pcr p4 5 pcr p4 4 pcr p4 3 pcr p4 2 pcr p4 1 pcr p4 0 pcr port 4 h'ee03f p5pcr 8 ????p5 3 pcr p5 2 pcr p5 1 pcr p5 0 pcr port 5 h'ee040 ? ???????? h'ee041 ? ???????? h'ee042 ? ???????? h'ee043 ? ???????? 661 data bit names address (low) register name bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'ee044 ? ???????? h'ee045 ? ???????? h'ee046 ? ???????? h'ee047 ? ???????? h'ee048 ? ???????? h'ee049 ? ???????? h'ee04a ? ???????? h'ee04b ? ???????? h'ee04c ? ???????? h'ee04d ? ???????? h'ee04e ? ???????? h'ee04f ? ???????? h'ee050 ? ???????? h'ee051 ? ???????? h'ee052 ? ???????? h'ee053 ? ???????? h'ee054 ? ???????? h'ee055 ? ???????? h'ee056 ? ???????? h'ee057 ? ???????? h'ee058 ? ???????? h'ee059 ? ???????? h'ee05a ? ???????? h'ee05b ? ???????? h'ee05c ? ???????? h'ee05d ? ???????? h'ee05e ? ???????? h'ee05f ? ???????? h'ee060 ? ???????? h'ee061 ? ???????? h'ee062 ? ???????? h'ee063 ? ???????? h'ee064 ? ???????? h'ee065 ? ???????? h'ee066 ? ???????? h'ee067 ? ???????? 662 data bit names address (low) register name bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'ee068 ? ???????? h'ee069 ? ???????? h'ee06a ? ???????? h'ee06b ? ???????? h'ee06c ? ???????? h'ee06d ? ???????? h'ee06e ? ???????? h'ee06f ? ???????? h'ee070 ? ???????? h'ee071 ? ???????? h'ee072 ? ???????? h'ee073 ? ???????? h'ee074 reserved area (access prohibited) h'ee075 h'ee076 h'ee077 ramcr* 5 8???? rams ram2 ram1 ram0 flash memory h'ee078 reserved area (access prohibited) h'ee079 h'ee07a h'ee07b h'ee07c h'ee07d h'ee07e h'ee07f h'ee080 h'ee081 h'fff20 h'fff21 h'fff22 h'fff23 h'fff24 h'fff25 h'fff26 h'fff27 h'fff28 h'fff29 663 data bit names address (low) register name bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'fff2a reserved area (access prohibited) h'fff2b h'fff2c h'fff2d h'fff2e h'fff2f h'fff30 h'fff31 h'fff32 h'fff33 h'fff34 h'fff35 h'fff36 h'fff37 h'fff38 h'fff39 h'fff3a h'fff3b h'fff3c h'fff3d h'fff3e h'fff3f h'fff40 ? ???????? h'fff41 ? ???????? h'fff42 ? ???????? h'fff43 ? ???????? h'fff44 ? ???????? h'fff45 ? ???????? h'fff46 ? ???????? h'fff47 ? ???????? h'fff48 ? ???????? h'fff49 ? ???????? h'fff4a ? ???????? h'fff4b ? ???????? h'fff4c ? ???????? h'fff4d ? ???????? 664 data bit names address (low) register name bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'fff4e ? ???????? h'fff4f ? ???????? h'fff50 ? ???????? h'fff51 ? ???????? h'fff52 ? ???????? h'fff53 ? ???????? h'fff54 ? ???????? h'fff55 ? ???????? h'fff56 ? ???????? h'fff57 ? ???????? h'fff58 ? ???????? h'fff59 ? ???????? h'fff5a ? ???????? h'fff5b ? ???????? h'fff5c ? ???????? h'fff5d ? ???????? h'fff5e ? ???????? h'fff5f ? ???????? h'fff60 tstr 8 ????? str2 str1 str0 16-bit timer, h'fff61 tsnc 8 ????? sync2 sync1 sync0 (all channels) h'fff62 tmdr 8 ? mdf fdir ? ? pwm2 pwm1 pwm0 h'fff63 tolr 8 ? ? tob2 toa2 tob1 toa1 tob0 toa0 h'fff64 tisra 8 ? imiea2 imiea1 imiea0 ? imfa2 imfa1 imfa0 h'fff65 tisrb 8 ? imieb2 imieb1 imieb0 ? imfb2 imfb1 imfb0 h'fff66 tisrc 8 ? ovie2 ovie1 ovie0 ? ovf2 ovf1 ovf0 h'fff67 h'fff68 16tcr0 8 ? cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 16-bit timer h'fff69 tior0 8 ? iob2 iob1 iob0 ? ioa2 ioa1 ioa0 channel 0 h'fff6a 16tcnt0h 16 h'fff6b 16tcnt0l h'fff6c gra0h 16 h'fff6d gra0l h'fff6e grb0h 16 h'fff6f grb0l 665 data bit names address (low) register name bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'fff70 16tcr1 8 ? cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 16-bit timer h'fff71 tior1 8 ? iob2 iob1 iob0 ? ioa2 ioa1 ioa0 channel 1 h'fff72 16tcnt1h 16 h'fff73 16tcnt1l h'fff74 gra1h 16 h'fff75 gra1l h'fff76 grb1h 16 h'fff77 grb1l h'fff78 16tcr2 8 ? cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 16-bit timer h'fff79 tior2 8 ? iob2 iob1 iob0 ? ioa2 ioa1 ioa0 channel 2 h'fff7a 16tcnt2h 16 h'fff7b 16tcnt2l h'fff7c gra2h 16 h'fff7d gra2l h'fff7e grb2h 16 h'fff7f grb2l h'fff80 8tcr0 8 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 8-bit timer h'fff81 8tcr1 8 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 channels 0 and 1 h'fff82 8tcsr0 8 cmfb cmfa ovf adte ois3 ois2 os1 os0 h'fff83 8tcsr1 8 cmfb cmfa ovf ice ois3 ois2 os1 os0 h'fff84 tcora0 8 h'fff85 tcora1 8 h'fff86 tcorb0 8 h'fff87 tcorb1 8 h'fff88 8tcnt0 8 h'fff89 8tcnt1 8 h'fff8a ? ???????? h'fff8b ? ???????? h'fff8c tcsr* 3 8 ovf wt/ it tme ? ? cks2 cks1 cks0 wdt h'fff8d tcnt* 3 8 h'fff8e ? ???????? h'fff8f rstcsr* 3 8 wrst ??????? 666 data bit names address (low) register name bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'fff90 8tcr2 8 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 8-bit timer h'fff91 8tcr3 8 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 channels 2 and 3 h'fff92 8tcsr2 8 cmfb cmfa ovf ? ois3 ois2 os1 os0 h'fff93 8tcsr3 8 cmfb cmfa ovf ice ois3 ois2 os1 os0 h'fff94 tcora2 8 h'fff95 tcora3 8 h'fff96 tcorb2 8 h'fff97 tcorb3 8 h'fff98 8tcnt2 8 h'fff99 8tcnt3 8 h'fff9a ? ???????? h'fff9b ? ???????? h'fff9c dadr0 8 d/a converter h'fff9d dadr1 8 h'fff9e dacr 8 daoe1 daoe0 dae ????? h'fff9f reserved area (access prohibited) h'fffa0 tpmr 8 ???? g3nov g2nov g1nov g0nov tpc h'fffa1 tpcr 8 g3cms1 g3cms0 g2cms1 g2cms0 g1cms1 g1cms0 g0cms1 g0cms0 h'fffa2 nderb 8 nder15 nder14 nder13 nder12 nder11 nder10 nder9 nder8 h'fffa3 ndera 8 nder7 nder6 nder5 nder4 nder3 nder2 nder1 nder0 h'fffa4 ndrb* 4 8 ndr15 ndr14 ndr13 ndr12 ndr11 ndr10 ndr9 ndr8 ndr15 ndr14 ndr13 ndr12 ???? h'fffa5 ndra* 4 8 ndr7 ndr6 ndr5 ndr4 ndr3 ndr2 ndr1 ndr0 ndr7 ndr6 ndr5 ndr4 ???? h'fffa6 ndrb* 4 8???????? ???? ndr11 ndr10 ndr9 ndr8 h'fffa7 ndra* 4 8???????? ???? ndr3 ndr2 ndr1 ndr0 h'fffa8 ? ???????? h'fffa9 ? ???????? h'fffaa ? ???????? h'fffab ? ???????? h'fffac ? ???????? h'fffad ? ???????? h'fffae ? ???????? h'fffaf ? ???????? 667 data bit names address (low) register name bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'fffb0 smr 8 c/ a chr pe o/ e stop mp cks1 cks0 sci channel 0 h'fffb1 brr 8 h'fffb2 scr 8 tie rie te re mpie teie cke1 cke0 h'fffb3 tdr 8 h'fffb4 ssr 8 tdre rdrf orer fer/ ers per tend mpb mpbt h'fffb5 rdr 8 h'fffb6 scmr 8 ???? sdir sinv ? smif h'fffb7 reserved area (access prohibited) h'fffb8 smr 8 c/ a chr pe o/ e stop mp cks1 cks0 sci channel 1 h'fffb9 brr 8 h'fffba scr 8 tie rie te re mpie teie cke1 cke0 h'fffbb tdr 8 h'fffbc ssr 8 tdre rdrf orer fer/ ers per tend mpb mpbt h'fffbd rdr 8 h'fffbe scmr 8 ???? sdir sinv ? smif h'fffbf reserved area (access prohibited) h'fffc0 reserved area (access prohibited) h'fffc1 h'fffc2 h'fffc3 h'fffc4 h'fffc5 h'fffc6 h'fffc7 h'fffc8 ? ???????? h'fffc9 ? ???????? h'fffca ? ???????? h'fffcb ? ???????? h'fffcc ? ???????? h'fffcd ? ???????? h'fffce ? ???????? h'fffcf ? ???????? h'fffd0 p1dr 8 p1 7 p1 6 p1 5 p1 4 p1 3 p1 2 p1 1 p1 0 port 1 h'fffd1 p2dr 8 p2 7 p2 6 p2 5 p2 4 p2 3 p2 2 p2 1 p2 0 port 2 h'fffd2 p3dr 8 p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 port 3 668 data bit names address (low) register name bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'fffd3 p4dr 8 p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 p4 0 port 4 h'fffd4 p5dr 8 ????p5 3 p5 2 p5 1 p5 0 port 5 h'fffd5 p6dr 8 p6 7 p6 6 p6 5 p6 4 p6 3 p6 2 p6 1 p6 0 port 6 h'fffd6 p7dr 8 p7 7 p7 6 p7 5 p7 4 p7 3 p7 2 p7 1 p7 0 port 7 h'fffd7 p8dr 8 ???p8 4 p8 3 p8 2 p8 1 p8 0 port 8 h'fffd8 p9dr 8 ? ? p9 5 p9 4 p9 3 p9 2 p9 1 p9 0 port 9 h'fffd9 padr 8 pa 7 pa 6 pa 5 pa 4 pa 3 pa 2 pa 1 pa 0 port a h'fffda pbdr 8 pb 7 pb 6 pb 5 pb 4 pb 3 pb 2 pb 1 pb 0 port b h'fffdb ? ???????? h'fffdc ? ???????? h'fffdd ? ???????? h'fffde ? ???????? h'fffdf ? ???????? h'fffe0 addrah 8 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 a/d converter h'fffe1 addral 8 ad1 ad0 ?????? h'fffe2 addrbh 8 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'fffe3 addrbl 8 ad1 ad0 ?????? h'fffe4 addrch 8 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'fffe5 addrcl 8 ad1 ad0 ?????? h'fffe6 addrdh 8 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'fffe7 addrdl 8 ad1 ad0 ?????? h'fffe8 adcsr 8 adf adie adst scan cks ch2 ch1 ch0 h'fffe9 adcr 8 trge ??????? notes: *1 writing to bits 6 to 0 of flmcr2 is prohibited. *2 writing to bits 5 to 3 of bcr is prohibited. *3 for the procedure for writing to tcsr, tcnt, and rstcsr, see section 11.2.4, notes on register access. *4 the address depends on the output trigger setting. *5 use byte access on flmcr1, flmcr2, ebr, and ramcr. these registers are not available in a mask rom version. legend: wdt: watchdog timer tpc: programmable timing pattern controller sci: serial communication interface 669 b.3 functions bit initial value r/w: 0 r/w 7 iciae 0 r/w 6 icibe 0 r/w 5 icice 0 r/w 4 ocide 0 r/w 3 ociae 1 r/w 2 ocibe 1 r/w 1 ovie 1 0 timer overflow interrupt enable 0 1 interrupt requested by ovf flag is disabled interrupt requested by ovf flag is enabled output compare interrupt b enable 0 1 interrupt requested by ocfb flag is disabled interrupt requested by ocfb flag is enabled output compare interrupt a enable 0 1 interrupt requested by ocfa flag is disabled interrupt requested by ocfa flag is enabled input capture interrupt d enable 0 1 interrupt requested by icfd flag is disabled interrupt requested by icfd flag is enabled tier?imer interrupt enable register h' 90 frt register abbreviation register name address to which register is mapped name of on-chip supporting module names of the bits. dashes (? indicate reserved bits. full name of bit descriptions of bit settings bit numbers initial bit values possible types of access r w r/w read only write only read and write 670 p1ddr?ort 1 data direction register h?e000 port 1 bit initial value read/write 0 w 7 p1 7 ddr 0 w 6 p1 6 ddr 0 w 5 p1 5 ddr 0 w 4 p1 4 ddr 0 w 3 p1 3 ddr 0 w 2 p1 2 ddr 0 w 1 p1 1 ddr 0 w 0 p1 0 ddr port 1 input/output select 0 1 generic input generic output initial value read/write 11111111 modes 1 to 4 modes 5 to 7 p2ddr?ort 2 data direction register h?e001 port 2 bit initial value read/write 0 w 7 p2 7 ddr 0 w 6 p2 6 ddr 0 w 5 p2 5 ddr 0 w 4 p2 4 ddr 0 w 3 p2 3 ddr 0 w 2 p2 2 ddr 0 w 1 p2 1 ddr 0 w 0 p2 0 ddr port 2 input/output select 0 1 generic input generic output initial value read/write 11111111 modes 1 to 4 modes 5 to 7 671 p3ddr?port 3 data direction register h?ee002 port 3 bit initial value read/write 0 w 7 p3 7 ddr 0 w 6 p3 6 ddr 0 w 5 p3 5 ddr 0 w 4 p3 4 ddr 0 w 3 p3 3 ddr 0 w 2 p3 2 ddr 0 w 1 p3 1 ddr 0 w 0 p3 0 ddr port 3 input/output select 0 1 generic input generic output p4ddr?port 4 data direction register h?ee003 port 4 bit initial value read/write 0 w 7 p4 7 ddr 0 w 6 p4 6 ddr 0 w 5 p4 5 ddr 0 w 4 p4 4 ddr 0 w 3 p4 3 ddr 0 w 2 p4 2 ddr 0 w 1 p4 1 ddr 0 w 0 p4 0 ddr port 4 input/output select 0 1 generic input generic output 672 p5ddr?port 5 data direction register h?ee004 port 5 bit initial value read/write 7654 0 w 3 p5 3 ddr 0 w 2 p5 2 ddr 0 w 1 p5 1 ddr 0 w 0 p5 0 ddr port 5 input/output select 0 1 generic input pin generic output pin initial value read/write 11111111 modes 1 to 4 modes 5 to 7 1111 p6ddr?port 6 data direction register h?ee005 port 6 bit 76 p6 6 ddr 5 p6 5 ddr 4 p6 4 ddr 3 p6 3 ddr 2 p6 2 ddr 1 p6 1 ddr 0 p6 0 ddr initial value read/write 10 w 0 w 0 w 0 w 0 w 0 w 0 w port 6 input/output select 0 1 generic input generic output 673 p8ddr?port 8 data direction register h?ee007 port 8 bit initial value read/write 7654 p8 4 ddr 0 w 3 p8 3 ddr 0 w 2 p8 2 ddr 0 w 1 p8 1 ddr 0 w 0 p8 0 ddr port 8 input/output select 0 1 generic input generic output initial value read/write 111 0 w 0 w 0 w 0 w modes 1 to 4 modes 5 to 7 111 0 w 1 w 674 p9ddr?port 9 data direction register h?ee008 port 9 bit initial value read/write 7 1 6 0 w 5 p9 5 ddr 0 w 4 p9 4 ddr 0 w 3 p9 3 ddr 0 w 2 p9 2 ddr 0 w 1 p9 1 ddr 0 w 0 p9 0 ddr port 9 input/output select 0 1 generic input generic output 1 paddr?port a data direction register h?ee009 port a bit initial value read/write 7 pa 7 ddr 6 pa 6 ddr 5 pa 5 ddr 4 pa 4 ddr 0 w 3 pa 3 ddr 0 w 2 pa 2 ddr 0 w 1 pa 1 ddr 0 w 0 pa 0 ddr initial value read/write 10 w 0 w 0 w 0 w modes 3, 4 modes 1, 2, 5, 6, 7 0 w 0 w port a input/output select 0 1 generic input generic output 0 w 0 w 0 w 0 w 0 w pbddr?port b data direction register h?ee00a port b bit initial value read/write 7 pb 7 ddr 0 w 6 pb 6 ddr 0 w 5 pb 5 ddr 0 w 4 pb 4 ddr 0 w 3 pb 3 ddr 0 w 2 pb 2 ddr 0 w 1 pb 1 ddr 0 w 0 pb 0 ddr port b input/output select 0 1 generic input generic output 0 w 675 mdcr?mode control register h?ee011 system control bit initial value read/write 1 7 1 6 0 5 0 4 0 3 r 2 mds2 r 1 mds1 r 0 mds0 mode select 2 to 0 0 1 0 1 operating mode * * * bit 2 md 2 bit 1 md 1 bit 0 md 0 0 1 0 1 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 0 1 0 1 0 1 note: * determined by the state of the mode pins (md 2 to md 0 ). 676 syscr?system control register h?ee012 system control bit initial value read/write 0 r/w 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 4 sts0 1 r/w 3 ue 0 r/w 2 nmieg 0 r/w 1 ssoe 1 r/w 0 rame nmi edge select 0 1 an interrupt is requested at the falling edge of nmi an interrupt is requested at the rising edge of nmi ram enable 0 1 on-chip ram is disabled on-chip ram is enabled user bit enable 0 1 ccr bit 6 (ui) is used as an interrupt mask bit ccr bit 6 (ui) is used as a user bit standby timer select 2 to 0 bit 6 sts2 waiting time = 8,192 states waiting time = 16,384 states waiting time = 32,768 states waiting time = 65,536 states waiting time = 131,072 states waiting time = 26,2144 states waiting time = 1,024 states illegal setting bit 5 sts1 bit 4 sts0 standby timer 0 1 0 1 0 1 0 1 0 1 0 1 0 1 software standby 0 1 sleep instruction causes transition to sleep mode sleep instruction causes transition to software standby mode software standby output port enable 0 1 in software standby mode, all address bus and bus control signals are high- impedance in software standby mode, address bus retains output state and bus control signals are fixed high 677 brcr?bus release control register h?ee013 bus controller bit 7 a23e 6 a22e 5 a21e 4 a20e 3210 brle initial value read/write 11111110 r/w modes 1, 2, 6, 7 initial value read/write 1 r/w 1 r/w 1 r/w 1 r/w 1110 r/w address 23 to 20 enable 0 1 address output other input/output mode 5 bus release enable 0 1 the bus cannot be released to an external device the bus can be released to an external device initial value read/write 1 r/w 1 r/w 1 r/w 011 10 r/w modes 3, 4 iscr?irq sense control register h?ee014 interrupt controller bit initial value read/write 0 r/w 7 0 r/w 6 0 r/w 5 irq5sc 0 r/w 4 irq4sc 0 r/w 3 irq3sc 0 r/w 2 irq2sc 0 r/w 1 irq1sc 0 r/w 0 irq0sc irq 5 to irq 0 sense control 0 1 interrupts are requested when irq irq irq irq 678 ier?irq enable register h?ee015 interrupt controller bit initial value read/write 0 r/w 7 0 r/w 6 0 r/w 5 irq5e 0 r/w 4 irq4e 0 r/w 3 irq3e 0 r/w 2 irq2e 0 r/w 1 irq1e 0 r/w 0 irq0e irq 5 to irq 0 enable 0 1 irq 5 to irq 0 interrupts are disabled irq 5 to irq 0 interrupts are enabled isr?irq status register h?ee016 interrupt controller bit initial value read/write 0 7 0 6 0 r/(w)* 5 irq5f 0 r/(w)* 4 irq4f 0 r/(w)* 3 irq3f 0 r/(w)* 2 irq2f 0 r/(w)* 1 irq1f 0 r/(w)* 0 irq0f irq5 to irq0 flags 0 note: * only 0 can be written to clear the flag. bits 5 to 0 irq5f to irq0f setting and clearing conditions 1 (n = 5 to 0) [clearing conditions] read irqnf when irqnf = 1, then write 0 in irqnf. irqnsc = 0, irqn irqnsc = 1 and irqn interrupt exception handling is being carried out. [setting conditions] irqnsc = 0 and irqn irqnsc = 1 and irqn 679 ipra?interrupt priority register a h?ee018 interrupt controller bit initial value read/write 0 r/w 7 ipra7 0 r/w 6 ipra6 0 r/w 5 ipra5 0 r/w 4 ipra4 0 r/w 3 ipra3 0 r/w 2 ipra2 0 r/w 1 ipra1 0 r/w 0 ipra0 priority level a7 to a0 0 1 priority level 0 (low priority) priority level 1 (high priority) interrupt sources controlled by each bit ipra bit interrupt source bit 7 ipra7 irq 0 bit 6 ipra6 irq 1 bit 5 ipra5 irq 2 , irq 3 bit 4 ipra4 irq 4 , irq 5 bit 3 ipra3 bit 2 ipra2 bit 1 ipra1 bit 0 ipra0 wdt, a/d con- verter 16-bit timer channel 0 16-bit timer channel 1 16-bit timer channel 2 iprb?nterrupt priority register b h?e019 interrupt controller bit initial value read/write 0 r/w 7 iprb7 0 r/w 6 iprb6 0 r/w 5 0 r/w 4 0 r/w 3 iprb3 0 r/w 2 iprb2 0 r/w 1 0 r/w 0 priority level b7, b6, b3, and b2 0 1 priority level 0 (low priority) priority level 1 (high priority) bit 7 iprb7 bit 6 iprb6 bit 5 bit 4 bit 3 iprb3 bit 2 iprb2 bit 1 bit 0 8-bit timer channels 0 and 1 8-bit timer channels 2 and 3 sci channel 0 sci channel 1 interrupt sources controlled by each bit iprb bit interrupt source 680 dastcr?d/a standby control register h?ee01a d/a bit initial value read/write 1 7 1 6 1 5 1 4 1 3 1 2 1 1 0 r/w 0 daste d/a standby enable 0 1 d/a output is disabled in software standby mode d/a output is enabled in software standby mode (initial value) 681 divcr?division control register h?ee01b system control bit initial value read/write 1 7 1 6 1 5 1 4 1 3 1 2 0 r/w 1 div1 0 r/w 0 div0 division ratio bits 1 and 0 frequency division ratio bit 1 div1 bit 0 div0 1/1 1/2 1/4 1/8 0 1 0 1 0 1 (initial value) 682 mstcrh?module standby control register h h?ee01c system control 765 4 321 0 pstop mstph1 mstph0 r/w r/w r/w r/w 011 1 100 0 module standby h1 and h0 selection bits for placing modules in standby state. bit initial value read/write reserved bits clock output. mstcrl module standby control register l h ee01d system control 765 4 321 0 mstpl2 mstpl3 mstpl4 mstpl0 r/w r/w r/w r/w r/w r/w r/w r/w 000 0 000 0 module standby l4 to l2, l0 selection bits for placing modules in standby state. reserved bits bit initial value read/write 683 adrcr ? address control register h'ee01e bus controller 7 1 bit initial value read/write 6 1 5 1 4 1 3 1 0 adrctl 1 r/w 2 1 1 1 reserved bits address control selects address update mode 1 or address update mode 2. description adrctl address update mode 2 is selected address update mode 1 is selected (initial value) 0 1 h8/3024f-ztat this register not provided this register provided h8/3026f-ztat h8/3024 mask rom version h8/3026 mask rom version note: 684 cscr ? chip select control register h ? ee01f bus controller bit initial value read/write 0 r/w 7 cs7e (n = 7 to 4) 0 r/w 6 cs6e 0 r/w 5 cs5e 0 r/w 4 cs4e 1 3 1 2 1 1 1 0 chip select 7 to 4 enable description bit n csne output of chip select signal csn csn 685 abwcr ? bus width control register h ? ee020 bus controller bit initial value initial value read/write 1 0 r/w 7 abw7 1 0 r/w 6 abw6 1 0 r/w 5 abw5 1 0 r/w 4 abw4 1 0 r/w 3 abw3 1 0 r/w 2 abw2 1 0 r/w 1 abw1 1 0 r/w 0 abw0 area 7 to 0 bus width control bus width of access area bits 7 to 0 abw7 to abw0 areas 7 to 0 are 16-bit access areas areas 7 to 0 are 8-bit access areas 0 1 modes 1, 3, 5, 6, and 7 modes 2 and 4 astcr ? access state control register h ? ee021 bus controller bit initial value read/write 1 r/w 7 ast7 1 r/w 6 ast6 1 r/w 5 ast5 1 r/w 4 ast4 1 r/w 3 ast3 1 r/w 2 ast2 1 r/w 1 ast1 1 r/w 0 ast0 area 7 to 0 access state control number of states in access area bits 7 to 0 ast7 to ast0 areas 7 to 0 are two-state access areas areas 7 to 0 are three-state access areas 0 1 686 wcrh ? wait control register h h ? ee022 bus controller 1 r/w 7 w71 1 r/w 6 w70 1 r/w 5 w61 1 r/w 4 w60 1 r/w 3 w51 1 r/w 2 w50 1 r/w 1 w41 1 r/w 0 w40 0 area 4 wait control 1 and 0 0 1 0 1 no program wait is inserted 1 program wait state is inserted 2 program wait states are inserted 3 program wait states are inserted 1 0 area 5 wait control 1 and 0 0 1 0 1 no program wait is inserted 1 program wait state is inserted 2 program wait states are inserted 3 program wait states are inserted 1 0 area 6 wait control 1 and 0 0 1 0 1 no program wait is inserted 1 program wait state is inserted 2 program wait states are inserted 3 program wait states are inserted 1 0 area 7 wait control 1 and 0 0 1 0 1 no program wait is inserted 1 program wait state is inserted 2 program wait states are inserted 3 program wait states are inserted 1 bit initial value read/write 687 wcrl ? wait control register l h ? ee023 bus controller bit initial value read/write 1 r/w 7 w31 1 r/w 6 w30 1 r/w 5 w21 1 r/w 4 w20 1 r/w 3 w11 1 r/w 2 w10 1 r/w 1 w01 1 r/w 0 w00 area 0 wait control 1 and 0 0 0 1 0 1 no program wait is inserted 1 program wait state is inserted 2 program wait states are inserted 3 program wait states are inserted 1 area 1 wait control 1 and 0 0 0 1 0 1 no program wait is inserted 1 program wait state is inserted 2 program wait states are inserted 3 program wait states are inserted 1 area 2 wait control 1 and 0 0 0 1 0 1 no program wait is inserted 1 program wait state is inserted 2 program wait states are inserted 3 program wait states are inserted 1 area 3 wait control 1 and 0 0 0 1 0 1 no program wait is inserted 1 program wait state is inserted 2 program wait states are inserted 3 program wait states are inserted 1 688 bcr ? bus control register h ? ee024 bus controller bit initial value read/write 1 r/w 7 icis1 1 r/w 6 icis0 0 * 5 0 * 4 0 * 3 1 2 1 r/w 1 rdea 0 r/w 0 waite 0 1 wait pin wait input is disabled wait pin wait input is enabled idle cycle insertion 0 0 1 no idle cycle is inserted in case of consecutive external read and write cycles idle cycle is inserted in case of consecutive external read and write cycles idle cycle insertion 1 note: * these bits can be read and written, but must not be set to 1. normal operation cannot be guaranteed if 1 is written in these bits. 0 1 no idle cycle is inserted in case of consecutive external read cycles for different areas idle cycle is inserted in case of consecutive external read cycles for different areas area division unit select 0 1 area divisions are as follows: areas 0 to 7 are the same size (2 mb) wait pin enable area 0: 2 mb area 4: 1.93 mb area 1: 2 mb area 5: 4 kb area 2: 8 mb area 6: 23.75 kb area 3: 2 mb area 7: 22 b 689 flmcr (flmcr1) ? flash memory control register h'ee030 flash memory bit initial value read/write 1/0 r 7 fwe 0 r/w 6 swe 0 r/w 5 esu 0 r/w 4 psu 0 r/w 3 ev 0 r/w 2 pv 0 r/w 1 e 0 r/w initial value read/write modes 5 and 7 modes 1 to 4, and 6 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 p 0 1 program mode cleared (initial value) transition to program mode [setting condition] when fwe = 1, swe = 1, and psu = 1 program mode 0 1 erase mode cleared (initial value) transition to erase mode [setting condition] when fwe = 1, swe = 1, and esu = 1 erase mode 0 1 program-verify mode cleared (initial value) transition to program-verify mode [setting condition] when fwe = 1 and swe = 1 program-verify mode 0 1 erase-verify mode cleared (initial value) transition to erase-verify mode [setting condition] when fwe = 1 and swe = 1 erase-verify mode 0 1 program setup cleared (initial value) program setup [setting condition] when fwe = 1 and swe = 1 program setup 0 1 erase setup cleared (initial value) erase setup [setting condition] when fwe = 1 and swe = 1 erase setup 0 1 write/erase disabled (initial value) write/erase enabled [setting condition] when fwe = 1 software write enable bit 0 1 when a low level is input to the fwe pin (hardware protection state) * when a high level is input to the fwe pin flash write enable bit h8/3024f-ztat this register provided this register provided (flmcr1) this register not provided h8/3026f-ztat h8/3024 mask rom version h8/3026 mask rom version note: * fix the fwe pin low in mode 6. 690 flmcr (flmcr2) ? flash memory control register 2 h'ee031 flash memory bit initial value read/write 0 r 7 fler 0 6 0 5 0 4 0 3 0 2 0 1 0 0 flash memory error reserved bits h8/3024f-ztat this register not provided note: writes to flmcr2 are prohibited. this register provided this register not provided h8/3026f-ztat h8/3024 mask rom version h8/3026 mask rom version 691 ebr (ebr1) ? erase block register h'ee032 flash memory bit 7 eb7 6 eb6 5 eb5 4 eb4 3 eb3 2 eb2 1 eb1 0 eb0 0 1 block eb7 to eb0 is not selected (initial value) block eb7 to eb0 is selected block 7 to 0 note: when not erasing, clear ebr to h'00. writes are invalid. a value of 1 cannot be set in this register in mode 6. initial value read/write 0 r 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w initial value read/write modes 5 and 7 modes 1 to 4, and 6 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 r h8/3024f-ztat this register provided this register provided (ebr1) this register not provided h8/3026f-ztat h8/3024 mask rom version h8/3026 mask rom version 692 ebr (ebr2) ? erase block register 2 h'ee033 flash memory bit 7 6 5 4 3 eb11 2 eb10 1 eb9 0 eb8 0 1 block eb11 to eb8 is not selected (initial value) block eb11 to eb8 is selected block 11 to 8 note: when not erasing, clear ebr to h'00. a value of 1 cannot be set in this register in mode 6. initial value read/write 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w initial value read/write modes 5 and 7 modes 1 to 4, and 6 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 r h8/3024f-ztat this register not provided this register not provided h8/3026f-ztat this register provided h8/3024 mask rom version h8/3026 mask rom version 693 p4pcr ? port 4 input pull-up control register h ? ee03e port 4 bit initial value read/write 0 r/w 7 p4 7 pcr 0 r/w 6 p4 6 pcr 0 r/w 5 p4 5 pcr 0 r/w 4 p4 4 pcr 0 r/w 3 p4 3 pcr 0 r/w 2 p4 2 pcr 0 r/w 1 p4 1 pcr 0 r/w 0 p4 0 pcr port 4 input pull-up control 7 to 0 0 1 input pull-up transistor is off input pull-up transistor is on note: valid when the corresponding p4ddr bit is cleared to 0 (designating generic input). p5pcr ? port 5 input pull-up control register h ? ee03f port 5 bit initial value read/write 1 7 1 6 1 5 1 4 0 r/w 3 p5 3 pcr 0 r/w 2 p5 2 pcr 0 r/w 1 p5 1 pcr 0 r/w 0 p5 0 pcr port 5 input pull-up control 3 to 0 0 1 input pull-up transistor is off input pull-up transistor is on note: valid when the corresponding p5ddr bit is cleared to 0 (designating generic input). 694 ramcr ? ram control register h'ee077 flash memory bit 3 bit 2 bit 1 rams ram2 ram1 ram area 0 1 0/1 0 1 0/1 0 1 0 1 ram emulation status h'fff000 to h'fff3ff h'000000 to h'0003ff h'000400 to h'0007ff h'000800 to h'000bff h'000c00 to h'000fff no emulation mapping ram ram select, ram2, ram1 note: * in mode 6 (single-chip normal mode), flash memory emulation by ram is not supported; these bits can be modified, but must not be set to 1. bit 7 rams 6543210 ram2 ram1 reserved bits modes 1 to 4 1 1 1 1 0 r 0 r 0 r 1 initial value r/w initial value r/w modes 5 to 7 1 1 1 1 0 r/w * 0 r/w * 0 r/w * 1 h8/3024f-ztat this register provided this register provided (bit specification below) this register not provided h8/3026f-ztat h8/3024 mask rom version h8/3026 mask rom version 695 ramcr (h8/3026f-ztat) ? ram control register h'ee077 flash memory bit 7 rams 6543210 ram2 ram1 ram0 reserved bits modes 1 to 4 1 1 1 1 0 r 0 r 0 r 0 r initial value r/w initial value r/w modes 5 to 7 1 1 1 1 0 r/w 0 r/w 0 r/w 0 r/w 696 flmsr-flash memory status register h'ee07d flash memory bit 7 fler description 0 1 flash memory program/erase protection (error protection * 1 ) is disabled (initial value) [clearing condition] wdt reset, reset via the res when flash memory is read * 2 during programming/erasing (including a vector read or instruction fetch, but excluding reads in a ram area overlapping flash memory space) immediately after the start of exception handling during programming/erasing (but excluding reset, illegal instruction, trap instruction, and division-by-zero exception handling) * 3 when a sleep instruction (including software standby) is executed during programming/erasing when the bus is released during programming/erasing flash memory error notes: *1 *2 *3 see 17.7.3, error protection, for details. the read value in this case is undefined. before the exception handling stack or vector read is performed. bit 7 fler 6543210 reserved bits 0 r 1 1 1 1 1 1 1 initial value r/w h8/3024f-ztat this register provided this register not provided (fler bit in flmcr2) this register not provided h8/3026f-ztat h8/3024 mask rom version h8/3026 mask rom version 697 tstr ? timer start register h ? fff60 16-bit timer (all channels) 7 1 bit initial value read/write 6 1 5 1 reserved bits 4 1 3 1 2 str2 0 r/w 1 str1 0 r/w 0 str0 0 r/w 0 1 16tcnt0 is halted (initial value) 16tcnt0 is counting counter start 0 0 1 16tcnt1 is halted (initial value) 16tcnt1 is counting counter start 1 0 1 16tcnt2 is halted (initial value) 16tcnt2 is counting counter start 2 698 tsnc ? timer synchro register h ? fff61 16-bit timer (all channels) 7 1 bit initial value read/write 6 1 5 1 4 1 3 1 2 sync2 0 r/w 1 sync1 0 r/w 0 sync0 0 r/w 0 1 channel 0 timer counter (16tcnt0) operates independently (16tcnt0 presetting/clearing is independent of other channels) (initial value) channel 0 operates synchronously synchronous presetting/synchronous clearing of 16tcnt0 is possible timer sync 0 0 1 channel 1 timer counter (16tcnt1) operates independently (16tcnt1 presetting/clearing is independent of other channels) (initial value) channel 1 operates synchronously synchronous presetting/synchronous clearing of 16tcnt1 is possible timer sync 1 0 1 channel 2 timer counter (16tcnt2) operates independently (16tcnt2 presetting/clearing is independent of other channels) (initial value) channel 2 operates synchronously synchronous presetting/synchronous clearing of 16tcnt2 is possible timer sync 2 reserved bits 699 tmdr ? timer mode register h ? fff62 16-bit timer (all channels) 7 1 bit initial value read/write 6 mdf 0 r/w 5 fdir 0 r/w 4 1 3 1 2 pwm2 0 r/w 1 pwm1 0 r/w 0 pwm0 0 r/w 0 1 channel 0 operates normally (initial value) channel 0 operates in pwm mode pwm mode 0 0 1 channel 1 operates normally (initial value) channel 1 operates in pwm mode pwm mode 1 0 1 channel 2 operates normally (initial value) channel 2 operates in pwm mode pwm mode 2 0 1 ovf is set to 1 in tisrc when 16tcnt2 overflows or underflows (initial value) ovf is set to 1 in tisrc when 16tcnt2 overflows flag direction 0 1 channel 2 operates normally (initial value) channel 2 operates in phase counting mode phase counting mode 700 tolr ? timer output level setting register h ? fff63 16-bit timer (all channels) 7 1 bit initial value read/write 6 1 5 tob2 0 w 4 toa2 0 w 3 tob1 0 w 2 toa1 0 w 1 tob0 0 w 0 toa0 0 w 0 1 tioca 0 is 0 tioca 0 is 1 output level setting a0 0 1 tiocb 0 is 0 tiocb 0 is 1 output level setting b0 0 1 tioca 1 is 0 tioca 1 is 1 output level setting a1 0 1 tiocb 1 is 0 tiocb 1 is 1 output level setting b1 0 1 tioca 2 is 0 tioca 2 is 1 output level setting a2 0 1 tiocb 2 is 0 (initial value) (initial value) (initial value) (initial value) (initial value) (initial value) tiocb 2 is 1 output level setting b2 701 tisra ? timer interrupt status register a h ? fff64 16-bit timer (all channels) 1 7 imiea2 0 r/w 6 imiea1 0 r/w 5 imiea0 0 r/w 4 1 3 imfa2 0 r/(w)* 2 imfa1 0 r/(w)* 1 imfa0 0 r/(w)* 0 0 1 input capture/compare match flag a0 [clearing conditions] read imfa0 when imfa0=1, then write 0 in imfa0 [setting conditions] 16tcnt0=gra0 when gra0 functions as an output compare register. 16tcnt0 value is transferred to gra0 by an input capture signal when gra0 functions as an input capture register. 0 1 input capture/compare match flag a1 [clearing conditions] read imfa1 when imfa1=1, then write 0 in imfa1 [setting conditions] 16tcnt1=gra1 when gra1 functions as an output compare register. 16tcnt1 value is transferred to gra1 by an input capture signal when gra1 functions as an input capture register. 0 1 input capture/compare match flag a2 [clearing conditions] read imfa2 when imfa2=1, then write 0 in imfa2 (initial value) (initial value) (initial value) [setting conditions] 16tcnt2=gra2 when gra2 functions as an output compare register. 16tcnt2 value is transferred to gra2 by an input capture signal when gra2 functions as an input capture register. 0 1 imia0 interrupt requested by imfa0 flag is disabled imia0 interrupt requested by imfa0 is enabled input capture/compare match interrupt enable a0 0 1 imia1 interrupt requested by imfa1 flag is disabled imia1 interrupt requested by imfa1 is enabled input capture/compare match interrupt enable a1 0 1 imia2 interrupt requested by imfa2 flag is disabled (initial value) (initial value) (initial value) imia2 interrupt requested by imfa2 is enabled input capture/compare match interrupt enable a2 bit: initial value: read/write: note: * only 0 can be written to clear the flag. 702 tisrb ? timer interrupt status register b h ? fff65 16-bit timer (all channels) 1 7 imieb2 0 r/w 6 imieb1 0 r/w 5 imieb0 0 r/w 4 1 3 imfb2 0 r/(w)* 2 imfb1 0 r/(w)* 1 imfb0 0 r/(w)* 0 0 1 input capture/compare match flag b0 [clearing condition] read imfb0 when imfb0=1, then write 0 in imfb0. [setting conditions] 16tcnt0=grb0 when grb0 functions as an output compare register. 16tcnt0 value is transferred to grb0 by an input capture signal when grb0 functions as an input capture register. 0 1 input capture/compare match flag b1 [clearing condition] read imfb1 when imfb1=1, then write 0 in imfb1. [setting conditions] 16tcnt1=grb1 when grb1 functions as an output compare register. 16tcnt1 value is transferred to grb1 by an input capture signal when grb1 functions as an input capture register. 0 1 input capture/compare match flag b2 [clearing condition] read imfb2 when imfb2=1, then write 0 in imfb2. (initial value) (initial value) (initial value) [setting conditions] 16tcnt2=grb2 when grb2 functions as an output compare register. 16tcnt2 value is transferred to grb2 by an input capture signal when grb2 functions as an input capture register. 0 1 imib0 interrupt requested by imfb0 flag is disabled imib0 interrupt requested by imfb0 is enabled input capture/compare match interrupt enable b0 0 1 imib1 interrupt requested by imfb1 flag is disabled imib1 interrupt requested by imfb1 is enabled input capture/compare match interrupt enable b1 0 1 imib2 interrupt requested by imfb2 flag is disabled (initial value) (initial value) (initial value) imib2 interrupt requested by imfb2 is enabled input capture/compare match interrupt enable b2 note : * only 0 can be written to clear the flag. bit: initial value: read/write: 703 tisrc ? timer interrupt status register c h ? fff66 16-bit timer (all channels) 1 7 ovie2 0 r/w 6 ovie1 0 r/w 5 ovie0 0 r/w 4 1 3 ovf2 0 r/(w)* 2 ovf1 0 r/(w)* 1 ovf0 0 r/(w)* 0 0 1 ovi0 interrupt requested by ovf0 flag is disabled ovi0 interrupt requested by ovf0 flag is enabled overflow interrupt enable 0 0 1 ovi1 interrupt requested by ovf1 flag is disabled ovi1 interrupt requested by ovf1 flag is enabled overflow interrupt enable 1 0 1 ovi2 interrupt requested by ovf2 flag is disabled (initial value) (initial value) (initial value) ovi2 interrupt requested by ovf2 flag is enabled overflow interrupt enable 2 bit: initial value: read/write: [clearing condition] read ovf0 when ovf0 = 1, then write 0 in ovf0. [setting condition] 16tcnt0 overflowed from h'ffff to h'0000. overflow flag 0 0 1 [clearing condition] read ovf1 when ovf1 = 1, then write 0 in ovf1. [setting condition] 16tcnt1 overflowed from h'ffff to h'0000. overflow flag 1 0 1 [clearing condition] read ovf2 when ovf2 = 1, then write 0 in ovf2. (initial value) (initial value) (initial value) [setting condition] 16tcnt2 overflowed from h'ffff to h'0000, or underflowed from h'0000 to h'ffff. overflow flag 2 0 1 note : * only 0 can be written to clear the flag. 704 16tcr0 ? timer control register 0 h ? fff68 16-bit timer channel 0 bit initial value read/write 1 7 0 r/w 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w 0 tpsc0 timer prescaler 2 to 0 description bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 internal clock : internal clock : / 2 internal clock : / 4 internal clock : / 8 external clock a : tclka input external clock b : tclkb input external clock c : tclkc input external clock d : tclkd input 0 1 0 1 0 1 0 1 0 1 0 1 0 1 clock edge 1 and 0 description bit 4 ckeg bit 3 ckeg0 rising edges counted falling edges counted both edges counted 0 1 0 0 1 counter clear 1 and 0 description bit 6 cclr1 bit 5 cclr0 16tcnt is not cleared 16tcnt is cleared by gra compare match or input capture 16tcnt is cleared by grb compare match or input capture synchronous clear : 16tcnt is cleared in synchronization with other synchronized timers 0 1 0 1 0 1 (initial value) (initial value) (initial value) 705 tior0 ? timer i/o control register 0 h ? fff69 16-bit timer channel 0 i/o control a2 to a0 description bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 no output at compare match (initial value) 0 output at gra compare match 1 output at gra compare match output toggles at gra compare match (1 output on channel 2) gra captures rising edges of input gra captures falling edges of input grb captures both edges of input gra is an output compare register gra is an input capture register i/o control b2 to b0 description bit 6 iob2 bit 5 iob1 bit 4 iob0 no output at compare match (initial value) 0 output at grb compare match 1 output at grb compare match output toggles at grb compare match (1 output on channel 2) grb captures rising edges of input grb captures falling edges of input grb captures both edges of input grb is an output compare register grb is an input capture register 1 7 iob2 0 r/w 6 iob1 0 r/w 5 iob0 0 r/w 4 1 3 ioa2 0 r/w 2 ioa1 0 r/w 1 ioa0 0 r/w 0 bit: initial value: read/write: 1 0 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 706 16tcnt0 h/l ? timer counter 0 h/l h ? fff6a, h ? fff6b 16-bit timer channel 0 bit initial value read/write 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w up-counter gra0 h/l ? general register a0 h/l h ? fff6c, h ? fff6d 16-bit timer channel 0 bit initial value read/write 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w output compare or input capture register grb0 h/l ? general register b0 h/l h ? fff6e, h ? fff6f 16-bit timer channel 0 bit initial value read/write 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w output compare or input capture register 707 16tcr1 timer control register 1 h ? fff70 16-bit timer channel 1 7 1 bit initial value read/write 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w 0 tpsc0 0 r/w note: bit functions are the same as for 16-bit timer channel 0. tior1 timer i/o control register 1 h fff71 16-bit timer channel 1 7 1 bit initial value read/write 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 1 2 ioa2 0 r/w 1 ioa1 0 r/w 0 ioa0 0 r/w note: bit functions are the same as for 16-bit timer channel 0. 16tcnt1 h/l timer counter 1 h/l h fff72, h fff73 16-bit timer channel 1 bit initial value read/write 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w note: bit functions are the same as for 16-bit timer channel 0. 708 gra1 h/l ? general register a1 h/l h ? fff74, h ? fff75 16-bit timer channel 1 bit initial value read/write 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w note: bit functions are the same as for 16-bit timer channel 0. grb1 h/l ? general register b1 h/l h ? fff76, h ? fff77 16-bit timer channel 1 bit initial value read/write 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w note: bit functions are the same as for 16-bit timer channel 0. 16tcr2 timer control register 2 h ? fff78 16-bit timer channel 2 7 1 bit initial value read/write 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w 0 tpsc0 0 r/w notes: 1. bit functions are the same as for 16-bit timer channel 0. 2. when phase counting mode is selected in channel 2, the settings of bits ckeg1 and ckeg0 and tpsc2 to tpsc0 in 16tcr2 are ignored. 709 tior2 ? timer i/o control register 2 h ? fff79 16-bit timer channel 2 7 1 bit initial value read/write 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 1 2 ioa2 0 r/w 1 ioa1 0 r/w 0 ioa0 0 r/w note: bit functions are the same as for 16-bit timer channel 0. 16tcnt2 h/l timer counter 2 h/l h fff7a, h fff7b 16-bit timer channel 2 bit initial value read/write 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w phase counting mode : other mode : up/down counter up-counter gra2 h/l general register a2 h/l h fff7c, h fff7d 16-bit timer channel 2 bit initial value read/write 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w note: bit functions are the same as for 16-bit timer channel 0. 710 grb2 h/l ? general register b2 h/l h ? fff7e, h ? fff7f 16-bit timer channel 2 bit initial value read/write 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w note: bit functions are the same as for 16-bit timer channel 0. 711 8tcr0 ? timer control register 0 8tcr1 ? timer control register 1 h ? fff80 h ? fff81 8-bit timer channel 0 8-bit timer channel 1 bit initial value read/write 0 r/w 7 cmieb 0 r/w 6 cmiea 0 r/w 5 ovie 0 r/w 4 cclr1 0 r/w 3 cclr0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w 0 cks0 clock select 2 to 0 0 0 0 1 0 1 0 0 1 1 0 1 1 clock input is disabled internal clock: counted on rising edge of 712 8tcsr0 ? timer control/status register 0 h ? fff82 8-bit timer channel 0 output select a1 and a0 0 description description description bit 1 os1 bit 0 os0 ice in 8tcsr1 bit 3 ois3 bit 4 adte trge * 2 bit 2 ois2 1 0 1 no change at compare match a 0 output at compare match a 1 output at compare match a output toggles at compare match a output/input capture edge select b3 and b2 0 0 1 0 1 0 1 0 1 0 1 0 1 no change at compare match b 0 output at compare match b 1 output at compare match b output toggles at compare match b tcorb input capture on rising edge tcorb input capture on falling edge tcorb input capture on both rising and falling edges 1 a/d trigger enable 0 0 1 0 1 a/d converter start requests by compare match a or an external trigger are disabled a/d converter start requests by compare match a or an external trigger are disabled a/d converter start requests by an external trigger are enabled, and a/d converter start requests by compare match a are disabled a/d converter start requests by compare match a are enabled, and a/d converter start requests by an external trigger are disabled timer overflow flag 0 [clearing condition] read ovf when ovf = 1, then write 0 in ovf. bit initial value read/write 0 r/(w) * 1 7 cmfb 0 r/(w) * 1 6 cmfa 0 r/(w) * 1 5 ovf 0 r/w 4 adte 0 r/w 3 ois3 0 r/w 2 ois2 0 r/w 1 os1 0 r/w 0 os0 0 1 1 [setting condition] 8tcnt overflows from h'ff to h'00. compare match flag a 0 [clearing condition] read cmfa when cmfa = 1, then write 0 in cmfa. 1 [setting condition] 8tcnt = tcora compare match/input capture flag b 0 [clearing condition] read cmfb when cmfb = 1, then write 0 in cmfb. 1 [setting conditions] 8tcnt = tcorb the 8tcnt value is transferred to tcorb by an input capture signal when tcorb functions as an input capture register. notes: *1 only 0 can be written to bits 7 to 5 to clear these flags. *2 trge is bit 7 of the a/d control register (adcr). 1 713 8tcsr1 ? timer control/status register 1 h ? fff83 8-bit timer channel 1 output select a1 and a0 0 description description bit 1 os1 bit 0 os0 ice in 8tcsr1 bit 3 ois3 bit 2 ois2 1 0 1 no change at compare match a 0 output at compare match a 1 output at compare match a output toggles at compare match a output/input capture edge select b3 and b2 0 0 1 0 1 0 1 0 1 0 1 0 1 no change at compare match b 0 output at compare match b 1 output at compare match b output toggles at compare match b tcorb input capture on rising edge tcorb input capture on falling edge tcorb input capture on both rising and falling edges 1 timer overflow flag 0 [clearing condition] read ovf when ovf = 1, then write 0 in ovf. 0 1 1 [setting condition] 8tcnt overflows from h'ff to h'00. compare match/input capture flag a 0 [clearing condition] read cmfa when cmfa = 1, then write 0 in cmfa. 1 [setting condition] 8tcnt = tcora compare match/input capture flag b 0 [clearing condition] read cmfb when cmfb = 1, then write 0 in cmfb. 1 note: * only 0 can be written to bits 7 to 5 to clear these flags. bit initial value read/write 0 r/(w)* 7 cmfb 0 r/(w)* 6 cmfa 0 r/(w)* 5 ovf 0 r/w 4 ice 0 r/w 3 ois3 0 r/w 2 ois2 0 r/w 1 os1 0 r/w 0 os0 input capture enable 0 1 tcorb is a compare match register tcorb is an input capture register [setting conditions] 8tcnt = tcorb the 8tcnt value is transferred to tcorb by an input capture signal when tcorb functions as an input capture register. 714 tcora0 ? time constant register a0 tcora1 ? time constant register a1 h ? fff84 h ? fff85 8-bit timer channel 0 8-bit timer channel 1 bit initial value read/write 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w tcora0 tcora1 tcorb0 ? time constant register b0 tcorb1 ? time constant register b1 h ? fff86 h ? fff87 8-bit timer channel 0 8-bit timer channel 1 bit initial value read/write 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w tcorb0 tcorb1 8tcnt0 ? timer counter 0 8tcnt1 ? timer counter 1 h ? fff88 h ? fff89 8-bit timer channel 0 8-bit timer channel 1 bit initial value read/write 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 8tcnt0 8tcnt1 715 tcsr ? timer control/status register h ? fff8c wdt bit initial value read/write 0 r/(w)* 7 ovf 0 r/w 6 wt/ it tcnt is initialized to h'00 and halted 1 timer enabled tcnt starts counting up timer mode select 0 interval timer: requests interval timer interrupts 1 watchdog timer: generates a reset signal overflow flag 0 [clearing condition] read ovf when ovf = 1, then write 0 in ovf 1 [setting condition] tcnt changes from h'ff to h'00 note: * only 0 can be written to clear the flag. cks2 cks1 cks0 description 716 tcnt ? timer counter h'fff8d (read), h'fff8c (write) wdt bit initial value read/write 0 r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 count value rstcsr ? reset control/status register h'fff8f (read), h'fff8e (write) wdt bit initial value read/write 0 r/(w)* 7 wrst 0 r/w 6 rstoe 1 5 1 4 1 3 1 2 1 1 1 0 reset output enable 0 external output of reset signal is disabled external output of reset signal is enabled 1 watchdog timer reset 0 [clearing conditions] reset signal at res read wrst when wrst = 1, then write 0 in wrst 1 [setting condition] tcnt overflow generates a reset signal during watchdog timer operation note: * only 0 can be written in bit 7 to clear the flag. 717 8tcr2 ? timer control register 2 8tcr3 ? timer control register 3 h ? fff90 h ? fff91 8-bit timer channel 2 8-bit timer channel 3 bit initial value read/write 0 r/w 7 cmieb 0 r/w 6 cmiea 0 r/w 5 ovie 0 r/w 4 cclr1 0 r/w 3 cclr0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w 0 cks0 clock select 2 to 0 0 0 0 1 0 1 0 0 1 1 0 1 1 clock input is disabled internal clock: counted on rising edge of 718 8tcsr2 ? timer control/status register 2 8tcsr3 ? timer control/status register 3 h ? fff92 h ? fff93 8-bit timer channel 2 8-bit timer channel 3 bit initial value read/write 0 r/(w)* 7 cmfb 0 r/(w)* 6 cmfa 0 r/(w)* 5 ovf 0 r/w 4 ice 0 r/w 3 ois3 0 r/w 2 ois2 0 r/w 1 os1 0 r/w 0 os0 timer overflow flag 0 [clearing condition] read ovf when ovf = 1, then write 0 in ovf. bit initial value read/write 0 r/(w)* 7 cmfb 0 r/(w)* 6 cmfa 0 r/(w)* 5 ovf 1 4 0 r/w 3 ois3 0 r/w 2 ois2 0 r/w 1 os1 0 r/w 0 os0 8tcsr3 8tcsr2 1 [setting condition] 8tcnt overflows from h'ff to h'00. compare match/input capture flag a 0 [clearing condition] read cmfa when cmfa = 1, then write 0 in cmfa. 1 [setting condition] 8tcnt = tcora compare match/input capture flag b 0 [clearing condition] read cmfb when cmfb = 1, then write 0 in cmfb. 1 [setting conditions] 8tcnt = tcorb the 8tcnt value is transferred to tcorb by an input capture signal when tcorb functions as an input capture register. note: * only 0 can be written to bits 7 to 5 to clear these flags. output select a1 and a0 0 description bit 1 os1 bit 0 os0 1 0 1 no change at compare match a 0 output at compare match a 1 output at compare match a output toggles at compare match a 0 1 description ice in 8tcsr3 bit 3 ois3 bit 3 ois2 output/input capture edge select b3 and b2 0 0 1 0 1 0 1 0 1 0 1 0 no change at compare match b 0 output at compare match b 1 output at compare match b output toggles at compare match b tcorb input capture on rising edge tcorb input capture on falling edge tcorb input capture on both rising and falling edges 1 input capture enable 0 1 tcorb is a compare match register tcorb is an input capture register 719 tcora2 ? time constant register a2 tcora3 ? time constant register a3 h ? fff94 h ? fff95 8-bit timer channel 2 8-bit timer channel 3 bit initial value read/write 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w tcora2 tcora3 tcorb2 ? time constant register b2 tcorb3 ? time constant register b3 h ? fff96 h ? fff97 8-bit timer channel 2 8-bit timer channel 3 bit initial value read/write 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w tcorb2 tcorb3 8tcnt2 ? timer counter 2 8tcnt3 ? timer counter 3 h ? fff98 h ? fff99 8-bit timer channel 2 8-bit timer channel 3 bit initial value read/write 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 8tcnt2 8tcnt3 720 dadr0 ? d/a data register 0 h ? fff9c d/a bit initial value read/write 0 r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 d/a conversion data dadr1 ? d/a data register 1 h ? fff9d d/a bit initial value read/write 0 r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 d/a conversion data 721 dacr ? d/a control register h ? fff9e d/a bit initial value read/write 0 r/w 7 daoe1 0 r/w 6 daoe0 0 r/w 5 dae 1 4 1 3 1 2 1 1 1 0 d/a enable bit 7 daoe1 d/a conversion is disabled in channels 0 and 1 d/a conversion is enabled in channel 0 d/a conversion is disabled in channel 1 d/a conversion is disabled in channel 0 d/a conversion is enabled in channel 1 description d/a conversion is enabled in channels 0 and 1 d/a conversion is enabled in channels 0 and 1 d/a conversion is enabled in channels 0 and 1 bit 6 bit 5 daoe0 dae 0 0 0 1 1 1 0 1 1 0 0 1 0 1 0 1 d/a output enable 0 0 da 0 analog output is disabled 1 channel-0 d/a conversion and da 0 analog output are enabled d/a output enable 1 0 da 1 analog output is disabled 1 channel-1 d/a conversion and da 1 analog output are enabled 722 tpmr ? tpc output mode register h ? fffa0 tpc bit initial value read/write 1 7 1 6 1 5 1 4 0 r/w 3 g3nov 0 r/w 2 g2nov 0 r/w 1 g1nov 0 r/w 0 g0nov group 0 non-overlap 0 normal tpc output in group 0. output values change at compare match a in the selected 16-bit timer channel 1 non-overlapping tpc output in group 0, controlled by compare match a and b in the selected 16-bit timer channel group 1 non-overlap 0 normal tpc output in group 1. output values change at compare match a in the selected 16-bit timer channel 1 non-overlapping tpc output in group 1, controlled by compare match a and b in the selected 16-bit timer channel group 2 non-overlap 0 normal tpc output in group 2. output values change at compare match a in the selected 16-bit timer channel 1 non-overlapping tpc output in group 2, controlled by compare match a and b in the selected 16-bit timer channel group 3 non-overlap 0 normal tpc output in group 3. output values change at compare match a in the selected 16-bit timer channel 1 non-overlapping tpc output in group 3, controlled by compare match a and b in the selected 16-bit timer channel 723 tpcr ? tpc output control register h ? fffa1 tpc group 0 compare match select 1 and 0 bit 1 g0cms1 16-bit timer channel selected as output trigger bit 0 g0cms0 tpc output group 0 (tp 3 to tp 0 ) is triggered by compare match in 16-bit timer channel 0 tpc output group 0 (tp 3 to tp 0 ) is triggered by compare match in 16-bit timer channel 1 tpc output group 0 (tp 3 to tp 0 ) is triggered by compare match in 16-bit timer channel 2 0 1 0 1 0 1 group 1 compare match select 1 and 0 bit 3 g1cms1 16-bit timer channel selected as output trigger bit 2 g1cms0 tpc output group 1 (tp 7 to tp 4 ) is triggered by compare match in 16-bit timer channel 0 tpc output group 1 (tp 7 to tp 4 ) is triggered by compare match in 16-bit timer channel 1 tpc output group 1 (tp 7 to tp 4 ) is triggered by compare match in 16-bit timer channel 2 0 1 0 1 0 1 group 2 compare match select 1 and 0 bit 5 g2cms1 16-bit timer channel selected as output trigger bit 4 g2cms0 tpc output group 2 (tp 11 to tp 8 ) is triggered by compare match in 16-bit timer channel 0 tpc output group 2 (tp 11 to tp 8 ) is triggered by compare match in 16-bit timer channel 1 tpc output group 2 (tp 11 to tp 8 ) is triggered by compare match in 16-bit timer channel 2 0 1 0 1 0 1 group 3 compare match select 1 and 0 bit 7 g3cms1 16-bit timer channel selected as output trigger bit 6 g3cms0 tpc output group 3 (tp 15 to tp 12 ) is triggered by compare match in 16-bit timer channel 0 tpc output group 3 (tp 15 to tp 12 ) is triggered by compare match in 16-bit timer channel 1 tpc output group 3 (tp 15 to tp 12 ) is triggered by compare match in 16-bit timer channel 2 0 1 0 1 0 1 bit initial value read/write 7 g3cms1 6 g3cms0 5 g2cms1 4 g2cms0 1 r/w 3 g1cms1 1 r/w 2 g1cms0 1 r/w 1 g0cms1 1 r/w 0 g0cms0 1 r/w 1 r/w 1 r/w 1 r/w 724 nderb ? next data enable register b h ? fffa2 tpc bit initial value read/write 0 r/w 7 nder15 0 r/w 6 nder14 0 r/w 5 nder13 0 r/w 4 nder12 0 r/w 3 nder11 0 r/w 2 nder10 0 r/w 1 nder9 0 r/w 0 nder8 next data enable 15 to 8 bits 7 to 0 nder15 to nder8 description tpc outputs tp 15 to tp 8 are disabled (ndr15 to ndr8 are not transferred to pb 7 to pb 0 ) tpc outputs tp 15 to tp 8 are enabled (ndr15 to ndr8 are transferred to pb 7 to pb 0 ) 0 1 ndera ? next data enable register a h ? fffa3 tpc bit initial value read/write 0 r/w 7 nder7 0 r/w 6 nder6 0 r/w 5 nder5 0 r/w 4 nder4 0 r/w 3 nder3 0 r/w 2 nder2 0 r/w 1 nder1 0 r/w 0 nder0 next data enable 7 to 0 bits 7 to 0 nder7 to nder0 description tpc outputs tp 7 to tp 0 are disabled (ndr7 to ndr0 are not transferred to pa 7 to pa 0 ) tpc outputs tp 7 to tp 0 are enabled (ndr7 to ndr0 are transferred to pa 7 to pa 0 ) 0 1 725 ndrb ? next data register b h ? fffa4/h ? fffa6 tpc ? ? ? ? ? ? 726 ndra ? next data register a h ? fffa5/h ? fffa7 tpc ? ? ? ? ? ? 727 smr ? serial mode register h ? fffb0 sci0 bit initial value read/write 0 r/w 7 c/ a e 728 brr ? bit rate register h ? fffb1 sci0 bit initial value read/write 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 serial communication bit rate setting 729 scr ? serial control register h ? fffb2 sci0 bit initial value read/write 0 r/w 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 2 teie 0 r/w 1 cke1 0 r/w 0 cke0 clock enable 1 and 0 (for serial communication interface) bit 1 cke1 bit 0 cke0 asynchronous mode synchronous mode asynchronous mode synchronous mode asynchronous mode synchronous mode asynchronous mode synchronous mode 0 1 0 1 0 1 description transmit-end interrupt enable 0 1 transmit-end interrupt requests (tei) are disabled transmit-end interrupt requests (tei) are enabled receive interrupt enable 0 1 receive-data-full (rxi) and receive-error (eri) interrupt requests are disabled receive-data-full (rxi) and receive-error (eri) interrupt requests are enabled internal clock: sck pin available for generic i/o internal clock: sck pin used for serial clock output internal clock: sck pin used for clock output internal clock: sck pin used for serial clock output external clock: sck pin used for clock input external clock: sck pin used for serial clock input external clock: sck pin used for clock input external clock: sck pin used for serial clock input multiprocessor interrupt enable 0 1 multiprocessor interrupts are disabled (normal receive operation) multiprocessor interrupts are enabled receive enable 0 1 receiving is disabled receiving is enabled transmit enable 0 1 transmitting is disabled transmitting is enabled transmit interrupt enable 0 1 transmit-data-empty interrupt request (txi) is disabled transmit-data-empty interrupt request (txi) is enabled clock enable 1 and 0 (for smart card interface) smr gm bit 1 cke1 bit 0 cke0 0 0 1 0 1 0 1 0 1 0 1 description sck pin available for generic i/o sck pin used for clock output sck pin output fixed low sck pin used for clock output sck pin output fixed high sck pin used for clock output 730 tdr ? transmit data register h ? fffb3 sci0 bit initial value read/write 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 serial transmit data 731 ssr ? serial status register h ? fffb4 sci0 bit initial value read/write 1 r/(w) * 7 tdre 0 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 fer/ers 0 r/(w) * 3 per 1 r 2 tend 0 r 1 mpb 0 r/w 0 mpbt transmit end (for serial communication interface) 0 multiprocessor bit transfer 0 1 multiprocessor bit value in transmit data is 0 multiprocessor bit value in transmit data is 1 multiprocessor bit 0 1 multiprocessor bit value in receive data is 0 multiprocessor bit value in receive data is 1 [clearing condition] read tdre when tdre = 1, then write 0 in tdre. [setting conditions] reset or transition to standby mode te is cleared to 0 in scr. tdre is 1 when last bit of 1-byte serial character is transmitted. parity error 0 1 [clearing conditions] reset or transition to standby mode read per when per = 1, then write 0 in per. [setting condition] parity error (parity of receive data does not match parity setting of o/ e reset or transition to standby mode read fer when fer = 1, then write 0 in fer. [setting condition] framing error (stop bit is 0) error signal status (for smart card interface) 0 [clearing conditions] reset or transition to standby mode read ers when ers = 1, then write 0 in ers. [setting condition] a low error signal is received. 1 1 overrun error 0 [clearing conditions] reset or transition to standby mode read orer when orer = 1, then write 0 in orer. [setting condition] overrun error (reception of the next serial data ends when rdrf = 1) 1 receive data register full 0 [clearing conditions] reset or transition to standby mode read rdrf when rdrf = 1, then write 0 in rdrf. [setting condition] serial data is received normally and transferred from rsr to rdr. 1 transmit data register empty note: * only 0 can be written, to clear the flag. 0 [clearing condition] read tdre when tdre = 1, then write 0 in tdre. [setting conditions] reset or transition to standby mode te is 0 in scr. data is transferred from tdr to tsr, enabling new data to be written in tdr 1 1 transmit end (for smart card interface) 0 [clearing condition] read tdre when tdre = 1, then write 0 in tdre. [setting conditions] reset or transition to standby mode te is cleared to 0 in scr and fer/ers is cleared to 0. tdre is 1 and fer/ers is 0 (normal transmission) 2.5 etu* (when gm = 0) or 1.0 etu (when gm = 1) after 1-byte serial character is transmitted. 1 note: * etu: elementary time unit (time required to transmit one bit) 732 rdr ? receive data register h ? fffb5 sci0 bit initial value read/write 0 r 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 2 0 r 1 0 r 0 serial receive data 733 scmr ? smart card mode register h ? fffb6 sci0 1 7 1 6 1 5 1 4 0 r/w 3 sdir 0 r/w 2 sinv 1 1 0 r/w 0 smif smart card interface mode select 0 1 smart card interface function is disabled smart card interface function is enabled (initial value) smart card data invert 0 1 unmodified tdr contents are transmitted receive data is stored unmodified in rdr (initial value) inverted 1/0 logic levels of tdr contents are transmitted 1/0 logic levels of received data are inverted before storage in rdr smart card data transfer direction 0 1 tdr contents are transmitted lsb-first receive data is stored lsb-first in rdr (initial value) tdr contents are transmitted msb-first receive data is stored msb-first in rdr bit initial value read/write 734 smr ? serial mode register h ? fffb8 sci1 0 r/w 7 c/ a e 735 tdr ? transmit data register h ? fffbb sci1 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 bit initial value read/write note: bit functions are the same as for sci0. ssr ? serial status register h ? fffbc sci1 0 r/(w)* 7 tdre 0 r/(w)* 6 rdrf 0 r/(w)* 5 orer 0 r/(w)* 4 fer/ers 0 r/(w)* 3 per 1 r 2 tend 0 r 1 mpb 0 r/w 0 mpbt bit initial value read/write notes: bit functions are the same as for sci0. * only 0 can be written to clear the flag. rdr ? receive data register h ? fffbd sci1 0 r 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 2 0 r 1 0 r 0 bit initial value read/write note: bit functions are the same as for sci0. 736 scmr ? smart card mode register h ? fffbe sci1 0 r/w 7 0 r/w 6 1 5 0 r/w 43 sdir 2 sinv 1 1111 0 smif bit initial value read/write note: bit functions are the same as for sci0. 737 p1dr ? port 1 data register h ? fffd0 port 1 0 r/w 7 p1 7 0 r/w 6 p1 6 0 r/w 5 p1 5 0 r/w 4 p1 4 0 r/w 3 p1 3 0 r/w 2 p1 2 0 r/w 1 p1 1 0 r/w 0 p1 0 data for port 1 pins bit initial value read/write p2dr ? port 2 data register h ? fffd1 port 2 0 r/w 7 p2 7 0 r/w 6 p2 6 0 r/w 5 p2 5 0 r/w 4 p2 4 0 r/w 3 p2 3 0 r/w 2 p2 2 0 r/w 1 p2 1 0 r/w 0 p2 0 data for port 2 pins bit initial value read/write p3dr ? port 3 data register h ? fffd2 port 3 0 r/w 7 p3 7 0 r/w 6 p3 6 0 r/w 5 p3 5 0 r/w 4 p3 4 0 r/w 3 p3 3 0 r/w 2 p3 2 0 r/w 1 p3 1 0 r/w 0 p3 0 data for port 3 pins bit initial value read/write 738 p4dr ? port 4 data register h ? fffd3 port 4 0 r/w 7 p4 7 0 r/w 6 p4 6 0 r/w 5 p4 5 0 r/w 4 p4 4 0 r/w 3 p4 3 0 r/w 2 p4 2 0 r/w 1 p4 1 0 r/w 0 p4 0 data for port 4 pins bit initial value read/write p5dr ? port 5 data register h ? fffd4 port 5 1 7 1 6 1 5 1 4 0 r/w 3 p5 3 0 r/w 2 p5 2 0 r/w 1 p5 1 0 r/w 0 p5 0 data for port 5 pins bit initial value read/write p6dr ? port 6 data register h ? fffd5 port 6 1 r 7 p6 7 0 r/w 6 p6 6 0 r/w 5 p6 5 0 r/w 4 p6 4 0 r/w 3 p6 3 0 r/w 2 p6 2 0 r/w 1 p6 1 0 r/w 0 p6 0 data for port 6 pins bit initial value read/write 739 p7dr ? port 7 data register h ? fffd6 port 7 r 7 p7 7 r 6 p7 6 r 5 p7 5 r 4 p7 4 r 3 p7 3 r 2 p7 2 r 1 p7 1 r 0 p7 0 data for port 7 pins * * * * * * * * note: * determined by pins p7 7 to p7 0 . bit initial value read/write p8dr ? port 8 data register h ? fffd7 port 8 1 7 1 6 1 5 0 r/w 4 p8 4 0 r/w 3 p8 3 0 r/w 2 p8 2 0 r/w 1 p8 1 0 r/w 0 p8 0 data for port 8 pins bit initial value read/write 740 p9dr ? port 9 data register h ? fffd8 port 9 1 7 1 6 0 r/w 5 p9 5 0 r/w 4 p9 4 0 r/w 3 p9 3 0 r/w 2 p9 2 0 r/w 1 p9 1 0 r/w 0 p9 0 data for port 9 pins bit initial value read/write padr ? port a data register h ? fffd9 port a 0 r/w 7 pa 7 0 r/w 6 pa 6 0 r/w 5 pa 5 0 r/w 4 pa 4 0 r/w 3 pa 3 0 r/w 2 pa 2 0 r/w 1 pa 1 0 r/w 0 pa 0 data for port a pins bit initial value read/write pbdr ? port b data register h ? fffda port b 0 r/w 7 pb 7 0 r/w 6 pb 6 0 r/w 5 pb 5 0 r/w 4 pb 4 0 r/w 3 pb 3 0 r/w 2 pb 2 0 r/w 1 pb 1 0 r/w 0 pb 0 data for port b pins bit initial value read/write 741 addra h/l ? a/d data register a h/l h ? fffe0, h ? fffe1 a/d 0 r 15 ad9 a/d conversion data 10-bit data giving an a/d conversion result 0 r 14 ad8 0 r 13 ad7 0 r 12 ad6 0 r 11 ad5 0 r 10 ad4 0 r 9 ad3 0 r 8 ad2 0 r 7 ad1 0 r 6 ad0 0 r 5 0 r 4 0 r 3 0 r 2 0 r 1 0 r 0 addrah addral bit initial value read/write addrb h/l ? a/d data register b h/l h ? fffe2, h ? fffe3 a/d 0 r 15 ad9 0 r 14 ad8 0 r 13 ad7 0 r 12 ad6 0 r 11 ad5 0 r 10 ad4 0 r 9 ad3 0 r 8 ad2 0 r 7 ad1 0 r 6 ad0 0 r 5 0 r 4 0 r 3 0 r 2 0 r 1 0 r 0 addrbh addrbl a/d conversion data 10-bit data giving an a/d conversion result bit initial value read/write 742 addrc h/l ? a/d data register c h/l h ? fffe4, h ? fffe5 a/d 0 r 15 ad9 0 r 14 ad8 0 r 13 ad7 0 r 12 ad6 0 r 11 ad5 0 r 10 ad4 0 r 9 ad3 0 r 8 ad2 0 r 7 ad1 0 r 6 ad0 0 r 5 0 r 4 0 r 3 0 r 2 0 r 1 0 r 0 addrch addrcl a/d conversion data 10-bit data giving an a/d conversion result bit initial value read/write addrd h/l ? a/d data register d h/l h ? fffe6, h ? fffe7 a/d 0 r 15 ad9 0 r 14 ad8 0 r 13 ad7 0 r 12 ad6 0 r 11 ad5 0 r 10 ad4 0 r 9 ad3 0 r 8 ad2 0 r 7 ad1 0 r 6 ad0 0 r 5 0 r 4 0 r 3 0 r 2 0 r 1 0 r 0 addrdh addrdl a/d conversion data 10-bit data giving an a/d conversion result bit initial value read/write adcr ? a/d control register h ? fffe9 a/d 0 r/w 7 trge 1 6 1 5 1 4 1 3 1 2 1 1 0 r/w 0 trigger enable 0 1 a/d conversion start by external trigger or 8-bit timer compare match is disabled a/d conversion is started by falling edge of external trigger signal ( adtrg 743 adcsr ? a/d control/status register h ? fffe8 a/d 0 r/(w)* 7 adf 0 r/w 6 adie 0 r/w 5 adst 0 r/w 4 scan 0 r/w 3 cks 0 r/w 2 ch2 0 r/w 1 ch1 0 r/w 0 ch0 channel select 2 to 0 group selection 0 1 0 1 an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 0 ch2 1 0 1 0 1 0 1 0 1 description single mode scan mode clock select 0 1 conversion time = 134 states (maximum) conversion time = 70 states (maximum) channel selection ch1 ch0 an 0 an 0, an 1 an 0 to an 2 an 0 to an 3 an 4 an 4, an 5 an 4 to an 6 an 4 to an 7 scan mode 0 1 single mode scan mode a/d start 0 1 a/d conversion is stopped 1. single mode: a/d conversion starts; adst is automatically cleared to 0 when conversion ends 2. scan mode: a/d conversion starts and continues, cycling among the selected channels adst is cleared to 0 by software, by a reset, or by a transition to standby mode a/d interrupt enable 0 1 a/d end interrupt request is disabled a/d end interrupt request is enabled a/d end flag 0 [clearing condition] read adf when adf = 1, then write 0 in adf [setting conditions] single mode: a/d conversion ends scan mode: a/d conversion ends in all selected channels 1 note: * only 0 can be written to clear the flag. bit initial value read/write 744 appendix c i/o port block diagrams c.1 port 1 block diagram reset r p1 ddr n modes 1 to 4 wp1d q d c reset r p1 dr n wp1 qd c rp1 modes 6/7 modes 1 to 5 internal data bus (upper) internal address bus wp1d: wp1: rp1: ssoe: n = 0 to 7 write to p1ddr write to port 1 read port 1 software standby output port enable p1 n external bus released hardware standby software standby modes 6/7 ssoe figure c.1 port 1 block diagram 745 c.2 port 2 block diagram reset r p2 dr n wp2 qd c reset r p2 ddr n wp2d qd c reset r p2 pcr n wp2p qd c modes 6/7 modes 1 to 5 internal data bus (upper) internal address bus p2 n rp2p rp2 wp2p: rp2p: wp2d: wp2: rp2: ssoe: n = 0 to 7 write to p2pcr read p2pcr write to p2ddr write to port 2 read port 2 software standby output port enable external bus released hardware standby software standby modes 6/7 modes 1 to 4 ssoe figure c.2 port 2 block diagram 746 c.3 port 3 block diagram p3 n reset r p3 ddr n wp3d qd c reset r p3 dr n wp3 qd c rp3 modes 1 to 5 internal data bus (upper) wp3d: wp3: rp3: n = 0 to 7 write to p3ddr write to port 3 read port 3 modes 6/7 write to external address modes 6/7 hardware standby external bus released read external address internal data bus (lower) figure c.3 port 3 block diagram 747 c.4 port 4 block diagram p4 n rp4p rp4 wp4 wp4d wp4p reset reset reset qd r c p4 pcr n qd r c p4 ddr n qd r c p4 dr n wp4p: rp4p: wp4d: wp4: rp4: n = 0 to 7 write to p4pcr read p4pcr write to p4ddr write to port 4 read port 4 write to external address hardware standby external bus released read external address internal data bus (upper) internal data bus (lower) 8-bit bus mode modes 6/7 modes 1 to 5 16-bit bus mode figure c.4 port 4 block diagram 748 c.5 port 5 block diagram p5 n rp5p rp5 wp5 wp5d wp5p reset reset reset qd r c p5 pcr n qd r c p5 ddr n qd r c p5 dr n wp5p: rp5p: wp5d: wp5: rp5: ssoe: n = 0 to 3 write to p5pcr read p5pcr write to p5ddr write to port 5 read port 5 software standby output port enable modes 6/7 modes 1 to 5 internal data bus (upper) internal address bus external bus released hardware standby software standby modes 6/7 modes 1 to 4 ssoe figure c.5 port 5 block diagram 749 c.6 port 6 block diagrams wp6d: wp6: rp6: write to p6ddr write to port 6 read port 6 rp6 input wp6d reset qd r c p6 ddr 0 wp6 reset qd r c p6 dr 0 p6 0 internal data bus bus controller wait input enable bus controller wait modes 6/7 hardware standby figure c.6 (a) port 6 block diagram (pin p6 0 ) 750 p6 1 wp6d: wp6: rp6: write to p6ddr write to port 6 read port 6 wp6d reset qd r c p6 ddr 1 wp6 reset qd r c p6 dr 1 rp6 internal data bus bus controller bus release enable breq input modes 6/7 hardware standby figure c.6 (b) port 6 block diagram (pin p6 1 ) 751 wp6d reset hardware standby qd r c p6 ddr 2 wp6 reset qd r c p6 dr 2 rp6 p6 2 wp6d: wp6: rp6: write to p6ddr write to port 6 read port 6 internal data bus bus controller bus release enable back output modes 6/7 figure c.6 (c) port 6 block diagram (pin p6 2 ) 752 p6 n reset r p6 ddr n wp6d modes 6/7 qd c reset r p6 dr n wp6 qd c rp6 modes 1 to 5 internal data bus wp6d: wp6: rp6: ssoe: n = 3 to 6 write to p6ddr write to port 6 read port 6 software standby output port enable modes 6/7 as output rd output hwr output lwr output bus controller external bus released hardware standby software standby modes 6/7 ssoe figure c.6 (d) port 6 block diagram (pins p6 3 to p6 6 ) 753 read port 6 rp6: hardware standby rp6 p6 7 figure c.6 (e) port 6 block diagram (pin p6 7 ) 754 c.7 port 7 block diagrams p7 n rp7 rp7: read port 7 n = 0 to 5 internal data bus a/d converter input enable channel select signal analog input figure c.7 (a) port 7 block diagram (pins p7 0 to p7 5 ) p7 n rp7 rp7: read port 7 n = 6 and 7 internal data bus d/a converter analog output output enable a/d converter input enable channel select signal analog input figure c.7 (b) port 7 block diagram (pins p7 6 and p7 7 ) 755 c.8 port 8 block diagrams p8 0 rp8 wp8d reset qd r c p8 ddr 0 wp8 reset qd r c p8 dr 0 wp8d: wp8: rp8: write to p8ddr write to port 8 read port 8 internal data bus interrupt controller input irq 0 figure c.8 (a) port 8 block diagram (pin p8 0 ) 756 p8 n wp8d reset qd r c p8 ddr n wp8 reset qd r c p8 dr n rp8 wp8d: wp8: rp8: ssoe: n = 1, 2 write to p8ddr write to port 8 read port 8 software standby output port enable internal data bus bus controller output interrupt controller irq irq cs cs 2 3 1 2 input modes 6/7 modes 1 to 5 modes 6/7 ssoe software standby external bus released hardware standby figure c.8 (b) port 8 block diagram (pins p8 1 and p8 2 ) 757 a/d converter wp8d p8 3 dr c qd write to p8ddr write to port 8 read port 8 software standby output port enable wp8d: wp8: rp8: ssoe: wp8 r reset internal data bus rp8 p8 3 bus controller cs 1 output reset modes 6/7 modes 1 to 5 interrupt controller irq 3 input adtrg input p8 3 ddr c qd r modes 6/7 ssoe software standby external bus released hardware standby figure c.8 (c) port 8 block diagram (pin p8 3 ) 758 p8 4 wp8d qd s c p8 ddr 4 wp8 reset reset modes 1 to 4 qd r c p8 dr 4 rp8 wp8d: wp8: rp8: ssoe: write to p8ddr write to port 8 read port 8 software standby output port enable internal data bus bus controller output 0 cs modes 6/7 modes 1 to 5 r modes 6/7 ssoe software standby external bus released hardware standby figure c.8 (d) port 8 block diagram (pin p8 4 ) 759 c.9 port 9 block diagrams wp9d: wp9: rp9: write to p9ddr write to port 9 read port 9 p9 0 rp9 wp9d reset hardware standby qd r c p9 ddr 0 wp9 reset qd r c p9 dr 0 internal data bus sci output enable serial transmit data guard time figure c.9 (a) port 9 block diagram (pin p9 0 ) 760 wp9d: wp9: rp9: write to p9ddr write to port 9 read port 9 p9 1 rp9 wp9d reset qd r c p9 ddr 1 wp9 reset qd r c p9 dr 1 internal data bus sci output enable serial transmit data guard time hardware standby figure c.9 (b) port 9 block diagram (pin p9 1 ) 761 wp9d: wp9: rp9: write to p9ddr write to port 9 read port 9 p9 2 wp9d reset qd r c p9 ddr 2 wp9 reset qd r c p9 dr 2 rp9 internal data bus input enable serial receive data sci hardware standby figure c.9 (c) port 9 block diagram (pin p9 2 ) 762 p9 3 ddr c qd wp9d rp9 p9 3 dr c qd p9 3 serial receive data input enable write to p9ddr write to port 9 read port 9 wp9d: wp9: rp9: wp9 r r reset internal data bus reset sci hardware standby figure c.9 (d) port 9 block diagram (pin p9 3 ) 763 wp9d: wp9: rp9: write to p9ddr write to port 9 read port 9 wp9d hardware standby reset qd r c p9 ddr 4 wp9 reset qd r c p9 dr 4 rp9 p9 4 internal data bus sci clock input enable clock output enable clock output clock input interrupt controller input irq 4 figure c.9 (e) port 9 block diagram (pin p9 4 ) 764 r p9 5 ddr c qd reset wp9d wp9 rp9 r p9 5 dr c qd reset p9 5 sci clock input enable clock output enable clock output interrupt controller irq 5 input clock input : write to p9ddr : write to port 9 : read port 9 wp9d wp9 rp9 internal data bus hardware standby figure c.9 (f) port 9 block diagram (pin p9 5 ) 765 c.10 port a block diagrams wpad: wpa: rpa: n = 0 and 1 write to paddr write to port a read port a pa n wpad reset hardware standby qd r c pa ddr n reset qd r c pa dr n rpa wpa internal data bus tpc output enable tpc next data output trigger counter clock input 16-bit timer counter clock input 8-bit timer figure c.10 (a) port a block diagram (pins pa 0 and pa 1 ) 766 wpad: wpa: rpa: n = 2 and 3 write to paddr write to port a read port a pa n rpa wpa wpad reset qd r c pa ddr n reset qd r c pa dr n internal data bus tpc output enable tpc next data output trigger output enable compare match output input capture counter clock input 16-bit timer counter clock input 8-bit timer hardware standby figure c.10 (b) port a block diagram (pins pa 2 and pa 3 ) 767 wpad: wpa: rpa: ssoe: n = 4 to 7 note: the pa 7 address output enable setting is fixed at 1 in modes 3 and 4. write to paddr write to port a read port a software standby output port enable pa n wpad reset rpa wpa qd r c pa n ddr reset qd r c pa n dr internal address bus internal data bus tpc 16-bit timer tpc output enable next data output trigger output enable compare match output input capture software standby ssoe bus released modes 3/4 address output enable hardware standby figure c.10 (c) port a block diagram (pins pa 4 to pa 7 ) 768 c.11 port b block diagrams pbn wpbd: wpb: rpb: ssoe: n = 0 , 2 write to pbddr write to port b read port b software standby output port enable reset qd r c pb ddr n wpbd reset qd r c pb dr n wpb rpb internal data bus tpc output enable tpc next data output trigger output enable compare match output 8-bit timer modes 1 to 5 bus released bus controller cs output enable cs7 cs5 output software standby hardware standby ssoe figure c.11 (a) port b block diagram (pins pb 0 and pb 2 ) 769 r pb n ddr c qd reset modes 1 to 5 wpbd wpb rpb r pb n dr c qd reset pb n tpc 8-bit timer tpc output enable bus controller cs output enable cs6 cs4 output next data output trigger output enable compare match output tmo2 tmo3 input write to pbddr write to port b read port b software standby output port enable wpbd: wpb: rpb: ssoe: n = 1, 3 bus released software standby ssoe internal data bus hardware standby figure c.11 (b) port b block diagram (pins pb 1 and pb 3 ) 770 pb 4 wpbd: wpb: rpb: write to pbddr write to port b read port b wpb rpb reset qd r c pb ddr hardware standby 4 wpbd reset qd r c pb dr 4 internal data bus tpc output enable next data output trigger tpc figure c.11 (c) port b block diagram (pin pb 4 ) 771 r pb 5 ddr c qd reset wpbd wpb rpb r pb 5 dr c qd reset pb 5 tpc tpc output enable next data output trigger write to pbddr write to port b read port b wpbd: wpb: rpb: internal data bus hardware standby figure c.11 (d) port b block diagram (pin pb 5 ) 772 wpbd reset reset qd r c pb ddr qd r c pb dr 6 rpb wpb tpc wpbd: wpb: rpb: write to pbddr write to port b read port b tpc output enable next data output trigger internal data bus 6 pb 6 hardware standby figure c.11 (e) port b block diagram (pin pb 6 ) 773 pb 7 wpbd reset reset qd r c pb ddr qd r c pb dr 7 rpb wpb tpc wpbd: wpb: rpb: write to pbddr write to port b read port b tpc output enable next data output trigger internal data bus 7 hardware standby figure c.11 (f) port b block diagram (pin pb 7 ) 774 appendix d pin states d.1 port states in each mode table d.1 port states pin name mode reset hardware standby mode software standby mode bus- released mode program execution mode reso 775 pin name mode reset hardware standby mode software standby mode bus- released mode program execution, mode p5 3 to p5 0 1 to 4 l t (ssoe = 0) t (ssoe = 1) keep t a 19 to a 16 5tt (ddr = 0) keep ( ddr=1,ssoe=0 ) t ( ddr=1,ssoe=1 ) keep t (ddr = 0) input port (ddr = 1) a 19 to a 16 6, 7 t t keep ? i/o port p6 0 1 to 5 t t keep keep i/o port wait breq back as rd hwr lwr cs 776 pin name mode reset hardware standby mode software standby mode bus- released mode program execution mode p8 2 1 to 5 t t (ddr=0) t (ddr=1, ssoe=0) t (ddr=1, ssoe=1) h (ddr=0) keep (ddr=1) t (ddr=0) input port (ddr=1) cs cs cs cs 777 pin name mode reset hardware standby mode software standby mode bus- released mode program execution mode pa 7 1, 2 t t keep keep i/o port 3, 4 l t (ssoe = 0) t (ssoe = 1) keep ta 20 5tt (address output)* 4 (ssoe = 0) t (ssoe = 1) keep (otherwise)* 5 keep (address output)* 4 t (otherwise)* 5 keep (address output)* 4 a 20 (otherwise)* 5 i/o port 6, 7 t t keep ? i/o port pb 3 to pb 0 1 to 5 t t (cs output)* 6 (ssoe = 0) t (ssoe = 1) h (otherwise)* 7 keep (cs output)* 6 t (otherwise)* 7 keep (cs output)* 6 cs cs reso 778 d.2 pin states at reset modes 1 and 2: figure d.1 is a timing diagram for the case in which res goes low during an external memory access in mode 1 or 2. as soon as res goes low, all ports are initialized to the input state. as , rd , hwr , lwr , and cs 0 go high, and d 15 to d 0 go to the high-impedance state. the address bus is initialized to the low output level 2.5 clock cycles after the low level of res is sampled. clock pin p6 7 / goes to the output state at the next rise of after res goes low. as , rd (read) d 15 to d 0 (write) hwr , lwr (write) internal reset signal res p6 7 / i/o port, cs 7 to cs 1 cs 0 a 19 to a 0 t1 t2 t3 access to external memory h'00000 high impedance high impedance figure d.1 reset during memory access (modes 1 and 2) 779 modes 3 and 4: figure d.2 is a timing diagram for the case in which res goes low during an external memory access in mode 3 or 4. as soon as res goes low, all ports are initialized to the input state. as , rd , hwr , lwr , and cs 0 go high, and d 15 to d 0 go to the high-impedance state. the address bus is initialized to the low output level 2.5 clock cycles after the low level of res is sampled. however, when pa 4 to pa 6 are used as address bus pins, or when p8 3 to p8 1 and pb 0 to pb 3 are used as cs output pins, they go to the high-impedance state at the same time as res goes low. clock pin p6 7 / goes to the output state at the next rise of after res goes low. t1 t2 t3 access to external memory h'00000 high impedance high impedance as , rd (read) d 15 to d 0 (write) hwr , lwr (write) internal reset signal res p6 7 / i/o port, pa 4 /a 23 to pa 6 /a 21 , cs 7 to cs 1 cs 0 a 20 to a 0 figure d.2 reset during memory access (modes 3 and 4) mode 5: figure d.3 is a timing diagram for the case in which res goes low during an external memory access in mode 5. as soon as res goes low, all ports are initialized to the input state. as , rd , hwr , and lwr go high, and the address bus and d 15 to d 0 go to the high-impedance state. clock pin p6 7 / goes to the output state at the next rise of after res goes low. 780 t1 t2 t3 access to external memory high impedance high impedance high impedance as , rd (read) d 15 to d 0 (write) hwr , lwr (write) internal reset signal res p6 7 / i/o port, cs 7 to cs 1 a 23 to a 0 figure d.3 reset during memory access (mode 5) modes 6 and 7: figure d.4 is a timing diagram for the case in which res goes low during an operation mode 6 or 7. as soon as res goes low, all ports are initialized to the input state. clock pin p6 7 / goes to the output state at the next rise of after res goes low. internal reset signal res p6 7 / i/o port high impedance figure d.4 reset during operation (modes 6 and 7) 781 appendix e timing of transition to and recovery from hardware standby mode timing of transition to hardware standby mode 1. to retain ram contents with the rame bit set to 1 in syscr, drive the res signal low 10 system clock cycles before the stby signal goes low, as shown below. res must remain low until stby goes low (minimum delay from stby low to res high: 0 ns). t 1 10t cyc t 2 0 ns stby res 2. to retain ram contents with the rame bit cleared to 0 in syscr, res does not have to be driven low as in (1). timing of recovery from hardware standby mode: drive the res signal low approximately 100 ns before stby goes high. stby res t 100 ns t osc 782 appendix f product code lineup table f.1 h8/3024 series product type product code mark code package (hitachi package code) h8/3026 mask rom version on-chip mask rom 3.3 v operation hd6433026f hd6433026te hd6433026fp hd6433026( *** )f hd6433026( *** )te hd6433026( *** )fp 100-pin qfp (fp-100b) 100-pin tqfp (tfp-100b) 100-pin qfp (fp-100a) h8/3024 mask rom version on-chip mask rom 3.3 v operation hd6433024f hd6433024te hd6433024fp hd6433024( *** )f hd6433024( *** )te hd6433024( *** )fp 100-pin qfp (fp-100b) 100-pin tqfp (tfp-100b) 100-pin qfp (fp-100a) h8/3026 f-ztat on-chip flash memory 3.3 v operation hd64f3026f hd64f3026te hd64f3026fp hd64f3026f hd64f3026te hd64f3026fp 100-pin qfp (fp-100b) 100-pin tqfp (tfp-100b) 100-pin qfp (fp-100a) h8/3024 f-ztat on-chip flash memory 3.3 v operation HD64F3024f HD64F3024te HD64F3024fp HD64F3024f HD64F3024te HD64F3024fp 100-pin qfp (fp-100b) 100-pin tqfp (tfp-100b) 100-pin qfp (fp-100a) note: for mask rom versions, ( *** ) is the rom code. 783 appendix g package dimensions figure g.1 shows the fp-100b package dimensions of the h8/3024 series. figure g.2 shows the tfp-100b package dimensions. figure g.3 shows the fp-100a package dimensions. hitachi code jedec jeita mass (reference value) fp-100b ? conforms 1.2 g *dimension including the plating thickness base material dimension 0.10 16.0 0.3 1.0 0.5 0.2 16.0 0.3 3.05 max 75 51 50 26 1 25 76 100 14 0 e 8 0.5 0.08 m *0.22 0.05 2.70 *0.17 0.05 0.12 + 0.13 ? 0.12 1.0 0.20 0.04 0.15 0.04 unit: mm figure g.1 package dimensions (fp-100b) 784 hitachi code jedec jeita mass (reference value) tfp-100b ? conforms 0.5 g *dimension including the plating thickness base material dimension 16.0 0.2 14 0.08 0.10 0.5 0.1 16.0 0.2 0.5 0.10 0.10 1.20 max *0.17 0.05 0 e 8 75 51 125 76 100 26 50 m *0.22 0.05 1.0 1.00 1.0 0.20 0.04 0.15 0.04 unit: mm figure g.2 package dimensions (tfp-100b) 785 hitachi code jedec jeita mass (reference value) fp-100a ? ? 1.7 g *dimension including the plating thickness base material dimension 0.13 m 0 e 10 *0.32 0.08 *0.17 0.05 3.10 max 1.2 0.2 24.8 0.4 20 80 51 50 31 30 1 100 81 18.8 0.4 14 0.15 0.65 2.70 2.4 0.20 + 0.10 ? 0.20 0.58 0.83 0.30 0.06 0.15 0.04 unit: mm figure g.3 package dimensions (fp-100a) 786 appendix h comparison of h8/300h series product specifications h.1 comparison of pin functions of 100-pin package products (fp-100b, tfp-100b) table h.1 pin arrangement of each product (fp-100b, tfp-100b) on-chip-rom products romless products pin no. h8/3067 series h8/3062 series, h8/3024 series h8/3048 series h8/3042 series h8/3006, h8/3007 h8/3002 1 v cc v cc /v cl * 2 v cc v cc v cc v cc 2 pb 0 /tp 8 /tmo 0 / cs 7 pb 0 /tp 8 /tmo 0 / cs 7 pb 0 /tp 8 / tioca 3 pb 0 /tp 8 / tioca 3 pb 0 /tp 8 /tmo 0 / cs 7 pb 0 /tp 8 / tioca 3 3 pb 1 /tp 9 /tmio 1 / dreq 0 / cs 6 pb 1 /tp 9 /tmio 1 / cs 6 pb 1 /tp 9 / tiocb 3 pb 1 /tp 9 / tiocb 3 pb 1 /tp 9 /tmio 1 / dreq 0 / cs 6 pb 1 /tp 9 / tiocb 3 4 pb 2 /tp 10 /tmo 2 / cs 5 pb 2 /tp 10 /tmo 2 / cs 5 pb 2 /tp 10 / tioca 4 pb 2 /tp 10 / tioca 4 pb 2 /tp 10 /tmo 2 / cs 5 pb 2 /tp 10 / tioca 4 5 pb 3 /tp 11 / tmio 3 / dreq 1 / cs 4 pb 3 /tp 11 / tmio 3 / cs 4 pb 3 /tp 11 / tiocb 4 pb 3 /tp 11 / tiocb 4 pb 3 /tp 11 / tmio 3 / dreq 1 / cs 4 pb 3 /tp 11 / tiocb 4 6 pb 4 /tp 12 / ucas pb 4 /tp 12 pb 4 /tp 12 / tocxa 4 pb 4 /tp 12 / tocxa 4 pb 4 /tp 12 / ucas pb 4 /tp 12 / tocxa 4 7 pb 5 /tp 13 / lcas /sck 2 pb 5 /tp 13 pb 5 /tp 13 / tocxb 4 pb 5 /tp 13 / tocxb 4 pb 5 /tp 13 / lcas /sck 2 pb 5 /tp 13 / tocxb 4 8 pb 6 /tp 14 /txd 2 pb 6 /tp 14 pb 6 /tp 14 / dreq 0 / cs 7 pb 6 /tp 14 / dreq 0 pb 6 /tp 14 /txd 2 pb 6 /tp 14 / dreq 0 9 pb 7 /tp 15 /rxd 2 pb 7 /tp 15 pb 7 /tp 15 / dreq 1 / adtrg pb 7 /tp 15 / dreq 1 / adtrg pb 7 /tp 15 /rxd 2 pb 7 /tp 15 / dreq 1 / adtrg 10 reso /fwe* 1 reso /fwe* 1 reso /v pp reso reso reso 11 vss vss vss vss vss vss 12 p9 0 /txd 0 p9 0 /txd 0 p9 0 /txd 0 p9 0 /txd 0 p9 0 /txd 0 p9 0 /txd 0 13 p9 1 /txd 1 p9 1 /txd 1 p9 1 /txd 1 p9 1 /txd 1 p9 1 /txd 1 p9 1 /txd 1 14 p9 2 /rxd 0 p9 2 /rxd 0 p9 2 /rxd 0 p9 2 /rxd 0 p9 2 /rxd 0 p9 2 /rxd 0 15 p9 3 /rxd 1 p9 3 /rxd 1 p9 3 /rxd 1 p9 3 /rxd 1 p9 3 /rxd 1 p9 3 /rxd 1 16 p9 4 /sck 0 / irq 4 p9 4 /sck 0 / irq 4 p9 4 /sck 0 / irq 4 p9 4 /sck 0 / irq 4 p9 4 /sck 0 / irq 4 p9 4 /sck 0 / irq 4 17 p9 5 /sck 1 / irq 5 p9 5 /sck 1 / irq 5 p9 5 /sck 1 / irq 5 p9 5 /sck 1 / irq 5 p9 5 /sck 1 / irq 5 p9 5 /sck 1 / irq 5 18 p4 0 /d 0 p4 0 /d 0 p4 0 /d 0 p4 0 /d 0 p4 0 /d 0 p4 0 /d 0 19 p4 1 /d 1 p4 1 /d 1 p4 1 /d 1 p4 1 /d 1 p4 1 /d 1 p4 1 /d 1 787 on-chip-rom products romless products pin no. h8/3067 series h8/3062 series, h8/3024 series h8/3048 series h8/3042 series h8/3006, h8/3007 h8/3002 20 p4 2 /d 2 p4 2 /d 2 p4 2 /d 2 p4 2 /d 2 p4 2 /d 2 p4 2 /d 2 21 p4 3 /d 3 p4 3 /d 3 p4 3 /d 3 p4 3 /d 3 p4 3 /d 3 p4 3 /d 3 22 vss vss vss vss vss vss 23 p4 4 /d 4 p4 4 /d 4 p4 4 /d 4 p4 4 /d 4 p4 4 /d 4 p4 4 /d 4 24 p4 5 /d 5 p4 5 /d 5 p4 5 /d 5 p4 5 /d 5 p4 5 /d 5 p4 5 /d 5 25 p4 6 /d 6 p4 6 /d 6 p4 6 /d 6 p4 6 /d 6 p4 6 /d 6 p4 6 /d 6 26 p4 7 /d 7 p4 7 /d 7 p4 7 /d 7 p4 7 /d 7 p4 7 /d 7 p4 7 /d 7 27 p3 0 /d 8 p3 0 /d 8 p3 0 /d 8 p3 0 /d 8 d 8 d 8 28 p3 1 /d 9 p3 1 /d 9 p3 1 /d 9 p3 1 /d 9 d 9 d 9 29 p3 2 /d 10 p3 2 /d 10 p3 2 /d 10 p3 2 /d 10 d 10 d 10 30 p3 3 /d 11 p3 3 /d 11 p3 3 /d 11 p3 3 /d 11 d 11 d 11 31 p3 4 /d 12 p3 4 /d 12 p3 4 /d 12 p3 4 /d 12 d 12 d 12 32 p3 5 /d 13 p3 5 /d 13 p3 5 /d 13 p3 5 /d 13 d 13 d 13 33 p3 6 /d 14 p3 6 /d 14 p3 6 /d 14 p3 6 /d 14 d 14 d 14 34 p3 7 /d 15 p3 7 /d 15 p3 7 /d 15 p3 7 /d 15 d 15 d 15 35 vcc vcc vcc vcc vcc vcc 36 p1 0 /a 0 p1 0 /a 0 p1 0 /a 0 p1 0 /a 0 a 0 a 0 37 p1 1 /a 1 p1 1 /a 1 p1 1 /a 1 p1 1 /a 1 a 1 a 1 38 p1 2 /a 2 p1 2 /a 2 p1 2 /a 2 p1 2 /a 2 a 2 a 2 39 p1 3 /a 3 p1 3 /a 3 p1 3 /a 3 p1 3 /a 3 a 3 a 3 40 p1 4 /a 4 p1 4 /a 4 p1 4 /a 4 p1 4 /a 4 a 4 a 4 41 p1 5 /a 5 p1 5 /a 5 p1 5 /a 5 p1 5 /a 5 a 5 a 5 42 p1 6 /a 6 p1 6 /a 6 p1 6 /a 6 p1 6 /a 6 a 6 a 6 43 p1 7 /a 7 p1 7 /a 7 p1 7 /a 7 p1 7 /a 7 a 7 a 7 44 vss vss vss vss vss vss 45 p2 0 /a 8 p2 0 /a 8 p2 0 /a 8 p2 0 /a 8 a 8 a 8 46 p2 1 /a 9 p2 1 /a 9 p2 1 /a 9 p2 1 /a 9 a 9 a 9 47 p2 2 /a 10 p2 2 /a 10 p2 2 /a 10 p2 2 /a 10 a 10 a 10 48 p2 3 /a 11 p2 3 /a 11 p2 3 /a 11 p2 3 /a 11 a 11 a 11 49 p2 4 /a 12 p2 4 /a 12 p2 4 /a 12 p2 4 /a 12 a 12 a 12 50 p2 5 /a 13 p2 5 /a 13 p2 5 /a 13 p2 5 /a 13 a 13 a 13 51 p2 6 /a 14 p2 6 /a 14 p2 6 /a 14 p2 6 /a 14 a 14 a 14 52 p2 7 /a 15 p2 7 /a 15 p2 7 /a 15 p2 7 /a 15 a 15 a 15 788 on-chip-rom products romless products pin no. h8/3067 series h8/3062 series, h8/3024 series h8/3048 series h8/3042 series h8/3006, h8/3007 h8/3002 53 p5 0 /a 16 p5 0 /a 16 p5 0 /a 16 p5 0 /a 16 a 16 a 16 54 p5 1 /a 17 p5 1 /a 17 p5 1 /a 17 p5 1 /a 17 a 17 a 17 55 p5 2 /a 18 p5 2 /a 18 p5 2 /a 18 p5 2 /a 18 a 18 a 18 56 p5 3 /a 19 p5 3 /a 19 p5 3 /a 19 p5 3 /a 19 a 19 a 19 57 vss vss vss vss vss vss 58 p6 0 / wait p6 0 / wait p6 0 / wait p6 0 / wait p6 0 / wait p6 0 / wait 59 p6 1 / breq p6 1 / breq p6 1 / breq p6 1 / breq p6 1 / breq p6 1 / breq 60 p6 2 / back p6 2 / back p6 2 / back p6 2 / back p6 2 / back p6 2 / back 61 p6 7 / p6 7 / p6 7 / 62 stby stby stby stby stby stby 63 res res res res res res 64 nmi nmi nmi nmi nmi nmi 65 vss vss vss vss vss vss 66 extal extal extal extal extal extal 67 xtal xtal xtal xtal xtal xtal 68 vcc vcc vcc vcc vcc vcc 69 p6 3 / as p6 3 / as p6 3 / as p6 3 / as as as 70 p6 4 / rd p6 4 / rd p6 4 / rd p6 4 / rd rd rd 71 p6 5 / hwr p6 5 / hwr p6 5 / hwr p6 5 / hwr hwr hwr 72 p6 6 / lwr p6 6 / lwr p6 6 / lwr p6 6 / lwr lwr lwr 73 md 0 md 0 md 0 md 0 md 0 md 0 74 md 1 md 1 md 1 md 1 md 1 md 1 75 md 2 md 2 md 2 md 2 md 2 md 2 76 avcc avcc avcc avcc avcc avcc 77 v ref v ref v ref v ref v ref v ref 78 p7 0 /an 0 p7 0 /an 0 p7 0 /an 0 p7 0 /an 0 p7 0 /an 0 p7 0 /an 0 79 p7 1 /an 1 p7 1 /an 1 p7 1 /an 1 p7 1 /an 1 p7 1 /an 1 p7 1 /an 1 80 p7 2 /an 2 p7 2 /an 2 p7 2 /an 2 p7 2 /an 2 p7 2 /an 2 p7 2 /an 2 81 p7 3 /an 3 p7 3 /an 3 p7 3 /an 3 p7 3 /an 3 p7 3 /an 3 p7 3 /an 3 82 p7 4 /an 4 p7 4 /an 4 p7 4 /an 4 p7 4 /an 4 p7 4 /an 4 p7 4 /an 4 83 p7 5 /an 5 p7 5 /an 5 p7 5 /an 5 p7 5 /an 5 p7 5 /an 5 p7 5 /an 5 84 p7 6 /an 6 /da 0 p7 6 /an 6 /da 0 p7 6 /an 6 /da 0 p7 6 /an 6 /da 0 p7 6 /an 6 /da 0 p7 6 /an 6 85 p7 7 /an 7 /da 1 p7 7 /an 7 /da 1 p7 7 /an 7 /da 1 p7 7 /an 7 /da 1 p7 7 /an 7 /da 1 p7 7 /an 7 789 on-chip-rom products romless products pin no. h8/3067 series h8/3062 series, h8/3024 series h8/3048 series h8/3042 series h8/3006, h8/3007 h8/3002 86 avss avss avss avss avss avss 87 p8 0 / rfsh / irq 0 p8 0 / irq 0 p8 0 / rfsh / irq 0 p8 0 / rfsh / irq 0 p8 0 / rfsh / irq 0 p8 0 / rfsh / irq 0 88 p8 1 / cs 3 / irq 1 p8 1 / cs 3 / irq 1 p8 1 / cs 3 / irq 1 p8 1 / cs 3 / irq 1 p8 1 / cs 3 / irq 1 p8 1 / cs 3 / irq 1 89 p8 2 / cs 2 / irq 2 p8 2 / cs 2 / irq 2 p8 2 / cs 2 / irq 2 p8 2 / cs 2 / irq 2 p8 2 / cs 2 / irq 2 p8 2 / cs 2 / irq 2 90 p8 3 / cs 1 / irq 3 / adtrg p8 3 / cs 1 / irq 3 / adtrg p8 3 / cs 1 / irq 3 p8 3 / cs 1 / irq 3 p8 3 / cs 1 / irq 3 / adtrg p8 3 / cs 1 / irq 3 91 p8 4 / cs 0 p8 4 / cs 0 p8 4 / cs 0 p8 4 / cs 0 p8 4 / cs 0 p8 4 / cs 0 92 vss vss vss vss vss vss 93 pa 0 /tp 0 / tend 0 /tclka pa 0 /tp 0 /tclka pa 0 /tp 0 / tend 0 /tclka pa 0 /tp 0 / tend 0 /tclka pa 0 /tp 0 / tend 0 /tclka pa 0 /tp 0 / tend 0 /tclka 94 pa 1 /tp 1 / tend 1 /tclkb pa 1 /tp 1 /tclkb pa 1 /tp 1 / tend 1 /tclkb pa 1 /tp 1 / tend 1 /tclkb pa 1 /tp 1 / tend 1 /tclkb pa 1 /tp 1 / tend 1 /tclkb 95 pa 2 /tp 2 / tioca 0 /tclkc pa 2 /tp 2 / tioca 0 /tclkc pa 2 /tp 2 / tioca 0 /tclkc pa 2 /tp 2 / tioca 0 /tclkc pa 2 /tp 2 / tioca 0 /tclkc pa 2 /tp 2 / tioca 0 /tclkc 96 pa 3 /tp 3 / tiocb 0 /tclkd pa 3 /tp 3 / tiocb 0 /tclkd pa 3 /tp 3 / tiocb 0 /tclkd pa 3 /tp 3 / tiocb 0 /tclkd pa 3 /tp 3 / tiocb 0 /tclkd pa 3 /tp 3 / tiocb 0 /tclkd 97 pa 4 /tp 4 / tioca 1 /a 23 pa 4 /tp 4 / tioca 1 /a 23 pa 4 /tp 4 / tioca 1 / cs 6 /a 23 pa 4 /tp 4 / tioca 1 /a 23 pa 4 /tp 4 / tioca 1 /a 23 pa 4 /tp 4 / tioca 1 /a 23 98 pa 5 /tp 5 / tiocb 1 /a 22 pa 5 /tp 5 / tiocb 1 /a 22 pa 5 /tp 5 / tiocb 1 / cs 5 /a 22 pa 5 /tp 5 / tiocb 1 /a 22 pa 5 /tp 5 / tiocb 1 /a 22 pa 5 /tp 5 / tiocb 1 /a 22 99 pa 6 /tp 6 / tioca 2 /a 21 pa 6 /tp 6 / tioca 2 /a 21 pa 6 /tp 6 / tioca 2 / cs 4 /a 21 pa 6 /tp 6 / tioca 2 /a 21 pa 6 /tp 6 / tioca 2 /a 21 pa 6 /tp 6 / tioca 2 /a 21 100 pa 7 /tp 7 / tiocb 2 /a 20 pa 7 /tp 7 / tiocb 2 /a 20 pa 7 /tp 7 / tiocb 2 /a 20 pa 7 /tp 7 / tiocb 2 /a 20 pa 7 /tp 7 / tiocb 2 /a 20 pa 7 /tp 7 / tiocb 2 /a 20 notes: *1 functions as reso in the mask rom versions, and as fwe in the on-chip flash memory versions. *2 functions as the v cl pin in the h8/3064f-ztat and mask rom b-mask versions and the h8/3062f-ztat and mask rom b-mask versions, and requires an external capacitor (0.1 f). functions as the v cc pin in the h8/3024 series. 790 h8/3024 series, h8/3024f-ztat , h8/3026f-ztat hardware manual publication date: 1st edition, march 2002 published by: business planning division semiconductor & integrated circuits hitachi, ltd. edited by: technical documentation group hitachi kodaira semiconductor co., ltd. copyright ? hitachi, ltd., 2002. all rights reserved. printed in japan. |
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