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digital btsc encoder with integrated adc and dac ad1970 rev. 0 in fo rmation furn is h e d by an al o g dev i ces is believed to be a ccu rate and r e liable. how e ver, no r e spons i bili ty is assumed by analog devices fo r its use, nor f o r an y i n fri n geme nt s of p a t e nt s or ot her ri g h t s o f th ird parties th at may result fro m its use . specifications subject to chan g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot he rwi s e un der a n y p a t e nt or p a t e nt r i ghts of anal og de vices. trad emarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 461. 31 13 ? 2005 analog de vices, i n c. al l r i ght s r e ser v ed . fea t ures complete btsc encoder pilot tone generator includes subca rrier modulat i on channel separ a tion: 30 db bandwidth up to 14 khz stereo analog or digital input phat-stereo? a l gorithm for stereo image en hancement dialog enhancement function for playing w i de d y namic range vid e o sources over bui l t-in tv speaker s includes l ? r dual-band compressor i 2 c port for con t rol of modes, effects, and parameters analog input performance 74 db dynamic range ?72 db thd + n digital input performance 87 db dynamic range ?83 db thd + n integrated op amps for analog inputs and o u tputs single-ende d output re duces external part c o unt integrated pll generates al l cl ocks from com p osite video, 48 kh z sample clock, or high speed master clock sync stripper to recover vide o clock from composite video signal output level control for setting aural carri er deviat ion macrovision ? -compliant do lby ? rf mo de-compatible 48-pin lqfp plastic package applic ati o ns digital set top box dvd pl ayer dvd r e co rder general description the ad1970 is a co m p lete a n al og o r dig i tal-in, a n alog-o u t b t sc e n co der w h ich i n cl udes p i lo t-ton e ge ner a t i o n an d sub - ca r r i er mixin g f u n c t i o n s. th e s t er e o ad c p r o v ides t h e m e a n s fo r dig i t i z a t i on o f t h e a n a l o g b a s e b a nd a u dio si g n a l . a b u i l t-i n h i g h p e r f or m a nc e d a c i s prov i d e d to output t h e bt s c b a s e - ba nd com p osi t e sig n al . the o u t p u t o f th e ad19 70 ca n be co nne c t e d wi t h minim a l ex ter n a l cir c ui t r y to t h e in p u t o f a 4.5 mh z a u ral fm m o d u l a t o r . i n addi tion t o t h e dig i tal b t s c en co der , th e ad1970 in c l udes a s t er e o ima g e en ha n c e m en t f u n c t i o n , p h a t s t er e o , t o in cr e a s e t h e s e ns e of sp ac iou s ne ss a v ai l a bl e f r om cl o s ely sp ac e d t v l o ud s p eak e r s . a d i al og e n h a n c em en t al g o ri thm so l v e s th e p r ob lem o f pla y in g wide d y nam i c r a n g e s o ur ces o v er limi te d - p e r f o r ma n c e t v sp e a k e rs and a m plif iers. an i 2 c p o r t al lo ws co n t r o l o f th e ad1970 s r e g i st ers a nd p a ram e t e rs. the ad1970 u t i l izes ad i s p a ten t e d m u l t ib i t - a r c h i t ec t u r e to p r o v ide b t s c p e r f o r ma n c e o f up to 87 db d y namic r a n g e and a thd+ n o f ?83 db . the ad1970 inc l udes p a t e n t e d b t sc st er eo t v t e c h n o log y l i c e ns e d f r om t h a t c o r p or a t i o n . func tio n a l block di agram anal o g l / r in p u ts i 2 c i/o gr ou p i 2 cp o r t co nt r o l r e g i st er s adc vo l u me c o nt ro l bt s c e n co de r co re bt s c e n co de d ou t p u t ana l o g bi as 3 da c de c i m a t i o n fi l t e r 05500-001 pl l syn c st r i pper adc adc 4 di g i t a l a udi o i n t e rf ace c o mpo si t e vi d e o ad1 9 7 0 fi g u r e 1 .
ad1970 rev. 0 | page 2 of 20 table of contents specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 6 package characteristics (48-lead lqfp) .................................. 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 theory of operation ........................................................................ 9 signal processing ............................................................................ 10 background of btsc ................................................................. 10 performance factors .................................................................. 10 separation alignment ................................................................ 11 phase linearity of the external analog filter ......................... 11 input levels ................................................................................. 11 clocking and pll ....................................................................... 11 crystal oscillator ........................................................................ 11 general purpose input/output (gpio) pins ......................... 11 power-up sequence ................................................................... 11 control port .................................................................................... 12 i 2 c port overview ...................................................................... 12 i 2 c address decoding ................................................................ 12 input level control .................................................................... 13 output level control ................................................................. 13 i 2 c read/write data formats ................................................... 14 analog input/output ..................................................................... 16 adc input ................................................................................... 16 dac output ................................................................................ 16 serial data port ........................................................................... 16 serial data modes ...................................................................... 16 typical applications circuit .......................................................... 18 outline dimensions ....................................................................... 19 ordering guide .......................................................................... 19 revision history 4/05revision 0: initial version
ad1970 rev. 0 | page 3 of 20 specifications test conditions, unless otherwise noted table 1. parameters conditions unit supply voltages (av dd , dv dd ) 3.3 v ambient temperature 25 c input signal 1 khz, 0.8 v rms analog, 0 dbfs digital hz, v rms, dbfs input sample rate 48 khz measurement bandwidth 20 hz to 14 khz khz word width 24 bits load capacitance 50 pf load current 1 ma input voltage high 2.0 v input voltage low 0.8 v table 2. analog input performance parameter min typ max unit maximum input level 1.0 (2.8) v rms (v p-p) output level 250 mv rms dynamic range (20 hz to 14 khz, C60 db input) (encoded output, left = right) 68 74 db thd + noise (encoded output, left = right, 20 hz to 14 khz) v in = 0 dbv rms C72 C65 db table 3. digital input performance parameter min typ max unit resolution 24 bits output level 250 mv rms dynamic range (20 hz to 14 khz, C60 db input) (encoded output, left = right) 81 87 db thd + noise (encoded output, left = right, 20 hz to 14 khz) v in = 0 dbfs C83 C74 db table 4. video input parameter min typ max unit input signal level 0.35 1.0 v p-p input impedance 2 k? table 5. crystal oscillator parameter min typ max unit transconductance 7 10 13 mmhos
ad1970 rev. 0 | page 4 of 20 table 6. btsc encoder performance parameter min typ max unit channel separation (C25 db input) 30 hz to 500 hz 24 30 db 500 hz to 5 khz 18 21 db 5 khz to 13.5 khz 14 15 db channel separation at 1 khz 0 db input 25 27 C2 db input 24 26 frequency response 30 hz to 10 khz C1 +0.5 db 30 hz to 13.5 khz C1.5 +0.5 db table 7. digital i/o parameter min typ max unit input voltage high (v ih ) 2.0 v input voltage low (v il ) 0.8 v input leakage (i ih @ v ih = 2.4 v) 10 a input leakage (i il @ v il = 0.4 v) 10 a high level output voltage (v oh ) i oh = 2 ma (except vid_pres) dvdd ? 0.6 v low level output voltage (v ol ) i ol = 2 ma 0.4 v table 8. power parameter min typ max unit supplies voltage, analog, digital, pll 3.0 3.3 3.6 v analog current 30 41 50 ma digital current 30 38 48 ma pll current 1 5 8 ma dissipation all supplies 277 mw analog supply 135 mw digital supply 125 mw pll supply 17 mw table 9. temperature range parameter min typ max unit specifications guaranteed 25 c functionality guaranteed 0 70 c storage C55 +125 c
ad1970 rev. 0 | page 5 of 20 table 10. digital timing parameter min typ max unit t dmd mclk duty cycle, external 512 f s mode 40 50 60 % t dbl mclk low pulse width, external 512 f s mode 15 ns t dbh mclk high pulse width, external 512 f s mode 15 ns t dbl mclk low pulse width, pll, 256 f s or f s mode 15 ns t dbh mclk high pulse width, pll, 256 f s or f s mode 15 ns t dls lrclk setup 10 ns t dlh lrclk hold 10 ns t dds sdata setup 10 ns t ddh sdata hold 10 ns t ibc i 2 c bus clock frequency 400 khz t isst i 2 c setup time for start condition 10 ns t ih i 2 c hold time for start condition 30 ns t sds sda setup time 50 ns t sdh sda hold time 25 ns t sdf sda fall time at 3 ma sink and 400 pf load 25 ns t sdr sda rise time 300 ns t pws pulse width of spikes supressed by the input filter 50 ns t pdrp resetb low pulse width 15 ns
ad1970 rev. 0 | page 6 of 2 0 absolute maximum ratings table 11. min max unit dv dd to dgnd C0.3 +3.95 v odv dd to dgnd C0.3 +3.95 v av dd to agnd C0.3 +3.95 v digital inputs dgnd C 0.3 dv dd + 0.3 v analog inputs agnd C 0.3 av dd + 0.3 v agnd to dg nd C0.3 +0.3 v reference voltage (av dd + 0.3)/2 v maximum junction temperature +125 c storage temperature range C65 +150 c s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s ra t i n g onl y a nd f u n c t i o n al op era t io n o f t h e de v i ce a t t h es e o r a n y o t h e r con d i t io n s ab o v e t h o s e i n dica t e d in t h e op era t io nal s e c t io n o f t h is sp e c if ic a t io n is no t im plie d . e x p o sur e t o a b s o l u te max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . package c h aracteristics (48-lead lqfp) table 12. min typ max unit ja ( t hermal resistance [junction-to-ambient]) 7 2 c / w jc ( t hermal resistance [j unction-to-cas e]) 1 9 . 5 c / w esd caution esd (electrostatic discharge) sensitive device. electrosta tic char ges as high as 4000 v readily ac cumulate on the human body and test eq uipment and c a n d i scharge wit h out d e tection. although th is product features proprietary esd protection circ uitry, permanent dama ge may occur on devices subjected to high energy electrostatic di scharge s . ther efore, pro p er esd precautions are rec o m m ended to avoid performan c e degradation or l o ss of functiona l ity.
ad1970 rev. 0 | page 7 of 2 0 pin conf iguration and fu nction descriptions nc = no connect ad1970 top view (not to scale) dvdd 1 resetb 2 dgnd 3 dvdd 4 rsvd 5 dgnd gpio1 gpio0 xin xout 36 35 34 33 32 vout_oamp 6 vin_oamp 7 avdd 8 btsc_out 9 agnd 10 vref 11 filtcap 12 vid_pres mclk pll_mode1 pll_mode0 nc 31 30 29 28 27 vid_in pgnd 26 25 av dd 13 agnd 14 v o ut_ i amp l 15 vin _ ia m p l 16 v o ut_ i amp r 17 vin _ ia m p r 18 cap lp 19 cap ln 20 cap rp 21 cap rn 22 pvd d 23 pll_lf 24 dgnd adr0 adr1 sc l sd a 48 47 46 45 44 dig_ in_ e n lrclk bclk s data gpio3 43 42 41 40 39 gpio2 dv dd 38 37 05500-002 f i gure 2. pin config ur ation ta ble 13. pi n f u nct i on des c ri pt i o ns pin o. pin ame input/output description 1 dvdd digital power. 2 resetb in resetactive low. after resetb transitions from low to high, t h e ad1970 bts c encoder core goes throu g h an initializ a tion sequen ce where all regi ster s are set to 0. the initializati on is completed after 1024 mclk cy cl es. new values should not be wr itten to the control port until the in itializ a tion is com p let e . 3 dgnd digital ground. 4 dvdd digital power. 3. 3 v nominal. 5 rsvd reservedconnect to dgnd. 6 vout_oamp out output voltage of internal o p a m p to be used for bt sc output l o w pa ss filter. 7 vin_oamp in negative input of internal op amp to be used for btsc output l o w pass filter. 8 avdd analog power. 9 btsc_out out encoded btsc output. the no min al output voltage for a 300 hz, 0 db mono input signal is 250 mv rms. 10 agnd analog ground. 11 vref out connectio n for voltage referenc e noise reduct ion capacitor. the nomina l vref voltage is 1.5 v; the analo g gain scale s directly with the voltage on this pin. any ac signal on this pin causes distortio n and therefore a large decoupli ng capacitor should be used to ensure the voltage on vref is clean. 12 filtcap out connectio n for dac noise reduction capa citor. a 10 f capacitor should be co nnected to this pin to reduce the noise on an intern al dac biasing point to provide the hig h est performan c e. it may not be nec e ssary to con n e c t this pin, depending on the q u ality of the layout and grounding used in th e application circuit. 13 avdd analog power. 3 . 3 v nominal. by pass c a pacitors should be pl ace d close to the pi ns and connected direc t ly to the analog ground plane. 14 agnd analog ground. 15 vout _iampl out output of intern al op am p for lef t channel in put amplifier. 16 vin_ia mpl in negative input of internal op amp for left channel input amplifier. 17 vout_iamp r out output of intern al op am p for ri ght channel in p ut amplifier.
ad1970 rev. 0 | page 8 of 20 pin no. pin name input/output description 18 vin_iampr in negative input of internal op amp for right channel input amplifier. 19 caplp i/o adc filter capacitor connect ion (positive left-channel input to modulator). a 1 nf capacitor should be placed between this pin and analog ground. 20 capln i/o adc filter capacitor connection (negative left-channel input to modulator). a 1 nf capacitor should be placed between this pin and analog ground. 21 caprp i/o adc filter capacitor connectio n (positive right-channel input to modulator). a 1 nf capacitor should be placed between this pin and analog ground. 22 caprn i/o adc filter capacitor connection (negative ri ght-channel input to modulator). a 1 nf capacitor should be placed between this pin and analog ground. 23 pvdd pll power. 3.3 v nominal. bypass capacitors sh ould be placed close to this pin and connected directly to the pll ground. 24 pll_lf pll loop filter connection. 25 pgnd pll ground. connect to dgnd. 26 vid_in in composite video input. composite video sign al input to the sync separator. the sync output is connected to a pll that generates the clocks for the ad1970. this pin has an input impedance of 2 k?. 27 nc no connect. 28 pll_mode0 in pll mode select pin 0. the setting of these pins indicates the source and frequency of the input clock to generate the internal mclk for the ad1970. 29 pll_mode1 in pll mode select pin 1. the setting of these pins indicates the source and frequency of the input clock to generate the internal mclk for the ad1970. 30 mclk in master clock input. this input is used to generate the intern al master clock if it is not derived from the composite video signal on vid_in. the master clock frequency must be either fs or 256 fs, where fs is the input sampling frequency. the pll_ctrlx pins should be set to accept the appropriate mclk input frequency. 31 vid_pres out video present flag. a high logic level on this pin indicates that a valid composite video signal is present on the vid_ in pin. open-drain output. 32 xout out crystal oscillator output. this pin is the output of the on-boa rd oscillator and should be connected to one side of a crystal. 33 xin in crystal oscillator input. this pin is the input to the on-board oscillator and should be connected to one side of a crystal. 34 gpio0 in/out general purpose i/o 0. this pin can be set to be either a static input or output, with levels and direction controlled through the i 2 c port. 35 gpio1 in/out general purpose i/o 1. this pin can be set to be either a static input or output, with levels and direction controlled through the i 2 c port. 36 dgnd digital ground. 37 dvdd digital power. 38 gpio2 in/out general purpose i/o 2. this pin can be set to be either a static input or output, with levels and direction controlled through the i 2 c port. 39 gpio3 in/out general purpose i/o 3. this pin can be set to be either a static input or output, with levels and direction controlled through the i 2 c port. 40 sdata in/out serial data input/output (befor e btsc encoding). digital input to the btsc encoder or output of the adc. the serial format is selected by writing to bits 3:2 of control register 1. 41 bclk in/out bit clock input/output. serial bit clock for clocki ng in the serial data. the interpretation of bclk changes according to the serial mode, which is set by writing to the control registers. 42 lrclk in/out left/right clock input/output. left/right cl ock for framing the serial input data. the interpretation of the lrclk changes according to the serial mode, set by writing to the control registers. 43 dig_in_en in digital input enable (active high). 44 sda in/out i 2 c serial data input/output. 45 scl in i 2 c serial clock input. 46 adr1 in i 2 c address 1. the address of the i 2 c port is set by these pins according to table 16. 47 adr0 in i 2 c address 0. the address of the i 2 c port is set by these pins according to table 16. 48 dgnd digital ground.
ad1970 rev. 0 | page 9 of 20 theory of operation the ad1970 is comprised of a btsc encoder with stereo analog inputs and a sync separator to derive the pilot signal from the composite video stream. figure 1 shows the block diagram of the device. signal processing parameters are stored in a parameter ram, which is initialized on power-up by an internal boot rom. the values stored in the parameter ram control all the filter coef- ficients, mixing, and dynamics-processing code used in the btsc algorithm. the ad1970 has an i 2 c port that supports complete read/write capability of the parameter ram, as well as a control port and several other registers that allow the various signal processing parameters to be controlled. the ad1970 can run as a stand- alone processor without external control. the ad1970 has a very flexible serial data input port that allows for glueless interconnection to a variety of digital signal sources. the ad1970 can be configured in left-justified, i 2 s, right- justified, or dsp serial port-compatible modes. it can support 16, 20, and 24 bits in all modes. the ad1970 accepts serial audio data in msb first, twos complement format. the ad1970 operates from a single 3.3 v power supply. it is fabricated on a single monolithic integrated circuit and is housed in a 48-pin lqfp package for operation over the temperature range of 0c to 70c.
ad1970 rev. 0 | page 10 of 20 signal processing backgrou nd of btsc b t sc is t h e nam e o f t h e st and a r d fo r addin g ster e o a u dio c a p a - b i li ty t o the us t e le vision sys t em. i t is in man y wa ys simi la r t o t h e alg o r i t h m us e d fo r fm s t er e o b r o a dcasts, wi t h t h e addi t i on of a s o ph i s t i c a t e d c o m p re ss or c i rc u i t to i m prove t h e s i g n a l - t o - noi s e r a t i o . t o m a i n t a i n c o m p a t ibi l it y w i t h non - bt s c t v re c e ive r s , t h e p r o c es sin g o f mo n o (l = r) sig n als is un c h a n ged f r o m the o r ig ina l p r e-b t sc sy st em. t h e l + r sig n a l is a p plie d t o a 75 s p r e-em ph asis f i lter , a nd is t h e n a p plie d to a 4.5 mh z f m m o d- u l a t or , w h i c h i s l a te r a dde d to t h e v i d e o s i g n a l to c r e a te a co m p osi t e vid e o sign al . s t er eo ca p a b i li ty is added b y ta kin g t h e l ? r s i g n al , a p p l yin g i t to a 2-b a nd d y n a mic co m p r e ss or , a n d t h e n m u l t i p ly in g t h is sig n al b y a ca r r i er sig n al a t tw ic e t h e h o r i zo n t al s c a n nin g ra t e (f h ), o r a b o u t 2 15.734 kh z. this m u l t i p lic a tio n is k n o w n as do ub le sideb a nd , su p p r ess e d - c a r r i er m o d u l a t i o n , a nd i t ef fe c t i v e l y t r a n sla t es t h e co m p res s e d l ? r s p e c t r um u p in f r eq uen c y s o tha t i t si ts abo v e t h e a u dio band ( s ee f i gur e 3). f o r th e r e ce i v e r t o r e co v e r th i s l ? r si gn al , a p i lo t t o n e a t th e h o r i zo n t al ra te is adde d t o t h e si g n al . the r e cei v er has a p ll tha t lo c k s t o this p i lo t an d g e n e ra t e s a sig n al a t th e ca r r ier f r eq ue n c y . t h i s s i gn al i s th en us ed t o m u l t i p l y t h e co m p os i t e b t sc -en c od e d si gn al , wh i c h tra n s l a t e s th i s co m p o n en t ba ck do wn to b a s e b a nd . on c e t h e l + r a nd l ? r si g n a l s a r e re c o ve re d, a s i mp l e a d d i t i on / s u b t r a c t i on c i rc u i t ( s ome t i m e s r e f e rr ed t o a s th e m a tri x ) ca n b e used t o r e co v e r th e ri gh t si gn al . s i n c e t h e p i lo t to n e is adde d a t 15.734 kh z, i t is n e ces s a r y t o r e d u ce t h e b a ndwi d t h o f t h e sig n a l s o t h a t a u di o sig n a l s ca nn ot in t e r f er e wi th t h e p i lo t t o n e . i n th e ad1970, t h e ban d wid t h is limi te d t o 14 k h z; ab o v e t h is f r e q uen c y , t h e r e sp o n s e de c a y s ve r y r a pi d l y . performance fac t ors t o m a in ta i n g o od se pa ra ti o n b e t w een t h e le ft a n d ri gh t ch an nel s , i t i s n e c e ss ar y to cl o s ely m a tc h t h e f i lte r i n g a n d co m p an di n g st anda r d s s e t fo r t h in t h e st an d a r d (f c c oet60). e v en smal l er r o rs ca n r e s u l t in p o o r p e r f o r ma n c e . th e ad1970 has b e en p r og ramme d t o m a t c h t h es e st anda r d s as acc u ra tely as p o s s i b le . t y p i ca l s e p a ra tion n u m b ers ra n g e f r om 30 db a t f r eq uen c ies be l o w 500 h z t o 1 5 db a t 13.5 kh z. m e as ur in g t h es e n u m b ers can b e dif f i c u l t , sin c e s i g n if ican t dif f er en ces exis t b e t w e e n m a n y u n it s s o l d a s re f e re nc e d e c o d e r s , w h i c h are a l l i m p l em en t e d w i th a n al og co m p o n en t s . 05500-003 matrix compressor 75 s pre-emph filter oscillator rms detect pre-emph second order lpf eight order gain bandpass second order gain bandpass fourth order 1/x rms detect nonlinear formula l-r in 2 fh carrier fh pilot l?r l+r l r main algorithm flow to dac spectral tilt filter f i gure 3 . s i gnal p r oc essi ng f l o w
ad1970 rev. 0 | page 11 of 20 separation alignment the btsc encoder outputs are all specified in terms of the deviation of the fm 4.5 mhz carrier. for the ad1970, a digital input level of 0 db (mono signal) should cause a carrier devia- tion of 25 khz without the 75 s pre-emphasis filter. in practice, the pre-emphasis filter can be left in for this adjust- ment, as long as the frequency is low enough to not be affected by the filter. it is critical to maintain the proper gain relationship between the btsc encoder and the 4.5 mhz fm modulator. a common mistake is to assume that changing the gain between the btsc encoder output and the fm modulator input has the same effect as changing the audio input level going in to the btsc encoder. the presence of a complicated 2-band nonlinear dynamics processor means that the encoder output must be connected to the decoder input (through the fm modulation/ demodulation process) with a known gain. if this gain is changed, then the separation significantly suffers. when measuring the ad1970 on the bench, it is possible to use a btsc reference decoder box, so that the fm modulation/ demodulation process can be skipped. these units have a method of adjusting the input voltage sensitivity to achieve best separation. the output level of the ad1970 can also be adjusted over a wide range using either the i 2 c control port or by adjusting the values of the components used in the external analog low-pass filter that is between the btsc encoder output and the input to the fm modulator. phase linearity of the external analog filter if the time-alignment of the pilot to the carrier signal is not close to 0, a loss of separation can occur. this means that the external analog low-pass filter should be a linear-phase design to provide constant group delay over the range from dc to 50 khz. a bessel filter is recommended for this application. the typical applications circuit (see figure 8) shows a recommended design for this filter. input levels the maximum input level to the ad1970 changes across frequency. table 14 shows the maximum allowable input level for different frequencies. these values are part of the btsc specification, not a function of this chip. table 14. maximum input levels to the btsc encoder across frequency frequency (hz) maximum input level (dbfs) 20 to 1000 0 1600 ?1 2500 ?3 3150 ?5 5000 ?8 8000 ?11 12500 ?15 clocking and pll the ad1970s master clock either can be directly fed to the mclk pin or generated by a pll from a composite video signal input on the vid_in pin. if the clock input is on the mclk pin, the pll can synthesize the internal clocks from either a clock at the digital audio frame sync frequency (f s = 48 khz) or 256 f s . the pll mode is controlled by pins pll_mode0 and pll_mode1. the settings are shown in table 15. table 15. pll modes pll_mode1 pll_mode0 setting 0 0 composite video input (on vid_in) 0 1 256 fs (on mclk) 1 0 fs (on mclk) 1 1 pll bypass crystal oscillator the ad1970 has an on-board crystal oscillator to generate a clock that can be used by an rf modulator or other application. for example, a 4 mhz crystal can be connected as shown in the application circuit (see figure 8). the ad1970 does not use this clock itself, so if it is not needed in an application the xin pin should be grounded and the xout pin left unconnected. general purpose input/output (gpio) pins pins gpio0, gpio1, gpio2, and gpio3 are set to be inputs or outputs by bits 19:16 of control register 2. all four default to input state. these pins do not take an input to or send an output from the main signal flow. when set as an output, the binary value on the pins is set according to bits 15:12 of control register 2. these pins can be used to interface with i/o pins on a microcontroller and allow hardware control via the i 2 c bus. power-up sequence the ad1970 has a built-in power-up sequence that initializes the contents of all internal rams. during this time, the parameter ram is filled with values from its associated boot rom. the data memories are also cleared during this time. the boot sequence lasts for 1024 mclk cycles and starts on the rising edge of the resetb pin. the user should avoid writing to or reading from the i 2 c registers during this period of time.
ad1970 rev. 0 | page 12 of 20 control port i 2 c port overview the ad1970 can be controlled using the i 2 c port. in general, there are three parameters that can be controlled: the encoder output level, the phat stereo image enhancement algorithm, and the dialog enhancement algorithm. it is also possible to write new data into the parameter ram to alter the filter coefficients used in the btsc encoding process. since this is a fairly complex topic and is unnecessary for normal operation of the chip, the details are not included in this data sheet; please contact adi sales if modifications to the btsc filters are required. the i 2 c port uses a 2-wire interface consisting of sda, the bidirectional data line, and scl, the clock. the r/ w bit is low for a write operation and high for a read operation. the 10-bit address word is decoded into either a location in the parameter ram or one of the registers. the number of data bytes varies according to the register or memory being accessed. the detailed data format diagram for continuous-mode operation is given in the section. i 2 c address decoding table 16 shows the address decoding used in the i 2 c port. four different addresses are available to avoid conflicting addresses on an i 2 c bus. the i 2 c address space encompasses a set a registers and the parameter ram. the parameter ram is loaded on power-up from an on-board boot rom. table 16. i 2 c address settings adr1 adr0 i 2 c address 0 0 0x20 0 1 0x21 1 0 0x22 1 1 0x23 table 17. i 2 c port address decoding register address register name read/write word length 0 input level control write: 22 bits read: 22 bits 1 to 254 parameter ram 255 output level control 256 control register 1 write: 11 bits read: 6 bits 257 control register 2 write: 22 bits 258 adc volume control 259 stereo spreading control 260 dialog enhancement control
ad1970 rev. 0 | page 13 of 20 input level control this register location controls the input level of both the left and right channels to the ad1970 btsc encoding algorithm. the register defaults to a value of 1.0 (0100000000000000000000 in binary 2.20 format) and allows a maximum of 12 db of gain at a full-scale value. this feature allows compatibility with the dolby digital specification for proper operation in both rf mode and line mode. in rf mode, the dialog level is specified at 11 db higher than the dialog level in line mode. a gain of 11 db can be achieved by writing 1.8836 to address 0. output level control the level control of the btsc-encoded output is controlled in this register location. the default value is 0.5 (C6 db, 0010000000000000000000 in binary 2.20 format), or 250 mv on the dac output. the output level should not be used as a volume control. its intended use, in conjunction with the output filter, is to match the level with the expected input of the btsc decoder. matching these allows maximum separation between the left and right encoded channels. control register 1 control register 1 is an 11-bit register that controls serial modes, de-emphasis, mute, power-down, and i 2 c-to-memory transfers. table 18 documents the contents of this register. bits 5:4 and 10:8 are reserved and should be set to 0 at all times. the audio signal is muted with bit 7 of the control register. the soft power-down bit (bit 6) stops the internal clocks to the dsp core, but does not reset the part. the digital power consumption is reduced to a low level when this bit is asserted. reset can only be asserted using the external reset pin. bits 3:2 select the serial format from one of four modes. these different formats are discussed in the section of this data sheet. the word length bits (1:0) are used in right-justified serial modes to determine where the msb is located relative to the start of the audio frame. table 18. control register 1 write register bits function 10:8 reserved, set to 000 7 soft mute (1 = start mute sequence) 6 soft power-down (1 = power-down) 5:4 reserved, set to 00 3:2 serial-in mode 00 = i 2 s 01 = right-justified 10 = dsp 11 = left-justified 1:0 word length 00 = 24 bits 01 = 20 bits 10 = 16 bits 11 = 16 bits table 19. control register 1 read register bits function 5:2 gpio 3:0 read back 1:0 reserved control register 2 control register 2 is a 22-bit write-only register that controls power down modes, pll and sync separator controls, and digital i/o pin functions. table 20. control register 2 register bits function 21 enable adc output on serial audio interface 20 reserved 19:16 gpio output enable 3:0 15:12 gpio data 11:9 pll shift, default 100 8:4 sync separator slicer voltage; default 10111 3 adc power-down 2 reference power-down 1 dac power-down 0 pll power-down adc volume control register this controls the input level of both adc channels. the default value is 1.0 (0100000000000000000000 in binary 2.20 format). stereo spreading register this register controls adis patented phat stereo spatial enhancement algorithm. the default is all 0s, which corresponds to no effect. the maximum setting is 0100000000000000000000 or a twos complement fractional value of 1.0. note that the bass energy in each channel is increased using this algorithm, which may cause some digital clipping on full-scale signal peaks, especially at low frequencies.
ad1970 rev. 0 | page 14 of 20 d i a l og en ha nc em e n t re gist e r this con t r o ls t h e b u i l t- in d i a l og en h a n c e m e n t a l go r i t h m, and def a u l ts t o 0. the max i m u m s e t t in g is 0100 0000 000000000 0000 0 or a t w o s c o m p l e me n t f r a c t i on a l v a lu e of 1 . 0 . t h i s a l gor i t h m i s in te nde d to s o lve t h e p r ob lem of pla y in g b a ck h i g h d y na mic ra n g e dig i tal a u dio sig n als o v er a t e l e visio n s b u i l t-in s p e a k e rs. i t p r o v ides a n am pli t ude b o ost t o sig n als t h a t a r e in t h e ra n g e w h er e dialog sig n als a r e us ual l y fo un d , w h i l e a t t h e s a me t i m e p r e v en t i n g lo ud s p e c ial ef fe c t s p a s s a g es f r o m o v erlo adin g t h e sp e a k e rs o r a m plif iers. i 2 c read/write data formats t h e r e a d /w ri t e f o rm a t s o f th e i 2 c p o r t are de s i g n e d to b e b y te o r ien t e d . this a l lo ws fo r e a sy p r o g ra mmin g o f co mm on micr o - co n t r o l l er c h i p s. i n o r der t o f i t in t o a b y te o r ien t ed f o r m a t , 0s a r e a p p e nde d to t h e d a t a f i elds i n o r der to ex tend t h e da t a w o r d t o th e n e xt m u l t i p le o f 8 b i ts. f o r exa m p l e , 22-b i t w o r d s wr i t t e n t o t h e p a ram e t e r r a m a r e a p p e n d e d wi t h t w o le adin g zer o es in o r der to r e ach 24 b i t s (3 b y tes). th e s e zer o -ex t e n de d d a t a f i elds a r e a p p e nde d t o a 2-b y t e f i el d c o n s ist i n g o f a r e ad/ w r i te b i t and a 10-b i t addr es s. the i 2 c p o r t k n o w s h o w man y da t a b y t e s t o exp e c t b a s e d on t h e addr es s r e c e i v e d in t h e f i rs t tw o b y t e s. 05500-009 r/w 0 scl sda 0 1 0 0 ad1 ad0 00 01 0 0 ack. by ad1970 start by master frame 1 chip address byte frame 2 register address upper byte ack. by ad1970 00 01 00 0 0 ack. by ad1970 frame 3 register address lower byte 0 register write i 2 c write d15 d14 d13 d12 d11 d10 d9 d8 ack. by ad1970 frame 4 register data upper byte d7 d6 d5 d4 d3 d2 d1 d0 ack. by ad1970 stop by master frame 5 register data lower byte scl (continued) sda (continued) r/w f i gure 4. s a mpl e of i 2 c writ e f o r m at (cont r ol r e g i s t e r 1 w r i t e) 05500-008 d7 d6 d5 d4 d3 d2 d1 d0 ack. by master frame 5 register data byte r/w 0 scl (continued) sda (continued) 0 1 0 0 ad1 ad0 repeated start by master frame 4 chip address byte ack. by ad1970 stop by master i 2 c read r/w 0 scl sda 0 1 0 0 ad1 ad0 00 01 0 0 ack. by ad1970 start by master frame 1 chip address byte frame 2 register address upper byte ack. by ad1970 00 01 00 0 0 ack. by ad1970 frame 3 register address lower byte 0 register read i 2 c write r/w fi g u r e 5 . s a m p l e o f i 2 c r e ad f o rm at (cont r ol r e g i s t e r 1 r e ad)
ad1970 rev. 0 | page 15 of 20 table 21. control register 1 write format byte 0 byte1 byte 2 byte 3 00000, r/ w = 0, adr [9:8] adr [7:0] 00000, bit [10:8] bit [7:0] table 22. control register 1 read format byte 0 byte 1 byte 2 00000, r/ w = 1, adr [9:8] adr [7:0] 00, bit [5:0] table 23. control register 2 write format byte 0 byte 1 byte 2 byte 3 byte 4 00000, r/ w = 0, adr [9:8] adr [7:0] 00, bit [21:16] bit [15:8] bit [7:0] table 24. input/output level control, adc volume control, ster eo spreading, and dialog enhancement registers write format byte 0 byte 1 byte 2 byte 3 byte 4 00000, r/ w = 0, adr [9:8] adr [7:0] 00, level [21:16] level [15:8] level [7:0]
ad1970 rev. 0 | page 16 of 20 analog input/output adc inpu t the ad1970 ac cep t s an a n alog lef t -r ig h t sig n al o n i t s in p u t. dac ou tpu t f i g u re 6 show s t h e bl o c k d i ag r a m of t h e a n a l o g output . a s e r i e s o f c u rr en t s o ur ces a r e co n t r o l l e d b y a dig i tal - mo d u la t o r . de pen d i n g o n th e d i gi tal cod e f r o m th e m o d u la t o r , ea c h cur - r e n t s o ur ce is conn ec t e d t o the summin g j u n c tio n o f ei t h er a p o si ti v e i-t o -v co n v er t e r o r a nega ti ve i-t o -v c o n v er t e r . t w o ex t r a c u r r en t s o ur ces t h a t p u sh in ste a d o f p u l l ar e adde d to s e t t h e mids cale comm on- m o d e vol t a g e . a l l c u r r en t s o ur ces a r e der i ve d f r o m t h e vref i n p u t pin. t h e ga in o f the ad1 970 is dir e c t l y p r o p o r tio n al t o th e ma g n i t ude of th e c u r r en t s o urces, a nd ther ef o r e th e ga in o f the ad1970 is prop or t i on a l to t h e vo lt age ge ne r a te d on t h e v r e f pi n . t h e n o minal vref v o l t a g e is 1.5 v . i re f i ref i re f ? d i g _ i n i re f + di g _ i n switched current sources v ref in out? out+ from digital ? ? modulator (dig_in) 05500-005 bias f i gure 6. intern a l da c a n al og a r chitec tur e sin c e t h e vref in p u t ef fe c t i v e l y m u l t i p lies t h e s i g n al , ca r e m u st be ta k e n t o in s u r e tha t n o ac sig n als a p p e a r on t h is p i n. this can be ac co m p lishe d b y usin g a la rg e de co u p lin g c a p a ci t o r con- ne c t e d to v r e f . the ad1970 sho u ld be us e d wi th a n ext e r n al t h ir d o r der f i l t er on e a ch output ch an nel, a s sho w n i n fi g u re 8 . t h e v a lu e s s h ow n a r e f o r a 100 kh z b e s s e l f i l t er . th e us e o f a b e s s e l f i l t er is im p o r - ta n t t o m a in ta in th e tim e - a li g n m e n t o f th e p i lo t t o th e ca rri e r . i f th es e sig n als a r e n o t in p h as e , a l o s s o f s e p a ra tio n o c c u rs. f o r bes t p e r f o r ma nce , a l a rg e (>10 f) ca p a c i to r s h o u ld be co nne c t e d b e twe e n t h e f i l t c a p p i n and a n a l o g g r o u n d . serial data port the ad1970 s f l exi b le s e r i al a u dio in t e r f ace ac cep t s an d s e n d s da ta in tw os com p le m e n t , ms b f i rs t f o r m a t . the lef t c h a n n e l d a t a f i el d a l w a y s p r e c e d es t h e r i g h t cha n nel da t a f i eld . t h e s e r i a l m o de is s e t b y u s in g mo de s e lec t b i ts in the co n t r o l r e g i s t er . i n a l l m o de s excep t fo r t h e r i g h t j u st if ie d m o de, t h e s e r i a l p o r t accep t s an a r b i t r a r y n u m b er o f b i ts u p t o a limi t o f 24 (extra b i ts do n o t ca us e a n er r o r , b u t t h e y ar e t r un ca t e d in ter n al l y ). i n t h e r i g h t- j u st if ie d m o de , co n t r o l r e g i st er b i ts a r e us e d t o s e t t h e w o r d len g th t o 16, 20, o r 24 b i ts. th e defa u l t o n p o w e r - u p is 24- b i t mo de. pr o p e r o p er a t io n o f t h e r i g h t j u st if ie d m o de r e q u ir es t h a t t h er e b e ex ac t l y 64 b c lks p e r a u dio f r a m e. serial data modes f i gur e 7 s h o w s th e lef t -j us t i f i ed m o de . lr cl k is hig h f o r th e lef t cha n n e l, and lo w fo r t h e r i g h t cha n nel. d a t a is s a m p le d on t h e r i sin g e d ge o f b c lk. th e ms b is lef t - j us t i f i e d t o a lrcl k tra n si ti o n , wi th n o ms b de la y . t h e le ft -j us ti f i e d m o d e ca n accep t an y w o r d len g th u p t o 24 b i ts. f i gur e 7 sh o w s t h e i2s m o de , w h ich is t h e def a u l t s e t t ing. lr clk is lo w f o r th e lef t c h a n n e l an d t h e m s b is de l a ye d f r o m t h e e d g e o f t h e lr clk b y a sing le b c lk p e r i o d . th e i2s m o de ca n be us e d t o accep t an y n u m b er o f b i ts u p t o 24. f i gur e 7 s h o w s th e r i g h t-j u s t if ied m o de o f th e ad1970. lr cl k i s h i gh f o r th e left c h a n n e l , lo w f o r th e ri gh t c h a n n e l . da ta i s s a m p l e d on t h e r i s i ng e d ge of b c l k . t h e st ar t of d a t a i s d e l a y e d f r o m th e lrcl k edg e b y 16, 1 2 , o r 8 b c lk in t e r v als, dep e ndin g o n th e se lec t ed w o r d le n g th . th e d e fa ul t w o r d le n g th i s 24 b i t s ; o t h e r w o r d len g t h s a r e s e t b y wr i t in g t o bi ts 1:0 o f t h e co n t r o l r e g i st er . i n r i g h t - j u st if ie d m o de , i t is assu m e d t h a t t h er e a r e 64 b c lks p e r f r a m e . f i g u re 7 shows t h e d s p s e r i a l p o r t mo de. l r c l k m u st p u l s e hig h fo r a t le as t o n e b i t clo c k p e r i o d b e fo r e t h e ms b o f t h e lef t c h a n n e l is valid a nd lr c l k m u s t p u ls e hig h a g a i n f o r a t le as t o n e b i t clo c k p e r i o d b e fo r e t h e ms b o f t h e r i g h t cha n n e l is valid . d a ta is s a m p le d on t h e fa l l in g e d g e o f b c lk. th e d s p s e r i al p o r t m o de can b e us ed wi th an y w o r d len g th u p t o 24 b i ts. i n th i s m o de , i t i s th e r e s p o n si b i li t y o f th e d s p t o e n s u r e th a t th e le ft da ta i s t r a n sm i t t e d w i t h th e f i r s t l r c l k p u lse a n d tha t sy n c hr o n ism is ma in t a i n e d f r o m t h a t p o i n t fo r w a r d .
ad1970 rev. 0 | page 17 of 20 lrclk bclk sdata left channel lsb right channel lsb msb msb lrclk bclk sdata left channel lsb right channel lsb msb msb lrclk bclk sdata left channel right channel msb msb lsb lsb lrclk bclk sdata lsb lsb 1/f s 05500-006 msb msb left justified mode: 16 to 24 bits per channel i 2 s mode: 16 to 24 bits per channel r i g h t j u s t i f i e d m o d e : sel ec t n u m b er of bits per channel dsp mode: 16 to 24 bits per channel notes: 1. dsp mode doesn't identify channel. 2. lrclk normally operates at fs except for dsp mode which is 2xfs. 3. bclk frequency is normally 64xlrclk but may be operated in burst mode. fi g u r e 7 . s e r i a l d a t a fo r m a t s
ad1970 rev. 0 | page 18 of 20 typical a p plicati ons circuit 19 20 21 22 15 16 17 18 r1 10k ? r2 10k ? c26 4.7 f c25 4.7 f r3 10k ? c1 82pf r4 10k ? c2 82pf c6 1nf c5 1nf c4 1nf c3 1nf pll_mode0 pll_mode1 28 29 vid_pres video_in r11 10k ? r12 1k ? c27 470pf c7 1nf 31 26 30 r13 1k ? c9 22pf y1 4mhz c8 22pf 33 32 4mhz optional auxiliary oscillator audio_in_left audio_in_right xin xout mclk 3 36 48 25 10 14 dg nd dg nd dg nd pg nd ag nd ag nd rsvd ++ c10 10 f c11 10 f 43 42 35 34 2 11 12 27 5 41 40 39 38 dig_in_en lrclk_intf bclk_intf sdata_intf gpio3 gpio2 gpio1 gpio0 reset + + + c24 0.1 f c23 0.1 f c22 0.1 f c20 0.1 f c21 0.1 f c18 4.7 f c19 0.1 f r5 1.6k ? c16 2.2 f c17 0.1 f l1 600z l2 600z 3.3v 3.3v 3.3v scl sda r15 2k ? r14 2k ? adr0 adr1 r6 11k ? r8 3.01k ? r7 11k ? r9 604 ? r10 49.9k ? c14 68pf c12 2.2nf c15 270pf btsc c13 10 f vout_iampl vin_iampl vout_iampr vin_iampr caplp capln caprp caprn pll_mode0 pll_mode1 vid_pres vid_in nc filtcap vref reset gpio0 gpio1 gpio2 gpio3 sdata bclk lrclk dig_in_en 7 6 44 9 45 46 47 vout_oamp vin_oamp btsc_out sda 24 scl adr1 adr0 pll_lf dvdd dvdd avdd avdd dvdd pvdd 05500-007 1 4 37 8 13 23 + + ad1970 f i g u re 8. t y pic a l a p plic at i o ns c i rcuit
ad1970 rev. 0 | page 19 of 20 outline dimensions compliant to jedec standards ms-026-bbc top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc lead pitch 7.00 bsc sq 1.60 max 0.75 0.60 0.45 view a 9.00 bsc sq pin 1 0.20 0.09 1.45 1.40 1.35 0.08 max coplanarity view a rotated 90 ccw seating plane 7 3. 5 0 0.15 0.05 f i g u re 9. 48-l e ad l o w-pr of i l e q u ad f l at p a ckag e [l qf p ] (st - 48) d i mensions are sh o wn in millime t ers ordering guide model temperature r a nge package descri ption package option AD1970JSTZ 1 0c to 70c 48-lead lqfp st-48 AD1970JSTZrl 1 0c to 70c 48-lead lqfp on 13-inch reel st-48 1 z = pb-free part.
ad1970 rev. 0 | page 20 of 20 notes pur c has e of licens ed i 2 c c o m p o n en ts o f analog d e vic e s o r o n e o f i t s s u b l ic en s e d a s s o c i a t e d c o m p a n ies c o n v e y s a lic e n s e f o r t h e p u r c ha s e r un d e r t h e p h i li ps i 2 c p a t e n t r i gh ts t o use t h es e c o m p o n en t s in a n i 2 c sys t em, p r o v id e d t h a t t h e sys t em c o nf o r m s t o t h e i 2 c s t a n da r d s p e c ifica t io n a s defin e d b y p h i l i p s . ? 2005 a n al og devic e s , inc . a ll rig h t s r e ser v e d . t r a d em arks an d r e gist er e d tr adem ar ks ar e t h e proper t y of t h eir respec tiv e o w ners . d05500C0C 4/05(0)

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