 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| document number: mc06XS3517 rev. 2.0, 2/2012 freescale semiconductor ? advance information * this document contains certain information on a new product. ? specifications and information herein are subject to change without notice. ? freescale semiconductor, in c., 2012. all rights reserved. smart high side switch module ? (triple 6.0 m ? and dual 17 m ? ) the 06XS3517 device is a five channel 12 v high side switch module with integrated control and a high number of protective and diagnostic functions. it is designed for automotive lighting and industrial applications. the low r ds(on) channels (three 6.0 m ? , two 17 m ? ) can control different types of lighting applications; bulbs, xenon-hid lights, and leds. contro l, device configuration, and diagnostics are performed through a 16-bit spi interface (3.3 v or 5.0 v). when communication with the ex ternal microcontroller or vdd is lost, the device enters a fail-safe operation mode, but remains operational, controllable, and protected. the channels are controlled by an external clock signal and allow staggered switch-on delay, to improve emc performances. programmable output voltage slew ra tes (individually programmable) further helps improve emc performance. to avoid shutting off the device upon inrush current while still being able to closely track the load current, a dynamic over-current threshold profile is featured. load current in each channel can be sensed. the duty cycle of the channels can be controlled independently and the switching frequency of each of them can be doubled. the 06XS3517 is housed in a non-leaded power qfn package with an exposed pad. features ? three 6.0 m ? and two 17 m ? protected high side switches ? optional sixth channel with an external smart mosfet ? 16-bit spi communication interface with daisy chain capability ? accurate temperature & current sensing ? fail-safe mode including autorestart ? pwm module with programmable swit ch-on delay and frequency prescaler ? over-voltage, under-voltage, over-current, ove r-temperature, and reverse battery protections ? dedicated bulb over-current protec tion with inrush current handling ? sleep mode with low current consumption ? normal operating range 7.0 v to 20 v, extended operating range 6.0 v - 28 v figure 1. 06XS3517 simpli fied application diagram high side switch fksuffix 98art10511d 24-pin pqfn pb free 06XS3517 ordering information device temperature range (t a ) package mc06XS3517afk -40c to 125c 24 pqfn bottom view vbat cp out1 out2 out3 out4 out5 fetin fetout vcc limp flasher ign rstb clock csb fog so si sclk csns gnd 06XS3517 mcu watchdog smart switch 12 v 12 v 5.0 v
analog integrated circuit device data ? 2 freescale semiconductor 06XS3517 internal block diagram internal block diagram figure 2. 06XS3517 simplified internal block diagram vcc vbat cp gnd over-temperature prewarning shared output current logic internal regulator gate drive out1 csns csb so si sclk clock limp flasher ign out2 out1 out2 sensing pin (analog mux) out3 out3 out4 out5 fetin fetout driver for an external smart mosfet out5 vcc failure open load over-temperature detection rstb out4 r dwn over-current detection detection detection ov/uv/por detections charge drain/gate clamp pump fog temperature feedback r dwn r up vcc led control current recopy synchronization (* park) (* lbeam) (* hbeam) (* fog) (* flash) (* sense in) (* logic level) * see 06XS3517 typical application analog integrated circuit device data ? freescale semiconductor 3 06XS3517 pin connections pin connections figure 3. 06XS3517 pin connections table 1. 06XS3517 pin definitions a functional description of each pin can be found in the functional pin description section beginning on page 17 . pin number pin name pin function formal name definition 1 fetin input external fet input this pin receives the current sense signal of the external smart mosfet. 2 ign input ignition input (active high) this input wakes the device. it also contro ls the outputs 1 and 2 in case of fail mode activation. this pin has an internal pull-down resistor. 3 rstb input reset this input wakes the device. it is also used to initiali ze the device configuration and fault registers through spi. this digita l pin has a passive internal pull-down. 4 flasher input flasher input (active high) this input wakes the device and allows co ntrol over channel 5. (flasher) this pin has an internal pull-down resistor. 5 clock input/output clock input this pin state depends on rstb logic level. as long as rstb input pin is set to logi c [0], this pin is pulled up to report wake events. otherwise, the pwm frequency and timing are generated from this digital clock input by the pwm module. this pin has a passive internal pull-down. 6 limp input limp home input (active high) the fail mode can be activated by this digital input. this pin has a passive internal pull-down. 7 fog input fog input (active high) this input wakes the device. this pin has a passive internal pull-down. 8 csb input chip select (active low) when this digital signal is high, spi sig nals are ignored. asserting this pin low starts a spi transaction. the transacti on is signaled as completed when this signal returns high. this pin has a passive internal pull-up resistance. 13 24 12 10 9 8 7 6 5 4 3 2 1 11 23 22 19 20 21 16 17 18 15 14 cp gnd out5 out4 out3 out2 out1 gnd csns fetout so vcc si sclk csb fog limp clock flasher rstb ign fetin gnd vbat transparent top view analog integrated circuit device data ? 4 freescale semiconductor 06XS3517 pin connections 9 sclk input spi clock input this digital input pin is connected to th e master microcontroller providing the required bit shift clock for spi communica tion. this pin has a passive internal pull-down resistance. 10 si input master-out slave- in this data input is sampled on the pos itive edge of the sclk. this pin has a passive internal pull-down resistance. 11 vcc power logic supply spi logic power supply. 12 so output master-in slave- out spi data is sent to the mcu by this pin. this data output changes on the negative edge of sclk and when csb is high, this pin is high-impedance. 13 fetout output external fet gate this pin outputs a logic level that can be used to control an external smart mosfet. this output is also called out6. if out6 is not used in the application, th is output pin is set to logic high when the current sense output becomes valid when csns sync spi bit is set to logic [1]. 14,17,23 gnd ground ground this pin is the ground for the logic and analog circuitry of the device . 15 vbat power battery input power supply pin. 16 cp output charge pump this pin is the connection fo r an external tank capacitor (for internal use only). 22 18 out1 out5 output output 1 output 5 protected 17 m ? high side switch output terminals. 21 20 19 out2 out3 out4 output output 2 output 3 output 4 protected 6.0 m ?? high side switch output terminals 24 csns output current sense output this pin is outputs the current sense signal of out1:out5, fet in current, and it is used externally to generate a ground-referenced voltage for the microcontroller to monitor output current. if desired, this pin can also report a voltage proportional to the temperature on the gnd flag. out1:out5, fet in current sensing and temperature sensing are activated through the spi interface. notes 1. the pins 14, 17, and 23 must be shorted on the board. table 1. 06XS3517 pin definitions (continued) a functional description of each pin can be found in the functional pin description section beginning on page 17 . pin number pin name pin function formal name definition analog integrated circuit device data ? freescale semiconductor 5 06XS3517 electrical characteristics maximum ratings electrical characteristics maximum ratings table 2. maximum ratings all voltages are with respect to ground, unless mentioned otherwise. exceeding these ratings may cause malfunction or permanent device damage. parameter symbol value unit electrical ratings over-voltage test range (all out[1:5] on with nominal dc current) maximum operating voltage load dump (400 ms) @ 25 c v bat 28 40 v reverse polarity voltage range (all out[1:5] on with nominal dc current) 2.0 min @ 25c v bat - 18 v vcc supply voltage v cc -0.3 to 5.5 v out[1:5] voltage positive negative (ground disconnected) v out 40 -16 v digital current in clamping mode (si, sc lk, csb, rstb, ign, flasher, limp, and fog) i in 1.0 ma fetin input current i fetin +10 -1.0 ma so, fetout, clock, and csns outputs voltage v so - 0.3 to v cc + 0.3 v outputs clamp energy using single pulse method (l = 2.0 mh; r = 0.0 ? ; v bat = 14 v @150 c initial) out[1,5] out[2:4] e 1,5 e 2,3,4 30 100 mj esd voltage (2) human body model (hbm) human body model (hbm) out [1:5], vpwr, and gnd charge device model (cdm) corner pins (1, 13, 19, 21) ? all other pins (2-12, 14-18, 20, 22-24) v esd 2000 8000 ? 750 ? 500 v notes 2. esd testing is performed in accordance with the human body model (hbm) (c zap = 100 pf, r zap = 1500 ? ) and the charge device model. analog integrated circuit device data ? 6 freescale semiconductor 06XS3517 electrical characteristics maximum ratings thermal ratings operating temperature ambient junction t a t j - 40 to 125 - 40 to 150 c peak package reflow temperature during reflow (3) t pprt 260 c storage temperature t stg - 55 to 150 ? c thermal resistance thermal resistance, junction to case (4) r ? jc 1.0 ? k/w notes 3. pin soldering temperature limit is for 40 seconds maximum dura tion. not designed for immersion so ldering. exceeding these lim its may cause malfunction or permanent damage to the device. 4. typical value guaranteed per design. table 2. maximum ratings (continued) all voltages are with respect to ground, unless mentioned otherwise. exceeding these ratings may cause malfunction or permanent device damage. parameter symbol value unit analog integrated circuit device data ? freescale semiconductor 7 06XS3517 electrical characteristics static electrical characteristics static electrical characteristics table 3. static electric al characteristics characteristics noted under conditions 3.0 v ? v cc ? 5.5 v, 7.0 v ? v bat ? 20 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit power inputs (vbat, vcc) battery supply voltage range full performance & short-circuit extended voltage range (5) v bat 7.0 6.0 ? ? 20.0 28.0 v battery supply under-voltage (uv flag is set on) v batuv 5.0 5.5 6.0 v battery supply over-voltage (ov flag is set on) v batov 27.5 30 32.5 v battery voltage clamp (6) v batclamp 40 ? 48 v battery supply power on reset if v bat < 5.5 v, v bat = v cc if v bat < 5.5 v, v cc = 0 v batpor1 v batpor2 2.0 2.0 ? ? 3.0 4.0 v vbat supply current @ 25 c and v bat = 12 v and v cc = 5.0 v sleep state current, outputs opened sleep state current, outputs grounded normal mode, ign = 5.0 v, rstb = 5.0 v, outputs open i bat sleep1 i bat sleep2 i bat ? ? ? 0.5 0.5 10.0 5.0 5.0 20.0 ? a ? a ma digital supply voltage range, full performance v cc 3.0 ? 5.5 v digital supply under-voltage (vcc failure) v ccuv 2.2 2.5 2.8 v sleep current consumption on v cc @ 25 c and v bat = 12 v output off i ccsleep ? 0.2 5.0 ? a supply current consumption on v cc and v bat = 12 v no spi 3.0 mhz spi communication i cc ? ? ? ? 2.6 5.0 ma logic input/output (ign, cs , csns, si, sclk, clock, so, flasher, rst , limp, fog) input high logic level (7) v ih 2.0 ? ? v input low logic level (7) v il ? ? 0.8 v voltage threshold for wake-up (ign, flasher, fog, rst ) v ignth 1.0 ? 2.2 v input clamp voltage (ign, flasher, limp, fog, cs , sclk, si, rst ) i = 1.0 ma v cl_pos 7.5 ? 13 v input forward voltage (ign, flasher, limp, fog, cs , sclk, si, rst ) i = -1.0 ma v cl_neg - 2.0 ? -0.3 v input passive pull-up resistance on cs input (8) r up 100 200 400 k ? input passive pull-down resistance on si, sclk, flasher, ign, fog, clock, limp, rst pins (8) r dwn 100 200 400 k ? notes 5. in extended mode, the functionality is guar anteed but not the electrical parameters. 6. outputs shorted to ground, i out = + 500 ma and i out = ochi (guaranteed by design). 7. valid for rst , si, sclk, cs , clock, ign, flasher, fog, and limp pins. 8. valid for the following input voltage range: -0.3 v to vcc +0.3 v. analog integrated circuit device data ? 8 freescale semiconductor 06XS3517 electrical characteristics static electrical characteristics logic input/output (ign, cs , csns, si, sclk, clock, so, flasher, rst , limp, fog) (continued) so high-state output voltage i oh = 1.0 ma v soh 0.8 0.95 ? v cc so low-state output voltage i ol = -1.6 ma v sol ? 0.2 0.4 v clock output voltage reporting wake-up event (i clock =1.0ma) v clockh 0.8 0.95 ? v cc so and csns tri-state leakage current i soleak - 1.0 0.0 1.0 ? a current sense output clamp voltage csns open and i out[1:5] = i fsr v csns 5.0 6.0 7.0 v outputs (out 1-5) output negative clamp voltage i out = - 500 ma, outputs off v out - 22.0 ? -16.0 v output leakage current in off state sleep mode, outputs grounded, t a = 25 c sleep mode, outputs grounded, t a = 125 c normal mode, outputs grounded i leak(off) ? ? ? 0.0 0.0 20 2.0 3.0 25 a current sense error (9) over the full voltage and temperature range %full scale range (fsr), led control bit = 0, channels 1,5 (17 m ? ) point @ 0.75 fsr point @ 0.50 fsr point @ 0.25 fsr point @ 0.1 fs point @ 0.05fsr % full-scale range (fsr), led control bit =0, channels 2,3,4 (6.0 m ? ) point @ 0.75 fsr point @ 0.50 fsr point @ 0.25 fsr point @ 0.1 fsr ? i cs / i cs -14 -15 -17 -25 -40 -14 -15 -17 -34 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 14 15 17 25 40 14 15 17 34 % current sense error with one calibration point (50% fsr, v bat = 13.5 at 25 c (10) -6.0 ? 6.0 % current sense error with one calibration point (50% fsr led , v bat = 13.5 at 25 c (10) -6.0 ? 6.0 % temperature drift of current sense output (11) v bat = 13.5 v, i out1,5 = 2.8 a, i out2-4 = 5.5 a, reference taken at t a =25 c ? ? i cs / ? t ? 280 400 ppm/c over-temperature shutdown t ots 155 175 195 c notes 9. 10 v < v bat < 16 v. ? i cs / i cs = (measured i cs - targeted i cs )/ targeted i cs with targeted i cs = 5.0 ma. test conditions of accuracy measurement of point i(hs[1]) @ 0.05*fsr: i(hs[5]) = 0, i(hs[2]) = i(hs[3]) = i(hs[4]) =8.0 a 10. based on statistical analysis covering 99.74% of parts, except 10% of fsr. refer to current sense section for more details. 11. based on statistical data. not production tested. ? ? i cs / ? t = [(measured i cs at t 1 - measured i cs at t 2 ) / measured i cs at room] / (t 1 -t 2 ) table 3. static electrical characteristics (continued) characteristics noted under conditions 3.0 v ? v cc ? 5.5 v, 7.0 v ? v bat ? 20 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit analog integrated circuit device data ? freescale semiconductor 9 06XS3517 electrical characteristics static electrical characteristics outputs (out 1-5) (continued) thermal prewarning (12) t otswarn 110 125 140 c output voltage threshold v out_th 0.475 0.5 0.525 vbat channel 1 - parking light (17 m ? channel) output drain-to-source on resistance (i out = 2.8 a, t a = 25 c) v bat = 13.5 v v bat = 7.0 v r ds(on)25 ? ? ? ? 17 26.7 m ? output drain-to-source on resistance (i out = 2.8 a, v bat = 13.5 v, t a = 150 c) (12) r ds(on)150 ? ? 28.9 m ? reverse output on resistance (i out = -2.8 a, t a = 25 ? c) (13) v bat = -12 v r sd(on) ? ? 34 m ? high over-current shutdown threshold 1, v bat = 16 v i ochi1 48 56.2 72 a high over-current shutdown threshold 2 i ochi2 21.0 25.8 30.5 a low over-current shutdown threshold i oclo 9.0 11.5 14 a open load-current threshold in on state (14) i ol 0.08 0.3 0.77 a open load-current threshold in on state with led (15) v out = v bat - 0.8 v i olled 4.0 10.0 20.0 ma current sense full-scale range (16) i cs fsr ? 9.5 ? a severe short-circuit impedance range (17) r sc1(out1) 225 ? ? m ? channel 2 - low beam (6.0 m ? channel) output drain-to-source on resistance (i out = 5.5 a, t a = 25 c) v bat = 13.5 v v bat = 7.0 v r ds(on)25 ? ? ? ? 6.0 9.0 m ? output drain-to-source on resistance (i out = 5.5 a, v bat = 13.5 v, t a = 150 c) (17) r ds(on)150 ? ? 10.2 m ? reverse source-to-drain on resistance (i out = -5.5 a, t a = 25 ? c) (18) v bat = -12 v r sd(on) ? ? 12.0 m ? high over-current shutdown threshold 1, v bat = 16 v i ochi1 96 123 150 a high over-current shutdown threshold 2 i ochi2 40 50.5 61 a notes 12. parameter guaranteed by design, however, it is not production tested. 13. source-to-drain on resistance (reverse drain-to -source on resistance) with negative polarity v bat . 14. olled1, bit d0 in si data is set to [0]. 15. olled1, bit d0 in si data is set to [1]. 16. for typical value of i cs fsr, i csns = 5.0 ma. 17. parameter guaranteed by design; however, it is not production tested. 18. source-to-drain on resistance (reverse drain-to -source on resistance) with negative polarity v bat . table 3. static electrical characteristics (continued) characteristics noted under conditions 3.0 v ? v cc ? 5.5 v, 7.0 v ? v bat ? 20 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit analog integrated circuit device data ? 10 freescale semiconductor 06XS3517 electrical characteristics static electrical characteristics channel 2 - low beam (6.0 m ? channel) (continued) low over-current shutdown threshold optional xenon lamp optional h7 bulb i oclo 28 17 35 22.5 42 28 a open load current threshold in on state (19) i ol 0.15 0.62 1.55 a open load current threshold in on state with led (20) v ol = v bat - 0.8 v i olled 4.0 10.0 20.0 ma current sense full-scale range (21) optional xenon bulb optional h7 bulb i cs fsr ? ? 30 19 ? ? a severe short-circuit impedance range (22) r sc1(out2) 65 ? ? m ? channel 3- high beam (6.0 m ? channel) output drain-to-source on resistance (i out = 5.5 a, t a = 25 c) v bat = 13.5 v v bat = 7.0 v r ds(on)25 ? ? ? ? 6.0 9.0 m ? output drain-to-source on resistance (i out = 5.5 a, v bat = 13.5 v, t a = 150 c) (22) r ds(on)150 ? ? 10.2 m ? reverse source-to-drain on resistance (i out = -5.5 a, t a = 25 ? c) (23) v bat = -12 v r sd(on)25 ? ? 12 m ? high over-current shutdown threshold 1, v bat = 16 v i ochi1 96 123 150 a high over-current shutdown threshold 2 i ochi2 40 50.5 61 a low over-current shutdown threshold h7 bulb i oclo 17 22.5 28 a open load current threshold in on state (24) i ol 0.15 0.62 1.55 a open load current threshold in on state with led (25) v ol = v bat - 0.8 v i olled 4.0 10.0 20.0 ma current sense full-scale range (21) i cs fsr ? 19 ? a severe short-circuit impedance range (22) r sc1(out3) 65 ? ? m ? notes 19. olled2, bit d1 in si data is set to [0]. 20. olled2, bit d1 in si data is set to [1]. 21. for typical value of i cs fsr, i csn s = 5.0ma. 22. parameter guaranteed by design; however, it is not production tested. 23. source-to-drain on resistance (reverse drain-to -source on resistance) with negative polarity v bat . 24. olled3, bit d2 in si data is set to [0]. 25. olled3, bit d2 in si data is set to [1]. table 3. static electrical characteristics (continued) characteristics noted under conditions 3.0 v ? v cc ? 5.5 v, 7.0 v ? v bat ? 20 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit analog integrated circuit device data ? freescale semiconductor 11 06XS3517 electrical characteristics static electrical characteristics channel 4 - fog light(6.0 m ? channel) output drain-to-source on resistance (i out = 5.5 a, t a = 25 c) v bat = 13.5 v v bat = 7.0 v r ds(on)25 ? ? ? ? 6.0 9.0 m ? output drain-to-source on resistance (i out = 5.5 a, v bat = 13.5 v, t a = 150 c) (26) r ds(on)150 ? ? 10.2 m ? reverse source-to-drain on resistance (i out = -5.5 a, t a = 25 ? c) (27) v bat = -12 v r sd(on)25 ? ? 12 m ? high over-current shutdown threshold 1, v bat = 16 v i ochi1 96 123 150 a high over-current shutdown threshold 2 i ochi2 40 50.5 61 a low over-current shutdown threshold h7 bulb i oclo 17 22.5 28 a open load current threshold in on state (28) i ol 0.15 0.62 1.5 a open load current threshold in on state with led (29) v ol = v bat - 0.8 v i olled 4.0 10.0 20.0 ma current sense full scale range (30) i cs fsr ? 19 ? a severe short-circuit impedance range (26) r sc1(out4) 65 ? ? m ? channel 5 - flasher (17 m ? channel) output drain-to-source on resistance (i out = 2.8 a, t a = 25 c) v bat = 13.5 v v bat = 7.0 v r ds(on)25 ? ? ? ? 17 26.7 m ? output drain-to-source on resistance (i out = 2.8 a, v bat = 13.5 v, t a = 150 c) (31) r ds(on)150 ? ? 18.9 m ? reverse source-to-drain on resistance (i out = -2.8a, t j = 25 ? c) (32) v bat = -12v r sd(on)25 ? ? 34 m ? high over-current shutdown threshold 1, i ochi1 48 56.2 72 a high over-current shutdown threshold 2 i ochi2 21.0 25.8 30.5 a low over-current shutdown threshold i oclo 9.0 11.5 14 a notes 26. parameter guaranteed by design; however, it is not production tested. 27. source-to-drain on resistance (reverse drain-to -source on resistance) with negative polarity v bat . 28. olled4, bit d3 in si data is set to [0]. 29. olled4, bit d3 in si data is set to [1]. 30. for typical value of i cs fsr, i csn s = 5.0 ma. 31. parameter guaranteed by design; however, it is not production tested. 32. source-to-drain on resistance (reverse drain-to -source on resistance) with negative polarity v bat . table 3. static electrical characteristics (continued) characteristics noted under conditions 3.0 v ? v cc ? 5.5 v, 7.0 v ? v bat ? 20 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit analog integrated circuit device data ? 12 freescale semiconductor 06XS3517 electrical characteristics static electrical characteristics channel 5 - flasher (17 m ? channel) (continued) open load current threshold in on state (33) i ol 0.08 0.3 0.77 a open load current threshold in on state with led (34) v ol = v bat - 0.8 v i olled 4.0 10.0 20.0 ma current sense full scale range (35) i cs fsr ? 8.8 ? a severe short-circuit impedance range (36) r sc1(out5) 225 ? ? m ? spare fetout(out6) / fetin (out1) fetout output high level @ i = 1.0 ma v h max 0.8 ? ? v cc fetout output low level @ i = -1.0 ma v h min ? 0.2 0.4 v fetin input full scale range current i fet in ? 5.0 ? ma fetin input clamp voltage i fet in = 5.0 ma, csns open v clin 5.3 ? 13 v drop voltage on fetin (fetin - csns) i fet in = 5.0 ma, 5.5 v > csns > 3.0 v v drin 0.0 ? 0.4 v fetin leakage current when external current switch sense is enabled 5.5 v > v fet in > 0.0 v, csns open i fetinleak - 1.0 ? 6.0 ? a temperature of gnd flag analog temperature feedback range t feed_range -40 ? 150 c analog temperature feedback at t a = 25 c with 5.0 k ? > r csns > 500 ? v t_feed 925 1000 1075 mv analog temperature feedback derating with 5.0 k ? > r csns > 500 ? ? (36) v dt_feed 10.9 11.3 11.7 mv/c analog temperature feedback precision (36) v dt_acc -15 ? 15 c analog temperature feedback precision with calibration point at 25 c (36) v dt_acc_cal -5.0 ? 5.0 c notes 33. olled5, bit d4 in si data is set to [0]. 34. olled5, bit d4 in si data is set to [1]. 35. for typical value of i cs fsr, i csn s = 5.0 ma. 36. parameter guaranteed by design; however, it is not production tested. table 3. static electrical characteristics (continued) characteristics noted under conditions 3.0 v ? v cc ? 5.5 v, 7.0 v ? v bat ? 20 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit analog integrated circuit device data ? freescale semiconductor 13 06XS3517 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 4. dynamic electrical characteristics characteristics noted under conditions 3.0 v ? v cc ? 5.5 v, 7.0 v ? v bat ? 20 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit power outputs timing (out1 to out5) current sense valid time (val id for resistive loads only), (37) sr bit = 0 sr bit = 1 t csns(val) 0 0 100 50 200 100 ? s current sense settling time on resistive load only (37) t csns(set) ? 10 30 ? s current sense synchronization si gnal - typical validation time sr bit = 0 sr bit = 1 t sync(val) 0 0 90 45 180 90 driver output positive slew rate (30% to 70% @ v bat = 14 v) sr bit = 0 i out = 2.8 a for out1 and out5 i out = 5.5 a for out2, out3, and out4 sr bit = 1 i out =0.7 a for out1 and out5 i out = 1.4 a for out2, out3, and out4 sr r 0.14 0.2 0.28 0.4 0.4 0.4 0.8 0.8 0.8 0.8 1.6 1.6 v/ ? s driver output negative slew rate (70% to 30% @ v bat = 14 v) sr bit = 0 i out = 2.8 a for out1 and out5 i out = 5.5 a for out2, out3, and out4 sr bit = 1 i out = 0.7 a for out1 and out5 i out = 1.4 a for out2, out3, and out4 sr f 0.14 0.2 0.28 0.4 0.4 0.4 0.8 0.8 0.8 0.8 1.6 1.6 v/ ? s driver output matching slew rate (sr r /sr f ) (70% to 30% @ v bat = 14 v @25 c) sr bit = 0: i out = 2.8 a for out1 and out5 and i out = 5.5 a for out2/3/4 sr bit = 1: i out = 0.7 a for out1 and out5 and i out = 1.4 a for out2/3/4 ? ? sr 0.8 0.8 1.0 1.0 1.2 1.2 driver output turn-on delay (spi on command [no pwm, cs positive edge] to output = 50% v bat @ v bat = 14 v) (see figure 6 ) sr bit = 0: i out = 2.8 a for out1 and out5 and i out = 5.5 a for out2/3/4 sr bit = 1: i out = 0.7 a for out1 and out5 and i out = 1.4 a for out2/3/4 t dlyon 65 35 ? ? 300 120 ? s driver output turn-off delay (spi off command [ cs positive edge] to output = 50% v bat @ v bat = 14 v) (see figure 6 ) sr bit = 0: i out = 2.8 a for out1 and out5 and i out = 5.5 a for out2/3/4 sr bit = 1: i out = 0.7 a for out1 and out5 and i out = 1.4 a for out2/3/4 t dlyoff 40 15 ? ? 110 80 ? s notes 37. not production tested. see figure 7, current sensing time delays . analog integrated circuit device data ? 14 freescale semiconductor 06XS3517 electrical characteristics dynamic electrical characteristics power outputs timing (o ut1 to out5) (continued) driver output matching time ( t dly(on) - t dly(off) ) @ output = 50% v bat with v bat = 14 v, f pwm = 240 hz, ? pwm = 50%, @25 c sr bit = 0: i out = 2.8 a for out1 and out5 and i out = 5.5 a for out2/3/4 sr bit = 1: i out = 0.7 a for out1 and out5 and i out = 1.4 a for out2/3/4 ? ? t rf 10 5.0 ? ? 200 70 ? s pwm module pwm frequency range f pwm 60.0 ? 400 hz clock input frequency range f clk 7.68 ? 51.2 khz output pwm duty cycle maximum range for 11 v analog integrated circuit device data ? 16 freescale semiconductor 06XS3517 electrical characteristics timing diagrams timing diagrams figure 4. input timing switching characteristics figure 5. sclk waveform and valid so data delay time si csb sclk don?t care don?t care don?t care valid valid vih vil vih vih vil vil vil twrstb tlead twsclkh trsi tlag tsisu twsclkl tsi(hold) tfsi 0.7 vdd 0.7vdd 0.2vdd 0.2vdd 0.7vdd 0.7vdd tcsb tenbl sclkb sib csb 10% v cc t lead t wsc lkh t rsi 90% v cc 10% v cc t si(su) t wsc lkl t si(hold) t fsi 90% v cc t lag vih vil vil vih vil vih vil t enbl t csb 90% v cc 10% v cc so so sclk voh vol voh vol voh vol tfsi tdlylh tdlyhl t valid trso tfso 3.5v 50% trsi high-to-low 1.0v 0.7 vdd 0.2vdd 0.2 vdd 0.7 vdd low-to-high t rsi t fsi 90% v cc sclkb sob sob voh vol voh vol voh vol 0.8 v 10% v cc 90% v cc t rso t fso 10% v cc t so(en) t so(dis) 2.0 v low to high high to low t valid analog integrated circuit device data ? freescale semiconductor 17 06XS3517 electrical characteristics timing diagrams figure 6. output slew rate and time delays figure 7. current sensing time delays v pwr v out[1:5] t dly(on) t dly(off) low logic level 70% v pwr 30% v pwr sr f sr r 50%v pwr r pwm csb high logic level v out[1:5] time time time i max i out[1:5] t dly(on) t csns(set) low logic level csb high logic level i csns time time time t csns(val) v fetout time low logic level high logic level t dly(off) only available with csns sync bit = 1 t sync(val) analog integrated circuit device data ? 18 freescale semiconductor 06XS3517 functional description introduction functional description introduction the 06XS3517 is designed for low-voltage automotive and industrial lighting applications. its five low r ds(on) mosfets (three 6.0 m ?? and ? two 16 m ? ) can control the high sides of five separate resistive loads (bulbs). programming, control, and diagnostics are accomplished using a 16-bit spi interface. functional pin description supply voltage (vbat) the vbat pin of the 06XS3517 is the power supply of the device. in addition to its supply function, this tab contributes to the thermal behavior of the device by conducting the heat from the switching mosfets to the printed circuit board. supply voltage (vcc) this is an external voltage input pin used to supply the digital portion of the circuit and the gate driver of the external smart mosfet. ground (gnd) this pin is the ground of the device. clock input / wake-up output (clock) when the part is in normal mode ( rst =1), the pwm frequency and timing are generated from the rising edge of clock input by the pwm module. the clock input frequency is the selectable factor 2 7 = 128 or 2 8 = 256 of the pwm frequency per output, depending pr bit value. the out1:6 can be controlled in the range of 4% to 96% with a resolution of 7 bits of the duty cycle (bits d[6:0]). figure 5 describes the pwm resolution. the timing includes four programmable pwm switching phases (0, 90, 180, and 270) to improve overall emc behavior of the light module. as an example: when the load currents have equal amplitude, the amplitude of the input current is divided by four, while the ripple frequency is 4 times the original. the two following pictures illustrate this behavior. the synchronization of the switching phases between different ic is provided by an spi command in combination with the csb input. the bit in the spi is called pwm sync (initialization register). in normal mode, no pwm feature (100% duty cycle) is provided in the following instances: ? with the following spi configuration: d7:d0=ff. ? in case of clock input signal failure (out of f pwm ), the outputs state depends of d7 bit value (d7=1=on) in normal mode. in fail mode, the ouputs state depend on ign, flasher, and fog pins. if rstb=0, this pin reports the wake-up event for wake=1 when vbat and vcc are in operational voltage range. limp home input (limp) the fail mode of the component can be activated by this digital input port. the signal is ?high active?, meaning the fail mode can be activated by a logic high signal at the input. ignition input (ign) the ignition input wakes the device. it also controls the fail mode activation. the signal is ?high active?, meaning the component is active in case of a logic high at the input. table 5. pwm resolution on/off (bit d7) duty cycle (7 bits resolution) output state 0 x off 1 0000000 pwm (1/128 duty cycle) 1 0000001 pwm (2/128 duty cycle) 1 0000010 pwm (3/128 duty cycle) 1 1111111 fully on analog integrated circuit device data ? freescale semiconductor 19 06XS3517 functional description functional pin description flasher input (flasher) the flasher input wakes the devic e. it also controls the fail mode activation. the signal is ?high active?, meaning the component is active in case of a logic high at the input. fog input (fog) the fog input wakes the device. it also controls the fail mode activation. the signal is ?high active?, meaning the component is active in case of a logic high at the input. reset input ( rstb ) this input wakes the device when the rstb pin is at logic [1]. it is also used to initialize the device configuration and the spi faults registers when the signal is low. all si/so registers described table 8 and table are reset. the fault management is not affected by rstb (see figure 2 ). current sense output (csns) the current sense output pin is an analog current output or a voltage proportional to the temperature on the gnd flag. the routing to the external resistor is spi programmable. this current sense monitori ng may be synchronized in case of the out6 is not used. the csns output is valid after a rising edge on the fetout pin (after t sync(val) s.) if the csns sync spi bit was set to logic [0] and remains valid till a falling edge is generated. connection of the fetout pin to a mcu input pin allows the mcu to sample the csns pin during a valid time slot. since this falling edge is generated at the end of this time slot, upon a switch-off command, this feature may be used to implement maximum current control. charge pump (cp) an external capacitor must be connected between the cp and the v bat pin. it is used as a tank for the internal charge pump. its value is 100 nf 20%, 25 v maximum. fet out output (fetout) this output pin can be used to control an external smart mosfet (out6) at a logi c level (1=on, 0=off). the high level of the fetout output is v cc , if v bat and v cc are available, in case fetout is a controlled on. fetout is not protected if ther e is a short-circuit or under- voltage on vbat. in case of a reverse battery, out6 is off. fet in input (fetin) this input pin receives the current recopy from an external smart mosfet. it can be routed on csns output by a spi command. spi protocol description the spi interface has a full-duplex, three-wire, synchronous data transfer with four i/o lines associated with it: serial clock (sclk), serial input (si), serial output (so), and chip select (csb). the si/so pins of the 06XS3517 device follow a first-in, first-out (d15 to d0) protoc ol, with both input and output words transferring the most significant bit (msb) first. all inputs are compatible with 3.3 v and 5.0 v cmos logic levels, supplied by v cc . the spi lines perform the following functions: serial clock (sclk) the sclk pin clocks the internal shift registers of the 06XS3517 device. the si pin accepts data into the input shift register on the falling edge of the sclk signal, while the so pin shifts data information out of the so line driver on the rising edge of the sclk signal. it is important that the sclk pin be in a logic low state whenever csb makes any transition. for this reason, it is recommended the sclk pin be in a logic [0] whenever the device is not accessed (csb logic [1] state). sclk has a passive pull-down, r dwn . when csb is logic [1], signals at the sclk and si pins are ignored, and so is tri-stated (high-impedance) (see figure 8 ). analog integrated circuit device data ? 20 freescale semiconductor 06XS3517 functional description functional pin description figure 8. single 16-bit word spi communication serial input (si) the si pin is a serial interface command data input pin. each si bit is read on the falling edge of sclk. a 16-bit stream of serial data is required on the si pin, starting with d15 to d0. si has a passive pull-down, r down . serial output (so) the so data pin is a tri-stateable output from the shift register. the so pin remains in a high-impedance state until the csb pin is put into a logic [0] state. the so data is capable of reporting the status of the output, the device configuration, and the state of the key inputs. the so pin changes state on the rising edge of sclk and reads out on the falling edge of sclk. chip select ( cs ) the csb pin enables communication with the master device. when this pin is in a logic [0] state, the device is capable of transferring information to, and receiving information from, the master device. the 06XS3517 device latches in data from the input sh ift registers to the addressed registers on the rising edge of csb. the device transfers status information from the power output to the shift register on the falling edge of csb. the so output driver is enabled when csb is logic [0]. csb should transition from a logic [1] to a logic [0] state only when sclk is a logic [0]. csb has a passive pull-up, r up . cs csb si sclk so d15 d1 d2 d3 d4 d5 d6 d7 d8 d9 d14 d13 d12 d11 d10 od12 d0 od13 od14 od15 od6 od7 od8 od9 od10 od11 od1 od2 od3 od4 od5 1. rstb is in a logic h state during the above operation. 2. do, d1, d2, ... , and d15 relate to the most recent ordered entry of program data into the lux ic 3. od0, od1, od2, ..., and od15 relate to the first 16 bits of ordered fault and status data out of the lux ic notes: od0 cs device. device. 1. d15 : d0 relate to the most recent ordered entry of data into the device. 2. od15 : od0 relate to the first 16 bits of or dered fault and status data out of the device. notes analog integrated circuit device data ? freescale semiconductor 21 06XS3517 functional device operation operation modes functional device operation operation modes sleep mode the sleep mode is the default mode of the 06XS3517. this is the state of the devic e after first applying battery voltage (v bat ) and prior to any i/o transitions. this is also the state of the device when ig n, fog, flasher, and rstb are logic [0] (wake=0). in the sleep mode, the outputs and all internal circuitry are off to minimize current draw. in addition, all spi-configurable features of the device are reset. the 06XS3517 will transit to two modes (normal and fail) depending on wake and fail signals (see fig13). the transition to the other modes is according following signals: ? wake = ign or ign_on or flasher or flasher_on or rstb or fog or fog_on ? fail = vcc fail or spi fail or external limp normal mode the 06XS3517 is in normal mode when: ? wake = 1 ? fail = 0 i n normal operating mode the power outputs are under full control of the spi as follows: ? the outputs 1 to 6, including multiphase timing and selectable slew-rate, are controlled by the programmable pwm module. ? the outputs 1 to 5 are switched off in case of an under-voltage on vbat. ? the outputs 1 to 5 are protec ted by the selectable over- current double window and ov er-temperature shutdown circuit. ? the digital diagnosis featur e transfers status of the smart outputs via spi. ? the analog current sense output (current recopy feature) can be routed by spi. ? the outputs 1 and 5 can be configured to control led loads. ? the spi reports nm=1 in this mode. the figure below describes the pwm, outputs and over- current behavior in normal mode. fail mode the 06XS3517 is in fail mode when: ? wake = 1 ? fail = 1. i n fail mode: ? the outputs are under control of external pins (see table 6 ) ? the outputs are fully protect ed in case of an overload, over-temperature and under-voltage (on vbat or on vcc). ? the spi reports continuously the content of address 11 (initialization register), re gardless previously requested output data word. ? analog current sense is not available. ? output 2 is configured in xenon mode. ? in case of an overload (ochi2 or oclo) conditions or under-voltage on vbat, the outputs are under control of autorestart feature. ? in case of serious overload condition (ochi1 or ot) the corresponding output is latched off until a new wake- up event (wake=0 then 1). table 6. output states during limp home over-current output d0-d6 bits d7 bit over-current out[1,2] ign (external) ign_on 1.4 sec min output 1 parking light output 2 low beam output 3 high beam output 4 fog light output 5 flasher external switch spare ign pin ign pin off fog pin flasher pin off analog integrated circuit device data ? 22 freescale semiconductor 06XS3517 functional device operation operation modes autorestart strategy the autorestart circuitry is used to supervise the outputs and reactivate high side switches in cases of overload or under-voltage failure conditions , to provide a high availability of the outputs. autorestart feature is availabl e in fail mode (after loss of spi communication). autorestart is activated in case of overload condition (ochi2 or oclo) or under-voltage condition on vbat (see figure 12 ). the autorestart periodically switches on the outputs. during on state of the switch ochi1 window is enabled for tochi_auto, then after the output is protected by oclo. figure 9. over-current window in case of autorestart in case of ochi1 or ot, the channel is latched off until wake-up (wake=0 then 1). in case of oclo or under-voltage, the output is switched off and turned on again automat ically after the autorestart period (150 ms for 6.0 mohm channels or 75 ms for 17 mohm channels). in case of an under-voltage in fail mode, the outputs 1 to 5 will be latched off. the correspon ding output is switched on only after the autorestart period (t autorst-t1 or t autorst-t2 ). the autorestart is not limited in time. transition fail to normal mode to leave fail mode, the fail condition must be removed (fail=0). the microcontroller has to toggle the spi d10 bit (0 to 1) to reset the watchdog bi t (wd); the other bits are not considered. the previous latc hed faults are reset by the transition into normal mode. transition normal to fail mode to leave the normal mode, a fail condition must occur (fail=1). the previous latched f aults are reset by the transition into fail mode. if the si is shorted to vdd, the device transmits to fail safe mode until the wd bit to ggles through t he spi (from [0] to [1]). all settings are according to predefined values (all bits set to logic [0]). start-up sequence the 06XS3517 enters in normal mode after start-up if following sequence is provided: ? vbat and vcc power supplie s must be above their under-voltage thresholds (sleep mode). ? generate wake up event (wake=1) from 0 to 1 on rstb . the device switches to normal mode. ? apply pwm clock after maximum 200 ? s (min 50 ? s). ? send spi command to the device status register to clear the clock fail flag to enable the pwm module to start. figure 10 describes the wake-up block diagram. power off mode the 06XS3517 is in power off mode when the battery voltage is below v batpor[1,2] thresholds. for more details, refer to loss of vbat . output current ochi1 oclo time tochi_auto auto period oclo or uv fault analog integrated circuit device data ? freescale semiconductor 23 06XS3517 functional device operation operation modes figure 10. operating modes state machine sleep (fail=0) and (wake=1) (wake=0) fail normal (wake=0) (fail=1) and (wake=1) (fail=0) and (wake=1) (wake=1) and (fail=1) * notes: * only available in case of a vcc fail condition wake = (rstb = 1) or (ign_on = 1) or (flasher_on = 1) or (fog_on = 1) fail = (vcc_fail = 1) or (spi_fail = 1) or (ext_limp = 1) power off v bat > v batpor[1,2] v bat < v batpor[1,2] v bat < v batpor[1,2] v bat < v batpor[1,2] analog integrated circuit device data ? 24 freescale semiconductor 06XS3517 functional device operation operation modes figure 11. wake-up block diagram internal regulator fault management pwm freq detector oscillator spi registers pwm module rstb fog ign vbat vcc dig2.5v wake-up bar fog_on ign_on wake fail spi fail vcc fail external limp or watchdog watchdog reset flasher flasher_on watchdog external_on external external: ign, flasher, fog external_on: ign_on, flasher_on, fog_on 1.4 sec min clock uvf or vcc vbat analog integrated circuit device data ? freescale semiconductor 25 06XS3517 functional device operation logic commands and registers logic commands and registers serial input communication spi communication compliant to 3.3 v and 5.0 v is accomplished using 16-bit messages. a message is transmitted by the master star ting with the msb, d15, and ending with the lsb, d0. each incoming command message on the si pin can be interpreted using the bit assignment described in table 7 . the 5 bits d15 : d11, called register address bits, are used to select the command register. bit d10 is the watchdog bit. the remaining 10 bits, d9 : d0, are used to configure and control t he output and its protection features. multiple messages can be transmitted in succession to accommodate those applications where daisy chaining is desirable or to conf irm transmitted data as long as the messages are all multiples of 16 bits. any attempt made to latch in a message that is not 16 bits will be ignored. all spi registers are reset (all bit equal 0) in case of rstb equal 0 or fail mode (fail=1). device register addressing the register addresses (d15 : d11) and the impact of the serial input registers on device operation are described in this section. table 8 summarizes the si registers. table 7. si message bit assignment bit sig si msg bit message bit description msb d15 : d11 register address bits. d10 watchdog in: toggled to satisfy watchdog requirements. lsb d9 : d0 used to configure inputs, outputs, device protection features, and so status content. table 8. serial input address and configuration bit map si register si address si data d1 5 d1 4 d1 3 d1 2 d1 1 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 initialization 0 0 0 0 0 wd 0 0 fogen pwm sync xenon mux2 mux1 mux0 soa1 soa0 config ol 0 0 0 0 1 wd 05 0 0 0 0 olled5 olled4 olled3 olled2 olled1 config prescaler 0 0 0 1 0 wd 0 pr1 pr2 pr3 0 0 0 pr4 pr5 pr6 config sr 0 0 0 1 0 wd 1 sr1 sr2 sr3 0 0 0 sr4 sr5 0 config csns 0 0 0 1 1 wd csns sync 0 0 0 0 no_oc hi5 no_oc hi4 no_oc hi3 no_oc hi2 no_oc hi1 control out1 0 1 0 0 1 wd phase2 phase1 onoff pwm6 pwm5 pwm4 pwm3 pwm2 pwm1 pwm0 control out2 0 1 0 1 0 wd phase2 phase1 onoff pwm6 pwm5 pwm4 pwm3 pwm2 pwm1 pwm0 control out3 0 1 0 1 1 wd phase2 phase1 onoff pwm6 pwm5 pwm4 pwm3 pwm2 pwm1 pwm0 control out4 0 1 1 0 0 wd phase2 phase1 onoff pwm6 pwm5 pwm4 pwm3 pwm2 pwm1 pwm0 control out5 0 1 1 0 1 wd phase2 phase1 onoff pwm6 pwm5 pwm4 pwm3 pwm2 pwm1 pwm0 control external switch 0 1 1 1 0 wd phase2 phase1 onoff pwm6 pwm5 pwm4 pwm3 pwm2 pwm1 pwm0 reset x x x x x 0 0 0 0 0 0 0 0 0 0 0 note: testmode address used only by fsl is d[15:1 1]=01111 with rstb pin voltage higher than 8.0 v typ. ? x = don?t care and 0 = need to rewrite logic ?0? analog integrated circuit device data ? 26 freescale semiconductor 06XS3517 functional device operation logic commands and registers address 00000 ? initialization the initialization register is used to read the various statuses, choose one of the six outputs current recopy, load the h7 bulbs profile for out2 only, enable the fog pin and synchronize the switching phas es between different devices. the register bits d1 and d0 determine the content of the 16 bits of the next so data. (refer serial output communication (device status return data) ) table describes the register of initialization. the watchdog timeout is specified by t wdto parameter. as long as the wd bit (d10) of an incoming spi message is toggled within the minimum watchdog timeout period (wdto), the device will operate normally. if an internal watchdog timeout occurs before the wd bit is toggled, the device will revert to fail mode. all registers are cleared. to exit the fail mode, send va lid spi communication with wd bit = 1. address 00001 ? configuration ol the configuration ol register is used to enable the open load detection for leds in normal mode (olledn in table 8 ) and to active the led control. when bit d0 is set to logic [1], the open load detection circuit for led is activated for output 1. when bit d0 is set to logic [0], open load detection circuit for standard bulbs is activated for output 1. when bit d5 is set to logic [1], the led control is activated for output 1. address 00010 ? configuration prescaler and sr two configuration registers are available at this address. the configuration prescaler when d9 bit is set to logic [0] and configuration sr when d9 bit is set to logic [1]. the configuration prescaler r egister is used to enable the pwm clock prescaler per output. when the corresponding pr bit is set to logic [1], the clock presca ler (reference clock divided by 2) is activated for the dedicated output. the sr prescaler register is used to increase the output slew rate by a factor of 2. when the corresponding sr bit is set to logic [1], the output switching time is divided by 2 for the dedicated output. address 00011 ? configuration csns the configuration current sense register is used to disable the high over-curre nt shutdown phase (ochi1 and ochi2 dynamic levels) in order to activate immediately the current sense analog feedback. when bit d9 is set to logic [1], the current sense synchronization signal is reported on fetout output pin. when the corresponding no_ochi bit is set to logic [1], the output is only protected wi th oclo level. the current sense is immediately available if it is selected through spi, as described in figures 13 . the no_ochi bit per output is automatically reset at each corresponding on/off bit transition from logic [1] to [0], and in case of over-temperature or over-current fault. all no_ochi bits are also reset in case of under-voltage fault detection. address 01001 ? control out1 bits d9 and d8 control the switching phases as shown in table 10 . table 9. initialization register si address si data d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 wd 0 0 fogen pwm sync xenon mux2 mux1 mux0 soa1 soa0 d6 (pwm sync) = 0, no synchronization d6 (pwm sync) = 1, synchronization on csb positive edge d5 ( xenon ) = 0, xenon d5 ( xenon ) = 1, h7 bulb d7 (fogen) = 0, fog pin does not control the output 4 d7 (fogen) = 1, fog input controls the output 4 d4, d3, d2 (mux2, mux1, mux0) = 000, no current sense d4, d3, d2 (mux2, mux1, mux0) = 001, out1 current sense d4, d3, d2 (mux2, mux1, mux0) = 010, out2 current sense d4, d3, d2 (mux2, mux1, mux0) = 011, out3 current sense d4, d3, d2 (mux2, mux1, mux0) = 100, out4 current sense d4, d3, d2 (mux2, mux1, mux0) = 101, out5 current sense d4, d3, d2 (mux2, mux1, mux0) = 110, external switch current sense d4, d3, d2 (mux2, mux1, mux0) = 111, temperature analog feedback table 10. switching phases d9 : d8 pwm phase 00 0 01 90 10 180 11 270 analog integrated circuit device data ? freescale semiconductor 27 06XS3517 functional device operation logic commands and registers bit d7 at logic [1] turns on out1. out1 is turned off with bit d7 at logic [0]. this register allows the master to control the duty cycl e and the switching phases of out1. the duty cycle resolution is given by bits d6 : d0. d7 = 0, d6 : d0 = xx output off. d7 = 1, d6 : d0 = 00 output on during 1/128. d7 = 1, d6 : d0 = 1a output on during 27/128 on pwm period. d7 = 1, d6 : d0 = 7f output continuous on (no pwm). address 01010 ? control out2 same description as out1. address 01011 ? control out3 same description as out1. address 01100 ? control out4 same description as out1. address 01101 ? control out5 same description as out1. address 01110 ? control external switch same description as out1. address 01111 ? test mode this register is reserved for test and is not available with spi during normal operation. serial output communication (device status return ? data) when the csb pin is pulled low, the output register is loaded. meanwhile, the data is clocked out msb first as the new message data is clocked into the si pin. the first 16 bits of data clocking out of the so, and following a csb transition, is dependant upon the previous ly written spi word (soa1 and soa0 defined in the last spi initialization word). any bits clocked out of the so pin after the first 16 will be representative of the initial me ssage bits clocked into the si pin since the csb pin first transitioned to a logic [0]. this feature is useful for daisy chaining devices. a valid message length is determined following a csb transition of logic [0] to logic [1]. if the message length is valid, the data is latched into t he appropriate registers. a valid message length is a multiple of 16 bits. at this time, the so pin is tri-stated and the fault status register is now able to accept new fault status information. the output status register corre ctly reflects the status of the initialization-selected regist er data at the time that the csb is pulled to a logic [0] during spi communication and / or for the period of time since the last valid spi communication, with the following exceptions: ? the previous spi communication was determined to be invalid. in this case, the status will be reported as though the invalid spi communication never occurred. ? battery transients below 6.0 v, resulting in an under- voltage shutdown of the outputs, may result in incorrect data loaded into the status register. serial output bit assignment the contents of bits od15 : od0 depend on bits d1: d0 from the most recent initiali zation command soa[1:0] (refer to table 8 ), and as explained in the paragraphs that follow. the register bits are reset by a read operation and also if the fault is removed. table 11 summarizes the so register content. bit od10 reflects normal mode (nm). table 11. serial output bit map description status / mode previous si data so data so a1 so a0 od1 5 od1 4 od13 od12 od11 od1 0 od9 od8 od7 od6 od5 od4 od3 od2 od1 od0 fault status 0 0 0 0 uvf otw ots nm ol5 ovl5 ol4 ovl4 ol3 ovl 3 ol2 ovl2 ol1 ovl1 overloa d status 0 1 0 1 uvf otw ots nm oc5 ots5 oc4 ots4 oc3 ots 3 oc2 ots2 oc1 ots1 device status 1 0 1 0 uvf otw ots nm 0 ov x x x rc fog pin flashe r pin ign pin clock fail output status 1 1 1 1 uvf otw ots nm 0 0 0 0 0 out 5 out4 out3 out 2 out1 reset x x 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 x = don?t care analog integrated circuit device data ? 28 freescale semiconductor 06XS3517 functional device operation logic commands and registers previous address soa[1:0] = 00 if the previous two l sbs are 00, bits od15 : od0 reflect the fault status ( table 11 ). previous address soa[1:0] = 01 if the previous two lsbs are 01, bits od15 :o d0 reflect the temperature status ( table 13 ). previous address soa[1:0] = 10 if the previous two lsbs are 10, bits od15 : od0 reflect the status of the 06XS3517 ( table 14 ). table 12. fault status od15 od14 od13 od12 od11 od10 od9 od8 od7 od6 od5 od4 od3 od2 od1 od0 0 0 uvf otw ots nm ol5 ovl5 ol4 ovl4 ol3 ovl3 ol2 ovl2 ol1 ovl1 od13 (uvf) = under-voltage flag on v bat od12 (otw) = over-temperature prewarning flag od11 (ots) = over-temperature flag for all outputs od10 (nm) = normal mode od9, od7, od5, od3, od1 (ol5, ol4, ol3, ol2, ol1) = open load flag at outputs 5 through 1, respectively. od8, od6, od4, od2, od0 (ovl5, ovl4, ovl3, ovl2, ovl1) = overload flag for outputs 5 through 1, respectively.this corresponds to ochi or oclo faults. note a logic [1] at bits od9:od0 i ndicates a fault. if there is no f ault, bits od9:od0 are logic [0]. ovl=ochi1+ochi2+oclo table 13. overload status od15 od14 od13 od12 od11 od10 od9 od8 od7 od6 od5 od4 od3 od2 od1 od0 0 1 uvf otw ots nm oc5 ots5 oc4 ots4 oc3 ots3 oc2 ots2 oc1 ots1 od13 (uvf) = under-voltage flag on v bat od12 (otw) = over-temperature prewarning flag od11 (ots) = over-temperature flag for all outputs od10 (nm) = normal mode od9, od7, od5, od3, od1 (oc5, oc4, oc3, oc2, oc1) = high over-current shutdown flag for outputs 5 through 1, respectively od8, od6, od4, od2, od0 (ots 5, ots4, ots3, ots2, ots1) = over-temperature flag for outputs 5 through 1, respectively note a logic [1] at bits od9:od0 indicates a fault. if there is no fault, bits od9:od0 are logic [0]. oc=ochi1+ochi2 table 14. device status od15 od14 od13 od12 od11 od10 od9 od8 od7 od6 od5 od4 od3 od2 od1 od0 1 0 uvf otw ots nm 0 0v x x x rc fog pin flasher pin ign pin clock fail od13 (uvf) = under-voltage flag on v bat od12 (otw) = over-temperature prewarning flag od11 (ots) = over-temperature flag for all outputs od10 (nm) = normal mode od8 (overvoltage) = over-voltage flag on v bat in real time od4 (rc) = logic [0] indicates a front penta device. logic [1] indicates a rear penta device od3 (fog pin) = indicates the fog pin state od2 (flasher pin) = indicates the flasher pin state in real time od1 (ign pin) = indicates the ign pin state in real time od0 (clock fail) = logic [1], which indicates a clock failure. the content of this bit is reset by read operation. analog integrated circuit device data ? freescale semiconductor 29 06XS3517 functional device operation protection and diagnosis features previous address soa[1:0] = 11 if the previous two l sbs are 11, bits od15 : od0 reflect the status of the 06XS3517 ( table 14 ). protection and diagnosis features output protection features the 06XS3517 provides the fo llowing protection features: ? protection against transients on v bat supply line (per iso 7637) ? active clamp, including protection against negative transients on output line ? over-temperature ? severe and resistive over-current ? open load during on state these protections are provided for each output (out1:5). over-temperature detection the 06XS3517 provides over-temperature shutdown for each output (out1:out5 ). it can occur when the output pin is in the on or off state. an over-temperature fault condition results in turning off the corresponding output. the fault is latched and reported via spi. to delatch the fault and be able to turn on again the outputs, the failure condition must be removed (t< 175 c, typically) and: ? if the device was in normal mode, the output corresponding register (bit d7) must be rewritten. ? application of complete ochi window (ochi1+ochi2 during t2) depends on toggling or not toggling the d7 bit. ? if the device was in fail mode, the corresponding output is locked until restart of the device: wake-up from sleep mode or v batpor1 . the corresponding spi fault report (ots bit) is removed after a read operation. over-current detections the 06XS3517 provides a dynami c over-current shutdown protection (see figure 12 ) in order to protect the internal power transistors and the harness in the event of overload (fuse characteristic). figure 12. two-segment over-current window in normal mode ochi (i ochi1 and then i ochi2 ) is only activated after toggling d7 bit of the correspon ding control out registers in normal mode. during switch-on, a severe short-circuit condition at the output is repor ted as an ochi fault. in fail mode, the control of ochi windo w is provided by the toggles: ign_on, flasher_on, and fog_on. the current thresholds (i ochi1 , i ochi2 and i oclo ) and the time (t 1 and t 2 ) are fixed numbers for each channel. after t 2, the oclo current threshold is activated to protect in steady state. t 1 and t 2 times are compared to ?on? state duration (t on ) of the output. in case of the output is controlled in pwm mode during the inrush period, the t on corresponds to the sum of each ?on? state duration in order to only account for times the channel was actually in the on state. out2 is default loaded with the xenon profile. the use of h7 bulbs at this output requires spi programming ( xenon bit). in case of overload (ochi1 or ochi2 or oclo detection), the corresponding output is disabled immediately. the fault is table 15. output status od15 od14 od13 od12 od11 od10 od9 od8 od7 od6 od5 od4 od3 od2 od1 od0 1 0 uvf otw ots nm 0 0 0 0 0 out5 out4 out3 out2 out1 od13 (uvf) = under-voltage flag on v bat od12 (otw) = over-temperature prewarning flag od11 (ots) = over-temperature flag for all outputs od10 (nm) = normal mode od4 (out5) = logic [0] indicates the out5 voltage is lower than v out_th . logic [1] indicates the out5 voltage is higher than v out_th od3 (out4) = logic [0] indicates the out4 voltage is lower than v out_th . logic [1] indicates the out4 voltage is higher than v out_th od2 (out3) = logic [0] indicates the out3 voltage is lower than v out_th . logic [1] indicates the out3 voltage is higher than v out_th od1 (out2) = logic [0] indicates the out2 voltage is lower than v out_th . logic [1] indicates the out2 voltage is higher than v out_th od0 (out1) = logic [0] indicates the out5 voltage is lower than v out_th . logic [1] indicates the out1 voltage is higher than v out_th ochi1 ochi2 oclo output current time t1 t2 analog integrated circuit device data ? 30 freescale semiconductor 06XS3517 functional device operation protection and diagnosis features latched and the status is reported via spi. to delatch the fault, the failure condition must be removed and: for ochi1: ? if the device was in normal mode: the channel?s associated on/off bit (bit d7) must be rewritten d7=1. application of complete ochi window depends on toggling or not toggling d7 bit. ? if the device was in fail mode, the failure is locked until restart of the device: wake-up from sleep mode or v batpor1 . for ochi2 and oclo: ? if the device was in normal mode: channel?s associated on/off bit (bit d7) must be rewritten d7=1. application of complete ochi window depends on toggling or not toggling d7 bit. ? if the device was in fail mode, autorestart is activated. the device autorestart feature opens a fixed window width and restarts at a fixed period wi th ochi1 window. autorestart feature resets ochi2 or oc lo fault after corresponding autorestart period. the spi fault reports are removed together after a read operation: - oc bit=(ochi1) or (ochi2) fault - ovl bit=(ochi1) or (ochi2) or (oclo) fault over-voltage detection and active clamp the 06XS3517 possesses an active gate clamp circuit in order to limit the maximum drain to source voltage. in case of overload on an ou tput the corresponding switch (out[1 to 5]) is turned off which leads to high-voltage at vbat with an inductive vbat line. the maximum vbat voltage is limited at v batclamp by automatically turning on the channel. in case of open load condition, the positive transient pulses (iso 7637 pulse 2 and inductive battery line) shall also be handled by the application. figures 13 and 14 describe the faults management in normal mode and fail mode. figure 13. faults management in normal mode (for out[1:5] only) off ochi1 ochi2 oclo (ochi2=1) or (ot=1) or (uv=1) or (d7=0) (ochi1=1) or (ot=1) or (uv=1) or (d7=0) d7=0 then 1 without fault and (no_ochi=0) (rewrite d7=1) and (t on analog integrated circuit device data ? 32 freescale semiconductor 06XS3517 functional device operation protection and diagnosis features board temperature feedback the 06XS3517 provides a voltage proportional to the temperature on the gnd flag, often representative for the temperature of the underlayin g pcb land. this voltage is available at the csns output pin when the associated ux[2,0] bits are set to ?111?. figure 15 shows the output voltage over temperature. . figure 15. temperature sensing voltage the board temperature feedback is not active in fail mode. with a calibration strategy, the temperature monitoring precision can be improved. so , one calibration point at 25 c allows removing part to part contribution, as presented in figure 16 . figure 16. analog temperature precision with calibration strategy output voltage status the 06XS3517 provides the st ate of out1:out5 outputs in real time through spi. the out bit is set to logic [1] when the corresponding output voltage is higher or equal then half of the supply voltage. this bit allows synchronizing current sense and diagnosin g short-circuit be tween out and vbat terminals. temperature prewarning the 06XS3517 provides a temperature prewarning reported via the spi (otw bit) in normal mode. the information is latched. to de latch, a read spi command is needed. in case of a power on reset, the fault will be reset. external pin status the 06XS3517 provides the st atus of the flasher, fog, and ign pins via the spi in real time and in normal mode. failure handling strategy a highly sophisticated fault handling strategy allows guaranteeing the various lighting functions even in case of failures inside the component or the light module. components are protected against: ? reverse polarity ? loss of supply lines ? fatal mistreatment of logic i/o pins reverse polarity protection on vbat in case of a permanently reverse voltage operation, the channels are turned on (r sd ohm) in order to prevent thermal overloads. no pr otections are available. an external diode on vcc is nec essary in order to protect the 06XS3517 in cases from reverse polarity. in case of negative transients on the v bat line (per iso 7637), the v cc supplied functions are still available operating, while t he vbat line is negativ e. without loads on out1:5 pin, an external clamp between v bat and gnd is mandatory to avoid exceeding maximum ratings. the maximum external clamp voltage shall be between the reverse battery condition and -20 v. therefore, the device is protec ted against latch-up with or without load on out outputs. loss of supply lines the 06XS3517 is protected aga inst the loss of any supply line. the detection of the supply line failure is provided inside the device itself. loss of vbat during an under-voltage of v bat (v batpor1 < v bat < v batuv ), the outputs [1-5] are switched off immediately. no current path from vbat to vcc exists. the external mosfet (out6) can be controlled in normal mode by the spi if vcc is above v ccuv . the fault is reported to the uvf bit (od13). to delatch the fault, the under-voltage condition should be removed and: ? to turn-on the output, the corresponding d7 bit must be rewritten to logic [1] in no rmal mode. application of the ochi window depends on toggling or not toggling the d7 bit. ? if the device was in fail mode, the fault will be delatched by the autorestart feature periodically. 0 0.5 1 1.5 2 2.5 -40 -20 0 20 40 60 80 100 120 140 160 180 board tem perature (c) csns feedback (v) typ min max 0 0.5 1 1.5 2 2.5 -40 -20 0 20 40 60 80 100 120 140 160 180 board temperature (c) csns feedback (v) typ min ma x analog integrated circuit device data ? freescale semiconductor 33 06XS3517 functional device operation protection and diagnosis features in case of v bat < v batpor1 (power off mode), the behavior depends on v cc : ? all latched faults are reset if vcc < v ccuv , ? all latched faults are maintained under v cc in nominal conditions. in case v bat is disconnected, out[1:5] outputs are off. out6 out put state depends on the previous spi configuration. the spi configuration, reporting, and daisy-chain features are provided for rst is set to logic [1]. the spi pull-up and pull-down current resistors are available. this fault condition can be diagnosed with uvf fault in od13 reporting bit. the previous device configuration is maintained. no current is conducted from v cc to v bat . loss of v cc (digital logic supply line) during loss of v cc (v cc < v ccuv ) and with wake=1, the 06XS3517 is switched automatically into fail mode. the external smart mosfet is tu rned off. all spi registers are reset and must be reprogrammed when v cc goes above v ccuv . the device will transit in off mode if v bat < v batpor2 . loss of v cc and vbat if the external v bat and v cc supplies are disconnected (or not within specification: (v cc and v bat ) < v batpor1 ), all spi register contents are reset with default values corresponding to all spi bits are set to logic [0] and all latched faults are also reset. loss of ground (gnd) during loss of ground, the 06XS3517 cannot drive the loads (the outputs (1:5) are switched off), but is not destroyed by the operating condition. current limit resistors in the digital input lines protect the digital supply against excessive current (1.0 kohm typical). the state of the external smart power switch controlled by fetout is not guaranteed, and the st ate of external smart mos is defined with an external termination resistor. fatal mistreatment of logic i / o pins the digital i / os are protected agains t fatal mistreatment by signal plausibility check according to table 16 . in case the limp input is set to logic [1] for a delay longer than 10 ms typical, the 06XS3517 is switched into fail mode. in case of a (pwm) clock failure, no pwm feature is provided and the bit d7 defines the outputs state. in case of spi failure, the 06XS3517 is switched into fail mode (see figure 17 ) figure 17. watchdog window table 16. logic i / o plausibility check input / output signal check strategy limp debounce for 10 ms (pwm) clock frequency range (bandpass filter) spi (mosi, sclk, cs) wd, d10 bit internal toggle wd bit d10 75 ms window watchdog 0 1 0 timeout fail mode activation 75 ms window watchdog d10 is toggled after the window watchdog analog integrated circuit device data ? 34 freescale semiconductor 06XS3517 typical applications typical applications figure 18 gives the architecture of a vehicle lighting system, including fog lights, battery redundancy concept, light substitution mode, and fail mode. figure 18. 06XS3517 typical application emc performances the 06XS3517 will be compliant to cispr25 class5 in the standby mode with 22 nf decoupling capacitor on out[1:5]. vcc vbat mosi, miso, sclk vcc vbat cs clock rst ign csns limp vcc vbat vcc vbat cs clock rst ign limp cornerlight switch (front right) cornerlight switch (front left) cornerlight switch (rear right) cornerlight switch (rear left) v cc (5.0v) (5.0v) wd microcontroller watchdog v bat ignition stop light v bat rear fo g l ig h t rear drive light l ic e nse l ig ht stop light flasher ta il light re ar fo g l ig h t rear dr iv e ligh t l ic ense light s top ligh t flash e r ta i l l ig ht spa r e f o g light hig h bea m l o w b e a m fla s her par kin g l igh t spare fog ligh t h ig h beam low be am flash e r p a r k in g lig h t csns flasher flasher stop stop cs clock rst ign csns cs clock rst ign csns limp flasher flasher limp 100nf cp cp 100nf 100nf cp cp 100nf flasher 06XS3517 06XS3517 35xs3500 35xs3500 fog fog analog integrated circuit device data ? freescale semiconductor 35 06XS3517 packaging packaging dimensions packaging packaging dimensions for the most current pa ckage revision, visit www.freescale.com and perform a keyword search using the ?98a? listed below. fk suffix 24-pin pqfn 98art10511d issue 0 analog integrated circuit device data ? 36 freescale semiconductor 06XS3517 packaging packaging dimensions fk suffix 24-pin pqfn 98art10511d issue 0 analog integrated circuit device data ? freescale semiconductor 37 06XS3517 packaging packaging dimensions fk suffix 24-pin pqfn 98art10511d issue 0 analog integrated circuit device data ? 38 freescale semiconductor 06XS3517 packaging packaging dimensions fk suffix 24-pin pqfn 98art10511d issue 0 analog integrated circuit device data ? freescale semiconductor 39 06XS3517 packaging packaging dimensions analog integrated circuit device data ? 40 freescale semiconductor 06XS3517 revision history revision history revision date description of changes 1.0 2/2012 ? initial release 2.0 2/2012 ? corrected ordering information from mc06XS3517fk to mc06XS3517afk ? updated 98a package drawing how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road ? tempe, arizona 85284 ? 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. ? headquarters ? arco tower 15f ? 1-8-1, shimo-meguro, meguro-ku, ? tokyo 153-0064 ? japan ? 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. ? exchange building 23f ? no. 118 jianguo road ? chaoyang district ? beijing 100022 ? china ? +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com freescale and the freescale logo are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. qorivva, s12 magniv, smartmos and xtrinsic are trademarks of freescale semiconductor, inc. arm is the registered trademark of arm limited. the power architecture and power.org word marks and the power and power.org logos and related marks are trademarks and service marks licensed by power.org. all other product or service names are the property of their respective owners. ?2011 freescale semiconductor, inc. mc06XS3517 rev. 2.0 2/2012 information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further to products herein. freescale semiconductor makes no warranty, representation or regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, be validated for each customer application by technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other applicatio n in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purcha se or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. |
Price & Availability of 06XS3517
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |