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1 of 44 february 25, 2004 ? 20 03 integrated device techno logy, in c. dsc 6210 idt an d the idt lo go a re re giste re d trad emarks of in teg ra te d device tech no logy, in c. device overview device overview device overview device overview the RC32365 device is a member of the idt? i nt erprise? family of integrated communications processors. this device is designed to address a range of communications applications that require the effi- cient processing of ipsec algorithms. these applications include gate- ways, wire less acce ss p o in ts, an d virt ua l privat e ne twork (v pn) equipment. the key to the RC32365?s efficient processing of ipsec algorithms is a highly progammable security engine which off-loads the cpu core of encryption/decryption, hashing, and padding tasks. f f f features li st eatures list eatures list eatures list rc32300 32-bit cpu core ? 32-bit mips instruction set ? supports big or little endian operation ? mmu ?16-entry tlb ? supports variable page sizes and enhanced write algo- rit hm ? supports variable number of locked entries ? 8kb instruction cache ? 2-way set associative ? lru re pla ceme nt alg orith m ? 4 word line size ? su b-b lock orde ring ? wo rd pa rity ? per line cache locking ? 2kb data cache ? 2-way set associative ? lru re pla ceme nt alg orith m ? 4 word line size ? su b-b lock orde ring ? byt e pa rity ? per line cache locking ? can be programmed on a page basis to implement write- through no write allocate, write-through write allocate, or write-back algorithms ? enhanced ejtag and jtag interfaces ? co mpa tible with ie ee st d. 114 9.1 -19 90 security engine ? dedicated dma channels for high speed data transfers to and from the security engine ? on-chip memory for storage of two security contexts ? supports ecb and cbc modes for the following symmetric encryption algorithms: des, t riple des (both two key (k1=k3) and three key (k1!=k3) modes), aes-128 with 128-bit blocks, aes-192 with 128-bit blocks ? hardware support for encryption pad generation and checking using one of seven popular padding algorithms: supports pad algorithm required by ipsec esp ? supports md5 and sha-1 one-way hash functions ? pro gra mma ble t ru n catio n le ng th o f co mp ut ed ha sh a nd hma c on a security context basis ? supports concurrent hash and encryption operations b b b block diagram lock di agram lock di agram lock di agram figure 1 RC32365 internal block diagram ejtag mmu d. cache i . cache 32-bi t mips cpu core jtag in terrupt cont rolle r 3 co unte r timer s bus/system dma cont roll er arbiter sdram & device uart (16550) gpio interface pci master/ target memory & pe ri pheral bus serial chan nel gpio pin s pci bus con trol ler spi sp i b us mii mii int egrit y moni tor ipbus tm interface pci arbiter (host mode) . . s ecurity functions security context storage rng encryption unit un it hash 10/ 100 2 ethe rnet int erf aces controllers includi ng pc mci a support (i ncludi ng pcmci a) RC32365 idt tm interprise tm integrated communications processor
2 of 44 february 25, 2004 RC32365 ? optimized for ipsec ah, esp, and ah+esp (single mac) tu nn el a nd tran spo rt mod e p roce ssing : init ia lizatio n ve cto r (iv ) inse rtion an d ex tract io n, hma c ch ec kin g , ah mu ta ble field proces sing for both ipv4 and ipv6 packets, ipsec pad gener- ation and checking random number generator ? true hardware random number generator suitable for security applications: may be used to generate symmetric and public keys, initialization vectors, and nonces ? dedicated dma engine for transferring random numbers to memory ? ge ne rat es ra nd om nu mbe rs at a bit ra te e qu al to ipb us clock frequency divided by 32 ? provides 4 word (16 byte) fifo to queue random numbers ? ran do mne ss t este r co ntin ua lly verifie s pro pe r o p erat ion of random number generator using a randomness test defined in fips 140-2 pci interface ? 32-bit pci revision 2.2 compliant ? supports host or satellite operation in both master and target modes ? pci clock : supports frequencies from 16 mhz to 66 mhz, pci clock may be asynchronous to master clock (clk) ? pci a rbite r in host mo de : su pp ort s 3 ex tern al mast ers, f ixe d prio rity or ro un d ro bin a rb itrat io n ?i 2 o ?like? pci messaging unit two ethernet interfaces ? 10 and 100 mb/s iso/iec 8802-3:1996 compliant ? two ieee 802.3u compatible media independent interfaces (mii) with serial management interface ? mii supports ieee 802.3u auto-negotiation speed selection ? supports 64 entry hash table based multicast address filtering ? 512 byte transmit and receive fifos ? supports flow control functions outlined in ieee std. 802.3x- 1997 sdram controller ? supports up to 512 mb of memory ? 2 chip selects (each supports 2 or 4 banks internal sdram banks) ? 32-bit data width, supports 8/16/32-bit width devices ? supports 16mb, 64mb, 128mb, and 256mb, and 512mb devices ? automatic refresh generation memory and peripheral device controller ? pro vide s ?glu ele ss? inte rfac e t o st an da rd s ram, fla sh , rom, du a l-p ort me mory, a nd pe riph era l de vices ? provides ?glueless? interface to many 16-bit pcmcia devices ? demu ltiple xed ad dre ss an d d a ta b use s: 3 2-b it da ta bu s, 2 6-bit address bus, 6 chip selects, control for external data bus buffers ? support s 8-bit, 16-bit, and 32-bit width devices: automatic byte ga th erin g a nd sc att ering ? flexib le prot oco l co nf ig u ra tio n pa ra met ers: pro gramma ble number of wait states (0 to 63), programmable postread/post- writ e de lay (0 to 3 1 ), su pp orts e xte rn a l wait st ate ge ne ra tio n, su pp orts int el a n d mo to ro la style pe rip he rals ? write protect capability per chip select ? p ro gra mma ble b u s t ra nsa ctio n timer ge ne rat es warm re set wh en co un te r exp ire s ? s up po rt s u p to 64 mb o f me mory p er c hip sele ct dma controller ? 9 dma channels: two channels for each of the two ethernet int erfa ce s (t ra n smit /rece ive), t wo ch an ne ls fo r pci (p ci to memory and memory to pci), two c hannels for security engine (input/output), one channel for the hardware random number generator ? provides flexible descriptor based operation ? supports unaligned transfers (i.e., source or destination a dd re ss may b e on an y byte bo un da ry) with arbitra ry b yte length general purpose peripherals ? serial port compatible with 16550 universal asynchronous receiver transmitter (uart) ? three general purpose 32-bit counter/timers ? interrupt controller ? s erial p eriph e ra l in te rf ace (sp i) su pp ortin g ho st mo de ? 1 6 ge ne ral p u rp ose i /o (gpi o) p ins which ca n be c on figu red as interrupt sources sy stem fe ature s ? jta g int erfa ce (i ee e s td . 11 49 .1 co mp at ible) ? 256 pin cabga package ? 2.5v core supply and 3.3v i/o supply c c c cpu execution core pu execution core pu execution core pu execution core the rc32 36 5 is bu ilt arou nd th e rc32 30 0 3 2-b it high pe rforma nce microprocessor core. the rc32300 implements the enhanced mips-ii isa and helps meet the real-time goals and maximize throughput of communications and consumer systems by prov iding capab ilities such as a prefetch instruction, multiple dsp instructions, and cache lock ing. the instruction set is largely compatible with the mips32 instruction set, allowing the customer to select from a broad range of software and development tools. cache locking guarantees real-time performance by holding critical code and parameters in the cache for immediate avail- ability. the microprocessor also implements an on-chip mmu with a tlb, making the it fully compliant with the requirements of real time operating systems. se cu r ity en gi ne se cu r ity en gi ne se cu r ity en gi ne se cu r ity en gi ne the RC32365 incorporates an on-chip security engine that has been designed to accelerate ipsec performance and minimize the amount of performance required by the cpu to process secure packet traffic. the engine includes hardware support for the des, 3des, and aes encryp- tion algorithms and the md5 and sha1 hash functions. the engine also supports hardware-assisted packet processing for the various modes of ipsec, including ah, esp, and ah+esp tunnel and transport modes. two dedicated dma channels are used to transfer data to and from the security engine, allowing the cpu to work on other tasks during this time.
3 of 44 february 25, 2004 RC32365 pci interface pci interface pci interface pci interface the pci interface on the RC32365 is compatible with version 2.2 of the pci specification. an on-chip arbiter supports up to three external bus masters, supporting both fixed priority and rotating priority arbitra- tion schemes. the RC32365 can support both satellite and host pci configurations, enabling it to act as a slave controller for a pci add-in card application, or as the primary pci controller in the system. the pci interface can be operated synchronously or asynchronously to the other i/o interfaces on the RC32365 device. pcmcia interface pcmcia interface pcmcia interface pcmcia interface the RC32365 provides a "glueless" connection to a single pcmcia i/o device via the memory and peripheral device controller. the pcmcia interfac e allows the RC32365 to connec t to various t ypes of i/o peripherals including fax modems, storage devices, and wireless lan chip set s. th e rc32 36 5 imp lemen ta tion pro vide s a ma ximu m throughput of 160 mbps through the 16-bit wide interface as specified by the pcmcia 2.1 standard. ethernet interface ethernet interface ethernet interface ethernet interface the RC32365 has two ethernet channels supporting 10mbps and 100mbps speeds and provides a standard media independent interface (mi i) of f-chip , a llo wing a wide ra ng e of ext erna l d evice s t o b e co nn ect ed efficiently. m m m memory and i emory and i emory and i emory and i / / / /o controller o controller o controller o controller the RC32365 incorporates a flexible memory and peripheral device controller providing direct support for sdram, flash rom, sram, pcmcia , an d ot he r i/ o de vices. i t c an in terfa ce dire ctly to 8 -bit bo ot rom for a v ery low cost system implementation. it also offers v arious trad e-o ffs in c ost / pe rf orman ce for th e ma in memo ry arch it ect ure. the timers implemented on the RC32365 satisfy the requirements of most real time operating systems. dma controller dma controller dma controller dma controller the dma controller off-loads the cpu core from moving data among the on-chip interfaces, external peripherals, and memory. the dma controller supports scatter / gather dma with no alignment restrictions, appropriate for communications and graphics systems. e e e enhanced jtag interface nhanced jtag interface nhanced jtag interface nhanced jtag interface for system debugging, the rc32300 cpu core inc ludes an enhanced jtag (ejtag) interface which operates in run-time mode. t t t thermal considerations hermal considerations hermal considerations hermal considerations the RC32365 is guaranteed in a ambient temperature range of 0 to +70 c fo r co mme rcia l te mpe ratu re de vices an d - 40 to +85 for indus- trial t empe rat ure de vices. r r r revision histor evision histor evision histor evision history y y y march 17, 2003 : initial publication. may 15, 2003 : removed ?write protect capability? from features of the sdram controller. jul y 9, 20 0 3 : in table 6, changed values for rstn (output). changed values in tables 7, 8, 9, 10, and 17. oc tobe r 3 , 20 03 : a dd ed 18 0 mhz sp ee d g rad e. ch an g ed min values in table 7 from 1.8 to 1.2 for all signals except sdclkinp and sdckenp. changed min values for tdo 10b and 10c in table 10 for pciben, et c. and pcigntn/pcireqn from 2. 0 t o 1.5. february 25, 2004 : deleted reference to rngclk in table 1 (gpio[6]) and table 22.
4 of 44 february 25, 2004 RC32365 p p p pin description table in description table in description table in description table the following table lists the functions of the pins provided on the RC32365. some of the functions listed may be multiplexed on to the same pin (indicated as alternate functions). to define the active polarity of a signal, a suffix will be used. signals ending with an ?n? should be interpreted as being act ive, or a sserte d , wh en at a logic zero (low) level. all other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level. signal type name/description memory and peripheral bus bdirn o extern al bu ffe r d irectio n. mem ory and peripheral b us external dat a bus buf fer direction con trol. if the rc3 2365 memory and pe ripheral bus is connected to the a side of a transceiver such as an idt74fct245, then this p in ma y be directly connected to the d irect ion control (e.g., bdir) pin of the transceiver. boen[1:0] o external buffer enable. the se signals p rovide output enab le control for external b uffers on the memory a nd peripheral data bus. bwen[3:0] o byte write enables . these sig nals are memory a nd peripheral bus byte write enab le signals. bwen[0] corresponds to byte lane mdata[7:0] bwen[1] corresponds to byte lane mdata[15:8] bwen[2] corresponds to byte lane mdata[23:16] bwen[3] corresponds to byte lane mdata[31:24] csn[5: 0] o chip selects. these signals are used t o select an external device on the me mory and periph eral bus. maddr[21:0] o address bus. 22 -bit memory a nd peripheral bus address bus. maddr[25:22] are available as gpio[ 5:2] alternate functions. mdata[31:0] i/o data bus. 32-b it me mory and peripheral data b us. during a cold reset, b its 0 through 16 of this data bus function as in puts t hat are used to loa d the boot configuratio n vector. oen o output enable. this signal is asserted wh en data should be driven by an e xternal device on the memory a nd peripheral bus. rwn o read write. this sign al indicat es whether the transaction on the memo ry and peripheral bus is a read transaction or a write transaction. a high level indica tes a read from an e xternal device. a low le vel indicates a write to an external device. waitackn i wait or transfer acknowledge. when configure d as wait, this signal is asserted during a mem- ory and pe riphera l bus transaction to e xtend the bus cycle. when configured a s a t ransfer acknowled ge, this signal is asserted du ring a transa ction to signal the completion of the transa c- tio n. rasn o sdra m row addres s strobe. row a ddress strobe asse rted durin g memory and peripheral bus sdram transactions. casn o sdra m column a ddre ss strobe. colum n addre ss strobe asserted during me mory and pe riph- eral bus sdram transactions. sdcsn[1:0] o sdra m chip selects. these signals are used to select sdram device(s) o n the memo ry and peripheral bus. sdwen o sdram write enable. this signal is asserted during memo ry and periph eral bus sdram write transactions. sdclkout o sdra m clock output. this clock is used for all sdram memory an d peripheral bu s ope rations. sdclkin p i sdra m clock input. this clock input is typically a delayed version of sdclkout. data from the sdrams is sampled using this clock. tabl e 1 pin description (pa rt 1 of 6)
5 of 44 february 25, 2004 RC32365 ge neral purpose i/o gpio[0] i/o ge neral purpose i/o. this pin can b e co nfigu red as a gene ral purp ose i /o pin. alternate fun ction pin name: u0sout alternate fun ction: uart channel 0 serial output . gpio[1] i/o ge neral purpose i/o. this pin can b e co nfigu red as a gene ral purp ose i /o pin. alternate fun ction pin name: u0sinp alternate fun ction: uart channel 0 serial input. gpio[2] i/o ge neral purpose i/o. this pin can b e co nfigu red as a gene ral purp ose i /o pin. alternate fun ction pin name: maddr[22] alternate fun ction: mem ory and periph eral bus address bit 22 (output). gpio[3] i/o ge neral purpose i/o. this pin can b e co nfigu red as a gene ral purp ose i /o pin. alternate fun ction pin name: maddr[23] alternate fun ction: mem ory and periph eral bus address bit 23 (output). gpio[4] i/o ge neral purpose i/o. this pin can b e co nfigu red as a gene ral purp ose i /o pin. alternate fun ction pin name: maddr[24] alternate fun ction: mem ory and periph eral bus address bit 24 (output). gpio[5] i/o ge neral purpose i/o. this pin can b e co nfigu red as a gene ral purp ose i /o pin. alternate fun ction pin name: maddr[25] alternate fun ction: mem ory and periph eral bus address bit 25 (output). gpio[6] i/o ge neral purpose i/o. this pin can b e co nfigu red as a gene ral purp ose i /o pin. the value of th is pin may be used as a coun ter tim er clock inpu t. gpio[7] i/o ge neral purpose i/o. this pin can b e co nfigu red as a gene ral purp ose i /o pin. alternate fun ction pin name: sdckenp alternate fun ction: sdram clock enable output the value of th is pin may be used as a coun ter tim er clock inpu t. gpio[8] i/o ge neral purpose i/o. this pin can b e co nfigu red as a gene ral purp ose i /o pin. alternate fun ction pin name: cen1 alternate fun ction: pcm cia chip e nable 1 (ce1 #) (output). gpio[9] i/o ge neral purpose i/o. this pin can b e co nfigu red as a gene ral purp ose i /o pin. alternate fun ction pin name: cen2 alternate fun ction: pcm cia chip e nable 2 (ce2 #) (output). gpio[10] i/o ge neral purpose i/o. this pin can b e co nfigu red as a gene ral purp ose i /o pin. alternate fun ction pin name: regn alternate fun ction: pcm cia attribute m emory select (reg#) (outpu t). gpio[11] i/o ge neral purpose i/o. this pin can b e co nfigu red as a gene ral purp ose i /o pin. alternate fun ction pin name : iordn alternate fun ction: pcm cia io read (iord#) (ou tput). gpio[12] i/o ge neral purpose i/o. this pin can b e co nfigu red as a gene ral purp ose i /o pin. alternate fun ction pin name: iowrn alternate fun ction: pcm cia io write (iowr#) (output). gpio[13] i/o ge neral purpose i/o. this pin can b e co nfigu red as a gene ral purp ose i /o pin. alternate fun ction pin name: pcireqn[2] alternate fun ction: pci bus request 2 (output). gpio[14] i/o ge neral purpose i/o. this pin can b e co nfigu red as a gene ral purp ose i /o pin. alternate fun ction pin name: pcigntn[2] alternate fun ction: pci bus g rant 2 (output). signal type name/description tabl e 1 pin description (pa rt 2 of 6)
6 of 44 february 25, 2004 RC32365 gpio[15] i/o ge neral purpose i/o. this pin can b e co nfigu red as a gene ral purp ose i /o pin. alternate fun ction pin name: pcimuintn alternate fun ction: pci messaging unit interrupt outp ut. serial interface sck i/o serial clock . this sign al is use d as the serial spi clock out put. this pin may be used as a bit inp ut/output po rt. sdi i/o serial data input . this signa l is use d to shift in serial spi data. this pin may be used as a bit inp ut/output po rt. sdo i/o serial data output . th is signa l is u sed t o shift out serial spi data. this pin may be used as a bit inp ut/output po rt. pci bus pciad[31 :0] i/o pci multiplexed address/data bus . address is driven by a bus master du ring in itial pcifra- men assertion. da ta is then drive n by the bus master during writes or by the bus targe t during reads. pcicben[3:0] i/o pci multiplexed command/byte enable bus . pci command is drive n by the bus master d uring the initial pciframen assertion. byte enab le s are driven by the bus master d uring subsequent data phase(s). pciclk i pci clock . clock used for a ll pci bus transa ctions. pcidevseln i/o pci de vice select . this signal is driven b y a b us ta rget to indicate that the target h as de code d the address as one o f its own addre ss space s. pciframen i/o pci frame . driven by a bus mast er. asse rtion indicates the be ginning of a bus transaction. negation indica tes th e last dat a . pcigntn[1:0] i/o pci bus grant . in pci host mode with internal a rbite r: the a ssertion o f these signals ind icates to the ag ent that the internal rc32 365 arb iter has grant ed the agent access to the pci bu s. in pci host mode with exte rnal arbiter: pcigntn[0]: asserted by an exte rnal arb iter to indicate to the RC32365 that a ccess to the pci bus has been granted. pcigntn[1]: unu sed a nd driven high. in pci satell ite mode: pcigntn[0]: this signal is asserted by an externa l arbite r to indicate to th e rc323 65 that access to the pci bus has b een gra nted. pcigntn[1]: t his signal takes on the alternate function of pcieecs a nd is used as a pci serial eeprom chip select. pciirdyn i/o pci initiator re ady . drive n by the bus master to indicate that the curren t data can complete. pcilockn i/o pci lock . this signal is asse rted by an e xternal bus master to indicate that an e xclusive opera- tio n is occurring. pcipar i/o pci parity . even parity of the pciad[31:0] bus. driven b y the bus m aste r during address and write data phases. driven by the bus target during th e read data phases. pciperrn i/o pci parity error . this signal is asserte d by the receiving bu s age nt 2 clocks a fter the data is receive d if a parity error is detected. signal type name/description tabl e 1 pin description (pa rt 3 of 6)
7 of 44 february 25, 2004 RC32365 pcireqn[ 1:0] i/o pci bus reque st. in pci host mode with internal a rbite r: these signals are inputs whose asse rtion indicates to the internal rc323 65 arbiter that an age nt desires ownership of th e pci bus. in pci host mode with exte rnal arbiter: pcireqn[0] : asserted by the RC32365 t o request own ership of the pci bus. pcireqn[1] : unused and driven high. in pci satell ite mode: pcireqn[0] : this sig nal is asserted by the RC32365 t o request ownership of the pci bus. pcireqn[1] : function chang es to pciidsel and is used as a chip select during configuration read and write t ransaction s. pcirstn i/o pci re set . in h ost m ode, this signal is asserted b y the rc323 65 to generate a pci reset. in sat- ellite mode , a ssertion o f this sig nal initiates a warm reset. pciserrn i/o pci system error . this signal is driven by an ag ent to indicate a n addre ss parity error, data par- ity error d uring a sp ecial cycle comman d, or any other syst em error. req uires a n e xternal pull-up. pcistopn i/o pci stop . driven by the bus target to termin ate the current bus transa ction. for example, to indi- ca te a retry. pcitrdyn i/o pci target ready . driven by the bu s target to indicate that the current d ata can co mple te. ethernet interface mii0cl i ethernet 0 mii collision detected. this signal is asserted by the e thernet phy when a collision is detected. mii0crs i ethernet 0 mii carrier sense. this signal is asserted by the etherne t phy when either the tra ns- mit or rece ive medium is not idle. mii0rxclk i ethernet 0 mii re ceive clock. this clo ck is a continuous clock that p rovide s a timing referen ce for th e reception of dat a. mii0rxd[3:0] i ethernet 0 mii re ceive data. this nibble wide data bu s contains the data received by the ether- net phy. mii0rxdv i ethernet 0 mii re ceive data valid. the assertion o f this signal indicates that valid receive data is in the mii receive dat a bus. mii0rxer i ethernet 0 mii re ceive error. the assertion of this signal indicates that an error was de tecte d so mewhere in the ethernet frame currently being sent in the m ii receive d ata bus. mii0txclk i ethernet 0 mii transmit clock. this clock is a co ntinu ous clock that provides a timing reference for th e transfer of tra nsmit data . mii0txd[3:0] o ethernet 0 mii tra nsmit data. this nibble wide data bus cont ains the da ta to be transmitte d. mii0txenp o ethernet 0 m ii transmit enable . the assertion of this signa l indicates that data is present on the mii for transmission. mii0txer o ethernet 0 mii tra nsmit coding error. when this signal is asserted together with miitxenp, the ethernet phy will transmit symbo ls which are not valid data o r delim iters. mii1cl i ethernet 1 mii collision detected. this signal is asserted by the e thernet phy when a collision is detected. mii1crs i ethernet 1 mii carrier sense. this signal is asserted by the etherne t phy when either the tra ns- mit or rece ive medium is not idle. mii1rxclk i ethernet 1 mii re ceive clock. this clo ck is a continuous clock that p rovide s a timing referen ce for th e reception of dat a. signal type name/description tabl e 1 pin description (pa rt 4 of 6)
8 of 44 february 25, 2004 RC32365 mii1rxd[3:0] i ethernet 1 mii re ceive data. this nibble wide data bu s contains the data received by the ether- net phy. mii1rxdv i ethernet 1 mii re ceive data valid. the assertion o f this signal indicates that valid receive data is in the mii receive dat a bus. mii1rxer i ethernet 1 mii re ceive error. the assertion of this signal indicates that an error was de tecte d so mewhere in the ethernet frame currently being sent in the m ii receive d ata bus. mii1txclk i ethernet 1 mii transmit clock. this clock is a co ntinu ous clock that provides a timing reference for th e transfer of tra nsmit data . mii1txd[3:0] o ethernet 1 mii tra nsmit data. this nibble wide data bus cont ains the da ta to be transmitte d. mii1txenp o ethernet 1 m ii transmit enable . the assertion of this signa l indicates that data is present on the mii for transmission. mii1txer o ethernet 1 mii tra nsmit coding error. when this signal is asserted together with miitxenp, the ethernet phy will transmit symbo ls which are not valid data o r delim iters. miimdc o mii management da ta cl ock. this signal is used as a timin g reference for transmission of data on the ma nagement interface. miimdio i/o mii man agem ent dat a. this bidirectional signal is used to transfer data be tween the station man- agement e ntity and t he ethernet phy. ejtag / jtag jt ag _tms i jtag m ode . the value on this signal controls the test mode select o f the boundary scan logic or jtag controller. when using the ejtag debug interface , this pin should be left disconnected (since t here is an internal pull-up) or driven h igh. ejtag_tms i ejtag mode . the value on th is signa l controls the test mo de se lect of the ejtag controller. when using th e jtag bo undary scan , t his pin shou ld be left disconne cted (since there is an inter- nal pull-up) or driven high. jt ag _tr st _n i jtag reset . this active low sign al asynchronously resets the bounda ry scan logic, jtag tap controller, and the ejtag debug tap controller. an e xternal pull-up on the b oard is recom- mended to meet the jtag specification in cases where the tester can access this signal. how- ever, for systems run ning in fun ctional mode, o ne of the following should occur: 1) actively drive this signal lo w with contro l logic 2) statically drive this signal low with an externa l pull-down on the bo ard 3) clock jtag_tck while holding ejtag_tms and/or jtag_tm s high. jt ag _tc k i jtag clock . this is an input test clo ck used to clock the shifting of data into or out of th e bound- ary sca n logic, jtag controller, or th e ejtag controller. jtag_ tck is inde pendent of t he sys- tem and th e processor clo ck with a nom inal 50% duty cycle. jt ag _td o o jtag data output . this is the serial data shifted out f rom the boundary scan logic, jtag con - troller, or the ejtag cont roller. when no data is be ing shifted out, this sign al is tri-stated. jt ag _td i i jtag data input . this is the serial data inp ut to the boundary scan logic, jtag contro ller, or the ejtag controller. signal type name/description tabl e 1 pin description (pa rt 5 of 6)
9 of 44 february 25, 2004 RC32365 p p p pin in in in characteristics characteristics characteristics characteristics miscellaneous clk i master cloc k. this is the ma ster clock inp ut. the processor fre quency is a multip le of this clock frequ ency. this clock is used a s the system clock for a ll memory and peripheral bus operations except those associa ted with sdram s. coldr stn i cold re set. the assertion of this signal initiates a cold reset. this causes the pro cessor state to be initialized, bo ot co nfigu ration to be loade d, and the internal pl l to lock onto t he master clock (c lk). rstn i/o reset. th e assertion of this bidirectional signal initiates a warm rese t. this signal is asserte d by the RC32365 d uring a warm re set. it can also be asserte d by a n external device to force the rc32 365 to take a warm reset exception. pin name type buffer i/o type inter nal resistor exter nal resistor 1 memory and peripheral bus bdirn o lvttl hig h drive boen[1:0] o lvttl high drive bwen[3:0] o lvttl high drive csn[5: 0] o lvttl hig h drive maddr [21:0] o lvttl hig h drive mdata[31:0] i/o lvttl hig h drive oen o lvttl hig h drive rwn o lvttl hig h drive waitackn i lvttl sti 2 pull-up rasn o lvttl high drive casn o lvttl high drive sdcsn [1:0] o lvttl hig h drive sdwen o lvttl hig h drive sdclkout o lvttl hig h drive sdclkinp i lvttl sti pull-up ge neral purpose i/o gpio[15:1 3] i/o pci pci gpio[1 2:0 ] i/o lvttl lo w drive pull-up serial interface sck i/o lvttl lo w drive pull-up pull-up on board sdi i/o lvttl lo w drive pull-up pull-up on board sdo i/o lvttl lo w drive pull-up pull-up on board pci bus interfa ce pciad[31 :0] i/o pci pci pcicben[3:0] i/o pci pci pciclk i pci pci pcidevseln i/o pci pci pull-up on board table 2 pin characte ris tics (part 1 of 2) signal type name/description tabl e 1 pin description (pa rt 6 of 6)
10 of 44 february 25, 2004 RC32365 pciframen i/o pci pci pull-up on board pcigntn[1:0] i/o pci pci pull-up on board pciirdyn i/o pci pci pull-up on board pcilockn i/o pci pci pcipar i/o pci pci pciperrn i/o pci pci pcireqn[ 1:0] i/o pci pci pull-up on board pcirstn i/o pci pci pu ll-do wn on boa rd pciserrn i/o pci open collector; pci pull-up on board pcistopn i/o pci pci pull-up on board pcitrdyn i/o pci pci pull-up on board ethernet interfaces mii0cl i lvttl sti pull-up mii0crs i lvttl sti pull-up mii0rxclk i lvttl sti pull-up mii0rxd[3:0] i lvttl sti pull-up mii0rxdv i lvttl sti pull-up mii0rxer i lvttl sti pull-up mii0txclk i lvttl sti pull-up mii0txd[3:0] o lvttl lo w drive mii0txenp o lvttl low drive mii0txer o lvttl lo w drive mii1cl i lvttl sti pull-up mii1crs i lvttl sti pull-up mii1rxclk i lvttl sti pull-up mii1rxd[3:0] i lvttl sti pull-up mii1rxdv i lvttl sti pull-up mii1rxer i lvttl sti pull-up mii1txclk i lvttl sti pull-up mii1txd[3:0] o lvttl lo w drive mii1txenp o lvttl low drive mii1txer o lvttl lo w drive miimdc o lvttl lo w drive miimdi o i/o lvttl lo w drive pull-up ejtag / jtag jtag_tms i lvttl sti pull-up see chapte rs 2 2 and 23 of the rc323 65 user reference manual ejtag_tms i lvttl sti pull-up jtag_trst_n i lvttl sti pull-up jtag_tck i lvttl sti pull-up jtag_tdo o lvttl low drive jtag_tdi i lvttl sti pull-up miscellaneous clk i lvttl sti coldrstn i lvttl sti rstn i/o lvttl low drive / sti pull-up pull-up on board 1. external pull-up required in most system applications. some applications may require additional pull-ups not identified in this table. 2. schmidt trigger input (s ti). pin name type buffer i/o type inter nal resistor exter nal resistor 1 table 2 pin characte ris tics (part 2 of 2)
11 of 44 february 25, 2004 RC32365 boot configuration boot configuration boot configuration boot configuration ve ve ve vector ctor ctor ctor the boot configuration vector is read into the RC32365 during cold reset. the vector defines parameters in the RC32365 that are e sse ntia l to op er- ation when cold reset is complete. the encoding of boot configuration vector is described in table 3, and the vector input is illustrated in figure 4. signal name/description mdata[2:0] cpu clock multiplier . th is field specifies the value by which the pll mu ltiplies the m aster clock input (clk) to obtain the proce ssor clock frequency (pclk). 0x0 - multiply by 2 0x1 - 0x7 ? re served mdata[3] endian. this bit specifies the endianness. 0x0 - little endian 0x1 - big endian mdata[4] reserved. this pin may b e driven high or low during boot configuratio n and its state is recorded in the boot configuratio n vecto r (bcv) field of the bcv registe r. this re served bit m ay be used to pass b oot configu ration parameters to software. mdata[6:5] boot device width . this field specifies the width of the boot device (i.e., device 0). 0x0 - 8-bit boot device width 0x1 - 16-b it boo t device width 0x2 - 32-b it boo t device width 0x3 - reserved mdata[7] reset mode . this bit spe cifies th e leng th of time the rstn signal is driven. 0x0 - normal reset: rstn driven for minim um of 4096 clock cycles 0x1 - reserved mdata[8] disable watchdog timer . whe n this bit is set, the watch dog timer is disabled follo wing a cold reset. 0x0 - watchdog timer is enabled 0x1 - watchdog timer is disabled mdata[11:9] pci mode . this bit controls the operating mode of the pci b us interface. the initial value of the en bit in the pcic register is dete rmined by the pci mode. 0x0 - disa bled (en initial value is zero) 0x1 - pci satellite mod e with pci target not ready (en initial value is o ne) 0x2 - pci satellite mod e with suspen ded cpu execution (en initial value is one) 0x3 - pci host mode with external arbiter (en initial value is zero) 0x4 - pci host mode with int ernal arbiter using fixed priority arbitration algorithm ( en i nit ial v alue is z ero) 0x5 - pci host mode with int ernal arbiter using round robin arb itratio n alg orithm ( en i nit ial v alue is z ero) 0x6 - reser ved 0x7 - reser ved mdata[15:12] reserved . these pins may be driven high or low during bo ot con figuration and the ir sta te is recorded in the boot configuratio n vecto r (bcv) field of the bcv registe r. these reserved bits m ay be used to pass b oot configu ration parameters to software. table 3 boot configuration vector encoding
12 of 44 february 25, 2004 RC32365 l l l logic diagram ogic diagram ogic diagram ogic diagram the fo llowing l og ic diag ram s ho ws th e primary p in f un ctio ns of the rc3 23 65 . figure 1 RC32365 logic diagram miscellaneous si gn al s me mo ry and peripheral bus clk coldrstn rstn 4 miimdc miimdio mii0cl mii0crs mii0rxclk mii0rxd[3:0] mii0rxdv mii0rxer mii0txclk mii0txd[3:0] mii0txenp mii0txer mii1cl mii1crs mii1rxclk mii1rxd[3:0] mii1rxdv mii1rxer mii1txclk mii1txd[3:0] mii1txenp mii1txer bdirn boe n[1:0] bwen[ 3:0] csn[5:0] maddr[21:0] mdata[31:0] oen rwn waitackn gpio[15:0] sdo jtag_trst_n jtag_tck jtag_tdo jtag_tdi ej tag _tm s 4 4 4 16 32 22 6 4 ejtag / jtag si gn al s gen e ral pu rp os e i/o serial i/o ethernet rc3 23 65 vc ccore vcci/o vs s vc cp ll vs sp ll power/ground sdi sck jtag_tms rasn casn sdclkinp sdcsn[1:0] 2 sdwe n 2 sdclkout pciad[31:0] pcicben[3:0] pciclk p cidev se ln pciframen pcigntn[1:0] pciirdyn pcilockn pcipar pcipe rrn pcireqn[1:0] pcirstn pcise rrn pcis topn pcitrdyn 2 2 4 32 pci bus
13 of 44 february 25, 2004 RC32365 a a a ac timing c timing c timing c timing definition definition definition definitions s s s below are examples of the ac timing characteristics used throughout this document. figure 2 ac timing definitions waveform symbol definition tp er clock pe riod. tlow clock low. am ount of time the clock is low in o ne clock period. th igh clock high. amo unt of time the clock is h igh in one clock p eriod. trise rise time . low to h igh transition time. tf all fall tim e. high to low transition time. tjitter jitter. amount of time the refe rence clock (or signa l) edge can vary on either the risin g or falling edges. td o data o ut. amount of t ime a fter the reference clock edge that the output will b ecom e va lid. th e min imum time represents t he d ata outp ut hold. the maximum time represe nts th e earliest time the design er can use the dat a. tzd z state to data valid. amou nt of time after the re ference clo ck edge t hat the tri-sta ted output ta kes to become valid. td z data valid to z state. am ount of time after the referen ce clock edg e that the valid output takes to become tri-st ated. tsu input set-up. amount of time before th e reference clock edge that the in put must be valid. th ld input ho ld. amou nt of time after the re ference clock edge that the input must remain va lid. tp w pulse width . amount of time the input or outp ut is active fo r asynchronous signa ls. tslew sle w rate . the rise or fall rate for a signa l to g o from a high to lo w, or low to high. x(clock) timing valu e. this notation re presents a valu e of ?x? multiplied by the clock time perio d of the specified clock. using 5(clk) as an exam ple: x = 5 an d the oscillato r clo ck (clk) = 25mhz, then th e tim ing value is 2 00. tskew ske w. th e amount of time two sign al ed ges d eviate from one a nother. table 4 ac t imi ng defin it ion s tdz tzd tdo tpw tpw thld tsu tlow thigh thigh tper clock out put signal 1 out put signal 2 inpu t signal 1 signal 1 tjitter tr ise t fall tdo signal 2 signal 3 tskew
14 of 44 february 25, 2004 RC32365 clock parameters clock parameters clock parameters clock parameters the values given below are based on systems running at recommended s upply voltages and operating temperatures , as s hown in tabl es 14 and 15 . figure 3 clock parameters wave form parameter symbol reference edge 150mhz 180mhz units timing diag ram reference min m ax min m ax pclk 1 1. the cpu pipeline clock (pclk) speed is selected during cold reset by the boot configuration vector (see table 3). frequency n one 1 00 1 50 1 00 180 mhz see figure 3 clk 2,3 2. ethernet clock (miixrxclk and miixtxclk) frequency must be less than or equal to 1/2 clk frequency. 3. pci clock (pciclk) frequency must be less than or equal to two times clk. frequency n one 5 0 7 5 5 0 9 0 mhz tper_5a 13.3 20 11.1 20 ns thigh_5a , tlow_5a 40 60 40 60 % of tper_5a trise_5a , tfall_5a ?3.0?3.0ns tjitte r_5a ? 250 ? 250 ps table 5 rc3236 5 clock parameters tlow_ 5a thigh_5a tper _5a clk trise _5a tfall_5 a tjitter_5a tjitter_5a
15 of 44 february 25, 2004 RC32365 ac timing characteristics ac timing characteristics ac timing characteristics ac timing characteristics the v alues given below are based on systems running at recommended operating supply voltages and temperatures as shown in table s 14 and 15 . signal symbol reference edge 150mhz 180mhz unit conditions timing diagram reference min max min max reset and system coldrstn tpw_6a 1 1. the values for this symbol were determined by calculation, not by testing. none 110 ? 110 ? ms cold reset see figures 4 a nd 5 trise_6a ? 5.0 ? 5.0 ns cold reset rstn 2 (outp ut) 2. rstn is a bidirectional signal. it is treated as an asynchronous input. tdo_6b clk rising 2.0 9.0 2.0 9.0 ns cold reset rstn 2 (input) tpw_6c 1 none 2(clk) ? 2(clk) ?ns cold reset mdata[15:0] boot con figuration vector thld_6d coldrstn rising 3.0 ? 3.0 ? ns cold reset tdz_6d 1 coldr stn falling ? 2(clk) ? 2(clk) ns cold reset tdz_6d 1 rstn falling ? 2(clk) ? 2(clk) ns warm reset tzd_6d 1 rstn rising 3.0 ? 3.0 ?nswarm reset ta ble 6 reset and system ac timing characteristics
16 of 44 february 25, 2004 RC32365 figure 4 cold reset ac timing waveform figure 5 warm re set ac timing waveform boot vector sdclkout coldrstn rstn mdata[31:0] bdirn boen[1: 0] >= 100 ms >=10ms >= 4096 clk clock cycles >= 4096 clk clock cycles tpw_6a tdo_6b clk 1 ffff_ffff thl d_6d 1. co ldrstn a sse rted by extern al logi c. 2. rc 32365 asserts rstn, asserts boen[0] l ow, drives bdir n l ow, and tri-sta tes th e d ata bus in respon se . 3. external log ic be gins driving val id boot con fig uration vector on the data bu s, and th e r c32365 starts samplin g i t. 4. external log ic ne gates co ldrstn a nd tri-state s the boot con fi guration vecto r on mdata[15:0]. the boo t configuration vector mu st n ot be tri -stated before cold rstn is deas- serted. the rc32 365 stop s sampli ng the boo t configuration vector. 5. the rc323 65 starts dri vi ng the da ta bus, mdata[31:0], dea sserts bo en[0] high, and drives bd irn hi gh. 6. sysclk may be held constant after this point if hold sysclk constant is selected in the boot configuration vector. 7. rstn negated by the rc32 365. 8. cpu beg ins e xecuti ng by taking mips reset exception , and the rc3236 5 starts samplin g r stn as a warm reset inp ut. 2 34 56 7 8 trise_6a tdz_6d (r stn ignored d uring this p eriod to allow p ull-up to drive signa l h igh ) (rstn sampled) active d easserted active clk cold rst n rst n mdata[3 1:0] mem co ntro l sign als >= 4096 clk clock cycles > = 4 096 c lk clock cycles (rstn ig nored du ring t his p eriod t o allo w pu ll-up to drive signal high ) 1. w arm reset co ndition caused by either rstn asserted, write to reset re giste r, or b us transaction ti mer time-out. the rc3236 5 asserts r stn output lo w i n re sp onse. 2. the rc323 65 tri-states the data b us, mdata[31:0], a nd deasserts al l memory contro l si gnals, su ch as rasn, casn, rw n, oen, etc . 3. the rc323 65 deasserts rstn. 4. the rc323 65 starts dri vi ng the da ta bus, mdata[31:0], aga in, bu t does not sampl e the rstn in put. 5. cpu beg ins executi ng by taking a mips so ft rese t exception and also starts sampling the rstn inp ut aga in. ffff_ffff 12 34 5 tzd_6d tdz_6d (rstn sampled)
17 of 44 february 25, 2004 RC32365 signal symbol reference edge 150mhz 180mhz unit conditions timing diagram refer ence min max min max memory a nd pe riphe ra l bus - sdram access mdata[31:0] tsu _7a sdclkinp rising 1.0 ? 1.0 ? ns see figures 6 an d 7 th ld _7 a 1.7 ? 1.7 ? ns tdo_7a sdclkout rising 1.2 6.0 1.2 6.0 ns tdz_7a 1 1. the values for this symbol were determined by calculation, not by testing. 1.2 7.0 1.2 7.0 ns tzd_7a 1 1.2 8.0 1.2 8.0 ns maddr[20:2] tdo_7b sdclkout rising 1.2 6.0 1.2 6.0 ns rasn tdo_7c sdcl kout rising 1.2 6.0 1.2 6.0 ns casn tdo _ 7d sdcl kout rising 1.2 6.0 1.2 6.0 ns sdwen td o_ 7e sdcl kout rising 1.2 6.0 1.2 6.0 ns sdcsn[1:0] tdo _7f sdcl kout rising 1.2 6.0 1.2 6.0 ns bdir n tdo _ 7g sdcl kout rising 1.2 6.0 1.2 6.0 ns boen[1:0] tdo _ 7h sdcl kout rising 1.2 6.0 1.2 6.0 ns bwen[3:0 ] tdo_7i sdcl kout rising 1.2 6.0 1.2 6.0 ns sdc lkinp tdelay_ 7k sdcl kout rising 0.0 2.5 0.0 2.5 ns see figures 6 an d 8 sdckenp tdo_7l sdcl kout rising 2.0 6.0 2.0 6.0 ns ta ble 7 m emory and peripheral bus ac timing characteristics
18 of 44 february 25, 2004 RC32365 figure 6 memory and peripheral bus ac timing waveform - sdram read acce ss addr 1111 be' s 1111 nop read nop 11 chi p- sel 11 11 buffer enables 11 data tzd_7a tdz_7a tdo_7h tdo_7h tdo_7g tdo_7g tdo_7f tdo_7c, 7d, and 7e tdo_7i tdo_7b thld_7a tsu_7a clk sdclkout maddr[21:0] bwen[ 3: 0] cmd[2:0]* sdcsn[1: 0] bdirn boen[1: 0] mdat a[ 31: 0] sdclki np sdram cas latency tdel ay _7k * note: cmd[2:0] = { rasn, casn, sdwen} RC32365 samples read data
19 of 44 february 25, 2004 RC32365 figure 7 m emory and peripheral bus ac timing wa veform - sdram write acc ess addr 1111 be' s 1111 nop wri te nop 11 chip- sel 11 11 buf f enable 11 dat a tdo_7a tdo_7h tdo_7g tdo_7f tdo_7c, 7d, and 7e tdo_7i tdo_7b cl k s dcl kout maddr[21: 0] bwen[ 3: 0] cmd[ 2:0]* sdcsn[1: 0] bdi rn boen[1: 0] mda t a[ 3 1: 0] * note: cmd[ 2: 0] = { rasn, casn, sdwen} sdram samples wr i te data
20 of 44 february 25, 2004 RC32365 figure 8 sd clk out - sdclkin p relationshi p signal symbol refer ence edge 150mhz 180mhz unit conditions timing diagr am reference min max min max memory and peripheral bus 1 ? device access mdata[ 3 1:0] tsu_8 a clk rising 2.5 ? 2.5 ? ns see figures 9 and 10 th ld_ 8 a 1.0 ? 1.0 ? ns tdo_ 8a 2.0 6.5 2.0 6.5 ns tdz_8a 2 2.0 9.5 2.0 9.5 ns tzd_8a 2 2.0 10.5 2.0 10.5 ns maddr[21:0] tdo_8b clk rising 2.0 6.5 2.0 6.5 ns maddr[25:22] tdo_8c clk rising 3.0 7.5 3.0 7.5 ns csn[5:0] tdo_ 8d clk rising 2.0 6.5 2.0 6.5 ns rwn tdo_ 8e clk rising 2.0 6.5 2.0 6.5 ns oen tdo _8f clk rising 2.0 6.5 2.0 6.5 ns bwen[1:0] tdo_ 8g clk rising 2.0 6.5 2.0 6.5 ns bdirn tdo_ 8h clk rising 2.0 6.5 2.0 6.5 ns boen[ 1:0] tdo_8i clk rising 2.0 6.5 2.0 6.5 ns waitackn 3 tsu _8j clk rising 2.0 ? 2.0 ? ns thld _8j 0.5 ? 0.5 ? ns tpw_8j 2 non e 2(clk) ? 2(clk) ?ns table 8 memory and peripheral bus ac timing characteristics ? device access (part 1 of 2) RC32365 sdram sram, eprom, etc. external sdclkout sdclki np clk memory bus tdelay_7k rs tn col drstn vcc pull - up buffer
21 of 44 february 25, 2004 RC32365 figure 9 memory a nd peripheral bus ac timing waveform - device read access cen1 4 , cen2 4 tdo_8k clk rising 3.0 7.5 3.0 7.5 ns see figures 9 and 10 (cont.) regn 4 tdo_8l clk rising 3.0 7.5 3.0 7.5 ns iordn 4 tdo_ 8m clk rising 3.0 7.5 3.0 7.5 ns iowrn 4 tdo_ 8n clk rising 3.0 7.5 3.0 7.5 ns 1. the RC32365 provides bus turnaround cycles to prevent bus contention when going from a read to write and write to read. for exa mple, there are no cycles where an external device and the RC32365 are both driving. see chapter 6, device controller, in the RC32365 user reference manu al . 2. the values for this symbol were determined by calculation, not by testing. 3. waitackn must meet the setup and hold times if it is synchronous or the minimum pulse width if it is asynchronous. 4. cen1, cen2, regn, iordn, and iowrn are alternate functions of gpio[12:8]. signal symbol refer ence edge 150mhz 180mhz unit conditions timing diagr am reference min max min max table 8 memory and peripheral bus ac timing characteristics ? device access (part 2 of 2) addr[21:0] addr[25:22] 1111 dat a tdo_8i tdo_8i tdo_8h tdo_8h tzd_8a tdz_8a tdo_8f tdo_8f tdo_8d tdo_8d tdo_8c tdo_8b thld_8a tsu_8a clk maddr[21:0] maddr[25:22] rwn csn[5:0] bwen[3: 0] oen mdata[31:0] bdirn boen[1: 0] wai tackn RC32365 samples read data
22 of 44 february 25, 2004 RC32365 figure 10 memory ac and peripheral bus timing waveform - device write access addr[21:0] addr[25:22] 1111 byte enables 1111 dat a tdo_8i tdo_8a tdo_8g tdo_8d tdo_8e tdo_8c tdo_8b clk maddr[21:0] maddr[25:22] rw n csn[ 5:0] bwen[ 3: 0] oen mdata[ 31: 0] bdi rn boen[ 1: 0] wai tackn
23 of 44 february 25, 2004 RC32365 signal symbol refer ence edge 150mhz 180mhz unit conditions timing diagr am reference min max min max ethernet 1 1. there are two mii interfaces and the timing is the same for each. ?x? represents interface 0 or 1 (for example, miixrxclk can b e either mii0rxclk or mii1rxclk). miimdc tper_9a none 53.3 ? 44.4 ? ns see figure 11 thigh_9a, tlow_9a 23. 0 ? 20. 0 ? ns miimdio tsu_9b miimdc rising 10.0 ? 10.0 ? ns thld_9b 1.0 ? 1.0 ? ns tdo_9b 1(iclk) 3(iclk) 1(iclk) 3(iclk) ns miixrxclk, miixtx- clk 2 2. the ethernet clock (miixrxclk and miixtxclk) frequency must be equal to or less than 1/2 clk (miixrxclk and miixtxclk <= 1/2(cl k)). tper_ 9c none 399.9 6 400. 4 399.9 6 400. 4 ns 10 mbps thigh_9c, tlow_9c 180 220 180 220 ns trise_9c, tfa ll_9c ?3.0?3.0 ns miixrxclk, miixtxclk 2 tper_9d none 39.9 40.0 39.9 40.0 ns 100 mbps thigh_9d, tlow_9d 18.0 22.0 18.0 22.0 ns trise_9d, tfall_9d ?2.0?2.0 ns miixrxd[3:0], miixrxdv, miixrxer tsu_9e miixrxclk rising 3.0 ? 3.0 ? ns thld_9e 2.0 ? 2.0 ? ns miixtxd[3:0 ], miixtxenp, miixtxer tdo_9f miixtxclk rising 5.0 13 5.0 13.0 ns table 9 ethernet ac timing characteris tics
24 of 44 february 25, 2004 RC32365 figure 11 ethernet ac timing waveform signal symbol reference edge 150mhz 180mhz unit conditions timing diagram refer ence min max min max pci 1 pciclk 2 tper_10a n one 15.0 30.0 15.0 30.0 ns 66 mhz pci see figure 12 thigh_10a, tlow_1 0a 6.0 ? 6.0 ? ns tslew_10 a 1.5 4.0 1.5 4.0 v/n s table 1 0 pci ac timing characteristics (part 1 of 2) tdo_ 9b tdo_9b tdo_ 9f tdo_9f thld_9b tsu_9b tlow tlow_9a th igh_9 a tper_9a tlow_9d tlow thigh_9d tper_9d thld_9e tsu_9e tlow_9d tlow thigh_9d tper_9d miixrxclk miixrxdv, miixrxd[3:0] , miixrxer mi ixtxclk miixtxen, mi ixtxd[3:0], m iixtxer mii xmdc m iixmdio (output ) miixmdio (input )
25 of 44 february 25, 2004 RC32365 pciad[31:0], tsu_10b pciclk rising 3.0 ? 3.0 ? ns thld_10b 0 ? 0 ? ns tdo_10b 2.0 6.0 2.0 6.0 ns tdz_10b 3 ? 14.0 ? 14.0 ns tzd_10b 3 2.0 ? 2.0 ? ns pciben[3:0], pcidevseln, pciframen,pciir- dyn, pcilockn, pci- par, pciperrn, pcistopn, pcitrdy 4 tsu_10 b 5 pcicl k rising 5.0 ? 5.0 ? ns thld_10b 0 ? 0 ? ns tdo_10b 1.5 6.0 1.5 6.0 ns pcigntn[2:0 ], pcireqn[2:0] 4,6 tsu_10c pciclk rising 5.0 ? 5.0 ? ns thld_10c 0 ? 0 ? ns tdo_10c 1.5 6.0 1.5 6.0 ns pcirstn (output) 7 tp w_10d 3 none 4000 (clk) ? 4000 (clk) ? ns see figure 13 pcirstn (input) 7,8 tp w_10e 3 none 2(clk) ? 2(clk) ? ns see figure 14 tdz_10e 3 pcirstn falling 6(clk) ? 6(clk) ? ns pciserrn 9 tsu_10f pciclk rising 3.0 ? 3.0 ? ns see figure 12 thld_10f 0 ? 0 ? ns tzd_10f 3 2.0 6.0 2.0 6.0 ns pcim uintn 10 tzd_10g 3 pciclk rising 4.7 11.1 4.7 11.1 ns 1. this pci interface conforms to the pci local bus specification, rev 2.2 at 33mhz. 2. pciclk must be equal to or less than two times clk (pciclk <= 2(clk)). 3. the values for this symbol were determined by calculation, not by testing. 4. pci local bus specification, rev 2.2 specifies tval minimum = 2.0ns. 5. the 5ns minimum set-up time conforms to the pci local bus specification, rev 2.2 at 33mhz. at 66mhz, the 5ns minimum set-up tim e provides a wide margin of 4ns, which is sufficient to ensure a working design at such frequency. 6. pcigntn[2] and pcireqn[2] are alternate functions of gpio[14] and gpio[13] respectively. 7. pcirstn is an output in host mode and an input in satellite mode. 8. to meet the pci delay specification from reset asserted t o outputs floating, the pci reset should be logically combined with th e coldrstn input, instead of input on pcirstn. 9. pciserrn uses open collector i/o types. 10. pcimuintn is an alternate function of gpio[15]. signal symbol reference edge 150mhz 180mhz unit conditions timing diagram refer ence min max min max table 1 0 pci ac timing characteristics (part 2 of 2)
26 of 44 february 25, 2004 RC32365 figure 12 pci ac timing waveform fi gure 13 pci ac timing waveform ? pci re set in host mode tdo_10c tzd_ 10b tdz_10b tdo_10b thld_10c tsu_10c thld_10b tsu_10b thigh_10a tper_10a tper_10a val id vali d pciclk bussed output point to p oint output bussed input point to point input tlow_10a tpw_ 10d tpw_ 10d pci interface enabled cold reset wa rm r ese t coldrstn pcirstn (out put) rstn note: during and after cold reset, pcirstn is tri-stated and requires a pull-down to reach a low state. after the pci interface is enabled in host mode, pcirstn will be driven either high or low depending on the (tri-state) reset state of the RC32365.
27 of 44 february 25, 2004 RC32365 figure 14 pci ac timing waveform ? pci re set in satel lite mode signal symbol reference edge 150mhz 180mhz unit conditions timing dia gram reference min max min max spi 1 1. in spi mode, the sck period and sampling edge are programmable. in pci mode, the sck period is fixed and the sampling edge is r isi ng . sck tper_12 a none ? 1920 ? 1920 n s 33 mhz pci see fig ures 15 through 18 tper_12 a ? 960 ? 960 n s 66 mhz pci tper_12 a 100 166667 100 166667 n s spi thigh_12a , tlow_ 12a 930 990 930 990 n s 33 mhz pci thigh_12a , tlow_ 12a 465 495 465 495 n s 66 mhz pci thigh_12a , tlow_ 12a 40 83353 40 83353 n s spi sdi tsu_12b sck rising o r falling 60 ? 60 ? ns spi or pci thld_12b 60 ? 60 ? n s sdo tdo _12 c sck rising o r falling 060060 ns spi or pci pcieecs 2 2. pcieecs is the pci serial eeprom chip select. it is an alternate function of pcigntn[1]. tdo_12d sck rising o r falling 060060 ns pci sck, sdi, sdo 3 3. in bit i/o mode, sck, sdi, and sdo must meet the setup and hold times if they are synchronous or the minimum pulse width if the y are asynchronous. tpw_12e none 2(c l k) ? 2(c l k) ?ns ta ble 11 spi ac timing characteristics tdz_10e tpw_10e tpw_10e warm reset clk pcirstn (in put) rstn mdata[15:0] pci bu s signals
28 of 44 february 25, 2004 RC32365 figure 15 spi ac timing waveform ? pci configurations load figure 1 6 spi ac timing waveform ? clock polarity 0 , clock phase 0 td o_12c tdo _ 12d thld _12b tsu_12b tlo w_12a tlo w_12a thigh_12a thigh_12a tper_1 2a m sb bi t 6 b it 5 b it 4 b it 3 bi t 2 b it 1 ls b loading pci configuration registers through spi from an eeprom. ms b b it 6 b it 4 b it 2 ls b bit 5 bit 3 bit 1 sck pcieecs sdi sdo tdo _12c thld_12b tsu_12b tlow_12a thigh _12 a tper_12a ms b b it 6 bi t 4 bit 5 bit 3bit 2bit 1 lsb control bits cpol = 0, cpha = 0 in the spi control register, spc. msb bit 6 bit 4 bit 2 lsb bit 5 bit 3 bit 1 sck sdi sdo
29 of 44 february 25, 2004 RC32365 figure 1 7 spi ac timing waveform ? clock polarity 0 , clock phase 1 figure 18 spi ac timing wav eform ? bit i/o mode tdo _ 12c thld _12b tsu_12 b tlow_12a thigh_12a tper_12a ms b b it 6 bi t 4 bit 5 bit 3 bit 2 bit 1 lsb control bits cpol = 0, cpha = 1 in the spi control register, spc. msb bit 6 bit 4 bi t 5 b it 3 b it 1 bit 2 lsb sck sdi sdo tdo_12e tdo_12e tpw_12e tpw_12e thld_12e tsu _12 e clk sck, sdi, sdo (output) sck, sdi, sdo (input) sck, sdi, sdo (asynchronous inp ut)
30 of 44 february 25, 2004 RC32365 figure 19 gpio ac timing waveform signal symbol reference edge 150mhz 180mhz unit conditions timing dia gram reference min max min max gpio gpio[15:0] 1 1. gpio signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. tsu_13a clk rising 4.0 ? 4.0 ? n s see fig ure 19 thld_13a 2.0 ? 2.0 ? n s tdo_13a 2.0 14.0 2.0 14.0 n s tpw_13b 2 2. the values for this symbol were determined by calculation, not by testing. none 2(c l k) ? 2(c l k) ?ns table 12 gpio ac timing characteristics tdo _13a tdo_13a tpw_13b tpw_13b thld_13 a tsu_ 13a clk gpio (synchronou s outp ut) gpio (synchronous inp ut) gpio (asynchronous inp ut)
31 of 44 february 25, 2004 RC32365 figure 20 ej tag/jtag ac timing wavefor m signal symbol reference edge 150mhz 180mhz unit conditions timing diagram reference min max min max ejtag and jtag jtag_tck tper_14a non e 100 ? 100 ? ns see figure 20 thigh_14 a, tlo w_14a 40 ? 40 ? ns trise_14 a, tfall_14a ?5.0?5.0 ns jtag_tdi tsu_14b jtag_tck rising 4.0 ? 4.0 ? ns thld_14 b 4.0 ? 4.0 ? ns jtag_tms tsu_ 14c 4.0 ? 4.0 ? ns thld_ 14c 4.0 ? 4.0 ? ns ejtag_tms tsu_14d 4.0 ? 4.0 ? ns thld_14 d 4.0 ? 4.0 ? ns jtag_tdo tdo_ 14e jtag_tck falling ? 12.5 ? 12.5 ns tdz_14e 1 ? 15.0 ? 15.0 ns jtag_trst_ n tpw_1 4f 1 1. the values for this symbol were determined by calculation, not by testing. non e 100 ? 100 ? ns vsense tris e_16 f non e ? 2 ? 2 sec measured from 0.5v (t active ) see fig ure 22 table 13 ejtag/jtag ac tim ing cha ra cterist ics tpw_14f tpw_1 tdz_14e tdo_14e th ld_1 4d tsu_14d th ld_1 4c tsu_ 14c th ld_1 4b tsu_ 14b tlo w_14a tlow_1 tper_ 14a thigh_1 4a jtag_tck jtag_tdi jtag_tms ejtag_tms jtag_tdo jtag_trst_n
32 of 44 february 25, 2004 RC32365 the ieee 1149.1 specification requires that the jtag and ejtag tap controllers be reset at power-up whether or not the interfac es are u sed fo r a bo un da ry sca n or a p rob e. re set ca n o ccu r th ro u gh a p ull-d o wn re sisto r on jtag_ trst_ n if th e prob e is n ot co nn ect ed . ho weve r, on -chip p ull-up re sisto rs a re imp lemen te d on the rc3 23 65 du e to an iee e 114 9. 1 re qu ireme nt. ha ving o n-ch ip p u ll-up an d ext erna l p ull-do wn resis tors for the jtag_trst_n signal requires special care in the design to ensure that a valid logical level is provided to jtag_trst_n, such as using a small ext ern al pu ll-d own re sisto r t o en su re th is le vel o verrid e s t he on -chip p ull-up . a n alt erna tive is to use an act ive p owe r-u p res et circuit for jtag_trst_n, which drives jtag_trst_n low only at power-up and then holds jtag_trst_n high afterwards with a pull-up resistor. figure 21 shows the electrical c onnection of the ejtag probe target system connector. figure 21 target system electrical ejtag connec tion using the ejtag probe using the ejtag probe using the ejtag probe using the ejtag probe in figure 21, the pull-up resistors for jtag_tdo and rst*, the pull-down resistor for jtag_trst_n, and the series resistor for jtag_tdo must be a dju ste d t o t he sp ecific de sign . ho weve r, th e re comme nd ed p ull-u p /do wn re sisto r is 1 .0 k ? because a low value reduces crosstalk on the cable to the connector, allowing higher jtag_tck frequencies. a typical value for the series resistor is 33 ? . recommended resistor values have 5% toler- an ce . if a probe is used, the pull-up resistor on jtag_tdo must ensure that the jtag_tdo level is high when no probe is connected and the jtag_tdo output is tri-stated. this requirement allows reliable connection of the probe if it is hooked-up when the power is al ready on (hot plug). the pu ll-u p re sisto r valu e of aro un d 47 k ? should be sufficient. optional diodes to protect against overshoot and undershoot voltage can be added on the sign als of the ch ip wit h e jta g. if a probe is used, the rst* signal must have a pull-up resistor because it is controlled by an open-collector (oc) driver in t h e pro be , an d th us is act ively pu lled lo w on ly. th e pu ll-u p re sis tor is re spo n sible f or the hig h va lu e wh en no t drive n by t he p rob e o f 25 pf. the in pu t on the target system reset circuit must be able to accept the rise time when the pull-up resistor charges the capacitance to a high logical level. v cc i/o must connect to a volt ag e re fere nce th at dro ps ra pid ly to be lo w 0 .5v whe n th e ta rge t sys tem lo ses po wer, eve n wit h a ca pa citive lo ad o f 2 5p f. th e p rob e can th us d e tect the lost power condition. for additional information on ejtag, refer to chapter 23 of the RC32365 user reference manual. g nd 1 g nd g nd g nd gnd trs t* tdi tdo tm s tck rs t* jtag _trst_n jtag_tdi jtag_tdo ejtag_tms jtag _tck gnd vdd g nd pul l-up pull-dow n seri e s-res. coldrstn target system reset ci rcuit pul l-up other reset sources RC32365 no conn ect or rstn vsense 2 gnd gn d gnd g nd g nd gnd g nd no connect no conn ect no conn ect gnd pul l-up v cc i/ o voltage ref erence 23 2 4
33 of 44 february 25, 2004 RC32365 voltage sense signal timing voltage sense signal timing voltage sense signal timing voltage sense signal timing figure 22 voltage sense signal timing the target system must ensure that t rise is obeyed after the system reaches 0.5v (t active ), so th e pro be ca n use t his va lue t o de te rmine wh en t he target has powered-up. the probe is allowed to measure the t rise time from a higher value than t ac ti ve (but lower than vcc i/o minimum) because the stable indication in this case comes later than the time when target power is guaranteed to be stable. if jtag_trst_n is assert ed by a pulse at power-up, this reset must be completed after t rise . if jtag_trst_n is asserted by a pull-down resistor, the probe will control jtag_trst_n. at power-down, no power is indicated to the probe when vcc i/o drops under the t active value, which the probe uses to stop driving the input signals, exc ep t fo r th e pro be rst* . a a a ac test conditions c test conditions c test conditions c test conditions fig ure 23 ou tp ut lo adin g f or a c tim ing phase-locked loop (pll) phase-locked loop (pll) phase-locked loop (pll) phase-locked loop (pll) the processor aligns the pipeline clock, pclock, to the master input clock (clk) by using an internal phase-locked loop (pll) c ircuit that generates aligned c locks. inherently, pll circuits are only capable of generating aligned clocks for master input clock (clk) frequencies within a limit ed range. pll analog filter the storage capacitor required for the phase-locked loop circuit is contained in the RC32365. however, it is recommended that t he system de sign er p rovid e a f ilt er n et work o f p as siv e co mpo n en ts f or th e pl l po wer su pp ly. v cc pll (circuit power) and v ss pll (circuit ground) should be isolated from v cc core (co re po we r) an d v ss (common ground) with a filter circuit such as the one shown in figure 24. vsense t rise_16f t act ive 1.5v parameter value units input pulse levels 0 to 3.0 v input rise/f all 3.5 ns input reference level 1.5 v output refere nce levels 1.5 v ac te st load 35 pf RC32365 output . 50 ? 50 ? test point
34 of 44 february 25, 2004 RC32365 because the optimum values for the filter components depend upon the application and the system noise environment, these values should be con side red a s sta rting p oin ts f or fu rth er e xpe rime nt at io n wit hin yo ur sp ec if ic ap plica tion . figure 24 pll filter circuit for noisy environments r r r recommended operating ecommended operating ecommended operating ecommended operating s s s supply voltage upply voltage upply voltage upply voltages s s s recommended operating temperatures recommended operating temperatures recommended operating temperatures recommended operating temperatures capacitive load deration capacitive load deration capacitive load deration capacitive load deration ref er to the RC32365 ibis model which can be found at the idt web site (www.idt.com). power-on rampup power-on rampup power-on rampup power-on rampup the 2.5v v cc co re an d v cc pll supplies can be fully powered without the 3.3v v cc i/o supply. however, the v cc i/o supply cannot exceed the v cc core an d v cc pll supplies by more than 1 volt during power up. a sustained large power difference could potentially damage the part. inputs should not be driven until the part is fully powered. specifically, the input high voltages should not be applied until the v cc i/o supply is powered. the re is no sp ecia l req uireme nt fo r ho w fa st v cc i/o ramps up to 3.3v. however, all timing references are based on a stable v cc i/o. symbol parameter minimum typical maximum unit v ss common ground 0 0 0 v v ss pll pll grou nd v cc i/o i/o supp ly 3.135 3.3 3 .465 v cc core interna l logic supply 2.375 2.5 2 .625 v cc pll pll su pply table 14 rc3 2365 operating supply voltages grade temperature commercial 0 c+ 70 c am bient indu strial -40 c+ 85 c ambient table 15 RC32365 operating temperature 10 f 0.1 f 10 0 pf vcc vss vccpll vsspll 10 ohm 1 1. th is resist or may be required in noisy circuit environments. RC32365
35 of 44 february 25, 2004 RC32365 dc electrical characteristics dc electrical characteristics dc electrical characteristics dc electrical characteristics the values given below are based on systems running at recommended supply voltages, as shown in table 14. note: for a complete list of i /o types, see table 2. power consumptio power consumptio power consumptio power consumption n n n para meter min max unit conditions low drive ou tput with schm itt trigger input (sti) i ol ?7.3mav ol = 0.4v i oh ?-8.0mav oh = (v cc i/o - 0.4) v il ?0.8v ? v ih 2.0 (v cc i/o + 0.5) v ? high drive ou tput with standard input i ol ?9.4mav ol = 0.4v i oh ?-15mav oh = (v cc i/o - 0.4) v il ?0.8v ? v ih 2.0 (v cc i/o + 0.5) v ? clock drive ou tput i ol 39 ? ma v ol = 0.4v i oh -2 4 ? ma v oh = (v cc i/o - 0.4) pci i oh (ac) switching -12(v cc i/o) ? ma 0 < v out < 0.3(v cc i/o) -17.1(v cc i/o - v out ) ? ma 0.3(v cc i/o) < v out < 0.9(v cc i/o) ? -32(v cc i/o) ma 0.7(v cc i/o) i ol (ac) switching +16(v cc i/o) ma v cc i/o > v out > 0.6 (v cc i/o) +26.7 (v ou t ) ma 0.6(v cc i/ o) > v out > 0.1(v cc i/o) ? +38(v cc i/o) ma v ou t = 0.18(v cc i/o) v il -0 .3 0 .3(v cc i/o) v ? v ih 0.5(v cc i/o) 5.5 v ? capacitance c in ?10pf ? leakage i/o leak ?20 a? table 16 dc electrical characteristic s parameter 150mhz 180mhz unit conditions ty pical m ax. ty pical m ax. icci/o 60 80 80 100 ma c l = 25pf (affe cts i/o) t a = 25 o c maxim um value s use the m aximum voltag es liste d in table 14. typical values use the typical vo ltage s listed in ta ble 1 4. i cc core normal mode 7 10 7 50 800 8 50 ma standb y mo de 1 1. riscore 32300 cpu core enters standby mode by executing wait instructions; however, other logic continues to function. standby mode reduces power consumption by 0.6 ma per mhz of the cpu pipeline clock, pclk. 620 660 690 740 ma power dissipation normal mode 2 .07 2 .2 2 .38 2 .58 w standb y mo de 1 1.8 2.0 2.1 2.3 w table 17 rc3 2365 power consumption
36 of 44 february 25, 2004 RC32365 power curve power curve power curve power curve the following graph contains a power curve that shows power consumption at various bus frequencies. figure 25 typical power usage absolute maximum ratings absolute maximum ratings absolute maximum ratings absolute maximum ratings sy mbol parameter min 1 1. functional and tested operating conditions are given in table 14. absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. stresses beyond those listed may affect device reliabil- ity or cause permanent damage to the device. max 1 unit v cc i/o i /o supp ly voltage -0. 6 4.0 v v cc core core su pply voltage -0.3 3.0 v v cc pll pll supply voltage -0.3 3.0 v vimin i nput voltage - u ndershoot -0.6 ? v vi i /o in put volt age gnd v cc i/o+0.6 v ta, indu strial am bient operating temperature -40 + 8 5 c ta, commercial am bient operating temperature 0+70 c tstg sto rage temperature -40 +12 5 c table 18 absolute maximum rati ngs typical power curve 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 70 75 80 8 5 90 95 100 system bus speed (mhz) power (w @ 3.3v io & 2.5v cor e
37 of 44 february 25, 2004 RC32365 package pin-out ? 2 package pin-out ? 2 package pin-out ? 2 package pin-out ? 256- 56- 56- 56-pin pin pin pin cabga cabga cabga cabga the following table lists the pin numbers and signal names for the RC32365. pin function alt pin function alt pin function alt pin function alt a1 m ii0rxd[0] e1 gpio[15] 1 j1 pcigntn[1] n1 pciad[4 ] a2 mii0rxdv e2 jtag_trst_n j2 pcidevseln n2 pciad[20] a3 mii0rxer e3 jtag_tdo j3 pcigntn[0] n3 pciad[19] a4 mii0txclk e4 jtag_tdi j4 pciframen n4 pciad[11] a5 mii0txd[2] e5 v cc cor e j5 v cc i/o n5 pciad[1 3] a6 mii0crs e6 v cc i/o j6 v ss n6 pciad[1 5] a7 vsspll e7 v cc i/o j7 v ss n7 boen[0] a8 m ii1rxclk e8 v cc i/o j8 v ss n8 csn[2 ] a9 mii1txd[2] e9 v cc i/o j9 v ss n9 csn[3 ] a10 mii1cl e10 v cc i/o j10 v ss n1 0 rwn a11 jtag_tck e11 v cc i/o j11 v ss n11 mdata[1] a12 gpio[9] 1 e12 v cc cor e j12 v cc i/o n1 2 mdata[3] a13 gpio[5] 1 e13 maddr[5] j13 sdwen n13 mdata[12] a14 gpio[3] 1 e14 maddr [16] j14 sdcl ki np n1 4 mdata[30] a15 gpio[1] 1 e15 maddr[17] j15 bwen[2] n1 5 mdata[11] a16 maddr[10] e16 maddr[6] j16 bwen[3] n16 mdata[27] b1 m ii0rxd[3] f1 gpio[14] 1 k1 pcicben[1] p1 pciad[5 ] b2 m ii0rxd[1] f2 gpio[13] 1 k2 pcicben[2] p2 pciad[2 1] b3 m ii0rxclk f3 pc itr dyn k3 pcic ben [0] p3 pciad[2 3] b4 mii0txer f4 pcistopn k4 pciclk p4 pciad[10] b5 m ii0txd[3 ] f5 v cc cor e k5 v cc i/o p5 pciad[2 8] b6 m ii0cl f6 v cc i/o k6 v ss p6 pciad[30] b7 vccpll f7 v ss k7 v ss p7 bdirn b8 m ii1rxdv f8 v ss k8 v ss p8 csn[1 ] b9 m ii1txd[3 ] f9 v ss k9 v ss p9 csn[4 ] b10mii1crs f10v ss k10 v ss p10 waitackn b11 gpio[12] 1 f11 v cc i/o k11 v ss p11 mdata[17] b12 gpio[8] 1 f12 v cc cor e k12 v cc core p12 mdata[19] b13 gpio[4] 1 f13 maddr[3] k13 bwen[1] p13 mdata[5] b14 gpio[2] 1 f14 maddr[14] k14 rasn p14 mdata[9] b15 maddr[21] f15 maddr[15] k15 casn p15 mdata[10] b16 maddr[20] f16 maddr[4] k16 bwen[0] p16 mdata[26] c1 m iimdc g1 pc irstn l1 pciad[1 6] r1 pciad[6 ] c2 m iimdio g2 pc iserrn l2 pciad[1 ] r2 pciad[7 ] table 19: 2 56-pin cabga pack age pin-out (part 1 of 2)
38 of 44 february 25, 2004 RC32365 c3 m ii0rxd[2] g3 pc iperrn l3 pciad[0 ] r3 pciad[2 4] c4 m ii0txenp g4 pcireqn[0] l4 pcicben[3] r4 pciad[2 5] c5 m ii0txd[1 ] g5 v cc cor e l5 v cc core r5 pciad[2 7] c6 m ii1rxd[3] g6 v ss l6 v cc i/o r6 pciad[2 9] c7 m ii1rxd[0] g7 v ss l7 v ss r7 pciad[3 1] c8 m ii1rxer g8 v ss l8 v ss r8 boen[1] c9 m ii1txenp g9 v ss l9 v ss r9 oen c1 0 m ii1txd[0 ] g10 v ss l10 v ss r1 0 mdata[16] c11ejtag_tms g11v ss l11 v cc i/o r11 mdata[18] c1 2 gpio[10] 1 g12 v cc i/o l12 v cc core r1 2 mdata[20] c1 3 gpio[6] 1 g13 maddr[1] l13 clk r1 3 mdata[21] c1 4 gpio[0] 1 g14 maddr [12] l14 sdcl kou t r1 4 mdata[7] c1 5 m ad dr[9 ] g15 maddr [13] l15 mdata[15] r1 5 mdata[24] c1 6 m ad dr[1 9] g16 maddr [2] l16 mdata[31] r1 6 mdata[25] d1 sdi h1 pcipar m1 pciad[18] t1 pciad[22] d2 c ol drstn h2 pc ireqn[1] m2 pciad[3 ] t2 pciad[8 ] d3 sd o h3 pc ilockn m3 pciad[2 ] t3 pciad[9 ] d4 sc k h4 pc irdyn m4 pciad[1 7] t4 pciad[2 6] d5 m ii0txd[0 ] h5 v cc i/o m5 v cc core t5 pciad[1 2] d6 m ii1rxd[2] h6 v ss m6 v cc i/o t6 pciad[1 4] d7 m ii1rxd[1] h7 v ss m7 v cc i/o t7 rstn d8 m ii1txer h8 v ss m8 v cc i/o t8 csn[0 ] d9 m ii1txcl k h9 v ss m9 v cc i/o t9 csn[5 ] d1 0 m ii1txd[1 ] h1 0 v ss m10 v cc i/o t10 mdata[0] d11 jtag_tms h11 v ss m11 v cc i/o t11 mdata[2] d1 2 gpio[11] 1 h1 2 v cc i/o m12 v cc core t12 mdata[4] d1 3 gpio[7] 1 h1 3 sd csn[0] m13 mdata[14] t13 mdata[6] d1 4 m ad dr[7 ] h1 4 sd csn[1] m14 mdata[13] t14 mdata[22] d1 5 m ad dr[1 8] h1 5 maddr [11] m15 mdata[28] t15 mdata[23] d1 6 m ad dr[8 ] h1 6 maddr [0] m16 mdata[29] t16 mdata[8] pin function alt pin function alt pin function alt pin function alt table 19: 2 56-pin cabga pack age pin-out (part 2 of 2)
39 of 44 february 25, 2004 RC32365 RC32365 p RC32365 p RC32365 p RC32365 power pins ower pi ns ower pi ns ower pi ns RC32365 g RC32365 g RC32365 g RC32365 ground pins round pins round pins round pins v cc i/o v cc i/o v cc core v cc pll e6 j5 e5 b7 e7 j12 e12 e8 k5 f5 e9 l6 f12 e10 l11 g5 e11 m6 k12 f6 m7 l5 f11 m8 l12 g12 m9 m5 h5 m10 m12 h12 m11 table 20 rc3 2365 power pins v ss v ss v ss v ss pll f7 h7 k6 a7 f8 h 8 k7 f9 h 9 k8 f10 h10 k9 g6 h11 k10 g7 j6 k11 g8 j7 l7 g9 j8 l8 g10 j9 l9 g11 j10 l10 h6 j11 ta ble 21 rc323 65 ground pins
40 of 44 february 25, 2004 RC32365 alternate pi n functi ons alternate pi n functi ons alternate pi n functi ons alternate pi n functi ons pin primar y alt #1 c14 gpio[0] u0sout a15 gpio[1] u0sinp b1 4 gpio[2] maddr[22] a1 4 gpio[3] maddr[23] b1 3 gpio[4] maddr[24] a1 3 gpio[5] maddr[25] c13 gpio[6] n/a d13 gpio[7] sdckenp b1 2 gpio[8] cen1 a1 2 gpio[9] cen2 c12 gpio[10] regn d12 gpio[11] iordn b1 1 gpio[12] iowrn f2 gpio[13] pcireqn[2] f1 gpio[14] pcigntn[2] e1 gpio[15] pcim unitn table 22 alt ernat e pin f un cti on s
41 of 44 february 25, 2004 RC32365 RC32365 p RC32365 p RC32365 p RC32365 pinout ? top view inout ? top view inout ? top view inout ? top view 1 2345678910 11 1 2 13 14 15 16 v ss (ground) v cc i/o (power) a b v cc core (power) c d e f g h j k l m n p r t vs spll vcc pll
42 of 44 february 25, 2004 RC32365 package drawing - package drawing - package drawing - package drawing - 256- 256- 256- 256-pin pin pin pin cabga cabga cabga cabga
43 of 44 february 25, 2004 RC32365 p p p package drawing - page two ackage drawing - page two ackage drawing - page two ackage drawing - page two
44 of 44 february 25, 2004 RC32365 corporate headquarters 29 75 s te nd er way santa clara, ca 95054 for sale s: 800-345-7015 or 408-727-6116 fax: 408-330-1748 www.idt.com for tech support: email: rischelp@idt.com phone: 408-492-8208 ordering infor mation ordering infor mation ordering infor mation ordering infor mation valid combinations valid combinations valid combinations valid combinations 79rc32t3 65 -150b c, 180bc 256-p in cabga package, commercial temperature 79rc32t3 65 -150b ci 256-p in cabga package, indu strial temperature 79rcxx yy xxxx 999 a a operating voltage device typ e speed package te mp ra ng e/ process t 150 blank commercial temperature (0c to +70c ambient) 150 mhz pipeline clk 2.5v +/-5% core voltage integrated core processor product typ e 79rc32 32-bit embedded microprocessor 256-pin cabga bc 365 i i nd ust ria l temp era ture (-40 c to +85 c ambient) 180 180 mhz p ipe lin e clk

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