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| ? 2005-2012 microchip technology inc. ds22018f-page 1 mcp2021/2/1p/2p features ? the mcp2021/2/1p/2p are compliant with lin bus specifications 1.3, 2.0, and 2.1 and are compliant to sae j2602 ? support baud rates up to 20 kbaud with lin-compatible output driver ? 43v load dump protected ? very low emi meets stringent oem requirements ? wide supply voltage, 6.0v - 18.0v continuous: - maximum input voltage of 30v ? extended temperature range: -40 to +125c ? interface to pic eusart and standard usarts ? local interconnect network (lin) bus pin: - internal pull-up resistor and diode - protected against ground shorts - protected against loss of ground - high current drive ? automatic thermal shutdown ? on-chip voltage regulator: - output voltage of 5.0v with tolerances of 3% overtemperature range - available with alternate output voltage of 3.3v with tolerances of 3% overtemperature range - maximum continuous input voltage of 30v - internal thermal overload protection - internal short circuit current limit - external components limited to filter capacitor only and load capacitor ? two low-power modes: - receiver on, transmitter off, voltage regulator on ( ? 85 a) - receiver monitoring bus, transmitter off, voltage regulator off ( ? 16 a) description the mcp2021/2/1p/2p provides a bidirectional, half- duplex communication physical interface to automotive and industrial lin systems that meets the lin bus specification revision 2.0. the devices incorporate a voltage regulator with 5v at 50 ma or 3.3v at 50 ma regulated power-supply outputs. the regulator is short-circuit protected, and is protected by an internal thermal shutdown circuit. the device has been specifically designed to operate in the automotive operating environment and will survive all specified transient conditions while meeting all of the stringent quiescent current requirements. the mcp2021/2/1p/2p family of devices includes the following packages. 8-pin pdip, dfn and soic packages: ? mcp2021-330, lin-compatible driver, 8-pin, 3.3v regulator, wake up on dominant level of lbus ? mcp2021-500, lin-compatible driver, 8-pin, 5.0v regulator, wake up on dominant level of lbus ? mcp2021p-330, lin-compatible driver, 8-pin, 3.3v regulator, wake up at falling edge of lbus voltage ? mcp2021p-500, lin-compatible driver, 8-pin, 5.0v regulator, wake up at falling edge of lbus voltage 14-pin pdip, tssop and soic packages with reset output: ? mcp2022-330, lin-compatible driver, 14-pin, 3.3v regulator, reset output, wake up on domi- nant level of lbus ? mcp2022-500, lin-compatible driver, 14-pin, 5.0v regulator, reset output, wake up on domi- nant level of lbus ? mcp2022p-330, lin-compatible driver, 14-pin, 3.3v regulator, reset output, wake up at falling edge of lbus voltage ? mcp2022p-500, lin-compatible driver, 14-pin, 5.0v regulator, reset output, wake up at falling edge of lbus voltage lin transceiver with voltage regulator
mcp2021/2/1p/2p ds22018f-page 2 ? 2005-2012 microchip technology inc. package types mcp2021/2 block diagram mcp2021 dfn-8, pdip-8, soic-8 1 2 3 4 8 7 6 5 mcp2022 pdip-14, soic-14, tssop-14 1 2 3 4 14 13 12 11 10 9 8 5 6 7 rxd cs/lwake v reg txd fault /txe v bb l bus v ss rxd cs/lwake v reg txd reset nc nc fault /txe v bb l bus v ss nc nc nc mcp2021p mcp2022p voltage regulator ratiometric reference oc thermal protection internal circuits v reg fault /txe rxd txd v bb l bus v ss ~30 k cs/lwake wake-up logic and power control reset short circuit protection short circuit protection thermal protection (mcp2022 only ) ? + ? 2005-2012 microchip technology inc. ds22018f-page 3 mcp2021/2/1p/2p mcp2021p/2p block diagram ratiometric reference internal circuits v reg rxd txd v bb v ss ~30 wake-up logic and power control reset thermal protection k (mcp2022p only ) l bus short-circuit protection oc cs/lwake fault /txe ? + voltage regulator short-circuit protection thermal short-circuit protection and mcp2021/2/1p/2p ds22018f-page 4 ? 2005-2012 microchip technology inc. notes: ? 2005-2012 microchip technology inc. ds22018f-page 5 mcp2021/2/1p/2p 1.0 device overview the mcp2021/2/1p/2p provides a physical interface between a microcontroller and a lin half-duplex bus. it is intended for automotive and industrial applications with serial bus speeds up to 20 kbaud. the mcp2021/2/1p/2p provides a half-duplex, bidirec- tional communications interface between a microcon- troller and the serial network bus. this device will translate the cmos/ttl logic levels to lin-level logic, and vice versa. the lin specification 2.0 requires that the trans- ceiver(s) of all nodes in the system be connected via the lin pin, referenced to ground, and with a maximum external termination resistance load of 510 from lin bus to battery supply. the 510 corresponds to 1 mas- ter and 16 slave nodes. the mcp2021/2/1p/2p-500 provides a +5v, 50 ma, regulated power output. the regulator uses an ldo design, is short-circuit protected, and will turn the regulator output off if it falls below 3.5v. the mcp2021/2/1p/2p also includes thermal- shutdown protection. the regulator is specifically designed to operate in the automotive environment and will survive +43v load dump transients, double-battery jumps, and reverse battery connections when a reverse blocking diode is used. the other members of the mcp2021/2/1p/2p- 330 family output +3.3v at 50 ma with a turn-off voltage of 2.5v. (see section 1.6 ?internal voltage regulator? ). mcp2021/2 wakes from power-down mode on a dominant level on lbus. mcp2021p/2p wakes at a transition from recessive level to dominant level on lbus. 1.1 optional external protection 1.1.1 reverse battery protection an external reverse-battery-blocking diode should be used to provide polarity protection (see figure 1-6 ). 1.1.2 transient voltage protection (load dump) an external 43v transient suppressor (tvs) diode, between v bb and ground, with a 50 transient protec- tion resistor (r tp ) in series with the battery supply and the v bb pin protect the device from power transients (see figure 1-6 ) and esd events. while this protection is optional, it is considered good engineering practice. the resistor value is chosen according to equation 1-1 . equation 1-1: 1.2 internal protection 1.2.1 esd protection for component-level esd ratings, please refer to the section 2.1 ?absolute maximum ratings?? . 1.2.2 ground loss protection the lin bus specification states that the lin pin must transition to the recessive state when ground is discon- nected. therefore, a loss of ground effectively forces the lin line to a hi-impedance level. 1.2.3 thermal protection the thermal protection circuit monitors the die temper- ature and is able to shut down the lin transmitter and voltage regulator if it detects a thermal overload. there are three causes for a thermal overload. a ther- mal shut down can be triggered by any one, or a com- bination of, the following thermal overload conditions: ? voltage regulator overload ? lin bus output overload ? increase in die temperature due to increase in environmental temperature driving the txd and checking the rxd pin makes it possible to determine whether there is a bus contention (i.e., rx = low, tx = high) or a thermal overload condi- tion (i.e., rx = high, tx = low). r tp <= (v bb min - 5.5) / 250 ma. 5.5v = v uvlo + 1.0v, 250 ma is the peak current at power-on when v bb = 5.5v mcp2021/2/1p/2p ds22018f-page 6 ? 2005-2012 microchip technology inc. figure 1-1: thermal shutdown state diagrams. 1.3 modes of operation for an overview of all operational modes, please refer to tab le 1 -1 . 1.3.1 power-on reset mode upon application of v bb , the device enters power-on reset mode (por). during this mode, the part main- tains the digital section in a reset mode and waits until the voltage on pin v bb rises above the ?on? threshold (typ. 5.75v) to enter to the ready mode. if during the operation, the voltage on pin v bb falls below the ?off? threshold (typ. 4.25v), the part comes back to the por mode. 1.3.2 power-down mode in the power-down mode, the transmitter and the voltage regulator are off. only the receiver wake-up from lin bus section, and the cs/lwake pin wake-up circuits are in operation. this is the lowest power mode. if pin cs/lwake goes to a high level during power- down mode, the device immediately enters ready mode and enables the voltage regulator; and after the output has stabilized (approximately 0.3 ms to 1.2 ms), the device goes to operation mode or transmitter-off mode (see figure 1-2 for mcp2021/2 and figure 1-3 for mcp2021p/2p). lin bus activity will also change the device from power-down mode to ready mode. mcp2021/2 wakes up on dominant level of lin bus, and mcp2021p/2p on a falling edge that follows a domi- nant level lasting 20 s of time. the power-down mode can be reached through either operation mode or transmitter-off mode. 1.3.3 ready mode upon entering ready mode, the voltage regulator and receiver-threshold-detect circuit are powered up. the transmitter remains in off state. the device is ready to receive data as soon as the regulator is stabilized, but not to transmit. if a microcontroller is being driven by the voltage regulator output, it will go through a por and initialization sequence. the lin pin is in the reces- sive state for mcp2021/2 and in floating state for mcp2021p/2p. the device will stay in ready mode until the output of the voltage regulator has stabilized and the cs/lwake pin is true (? 1 ?). after v reg is stable and cs/lwake is high, mcp2021/2 will enter operation mode; and mcp2021p/2p will enter either operation mode or transmitter-off mode, depending on the level of the fault /txe pin (refer to figure 1-3 ). 1.3.4 operation mode in this mode, all internal modules are operational. the device will go into the power-down mode on the falling edge of cs/lwake. for the mcp2021p/2p devices, the pull-up resistor is switched on only in this mode. operation mode transmitter shutdown lin bus voltage shutdown regulator output temperature mcp2021/2/1p/2p ds22018f-page 8 ? 2005-2012 microchip technology inc. figure 1-2: mcp2021/2 operational modes state diagrams. figure 1-3: mcp2021p/2p operational modes state diagrams. power-down tx: off rx: off vreg: off cs/lwake=0 transmitter off tx: off rx: on vreg: on por tx: off rx: off vreg: off operation tx: on rx: on vreg: on ready tx: off rx: on vreg: on vbat > 5 . 75 v cs/lwake=1& vreg_ok=1 cs/lwake=0 fault/txe=0 or faults* fault/txe=1 &no faults* cs/lwake=1 or dominant level on lbus start *fault: thermal shutdown and txd/lbus permanent dominant note: while the device is in shutdown, t xd should not be actively driven high or it may power internal logic through the esd diodes and may damage the device. power-down tx: off rx: off vreg: off cs/lwake=0 transmitter off tx: off rx: on vreg: on por tx: off rx: off vreg: off operation tx: on rx: on vreg: on ready tx: off rx: on vreg: on vbat > 5 . 75 v cs/lwake=1& vreg_ok=1& fault/txe=1 cs/lwake=0 fault/txe=0 or faults* fault/txe=1 &no faults* cs/lwake=1 or falling edge on lbus start *fault: thermal shutdown and txd/lbus permanent dominant cs=1&vreg_ok=1 &fault/txe=0 ? 2005-2012 microchip technology inc. ds22018f-page 9 mcp2021/2/1p/2p figure 1-4: mcp2021p/2p wake-up due to bus disconnecting. ready state sleep 0 lbus nfault_txe vreg cs_lwake 0 mcp2021/2/1p/2p ds22018f-page 10 ? 2005-2012 microchip technology inc. figure 1-5: forced power-down mode sequence for mcp2021p/2p. cs/lwake v reg fault/txe l bus operation mode transmitter-off mode power-down mode t csactive > = 2s fault/txe = 1 forced internally fault/txe = 0 forced externally lbus disconnected; e.g., master pull-up & internal resistor off; lbus floating. forced power-down mode after bus-off instruction or a longer lin-bus inactivity ( > = 4 sec according to lin specification) state ? 2005-2012 microchip technology inc. ds22018f-page 11 mcp2021/2/1p/2p table 1-1: overview of operational modes state transmitter receiver voltage regulator operation comments por off off off read vbb; if vbb>5.75v, enter ready mode ready off on on mcp2021/2 : if cs/lwake is high level, then operation mode. mcp2021p/2p : if cs/lwake is high level and fault /txe is high level, then operation mode. if cs/lwake is high level and fault /txe is low level, then txoff mode. bus off state operation on on on if cs/lwake is low level, then power- down mode. if fault /txe is low level or txd/lbus permanent dominant is detected, then transmitter-off mode. normal operation mode power-down off activity detect off on lin bus falling, go to ready mode. on cs/lwake high level, go through ready mode; then, to either operation or transmitter-off mode (refer to figure 1-2 and figure 1-3 ). low power mode transmitter-off off on on if cs/lwake is low level, then power- down mode. if fault /txe is high, then operation mode. mcp2021/2/1p/2p ds22018f-page 12 ? 2005-2012 microchip technology inc. 1.4 pin descriptions table 1-1: pinout descriptions 1.4.1 power output (v reg ) positive supply voltage regulator output pin. 1.4.2 ground (v ss ) ground pin. 1.4.3 battery (v bb ) battery positive supply voltage pin. this pin is also the input for the internal voltage regulator. 1.4.4 transmit data input (txd) the transmit data input pin has an internal pull-up to v reg . the lin pin is low (dominant) when txd is low, and high (recessive) when txd is high. for extra bus security, txd is internally forced to ? 1 ? when v reg is less than 1.8v (typ.). if the thermal protection detects an over-temperature condition while the signal txd is low, the transmitter is shut down. the recovery from the thermal shutdown is equal to adequate cooling time. 1.4.5 receive data output (rxd) the receive data output pin is a standard cmos output and follows the state of the lin pin. 1.4.6 lin bus the bidirectional lin bus interface pin is the driver unit for the lin pin and is controlled by the signal txd. lin has an open collector output with a current limitation. to reduce emi, the edges during the signal changes are slope-controlled. to further reduce radiated emis- sions, the l bus pin has corner-rounding control for both falling and rising edges. the internal lin receiver observes the activities on the lin bus, and generates output signal rxd that follows the state of the l bus . a 1 st degree with 1 s time con- stant (160khz), low-pass input filter is placed to maintain emi immunity. 1.4.7 cs/lwake chip select input pin. a internal pull-down resistor will keep the cs/lwake pin low. this is done to ensure that no disruptive data will be present on the bus while the microcontroller is executing a por and i/o initial- ization sequence. the pin must see a high level to activate the transmitter. if cs/lwake= ? 0 ? when the v bb supply is turned on, the device stays in ready mode (low-power mode). in ready mode, both the receiver and the voltage regulator are on and the lin transmitter driver is off. if cs/lwake = ? 1 ? when the v bb supply is turned on, the device will proceed to either operation or transmit- ter-off mode (refer to figure 1-2 and figure 1-3 ) after the v reg output has stabilized. this pin may also be used as a local wake-up input (see figure 1-6 ). in this implementation, the microcon- troller will set the i/o pin that controls the cs/lwake as an high-impedance input. the internal pull-down resistor will keep the input low. an external switch, or other source, can then wake up the transceiver and the microcontroller. pin name devices pin type function 8-pin dfn, pdip, soic 14-pin pdip, soic, tssop normal operation v reg 3 3 o power output v ss 5 11 p ground v bb 7 13 p battery supply txd 4 4 i transmit data input (ttl) rxd 1 1 o receive data output (cmos) l bus 6 12 i/o lin bus (bidirectional) cs/lwake 2 2 ttl chip select (ttl) fault /txe 8 14 od fault detect output, transmitter enable (od) reset ? 5 od reset signal output (od) legend: o = output, p = power, i = input, ttl = ttl input buffer, od = open-drain output note: cs/lwake should not be tied directly to v reg as this could force the mcp202x into operation mode before the microcontroller is initialized. ? 2005-2012 microchip technology inc. ds22018f-page 13 mcp2021/2/1p/2p 1.4.8 fault /txe fault detect output and transmitter enable input bidirectional pin. this pin is an open-drain output. its state is defined as shown in table 1-2 . the transmitter driver is disabled whenever this pin is low (? 0 ?), either from an internal fault condition or by external drive. this allows the transmitter to be placed in an off state and still allow the voltage regulator to operate. refer to ta b l e 1 - 1 . the fault /txe also signals a mismatch between the txd input and the l bus level. this can be used to detect a bus contention. since the bus exhibits a propagation delay, the sampling of the internal compare is debounced to eliminate false faults. this pin has an internal pull-up resistor of approximately 750 k . the fault /txe pin sampled at a rate faster than every 10 s. table 1-2: fault / txe truth table 1.4.9 reset reset is an open-drain output pin. this pin reflects an internal signal that tracks the internal system voltage has reached a valid, stable level. as long as the internal voltage is valid, this pin will keep high impedance. when the system voltage drops below the minimum required, the voltage regulator will shut down and immediately convert the reset output to short to gnd. a pull-up resistor is needed to change the output to high/low voltage. when connected to a micro-controller input, this can provide a warning that the voltage regulator is shutting down (see figure 1-2 ). alternately, it can act as an external brown-out by con- necting the reset output to mclr (see figure 1-2 ). in addition to monitoring the internal voltage, reset is asserted immediately upon entering the power-down mode. note 1: the fault /txe pin is true ( 0 ) whenever the internal circuits have detected a short or thermal excursion and have disabled the l bus output driver. 2: fault /txe is true ( 0 ) when v reg not ok and has disabled the l bus output driver. txd in rxd out lin bus i/o thermal override fault/ txe definition external input driven output lhv bb off h l fault , txd driven low, lin bus shorted to v bb (note 1) hh v bb off h h ok llgnd off h h ok hlgnd off h h ok , data is being received from the lin bus xxv bb on h l fault , transceiver in thermal shutdown xxv bb xlx no fault , the cpu is commanding the transceiver to turn off the transmitter driver legend: x = don?t care note 1: the fault /txe is valid after approximately 25 s after txd falling edge. this is to eliminate false fault reporting during bus propagation delays. mcp2021/2/1p/2p ds22018f-page 14 ? 2005-2012 microchip technology inc. 1.5 typical applications figure 1-6: typical mcp2021/mcp2021p application. lin bus 27v (4) v bb l bus v reg txd rxd v ss v dd txd rxd +12 c f c g cs/lwake i/o fault/ txe i/o 43v (5) 1k +12 master node only +12 220 k wake-up note 1: see figure 2-3 for correct capacity and esr for stable operation. . 2: c f is the filter capacitor for the external voltage supply. 3: this diode is only needed if cs/lwake is connected to a 12v supply. 4: transient suppressor diode. vclamp l = 43v. 5: these components are required for additional load dump protection above 43v. (3) r tp (5) 100 pf ? 2005-2012 microchip technology inc. ds22018f-page 15 mcp2021/2/1p/2p figure 1-7: typical mcp2022/mcp2022p application. figure 1-8: typical lin network configuration. lin bus 27v (4) v bb l bus v reg txd rxd v ss v dd txd rxd +12 c f c g cs/lwake i/o fault/ txe i/o 43v (5) 1k +12 master node only +12 220 k wake-up note 1: see figure 2-3 for correct capacity and esr for stable operation. 2: c f is the filter capacitor for the external voltage supply. 3: this diode is only needed if cs/lwake is connected to a 12v supply. 4: transient suppressor diode. vclamp l = 43v. 5: these components are required for additional load dump protection above 43v. 6: required if cpu does not have internal pull-up. (3) r tp (5) 100 pf int or mclr reset v dd (6) lin bus mcp202x master c 1k v bb slave 1 c slave 2 c slave n <16 c 40m + return lin bus lin bus mcp202x lin bus mcp202x lin bus mcp202x mcp2021/2/1p/2p ds22018f-page 16 ? 2005-2012 microchip technology inc. 1.6 internal voltage regulator 1.6.1 5.0v regulator the mcp2021 has a low-drop-out voltage, positive reg- ulator capable of supplying 5.00 v dc 3% at up to 50 ma of load current over the entire operating temper- ature range of -40c to +125c. with a load current of 50 ma, the minimum input to output voltage differential required for the output to remain in regulation is typi- cally +0.5v (+1v maximum over the full operating tem- perature range). quiescent current is less than 100 a with a full 50 ma load current when the input to output voltage differential is greater than +3.00v. the regulator requires an external output bypass capacitor for stability. see figure 2-3 for correct capacity and esr for stable operation. designed for automotive applications, the regulator will protect itself from double-battery jumps and up to +43v load dump transients. the voltage regulator has both short-circuit and thermal-shut-down protection built in. regarding the correlation between v bb , v reg and i dd , please refer to figure 1-10 through figure 1-12 . when the input voltage (v bb ) drops below the differential needed to provide stable regulation, the output v reg will track the input down to approximately 3.5v, at which point the regulator will turn off. this will allow microcontrollers with internal por circuits to generate a clean arming of the por trip point. the mcp2021 will then monitor v bb and turn on the regulator when v bb rises above 5.75, again. when the input voltage (v bb ) drops below the differen- tial needed to provide stable regulation, the output v reg ) will track the input down to approximately +4.25v. the regulator will turn off the output at this point. this will allow pic ? microcontrollers with internal por circuits to generate a clean arming of the por trip point. the regulator output will stay off until v bb is above +5.75 v dc . in the start phase, the device must detect at least 5.75v to initiate operation during power up. in the power- down mode, the v bb monitor will be turned off. the regulator has a thermal shutdown. if the thermal protection circuit detects an overtemperature condition, and the signals t xd and rxd are low, or t xd is high, the regulator will shut down. the recovery from the thermal shutdown is equal to adequate cooling time. figure 1-9: voltage regulator block diagram. note: the regulator has an overload current limiting of approximately 100 ma. during a short circuit, the v reg is monitored. if v reg is lower than 3.5v, the v reg will turn off. after a recovery time of about three milliseconds, the v reg will be checked again. if there is no short circuit (v reg >3.5v), the v reg will be switched back on. pass element sampling network buffer v reg v bb v ss fast transient loop v ref ? 2005-2012 microchip technology inc. ds22018f-page 17 mcp2021/2/1p/2p 1.6.2 3.3v regulator a metal option provides for a alternate 3.30 v dc 3% at up to 50 ma of load current over the entire operating temperature range of -40c to +125c. all specifications given above for the 5.0v operation apply except for any difference noted here. the same input tracking of 4.25v applies the 3.3v regulator. figure 1-10: voltage regulator output on por. note: the regulator has an overload current limiting of approximately 100 ma. if v reg is lower than 2.5v, the v reg will turn off. note 1: start-up, v bb < 5.75v, regulator off. 2: v bb > 5.75v, regulator on. 3: v bb 5.5v, regulator tracks v bb . 4: v bb < 4.25v, regulator will turn off. 5.0 3.5 3 0 (1) (2) (3) t 0 t 6 2 8 4 v bb v v reg v mcp2021/2/1p/2p ds22018f-page 18 ? 2005-2012 microchip technology inc. figure 1-11: voltage regulator output on power dip. note 1: voltage regulator on. 2: v bb 5.5v, regulator tracks v bb until v bb < 4.25v. 3: v reg < 3.5v, regulator is off. 4: v bb > 5.75v, regulator on. 5 3.5 3 0 (1) (2) (3) t 0 t 6 2 8 4 3.5 12 (4) 4 v bb v v reg v ? 2005-2012 microchip technology inc. ds22018f-page 19 mcp2021/2/1p/2p figure 1-12: voltage regulator output on overcurrent situation. 1.7 icsp? considerations the following should be considered when the mcp2021/2/1p/2p is connected to pins supporting in-circuit programming: ? power used for programming the microcontroller can be supplied from the programmer or from the mcp2021/2/1p/2p. ? the voltage on v reg should not exceed the maximum output voltage of v reg . note 1: i reg less than 50 ma, regulator on. 2: after i reg exceeds i reg max, voltage regulator output will be reduced until v reg off is reached. 5.0 3.5 3 0 (1) (2) t 0 t 50 6 i reg ma v reg v mcp2021/2/1p/2p ds22018f-page 20 ? 2005-2012 microchip technology inc. notes: ? 2005-2012 microchip technology inc. ds22018f-page 21 mcp2021/2/1p/2p 2.0 electrical characteristics 2.1 absolute maximum ratings? v in dc voltage on rxd and txd ..................................................................................................... ... -0.3 to v reg +0.3v v in dc voltage on fault and reset .........................................................................................................-0.3 to +5.5v v in dc voltage on cs/lwake........................................................................................................ ...............-0.3 to +43v v bb battery voltage, non-operating (lin bus recessive, no regulator load, t < 60s) .....................................-0.3 to +43 v v bb battery voltage, transient iso 7637 test 1 ................................................................................... ...................-200v v bb battery voltage, transient iso 7637 test 2a .................................................................................. .................+150v v bb battery voltage, transient iso 7637 test 3a .................................................................................. ..................-300v v bb battery voltage, transient iso 7637 test 3b .................................................................................. .................+200v v bb battery voltage, continuous ................................................................................................... .................-0.3 to +30v v lbus bus voltage, continuous....................................................................................................... ................-18 to +30v v lbus bus voltage, transient ( note 1 )............................................................................................................-27 to +43v i lbus bus short circuit current limit ............................................................................................... .....................200 ma esd protection on lin, v bb (iec 61000-4-2, 330 ohm, 150 pf) ( note 3 ) .............................................. minimum 9 kv esd protection on lin, v bb (charge device model) ( note 2 )..............................................................................1500v esd protection on lin, vbb (human body model, 1 kohm, 100 pf) ( note 4 ) ....................................................... 8 kv esd protection on lin, v bb (machine model) ( note 2 ) ..........................................................................................800v esd protection on all other pins (human body model) ( note 2 ) ............................................................................ > 4 kv maximum junction temperature ................................................................................................... .......................... 150 c storage temperature ............................................................................................................ ...................... -55 to +150 c note 1: iso 7637/1 load dump compliant (t < 500 ms). 2: according to jesd22-a114-b. 3: according to ibee, without bus filter. 4: limited by test equipment. ? notice : stresses above those listed under ?maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. mcp2021/2/1p/2p ds22018f-page 22 ? 2005-2012 microchip technology inc. 2.2 dc specifications dc specifications electrical characteristics: unless otherwise indicated, all limits are specified for: v bb = 6.0v to 18.0v t a = -40c to +125c c loadreg = 10 f parameter sym min. typ. max. units conditions power v bb quiescent operating current i bbq 115 210 a i out = 0 ma, l bus recessive ? 120 215 a v out = 3.3v v bb transmitter-off current i bbto ? 90 190 a with v reg on, transmitter off, receiver on, fault /txe = v il , cs = v ih ?95210av out = 3.3v v bb power-down current i bbpd ?16 26 awith v reg powered-off, receiver on and transmitter off, fault /txe = v ih , txd = v ih , cs = v il ) v bb current with v ss floating i bbnognd -1 ? 1mav bb = 12v, gnd to v bb , vlin = 0-18v microcontroller interface high level input voltage (txd, fault /txe) v ih 2.0 or (0.25v reg +0.8) ? v reg +0.3 v low level input voltage (txd, fault /txe) v il -0.3 ? 0.15 v reg v high level input current (txd, fault /txe) i ih -2.5 ? ? a input voltage = 0.8*v reg low level input current (txd, fault /txe) i il -10 ? ? a input voltage = 0.2*v reg pull-up current on input (txd) i pu txd -3.0 ? ? a ~800 k internal pull-up to v reg @ v ih = 0.7*v reg high level input voltage (cs/lwake) v ih 0.7v reg ? v bb v through a current-limiting resistor low level input voltage (cs/lwake) v il -0.3 ? 0.3v reg v high level input current (cs/lwake) i ih ? ? 7.0 a input voltage = 0.8*v reg low level input current (cs/lwake) i il ? ? 3.0 a input voltage = 0.2*v reg pull-down current on input (cs/lwake) i pdcs ? ? 6.0 a ~1.3m internal pull-down to v ss @ v ih = 3.5v note 1: internal current limited. 2.0 ms maximum recovery time (r lbus = 0 , tx = 0.4 v reg , v lbus = v bb ). 2: for design guidance only, not tested. 3: node has to sustain the current that can flow under this condition; bus must be operational under this condition. ? 2005-2012 microchip technology inc. ds22018f-page 23 mcp2021/2/1p/2p bus interface high level input voltage v ih (l bus )0.6 v bb ? 18 v recessive state low level input voltage v il (l bus )-8 ? 0.4 v bb v dominant state input hysteresis v hys ?? 0.175 v bb vv ih (l bus ) - v il (l bus ) low level output current i ol (l bus )40 ? 200 ma output voltage = 0.1 v bb , v bb = 12v pull-up current on input i pu (l bus )5 ? 180 a ~30 k internal pull-up @ v ih (l bus ) = 0.7 v bb short circuit current limit i sc 50 ? 200 ma (note 1) high level output voltage v oh (l bus )0.8 v bb ? v bb vv oh (l bus ) must be at least 0.8 v bb low level output voltage v ollo (l bus ) ? ? 0.2 v bb v input leakage current (at the receiver during dominant bus level) i bus _ pas _ dom -1 ? ? ma driver off, v bus = 0v, v bat = 12v leakage current (disconnected from ground) i bus _ no _ gnd -1 ? +1 ma gnd device = v bat , 0v < v bus < 18v, v bat = 12v leakage current (disconnected from v bat ) i bus ? ? 10 a v bat = gnd, 0 < v bus < 18v, t a = -40 c to +85 c (note 3) 50 a t a = +85 c to +125 c receiver center voltage v bus _ cnt 0.475 v bb 0.5 v bb 0.525 v bb vv bus _ cnt = (v il (l bus ) + v ih (l bus ))/2 slave termination rslave 20 30 47 k 2.2 dc specifications (continued) dc specifications electrical characteristics: unless otherwise indicated, all limits are specified for: v bb = 6.0v to 18.0v t a = -40c to +125c c loadreg = 10 f parameter sym min. typ. max. units conditions note 1: internal current limited. 2.0 ms maximum recovery time (r lbus = 0 , tx = 0.4 v reg , v lbus = v bb ). 2: for design guidance only, not tested. 3: node has to sustain the current that can flow under this condition; bus must be operational under this condition. mcp2021/2/1p/2p ds22018f-page 24 ? 2005-2012 microchip technology inc. 2.2 dc specification (continued) figure 2-1: mcp2021-500 safe operating range. dc specifications electrical characteristics: unless otherwise indicated, all limits are specified for: v bb = 6.0v to 18.0v t a = -40c to +125c c loadreg = 10 f parameter sym min. typ. max. units conditions voltage regulator - 5.0v output voltage v out 4.85 5.00 5.15 v 0 ma < i out < 50 ma, load regulation v out 2?1050mv5ma < i out < 50 ma refer to section 1.6 ?internal voltage regulator? quiescent current i vrq ?? 25 ai out = 0 ma, (note 2) power supply ripple reject psrr ? ? 50 db 1 v pp @10-20 khz c load = 10 f, i load = 50 ma output noise voltage en ? ? 100 v rms 10 hz ? 40 mhz c filter = 10 f, c bp = 0.1 f, c load 10 f, i load = 50 ma shutdown voltage v sd 3.5 ? 4.0 v see figure 1-8 input voltage to maintain regulation v bb 6.0 ? 18.0 v input voltage to turn off output v off 4.0 ? 4.5 v input voltage to turn on output v on 5.5 ? 6.0 v note 1: internal current limited. 2.0 ms maximum recovery time (r lbus = 0 , tx = 0.4 v reg , v lbus = v bb ). 2: for design guidance only, not tested. 3: node has to sustain the current that can flow under this condition; bus must be operational under this condition. 0 10 20 30 40 50 60 -40 -34 -28 -22 -16 -10 -4 2 8 14 20 26 32 38 44 50 56 62 68 74 80 86 92 98 104 110 116 122 temperature (c) voltage regulator load (ma) 18v dfn 18v soic 12v soic 12v dfn ? 2005-2012 microchip technology inc. ds22018f-page 25 mcp2021/2/1p/2p 2.2 dc specification (continued) figure 2-2: mcp2021-330 safe operating range. dc specifications electrical characteristics: unless otherwise indicated, all limits are specified for: v bb = 6.0v to 18.0v t a = -40c to +125c c loadreg = 10 f parameter sym min. typ. max. units conditions voltage regulator - 3.3v output voltage v out 3.20 3.30 3.40 v 0 ma < i out < 50 ma line regulation v out 1?1050mvi out = 1 ma, 6.0v < v bb < 18v load regulation v out 2?1050mv5ma < i out < 50 ma refer to section 1.6 ?internal voltage regulator? quiescent current i vrq ?? 25 ai out = 0 ma, (note 2) power supply ripple reject psrr ? ? 50 db 1 v pp @10-20 khz c load = 10 f, i load = 50 ma output noise voltage en ? ? 100 v rms / hz 10 hz ? 40 mhz c filter = 10 f, c bp = 0.1 f c load = 10 f, i load = 50 ma shutdown voltage v sd 2.5 ? 2.7 v see figure 1-8 input voltage to maintain regulation v bb 6.0 ? 18.0 v input voltage to turn off output v off 4.0 ? 4.5 v input voltage to turn on output v on 5.5 ? 6.0 v note 1: internal current limited. 2.0 ms maximum recovery time (r lbus = 0 , tx = 0.4 v reg , v lbus = v bb ). 2: for design guidance only, not tested. 3: node has to sustain the current that can flow under this condition; bus must be operational under this condition. 0 10 20 30 40 50 60 -40 -34 -28 -22 -16 -10 -4 2 8 14 20 26 32 38 44 50 56 62 68 74 80 86 92 98 104 110 116 122 temperature (c) voltage regulator load (ma) 18v dfn 18v soic 12v soic 12v dfn mcp2021/2/1p/2p ds22018f-page 26 ? 2005-2012 microchip technology inc. figure 2-3: esr curves for load capacitor selection. load capacitor [uf] esr curves esr [ohm] 10 1 0.1 0.01 0.001 10 100 1000 1 0.1 instable instable instable stable only with tantalum or electrolytic cap. stable with tantalum, electrolytic and ceramic cap. ? 2005-2012 microchip technology inc. ds22018f-page 27 mcp2021/2/1p/2p 2.3 ac specification ac characteristics v bb = 6.0v to 18.0v; t a = -40c to +125c parameter sym min. typ. max. units test conditions bus interface - constant slope time parameters slope rising and falling edges t slope 3.5 ? 22.5 s 7.3v <= v bb <= 18v propagation delay of transmitter t transpd ??4.0st transpd = max (t transpdr or t transpdf ) propagation delay of receiver t recpd ??6.0st recpd = max (t recpdr or t recpdf ) symmetry of propagation delay of receiver rising edge w.r.t. falling edge t recsym -2.0 ? 2.0 s t recsym = max (t recpdf - t recpdr ) symmetry of propagation delay of transmitter rising edge w.r.t. falling edge t transsym -2.0 ? 2.0 s t transsym = max (t transpdf - t transpdr ) time to sample of fault/ txe for bus conflict reporting t fault ??32.5st fault = max (t transpd + t slope + t recpd ) duty cycle 1 @20.0 kbit/sec 39.6 ? ? %t bit c bus ;r bus conditions: 1nf; 1k | 6.8 nf; 660 | 10 nf; 500 th rec ( max ) = 0.744 x v bb , th dom ( max ) = 0.581 x v bb , v bb =7.0v - 18v; t bit = 50 s. d1 = t bus _ rec ( min ) / 2 x t bit ) duty cycle 2 @20.0 kbit/sec ? ? 58.1 %t bit c bus ;r bus conditions: 1nf; 1k | 6.8 nf; 660 | 10 nf; 500 th rec ( max ) = 0.284 x v bb , th dom ( max ) = 0.422 x v bb , v bb =7.6v - 18v; t bit = 50 s. d2 = t bus _ rec ( max ) / 2 x t bit ) duty cycle 3 @10.4 kbit/sec 41.7 ? ? %t bit c bus ;r bus conditions: 1nf; 1k | 6.8 nf; 660 | 10 nf; 500 th rec ( max ) = 0.778 x v bb , th dom ( max ) = 0.616 x v bb , v bb =7.0v - 18v; t bit = 96 s. d3 = t bus _ rec ( min ) / 2 x t bit ) duty cycle 4 @10.4 kbit/sec ? ? 59.0 %t bit c bus ;r bus conditions: 1nf; 1k | 6.8 nf; 660 | 10 nf; 500 th rec ( max ) = 0.251 x v bb , th dom ( max ) = 0.389 x v bb , v bb =7.6v - 18v; t bit = 96 s. d4 = t bus _ rec ( max ) / 2 x t bit ) mcp2021/2/1p/2p ds22018f-page 28 ? 2005-2012 microchip technology inc. 2.4 thermal specifications voltage regulator bus activity debounce time t bdb 5 10 20 s bus debounce time bus activity to voltage regulator enabled t bactve 100 250 500 s after bus debounce time voltage regulator enabled to ready t vevr ? ? 1200 s (note 1) chip select to operation ready t csor ? ? 500 s (note 1) chip select to power-down t cspd ??80s short-circuit to shut-down t shutdown 20 ? 100 s reset timing v reg ok detect to reset inactive t rpu ??10.0s v reg ok detect to reset active t rpd ??10.0s note 1: time depends on external capacitance and load. thermal characteristics parameter symbol typ max units test conditions recovery temperature recovery +140 ? c shutdown temperature shutdown +150 ? c short circuit recovery time t therm 1.5 5.0 ms thermal package resistances thermal resistance, 8l-dfn ja 35.7 ? c/w thermal resistance, 8l-pdip ja 89.3 ? c/w thermal resistance, 8l-soic ja 149.5 ? c/w thermal resistance, 14l-pdip ja 70 ? c/w thermal resistance, 14l-soic ja 95.3 ? c/w thermal resistance, 14l-tssop ja 100 ? c/w note 1: the maximum power dissipation is a function of t jmax , ja and ambient temperature t a . the maximum allowable power dissipation at an ambient temperature is p d = (t jmax - t a ) ja . if this dissipation is exceeded, the die temperature will rise above 150 c and the mcp2021 will go into thermal shutdown. 2.3 ac specification (continued) ac characteristics v bb = 6.0v to 18.0v; t a = -40c to +125c parameter sym min. typ. max. units test conditions ? 2005-2012 microchip technology inc. ds22018f-page 29 mcp2021/2/1p/2p 2.5 timing diagrams and specifications figure 2-4: bus timing diagram. figure 2-5: regulator cs/lwake timing diagram. .95v lbus .0.4v bb t transpdr t recpdr t transpdf t recpdf txd l bus rxd internal txd/rxd compare fault sampling t fault t fault fault /txe output stable stable stable match match match match match hold value hold value 50% 50% .50v bb 50% 50% 0.0v t cspd t csor cs/lwake v out v reg mcp2021/2/1p/2p ds22018f-page 30 ? 2005-2012 microchip technology inc. figure 2-6: regulator bus wake timing diagram. figure 2-7: reset timing diagram. v out l bus 0.4v bb t vevr v reg t bdb + t bactve reset v bb 6.0v v reg 5.0v 5.0v 4.0v 3.5v t rpu t rpd t rpd t rp u ? 2005-2012 microchip technology inc. ds22018f-page 31 mcp2021/2/1p/2p figure 2-8: cs/lwake to reset timing diagram. figure 2-9: typical i bbq vs. temperature. t cspd t csor cs/lwake v out v reg reset t rpu 0 0.05 0.1 0.15 0.2 -40c 25c 85c 125c temperature (c) ibbq ma vbb = 6v vbb = 7.3v vbb = 12v vbb = 14.4v vbb = 18v mcp2021/2/1p/2p ds22018f-page 32 ? 2005-2012 microchip technology inc. figure 2-10: typical i bbto vs temperature. figure 2-11: typical i bbpd vs. temperature. 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 -40c 25c 85c 125c temperature (c) ma vbb = 6v vbb = 7.3v vbb = 12v vbb = 14.4v vbb = 18v 0 0.005 0.01 0.015 0.02 0.025 -40c 25c 85c 125c temperature (c) ipd (ma) vbb = 6v vbb = 7.3v vbb = 12v vbb = 14.4v vbb = 18v ? 2005-2012 microchip technology inc. ds22018f-page 33 mcp2021/2/1p/2p 3.0 packaging information 3.1 package marking information legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e pin 1 nnn pin 1 8-lead dfn-s (6x5x0.9 mm) example 8-lead dfn (4x4x0.9 mm) example yyww nnn xxxxxx xxxxxx pin 1 pin 1 mcp2021 202150 8-lead pdip (300 mil) example xxxxxxxx xxxxxnnn yyww mcp2021 mcp2021p 2021500 2021p500 202150 e/md 1033 256 2021500 e/mf 1033 256 3 3 2021500 e/p 256 1033 3 mcp2021 mcp2021p 2021500 2021p50 mcp2021/2/1p/2p ds22018f-page 34 ? 2005-2012 microchip technology inc. 3.1 package marking information (continued) mcp2022 mcp2022p mcp2022-500 2022p-500 mcp2022 mcp2022p mcp2022-500 mcp2022p-500 8-lead soic (3.90 mm) example nnn mcp2021 mcp2021p 2021500e 2021p50e 2021500e sn 1033 256 3 14-lead pdip (300 mil) example 14-lead soic (3.90 mm) example legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e mcp2022-500 e/p 1033256 3 mcp2022-500 e/sl 1033256 3 ? 2005-2012 microchip technology inc. ds22018f-page 35 mcp2021/2/1p/2p 3.1 package marking information (continued) 14-lead tssop (4.4 mm) example yyww nnn xxxxxxxx mcp2022 mcp2022p 2022500e 2022p50e legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 2022500e 1033 256 mcp2021/2/1p/2p ds22018f-page 36 ? 2005-2012 microchip technology inc. 8-lead plastic dual flat, no lead package (md) C 4x4x0.9 mm body [dfn] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. package may have one or more exposed tie bars at ends. 3. package is saw singulated. 4. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 8 pitch e 0.80 bsc overall height a 0.80 0.90 1.00 standoff a1 0.00 0.02 0.05 contact thickness a3 0.20 ref overall length d 4.00 bsc exposed pad width e2 0.00 2.20 2.80 overall width e 4.00 bsc exposed pad length d2 0.00 3.00 3.60 contact width b 0.25 0.30 0.35 contact length l 0.30 0.55 0.65 contact-to-exposed pad k 0.20 ? ? d n e note 1 1 2 a 3 a a1 note 2 note 1 d2 1 2 e2 l n e b k exposed pad to p view b otto m view microchip technology drawing c04-131c ? 2005-2012 microchip technology inc. ds22018f-page 37 mcp2021/2/1p/2p d mcp2021/2/1p/2p ds22018f-page 38 ? 2005-2012 microchip technology inc. 8-lead plastic dual flat, no lead package (mf) C 6x5 mm body [dfn-s] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. package may have one or more exposed tie bars at ends. 3. package is saw singulated. 4. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 8 pitch e 1.27 bsc overall height a 0.80 0.85 1.00 standoff a1 0.00 0.01 0.05 contact thickness a3 0.20 ref overall length d 5.00 bsc overall width e 6.00 bsc exposed pad length d2 3.90 4.00 4.10 exposed pad width e2 2.20 2.30 2.40 contact width b 0.35 0.40 0.48 contact length l 0.50 0.60 0.75 contact-to-exposed pad k 0.20 C C note 2 a1 a a3 note 1 12 e n d exposed pad note 1 2 1 e2 l n e b k b otto m view to p view d2 microchip technology drawing c04-122 b ? 2005-2012 microchip technology inc. ds22018f-page 39 mcp2021/2/1p/2p mcp2021/2/1p/2p ds22018f-page 40 ? 2005-2012 microchip technology inc. 8-lead plastic dual i n-line (p) C 300 mil body [pd i p] notes: 1. pin 1 visual index feature may vary, but must be located with the hatched area. 2. significant characteristic. 3. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010" per side. 4. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units inches dimension limits min nom max number of pins n 8 pitch e .100 bsc top to seating plane a C C .210 molded package thickness a2 .115 .130 .195 base to seating plane a1 .015 C C shoulder to shoulder width e .290 .310 .325 molded package width e1 .240 .250 .280 overall length d .348 .365 .400 tip to seating plane l .115 .130 .150 lead thickness c .008 .010 .015 upper lead width b1 .040 .060 .070 lower lead width b .014 .018 .022 overall row spacing eb C C .430 n e1 note 1 d 12 3 a a1 a2 l b1 b e e eb c microchip technology drawing c04-018b ? 2005-2012 microchip technology inc. ds22018f-page 41 mcp2021/2/1p/2p 8-lead plastic small o utline (sn) C narrow, 3.90 mm body [s oi c] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. significant characteristic. 3. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15 mm per side. 4. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 8 pitch e 1.27 bsc overall height a C C 1.75 molded package thickness a2 1.25 C C standoff a1 0.10 C 0.25 overall width e 6.00 bsc molded package width e1 3.90 bsc overall length d 4.90 bsc chamfer (optional) h 0.25 C 0.50 foot length l 0.40 C 1.27 footprint l1 1.04 ref foot angle 0 C 8 lead thickness c 0.17 C 0.25 lead width b 0.31 C 0.51 mold draft angle top 5 C 15 mold draft angle bottom 5 C 15 d n e e e1 note 1 12 3 b a a1 a2 l l1 c h h microchip technology drawing c04-057b mcp2021/2/1p/2p ds22018f-page 42 ? 2005-2012 microchip technology inc. ? 2005-2012 microchip technology inc. ds22018f-page 43 mcp2021/2/1p/2p 14-lead plastic dual i n-line (p) C 300 mil body [pd i p] notes: 1. pin 1 visual index feature may vary, but must be located with the hatched area. 2. significant characteristic. 3. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010" per side. 4. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units inches dimension limits min nom max number of pins n 14 pitch e .100 bsc top to seating plane a C C .210 molded package thickness a2 .115 .130 .195 base to seating plane a1 .015 C C shoulder to shoulder width e .290 .310 .325 molded package width e1 .240 .250 .280 overall length d .735 .750 .775 tip to seating plane l .115 .130 .150 lead thickness c .008 .010 .015 upper lead width b1 .045 .060 .070 lower lead width b .014 .018 .022 overall row spacing eb C C .430 n e1 d note 1 12 3 e c eb a2 l a a1 b1 be microchip technology drawing c04-005b mcp2021/2/1p/2p ds22018f-page 44 ? 2005-2012 microchip technology inc. 14-lead plastic small o utline (sl) C narrow, 3.90 mm body [s oi c] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. significant characteristic. 3. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15 mm per side. 4. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 14 pitch e 1.27 bsc overall height a C C 1.75 molded package thickness a2 1.25 C C standoff a1 0.10 C 0.25 overall width e 6.00 bsc molded package width e1 3.90 bsc overall length d 8.65 bsc chamfer (optional) h 0.25 C 0.50 foot length l 0.40 C 1.27 footprint l1 1.04 ref foot angle 0 C 8 lead thickness c 0.17 C 0.25 lead width b 0.31 C 0.51 mold draft angle top 5 C 15 mold draft angle bottom 5 C 15 note 1 n d e e1 1 23 b e a a1 a2 l l1 c h h microchip technology drawing c04-065b ? 2005-2012 microchip technology inc. ds22018f-page 45 mcp2021/2/1p/2p mcp2021/2/1p/2p ds22018f-page 46 ? 2005-2012 microchip technology inc. 14-lead plastic t hin shrink small o utline (s t ) C 4.4 mm body [ t ss o p] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15 mm per side. 3. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 14 pitch e 0.65 bsc overall height a C C 1.20 molded package thickness a2 0.80 1.00 1.05 standoff a1 0.05 C 0.15 overall width e 6.40 bsc molded package width e1 4.30 4.40 4.50 molded package length d 4.90 5.00 5.10 foot length l 0.45 0.60 0.75 footprint l1 1.00 ref foot angle 0 C 8 lead thickness c 0.09 C 0.20 lead width b 0.19 C 0.30 note 1 d n e e1 1 2 e b c a a1 a2 l1 l microchip technology drawing c04-087b ? 2005-2012 microchip technology inc. ds22018f-page 47 mcp2021/2/1p/2p appendix a: revision history revision f (january 2012) the following modifications were made to this data sheet: added the mcp2021p and mcp2022p options and related information throughout the document. revision e (february 2009) the following is the list of modifications. 1. added example 1-7 and example 1-8. 2. updated section 1.4.9 ?reset? . 3. updated section 1.7 ?icsp? consider- ations? . 4. updated section 2.1 ?absolute maximum ratings?? . 5. updated section 2.2 ?dc specifications? and section 2.3 ?ac specification? . 6. added figure 2-3: ?esr curves for load capacitor selection.? . 7. updated the product identification system section. revision d (july 2008) the following is the list of modifications. 1. updated esd specs under ?absolute dc?. 2. updated notes in example 1-1. 3. updated package outline drawings. revision c (april 2008) the following is the list of modifications. 1. added lin2.1 and j2602 compliance statement to features section. 2. added recommended rc network for cs/ lwake in example 1-1. 3. updated 2.1 absolute maximum ratings to reflect current test results. 4. updated 2.2 dc specifications and 2.3 ac specifications to reflect current production device. 5. added 8-lead soic landing pattern outline drawing. revision b (august 2007) the following is the list of modifications: 1. modified block diagram on page 2. 2. section 1.3.5 ?transmitter-off mode? : deleted text in 1st paragraph. 3. example 1-6 : removed +5v notation. 4. section 1.4 ?pin descriptions? : removed 10- pin dfn, msop column from table. 5. section 1.4.8 ?fault/txe? : deleted text from 2nd paragraph. 6. section 3.0 ?packaging information? : added 8-lead 4x4 and 6x5 dfn and 14-lead tssop packages. updated package outline drawings and added drawings for 8-lead dfn and 14-lead tssop drawings. revision a (november 2005) original release of this document. mcp2021/2/1p/2p ds22018f-page 48 ? 2005-2012 microchip technology inc. notes: ? 2005-2012 microchip technology inc. ds22018f-page 49 mcp2021/2/1p/2p product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . device: mcp2021: lin transceiver with voltage regulator; wakes up on dominant level of lin bus. mcp2021t: lin transceiver with voltage regulator; wakes up on dominant level of lin bus. (tape and reel) (soic only) mcp2022: lin transceiver with voltage regulator, and reset pin; wakes up on dominant level of lin bus. mcp2022t: lin transceiver with voltage regulator, and reset pin; wakes up on dominant level of lin bus. (tape and reel) (soic only) mcp2021p: lin transceiver with voltage regulator; wakes up at a falling edge of lin bus level. mcp2021pt: lin transceiver with voltage regulator; wakes up at a falling edge of lin bus level (tape and reel) (soic only) mcp2022p: lin transceiver with voltage regulator, and reset pin; wakes up at a falling edge of lin bus level. mcp2022pt: lin transceiver with voltage regulator, and reset pin; wakes up at a falling edge of lin bus level. (tape and reel) (soic only) temperature range: e = -40c to +125c package: md = plastic micro small outline (4x4), 8-lead mf = plastic micro small outline (6x5), 8-lead p = plastic dip (300 mil body), 8-lead, 14-lead sn = plastic soic, (150 mil body), 8-lead sl = plastic soic, (150 mil body), 14-lead st = plastic thin shrink small outline, 14-lead part no. ?x /xx package temperature range device examples: a) mcp2021-330e/sn: 3.3v, 8l-soic pkg. b) mcp2021-330e/p: 3.3v, 8l-pdip pkg. c) mcp2021-500e/mf: 5.0v, 8l-dfn-s pkg. d) mcp2021-500e/sn: 5.0v, 8l-soic pkg. e) mcp2021-500e/md: 5.0v, 8l-dfn pkg. f) mcp2021-330e/p: 5.0v, 8l-pdip pkg. g) mcp2021t-330e/sn: tape and reel, 3.3v, 8l-soic pkg. h) mcp2021t-500e/md: tape and reel, 5.0v, 8l-dfn pkg. i) mcp2021t-500e/sn: tape and reel, 5.0v, 8l-soic pkg. a) mcp2022-330e/sl: 3.3v, 14l-soic pkg. b) mcp2022-330e/p: 3.3v, 14l-pdip pkg. c) mcp2022-500e/sl: 5.0v, 14l-soic pkg. d) mcp2022-500e/p: 5.0v, 14l-pdip pkg. e) mcp2022t-330e/sl: tape and reel, 3.3v, 14l-soic pkg. f) mcp2022t-500e/sl: tape and reel, 5.0v, 14l-soic pkg. g) mcp2022t-500e/st: tape and reel, 5.0v, 14l-tssop pkg. mcp2021/2/1p/2p ds22018f-page 50 ? 2005-2012 microchip technology inc. notes: ? 2005-2012 microchip technology inc. ds22018f-page 51 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, app lication maestro, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, total endurance, tsharc, uniwindriver, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2005-2012, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-61341-884-0 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. ds22018f-page 52 ? 2005-2012 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://www.microchip.com/ support web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 cleveland independence, oh tel: 216-447-0464 fax: 216-447-0643 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 indianapolis noblesville, in tel: 317-773-8323 fax: 317-773-5453 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8569-7000 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - chongqing tel: 86-23-8980-9588 fax: 86-23-8980-9500 china - hangzhou tel: 86-571-2819-3187 fax: 86-571-2819-3189 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 asia/pacific india - bangalore tel: 91-80-3090-4444 fax: 91-80-3090-4123 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - osaka tel: 81-66-152-7160 fax: 81-66-152-9310 japan - yokohama tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-5778-366 fax: 886-3-5770-955 taiwan - kaohsiung tel: 886-7-536-4818 fax: 886-7-330-9305 taiwan - taipei tel: 886-2-2500-6610 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 worldwide sales and service 11/29/11 |
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