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1 ? isl6314 single-phase buck pwm controller with integrated mosfet drivers for intel vr11 and amd applications the isl6314 single-phase pwm control ic provides a precision voltage regulation system for advanced microprocessors. this contro ller ic maintains the same features as the multi-phase pr oduct family, but reduces the output to a single-phase, for lower current systems. by reducing the number of external parts, this integration is optimized for a cost and space saving power management solution. one outstanding feature of this controller ic is its multi-processor compatibility, allowing it to work with both intel and amd microprocessors. included are programmable vid codes for intel vr11 as well as amd 5-bit and 6-bit dac tables. a circuit is provided for remote voltage sensing, compensating for any potential difference between remote and local grounds. the output voltage can also be positively or negatively offset through the use of a single external resistor. another unique feature of the isl6314 is the addition of a circuit that allows optimizing compensation to be added for flatter load transient response and well controlled dynamic vid response. the isl6314 also includes adv anced control loop features for optimal transient response to load apply and removal. one of these features is highly accurate, fully differential, continuous dcr current sensin g for load line programming. active pulse positioning (app) and adaptive phase alignment (apa) are two other unique features, allowing for quicker initial response to high di/dt load transients; the number of output bulk capacitors can be reduced, helping to reduce cost. protection features of this c ontroller ic include a set of sophisticated overvoltage, un dervoltage, and overcurrent protection. furthermore, the isl6314 includes protection against an open circuit on the remote sensing inputs. combined, these features provid e advanced protection for the microprocessor and power system. features ? integrated-driver single- phase power conversion ? precision core voltage regulation - differential remote voltage sensing - 0.5% system accuracy over-temperature - adjustable reference-voltage offset ? optimal transient response - adaptive phase alignment (apa) - active pulse positioning (app) modulation ? fully differential, continuous dcr current sensing - accurate load line programming ? variable gate drive bias: 5v to 12v ? multi-processor compatible - intel vr11 mode of operation - amd mode of operation ? microprocessor voltag e identification inputs - 8-bit dac - selectable between intel vr11, amd 5-bit, and amd 6-bit dac tables - dynamic vid technology ? overcurrent protection ? multi-tiered overvoltage protection ? digital soft-start ? selectable operation frequency up to 1.0mhz ? pb-free (rohs compliant) ordering information part number (note) part marking temp. range (c) package (pb-free) pkg. dwg. # isl6314crz* isl6314 crz 0 to +70 32 ld 5x5 qfn l32.5x5b isl6314irz* isl6314 irz -40 to +85 32 ld 5x5 qfn l32.5x5b *add ?-t? suffix for tape and reel. pl ease refer to tb347 for details on reel specifications. note: these intersil pb-free plas tic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-f ree products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. data sheet caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2007, 2009. all rights reserved all other trademarks mentioned are the property of their respective owners. october 8, 2009 fn6455.2
2 fn6455.2 october 8, 2009 pinout isl6314 (32 ld qfn) top view isl6314 integrated dr iver block diagram comp lgate vid1 vid3 vid4 phase vid0 vid2 vid5 vid6 ugate boot nc vcc pvcc dvc fb vdiff vsen ocset iseno isen- isen+ en vid7 pgood ss fs ref ofs apa rgnd 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10111213141516 33 gnd through shoot- protection boot ugate phase lgate logic control gate pvcc 10k pwm soft-start and fault logic 20k isl6314 isl6314
3 fn6455.2 october 8, 2009 block diagram isen amp 100a e/a ref fb ofs comp boot ugate phase lgate pwm apa dvc 2k pvcc vcc ss fs isen- isen+ rgnd vsen vdiff en gnd ocset pgood iseno 100a oc x1 soft-start and fault logic reset power-on 0.85v overvoltage detection logic undervoltage detection logic open sense line detect driver mosfet clock and generator modulator waveform dynamic vid d/a vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 mode/dac select fs/droop select offset adaptive phase allignment circuitry fsd fsd x2 isl6314 isl6314
4 fn6455.2 october 8, 2009 typical application - isl6314 vid4 vid5 pgood vid3 vid2 vid1 vcc isl6314 vid0 fs ofs ref load en gnd vid6 vid7 ss +5v fb comp vsen rgnd vin phase ugate boot lgate pvcc apa ocset isen- iseno isen+ vdiff dvc r comp c comp r s r ocset pvcc typical applications 1. pvcc = 12v; vin =12v; 2. pvcc = 5v; vin = 19v; other combinations are also possible isl6314 isl6314
5 fn6455.2 october 8, 2009 typical application - isl6314 with ntc thermal compensation vid4 vid5 pgood vid3 vid2 vid1 vcc isl6314 vid0 fs ofs ref load en gnd vid6 vid7 ss +5v fb comp vsen rgnd +12v phase ugate boot lgate pvcc apa ocset isen- iseno isen+ vdiff dvc ntc place in close proximity r comp c comp r s r ocset isl6314 isl6314
6 fn6455.2 october 8, 2009 absolute m aximum ratings supply voltage, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6v supply voltage, pvcc . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +15v absolute boot voltage, v boot . . . . . . . . gnd - 0.3v to gnd + 36v phase voltage, v phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 8v (<400ns, 20j) to 30v (<200ns, v boot-phase = 5v) upper gate voltage, v ugate . . . . v phase - 0.3v to v boot + 0.3v v phase - 3.5v (<100ns pulse width, 2j) to v boot + 0.3v lower gate voltage, v lgate . . . . . . . . gnd - 0.3v to pvcc + 0.3v gnd - 5v (<100ns pulse width, 2j) to pvcc+ 0.3v input, output, or i/o voltage . . . . . . . . . gnd - 0.3v to vcc + 0.3v thermal information thermal resistance ja (c/w) jc (c/w) qfn package (notes 1, 2) . . . . . . . . . . 32 3.5 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . +150c maximum storage temperature range . . . . . . . . . .-65c to +150c pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp recommended operating conditions vcc supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5v 5% pvcc supply voltage . . . . . . . . . . . . . . . . . . . . . . . +5v to 12v 5% ambient temperature isl6314crz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0c to +70c isl6314irz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 2. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications recommended operating conditions, unless otherwise specif ied. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. tem perature limits established by characterization and are not production tested. parameter test conditions min typ max units bias supplies input bias supply current i vcc ; v cc = 5v; en = high, not switching; 911.416ma gate drive bias current - pvcc pin i pvcc ; pvcc = 12v; en = high, high, not switching 124ma v cc por (power-on reset) threshold v cc rising 4.25 4.38 4.50 v v cc falling 3.75 3.88 4.00 v pvcc por (power-on reset) threshold pvcc rising 4.25 4.38 4.50 v pvcc falling 3.75 3.88 4.00 v pwm modulator oscillator frequen cy accuracy, f sw (isl6314crz) r t = 100k ( 0.1%) 225 250 275 khz oscillator frequen cy accuracy, f sw (isl6314irz) r t = 100k ( 0.1%) 215 250 280 khz adjustment range of switching frequency (note 3) 0.08 - 1.0 mhz oscillator ramp amplitude, v p-p (note 3) - 1.50 - v control thresholds en rising threshold 0.84 0.86 0.88 v en hysteresis -110-mv reference and dac system accuracy (1.000v to 1.600v) -0.5 - 0.5 % system accuracy (0.600v to 1.000v) -1.0 - 1.0 % system accuracy (0.375v to 0.600v) -2.0 - 2.0 % vidx input low voltage (intel) pins vid0 to vid7 - - 0.4 v isl6314 isl6314
7 fn6455.2 october 8, 2009 vidx input high voltage (intel) pins vid0 to vid7 0.8 - - v vidx input low voltage (amd) pins vid0 to vid7 - - 0.8 v vidx input high voltage (amd) pins vid0 to vid7 1.4 - - v vidx pull-up current (intel) pins vid0 to vid7; vidx = 0v - -40 - a vidx pull-down current (amd) pins vid0 to vid7; vidx = 0.5v - 20 - a pin-adjustable offset ofs sink current accuracy (negative offset) r ofs = 32.4k from ofs to vcc 47.0 49.4 53.0 a ofs source current accuracy (positive offset) r ofs = 6.04k from ofs to gnd 47.0 49.7 53.0 a error amplifier dc gain r l = 10k to ground, (note 3) - 96 - db gain-bandwidth product c l = 100pf, r l = 10k to ground, (note 3) -40-mhz slew rate c l = 100pf, load = 400a, (note 3) -20-v/s maximum output voltage load = 1ma 3.90 4.20 - v minimum output voltage load = -1ma - 1.20 1.4 v soft-start ramp soft-start ramp rate vr11, r ss = 100k - 1.25 - mv/s amd, r ss = 100k - 1.25 - mv/s adjustment range of soft-start ramp rate (note 3) 0.156 - 6.25 mv/s overcurrent protection ocset trip current (isl6314crz) 94 100 106 a ocset trip current (isl6314irz) 93 100 107 a ocset accuracy ocset and isum difference -5 0 5 mv iseno offset -1.7 0 1.7 mv protection undervoltage threshold vsen falling vdac - 325 vdac - 350mv vdac - 375 v undervoltage hysteresis vsen rising - 100 - mv overvoltage threshold during soft-start vr11 and amd 1.24 1.27 1.30 v overvoltage threshold (default) vr11, vsen rising vdac + 150mv vdac + 175mv vdac + 200mv v amd, vsen rising vdac + 200mv vdac + 225mv vdac + 250mv v overvoltage hysteresis vsen falling - 100 - mv pgood output sink current pgood = 0.4v - 7.5 - ma over-temperature shutdown (note 3) thermal shutdown setpoint - 160 - c thermal recovery setpoint - 100 - c electrical specifications recommended operating conditions, unless otherwise specif ied. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. tem perature limits established by characterization and are not production tested. (continued) parameter test conditions min typ max units isl6314 isl6314
8 fn6455.2 october 8, 2009 timing diagram switching time (note 3) ugate rise time t rugate; v pvcc = 12v, 3nf load, 10% to 90% -26-ns lgate rise time t rlgate; v pvcc = 12v, 3nf load, 10% to 90% -18-ns ugate fall time t fugate; v pvcc = 12v, 3nf load, 90% to 10% -18-ns lgate fall time t flgate; v pvcc = 12v, 3nf load, 90% to 10% -12-ns ugate turn-on non-overlap t pdhugate ; v pvcc = 12v, 3nf load, adaptive -10-ns lgate turn-on non-overlap t pdhlgate ; v pvcc = 12v, 3nf load, adaptive -10-ns gate drive resistance (note 3) upper drive source resistance v pvcc = 12v, 15ma source current 1.25 2.0 3.0 upper drive sink resistance v pvcc = 12v, 15ma sink current 0.9 1.65 3.0 lower drive source resistance v pvcc = 12v, 15ma source current 0.85 1.25 2.2 lower drive sink resistance v pvcc = 12v, 15ma sink current 0.60 0.80 1.35 note: 3. limits should be considered typi cal and are not production tested. electrical specifications recommended operating conditions, unless otherwise specif ied. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. tem perature limits established by characterization and are not production tested. (continued) parameter test conditions min typ max units ugate lgate t flgate t pdhugate t rugate t fugate t pdhlgate t rlgate isl6314 isl6314
9 fn6455.2 october 8, 2009 functional pin description vcc (pin 18) vcc is the bias supply for the ics small-signal circuitry. connect this pin to a +5v supply and decouple using a quality 0.1f ceramic capacitor. pvcc (pin 19) this pin is the power supply pin for the channel mosfet drivers, and can be connected to any voltage from +5v to +12v depending on the desired mosfet gate-drive level. decouple this pin with a quality 1.0f ceramic capacitor. gnd (pin 33 = metal pad) gnd is the bias and reference ground for the ic, connected to the metal pad under the ic. en (pin 17) this pin is a threshold-sensitive (approximately 0.85v) enable input for the controller. held low, this pin disables controller operation. pulled high, the pin enables the controller for operation. fs (pin 3) a resistor, r t , tied to this pin sets the channel switching frequency of the controller. refer to equation 42 for proper resistor calculation. the fs pin also controls whether the droop voltage (as described under pins iseno, isen-, isen+) is added to the differential remote-sense amplifie r?s output (vdiff). tying the r t resistor to ground connects droop voltage, allowing the converter to incorporate output voltage droop proportional to the output current. tying the r t resistor to vcc disconnects the droop voltage. vid0, vid1, vid2, vid3, vi d4, vid5, vid6, and vid7 (pins 31, 30, 29, 28, 27, 26, 25, 32) these are the inputs for the in ternal dac that provide the reference voltage for output regulation. these pins respond to ttl logic thresholds. these pins are internally pulled high, to approximately 1.2v, by 40a internal current sources for intel modes of operation, and pulled low by 20a internal current sources for amd modes of ope ration. the internal pull-up current decreases to 0 as the vid voltage approaches the internal pull-up voltage. all vid pins are compatible with external pull-up voltages not exceeding the ic?s bias voltage (vcc). vsen (pin 12) this pin senses the microprocessor?s core voltage. connect this pin to the core voltage sense pin or point of the microprocessor. rgnd (pin 11) this pin senses the local ground voltage of the microprocessor. connect this pin to the ground sense pin or point of the microprocessor. fb and comp (pins 9, 7) these pins are the internal error amplifier inverting input and output respectively. the fb pin, comp pin, and the vdiff pins are tied together thr ough external r-c networks to compensate the regulator. dvc (pin 8) a series resistor and capacitor can be connected from the dvc pin to the fb pin to compensate and smooth dynamic vid transitions. ocset (pin 13) this is the overcurrent set pin. placing a resistor from ocset pin to iseno allows a 100a current to flow out of this pin, producing a voltage reference. internal circuitry compares the voltage at ocset to the voltage at isen-, and if isen- ever exceeds ocset, the overcurrent protection activates. apa (pin 6) this is the adaptive phase alignment set pin. a 100a current flows out the apa pin and by tying a resistor from this pin to comp the trip level fo r the adaptive phase alignment circuitry can be set. ref (pin 4) the ref input pin is the positive input of the error amplifier. it is internally connected to the dac output through a 2k resistor. a capacitor is used between the ref pin and ground to smooth the voltage transition during soft-start and dynamic vid transitions. this pin can also be returned to rgnd if desired. nc (pin 20) this pin is presently nc (no connect), but is reserved for a future function. ofs (pin 5) the ofs pin provides a means to program a dc current for generating an offset voltage ac ross the resistor between fb and vdiff. the offset current is generated via an external resistor and precision internal voltage references. the polarity is selected by connecting the re sistor to gnd (for positive offset) or to vcc (for negative offset). for no offset, the ofs pin should be left unconnected. ugate (pin 23) connect this pin to the corresponding upper mosfet gate. this pin is used to contro l the upper mosfet and is monitored for shoot-through prevention purposes. boot (pin 22) this pin provides the bias voltage for the upper mosfet drive. connect this pin to appropriately-chosen external bootstrap capacitors. internal bootstrap diodes connected to the pvcc pin provides the nec essary bootstrap charge. isl6314 isl6314
10 fn6455.2 october 8, 2009 phase (pin 24) connect this pin to the source of the upper mosfet. this pin is the return path for the upper mosfet drive. lgate (pin 21) this pin is used to control the lower mosfet. connect this pin to the lower mosfet gate. ss (pin 2) a resistor, r ss , placed from ss to vcc or gnd will set the soft-start ramp slope. refer to equations 16 and 17 for proper resistor calculation. the state of the ss pin also selects which of the available dac tables will be used to decode the vid inputs and puts the controller into the corresponding mode of operation. for intel vr11 mode of operation the r ss resistor should be tied to gnd. amd compliance is selected if the r ss resistor is tied to vcc (once in amd mode, the vid7 bit selects 5-bit dac if set to a logic high, or 6-bit dac if set to a logic low). pgood (pin 1) for intel mode of operation, pgood indicates whether vsen is within specified overvoltage and undervoltage limits after a fixed delay from the end of soft -start. if vsen exceeds these limits, or if an overcurrent event occurs, or if the part is disabled, pgood is pulled low. pgood is always low prior to the end of soft-start. for amd modes of operation, pgood will always be high as long as vsen is within the s pecified undervoltage/overvoltage window and soft-start has ended. pgood only goes low if vsen is outside this window. iseno, isen-, and isen + (pins 14, 15, 16) isen-, isen+, and iseno are the dcr current sense amplifier?s negative input, positive input, and output respectively. for accurate d cr current sensing, connect a resistor from the phase node to isen- and connect isen+ to the output inductor, roughly vout. a parallel r-c feedback circuit connected between isen- and iseno will then create a voltage from isen+ to iseno proportional to the voltage drop across the inductor dcr. this voltage is referred to as the droop voltage and is added to the differential remote-sense amplifier?s output. an optional 0.001f to 0.01f ceramic capacitor can be placed from the isen+ pin to the isen- pin to help reduce common mode noise that might be introduced by the layout. vdiff (pin 10) vdiff is the output of the diff erential remote-sense amplifier. the voltage on this pin is equal to the difference between vsen and rgnd (vout) added to the difference between isen+ and iseno (droop). vdi ff therefore represents the vout voltage plus the droop voltage. the state of the fs pin determines whether the droop voltage is added or not. operation power conversion the isl6314 controller helps simplify implementation by integrating vital functions and requiring minimal external components. the ?block diagram? on page 3 provides a top level view of the single-phase power conversion using the isl6314 controller. output ripple figure 1 illustrates the output ripple. the pwm current forms the ac ripple current and the dc load current. the peak-to-peak current about 7a, and the dc components of the inductor current feeds the load. to understand the ripple current amplitude, examine equation 1 representing a single channel peak-to-peak inductor current. in equation 1, v in and v out are the input and output voltages respectively, l is the single-channel inductor value, and f s is the switching frequency. the output capacitors conduct the ripple component of the inductor current. output voltage ripple is a function of capacitance, capacitor equivalent series resistance (esr), and inductor ripple current. reducing the inductor ripple current allows the designer to us e fewer or less costly output capacitors. equation 2 shows the approximation for the output voltage ripple. adaptive phase alignment (apa) to improve the transient response, the isl6314 implements intersil?s proprietary adaptive phase alignment (apa) technique, which turns on the channel during large current step transient events. figure 1. pwm and inductor-current waveforms for 1-phase converter 1s/div pwm, 5v/div il, 7a/div (eq. 1) i p-p v in v out ? () v out ? lf s v ? in ? --------------------------------------------------------- - = (eq. 2) v p-p i p-p esr ? = isl6314 isl6314
11 fn6455.2 october 8, 2009 as figure 2 shows, the apa ci rcuitry works by monitoring the voltage on the apa pin and comparing it to a filtered copy of the voltage on the comp pin. the voltage on the apa pin is a copy of the comp pin volt age that has been negatively offset. if the apa pin exceeds the filtered comp pin voltage an apa event occurs and the channel is forced on. the apa trip level is the am ount of dc offset between the comp pin and the apa pin. this is the voltage excursion that the apa and comp pin must have during a transient event to activate the adaptive phase alignment circuitry. this apa trip level is set through a resistor, r apa , that connects from the apa pin to the comp pin. a 100a current flows across r apa into the apa pin to set the apa trip level as described in equation 3. an apa trip level of 500mv is recommended for most applications. a 1000pf capacitor, c apa , should also be placed across the r apa resistor to help with noise immunity. active pulse positioning (app) modulated pwm operation the isl6314 uses a proprietary active pulse positioning (app) modulation scheme to control the internal pwm signals that command each channel?s driver to turn their upper and lower mosfets on and off. the time interval in which a pwm signal can occur is generated by an internal clock, whose cycle time is t he inverse of the switching frequency set by the resistor connected to the fs pin. the advantage of intersil?s proprietary active pulse positioning (app) modulator is that the pwm signal has the ability to turn on at any point during this pwm time interval, and turn off immediately after the pwm signal has transitioned high. this is important because is allows the controller to quickly respond to output voltage drops associated with current load spikes, while avoiding the ring back affects associated with other modulation schemes. the pwm output state is driven by the position of the error amplifier output signal, v comp , as illustrated in figure 3. at the beginning of each pwm time interval, this v comp signal is compared to the internal modulator waveform. as long as the v comp voltage is lower then the modulator waveform voltage, the pwm signal is commanded low. the internal mosfet driver detects the low state of the pwm signal and turns off the upper mosfet and turns on the lower synchronous mosfet. when the v comp voltage crosses the modulator ramp, the pw m output transitions high, turning off the synchronous mosfet and turning on the upper mosfet. the pwm signal will remain high until the v comp voltage crosses the modulator ramp again. when this occurs, the pwm signal will transition low again. during each pwm time interval, the pwm signal can only transition high once. once pwm transitions high, it can not transition high again until the beginning of the next pwm time interval. this prevents the occurrence of double pwm pulses occurring during a single period. output voltage setting the isl6314 uses a digital to analog converter (dac) to generate a reference voltage based on the logic signals at the vid pins. the dac decodes the logic signals into one of the discrete voltages shown in tabl es 2, 3 or 4. in the intel vr11 mode of operation, each vid pin is pulled up to an internal 1.2v voltage by a weak current source (40a), which decreases to 0a as the voltage at the vid pin varies from 0 to the internal 1.2v pull-up voltage. in amd modes of operation, the vid pins are pulled low by a weak 20a current source. external pull-up resistors or active-high output stages can augment the pull-up current sources, up to a voltage of 5v. . the isl6314 accommodates th ree different dac ranges: intel vr11, amd k8/k9 5-bit, and amd 6-bit. the state of the ss and vid7 pins decide which dac version is active. refer to table 1 for a description of how to select the desired dac version. figure 2. adaptive phase alignment detection external circuit isl6314 internal circuit comp v apa,trip error apa amplifier c apa r apa + - low filter - + apa pass 100a - + to apa circuitry v apa trip , r apa 100 10 6 ? ? = (eq. 3) figure 3. channel pwm function - + pwm v comp to gate control logic modulator ramp waveform isl6314 isl6314
12 fn6455.2 october 8, 2009 table 1. isl6314 dac select and function table dac version ss pin vid7 pin intel vr11 r ss resistor tied to gnd - amd 5-bit r ss resistor tied to vcc high amd 6-bit r ss resistor tied to vcc low tie resistor to vcc open tie resistor to gnd r ss : amd tables - r ss : intel table r ofs : negative no offset r ofs : positive r t : no droop - r t : droop table 2. vr11 voltage identification codes vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 vdac 00000000off 00000001off 000000101. 60000 000000111. 59375 000001001. 58750 000001011. 58125 000001101. 57500 000001111. 56875 000010001. 56250 000010011. 55625 000010101. 55000 000010111. 54375 000011001. 53750 000011011. 53125 000011101. 52500 000011111. 51875 000100001. 51250 000100011. 50625 000100101. 50000 000100111. 49375 000101001. 48750 000101011. 48125 000101101. 47500 000101111. 46875 000110001. 46250 000110011. 45625 000110101. 45000 000110111. 44375 000111001. 43750 000111011. 43125 000111101. 42500 000111111. 41875 001000001. 41250 001000011. 40625 001000101. 40000 001000111. 39375 001001001. 38750 001001011. 38125 001001101. 37500 001001111. 36875 001010001. 36250 001010011. 35625 001010101. 35000 001010111. 34375 001011001. 33750 001011011. 33125 001011101. 32500 001011111. 31875 001100001. 31250 001100011. 30625 001100101. 30000 001100111. 29375 001101001. 28750 001101011. 28125 001101101. 27500 001101111. 26875 001110001. 26250 001110011. 25625 001110101. 25000 001110111. 24375 001111001. 23750 001111011. 23125 001111101. 22500 001111111. 21875 010000001. 21250 010000011. 20625 010000101. 20000 table 2. vr11 voltage identi fication codes (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 vdac isl6314 isl6314
13 fn6455.2 october 8, 2009 010000111. 19375 010001001. 18750 010001011. 18125 010001101. 17500 010001111. 16875 010010001. 16250 010010011. 15625 010010101. 15000 010010111. 14375 010011001. 13750 010011011. 13125 010011101. 12500 010011111.1 1875 010100001.1 1250 010100011. 10625 010100101. 10000 010100111. 09375 010101001. 08750 010101011. 08125 010101101. 07500 010101111. 06875 010110001. 06250 010110011. 05625 010110101. 05000 010110111. 04375 010111001. 03750 010111011. 03125 010111101. 02500 010111111. 01875 011000001. 01250 011000011. 00625 011000101. 00000 011000110. 99375 011001000. 98750 011001010. 98125 011001100. 97500 011001110. 96875 011010000. 96250 011010010. 95625 011010100. 95000 table 2. vr11 voltage identi fication codes (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 vdac 011010110. 94375 011011000. 93750 011011010. 93125 011011100. 92500 011011110. 91875 011100000. 91250 011100010. 90625 011100100. 90000 011100110. 89375 011101000. 88750 011101010. 88125 011101100. 87500 011101110. 86875 011110000. 86250 011110010. 85625 011110100. 85000 011110110. 84375 011111000. 83750 011111010. 83125 011111100. 82500 011111110. 81875 100000000. 81250 100000010. 80625 100000100. 80000 100000110. 79375 100001000. 78750 100001010. 78125 100001100. 77500 100001110. 76875 100010000. 76250 100010010. 75625 100010100. 75000 100010110. 74375 100011000. 73750 100011010. 73125 100011100. 72500 100011110. 71875 100100000. 71250 100100010. 70625 100100100. 70000 table 2. vr11 voltage identi fication codes (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 vdac isl6314
14 fn6455.2 october 8, 2009 100100110. 69375 100101000. 68750 100101010. 68125 100101100. 67500 100101110. 66875 100110000. 66250 100110010. 65625 100110100. 65000 100110110. 64375 100111000. 63750 100111010. 63125 100111100. 62500 100111110. 61875 101000000. 61250 101000010. 60625 101000100. 60000 101000110. 59375 101001000. 58750 101001010. 58125 101001100. 57500 101001110. 56875 101010000. 56250 101010010. 55625 101010100. 55000 101010110. 54375 101011000. 53750 101011010. 53125 101011100. 52500 101011110. 51875 101100000. 51250 101100010. 50625 101100100. 50000 11111110off 11111111off table 3. amd 5-bit voltage identification codes vid4 vid3 vid2 vid1 vid0 vdac 11111off 111100.800 111010.825 table 2. vr11 voltage identi fication codes (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 vdac 111000.850 110110.875 110100.900 110010.925 110000.950 101110.975 101101.000 101011.025 101001.050 100111.075 100101.100 100011.125 100001.150 011111.175 011101.200 011011.225 011001.250 010111.275 010101.300 010011.325 010001.350 001111.375 001101.400 001011.425 001001.450 000111.475 000101.500 000011.525 000001.550 table 4. amd 6-bit voltage identification codes vid5 vid4 vid3 vid2 vid1 vid0 vdac 0 0 0 0 0 0 1.5500 0 0 0 0 0 1 1.5250 0 0 0 0 1 0 1.5000 0 0 0 0 1 1 1.4750 0 0 0 1 0 0 1.4500 0 0 0 1 0 1 1.4250 0 0 0 1 1 0 1.4000 table 3. amd 5-bit voltage identification codes (continued) vid4 vid3 vid2 vid1 vid0 vdac isl6314
15 fn6455.2 october 8, 2009 voltage regulation in order to regulate the output voltage to a specified level, the isl6314 uses the integr ating compensation network shown in figure 4. this compensation network insures that the steady-state error in the ou tput voltage is limited only to the error in the reference volt age (output of the dac) and offset errors in the ofs current source, remote-sense and error amplifiers. intersil specif ies the guaranteed tolerance of the isl6314 to include the comb ined tolerances of each of these elements. the isl6314 incorporates an internal differential remote-sense amplifier in the feedback path. the amplifier removes the voltage error encountered when measuring the output voltage relative to the controller ground reference point, resulting in a more accurate means of sensing output voltage. connect the microprocessor sense pins to the non-inverting input, vsen, and inverting i nput, rgnd, of the remote-sense amplifier. the droop voltage, v droop , also feeds into the remote-sense amplifier. the remote-sense output, v diff , is therefore equal to the sum of the output voltage, v out , and the droop voltage. v diff is connected to the inverting input of the error amplifier through an external resistor. 0 0 0 1 1 1 1.3750 0 0 1 0 0 0 1.3500 0 0 1 0 0 1 1.3250 0 0 1 0 1 0 1.3000 0 0 1 0 1 1 1.2750 0 0 1 1 0 0 1.2500 0 0 1 1 0 1 1.2250 0 0 1 1 1 0 1.2000 0 0 1 1 1 1 1.1750 0 1 0 0 0 0 1.1500 0 1 0 0 0 1 1.1250 0 1 0 0 1 0 1.1000 0 1 0 0 1 1 1.0750 0 1 0 1 0 0 1.0500 0 1 0 1 0 1 1.0250 0 1 0 1 1 0 1.0000 0 1 0 1 1 1 0.9750 0 1 1 0 0 0 0.9500 0 1 1 0 0 1 0.9250 0 1 1 0 1 0 0.9000 0 1 1 0 1 1 0.8750 0 1 1 1 0 0 0.8500 0 1 1 1 0 1 0.8250 0 1 1 1 1 0 0.8000 0 1 1 1 1 1 0.7750 1 0 0 0 0 0 0.7625 1 0 0 0 0 1 0.7500 1 0 0 0 1 0 0.7375 1 0 0 0 1 1 0.7250 1 0 0 1 0 0 0.7125 1 0 0 1 0 1 0.7000 1 0 0 1 1 0 0.6875 1 0 0 1 1 1 0.6750 1 0 1 0 0 0 0.6625 1 0 1 0 0 1 0.6500 1 0 1 0 1 0 0.6375 1 0 1 0 1 1 0.6250 1 0 1 1 0 0 0.6125 1 0 1 1 0 1 0.6000 table 4. amd 6-bit voltage identification codes (continued) vid5 vid4 vid3 vid2 vid1 vid0 vdac 1 0 1 1 1 0 0.5875 1 0 1 1 1 1 0.5750 1 1 0 0 0 0 0.5625 1 1 0 0 0 1 0.5500 1 1 0 0 1 0 0.5375 1 1 0 0 1 1 0.5250 1 1 0 1 0 0 0.5125 1 1 0 1 0 1 0.5000 1 1 0 1 1 0 0.4875 1 1 0 1 1 1 0.4750 1 1 1 0 0 0 0.4625 1 1 1 0 0 1 0.4500 1 1 1 0 1 0 0.4375 1 1 1 0 1 1 0.4250 1 1 1 1 0 0 0.4125 1 1 1 1 0 1 0.4000 1 1 1 1 1 0 0.3875 1 1 1 1 1 1 0.3750 table 4. amd 6-bit voltage identification codes (continued) vid5 vid4 vid3 vid2 vid1 vid0 vdac v out v ref v ofs ? v droop ? = (eq. 4) isl6314
16 fn6455.2 october 8, 2009 the output of the error amplifier, v comp , is compared to the sawtooth waveform to generate the pwm signal. the pwm signal controls the timing of the internal mosfet drivers and regulates the converter outpu t so that the voltage at fb is equal to the voltage at ref. this will regulate the output voltage to be equal to equation 4. the internal and external circuitry that controls voltage regulation is illustrated in figure 4. load-line (droop) regulation some microprocessor manufacturers require a precisely-controlled output resistance. this dependence of output voltage on load current is often termed ?droop? or ?load line? regulation. by adding a well controlled output impedance, the output voltage c an effectively be level shifted in a direction which works to achieve the load-line regulation required by these manufacturers. in other cases, the designer may determine that a more cost-effective solution can be achieved by adding droop. droop can help to reduce the output-voltage spike that results from fast load-current demand changes. the magnitude of the spike is dictated by the esr and esl of the output capacitors selected. by positioning the no-load voltage level near the upper s pecification limit, a larger negative spike can be sustained without crossing the lower limit. by adding a well cont rolled output impedance, the output voltage under load can effectively be level shifted down so that a larger positive spike can be sustained without crossing the upper specification limit. . as shown in figure 5, a voltage, v droop , proportional to the current in the channel, i out , feeds into the differential remote-sense amplifier. the resulting voltage at the output of the remote-sense amplifier is the sum of the output voltage and the droop voltage. equation 5 shows that feeding this voltage into the compensation network causes the regulator to adjust the output voltage so that it?s equal to the reference voltage minus the droop voltage. the droop voltage, v droop , is created by sensing the current through the output inductors. this is accomplished by using a continuous dcr current sensing method. inductor windings have a ch aracteristic distributed resistance or dcr (direct current resistance). for simplicity, the inductor dcr is considered as a separate lumped quantity, as shown in figure 5. the channel current, i l , flowing through the inductor, passes through the dcr. equation 5 shows the s-domain equivalent voltage, v l , across the inductor. the inductor dcr is important because the voltage dropped across it is proportional to the channel current. by using a simple r-c network and a current sense amplifier, as shown in figure 5, the voltage drop across the inductor?s dcr can be extracted. the output of the current sense amplifier, v droop , can be shown to be proportional to the channel current i l , shown in equation 6. if the r-c network components are selected such that the r-c time constant matches the inductor l/dcr time constant, then v droop is equal to the voltage drop across the dcr, multiplied by a gain. as equation 7 shows, v droop is therefore proportional to the total output current, i out . figure 4. output voltage and load-line regulation with offset adjustment i ofs external circuit isl6314 internal circuit comp r c r fb fb vdiff vsen rgnd - + v ofs error amplifier - + differential remote-sense amplifier v comp c c ref c ref - + vid dac 2k isen+ iseno + - + v droop - + v out - figure 5. dcr sensing configuration - + iseno dcr l inductor v out c out i l - + v l (s) phase r s r comp c comp isen- isen+ isl6314 - + v droop i out (optional) (eq. 5) v l s () i l sl dcr + ? () ? = (eq. 6) v droop s () sl ? dcr ------------- 1 + ?? ?? sr comp c comp ?? 1 + () -------------------------------------------------------------------------- r comp r s ----------------------- i l () dcr ?? ? = isl6314
17 fn6455.2 october 8, 2009 . by simply adjusting the value of r s , the load line can be set to any level, giving the converter the right amount of droop at all load currents. it may also be necessary to compensate for any changes in dcr due to temperature. these changes cause the load line to be ske wed, and cause the r-c time constant to not match the l/dcr time constant. if this becomes a problem a simple negative temperature coefficient resistor network can be used in the place of r comp to compensate for the rise in dcr due to temperature. note: an optional 10nf ceramic capacitor from the isen+ pin to the isen- pin is recommended to help reduce any noise affects on the current sense amplifier due to layout output-voltage offset programming the isl6314 allows the designer to accurately adjust the offset voltage by connecting a resistor, r ofs , from the ofs pin to vcc or gnd. when r ofs is connected between ofs and vcc, the voltage across it is regulated to 1.6v. this causes a proportional current (i ofs ) to flow into the ofs pin and out of the fb pin, providing a negative offset. if r ofs is connected to ground, the voltage across it is regulated to 0.3v, and i ofs flows into the fb pin and out of the ofs pin, providing a positive offset. the offset current flowing through the resistor between vdiff and fb will generate the desired offset voltage which is equal to the product (i ofs x r fb ). these functions are shown in figures 6 and 7. once the desired output offset voltage has been determined, use the following formulas in equations 8 and 9 to set r ofs : for negative offset (connect r ofs to vcc): for positive offset (connect r ofs to gnd): (eq. 7) v droop r comp r s --------------------- i out dcr ?? = (eq. 8) r ofs 1.6 r fb ? v offset -------------------------- = (eq. 9) r ofs 0.3 r fb ? v offset -------------------------- = e/a fb ofs vcc gnd + - + - 0.3v 1.6v gnd r ofs r fb vdiff isl6314 figure 6. positive offset output voltage programming vref v ofs + - i ofs e/a fb ofs vcc gnd + - + - 0.3v 1.6v vcc r ofs r fb vdiff isl6314 figure 7. negative offset output voltage programming vref v ofs + - i ofs isl6314
18 fn6455.2 october 8, 2009 dynamic vid modern microprocessors need to make changes to their core voltage as part of normal operation. they direct the isl6314 to do this by making changes to the vid inputs. the isl6314 is required to monitor the dac inputs and respond to on-the-fly vid changes in a co ntrolled manner, supervising a safe output voltage transition without discontinuity or disruption. the dac mode, isl6314 is operating in, determines how the controller responds to a dynamic vid change. intel dynamic vid transitions when in intel vr11 mode the isl6314 checks the vid inputs on the positive edge of an internal 5.5mhz clock. if a new code is established and it remains stable for three consecutive readings (0.36s to 0.54s), the isl6314 recognizes the new code and changes the internal da c reference directly to the new level. the intel processor controls the vid transitions and is responsible for incrementing or decrementing one vid step at a time. in vr11 mode, the isl6314 will immediately change the internal dac reference to the new requested value as soon as the request is validat ed, which means the fastest recommended rate at which a bit change can occur is once every 1s. if the vid code is changed by more then one step at a time, the dac will try to track it at a 5.5mhz step rate. this will likely cause an over current or overvoltage fault. amd dynamic vid transitions when running in amd 5-bit or 6-bit modes of operation, the isl6314 responds differently to a dynamic vid change. in the amd modes the isl6314 still c hecks the vid inputs on the positive edge of an internal 5.5mhz clock. in these modes the vid code can be changed by more than a 1-bit step at a time. if a new code is established and it remains stable for three consecutive readings (0.36s to 0.54s), the isl6314 recognizes the change and begins slewing the dac in 6.25mv steps at a stepping freq uency of 345khz until the vid and dac are equal. thus, the total time required for a vid change, t dvid , is dependent only on the size of the vid change ( v vid ). the time required for a isl6314-based converter in amd 5-bit dac configuration to make a 1.1v to 1.5v reference voltage change is about 186s, as calculated using equation 10. vid ?off? dac codes both the intel vr11 and the amd 5-bit vid tables include ?off? dac codes, which indicate to the controller to disable all regulation. recognition of these codes is slightly different in that they must be stable for four co nsecutive readings of a 5.5mhz clock (0.54s to 0.72s) to be recognized. once an ?off? code is recognized the isl6314 latches off, and must be reset by dropping the en pin. compensating dynamic vid transitions during a vid transition, the resulting change in voltage on the fb pin and the comp pin causes an ac current to flow through the error amplifier compensation components from the fb to the comp pin. this current then flows through the feedback resistor, r fb , and can cause the output voltage to overshoot or undershoot at the end of the vid transition. in order to ensure the smooth trans ition of the output voltage during a vid change, a vid-on-the-fly compensation network is required. this netw ork is composed of a resistor and capacitor in series, r dvc and c dvc , between the dvc and the fb pin, as shown in figure 8. this vid-on-the-fly compen sation network works by sourcing ac current into the fb node to offset the effects of the ac current flowing from t he fb to the comp pin during a vid transition. to create th is compensation current the isl6314 sets the voltage on the dvc pin to be 2x the voltage on the ref pin. since the error amplifier forces the voltage on the fb pin and the ref pin to be equal, the resulting voltage across the series rc between dvc and fb is equal to the ref pin voltage. the rc compensation components, r dvc and c dvc , can then be selected to create the desired amount of compensation current. the amount of compensation current required is dependant on the modulator gain of t he system, k1, and the error amplifier r-c components, r c and c c , that are in series between the fb and comp pins. use equations 11, 12, and 13 to calculate the rc component values, r dvc and c dvc , for the vid-on-the-fly compensation network. for these equations: v in is the input voltage for the power train; v p-p is the oscillator ramp amplitude (1.5v); and r c and c c are the error amplifier r-c components between the fb and comp pins. (eq. 10) t dvid 1 345 10 3 ------------------------- - v vid 0.00625 --------------------- ?? ?? ? = figure 8. vid-on-the-fly compensation network isl6314 internal circuit error ref amplifier c dvc r dvc - + x2 c c r c c ref dvc fb comp r fb vdiff i dvc i c i dvc = i c vdac+rgnd k1 v in v pp ----------- = (eq. 11) a k1 k1 1 ? ---------------- - = isl6314
19 fn6455.2 october 8, 2009 advanced adaptive zero shoot-through deadtime control (patent pending) the integrated drivers incorporate a unique adaptive deadtime control technique to minimize deadtime, resulting in high efficiency from the reduced freewheeling time of the lower mosfet body-diode conduction, and to prevent the upper and lower mosfets from conducting simultaneously. this is accomplished by ensuring either rising gate turns on its mosfet with minimum and sufficient delay after the other has turned off. during turn-off of the lowe r mosfet, the phase voltage is monitored until it reaches a -0.3v/+0.8v (forward/reverse inductor current). at this time the ugate is released to rise. an auto-zero comparator is used to correct the r ds(on) drop in the phase voltage preventing false detection of the -0.3v phase level during r ds(on) conduction period. in the case of zero current, the ugate is released after 35ns delay of the lgate dropping below 0.5v. when lgate first begins to transition low, this quick transition can disturb the phase node and cause a false trip, so there is 20ns of blanking time once lgate falls until phase is monitored. once the phase is high , the advanced adaptive shoot-through circuitry mo nitors the phase and ugate voltages during a pwm falling edge and the subsequent ugate turn-off. if either the ugate falls to less than 1.75v above the phase or the phase fall s to less than +0.8v, the lgate is released to turn-on. internal bootstrap device the integrated driver features an internal bootstrap schottky diode. simply adding an external capacitor across the boot and phase pins completes th e bootstrap circuit. the bootstrap function is also designed to prevent the bootstrap capacitor from overcharging du e to the large negative swing at the phase node. this reduces voltage stress on the boot to phase pins. the bootstrap capacitor must have a maximum voltage rating above pvcc + 4v and its capacitance value can be chosen from equation 14: where q g1 is the amount of gate charge per upper mosfet at v gs1 gate-source voltage and n q1 is the number of control mosfets. the v boot_cap term is defined as the allowabl e droop in the rail of the upper gate drive. typical curves are shown in figure 9. gate drive voltage versatility the isl6314 provides the user flexibility in choosing the gate drive voltage for efficiency optimization. the controller ties the upper and lower drive rails together. simply applying a voltage from 5v up to 12v on pvcc sets both gate drive rail voltages simultaneously. initialization prior to initialization, proper conditions must exist on the en, vcc, pvcc and the vid pins. when the conditions are met, the controller begins soft-start. once the output voltage is within the proper window of oper ation, the controller asserts pgood. r dvc ar c = (eq. 12) c dvc c c a ------- - = (eq. 13) 50nc 20nc figure 9. bootstrap capacitance vs boot ripple voltage v boot_cap (v) c boot_cap ( f) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.3 0.0 0.1 0.2 0.4 0.5 0.6 0.9 0.7 0.8 1.0 q gate = 100nc c boot_cap q gate v boot_cap -------------------------------------- q gate q g1 pvcc ? v gs1 ---------------------------------- n q1 ? = (eq. 14) isl6314
20 fn6455.2 october 8, 2009 . enable and disable while in shutdown mode, the lgate and ugate signals are held low to assure the mosfets remain off. the following input conditions must be met, for both intel and amd modes of operation, before the isl6314 is released from shutdown mode to begin the soft-start start-up sequence: 1. the bias voltage applied at vcc must reach the internal power-on reset (por) rising threshold. once this threshold is reached, proper operation of all aspects of the isl6314 is guaranteed. hyst eresis between the rising and falling thresholds assure that once enabled, the isl6314 will not inadvertently turn off unless the bias voltage drops substantia lly (see ?electrical specifications? on page 6). 2. the voltage on en must be above 0.85v. the en input allows for power sequencing between the controller bias voltage and another voltage rail. the enable comparator holds the isl6314 in shutdown until the voltage at en rises above 0.85v. the enable comparator has 110mv of hysteresis to prevent bounce. 3. the driver bias voltage applied at the pvcc pin must reach the internal power-on reset (por) rising threshold. hysteresis between the rising and falling thresholds assure that once enabled, the isl6314 will not inadvertently turn off unless the pvcc bias voltage drops substantially (see ?electrica l specifications? on page 6). for intel vr11 and amd 6-bit modes of operation these are the only conditions that must be met for the controller to immediately begin the soft-start sequence, as shown in figure 10. if running in amd 5-bit mode of operation there is one more condition that must be met: 4. the vid code must not be 11111 in amd 5-bit mode. this code signals the controller that no load is present. the controller will not allow soft-sta rt to begin if this vid code is present on the vid pins. once all of these conditions are met the controller will begin the soft-start sequence and will ramp the output voltage up to the user designated level. intel soft-start the soft-start function allows the converter to bring up the output voltage in a controlled fashion, resulting in a linear ramp-up. the soft-start sequ ence for the intel modes of operation is slightly differ ent than the amd soft-start sequence. for the intel vr11 mode of operation, the soft-start sequence is composed of four periods, as shown in figure 11. once the isl6314 is released from shutdown and soft-start begins (as described in ?enable and disable? on page 20), the controller will have fixed delay period t d1 , typically 1.1ms. after this dela y period, the vr will begin first soft-start ramp until the out put voltage reaches 1.1v vboot voltage. then, the controller will regulate the vr voltage at 1.1v for another fixed period t d3, typically 93s. at the end of t d3 period, isl6314 will read the vid signals. it is recommended that the vid codes be set no later then 50s into period t d3 . if the vid code is valid, isl6314 will initiate the second soft-start ramp un til the output voltage reaches the vid voltage plus/minus any offset or droop voltage. the soft-start time is the sum of the 4 periods as shown in equation 15. during t d2 and t d4 , isl6314 digitally controls the dac voltage change at 6.25mv per step. the time for each step is determined by the frequency of t he soft-start oscillator which is defined by the resistor r ss from ss pin to gnd. the second soft-start ramp time t d2 and t d4 can be calculated based on equations 16 and 17: figure 10. power sequencing using threshold-sensitive enable (en) function external circuit isl6314 internal circuit - + 0.85v en +12v por circuit 10.7k 1.40k enable comparator soft-start and fault logic vcc pvcc figure 11. intel soft-start waveforms v out , 500mv/div en 500s/div t d3 t d4 t d5 pgood t d2 t d1 t ss t d1 t d2 t d3 t d4 +++ = (eq. 15) isl6314
21 fn6455.2 october 8, 2009 for example, when vid is set to 1.5v and the r ss is set at 100k , the first soft-start ramp time t d2 will be 880s and the second soft-start ramp time t d4 will be 320s. after the dac voltage reaches the final vid setting, pgood will be set to high with the fixed delay t d5 . the typical value for t d5 is 93s. amd soft-start for the amd 5-bit and 6-bi t modes of operation, the soft-start sequence is composed of two periods, as shown in figure 12. at the beginning of soft-start, the vid code is immediately obtained from the vid pins, followed by a fixed delay period t da of typically 1.1ms. after this delay period the isl6314 will begin ramping the output voltage to the desired dac level at a fixed rate of 6.25mv per step. the time for each step is determined by the frequency of the soft-start oscillator which is de fined by the resistor r ss on the ss pin. the amount of time required to ramp the output voltage to the final dac voltage is referred to as t db , and can be calculated as shown in equation 18. at the end of soft-start, pgood will immediately go high if the vsen voltage is within the undervoltage and overvoltage limits. table 5 is a summary table of the typical soft-start timing for both modes. the times listed are fixed delays; the variable ones (defined by the equations) depend on the slope of the ramp (1.25 mv/s for a nominal 100k r ss resistor), and the amount of voltage excursion. pre-biased soft-start the isl6314 also has the ability to start up into a pre-charged output, without causing any un necessary disturbance. the fb pin is monitored during soft-start, and should it be higher than the equivalent internal ramping reference voltage, the output drives hold both mosfets off. once the internal ramping reference exceeds the fb pin pot ential, the output drives are enabled, allowing the output to ramp from the pre-charged level to the final level dictated by the dac setting. should the output be pre-charged to a leve l exceeding the dac setting, the output drives are enabled at the end of the soft-start period, leading to an abrupt correction in the output voltage down to the dac-set level. see figure 13. fault monitoring and protection the isl6314 actively monitors output voltage and current to detect fault conditions. fault monitors trigger protective measures to prevent damage to a microprocessor load. one common power good indicator is provided for linking to external system monitors. the schematic in figure 14 outlines the interaction between the fault monitors and the power-good signal. (eq. 16) t d2 1.1 r ? ss 810 3 ? s () ?? = (eq. 17) t d4 v vid 1.1 ? r ss 810 3 ? s () ??? = figure 12. amd soft-start waveforms v out , 500mv/div en 500s/div t da t db pgood (eq. 18) t db v vid r ? ss 810 3 ? s () ?? = table 5. isl6314 soft_start timing summary mode time slot time vr11 t d1 1.1ms vr11 t d2 equation 16 vr11 t d3 93s vr11 t d4 equation 17 vr11 t d5 93s amd t da 1.1ms amd t db equation 18 figure 13. soft-start waveforms for isl6314-based converter en (5v/div) v out (0.5v/div) gnd> t1 gnd> t2 t3 output precharged below dac level output precharged above dac level isl6314
22 fn6455.2 october 8, 2009 . power-good signal the power-good pin (pgood) is an open-drain logic output that signals whether or not the isl6314 is regulating the output voltage within the proper levels, and whether any fault conditions exist. this pin should be tied through a resistor to a voltage source that?s equal to or less than vcc. for intel mode of operation, pgood indicates whether vsen is within specified overvoltage and undervoltage limits after a fixed delay from the end of soft-start. pgood transitions low when an undervoltage, overvoltage, or overcurrent condition is detected or when the controller is disabled by a reset from en, por, or one of the no-cp u vid codes. in the event of an overvoltage or overcurrent condition, or a no-cpu vid code, the controller latches off and pgood will not return high until en is toggled and a successful soft-start is completed. in the case of an undervoltage event, pgood will return high when the output voltage rises above the undervoltage hysteresis level. pgood is always low prior to the end of soft-start. for amd modes of operation, pgood will always be high as long as vsen is within the specified undervoltage/overvoltage window and soft-start has ende d. pgood only goes low if vsen is outside this window. ev en if the controller is shut down the pgood signal will still stay high until vsen falls below the undervoltage threshold. overvoltage protection the isl6314 constantly monitors the difference between the vsen and rgnd voltages to detect if an overvoltage event occurs. during soft-start, whil e the dac is ramping up, the overvoltage trip level is the hi gher of a fixed voltage 1.27v or dac + 175mv for intel modes of operation and dac + 225mv for amd modes of operation. upon successful soft-start, the overvoltage trip level is onl y dac + 175mv or dac + 225mv depending on whether the controller is running in intel or amd mode. when the output voltage rises above the ovp trip level actions are taken by the isl6314 to protect the microprocessor load. at the inception of an over voltage event, lgate is commanded high and the pgood signal is driven low. this turns on the lower mosfets and pulls the output voltage below a level that might cause damage to the load. the lgate output remain s high until vsen fa lls 100mv below the ovp threshold that tripped the overvoltage protection circuitry. the isl6314 will continue to protect the load in this fashion as long as the overvoltage condition recurs. once an overvoltage condition ends, the isl6314 latches off, and must be reset by toggling en, or through por, before a soft-start can be reinitiated. there is an ovp condition that ex ists that will not latch off the isl6314. during a soft-start sequence, if the vsen voltage is above the ovp threshold an overvoltage event will occur, but will be released once vsen fa lls 100mv below the ovp threshold. if vsen then rises above the ovp trip threshold a second time, the isl6314 will be latched off and cannot be restarted until the controller is reset. pre-por overvoltage protection prior to pvcc and vcc exceeding their por levels, the isl6314 is designed to protect the load from any overvoltage events that may occur. this is accomplished by means of an internal 10k resistor tied from phase to lgate, which turns on the lower mosfet to control the output voltage until the overvoltage event ceases or the input power supply cuts off. for complete protection, the low side mosfet should have a gate threshold well below the maximum voltage rating of the load/micropr ocessor. in the event that during normal operation the pvcc or vcc voltage falls back below the por threshold, the pre-por overvoltage protection circuitry reactivates to protect from any more pre-por overvoltage events. undervoltage detection the undervoltage threshold is set at dac - 350mv of the vid code. when the output voltage (v sen - r gnd ) is below the undervoltage threshold, pgood gets pulled low. no other action is taken by the controller. pgood will return high if the output voltage rises above dac - 250mv. figure 14. power-good and protection circuitry - + vid + offset mv vsen - + vid - offset mv ov uv pgood soft-start, fault and control logic - + oc - + isen isen+ isen- iseno ocset r ocset + - v droop v ocset + - v ovp 100a isl6314 internal circuitry - + rgnd x1 - + +1v vdiff isl6314
23 fn6455.2 october 8, 2009 open sense line protection in the case that ei ther of the remote sense lines (vsen or rgnd) become open, the isl6314 is designed to prevent the controller from regulating. this is accomplished by means of a small 5a pull-up current on vsen, and a pull-down current on rgnd. if the sense lines are opened at any time, the voltage difference between v sen and r gnd will increase until an overvolt age event occurs, at which point overvoltage protection activates and the controller stops regulating. the isl6314 will be latched off and cannot be restarted until the controller is reset. overcurrent protection the isl6314 detects overcurrent events by comparing the droop voltage, v droop , to the ocset voltage, v ocset , as shown in figure 14. the droop voltage, set by the external current sensing circuitry, is pro portional to the output current as shown in equation 19. a constant 100a flows through r ocset , creating the ocset voltage. when the droop voltage exceeds the ocset voltage, the overcurrent protection circuitry activates. since the droop voltage is proportional to the output curren t, the overcurrent trip level, i max , can be set by selecting the proper value for r ocset , as shown in equation 20. once the output current exceeds the overcurrent trip level, v droop will exceed v ocset , and a comparator will trigger the converter to begin overcu rrent protection procedures. at the beginning of an overcurrent shutdown, the controller turns off both upper and lower mosfets and lowers pgood. the controller will then immediately attempt to soft-start (which includes the 1.1ms delay of either t d1 or t da ). if the overcurrent fault remains, the trip-retry cycles will continue until either the controller is disabled or the fault is cleared. but if five overcurrent events occur without successfully completing soft-start, the controller will latch off after the fifth try and must be reset by toggling en before a soft-start can be reinitiated. note that the energy delivered during trip-retry cycling is much less than during full-load operation, so there is no thermal hazard. figure 15 shows an example. general design guide this design guide is intended to provide a high-level explanation of the steps necessary to create a power converter. it is assumed that the reader is familiar with many of the basic skills and techniques referenced in the following. in addition to this guide, intersil provides complete reference designs that include schematics, bills of materials, and example board layouts for all common microprocessor applications. power stage the first step in designing a power converter using the isl6314 is to determine if one phase is sufficient (if not, intersil offers other parts, such as the isl6313, which has two phases with similar features). this determination depends heavily on the cost analysis which in turn depends on system constraints that differ from one design to the next. principally, the designer will be concerned with whether components can be mounted on both sides of the circuit board, whether through-hole co mponents are permitted, the total board space available for power-supply circuitry, and the maximum amount of load current. generally speaking, the most economical solutions are those in which the output handles between 25a and 30a. all surface-mount designs will tend toward the lower end of this current range. if through-hole mosfets and inductors can be used, higher currents are possible. in cases where board space is the limiting constraint, current can be pushed as high as 40a, but these designs require heat sinks and forced air to cool the mosfets, inductors and heat-dissipating surfaces. mosfets the choice of mosfets depends on the current each mosfet will be required to con duct, the switching frequency, the capability of the mosfets to dissipate heat, and the availability and nature of heat sinking and air flow. (eq. 19) v droop r comp r s --------------------- i out dcr ?? = (eq. 20) r ocset i max r comp dcr ?? 100 ar s ? ---------------------------------------------------------- = figure 15. overcurrent behavior in hiccup mode 0a 0v 1ms/div output current, 25a/div output voltage, 500mv/div isl6314
24 fn6455.2 october 8, 2009 lower mosfet power calculation the calculation for power loss in the lower mosfet is simple, since virtually all of the loss in the lower mosfet is due to current conducted through the channel resistance (r ds(on) ). in equation 21, i m is the maximum continuous output current, i pp is the peak-to-peak inductor current (see equation 1), and d is the duty cycle (v out /v in ). an additional term can be added to the lower-mosfet loss equation to account for additional loss accrued during the dead time when inductor current is flowing through the lower-mosfet body diode. this term is dependent on the diode forward voltage at i m , v d(on) , the switching frequency, f s , and the length of dead times, t d1 and t d2 , at the beginning and the end of the lower-mo sfet conduction interval respectively. note th at the dead times t d1 and t d2 in equation 22 are not related to the soft-start timing delays. the total maximum power dissipated in each lower mosfet is approximated by the summation of p low(1) and p low(2) . upper mosfet power calculation in addition to r ds(on) losses, a large portion of the upper-mosfet losses are due to currents conducted across the input voltage (v in ) during switching. since a substantially higher portion of the upper-mosfet losses are dependent on switching frequency, the power calculation is more complex. upper mosfet losses can be divided into separate components involving the upper-mosfet switching times, the lower-mosfet body-diode reverse-recovery charge, q rr , and the upper mosfet r ds(on) conduction loss. when the upper mosfet turns off, the lower mosfet does not conduct any portion of the inductor current until the voltage at the phase node falls below ground. once the lower mosfet begins conducting, the current in the upper mosfet falls to zero as the current in the lower mosfet ramps up to assume the full inductor current. in equation 23, the required time for this commutation is t 1 and the approximated associated power loss is p up(1). . at turn on, the upper mosfet begins to conduct and this transition occurs over a time t 2 . in equation 24, the approximate power loss is p up(2). . a third component involves the lower mosfet reverse-recovery charge, q rr . since the inductor current has fully commutated to the upper mosfet before the lower-mosfet body diode can recover all of q rr , it is conducted through the upper mosfet across vin. the power dissipated as a result is p up(3) , as shown in equation 25. finally, the resistive part of the upper mosfet is given in equation 26 as p up(4). . the total power dissipated by the upper mosfet at full load can now be approximated as the summation of the results from equations 23, 24, 25 and 26. since the power equations depend on mosfet parameters, choosing the correct mosfets can be an it erative process involving repetitive solutions to the loss equations for different mosfets and different switching frequencies. package power dissipation when choosing mosfets it is important to consider the amount of power being dissipa ted in the integrated drivers located in the controller. since there is one set of drivers in the controller package, the tota l power dissipated by it must be less than the maximum allowable power dissipation for the qfn package. calculating the power dissipation in the drivers for a desired application is critical to ensure safe operation. exceeding the maximum allowable power dissipation level will push the ic beyond the maximum recommended operating junction temperature of +125c. the maximum allowable ic power dissipation for the 5x5 qfn package is approximately 3w at room temperature. see ?layou t considerations? on page 29 for thermal transfer improvement suggestions. when designing the isl6314 into an application, it is recommended that the following calculation is used to ensure safe operation at the desired frequency for the selected mosfets. the total gate drive power losses, p qg_tot , due to the gate charge of mosfets and the integrated driver?s internal circuitry and their corresponding average driver current can be estimated with equations 27 and 28, respectively. (eq. 21) p low 1 () r ds on () i m n ----- - ?? ?? ?? 2 1d ? () ? i lp-p () 2 1d ? () ? 12 --------------------------------------- - + ? = (eq. 22) p low 2 () v don () f s i m n ------ i p-p 2 ----------- + ?? ?? ?? t d1 ? i m n ------ i p-p 2 ----------- ? ?? ?? ?? ?? t d2 ? + ?? = (eq. 23) p up 1 () v in i m n ----- - i p-p 2 ---------- + ?? ?? t 1 2 ---- ?? ?? ?? f s ??? (eq. 24) p up 2 () v in i m n ----- - i p-p 2 ---------- ? ?? ?? ?? t 2 2 ---- ?? ?? ?? f s ??? (eq. 25) p up 3 () v in q rr f s ?? = (eq. 26) p up 4 () r ds on () d i m n ----- - ?? ?? ?? 2 i p-p 2 12 ---------- + ?? isl6314
25 fn6455.2 october 8, 2009 . in equations 27 and 28, p qg_q1 is the total upper gate drive power loss and p qg_q2 is the total lower gate drive power loss; the gate charge (q g1 and q g2 ) is defined at the particular gate to source drive voltage pvcc in the corresponding mosfet data sheet; i q is the driver total quiescent current with no load at both drive outputs; n q1 and n q2 are the number of upper and lower mosfets respectively. the i q* vcc product is the quiescent power of the controller without capacitive load and is typically 75mw at 300khz. the total gate drive power loss es are dissipated among the resistive components along the transition path and in the bootstrap diode. the portion of the total power dissipated in the controller itself is the pow er dissipated in the upper drive path resistance, p dr_up , the lower drive path resistance, p dr_up , and in the boot strap diode, p boot . the rest of the power will be dissipated by the external gate resistors (r g1 and r g2 ) and the internal gate resistors (r gi1 and r gi2 ) of the mosfets. figures 16 and 17 show the typical upper and lower gate drives turn-on transition path. the total power dissipation in the controller itself, p dr , can be roughly estimated as shown in equation 29: inductor dcr current sensing component selection for accurate load line regulation, the isl6314 senses the total output current by detect ing the voltage across the output inductor dcr (as described in ?load-line (droop) regulation? on page 16). as figure 18 illustrates, an r-c network is required to accurately sense the inductor dcr voltage and convert this information into a ?droop? voltage, which is proportional to the total output current. choosing the components for this current sense network is a two step process. first, r comp and c comp must be chosen so that the time constant of this r comp - c comp network matches the time cons tant of the inductor l/dcr. then the resistor r s must be chosen to set the current sense network gain, obtaining the desired full load droop voltage. follow the steps outlined in the following to choose the component values for this r-c network. figure 16. typical upper-gate drive turn-on path figure 17. typical lower-gate drive turn-on path p qg_tot p qg_q1 p qg_q2 i q vcc ? ++ = (eq. 27) p qg_q1 3 2 -- - q g1 pvcc f sw n q1 ?? ?? = p qg_q2 q g2 pvcc f sw n q2 ??? = i dr 3 2 -- - q g1 n ? q1 ? q g2 n q2 ? + ?? ?? f sw i q + ? = (eq. 28) q1 d s g r gi1 r g1 boot r hi1 c ds c gs c gd r lo1 phase pvcc ugate pvcc q2 d s g r gi2 r g2 r hi2 c ds c gs c gd r lo2 lgate p dr p dr_up p dr_low p boot i q vcc ? () +++ = (eq. 29) p dr_up r hi1 r hi1 r ext1 + -------------------------------------- r lo1 r lo1 r ext1 + ---------------------------------------- + ?? ?? ?? p qg_q1 3 --------------------- ? = p dr_low r hi2 r hi2 r ext2 + -------------------------------------- r lo2 r lo2 r ext2 + ---------------------------------------- + ?? ?? ?? p qg_q2 2 --------------------- ? = r ext1 r g1 r gi1 n q1 ------------- + = r ext2 r g2 r gi2 n q2 ------------- + = p boot p qg_q1 3 --------------------- = figure 18. dcr sensing configuration - + iseno dcr l inductor v out c out i l - + v l (s) phase r s r comp c comp isen- isen+ isl6314 - + v droop i out (optional) isl6314
26 fn6455.2 october 8, 2009 1. choose an arbitrary value for c comp . the recommended value is 0.01f. 2. plug the inductor l and dcr component values, and the values for c comp chosen in step 1, into equation 30 to calculate the value for r comp . 3. use the new value for r comp obtained from equation 30, as well as the desired full load current, i fl , full load droop voltage, v droop , and inductor dcr in equation 31 to calculate the value for r s . due to errors in the inductance or dcr it may be necessary to adjust the value of r 1 to match the time constants correctly. the effects of time co nstant mismatch can be seen in the form of droop overs hoot or undershoot during the initial load transient spike, as shown in figure 19. follow the steps outlined in the following to ensure the r-c and inductor l/dcr time constants are matched accurately. 1. capture a transient event with the oscilloscope set to about l/dcr/2 (sec/div). fo r example, with l = 1h and dcr = 1m , set the oscilloscope to 500s/div. 2. record v1 and v2 as shown in figure 19. 3. select new values, r 1,new , for the time constant resistor based on the original value, r 1,old , using equation 32. 4. replace r 1 with the new value and check to see that the error is corrected. repeat the procedure if necessary. loadline regulation resistor if loadline regulation is desired, the resistor on the fs pin, r t , should be connected to ground (the value of r t separately selects the switching frequency, as per equation 42). the desired loadline, r ll , can be calculated by equation 33 where v droop is the desired droop voltage at the full load current i fl . based on values for equation 31, the desired loadline can also be calculated from equation 34. if no loadline regulation is required, the resistor on the fs pin, r t , should be connected to the vcc pin (the value of r t separately selects the switching frequency, as per equation 42). apa pin component selection a 100a current flows out of the apa pin and across r apa to set the apa trip leve l. a 1000pf capacitor, c apa , should also be placed across the r apa resistor to help with noise immunity. an apa trip level of 500mv is recommended for most applications. use equation 35 to set r apa to get the desired apa trip level. compensation the two opposing goals of compensating the voltage regulator are stability and speed. depending on whether the regulator employs the optional load-line regulation as described in load-line regulation, there are two distinct methods for achieving these goals. compensation with load-line regulation the load-line regulated converter behaves in a similar manner to a peak current m ode controller because the two poles at the output filt er l-c resonant frequency split with the introduction of current informat ion into the control loop. the final location of th ese poles is determ ined by the system function, the gain of the current signal, and the value of the compensation components, r c and c c , as shown in figure 20. (eq. 30) r comp l dcr c comp ? --------------------------------------- = (eq. 31) r s i fl v droop ------------------------ - r comp dcr ?? = r 1new , r 1old , v 1 v 2 ---------- ? = (eq. 32) figure 19. time constant mismatch behavior v 1 v out i tran v 2 i r ll v droop i fl ------------------------ - = (eq. 33) (eq. 34) r ll r comp dcr ? r s --------------------------------------- = r apa v apa trip , 100 10 6 ? ------------------------------ - 500mv 100 10 6 ? ---------------------------- - 5k === (eq. 35) isl6314
27 fn6455.2 october 8, 2009 since the system poles and zero are affected by the values of the components that are meant to compensate them, the solution to the system equatio n becomes fairly complicated. fortunately, there is a simple approximation that comes very close to an optimal solution. tr eating the system as though it were a voltage-mode regulator, by compensating the l-c poles and the esr zero of the voltage mode approximation, yields a solution that is always stable with very close to ideal transient performance. select a target bandwidth fo r the compensated system, f 0 . the target bandwidth must be large enough to assure adequate transient performance, but smaller than 1/3 of the switching frequency. the values of the compensation components depend on the relationships of f 0 to the l-c pole frequency and the esr zero frequency. for each of the following three, there is a separate set of equations for the compensation components. in equation 36, l is th e filter inductance; c is the sum total of all output capacitors; esr is the equivalent series resistance of the bulk output filter capacitance; and v p-p is the peak-to-peak sawtooth signal amplitude, as described in the ?electrical specifications? on page 6. once selected, the compensation values in equation 36 assure a stable converter with reasonable transient performance. in most cases, transient performance can be improved by making adjustments to r c . slowly increase the value of r c while observing the transient performance on an oscilloscope until no further improvement is noted. normally, c c will not need adjustment. keep the value of c c from equation 36 unless some performance issue is noted. the optional capacitor c 2 , is sometimes needed to bypass noise away from the pwm comparator (see figure 20). keep a position available for c 2 , and be prepared to install a high-frequency capacitor of between 22pf and 150pf in case any leading edge jitter problem is noted. for the solutions in equation 36, r fb is selected arbitrarily, typically in the 1k to 5k range. compensation without load-line regulation the non load-line regulated converter is accurately modeled as a voltage-mode regulator with two poles at the l-c resonant frequency and a zero at the esr frequency. a type iii controller, as shown in figure 21, provides the necessary compensation. the first step is to choose the desired bandwidth, f 0 , of the compensated system. choose a frequency high enough to assure adequate transient per formance but not higher than 1/3 of the switching frequency. the type-iii compensator has an extra high-frequency pole, f hf . this pole can be used for added noise rejection or to assure adequate attenuation at the error-amplifier high-order pole and zero frequencies. a good general rule is to choose f hf =10f 0 , but it can be higher if desired. choosing f hf to be lower than 10f 0 can cause problems with too much phase shift below the system bandwidth. figure 20. compensation configuration for load-line regulated isl6314 circuit isl6314 comp c c r c r fb fb vdiff c 2 (optional) 1 2 lc ? ?? ------------------------------- -f 0 > r c r fb 2 f 0 v p-p lc ? ?? ? ? v in ---------------------------------------------------------- ? = c c v in 2 v p-p r fb f 0 ?? ? ? ----------------------------------------------------- - = case 1: 1 2 lc ? ?? ------------------------------- - f 0 1 2 c esr ?? ? ------------------------------------- < r c r fb v p-p 2 ? () ? 2 f 0 2 lc ??? v in ----------------------------------------------------------------- - ? = c c v in 2 ? () 2 f 0 2 v p-p r fb lc ? ?? ? ? -------------------------------------------------------------------------------------- - = case 2: (eq. 36) f 0 1 2 c esr ?? ? ------------------------------------- > r c r fb 2 f 0 v p-p l ?? ? ? v in esr ? --------------------------------------------- - ? = c c v in esr c ?? 2 v p-p r fb f 0 l ?? ? ? ? ----------------------------------------------------------------- - = case 3: isl6314
28 fn6455.2 october 8, 2009 . in the solutions to the compensation equations, there is a single degree of freedom. for the solutions presented in equation 37, r fb is selected arbitrarily, typically in the 1k to 5k range. the remaining compensation components are then selected according to equation 37. in equation 37, l is th e filter inductance; c is the sum total of all output capacitors; esr is the equivalent-series resistance of the bulk output-filter capacitance; and v p-p is the peak-to-peak sawtooth signal amplitude as described in the ?electrical specifications? on page 6. output filter design the output inductors and the output capacitor bank together to form a low-pass filter re sponsible for smoothing the pulsating voltage at the phase node. the output filter also must provide the transient ene rgy until the regulator can respond. because it has a low bandwidth compared to the switching frequency, the outp ut filter limits the system transient response. the output capacitors must supply or sink load current while the current in the output inductor increases or decreases to meet the demand. in high-speed converters, the out put capacitor bank is usually the most costly (and often the largest) part of the circuit. output filter design begins with minimizing the cost of this part of the circuit. the critical load parameters in choosing the output capacitors are the maximum size of the load step, i, the load-current slew rate, di/dt, and the maximum allowable output-voltage deviation under transient loading, v max . capacitors are characterized according to their capacitance, esr, and esl (equivalent series inductance). at the beginning of the load tr ansient, the output capacitors supply all of the transient cu rrent. the output voltage will initially deviate by an amount approximated by the voltage drop across the esl. as the load current increases, the voltage drop across the esr increases linearly until the load current reaches its final value. the capacitors selected must have sufficiently low esl and esr so that the total output-voltage deviation is less than the allowable maximum. neglecting the contribution of inductor current and regulator response, equation 38 shows the output voltage initially deviates by an amount as expressed in equation 38: the filter capacitor must have sufficiently low esl and esr so that v < v max . most capacitor solutions rely on a mixture of high frequency capacitors with relatively lo w capacitance in combination with bulk capacitors having high capacitance but limited high-frequency performance. minimizing the esl of the high-frequency capacitors allows them to support the output voltage as the current increases. minimizing the esr of the bulk capacitors allows them to supply the increased current with less output voltage deviation. the esr of the bulk capacitors also creates the majority of the output-voltage ripple. as th e bulk capacitors sink and source the inductor ac ripple current (see ?output ripple? on page 10 and equation 39), a voltage develops across the bulk capacitor esr equal to i c(p-p ) (esr). thus, once the output capacitors are selected, the maximum allowable ripple voltage, v p-p(max) , determines the lower limit on the inductance. since the capacitors are supplying a decreasing portion of the load current while the regulator recovers from the transient, the capacitor voltage becomes slightly depleted. the output inductor must be ca pable of assuming the entire load current before the output voltage decreases more than v max . this places an upper limit on inductance. equation 40 gives the upper limit on l for the cases when the trailing edge of the current transient causes a greater output-voltage deviation than the leading edge. equation 41 c c v in 2 f hf lc ? 1 ? ?? ? () ? 2 ? () 2 f 0 f hf lc ? () r fb v p-p ?? ? ? ? ----------------------------------------------------------------------------------------------------- = r c v pp 2 ?? ?? ? 2 f 0 f hf lcr fb ?? ??? v in 2 f hf lc ? 1 ? ?? ? () ? ---------------------------------------------------------------------------------------- - = r 1 r fb cesr ? lc ? c esr ? ? ------------------------------------------- - ? = c 1 lc ? c esr ? ? r fb ------------------------------------------- - = c 2 v in 2 ? () 2 f 0 f hf lc ? () r fb v p-p ?? ? ? ? ----------------------------------------------------------------------------------------------------- = (eq. 37) figure 21. compensation circuit without load-line regulation isl6314 comp c c r c r fb fb vdiff c 2 c 1 r 1 vesl di dt ---- - ? esr i ? + (eq. 38) l esr v in v out ? ?? ?? v out ? f s v in v p-p max () ?? ---------------------------------------------------------- ? (eq. 39) isl6314
29 fn6455.2 october 8, 2009 addresses the leading edge. normally, the trailing edge dictates the selection of l because duty cycles are usually less than 50%. nevertheless, both inequalities should be evaluated, and l should be selected based on the lower of the two results. in each equati on, l is the inductance, and c is the total output capacitance. switching frequency there are a number of variables to consider when choosing the switching frequency, as there are considerable effects on the upper mosfet loss calculation. these effects are outlined in ?mosfets? on page 23, and they establish the upper limit for the switching frequency. the lower limit is established by the requirement for fast transient response and small output-voltage ripple. choose the lowest switching frequency that allows the regulator to meet the transient-response requirements. switching frequency is determined by the selection of the frequency-setting resistor, r t . figure 22 and equation 42 are provided to assist in selecting the correct value for r t . input capacitor selection the input capacitors are responsible for sourcing the ac component of the input current flowing into the upper mosfets. their rms current capa city must be sufficient to handle the ac component of t he current drawn by the upper mosfets which is related to duty cycle and the number of active phases. use figure 23 to determine the input-capacitor rms current requirement set by the duty cycle, maximum sustained output current (i o ), and the ratio of the peak-to-peak inductor current (i l(p-p) ) to i o . select a bulk capacitor with a ripple current rating which will minimize the total number of input capacitors required to support the rms current calculated. the voltage rating of the capacitors should also be at least 1.25x greater than the maximum input voltage. . low capacitance, high-frequency ceramic capacitors are needed in addition to the input bulk capacitors to suppress leading and falling edge voltage spikes. the spikes result from the high current slew rate produced by the upper mosfet turn on and off. select low esl ceramic capacitors and place one as close as possible to each upper mosfet drain to minimize board parasitics and maximize suppression. layout considerations mosfets switch very fast and efficiently. the speed with which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. these voltage spikes can degrade efficiency, radiate noise into the circuit and lead to device overvoltage stress. careful component selection, layout, and placement minimizes these voltage spikes. consider, as an example, the turnoff transition of the upper pwm mosfet. prior to turn-off, the upper mosfet was carrying channel current. during the turn-off, current stops flowing in the upper mosfet and is picked up by the lower mosfet. any inductance in the switched current path generates a large voltage spike during the switching interval. careful component selection, tight layout of the critical components, and short, wide circuit traces minimize the magnitude of voltage spikes. there are two sets of crit ical components in a dc/dc converter using a isl6314 controller. the power components are the most critical because they switch large amounts of energy. next, are small signal components that connect to sensitive nodes or supply critical bypassing current and signal coupling. l 2cv o ?? i () 2 ------------------------ - v max iesr ? () ? ? (eq. 40) l 1.25 c ? i () 2 ------------------- - v max i esr ? () ? v in v o ? ?? ?? ?? (eq. 41) r t 10 10.61 1.035 f s () log ? () ? [] = (eq. 42) figure 22. r t vs switching frequency 10 100 500 50 100 1k 2k switching frequency (khz) r t (k ) figure 23. normalized input-capacitor rms current for single-phase converter 00.4 1.0 0.2 0.6 0.8 duty cycle (v o /v in ) input-capacitor current (i rms /i o ) 0.6 0.2 0 0.4 i l(p-p) = 0 i l(p-p) = 0.5 i o i l(p-p) = 0.75 i o isl6314
30 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6455.2 october 8, 2009 the power components should be placed first, which include the mosfets, input and output capacitors, and the inductor. keep the gate drive traces short, resulting in low trace impedances. when placing the mosfets try to keep the source of the upper fets and the drain of the lower fets as close as thermally possible. input bulk capacitors should be placed close to the drain of the upper fe ts and the source of the lower fets. locate the output inductor and output capacitors between the mosfets and the load. the high-frequency input and output decoupling capacitors (ceramic) should be placed as close as practicable to the decoupling target, making use of the shortest connection paths to any internal planes, such as vias to gnd next to, or on the capacitor solder pad. the critical small components include the bypass capacitors for vcc and pvcc, and many of the components surrounding the controller including the feedback network and current sense components. locate the vcc and pvcc bypass capacitors as close to the isl6314 as possible. it is especially important to locate the components associated with the feedback circuit close to their respective controller pins, since they belong to a high-impedance circuit loop, sensitive to emi pick-up. a multi-layer printed circuit board is recommended. figure 24 shows the connections of the critical components for the converter. note that capacitors c xxin and c xxout could each represent numerous physical capacitors. dedicate one solid layer, usually the one underneath the component side of the board, for a ground plane and make all critical component ground connections with vias to this layer. dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. keep the metal runs from the phase termina l to output in ductor short. the power plane should support the input power and output power nodes. use copper filled po lygons on the top and bottom circuit layers for the phase nod e. use the remaining printed circuit layers for small signal wiring. routing ugate, lgate, and phase traces great attention should be paid to routing the ugate, lgate, and phase traces since they drive the power train mosfets using short, high current pulses. it is important to size them as large and as short as possible to reduce their overall impedance and inductance. they s hould be sized to carry at least one ampere of current (0.02? to 0.05?). going between layers with vias should also be avoided, but if so, use two vias for interconnection when possible. extra care should be given to the lgate traces in particular since keeping their impedance and inductance low helps to significantly reduce the possibilit y of shoot-through. it is also important to route each channels ugate and phase traces in as close proximity as possible to reduce their inductances. current sense component placement and trace routing one of the most critical aspec ts of the isl6314 regulator layout is the placement of the inductor dcr current sense components and traces. the r-c current sense components must be placed as close to their respective isen+ and isen- pins on the isl6314 as possible. the sense traces that connect the r-c sense components to each side of the output induc tors should be routed on the bottom of the board, away from the noisy switching components located on the top of the board. these traces should be routed side by side, and they should be very thin traces. it?s important to route these traces as far away from any other noisy traces or pla nes as possible. these traces should pick up as little noise as possible. thermal management for maximum thermal performanc e in high current, high switching frequency applicatio ns, connecting the thermal gnd pad of the isl6314 to the ground plane with multiple vias is recommended. this heat spreading allows the part to achieve its full thermal potential. it is also recommended that the controller be placed in a direct path of airflow if possible to help thermally manage the part. isl6314
31 fn6455.2 october 8, 2009 figure 24. printed circuit board power planes and islands vid4 vid5 pgood vid3 vid2 vid1 vcc isl6314 vid0 fs ofs ref load en gnd vid6 vid7 ss +5v fb comp vsen rgnd +12v phase ugate boot lgate pvcc apa ocset isen- iseno isen+ vdiff dvc r comp c comp r s r ocset locate close to ic (minimize connection path) via connection to ground plane island on power plane layer island on circuit plane layer key heavy trace on circuit plane layer locate near switchi ng transistors; (minimize connection path) locate near load; (minimize connection path) r 1 c 1 c 3 r fb c 2 r 2 r dvc c dvc r apa r ofs r t c ref r ss (cf1) c boot c bin (chfin) (cf2) (c hfout ) c bout c apa isl6314
32 fn6455.2 october 8, 2009 isl6314 package outline drawing l32.5x5b 32 lead quad flat no-lead plastic package rev 2, 11/07 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view 5.00 a 5.00 b index area pin 1 6 (4x) 0.15 32x 0.40 0.10 4 a 32x 0.23 m 0.10 c b 16 9 4x 0.50 28x 3.5 6 pin #1 index area 3 .30 0 . 15 0 . 90 0.1 base plane see detail "x" seating plane 0.10 c c 0.08 c 0 . 2 ref c 0 . 05 max. 0 . 00 min. 5 ( 3. 30 ) ( 4. 80 typ ) ( 28x 0 . 5 ) (32x 0 . 23 ) ( 32x 0 . 60) + 0.07 - 0.05 17 25 24 8 1 32

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