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features description applications ads7863 sbas383 ? june 2007 dual, 1.5msps, 12-bit, 2 + 2 channel, simultaneous sampling analog-to-digital converter four fully- or six pseudo-differential inputs the ads7863 is a dual, 12-bit, 1.5msps, analog-to-digital converter (adc) with four fully sinad: 70db (min), thd: ?75db (max) differential input channels grouped into two pairs for programmable and buffered internal 2.5v high-speed, simultaneous signal acquisition. inputs reference to the sample-and-hold (s/h) amplifiers are fully flexible power-down features differential and are maintained differential to the input of the adc. this architecture provides excellent variable power supply ranges common-mode rejection of 80db at 50khz, which is low power operation: 40mw at 5v a critical performance characteristic in noisy operating temperature range: ?40 c to environments. +125 c the ads7863 is pin-compatible with the ads8361 , pin-compatible with ads7861 and ads8361 but offers additional features such as a (ssop package) programmable reference output, flexible supply voltage (2.7v to 5.5v for av dd and 1.65v to 5.5v for bv dd ), a pseudo-differential input multiplexer with three channels per adc, and several power-down motor control features. multi-axis positioning systems three-phase power control the high-speed, dual serial interface is also pin-compatible with the ads7861 while offering additional flexibility. the ads7863 is offered in an ssop-24 and a 4x4mm qfn-24 package. it is specified over the extended operating temperature range of ?40 c to +125 c. functional block diagram please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. all trademarks are the property of their respective owners. product preview information concerns products in the copyright ? 2007, texas instruments incorporated formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without notice.
ads7863 ads7863 product preview s/h comparator cdac input mux av dd ref in sar s/h comparator cdac input mux ref out agnd sar 10-bit dac 2.5v reference serial interface cha0+ cha0 - cha1+ cha1 - bv dd sdoa sdob m0 m1 sdi clock cs rd busy convst bgnd chb0+ chb0 - chb1+ chb1 -
absolute maximum ratings (1) ads7863 sbas383 ? june 2007 this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ordering information (1) package transport media, product package-lead designator ordering number quantity ads7863idbq tube, 56 ssop-24 dbq ads7863idbqr tape and reel, 2500 ads7863i ads7863irge tape and reel, 250 4x4 qfn-24 rge ADS7863IRGER tape and reel, 3000 (1) for the most current package and ordering information, see the package option addendum at the end of this document or see the ti web site at www.ti.com over operating free-air temperature range, unless otherwise noted. ads7863 unit supply voltage, av dd to agnd ?0.3 to +6 v supply voltage, bv dd to bgnd ?0.3 to +6 v supply voltage, bv dd to av dd 1.5 av dd v analog and reference input voltage with respect to agnd agnd ? 0.3 to av dd + 0.3 v digital input voltage with respect to bgnd bgnd ? 0.3 to bv dd + 0.3 v ground voltage difference |agnd ? bgnd| +0.3 v input current to any pin except supply pins ?10 to +10 ma operating virtual junction temperature range, t j ?40 to +150 c storage temperature range, t stg ?65 to +150 c lead temperature 1.6mm (1/16in) from case for 10s +250 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum rated conditions for extended periods may affect device reliability. 2 submit documentation feedback www.ti.com product preview
recommended operating conditions dissipation ratings thermal characteristics (1) ads7863 sbas383 ? june 2007 over operating free-air temperature range, unless otherwise noted. ads7863 parameter min nom max unit supply voltage, av dd to agnd 2.7 5.0 5.5 v low voltage levels 1.65 3.6 supply voltage, bv dd to bgnd v 5v logic levels 4.5 5.0 5.5 reference input voltage on ref in 0.5 2.5 2.525 v analog differential input voltage (chxx+) ? (chxx?) ?v ref +v ref mv operating ambient temperature range, t a ?40 +125 c derating factor above t a +25 c t a = +70 c t a = +85 c t a = +125 c package t a = +25 c power rating power rating power rating power rating ssop-24 10mw/ c 1250mw 800mw 650mw 250mw qfn-24 22mw/ c 2740mw 1750mw 1420mw 540mw (4mm x 4mm) over operating free-air temperature range, unless otherwise noted. parameter ssop-24 qfn-24 unit low-k thermal resistance 99.8 45.6 ja junction-to-air thermal resistance c/w high-k thermal resistance 61.0 33.1 jc junction-to-case thermal resistance 23.3 35 c/w p diss device power dissipation at 5v 40 40 mw (1) tested in accordance with the low-k or high-k thermal metric definitions of eia/jesd51-3 for leaded surface-mount packages. 3 submit documentation feedback product preview www.ti.com
electrical characteristics ads7863 sbas383 ? june 2007 at t a = ?40 c to +125 c, and av dd = 5v, bv dd = 3.3v, v ref = 2.5v (internal), f clk = 24mhz, and f sample = 1.5msps, unless otherwise noted. ads7863 parameter test conditions min typ (1) max unit resolution 12 bits analog input fsr full-scale differential input range (chxx+) ? (chxx?) ?v ref +v ref v v in absolute input voltage chxx+ or chxx+ to agnd ?0.1 av dd + 0.1 v c in input capacitance chxx+ or chxx? to agnd 2 pf c id differential input capacitance 4 pf i il input leakage current ?1 +1 na cmrr common-mode rejection ratio 80 db dc accuracy inl integral nonlinearity ?1 +1 lsb inl match lsb dnl differential nonlinearity (2) ?1 +1 lsb dnl match lsb v os input offset error ?1 +1 lsb v os match asynchronous to synchronous lsb dv os /dt input offset thermal drift v/ c g err gain error (2) 0.25 % g err match % g err /dt gain error thermal drift ppm/ c psrr power-supply rejection ratio 2.7v < av dd < 5.5v 70 db ac accuracy sinad signal-to-noise + distortion v in = 5v pp at 100khz 70 db snr signal-to-noise ratio v in = 5v pp at 100khz db thd total harmonic distortion v in = 5v pp at 100khz ?75 db sfdr spurious-free dynamic range v in = 5v pp at 100khz 75 db sampling dynamics t conv conversion time per adc 1mhz < f clk 24mhz 0.542 13 s t acq acquisition time 125 ns t data throughput rate 1mhz < f clk 24mhz 62.5 1500 ksps t a aperture delay 6 ns t a match 50 ps t ajit aperture jitter 50 ps f clk clock frequency on clock 1 24 mhz internal voltage reference resolution reference output dac resolution 10 bits over 20%...100% dac range 0.496 2.520 v dac = 0x3ff, v refout reference output voltage 2.480 2.500 2.520 v ?40 c < t a < +125 c dac = 0x3ff at +25 c 2.485 2.500 2.515 v dv refout /dt reference voltage drift 10 ppm/ c ?9.76 9.76 mv dnl dac dac differential nonlinearity ?4 4 lsb ?9.76 9.76 mv inl dac dac integral nonlinearity ?4 4 lsb 9.76 mv v osdac dac offset error v refout = 0.5v 4 lsb (1) all typical values at t a = +25 c. (2) ensured by design, not production tested. 4 submit documentation feedback www.ti.com product preview
ads7863 sbas383 ? june 2007 electrical characteristics (continued) at t a = ?40 c to +125 c, and av dd = 5v, bv dd = 3.3v, v ref = 2.5v (internal), f clk = 24mhz, and f sample = 1.5msps, unless otherwise noted. ads7863 parameter test conditions min typ (1) max unit internal voltage reference, continued psrr power-supply rejection ratio db i refout reference output dc current 1 ma i refsc reference output short-circuit current ma t refon reference output settling time 100 s voltage reference input v ref reference input voltage range 0.5 2.5 2.525 v i ref reference input current 50 a c ref reference input capacitance 10 pf digital inputs logic family cmos v ih high-level input voltage 0.7 bv dd bv dd + 0.3 v v il low-level input voltage ?0.3 0.3 bv dd v i in input current v in = bv dd to bgnd ?50 +50 na c in input capacitance 5 pf digital outputs logic family cmos v oh high-level output voltage i oh = ?100 a bv dd ? 0.2 v v ol low-level output voltage i oh = 100 a 0.2 v i oz high-impedance-state output current v in = bv dd to bgnd ?50 +50 na c out output capacitance 5 pf c load load capacitance 30 pf power supply av dd analog supply voltage av dd to agnd 2.7 5.0 5.5 v bv dd buffer i/o supply voltage bv dd to bgnd 1.65 3.3 5.5 v av dd = 3v 6 7 av dd = 5.5v 7 8 av dd = 3v, nap power-down ai dd analog supply current a av dd = 5.5v, nap power-down av dd = 3v, deep power-down av dd = 5.5v, deep power-down bi dd buffer i/o supply current a av dd = 3v 18.9 p diss power dissipation w av dd = 5.5v 40 5 submit documentation feedback product preview www.ti.com
device information ads7863 sbas383 ? june 2007 ads7863idbq ads7863irg ssop-24 (dbq) 4 x 4 qfn-24 (rge) (top view) (top view) pin descriptions pin number ssop qfn name description 1 17 bgnd buffer i/o ground. connect to digital ground plane. 2 18 chb1+ noninverting analog input channel b1 3 19 chb1? inverting analog input channel b1 4 20 chb0+ noninverting analog input channel b0 5 21 chb0? inverting analog input channel b0 6 22 cha1+ noninverting analog input channel a1 7 23 cha1? inverting analog input channel a1 8 24 cha0+ noninverting analog input channel a0 9 1 cha0? inverting analog input channel a0 10 2 ref in reference voltage input. a ceramic capacitor of 470nf (min) is required at this terminal. 11 3 ref out reference voltage output. the programmable internal voltage reference output is available on this pin. 12 4 agnd analog ground. connect to analog ground plane. 13 5 av dd analog power supply, 2.7v to 5.5v. decouple to agnd with a 1 f ceramic capacitor. 14 6 m1 mode pin 1. selects between the sdox digital outputs (see table 7 ). 15 7 m0 mode pin 0. selects between analog input channels (see table 7 ). serial data input. this pin allows the additional features of the ads7863 to be used but can also be used 16 8 sdi in ads7861-compatible manner. conversion start. the adc switches from the sample into the hold mode on the rising edge of convst, 17 9 convst independent of the status of clock. 18 10 rd read data. synchronization pulse for the sdox outputs and sdi input. rd only triggers when cs is low. 19 11 cs chip select. when low, the sdox outputs are active; when high, the sdox outputs are tri-stated. 20 12 clock external clock input adc busy indicator. busy goes high when the inputs are in hold mode and returns to low after the 21 13 busy conversion has been finished. 22 14 sdob serial data output for converter b. data are valid on the falling edge of clock. serial data output for converter a. when m1 is high, both sdoa and sdob are active. data are valid on 23 15 sdoa the falling edge of clock. 24 16 bv dd buffer i/o supply, 1.65v to 5.5v. decouple to bgnd with a 1 f ceramic capacitor. 6 submit documentation feedback www.ti.com product preview cha0 - ref in ref out agnd av dd m1 chb1+ bgnd bv dd sdoasdob busy 1 2 3 4 5 6 18 17 16 15 14 13 ads7863 cha0+ cha1 - cha1+ chb0 - chb0+ chb1 - 24 m0 sdi convst rd cs clock 7 23 8 22 9 21 10 20 11 19 12 bgnd chb1+ chb1 - chb0+ chb0 - cha1+ cha1 - cha0+ cha0 - ref in ref out agnd 12 3 4 5 6 7 8 9 1011 12 2423 22 21 20 19 18 17 16 15 14 13 bv dd sdoasdob busy clock cs rdconvst sdi m0 m1 av dd
equivalent input circuit timing characteristics ads7863 sbas383 ? june 2007 figure 1. detailed timing diagram (mode i) 7 submit documentation feedback product preview www.ti.com r = 200 w ser r = 50 w sw chxx+ r = 200 w ser r = 50 w sw chxx - c = 5pf par c = 5pf par c = 2pf s c = 2pf s clock convst rd sdi busy cs s rial e d ta a a c1 c0 p1 p0 dp n an rp s4 a2 a1 a0 d10 d11 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 d11 0 0 serial data b d10 d11 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 d11 0 0 c1 c0 p1 t ckh t ckl t 12 t 11 t 1 t 6 t 7 t 5 t 3 t 13 t 8 t 9 t 10 t 2 t 4 t acq t conv conversion 1 conversion 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4
timing requirements (1) ads7863 sbas383 ? june 2007 timing characteristics (continued) note: all convst commands that occur more than 12ns before the rising edge of cycle ?1? of the external clock (region ?a?) initiate a conversion on the rising edge of cycle ?1?. all convst commands that occur tbdns after the rising edge of cycle ?1? or 12ns before the rising edge of cycle 2 (region ?b?) initiate a conversion on the rising edge of cycle ?2?. all convst commands that occur tbdns after the rising edge of cycle ?2? (region ?c?) initiate a conversion on the rising edge of the next clock period. the convst pin should never be switched from low to high in the region 12ns prior to the rising edge of the clock and tbdns after the rising edge (gray areas). if convst is toggled in this gray area, the conversion could begin on either the same rising edge of the clock or the following edge. figure 2. convst timing over recommended operating free-air temperature range at ?40 c to +125 c, av dd = 5v, and bv dd = 2.7v to 5v, unless otherwise noted. ads7863 symbol parameter comments min max unit t conv conversion time f clock = 24mhz 541.67 ns t acq acquisition time f clock = 24mhz 125 ns f clock clock frequency see figure 1 1 24 mhz t clock clock period see figure 1 41.67 1000 ns t ckl clock low time see figure 1 5 ns t ckh clock high time see figure 1 5 ns t 1 convst high time see figure 1 15 ns t 2 sdi setup time to clock falling edge see figure 1 10 ns t 3 sdi hold time to clock falling edge see figure 1 5 ns t 4 rd high setup time to clock falling edge see figure 1 10 ns t 5 rd high hold time to clock falling edge see figure 1 5 ns t 6 convst low time see figure 1 15 ns t 7 rd low time relative to clock falling edge see figure 1 15 ns t 8 cs low to sdox valid see figure 1 20 ns sdox data setup time to clock falling t 9 see figure 1 25 ns edge t 10 sdox data hold time to clock falling edge see figure 1 5 ns convst setup time to rising edge of t 11 see figure 1 12 ns clock t 12 clock rising edge to busy low delay see figure 1 3 ns t 13 cs low to rd high delay see figure 1 10 ns (1) all input signals are specified with t r = t f = 1.5ns (10% to 90% of bv dd ) and timed from a voltage level of (v il + v ih )/2. 8 submit documentation feedback www.ti.com product preview clock convst 12ns cyc el 1 cyc el 2 a b c 12ns tbd tbd
typical characteristics ads7863 sbas383 ? june 2007 at t a = +25 c, +v a + v d = +5v, and v ref = 2.5v (internal), f clk = 8mhz, and f sample = 2mhz, unless otherwise noted. need title vs need title vs need title need title figure 3. figure 4. need title vs need title vs need title need title figure 5. figure 6. need title vs need title vs need title need title figure 7. figure 8. 9 submit documentation feedback product preview www.ti.com
ads7863 sbas383 ? june 2007 typical characteristics (continued) at t a = +25 c, +v a + v d = +5v, and v ref = 2.5v (internal), f clk = 8mhz, and f sample = 2mhz, unless otherwise noted. need title vs need title vs need title need title figure 9. figure 10. need title vs need title vs need title need title figure 11. figure 12. need title vs need title vs need title need title figure 13. figure 14. 10 submit documentation feedback www.ti.com product preview
applications information general description analog analog inputs (1) ads7863 sbas383 ? june 2007 the ads7863 includes two 12-bit analog-to-digital converters (adcs) that operate based on the successive-approximation register (sar) principle. the adcs sample and convert simultaneously. conversion time can be as low as 541.67ns. adding the acquisition time of 125ns results in a maximum conversion rate of 1.5msps. figure 15. input multiplexer configuration each adc has a fully differential, 2:1 multiplexer front-end. in many common applications, all negative table 1. fully differential 2:1 multiplexer input signals remain at the same constant voltage configuration (for example, 2.5v). in this type of application, the c1 c0 adc+ adc? multiplexer can be used in a pseudo-differential 3:1 0 0 chx0+ chx0? mode, where chx0? functions as a common pin and the remaining three inputs (chx0+, chx1?, and 1 1 chx1+ chx1? chx1+) operate as separate inputs referred to the common pin. table 2. pseudo-differential 3:1 multiplexer configuration the ads7863 also includes a 2.5v internal reference. the reference drives a 10-bit c1 c0 adc+ adc? digital-to-analog converter (dac), allowing the 0 0 chx0+ chx0? voltage at the ref out pin to be adjusted via the 0 1 chx1? chx0? serial interface in 2.44mv steps. a low-noise 1 1 chx1+ chx0? operational amplifier with unity gain buffers the dac output voltage and drives the ref out pin. each of the of 2pf sample-and-hold capacitors the ads7863 offers a serial interface that is (shown as c s in the equivalent input circuit ) is compatible with the ads7861 . however, instead of connected via switches to the multiplexer output. the a0 pin of the ads7861 that controls the channel opening the switches holds the sampled data during selection, the ads7863 offers a serial data input the conversion process. after finishing the (sdi) pin that supports additional functions described conversion, both capacitors are pre-charged for the in the digital section of this data sheet. duration of one clock cycle to the voltage present at the ref in pin. after the pre-charging, the multiplexer outputs are connected to the sampling capacitors again. the voltage at the analog input pin is usually this section addresses the analog input circuit, the different from the reference voltage; therefore, the adcs, and the reference design of the device. sample capacitors must be charged to within one-half lsb for 12-bit accuracy during the acquisition time t acq (see the timing characteristics ). each adc is fed by an input multiplexer; see figure 15 . each multiplexer is either used in a acquisition time is indicated with the busy signal fully-differential 2:1 configuration (as described in being held low. it starts by closing the input switches table 1 ) or a pseudo-differential 3:1 configuration (as (after finishing the previous conversion and shown in table 2 ). the channel selection is pre-charging) and finishes with the rising edge of the performed using bits c1 and c0 in the sdi register convst signal. if the ads7863 operates at full (see also the serial data input section). speed, the acquisition time is typically 125ns. the input path for the converter is fully differential the minimum ?3db bandwidth of the driving and provides a common-mode rejection of 80db at operational amplifier can be calculated as shown in 50khz. the high cmrr also helps suppress noise in equation 1 , with n = 12 being the resolution of the harsh industrial environments. ads7863: 11 submit documentation feedback product preview www.ti.com input mux adc+ adc - chx1+ chx1 - chx0+ chx0 - f = - 3db ln(2) (n + 1) 2 t p acq
clock analog-to-digital converter (adc) ads7863 sbas383 ? june 2007 with t acq = 125ns, the minimum bandwidth of the driving amplifier is 11.5mhz. the required bandwidth the adc uses an external clock in the range of can be lower if the application allows a longer 1mhz to 24mhz. 12 clock cycles are needed for a acquisition time. complete conversion; one additional clock cycle is a gain error occurs if a given application does not used for pre-charging the sample capacitors. with a fulfill the settling requirement shown in equation 1 . minimum of 16 clocks required per conversion, three as a result of precharging the capacitors, linearity clock cycles are used for sampling. and thd are not directly affected. the clock duty cycle should be 50%. however, the the opa365 from texas instruments is ads7863 functions properly with a duty cycle recommended; in addition to offering the required between 30% and 70%. bandwidth, it provides a low offset and also offers excellent thd performance. reset the phase margin of the driving operational amplifier the ads7863 features an internal power-on reset is usually reduced by the adc sampling capacitor. a (por) function. however, an external reset can also resistor placed between the capacitor and the be issued using sdi register bits a[2:0] (see the amplifier limits this effect; therefore, an internal 200 w digital section). resistor (r ser ) is placed in series with the switch. the switch resistance (r sw ) is typically 50 w (see ref in equivalent input circuit ). the reference input is not buffered and is directly the differential input voltage range of the adc is connected to the adc. the converter generates v ref , the voltage at the ref in pin. spikes on the reference input voltage because of internal switching. therefore, an external capacitor to it is important to keep the voltage to all inputs within the analog ground (agnd) should be used to the 0.3v limit below agnd and above av dd while stabilize the reference input voltage. this capacitor not allowing dc current to flow through the inputs. should be at least 470nf. ceramic capacitors (x5r current is only necessary to recharge the type) with values up to 1 f are commonly available sample-and-hold capacitors. as smd in 0402 size. ref out the ads7863 includes two sar-type, 1.5msps, the ads7863 includes a low-drift, 2.5v internal 12-bit adcs (shown in the functional block diagram reference source. this source feeds a 10-bit string on the front page of this data sheet). dac that is controlled via the serial interface. as a result of this architecture, the voltage at the ref out convst pin is programmable in 2.44mv steps and can be adjusted to specific application requirements without the analog inputs are held with the rising edge of the the use of additional external components. convst (conversion start) signal. the setup time of convst referred to the next rising edge of clock however, the dac output voltage should not be (system clock) is 12ns (minimum). the conversion programmed below 0.5v to ensure the correct automatically starts with the rising clock edge. functionality of the reference output buffer. this convst should not be issued during a conversion, buffer is connected between the dac and the that is, when busy is high. ref out pin, and is capable of driving the capacitor at the ref in pin. a minimum of 470nf is required to rd (read data) and convst can be shorted to keep the reference stable (see the previous minimize necessary software and wiring. the rd discussion of ref in above). for applications that use signal is triggered by the ads7863 on the falling an external reference source, the internal reference edge of clock. therefore, the combined signals can be disabled using bit rp in the sdi register must be activated with the rising clock edge. the (see the digital section). the settling time of the conversion then starts with the subsequent rising ref out pin is 100 s. the default value of the clock edge. ref out pin after power-up is 2.5v. 12 submit documentation feedback www.ti.com product preview
digital serial data input (sdi) timing and control ads7863 sbas383 ? june 2007 for operation with a 2.7v analog supply and a 2.5v an: autonap power-down enable ('1' = device in reference, the internal reference buffer requires a autonap power-down mode) rail-to-rail input and output. such buffers typically rp: reference power-down ('1' = reference contain two input stages; when the input voltage turned off) passes the mid-range area, a transition occurs at the s4: special read mode for modes ii and iv output because of switching between the two input ('1' = special mode enabled) stages. in this voltage range, rail-to-rail amplifiers generally show a very poor power-supply rejection. table 6. a2, a1, and a0: dac control and device reset as a result of this poor performance, the ads7863 buffer has a fixed transition at dac code 496 a2 a1 a0 function (0x1f0). at this code, the dac may show a jump of 0 0 0 no action up to 10mv in its transfer function. 0 0 1 dac write with next access 0 1 0 no action 0 1 1 dac read with next access this section addresses the timing and control of the 1 0 0 no action ads7863 serial interface. 1 0 1 device reset 1 1 0 no action 1 1 1 no action the serial data input or sdi pin (corresponding to pin a0 on the ads7861) is coupled to rd and clocked all additional features become active with the rising into the ads7863 on each falling edge of clock. edge of the 12th clock signal after issuing the rd the data word length of the sdi register is 12 bits. pulse. table 3 shows the register structure. the data must be transferred msb-first. table 4 through table 6 describe specific bits of this register. the default value of this register after power-up is 0x000. important: consider the detailed timing diagram (figure 1 ) table 3. sdi register contents and convst timing diagram (figure 2 ) shown in the timing characteristics section. for maximum sdi register bit data throughput, the descriptions and diagrams 11 10 9 8 7 6 5 4 3 2 1 0 given in this data sheet assume that the c1 c0 p1 p0 dp n an rp s4 a2 a1 a0 convst and rd pins are tied together. note that they can also be controlled independently. table 4. c1 and c0: channel selection the operation of the ads7863 can be configured in adc a/b four different modes by using the mode pins m0 and c1 c0 positive input negative input m1, as shown in table 7 . 0 0 cha0+ / chb0+ cha0? / chb0? pin m0 sets either manual or automatic channel 0 1 cha1? / chb1? cha0? / chb0? selection. in manual mode, the sdi pin is used to 1 0 cha1+ / chb1+ cha0? / chb0? select between channels chx0 and chx1; in automatic operation, the sdi pin is ignored and 1 1 cha1+ / chb1+ cha1? / chb1? channel selection is controlled by the device after each conversion. pin m1 selects between serial data table 5. p1 and p0: additional features enable being transmitted simultaneously on both outputs p1 p0 function sdoa and sdob for each channel respectively, or using only the sdoa output for transmitting data 0 0 convert both chx0 channels from both channels (see figure 16 through figure 23 0 1 activate additional features and the associated text for more information). 1 0 reserved for factory test (do not use) table 7. m1/m0 truth table 1 1 convert both chx1 channels channel m0 m1 selection sdox used dp: deep power-down enable ('1' = device in deep power-down mode) 0 0 manual (via sdi) sdoa and sdob 0 1 manual (via sdi) sdoa only n: nap power-down enable ('1' = device in nap power-down mode) 1 0 automatic sdoa and sdob 1 1 automatic sdoa only 13 submit documentation feedback product preview www.ti.com
mode i ads7863 sbas383 ? june 2007 additionally, the sdi pin is used for controlling device 16 clock cycles are required to perform a single functionality; see the serial data input section for conversion. with the rising edge of convst, the details. ads7863 switches asynchronously to the external clock from sample to hold mode. converted data on the sdox pins becomes valid with the third falling clock edge after generating an after some delay (t 12 ), the busy output pin goes rd pulse. the following sections explain the four high and remains high for the duration of the different modes of operation in detail. conversion cycle. on the falling edge of the second clock cycle, the ads7863 latches in the channel for the next conversion cycle, depending on the status of the sdi pin. cs must be brought low to with the m0 and m1 pins both set to '0', the enable both serial outputs. data are valid on the ads7863 enters manual channel control operation. falling edge of every 16 clock cycles per conversion. the sdi pin is used to switch between the channels. the first two bits are set to '0'. the subsequent data a conversion is initiated by bringing convst high. contain the 12-bit conversion result (the most significant bit is transferred first), followed by two '0's (see figure 1 and figure 16 ). figure 16. mode i timing diagram (m0 = 0; m1 = 0) 14 submit documentation feedback www.ti.com product preview c[1:0] = '11' convert chx1 next ? p[1:0] = '11' sdi features not used ? c[1:0] = '00' convert chx0 next ? p[1:0] = '00' sdi features not used ? c[1:0] = '00' convert chx0 next ? p[1:0] = '00' sdi features not used ? 0 0 previous 12-bit data chax 12-bit data cha1 high-zhigh-z 12-bit data chb1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 previous conversion of both chxx conversion of both chx1 conversion of both chx0 1.0 s m 0.5 s m 0 s m 1 16 1 16 clock convst sdi m0 m1 rd cs sdoa sdob busy previous 12-bit data chbx
mode ii ads7863 sbas383 ? june 2007 (instead of 16 cycles, if m1 = 0), the ads7863 requires 1 s to perform a complete conversion/read with m0 = 0 and m1 set to '1', the ads7863 also cycle. if the convst signal is issued every 0.5 s operates in manual channel control mode and (which is required for the rd signal) as in mode i, outputs data on the sdoa pin only while sdob is every second pulse is ignored; see figure 17 . set to tri-state. all other pins function in the same manner as they do in mode i. because it takes 32 the output data consist of a '0' followed by an adc clock cycles to output the results from both adcs indicator ('0' for chax or '1' for chbx), 12 bits of conversion results, and another '00'. figure 17. mode ii timing diagram (m0 = 0; m1 = 1) 15 submit documentation feedback product preview www.ti.com every 2nd convst is ignored every 2nd convst is ignored every 2nd convst is ignored c[1:0] = '00' chx0 next ? p[1:0] = '00' no features ? c[1:0] = '11' chx1 next ? p[1:0] = '11' no features ? c[1:0] = '00' chx0 next ? p[1:0] = '00' no features ? c[1:0] = '11' chx1 next ? p[1:0] = '11' no features ? sdi ignored sdi ignored a a a chx b b chx 12-bit data chb1 12-bit data cha0 12-bit data cha0 12-bit data chb0 12-bit data cha1 previous 12-bit data chax data chbx high-z no conversion, read access only no conversion, read access only conversion of both chx0 conversion of both chx1 conversion of both chx0 previous conversion of both chxx 0 s m 0.5 s m 1.0 s m 1.5 s m 2.0 s m 2.5 s m 3.0 s m 1 16 1 16 1 16 1 16 1 16 1 1 clock convst sdi m0 m1 rd cs sdoa sdob busy previous 12-bit data chbx
mode iii ads7863 sbas383 ? june 2007 output data consist of a channel indicator ('0' for chx0 or '1' for chx1), followed by a '0', 12 bits of with m0 set to '1' and m1 = 0, the ads7863 conversion results, and another '00'. automatically cycles between the multiplexer inputs (ignoring the sdi pin) while offering the conversion result of chax on sdoa and the conversion result of chbx on sdob (see figure 18 ). figure 18. mode iii timing diagram (m0 = 1; m1 = 0) 16 submit documentation feedback www.ti.com product preview 1 16 1 16 both channel 0s are converted first,followed by conversion of both channel 1s. c[1:0] is ignored p[1:0] = 00 sdi features are not used ? c[1:0] is ignored p[1:0] = 11 sdi features are not used ? c[1:0] is ignored p[1:0] = 11 sdi features are not used ? previous 12-bit data chax 12-bit data cha0 12-bit data cha1 previous 12-bit data chbx previous 12-bit data chb0 previous 12-bit data chb1 previous conversion of both chxx conversion of both chx0 conversion of both chx1 ch1 ch1 ch0ch0 clock convst sdi m0 m1 rd cs sdoa sdob busy 0 s m 0.5 s m 1.0 s m
mode iv ads7863 sbas383 ? june 2007 output data consist of a channel indicator ('0' for chx0 or '1' for chx1), followed by the adc indicator in the same way as mode ii, mode iv uses the ('0' for chax or '1' for chbx), 12 bits of conversion sdoa output line exclusively to transmit data while results, and ends with '00'. the multiplexer channels are switched automatically. following the first conversion after m1 goes high, the sdob output tri-states (see figure 19 ). figure 19. mode iv timing diagram (m0 = 1 ; m1 = 1) 17 submit documentation feedback product preview www.ti.com every 2nd convst is ignored every 2nd convst is ignored every 2nd convst is ignored c[1:0] is ignored p[1:0] = '00' c[1:0] is ignored p[1:0] = '11' sdi ignored sdi ignored chx b 0 a 1 0 a 1 b 0 a chx 12-bit data chb1 12-bit data cha0 12-bit data cha0 12-bit data chb0 12-bit data cha1 previous 12-bit data chax previous 12-bit data chbx high-z no conversion, read access only no conversion, read access only conversion of both chx0 conversion of both chx1 conversion of both chx0 previous conversion of both chxx 0 s m 0.5 s m 1.0 s m 1.5 s m 2.0 s m 2.5 s m 3.0 s m 1 16 1 16 1 16 1 16 1 16 1 1 clock convst sdi m0 m1 rd cs sdoa sdob busy both channel 0s are converted first,followed by conversion of both channel 1s.
special mode ii (not ads7861-compatible) ads7863 sbas383 ? june 2007 the convst and rd pins can still be tied together, but do not need to be issued every 16 clock for mode ii, a special read mode is available in the cycles. output data are presented on both terminals, ads7863 where both data results can be read out, sdoa and sdob. triggered by a single rd pulse. to activate this mode, bit s4 in the sdi register must be set to '1' the special read mode is not available in mode i or (see also the serial data input section). mode iii. figure 20 illustrates the special read mode. figure 20. special mode ii timing diagram (m0 = 0; m1 = 1; s4 = 1) 18 submit documentation feedback c[1:0] = '00' chx0 ? p[1:0] = '01' features on ? p[1:0] = '01' s4 = '1' ? c[1:0] = '11' chx1 ? p[1:0] = '11' no updates ? p[1:0] = '11' s4 still = '1' ? c[1:0] = '11' chx1 ? p[1:0] = '11' no updates ? p[1:0] = '11' s4 still = '1' ? c[1:0] = '11' chx1 ? p[1:0] = '11' no updates ? p[1:0] = '11' s4 still = '1' ? b a a b a 12-bit data chb1 12-bit data cha1 12-bit data cha0 12-bit data chb0 12-bit data cha1 previous 12-bit data chax previous 12-bit data chbx high-z no conversion, read access only no conversion, read access only conversion of both chx1 conversion of both chx1 conversion of both chx0 previous conversion of both chxx 0 s m 0.5 s m 1.0 s m 1.5 s m 2.0 s m 2.5 s m 3.0 s m 1 16 1 16 1 16 1 16 1 16 1 1 clock convst sdi m0 m1 rd cs sdoa sdob busy www.ti.com product preview
special mode iv (not ads7861-compatible) ads7863 sbas383 ? june 2007 as with special mode ii, these two pins do not need to be issued every 16 clock cycles. data are analogous to special mode ii, the ads7863 also available on the sdoa pin. offers a special read mode for mode iv in which both data results of a conversion can be read, triggered this special read mode (shown in figure 21 ) is not by a single rd pulse. in this case as well, bit s4 in available in mode i or mode iii. the sdi register must be set to '1' while the convst and rd pins can still be tied together . figure 21. special mode iv timing diagram (m0 = 1; m1 = 1; s4 = 1) 19 submit documentation feedback product preview www.ti.com c[1:0] is ignored p[1:0] = '01' features on ? p[1:0] = '01' s4 = '1' ? c[1:0] is ignored p[1:0] = '11' no updates ? p[1:0] = '11' s4 still = '1' ? c[1:0] is ignored p[1:0] = '11' no updates ? p[1:0] = '11' s4 still = '1' ? c[1:0] is ignored p[1:0] = '11' no updates ? p[1:0] = '11' s4 still = '1' ? 0 b 1 a 0 a chx chx 1 b 0 a 12-bit data chb1 12-bit data cha0 12-bit data cha0 12-bit data chb0 12-bit data cha1 previous 12-bit data chax previous 12-bit data chbx high-z no conversion, read access only no conversion, read access only conversion of both chx0 conversion of both chx1 conversion of both chx0 previous conversion of both chxx 0 s m 0.5 s m 1.0 s m 1.5 s m 2.0 s m 2.5 s m 3.0 s m 1 16 1 16 1 16 1 16 1 16 1 1 clock convst sdi m0 m1 rd cs sdoa sdob busy both channel 0s are converted first,followed by conversion of both channel 1s.
pseudo-differential mode i ads7863 sbas383 ? june 2007 for more details, see the serial data input section. (not ads7861-compatible) data are available on both output terminals, sdoa and sdob. in mode i, the ads7863 input multiplexers can also operate in a pseudo-differential manner. in this case, the input multiplexer cannot be used for sdi bits c[1:0] are used to choose the channels pseudo-differential signals in mode iii or mode iv. accordingly. figure 22. pseudo-differential mode i (m0 = 0; m1 = 0) 20 submit documentation feedback www.ti.com product preview c[1:0] = '00' chx0+/chx0 ? - p[1:0] = '00' features off ? c[1:0] = '01' chx1 /chx0 ? - - p[1:0] = '11' features off ? c[1:0] = '10' chx1+/chx0 ? - p[1:0] = '00' features off ? c[1:0] = '00' chx0+/chx0 ? - p[1:0] = '00' features off ? c[1:0] = '01' chx1 /chx0 ? - - p[1:0] = '11' features off ? c[1:0] = '10' chx1+/chx0 ? - p[1:0] = '00' features off ? 12-bit data cha0+/cha0 - 12-bit data cha1 /cha0 - - 12-bit data cha0+/cha0 - 12-bit data cha1 /cha0 - - 12-bit data cha1+/cha0+ previous 12-bit data chax 12-bit data chb0+/chb0 - 12-bit data chb1 /chb0 - - 12-bit data chb0+/chb0 - 12-bit data chb1 /chb0 - - 12-bit data chb1+/chb0+ previous 12-bit data chbx conversion of both chx1+/chx0 - conversion of both chx0+/chx0 - conversion of both chx1 /chx0 - - conversion of both chx1 /chx0 - - conversion of both chx0+/chx0 - previous conversion of both chxx 0 s m 0.5 s m 1.0 s m 1.5 s m 2.0 s m 2.5 s m 3.0 s m 1 16 1 16 1 16 1 16 1 16 1 1 clock convst sdi m0 m1 rd cs sdoa sdob busy
pseudo-differential mode ii ads7863 sbas383 ? june 2007 channel switching is performed by setting the c[1:0] (not ads7861-compatible) bits in the sdi register accordingly (see also the serial data input section). in mode ii, the ads7863 input multiplexers can also operate in a pseudo-differential configuration. in this the input multiplexer cannot be used for case, output data are available on terminal sdoa pseudo-differential signals in mode iii or mode iv. only, while sdob is held in tri-state. figure 23. pseudo-differential mode ii (m0 = 0; m1 = 1) 21 submit documentation feedback product preview www.ti.com c[1:0] = '00' chx0+/chx0 ? - p[1:0] = '00' features off ? c[1:0] = '01' chx1 /chx0 ? - - p[1:0] = '11' features off ? c[1:0] = '10' chx1+/chx0 ? - p[1:0] = '00' features off ? 12-bit data chb1 /chb0 - - 12-bit data cha1+/cha0 - 12-bit data cha0+/cha0 - 12-bit data chb0+/cha0 - 12-bit data cha1 /cha0 - - previous 12-bit data chax 0 s m 0.5 s m 1.0 s m 1.5 s m 2.0 s m 2.5 s m 3.0 s m 1 16 1 16 1 16 1 16 1 16 1 1 clock convst sdi m0 m1 rd cs sdoa sdob busy high-z conversion of both chx1+/chx0 - no conversion, read data only conversion of both chx1+/chx0 - no conversion, read data only conversion of both chx0+/chx0 - previous conversion of both chxx every 2nd convst is ignored every 2nd convst is ignored every 2nd convst is ignored data chbx previous 12-bit
programming the reference dac ads7863 sbas383 ? june 2007 read access. triggering the rd line again causes the (not ads7861-compatible) sdoa output to send '0000' followed by the 10-bit dac value and another '00'. during the second rd the internal reference dac can be set by issuing an access, data present on sdi are ignored, while in rd pulse while providing an sdi word with p[1:0] = mode i and mode iii valid conversion data for '01' and a[2:0] = '001'. thereafter, a second rd channel b are present on sdob. the default value pulse must be generated with an sdi word starting of the dac register after power-up is 0x3ff, with '00' followed by the actual 10-bit dac value (see corresponding to a reference voltage of 2.5v on the figure 24 ). during the second access, the first two ref out pin. '00' bits are not interpreted as channel selection bits. to verify the dac setting, an rd pulse must be generated while providing an sdi word containing p[1:0] = '01' and a[2:0] = '011' to initialize the dac figure 24. dac write and read access timing diagram 22 submit documentation feedback www.ti.com product preview c[1:0] = '00' ? chx0 is next p[1:0] = '01' ? features on a[2:0] = '001' ? write dac c[1:0] = '00' ? chx0 is next p[1:0] = '11' ? no features data interpreted as dac value only sdi data ignored c[1:0] = '00' ? chx0 is next p[1:0] = '11' ? no features 12-bit data cha1 12-bit data cha0 12-bit data cha0 12-bit data cha0 10-bit dac value previous 12-bit data chax 12-bit data chb1 12-bit data chb0 12-bi data chb0 12-bit data chb0 12-bit data chb1 previous 12-bit data chbx conversion of both chx1 conversion of both chx1 conversion of both chx0 conversion of both chx0 conversion of both chx0 previous conversion of both chxx 0 s m 0.5 s m 1.0 s m 1.5 s m 2.0 s m 2.5 s m 3.0 s m 1 16 1 16 1 16 1 16 1 16 1 1 clock convst sdi m0 m1 rd cs sdoa sdob busy c[1:0] = '11' ? chx1 is next p[1:0] = '01' ? features on a[2:0] = '011' ? read dac 10-bit dac value
power-down modes and reset ads7863 sbas383 ? june 2007 in nap power-down mode, the ads7863 turns off (not ads7861-compatible) the biasing of the comparator and the mid-voltage buffer. in this mode, power dissipation reduces to the ads7863 has a comprehensive built-in approximately 0.3ma within 200ns. the device goes power-down feature. there are three power-down into nap power-down mode regardless of the modes: deep power-down, nap power-down, and conversion state. auto-nap power-down. all three power-down modes are activated with the 12th falling clock edge of the auto-nap power-down mode is almost identical the sdi access, during which the related bit asserts to the nap mode. the only difference is the time (dp = '1', n = '1', or an = '1'). all modes are required to power down and the method of waking deactivated by de-asserting the respective bit in the up the device. the sdi register bit an is only used sdi register. contents of the sdi register are not to enable/disable this feature. if the auto-nap mode affected by any of the power-down modes. any is enabled, the ads7863 turns off the biasing ongoing conversion aborts when deep or nap automatically after finishing a conversion; thus, the power-down is initiated. table 8 lists the differences end of conversion actually activates the auto-nap among the three power-down modes. power-down. device power dissipation reduces to about 0.3ma within 200ns in this mode, as well. in deep power-down mode, all functional blocks triggering a new conversion by applying a convst except the digital interface are disabled. the analog pulse puts the device back into normal operation. block has its bias currents and the internal oscillator turned off. in this mode, the power dissipation to issue a device reset, an rd pulse must be reduces to 1 a within 2 s. the wake-up time from generated along with an sdi word containing a[2:0] deep power-down mode is 1 s. = '101'. with the 12th falling edge after generating the rd pulse, the entire device?including the serial interface?is forced into reset. after approximately 20ns, the serial interface becomes active again. table 8. power-down modes power- power enabled activated activation resumed reactivation disabled down type dissipation by by time by time by deep 1 a dp = ?1? 12th clock 2 s dp = ?0? 1 s dp = ?0? nap 300 a n = ?1? 12th clock 200ns n = ?0? 3 clocks n = ?0? each end of auto-nap 300 a an = ?1? 200ns convst pulse 3 clocks an = ?0? conversion 23 submit documentation feedback product preview www.ti.com
layout supply grounding digital interface ads7863 sbas383 ? june 2007 underneath (or next) to the adc. otherwise, even short undershoots on the digital interface with a for optimum performance, care should be taken with value lower than ?300mv will lead to conduction of the physical layout of the ads7863 circuitry. this esd diodes, causing current flow through the condition is particularly true if the clock input is substrate and degrading the analog performance. approaching the maximum throughput rate. the basic sar architecture is quite sensitive to glitches during the pcb layout, care should also be taken to or sudden changes on the power supply, reference, avoid any return currents crossing any sensitive ground connections, and digital inputs that occur just analog areas or signals. no signal must exceed the prior to latching the output of the analog comparator. limit of ?300mv with respect to the according ground therefore, driving any single conversion for an n-bit plane. sar converter, there are n windows in which large external transient voltages can affect the conversion result. such glitches might originate from switching the ads7863 has two separate supplies, the bv dd power supplies, nearby digital logic, or high-power pin for the digital interface and the av dd pin for all devices. the degree of error in the digital output remaining (analog) circuits. depends on the reference voltage, layout, and the exact timing of the external event. these errors can bv dd can range from 1.65v to 5.5v, allowing the change if the external event also changes in time ads7863 to interface with all state-of-the-art with respect to the clock input. processors and controllers. to limit the injection of noise energy from external digital circuitry, bv dd with this possibility in mind, power to the ads7863 should be filtered properly. bypass capacitors of should be clean and well-bypassed. a 0.1 f ceramic 0.1 f and 10 f should be placed between the bv dd bypass capacitor should be placed as close to the pin and the ground plane. device as possible. in addition, a 1 f to 10 f capacitor is recommended. if needed, an even larger av dd is used to supply the internal analog circuitry. capacitor and a 5 w or 10 w series resistor may be for optimum performance, a linear regulator (for used to low-pass filter a noisy supply. example, the ua7805 family) is recommended to generate the analog supply voltage in the range of if the reference voltage is external and originates 2.7v to 5.5v for the ads7863 and the necessary from an operational amplifier, be sure that it can analog front-end circuitry. drive the bypass capacitor or capacitors without oscillation. bypass capacitors should be connected to the ground plane such that the current is allowed to flow through the pad of the capacitor (that is, the vias should be placed on the opposite side of the the xgnd pins should be connected to a clean connection between the capacitor and the ground reference. these connections should be kept power-supply pin of the adc). as short as possible to minimize the inductance of its path. it is recommended to use vias connecting the pads directly to the ground plane. in designs without ground planes, the ground trace should be kept as to further optimize device performance, a resistor of wide as possible. avoid connections that are too 10 w to 100 w can be used on each digital pin of the near the grounding point of a microcontroller or ads7863. in this way, the slew rate of the input and digital signal processor. output signals is reduced, limiting the noise injection from the digital interface. depending on the circuit density on the board, placement of the analog and digital components, and the related current loops, a single solid ground plane for the entire printed circuit board (pcb) or a dedicated analog ground area may be used. in an instance of a separated analog ground area, ensure a low-impedance connection between the analog and digital ground of the adc by placing a bridge 24 submit documentation feedback www.ti.com product preview
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) ads7863idbq preview ssop/ qsop dbq 24 56 tbd call ti call ti ads7863idbqr preview ssop/ qsop dbq 24 2500 tbd call ti call ti ADS7863IRGER preview qfn rge 24 3000 tbd call ti call ti ads7863irget preview qfn rge 24 250 tbd call ti call ti (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 28-jun-2007 addendum-page 1

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