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description the 4524 group is a 4-bit single-chip microcomputer designed with cmos technology. its cpu is that of the 4500 series using a simple, high-speed instruction set. the computer is equipped with main clock selection function, serial i/o, four 8-bit timers (each timer has one or two reload registers), 10-bit a/d converter, inter- rupts, and lcd control circuit. the various microcomputers in the 4524 group include variations of the built-in memory size as shown in the table below. features minimum instruction execution time .................................. 0.5 s (at 6 mhz oscillation frequency, in high-speed through-mode) supply voltage mask rom version ...................................................... 2.0 to 5.5 v one time prom version ............................................. 2.5 to 5.5 v (it depends on oscillation frequency and operation mode) timers timer 1 ...................................... 8-bit timer with a reload register timer 2 ...................................... 8-bit timer with a reload register timer 3 ...................................... 8-bit timer with a reload register timer 4 ................................. 8-bit timer with two reload registers timer 5 .............................. 16-bit timer (fixed dividing frequency) part number m34524m8-xxxfp m34524mc-xxxfp m34524edfp ( note ) rom type mask rom mask rom one time prom package 64p6n-a 64p6n-a 64p6n-a ram size ( ? 4 bits) 512 words 512 words 512 words rom (prom) size ( ? 10 bits) 8192 words 12288 words 16384 words interrupt ........................................................................ 9 sources key-on wakeup function pins ................................................... 10 lcd control circuit segment output ........................................................................ 20 common output .......................................................................... 4 serial i/o ......................................................................... 8-bit ? 1 a/d converter .............. 10-bit successive approximation method voltage drop detection circuit (reset) ......................... t yp. 3.5 v watchdog timer clock generating circuit main clock (ceramic resonator/rc oscillation/internal on-chip oscillator) sub-clock (quartz-crystal oscillation) led drive directly enabled (port d) application household appliance, consumer electronics, office automation equipment note: shipped in blank. 4524 group single-chip 4-bit cmos microcomputer rej03b0091-0200z rev.2.00 2004.07.27 rev.2.00 jul 27, 2004 page 1 of 159 rej03b0091-0200z
rev.2.00 jul 27, 2004 page 2 of 159 rej03b0091-0200z 4524 group pin configuration pin configuration (top view) (4524 group) outline 64p6n-a 6 4 4 9 50 5 1 5 2 53 5 4 55 56 5 7 58 5 9 6 0 61 6 2 63 78910111 2131 4151 6 3456 12 17 3 2 31 30 2 9 2 8 27 2 6 2 5 24 23 2 2 21 20 1 9 1 8 d 3 p 3 1 / a i n 5 p 3 0 / a i n 4 p 0 0 p 0 1 p 0 2 p 0 3 p 1 1 p 1 3 p 1 0 p 1 2 d 1 d 2 r e s e t p 3 3 / a i n 7 p 3 2 / a i n 6 x c o u t x cin c n v s s x o u t x in v ss v d d d 5 / s o u t d 4 / s i n 4 84 74 24 14 0393 83 73 6353 43 3 46 45 44 43 seg 14 s e g 1 5 s e g 1 3 seg 12 d 0 v d c e p 2 1 / a i n 1 p 2 2 / a i n 2 s e g 6 s e g 5 seg 4 s e g 3 v lc 1 /seg 2 v l c 2 / s e g 1 v l c 3 / s e g 0 c o m 0 c o m 1 c o m 2 c o m 3 s e g 7 seg 8 s e g 9 s e g 1 1 p 2 3 / a i n 3 seg 10 s e g 1 6 d 7 /cntr0 c / c n t r 1 d 8 /int0 d 9 / i n t 1 d 6 /s ck m34524mx-xxxfp m34524edfp s e g 1 9 p 2 0 / a i n 0 s e g 1 7 s e g 1 8 p 4 1 p 4 0 p 4 3 p 4 2
rev.2.00 jul 27, 2004 page 3 of 159 rej03b0091-0200z 4524 group block diagram (4524 group) 4 4 4 2 0 4 4 4 8 1 2 r a m r o m m e m o r y i / o p o r t i n t e r n a l p e r i p h e r a l f u n c t i o n s t i m e r t i m e r 1 ( 8 b i t s ) s y s t e m c l o c k g e n e r a t i o n c i r c u i t t i m e r 2 ( 8 b i t s ) 5 1 2 w o r d s ? 4 b i t s l c d d i s p l a y r a m i n c l u d i n g 2 0 w o r d s ? 4 b i t s 8 1 9 2 , 1 2 2 8 8 , 1 6 3 8 4 w o r d s ? 1 0 b i t s 4 5 0 0 s e r i e s c p u c o r e r e g i s t e r b ( 4 b i t s ) r e g i s t e r a ( 4 b i t s ) r e g i s t e r d ( 3 b i t s ) r e g i s t e r e ( 8 b i t s ) s t a c k r e g i s t e r s k ( 8 l e v e l s ) i n t e r r u p t s t a c k r e g i s t e r s d p ( 1 l e v e l ) a l u ( 4 b i t s ) w a t c h d o g t i m e r ( 1 6 b i t s ) p o r t p 0 p o r t p 1 p o r t p 2 p o w e r - o n r e s e t c i r c u i t v o l t a g e d r o p d e t e c t i o n c i r c u i t t i m e r 3 ( 8 b i t s ) t i m e r 4 ( 8 b i t s ) l c d d r i v e c o n t r o l c i r c u i t ( m a x . 2 0 s e g m e n t s ? 4 c o m m o n ) x i n - x o u t ( m a i n c l o c k ) x c i n - x c o u t ( s u b - c l o c k ) s e g m e n t o u t p u t c o m m o n o u t p u t p o r t p 3 p o r t d t i m e r 5 ( 1 6 b i t s ) p o r t c p o r t p 4 s e r i a l i / o ( 8 b i t s ? 1 ) a / d c o n v e r t e r ( 1 0 b i t s ? 8 c h )
rev.2.00 jul 27, 2004 page 4 of 159 rej03b0091-0200z 4524 group performance overview function 159 0.5 s (at 6 mhz oscillation frequency, in high-speed through mode) 8192 words ? 10 bits 12288 words ? 10 bits 16384 words ? 10 bits 512 words ? 4 bits (including lcd display ram 20 words ? 4 bits) eight independent i/o ports. input is examined by skip decision. the output structure can be switched by software. ports d 4 , d 5 , d 6 and d 7 are also used as s in , s out , s ck and cntr0 pin. two independent output ports. ports d 8 and d 9 are also used as int0 and int1, respectively. 4-bit i/o port; a pull-up function, a key-on wakeup function and output structure can be switched by software. 4-bit i/o port; a pull-up function, a key-on wakeup function and output structure can be switched by software. 4-bit i/o port; ports p2 0 ?2 3 are also used as a in0 ? in3 , respectively. 4-bit i/o port; ports p3 0 ?3 3 are also used as a in4 ? in7 , respectively. 4-bit i/o port; the output structure can be switched by software. 1-bit output; port c is also used as cntr1 pin. 8-bit programmable timer with a reload register and has an event counter. 8-bit programmable timer with a reload register. 8-bit programmable timer with a reload register and has an event counter. 8-bit programmable timer with two reload registers. 16-bit timer, fixed dividing frequency 10-bit ? 1, 8-bit comparator is equipped. 8-bit ? 1 1/2, 1/3 bias 2, 3, 4 duty 4 20 2r ? 3, 2r ? 2, r ? 3, r ? 2 (they can be switched by software.) 9 (two for external, five for timer, a/d, serial i/o) 1 level 8 levels cmos silicon gate 64-pin plastic molded qfp (64p6n) ?0 ? to 85 ? 2 to 5.5 v (it depends on the operation source clock, operation mode and oscillation frequency.) 2.5 to 5.5 v (it depends on the operation source clock, operation mode and oscillation frequency.) 2.8 ma (ta=25?, v dd = 5 v, f(x in ) = 6 mhz, f(x cin ) = 32 khz, f(stck) = f(x in )) 20 a (ta=25?, v dd = 5 v, f(x cin ) = 32 khz) 0.1 a (ta=25?, v dd = 5 v) parameter number of basic instructions minimum instruction execution time memory sizes input/output ports timers a/d converter serial i/o lcd control circuit interrupt subroutine nesting device structure package operating temperature range supply voltage power dissipation rom ram d 0 ? 7 d 8 , d 9 p0 0 ?0 3 p1 0 ?1 3 p2 0 ?2 3 p3 0 ?3 3 p4 0 ?4 3 c timer 1 timer 2 timer 3 timer 4 timer 5 selective bias value selective duty value common output segment output internal resistor for power supply sources nesting mask rom version one time prom version active mode clock operating mode at ram back-up m34524m8 m34524mc m34524ed i/o output i/o i/o i/o i/o i/o output
rev.2.00 jul 27, 2004 page 5 of 159 rej03b0091-0200z 4524 group pin description name power supply ground cnv ss voltage drop detection circuit enable reset input/output main clock input sub-clock input sub-clock output pin v dd v ss cnv ss vdce reset x in x cin x cout input/output input i/o input input output function connected to a plus power supply. connected to a 0 v power supply. connect cnv ss to v ss and apply ??(0v) to cnv ss certainly. this pin is used to operate/stop the voltage drop detection circuit. when ??level is input to this pin, the circuit starts operating. when ??level is input to this pin, the circuit stops operating. an n-channel open-drain i/o pin for a system reset. when the watchdog timer, the built-in power-on reset or the voltage drop detection circuit causes the system to be reset, the reset pin outputs ??level. i/o pins of the main clock generating circuit. when using a ceramic resonator, con- nect it between pins x in and x out . a feedback resistor is built-in between them. when using the rc oscillation, connect a resistor and a capacitor to x in , and leave x out pin open. i/o pins of the sub-clock generating circuit. connect a 32 khz quartz-crystal oscillator between pins x cin and x cout . a feedback resistor is built-in between them. x out main clock output output d 0 ? 7 d 8 , d 9 p0 0 ?0 3 p1 0 ?1 3 p2 0 ?2 3 p3 0 ?3 3 p4 0 ?4 3 port c com 0 com 3 seg 0 ?eg 19 v lc3 ? lc1 cntr0, cntr1 int0, int1 a in0 ? in7 s ck s out s in i/o port d input is examined by skip decision. output port d i/o port p0 i/o port p1 i/o port p2 i/o port p3 i/o port p4 output port c common output segment output lcd power supply timer input/output interrupt input analog input serial i/o data i/o serial i/o data output serial i/o clock input i/o output i/o i/o i/o i/o i/o output output output i/o input input i/o output input each pin of port d has an independent 1-bit wide i/o function. the output structure can be switched to n-channel open-drain or cmos by software. for input use, set the latch of the specified bit to ??and select the n-channel open-drain. ports d 4 ? 7 is also used as s in , s out , s ck and cntr0 pin. each pin of port d has an independent 1-bit wide output function. the output struc- ture is n-channel open-drain. ports d 8 and d 9 are also used as int0 pin and int1 pin, respectively. p ort p0 serves as a 4-bit i/o port. the output structure can be switched to n-channel open-drain or cmos by software. for input use, set the latch of the specified bit to ??and select the n-channel open-drain. port p0 has a key-on wakeup function and a pull-up function. both functions can be switched by software. p ort p1 serves as a 4-bit i/o port. the output structure can be switched to n-channel open-drain or cmos by software. for input use, set the latch of the specified bit to ??and select the n-channel open-drain. port p1 has a key-on wakeup function and a pull-up function. both functions can be switched by software. p ort p2 serves as a 4-bit i/o port. the output structure is n-channel open-drain. for input use, set the latch of the specified bit to ?? ports p2 0 ?2 3 are also used as a in0 ? in3 , respectively. p ort p3 serves as a 4-bit i/o port. the output structure is n-channel open-drain. for input use, set the latch of the specified bit to ?? ports p3 0 ?3 3 are also used as a in4 ? in7 , respectively. p ort p4 serves as a 4-bit i/o port. the output structure can be switched to n-channel open-drain or cmos by software. for input use, set the latch of the specified bit to ??and select the n-channel open-drain. 1 -bit output port. the output structure is cmos. port c is also used as cntr1 pin. lcd common output pins. pins com 0 and com 1 are used at 1/2 duty, pins com 0 com 2 are used at 1/3 duty and pins com 0 ?om 3 are used at 1/4 duty. lcd segment output pins. seg 0 ?eg 2 pins are used as v lc3 ? lc1 pins, respectively. lcd power supply pins. when the internal resistor is used, v dd pin is connected to v lc3 pin (if luminance ad- justment is required, v dd pin is connected to v lc3 pin through a resistor). when the external power supply is used, apply the voltage 0 v lc1 v lc2 v lc3 v dd . v lc3 ? lc1 pins are used as seg 0 ?eg 2 pins, respectively. cntr0 pin has the function to input the clock for the timer 1 event counter, and to output the timer 1 or timer 2 underflow signal divided by 2. cntr1 pin has the function to input the clock for the timer 3 event counter, and to output the pwm signal generated by timer 4.cntr0 pin and cntr1 pin are also used as ports d 7 and c, respectively. int0 pin and int1 pin accept external interrupts. they have the key-on wakeup func- tion which can be switched by software. int0 pin and int1 pin are also used as ports d 8 and d 9 , respectively. a/d converter analog input pins. a in0 ? in7 are also used as ports p2 0 ?2 3 and p3 0 p3 3 , respectively. serial i/o data transfer synchronous clock i/o pin. s ck pin is also used as port d 6 . serial i/o data output pin. s out pin is also used as port d 5 . serial i/o data input pin. s in pin is also used as port d 4 .
rev.2.00 jul 27, 2004 page 6 of 159 rej03b0091-0200z 4524 group definition of clock and cycle operation source clock the operation source clock is the source clock to operate this product. in this product, the following clocks are used. ?clock (f(x in )) by the external ceramic resonator ?clock (f(x in )) by the external rc oscillation ?clock (f(x in )) by the external input ?clock (f(ring)) of the on-chip oscillator which is the internal oscillator ?clock (f(x cin )) by the external quartz-crystal oscillation register mr system clock f(stck) = f(x in ) or f(ring) f(stck) = f(x cin ) f(stck) = f(x in )/2 or f(ring)/2 f(stck) = f(x cin )/2 f(stck) = f(x in )/4 or f(ring)/4 f(stck) = f(x cin )/4 f(stck) = f(x in )/8 or f(ring)/8 f(stck) = f(x cin )/8 table selection of system clock ? : 0 or 1 note: the f(ring)/8 is selected after system is released from reset. mr 2 0 1 0 1 mr 3 0 0 1 1 operation mode high-speed through mode low-speed through mode high-speed frequency divided by 2 mode low-speed frequency divided by 2 mode high-speed frequency divided by 4 mode low-speed frequency divided by 4 mode high-speed frequency divided by 8 mode low-speed frequency divided by 8 mode system clock (stck) the system clock is the basic clock for controlling this product. the system clock is selected by the clock control register mr shown as the table below. instruction clock (instck) the instruction clock is the basic clock for controlling cpu. the instruction clock (instck) is a signal derived by dividing the system clock (stck) by 3. the one instruction clock cycle gen- erates the one machine cycle. machine cycle the machine cycle is the standard cycle required to execute the instruction. mr 0 0 1 0 1 0 1 0 1 mr 1 0 ? 0 ? 0 ? 0 ? notes 1: pins except above have just single function. 2: the output of d 8 and d 9 can be used even when int0 and int1 are selected. 3: the input of ports d 4 ? 6 can be used even when s in , s out and s ck are selected. 4: the input/output of d 7 can be used even when cntr0 (input) is selected. 5: the input of d 7 can be used even when cntr0 (output) is selected. 6: the port c ??output function can be used even when cntr1 (output) is selected. pin d 4 d 5 d 6 d 7 d 8 d 9 v lc3 v lc2 v lc1 multifunction s in s out s ck cntr0 int0 int1 seg 0 seg 1 seg 2 multifunction pin s in s out s ck cntr0 int0 int1 seg 0 seg 1 seg 2 multifunction d 4 d 5 d 6 d 7 d 8 d 9 v lc3 v lc2 v lc1 pin c p2 0 p2 1 p2 2 p2 3 p3 0 p3 1 p3 2 p3 3 multifunction cntr1 a in0 a in1 a in2 a in3 a in4 a in5 a in6 a in7 pin cntr1 a in0 a in1 a in2 a in3 a in4 a in5 a in6 a in7 multifunction c p2 0 p2 1 p2 2 p2 3 p3 0 p3 1 p3 2 p3 3
rev.2.00 jul 27, 2004 page 7 of 159 rej03b0091-0200z 4524 group port function port port d port p0 port p1 port p2 port p3 port p4 port c i/o unit 1 4 4 4 4 4 1 control instructions sd, rd szd cld op0a iap0 op1a iap1 op2a iap2 op3a iap3 op4a iap4 rcp scp control registers fr1, fr2 j1 w6 i1, i2 k2 fr0 pu0 k0 fr0 pu1 k1 q2 q3 fr3 w4 output structure n-channel open-drain/ cmos n-channel open-drain n-channel open-drain/ cmos n-channel open-drain/ cmos n-channel open-drain n-channel open-drain n-channel open-drain/ cmos cmos input output i/o (8) output (2) i/o (4) i/o (4) i/o (4) i/o (4) i/o (4) output (1) remark pin d 0 ? 3 , d 4 /s in , d 5 /s out , d 6 /s ck , d 7 /cntr0 d 8 /int0, d 9 /int1 p0 0 ?0 3 p1 0 ?1 3 p2 0 /a in0 ?2 3 /a in3 p3 0 /a in4 ?3 3 /a in7 p4 0 ?4 3 c/cntr1 output structure selection function (programmable) key-on wakeup function (programmable) built-in programmable pull-up functions and key-on wakeup functions (programmable) built-in programmable pull-up functions and key-on wakeup functions (programmable) output structure selection function (programmable)
rev.2.00 jul 27, 2004 page 8 of 159 rej03b0091-0200z 4524 group connections of unused pins connection connect to v ss . open. connect to v ss . open. open. connect to v ss . open. connect to v ss . open. connect to v ss . open. connect to v ss . open. connect to v ss . open. connect to v ss . open. connect to v ss . open. open. connect to vss. open. connect to vss. open. connect to vss. open. connect to vss. open. connect to vss. open. open. open. open. open. pin x in x out x cin x cout d 0 ? 3 d 4 /s in d 5 /s out d 6 /s ck d 7 /cntr0 d 8 /int0 d 9 /int1 c/cntr1 p0 0 ?0 3 p1 0 ?1 3 p2 0 /a in0 p2 3 /a in3 p3 0 /a in4 p3 3 /a in7 p4 0 ?4 3 com 0 ?om 3 v lc3 /seg 0 v lc2 /seg 1 v lc1 /seg 2 seg 3 ?eg 19 usage condition internal oscillator is selected (cmck and crck instructions are not executed.) (note 1) sub-clock input is selected for system clock (mr 0 =1). (note 2) internal oscillator is selected (cmck and crck instructions are not executed.) (note 1) rc oscillator is selected (crck instruction is executed) external clock input is selected for main clock (cmck instruction is executed). (note 3) sub-clock input is selected for system clock (mr 0 =1). (note 2) sub-clock is not used. sub-clock is not used. n-channel open-drain is selected for the output structure. (note 4) s in pin is not selected. n-channel open-drain is selected for the output structure. n-channel open-drain is selected for the output structure. s ck pin is not selected. n-channel open-drain is selected for the output structure. cntr0 input is not selected for timer 1 count source. n-channel open-drain is selected for the output structure. ??is set to output latch. ??is set to output latch. cntr1 input is not selected for timer 3 count source. the key-on wakeup function is not selected. (note 4) n-channel open-drain is selected for the output structure. (note 5) the pull-up function is not selected. (note 4) the key-on wakeup function is not selected. (note 4) the key-on wakeup function is not selected. (note 4) n-channel open-drain is selected for the output structure. (note 5) the pull-up function is not selected. (note 4) the key-on wakeup function is not selected. (note 4) n-channel open-drain is selected for the output structure. (note 5) seg 0 pin is selected. seg 1 pin is selected. seg 2 pin is selected. notes 1: when the cmck and crck instructions are not executed, the internal oscillation (on-chip oscillator) is selected for ma in clock. 2: when sub-clock (x cin ) input is selected (mr 0 = 1) for the system clock by setting ??to bit 1 (mr 1 ) of clock control register mr, main clock is stopped. 3: select the ceramic resonance by executing the cmck instruction to use the external clock input for the main clock. 4: be sure to select the output structure of ports d 0 ? 3 and p4 0 ?4 3 and the pull-up function and key-on wakeup function of p0 0 ?0 3 and p1 0 ?1 3 with every one port. set the corresponding bits of registers for each port. 5: be sure to select the output structure of ports p0 0 ?0 3 and p1 0 ?1 3 with every two ports. if only one of the two pins is used, leave another one open. (note when connecting to v ss and v dd ) connect the unused pins to v ss and v dd using the thickest wire at the shortest distance against noise.
rev.2.00 jul 27, 2004 page 9 of 159 rej03b0091-0200z 4524 group port block diagrams port block diagram (1) d 0 s rq fr1 0 d 1 s rq fr1 1 d 2 s rq fr1 2 d 3 s rq fr1 3 c/cntr1 d t q r w3 2 w6 1 s c p i n s t r u c t i o n r c p i n s t r u c t i o n s r w3 1 w3 0 q p w m o d r e g i s t e r yd e c o d e r s d i n s t r u c t i o n rd instruction s k i p d e c i s i o n ( s z d i n s t r u c t i o n ) cld instruction ( n o t e 1 ) (note 2) c l o c k ( i n p u t ) f o r t i m e r 3 e v e n t c o u n t timer 3 underflow signal t h i s s y m b o l r e p r e s e n t s a p a r a s i t i c d i o d e o n t h e p o r t . 2 : a p p l i e d p o t e n t i a l t o t h e s e p o r t s m u s t b e v d d o r l e s s . 3 : w h e n c n t r 1 i n p u t i s s e l e c t e d , o u t p u t t r a n s i s t o r i s t u r n e d o f f . n o t e s 1 : r e g i s t e r yd e c o d e r s d i n s t r u c t i o n rd instruction skip decision (szd instruction) c l d i n s t r u c t i o n ( n o t e 1 ) (note 2) r e g i s t e r y decoder s d i n s t r u c t i o n r d i n s t r u c t i o n s k i p d e c i s i o n ( s z d i n s t r u c t i o n ) cld instruction (note 1) ( n o t e 2 ) register y decoder s d i n s t r u c t i o n r d i n s t r u c t i o n skip decision (szd instruction) c l d i n s t r u c t i o n ( n o t e 1 ) (note 2) ( n o t e 1 ) (note 2, note 3)
rev.2.00 jul 27, 2004 page 10 of 159 rej03b0091-0200z 4524 group port block diagram (2) s rq fr2 1 j1 0 0 1 s e r i a l d a t a o u t p u t d 5 /s out d 4 / s i n f r 2 0 s e r i a l d a t a i n p u t j1 1 s r q this symbol represents a parasitic diode on the port. 2: applied potential to these ports must be v dd or less. notes 1: r e g i s t e r y decoder s d i n s t r u c t i o n rd instruction s k i p d e c i s i o n ( s z d i n s t r u c t i o n ) c l d i n s t r u c t i o n (note 1) ( n o t e 2 ) r e g i s t e r y d e c o d e r s d i n s t r u c t i o n r d i n s t r u c t i o n s k i p d e c i s i o n ( s z d i n s t r u c t i o n ) c l d i n s t r u c t i o n ( n o t e 1 ) ( n o t e 2 ) d 6 /s ck s r fr2 2 j1 3 j1 2 j 1 1 j 1 0 q s y n c h r o n o u s c l o c k ( o u t p u t ) f o r s e r i a l d a t a t r a n s f e r r e g i s t e r yd e c o d e r s d i n s t r u c t i o n r d i n s t r u c t i o n skip decision (szd instruction) cld instruction ( n o t e 1 ) ( n o t e 2 ) s y n c h r o n o u s c l o c k ( i n p u t ) f o r s e r i a l d a t a t r a n s f e r
rev.2.00 jul 27, 2004 page 11 of 159 rej03b0091-0200z 4524 group port block diagram (3) w1 1 w1 0 s rq f r 2 3 w6 0 0 1 d 7 /c n t r 0 s rq d 8 /int0 s rq d 9 / i n t 1 r e g i s t e r yd e c o d e r s d i n s t r u c t i o n r d i n s t r u c t i o n s k i p d e c i s i o n ( s z d i n s t r u c t i o n ) c l d i n s t r u c t i o n ( n o t e 1 ) ( n o t e 2 ) c l o c k ( i n p u t ) f o r t i m e r 1 e v e n t c o u n t u n d e r f l o w s i g n a l d i v i d e d b y 2 o f t i m e r 1 o r t i m e r 2 ( n o t e 1 ) ( n o t e 2 ) r e g i s t e r y decoder s d i n s t r u c t i o n rd instruction cld instruction (note 3) external 0 interrupt circuit e x t e r n a l 0 i n t e r r u p t k e y - o n w a k e u p timer 1 count start synchronous circuit input ( n o t e 1 ) ( n o t e 2 ) r e g i s t e r yd e c o d e r sd instruction r d i n s t r u c t i o n cld instruction (note 3) external 1 interrupt circuit external 1 interrupt key-on wakeup t i m e r 3 c o u n t s t a r t s y n c h r o n o u s c i r c u i t i n p u t t h i s s y m b o l r e p r e s e n t s a p a r a s i t i c d i o d e o n t h e p o r t . 2 : a p p l i e d p o t e n t i a l t o t h e s e p o r t s m u s t b e v d d o r l e s s . 3 : a s f o r d e t a i l s , r e f e r t o t h e d e s c r i p t i o n o f e x t e r n a l i n t e r r u p t c i r c u i t . notes 1:
rev.2.00 jul 27, 2004 page 12 of 159 rej03b0091-0200z 4524 group port block diagram (4) p0 0 k0 0 o p 0 a i n s t r u c t i o n r e g i s t e r a a 0 a 0 d k e y - o n w a k e u p (note 2) ( n o t e 1 ) fr0 0 iap0 instruction pu0 0 p u l l - u p t r a n s i s t o r t q l l e v e l d e t e c t i o n c i r c u i t p 0 1 k0 1 a 1 a 1 d f r 0 0 pu0 1 t q p 0 2 k0 2 a 2 a 2 d f r 0 1 pu0 2 t q p0 3 k0 3 a 3 a 3 d fr0 1 pu0 3 t q o p 0 a i n s t r u c t i o n r e g i s t e r a k e y - o n w a k e u p ( n o t e 2 ) ( n o t e 1 ) iap0 instruction p u l l - u p t r a n s i s t o r l level detection circuit op0a instruction r e g i s t e r a k e y - o n w a k e u p ( n o t e 2 ) ( n o t e 1 ) iap0 instruction p u l l - u p t r a n s i s t o r l level detection circuit o p 0 a i n s t r u c t i o n r e g i s t e r a k e y - o n w a k e u p ( n o t e 2 ) (note 1) iap0 instruction p u l l - u p t r a n s i s t o r l l e v e l d e t e c t i o n c i r c u i t t h i s s y m b o l r e p r e s e n t s a p a r a s i t i c d i o d e o n t h e p o r t . 2 : a p p l i e d p o t e n t i a l t o t h e s e p o r t s m u s t b e v d d o r l e s s . n o t e s 1 :
rev.2.00 jul 27, 2004 page 13 of 159 rej03b0091-0200z 4524 group port block diagram (5) p 1 0 k 1 0 o p 1 a i n s t u c t i o n r e g i s t e r a a 0 a 0 d k e y - o n w a k e u p ( n o t e 2 ) ( n o t e 1 ) f r 0 2 i a p 1 i n s t r u c t i o n p u 1 0 p u l l - u p t r a n s i s t o r t q l l e v e l d e t e c t i o n c i r c u i t p 1 1 k 1 1 a 1 a 1 d f r 0 2 p u 1 1 t q p 1 2 k 1 2 a 2 a 2 d f r 0 3 p u 1 2 t q p 1 3 k 1 3 a 3 a 3 d f r 0 3 p u 1 3 t q o p 1 a i n s t u c t i o n r e g i s t e r a k e y - o n w a k e u p i a p 1 i n s t r u c t i o n p u l l - u p t r a n s i s t o r l l e v e l d e t e c t i o n c i r c u i t ( n o t e 2 ) ( n o t e 1 ) o p 1 a i n s t u c t i o n r e g i s t e r a k e y - o n w a k e u p i a p 1 i n s t r u c t i o n p u l l - u p t r a n s i s t o r l l e v e l d e t e c t i o n c i r c u i t ( n o t e 2 ) ( n o t e 1 ) o p 1 a i n s t u c t i o n r e g i s t e r a k e y - o n w a k e u p i a p 1 i n s t r u c t i o n p u l l - u p t r a n s i s t o r l l e v e l d e t e c t i o n c i r c u i t ( n o t e 2 ) ( n o t e 1 ) t h i s s y m b o l r e p r e s e n t s a p a r a s i t i c d i o d e o n t h e p o r t . 2 : a p p l i e d p o t e n t i a l t o t h e s e p o r t s m u s t b e v d d o r l e s s . n o t e s 1 :
rev.2.00 jul 27, 2004 page 14 of 159 rej03b0091-0200z 4524 group port block diagram (6) p2 0/ a in0 p2 3/ a in3 d e c o d e r o p 2 a i n s t r u c t i o n r e g i s t e r a a i a i d a n a l o g i n p u t t q 0 1 q2 i iap2 instruction q 2 i q 1 ( n o t e 3 ) (note 3) p3 0/ a in4 p3 3/ a in7 op3a instruction a i a i d t q 0 1 q3 i i a p 3 i n s t r u c t i o n q3 i q 1 p4 0 p4 3 o p 4 a i n s t r u c t i o n a i a i d fr3 i i a p 4 i n s t r u c t i o n t q (note 3) ( n o t e 1 ) (note 2) (note 3) ( n o t e 3 ) ( n o t e 1 ) (note 2) r e g i s t e r a (note 3) d e c o d e r a n a l o g i n p u t register a ( n o t e 3 ) (note 3) ( n o t e 1 ) (note 2) this symbol represents a parasitic diode on the port. 2: applied potential to these ports must be v dd or less. 3: i represents bits 0 to 3. n o t e s 1 :
rev.2.00 jul 27, 2004 page 15 of 159 rej03b0091-0200z 4524 group port block diagram (7) ( v l c 3 / v d d ) v l c 3 / s e g 0 l2 3 ( v l c2 ) v l c 2 / s e g 1 l 2 2 ( v l c 1 ) v lc1 /seg 2 l 2 1 l1 3 l 2 0 l1 2 l 1 1 v dd r e s e t s i g n a l e p o f + p o f 2 i n s t r u c t i o n ( c o n t i n u o u s e x e c u t i o n ) ( n o t e 1 ) l c d c o n t r o l s i g n a l c o n n e c t i n g t o w h e n s e g i s s e l e c t e d . lcd power supply l c d p o w e r s u p p l y ( n o t e s 2 a n d 3 ) l c d p o w e r s u p p l y (note 1) l c d c o n t r o l s i g n a l c o n n e c t i n g t o w h e n s e g i s s e l e c t e d . l c d p o w e r s u p p l y l c d p o w e r s u p p l y ( n o t e 2 ) lcd power supply lcd power supply lcd power supply lcd power supply lcd control signal (note 1) (note 2) connecting to when seg is selected. t h i s s y m b o l r e p r e s e n t s a p a r a s i t i c d i o d e o n t h e p o r t . 2 : a p p l i e d p o t e n t i a l w h e n v l c i s s e l e c t e d m u s t b e a s f o l l o w s ; v d d
rev.2.00 jul 27, 2004 page 16 of 159 rej03b0091-0200z 4524 group port block diagram (8) com 0 com 3 pch s e g 3 s e g 1 9 pch n c h nch pch n c h l c d c o n t r o l s i g n a l lcd power supply l c d c o n t r o l s i g n a l l c d p o w e r s u p p l y l c d c o n t r o l s i g n a l lcd power supply l c d c o n t r o l s i g n a l l c d p o w e r s u p p l y l c d c o n t r o l s i g n a l lcd power supply l c d c o n t r o l s i g n a l
rev.2.00 jul 27, 2004 page 17 of 159 rej03b0091-0200z 4524 group function block operations cpu (1) arithmetic logic unit (alu) the arithmetic logic unit alu performs 4-bit arithmetic such as 4- bit data addition, comparison, and operation, or operation, and bit manipulation. (2) register a and carry flag register a is a 4-bit register used for arithmetic, transfer, ex- change, and i/o operation. carry flag cy is a 1-bit flag that is set to 1 when there is a carry with the amc instruction (figure 1). it is unchanged with both a n instruction and am instruction. the value of a 0 is stored in carry flag cy with the rar instruction (fig- ure 2). carry flag cy can be set to 1 with the sc instruction and cleared to 0 with the rc instruction. (3) registers b and e register b is a 4-bit register used for temporary storage of 4-bit data, and for 8-bit data transfer together with register a. register e is an 8-bit register. it can be used for 8-bit data transfer with register b used as the high-order 4 bits and register a as the low-order 4 bits (figure 3). register e is undefined after system is released from reset and re- turned from the ram back-up. accordingly, set the initial value. (4) register d register d is a 3-bit register. it is used to store a 7-bit rom address together with register a and is used as a pointer within the specified page when the tabp p, bla p, or bmla p instruction is executed (figure 4). register d is undefined after system is released from reset and re- turned from the ram back-up. accordingly, set the initial value. fig. 1 amc instruction execution example fig. 2 rar instruction execution example fig. 3 registers a, b and register e fig. 4 tabp p instruction execution example ( c y ) ( m ( d p ) ) ( a ) addition a l u < r e s u l t > cy a 3 a 2 a 1 a 0 a 0 c ya 3 a 2 a 1 < r o t a t i o n > r a r i n s t r u c t i o n sc instruction rc instruction a 3 a 2 a 1 a 0 b 3 b 2 b 1 b 0 e 7 e 6 e 5 e 4 e 3 e 2 e 1 e 0 a 3 a 2 a 1 a 0 b 3 b 2 b 1 b 0 tab instruction t e a b i n s t r u c t i o n t a b e i n s t r u c t i o n tba instruction r e g i s t e r br e g i s t e r a register b register a register e s p e c i f y i n g a d d r e s s tabp p instruction p 6 p 5 p 4 p 3 p 2 p 1 p 0 p c h dr 2 d r 1 d r 0 a 3 a 2 a 1 a 0 p c l i m m e d i a t e f i e l d v a l u e p t h e c o n t e n t s o f r e g i s t e r d rom 840 middle-order 4 bits l o w - o r d e r 4 b i t s register a (4) register b (4) t h e c o n t e n t s o f r e g i s t e r a
rev.2.00 jul 27, 2004 page 18 of 159 rej03b0091-0200z 4524 group (5) stack registers (sk s ) and stack pointer (sp) stack registers (sks) are used to temporarily store the contents of program counter (pc) just before branching until returning to the original routine when; branching to an interrupt service routine (referred to as an inter- rupt service routine), performing a subroutine call, or executing the table reference instruction (tabp p). stack registers (sks) are eight identical registers, so that subrou- tines can be nested up to 8 levels. however, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. accordingly, be care- ful not to over the stack when performing these operations together. the contents of registers sks are destroyed when 8 lev- els are exceeded. the register sk nesting level is pointed automatically by 3-bit stack pointer (sp). the contents of the stack pointer (sp) can be transferred to register a with the tasp instruction. figure 5 shows the stack registers (sks) structure. figure 6 shows the example of operation at subroutine call. (6) interrupt stack register (sdp) interrupt stack register (sdp) is a 1-stage register. when an inter- rupt occurs, this register (sdp) is used to temporarily store the contents of data pointer, carry flag, skip flag, register a, and regis- ter b just before an interrupt until returning to the original routine. unlike the stack registers (sks), this register (sdp) is not used when executing the subroutine call instruction and the table refer- ence instruction. (7) skip flag skip flag controls skip decision for the conditional skip instructions and continuous described skip instructions. when an interrupt oc- curs, the contents of skip flag is stored automatically in the interrupt stack register (sdp) and the skip condition is retained. fig. 5 stack registers (sks) structure fig. 6 example of operation at subroutine call s k 0 s k 1 s k 2 s k 3 s k 4 s k 5 s k 6 s k 7 ( s p ) = 0 ( s p ) = 1 ( s p ) = 2 ( s p ) = 3 ( s p ) = 4 ( s p ) = 5 ( s p ) = 6 ( s p ) = 7 program counter (pc) e x e c u t i n g r t i n s t r u c t i o n executing bm instruction stack pointer (sp) points 7 at reset o r returning from ram back-up mode. it points 0 by executing the first bm instruction, and th e contents of program counter is stored in sk 0 . when the bm instruction is executed after eigh t stack registers are used ((sp) = 7), (sp) = 0 and the contents of sk 0 is destroyed. returning to the bm instruction execution address with the rt instruction, and the bm instruction becomes the nop instruction. (sp) note :
rev.2.00 jul 27, 2004 page 19 of 159 rej03b0091-0200z 4524 group (8) program counter (pc) program counter (pc) is used to specify a rom address (page and address). it determines a sequence in which instructions stored in rom are read. it is a binary counter that increments the number of instruction bytes each time an instruction is executed. however, the value changes to a specified address when branch instructions, subroutine call instructions, return instructions, or the table refer- ence instruction (tabp p) is executed. program counter consists of pc h (most significant bit to bit 7) which specifies to a rom page and pc l (bits 6 to 0) which speci- fies an address within a page. after it reaches the last address (address 127) of a page, it specifies address 0 of the next page (figure 7). make sure that the pc h does not specify after the last page of the built-in rom. (9) data pointer (dp) data pointer (dp) is used to specify a ram address and consists of registers z, x, and y. register z specifies a ram file group, reg- ister x specifies a file, and register y specifies a ram digit (figure 8). register y is also used to specify the port d bit position. when using port d, set the port d bit position to register y certainly and execute the sd, rd, or szd instruction (figure 9). note register z of data pointer is undefined after system is released from reset. also, registers z, x and y are undefined in the ram back-up. after system is returned from the ram back-up, set these registers. fig. 7 program counter (pc) structure fig. 8 data pointer (dp) structure fig. 9 sd instruction execution example p 5 p 4 p 3 p 2 p 1 p 0 a 6 a 5 a 4 a 3 a 2 a 1 a 0 p r o g r a m c o u n t e r p c h s p e c i f y i n g p a g e p c l s p e c i f y i n g a d d r e s s p 6 z 1 z 0 x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 d a t a p o i n t e r ( d p ) register z (2) r e g i s t e r x ( 4 ) register y (4) s p e c i f y i n g r a m d i g i t s p e c i f y i n g r a m f i l e specifying ram file group 0 01 1 set s p e c i f y i n g b i t p o s i t i o n port d output latch register y (4) d 2 d 3 d 1 d 0 0
rev.2.00 jul 27, 2004 page 20 of 159 rej03b0091-0200z 4524 group program memory (rom) the program memory is a mask rom. 1 word of rom is composed of 10 bits. rom is separated every 128 words by the unit of page (addresses 0 to 127). table 1 shows the rom size and pages. fig- ure 10 shows the rom map of m34524ed. table 1 rom size and pages part number m34524m8 m34524mc m34524ed rom (prom) size ( ? fig. 10 rom map of m34524ed fig. 11 page 1 (addresses 0080 16 to 00ff 16 ) structure 90 87654321 i n t e r r u p t a d d r e s s p a g e 0 0 0 0 1 6 0 0 8 0 1 6 0 1 7 f 1 6 s u b r o u t i n e s p e c i a l p a g e 0 0 7 f 1 6 0 0 f f 1 6 0 1 0 0 1 6 3 f f f 1 6 0 1 8 0 1 6 p a g e 1 p a g e 2 p a g e 0 p a g e 3 p a g e 1 2 7 90 87654321 external 0 interrupt address 0 0 8 0 1 6 0082 16 0 0 8 4 1 6 timer 1 interrupt address t i m e r 2 i n t e r r u p t a d d r e s s 0 0 8 6 1 6 0 0 8 8 1 6 0 0 8 a 1 6 008c 16 0 0 8 e 1 6 00ff 16 a/d interrupt address external 1 interrupt address t i m e r 3 i n t e r r u p t a d d r e s s timer 5 interrupt address t i m e r 4 , s e r i a l i / o i n t e r r u p t a d d r e s s
rev.2.00 jul 27, 2004 page 21 of 159 rej03b0091-0200z 4524 group data memory (ram) 1 word of ram is composed of 4 bits, but 1-bit manipulation (with the sb j, rb j, and szb j instructions) is enabled for the entire memory area. a ram address is specified by a data pointer. the data pointer consists of registers z, x, and y. set a value to the data pointer certainly when executing an instruction to access ram (also, set a value after system returns from ram back-up). ram includes the area for lcd. when writing 1 to a bit corresponding to displayed segment, the segment is turned on. table 2 shows the ram size. figure 12 shows the ram map. note register z of data pointer is undefined after system is released from reset. also, registers z, x and y are undefined in the ram back-up. after system is returned from the ram back-up, set these registers. fig. 12 ram map table 2 ram size part number m34524m8 m34524mc m34524ed ram size 512 words ? ? ? ?
rev.2.00 jul 27, 2004 page 22 of 159 rej03b0091-0200z 4524 group interrupt function the interrupt type is a vectored interrupt branching to an individual address (interrupt address) according to each interrupt source. an interrupt occurs when the following 3 conditions are satisfied. an interrupt activated condition is satisfied (request flag = 1 ) interrupt enable bit is enabled ( 1 ) interrupt enable flag is enabled (inte = 1 ) table 3 shows interrupt sources. (refer to each interrupt request flag for details of activated conditions.) (1) interrupt enable flag (inte) the interrupt enable flag (inte) controls whether the every inter- rupt enable/disable. interrupts are enabled when inte flag is set to 1 with the ei instruction and disabled when inte flag is cleared to 0 with the di instruction. when any interrupt occurs, the inte flag is automatically cleared to 0, so that other interrupts are disabled until the ei instruction is executed. (2) interrupt enable bit use an interrupt enable bit of interrupt control registers v1 and v2 to select the corresponding interrupt or skip instruction. table 4 shows the interrupt request flag, interrupt enable bit and skip instruction. table 5 shows the interrupt enable bit function. (3) interrupt request flag when the activated condition for each interrupt is satisfied, the cor- responding interrupt request flag is set to 1. each interrupt request flag is cleared to 0 when either; an interrupt occurs, or the next instruction is skipped with a skip instruction. each interrupt request flag is set to 1 when the activated condi- tion is satisfied even if the interrupt is disabled by the inte flag or its interrupt enable bit. once set, the interrupt request flag retains set until it is cleared to 0 by the interrupt occurrence or the skip instruction. accordingly, an interrupt occurs when the interrupt disable state is released while the interrupt request flag is set. if more than one interrupt request flag is set to 1 when the inter- rupt disable state is released, the interrupt priority level is as follows shown in table 3. table 3 interrupt sources activated condition level change of int0 pin level change of int1 pin timer 1 underflow timer 2 underflow timer 3 underflow timer 5 underflow completion of a/d conversion timer 4 underflow or completion of serial i/o transmit/ receive priority level 1 2 3 4 5 6 7 8 interrupt name external 0 interrupt external 1 interrupt timer 1 interrupt timer 2 interrupt timer 3 interrupt timer 5 interrupt a/d interrupt timer 4 interrupt or serial i/o interrupt (note) interrupt request flag exf0 exf1 t1f t2f t3f t5f adf t4f siof interrupt name external 0 interrupt external 1 interrupt timer 1 interrupt timer 2 interrupt timer 3 interrupt timer 5 interrupt a/d interrupt timer 4 interrupt serial i/o interrupt table 5 interrupt enable bit function occurrence of interrupt enabled disabled skip instruction invalid valid interrupt enable bit 1 0 interrupt address address 0 in page 1 address 2 in page 1 address 4 in page 1 address 6 in page 1 address 8 in page 1 address a in page 1 address c in page 1 address e in page 1 table 4 interrupt request flag, interrupt enable bit and skip in- struction skip instruction snz0 snz1 snzt1 snzt2 snzt3 snzt5 snzad snzt4 snzsi interrupt nable bit v1 0 v1 1 v1 2 v1 3 v2 0 v2 1 v2 2 v2 3 v2 3 note: timer 4 interrupt or serial i/o interrupt can be selected by the timer 4, serial i/o interrupt source selection bit (i3 0 ).
rev.2.00 jul 27, 2004 page 23 of 159 rej03b0091-0200z 4524 group (4) internal state during an interrupt the internal state of the microcomputer during an interrupt is as fol- lows (figure 14). program counter (pc) an interrupt address is set in program counter. the address to be executed when returning to the main routine is automatically stored in the stack register (sk). interrupt enable flag (inte) inte flag is cleared to 0 so that interrupts are disabled. interrupt request flag only the request flag for the current interrupt source is cleared to 0. data pointer, carry flag, skip flag, registers a and b the contents of these registers and flags are stored automatically in the interrupt stack register (sdp). (5) interrupt processing when an interrupt occurs, a program at an interrupt address is ex- ecuted after branching a data store sequence to stack register. write the branch instruction to an interrupt service routine at an in- terrupt address. use the rti instruction to return from an interrupt service routine. interrupt enabled by executing the ei instruction is performed after executing 1 instruction (just after the next instruction is executed). accordingly, when the ei instruction is executed just before the rti instruction, interrupts are enabled after returning the main routine. (refer to figure 13) fig. 13 program example of interrupt processing program counter (pc) ............................................................... each interrupt address stack register (sk) .................................................................................................... interrupt enable flag (inte) .................................................................. 0 (interrupt disabled) interrupt request flag (only the flag for the current interrupt source) ................................................................................... 0 data pointer, carry flag, registers a and b, skip flag ........ stored in the interrupt stack register (sdp) automatically the address of main routine to be executed when returning fig. 15 interrupt system diagram fig. 14 internal state when interrupt occurs e i r t i i n t e r r u p t s e r v i c e r o u t i n e interrupt occurs interrupt is enabled m a i n r o u t i n e : i n t e r r u p t e n a b l e d s t a t e : i n t e r r u p t d i s a b l e d s t a t e v 1 1 e x f 0 v 1 0 address 2 in page 1 a d d r e s s 4 i n p a g e 1 a d d r e s s 0 i n p a g e 1 timer 1 underflow t i m e r 2 u n d e r f l o w t 1 fv 1 2 r e q u e s t f l a g ( s t a t e r e t a i n e d ) e n a b l e b i t e n a b l e f l a g a c t i v a t e d c o n d i t i o n v1 3 a d d r e s s 6 i n p a g e 1 a / d c o n v e r s i o n c o m p l e t e d i n t e adf t2f v2 0 t 3 f v 2 1 t4f v2 3 t5f v 2 2 siof i 3 0 0 1 i n t 0 p i n i n t e r r u p t w a v e f o r m i n p u t t i m e r 3 u n d e r f l o w t i m e r 5 u n d e r f l o w timer 4 underflow s e r i a l i / o t r a n s m i t / r e c e i v e c o m p l e t e d i n t 1 p i n i n t e r r u p t w a v e f o r m i n p u t exf1 a d d r e s s 8 i n p a g e 1 address a in page 1 a d d r e s s c i n p a g e 1 a d d r e s s e i n p a g e 1
rev.2.00 jul 27, 2004 page 24 of 159 rej03b0091-0200z 4524 group (6) interrupt control registers interrupt control register v1 interrupt enable bits of external 0, timer 1 and timer 2 are as- signed to register v1. set the contents of this register through register a with the tv1a instruction. the tav1 instruction can be used to transfer the contents of register v1 to register a. interrupt control register v2 the timer 3, timer 5, a/d, timer 4 and serial i/o interrupt enable bit is assigned to register v2. set the contents of this register through register a with the tv2a instruction. the tav2 instruction can be used to transfer the contents of register v2 to register a. table 6 interrupt control registers notes 1: r represents read enabled, and w represents write enabled. 2: these instructions are equivalent to the nop instruction. 3: select the timer 4 interrupt or serial i/o interrupt by the timer 4, serial i/o interrupt source selection bit (i3 0 ). (7) interrupt sequence interrupts only occur when the respective inte flag, interrupt en- able bits (v1 0 v1 3 , v2 0 v2 3 ), and interrupt request flag are 1. the interrupt actually occurs 2 to 3 machine cycles after the ma- chine cycle in which all three conditions are satisfied. the interrupt occurs after 3 machine cycles when the interrupt conditions are satisfied on execution of two-cycle instructions or three-cycle in- structions. (refer to figure 16). interrupt disabled (snzt4, snzsi instruction is valid) interrupt enabled (snzt4, snzsi instruction is invalid) (note 2) interrupt disabled (snzad instruction is valid) interrupt enabled (snzad instruction is invalid) (note 2) interrupt disabled (snzt5 instruction is valid) interrupt enabled (snzt5 instruction is invalid) (note 2) interrupt disabled (snzt3 instruction is valid) interrupt enabled (snzt3 instruction is invalid) (note 2) v1 3 v1 2 v1 1 v1 0 v2 3 v2 2 v2 1 v2 0 timer 4, serial i/o interrupt enable bit (note 3) a/d interrupt enable bit timer 5 interrupt enable bit timer 3 interrupt enable bit interrupt control register v2 at power down : 0000 2 at reset : 0000 2 0 1 0 1 0 1 0 1 interrupt control register v1 timer 2 interrupt enable bit timer 1 interrupt enable bit external 1 interrupt enable bit external 0 interrupt enable bit interrupt disabled (snzt2 instruction is valid) interrupt enabled (snzt2 instruction is invalid) (note 2) interrupt disabled (snzt1 instruction is valid) interrupt enabled (snzt1 instruction is invalid) (note 2) interrupt disabled (snz1 instruction is valid) interrupt enabled (snz1 instruction is invalid) (note 2) interrupt disabled (snz0 instruction is valid) interrupt enabled (snz0 instruction is invalid) (note 2) 0 1 0 1 0 1 0 1 at power down : 0000 2 at reset : 0000 2 r/w tav1/tv1a r/w tav2/tv2a i3 0 timer 4, serial i/o interrupt source selection bit interrupt control register i3 r/w tai3/ti3a at power down : state retained at reset : 0 2 timer 4 interrupt valid, serial i/o interrupt invalid serial i/o interrupt valid, timer 4 interrupt invalid 0 1 interrupt control register i3 the timer 4, serial i/o interrupt source selection bit is assigned to register i3. set the contents of this register through register a with the ti3a instruction. the tai3 instruction can be used to transfer the contents of register i3 to register a.
rev.2.00 jul 27, 2004 page 25 of 159 rej03b0091-0200z 4524 group fig. 16 interrupt sequence t1f,t2f,t3f,t4f t5f,adf,siof int0,int1 exf0,exf1 t 1 t 2 t 3 t 1 t 2 t 3 t 2 t 3 t 1 t 1 t 2 t 3 t 1 t 2
rev.2.00 jul 27, 2004 page 26 of 159 rej03b0091-0200z 4524 group table 7 external interrupt activated conditions name external 0 interrupt external 1 interrupt input pin d 8 /int0 d 9 /int1 activated condition when the next waveform is input to d 8 /int0 pin falling waveform ( h l ) rising waveform ( l h ) both rising and falling waveforms when the next waveform is input to d 9 /int1 pin falling waveform ( h l ) rising waveform ( l h ) both rising and falling waveforms valid waveform selection bit i1 1 i1 2 i2 1 i2 2 fig. 17 external interrupt circuit structure external interrupts the 4524 group has the external 0 interrupt and external 1 inter- rupt. an external interrupt request occurs when a valid waveform is input to an interrupt input pin (edge detection). the external interrupt can be controlled with the interrupt control registers i1 and i2. ri s i ng f a lli ng o n e - s i d e d e d g e d e t e c t i o n c i r c u i t key-on wakeup e x t e r n a l 1 i n t e r r u p t t i m e r 3 c o u n t s t a r t s y n c h r o n o u s c i r c u i t level detection circuit edge detection circuit skip decision (snzi1 instruction) both edges detection circuit 0 1 i 2 2 0 1 exf1 i2 1 d 9 / i n t 1 k 2 2 i2 3 0 1 k2 3 ri s i ng 0 1 f a lli ng i 1 2 o n e - s i d e d e d g e d e t e c t i o n c i r c u i t key-on wakeup 0 1 exf0 external 0 interrupt i1 1 d 8 / i n t 0 k2 0 timer 1 count start synchronous circuit i1 3 (note 1) level detection circuit edge detection circuit 0 1 k2 1 skip decision (snzi0 instruction) b o t h e d g e s d e t e c t i o n c i r c u i t this symbol represents a parasitic diode on the port. n o t e s 1 : (note 2) (note 3) ( n o t e 1 ) ( n o t e 2 ) ( n o t e 3 ) 2 : i 1 2 ( i 2 2 ) = 0 : l l e v e l d e t e c t e d i 1 2 ( i 2 2 ) = 1 : h l e v e l d e t e c t e d 3 : i 1 2 ( i 2 2 ) = 0 : f a l l i n g e d g e d e t e c t e d i 1 2 ( i 2 2 ) = 1 : r i s i n g e d g e d e t e c t e d
rev.2.00 jul 27, 2004 page 27 of 159 rej03b0091-0200z 4524 group (1) external 0 interrupt request flag (exf0) external 0 interrupt request flag (exf0) is set to 1 when a valid waveform is input to d 8 /int0 pin. the valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (refer to figure 16). the state of exf0 flag can be examined with the skip instruction (snz0). use the interrupt control register v1 to select the interrupt or the skip instruction. the exf0 flag is cleared to 0 when an in- terrupt occurs or when the next instruction is skipped with the skip instruction. external 0 interrupt activated condition external 0 interrupt activated condition is satisfied when a valid waveform is input to d 8 /int0 pin. the valid waveform can be selected from rising waveform, falling waveform or both rising and falling waveforms. an example of how to use the external 0 interrupt is as follows. ? 1 for the int0 pin to be in the in- put enabled state. ? ? 0 with the snz0 instruction. ? ? 1. the external 0 interrupt is now enabled. now when a valid wave- form is input to the d 8 /int0 pin, the exf0 flag is set to 1 and the external 0 interrupt occurs. (2) external 1 interrupt request flag (exf1) external 1 interrupt request flag (exf1) is set to 1 when a valid waveform is input to d 9 /int1 pin. the valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (refer to figure 16). the state of exf1 flag can be examined with the skip instruction (snz1). use the interrupt control register v1 to select the interrupt or the skip instruction. the exf1 flag is cleared to 0 when an in- terrupt occurs or when the next instruction is skipped with the skip instruction. external 1 interrupt activated condition external 1 interrupt activated condition is satisfied when a valid waveform is input to d 9 /int1 pin. the valid waveform can be selected from rising waveform, falling waveform or both rising and falling waveforms. an example of how to use the external 1 interrupt is as follows. ? 1 for the int1 pin to be in the in- put enabled state. ? ? 0 with the snz1 instruction. ? ? 1. the external 1 interrupt is now enabled. now when a valid wave- form is input to the d 9 /int1 pin, the exf1 flag is set to 1 and the external 1 interrupt occurs.
rev.2.00 jul 27, 2004 page 28 of 159 rej03b0091-0200z 4524 group (3) external interrupt control registers interrupt control register i1 register i1 controls the valid waveform for the external 0 inter- rupt. set the contents of this register through register a with the ti1a instruction. the tai1 instruction can be used to transfer the contents of register i1 to register a. table 8 external interrupt control register interrupt control register i2 register i2 controls the valid waveform for the external 1 inter- rupt. set the contents of this register through register a with the ti2a instruction. the tai2 instruction can be used to transfer the contents of register i2 to register a. notes 1: r represents read enabled, and w represents write enabled. 2: when the contents of these bits (i1 2 , i1 3 , i2 2 and i2 3 ) are changed, the external interrupt request flag (exf0, exf1) may be set. i1 3 i1 2 i1 1 i1 0 int0 pin input control bit (note 2) interrupt valid waveform for int0 pin/ return level selection bit (note 2) int0 pin edge detection circuit control bit int0 pin timer 1 count start synchronous circuit selection bit interrupt control register i1 r/w tai1/ti1a at power down : state retained at reset : 0000 2 int0 pin input disabled int0 pin input enabled falling waveform/ l level ( l level is recognized with the snzi0 instruction) rising waveform/ h level ( h level is recognized with the snzi0 instruction) one-sided edge detected both edges detected timer 1 count start synchronous circuit not selected timer 1 count start synchronous circuit selected 0 1 0 1 0 1 0 1 i2 3 i2 2 i2 1 i2 0 int1 pin input control bit (note 2) interrupt valid waveform for int1 pin/ return level selection bit (note 2) int1 pin edge detection circuit control bit int1 pin timer 3 count start synchronous circuit selection bit interrupt control register i2 r/w tai2/ti2a at power down : state retained at reset : 0000 2 int1 pin input disabled int1 pin input enabled falling waveform/ l level ( l level is recognized with the snzi1 instruction) rising waveform/ h level ( h level is recognized with the snzi1 instruction) one-sided edge detected both edges detected timer 3 count start synchronous circuit not selected timer 3 count start synchronous circuit selected 0 1 0 1 0 1 0 1
rev.2.00 jul 27, 2004 page 29 of 159 rej03b0091-0200z 4524 group (4) notes on external 0 interrupts ? depending on the input state of the d 8 /int0 pin, the external 0 in- terrupt request flag (exf0) may be set when the bit 3 of register i1 is changed. in order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register v1 to 0 (refer to figure 18 ? 0 after executing at least one instruction (refer to figure 18 ? ? ??? ? ??? ? ? ? fig. 18 external 0 interrupt program example-1 ? when the input of int0 pin is disabled, invalidate the key-on wakeup function of int0 pin (register k2 0 = 0 ) before system goes into the power down mode. (refer to figure 19 ? la 0 ; ( ??? ? ? fig. 19 external 0 interrupt program example-2 ? depending on the input state of the d 8 /int0 pin, the external 0 in- terrupt request flag (exf0) may be set when the bit 2 of register i1 is changed. in order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register v1 to 0 (refer to figure 20 ? 0 after executing at least one instruction (refer to figure 20 ? ? ??? ? ? ?? ? ? ? fig. 20 external 0 interrupt program example-3
rev.2.00 jul 27, 2004 page 30 of 159 rej03b0091-0200z 4524 group (5) notes on external 1 interrupts ? depending on the input state of the d 9 /int1 pin, the external 1 in- terrupt request flag (exf1) may be set when the bit 3 of register i2 is changed. in order to avoid the occurrence of an unexpected interrupt, clear the bit 1 of register v1 to 0 (refer to figure 21 ? 0 after executing at least one instruction (refer to figure 21 ? ? ?? ? ? ??? ? ? ? fig. 21 external 1 interrupt program example-1 ? when the input of int1 pin is disabled, invalidate the key-on wakeup function of int1 pin (register k2 2 = 0 ) before system goes into the power down mode. (refer to figure 22 ? la 0 ; ( ? ?? ? ? fig. 22 external 1 interrupt program example-2 ? depending on the input state of the d 9 /int1 pin, the external 1 in- terrupt request flag (exf1) may be set when the bit 2 of register i2 is changed. in order to avoid the occurrence of an unexpected interrupt, clear the bit 1 of register v1 to 0 (refer to figure 23 ? 0 after executing at least one instruction (refer to figure 23 ? ? ?? ? ? ? ?? ? ? ? fig. 23 external 1 interrupt program example-3
rev.2.00 jul 27, 2004 page 31 of 159 rej03b0091-0200z 4524 group timers the 4524 group has the following timers. programmable timer the programmable timer has a reload register and enables the frequency dividing ratio to be set. it is decremented from a set- ting value n. when it underflows (count to n + 1), a timer interrupt request flag is set to 1, new data is loaded from the reload reg- ister, and count continues (auto-reload function). fixed dividing frequency timer the fixed dividing frequency timer has the fixed frequency divid- ing ratio (n). an interrupt request flag is set to 1 after every n count of a count pulse. fig. 24 auto-reload function the 4524 group timer consists of the following circuits. prescaler : 8-bit programmable timer timer 1 : 8-bit programmable timer timer 2 : 8-bit programmable timer timer 3 : 8-bit programmable timer timer 4 : 8-bit programmable timer timer 5 : 16-bit fixed dividing frequency timer timer lc : 4-bit programmable timer watchdog timer : 16-bit fixed dividing frequency timer (timers 1, 2, 3, 4 and 5 have the interrupt function, respectively) prescaler and timers 1, 2, 3, 4, 5 and lc can be controlled with the timer control registers pa, w1 to w6. the watchdog timer is a free counter which is not controlled with the control register. each function is described below. ff 16 n 00 16 n : counter initial value c o u n t s t a r t s r e l o a d reload 1 s t u n d e r f l o w 2 n d u n d e r f l o w n + 1 c o u n t n + 1 c o u n t t i m e an interrupt occurs or a skip instruction is executed. t i m e r i n t e r r u p t r e q u e s t f l a g t h e c o n t e n t s o f c o u n t e r 1 0
rev.2.00 jul 27, 2004 page 32 of 159 rej03b0091-0200z 4524 group count source instruction clock (instck) instruction clock (instck) prescaler output (orclk) timer 5 underflow (t5udf) cntr0 input system clock (stck) prescaler output (orclk) timer 1 underflow (t1udf) pwm output (pwmout) pwm output (pwmout) prescaler output (orclk) timer 2 underflow (t2udf) cntr1 input x in input prescaler output (orclk) x cin input bit 4 of timer 5 prescaler output (orclk) instruction clock (instck) structure 8-bit programmable binary down counter 8-bit programmable binary down counter (link to int0 input) 8-bit programmable binary down counter 8-bit programmable binary down counter (link to int1 input) 8-bit programmable binary down counter (pwm output function) 16-bit fixed dividing frequency 4-bit programmable binary down counter 16-bit fixed dividing frequency circuit prescaler timer 1 timer 2 timer 3 timer 4 timer 5 timer lc watchdog timer use of output signal timer 1, 2, 3, 4 and lc count sources timer 2 count source cntr0 output timer 1 interrupt timer 3 count source cntr0 output timer 2 interrupt cntr1 output control timer 3 interrupt timer 2, 3 count source cntr1 output timer 4 interrupt timer 1, lc count source timer 5 interrupt lcd clock system reset (count twice) wdf flag decision frequency dividing ratio 1 to 256 1 to 256 1 to 256 1 to 256 1 to 256 8192 16384 32768 65536 1 to 16 65534 control register pa w1 w2 w2 w3 w4 w5 w6 table 9 function related timers
rev.2.00 jul 27, 2004 page 33 of 159 rej03b0091-0200z 4524 group fig. 25 timer structure (1) s t c k 1 w2 2 0 w 2 1 , w 2 0 1 0 1 1 01 0 0 o r c l k t 1 u d f p w m o u t t2f (tab2) (tab2) (t2ab) ( t 2 a b ) (t2ab) t 1 u d f 1 w2 3 0 1/2 t 2 u d f 1/2 1 w 6 0 0 p o r t d 7 o u t p u t d 7 /cntr0 division circuit divided by 8 divided by4 divided by 2 s y s t e m c l o c k ( s t c k ) x c i n i n s t r u c t i o n c l o c k ( i n s t c k ) m u l t i - p l e x e r ( c m c k / c r c k ) q u a r t z - c r y s t a l o s c i l l a t i o n 1 mr 0 0 orclk reload register rps (8) prescaler (8) r e g i s t e r b r e g i s t e r a (tabps) (tabps) ( t p s a b ) 1 p a 0 0 mr 3 , mr 2 0 1 0 0 10 1 1 i n s t c k 0 1 q r s 0 1 i 1 2 0 1 d 8 / i n t 0 w 1 3 t 1 u d f i1 0 i 1 3 i1 1 i1 0 1 w1 2 0 w1 1 , w1 0 10 1 1 01 00 orclk t5udf d 7 /cntr0 t 1 f (tab1) (tab1) (t1ab) (t1ab) (t1ab) (tr1ab) (tpsab) ( t p s a b ) p w m o u t 0 1 q r s 0 1 i 2 2 0 1 d 9 / i n t 1 w 3 3 t 3 u d f i2 0 i2 3 i2 1 i2 0 1 w3 2 0 w3 1 , w3 0 10 11 01 0 0 o r c l k t 2 u d f c/cntr1 t 3 f (tab3) (tab3) (t3ab) (t3ab) (t3ab) ( t r 3 a b ) t 5 u d f : p w m o u t : t i m e r 5 u n d e r f l o w s i g n a l ( f r o m t i m e r 5 ) p w m o u t p u t s i g n a l ( f r o m t i m e r 4 o u t p u t u n i t ) (note 1) (note 2) (note 4) ( n o t e 4 ) ( n o t e 3 ) (note 4) on-chip oscillator x in c e r a m i c r e s o n a n c e ( c m c k ) r c o s c i l l a t i o n (crck) timer 1 (8) timer 1 interrupt reload register r1 (8) register b r e g i s t e r a t i m e r 1 u n d e r f l o w s i g n a l ( t 1 u d f ) o ne-s id e d e d ge detection circuit b ot h e d ges detection circuit f a l l i n g r i s i n g ( n o t e 4 ) o n e - s i d e d e d g e d e t e c t i o n c i r c u i t b ot h e d ges detection circuit falling r i s i n g timer 2 interrupt t i m e r 2 u n d e r f l o w s i g n a l ( t 2 u d f ) timer 2 (8) r e l o a d r e g i s t e r r 2 ( 8 ) register b register a timer 3 interrupt timer 3 underflow signal (t3udf) t i m e r 3 ( 8 ) reload register r3 (8) register b register a i n t e r n a l c l o c k g e n e r a t i n g c i r c u i t ( d i v i d e d b y 3 ) data is set automatically from each reload register when timer underflows (auto-reload function). notes 1: when cmck instruction is executed, ceramic resonance is selected. when crck instruction is executed, rc oscillation is selected. when any instructions are not executed, on-chip oscillator clock (internal oscillation) is selected. 2: timer 1 count start synchronous circuit is set by the valid edge of d 8 /int0 pin selected by bits 1 (i1 1 ) and 2 (i1 2 ) of register i1. 3: timer 3 count start synchronous circuit is set by the valid edge of d 9 /int1 pin selected by bits 1 (i2 1 ) and 2 (i2 2 ) of register i2. 4: count source is stopped by clearing to 0.
rev.2.00 jul 27, 2004 page 34 of 159 rej03b0091-0200z 4524 group fig. 26 timer structure (2) r e g i s t e r a r e l o a d c o n t r o l c i r c u i t ( t a b 4 ) w4 3 q r t ( t 4 a b ) timer 4 (8) r e g i s t e r b r e l o a d r e g i s t e r r 4 h ( 8 ) ( t a b 4 ) ( t 4 a b ) p w m o d (t4r4l) t 4 f o r c l k x i n 1 w4 1 0 timer 4, serial i/o interrupt 1 w4 0 0 ( t 4 h a b ) t 3 u d f p w m o d p o r t c o u t p u t q c / c n t r 1 w 3 1 w 3 0 r d t w3 2 w 6 1 1 w5 2 0 t i m e r 5 ( 1 6 ) 1 - - 4 - - - - - - - -13 14 15 16 w5 1 , w5 0 01 00 10 11 t5f t i m e r 5 i n t e r r u p t timer 5 underflow signal (t5udf) x c i n 1 w 6 3 0 1 / 2 l c d c l o c k reload register rlc (4) timer lc (4) register a (tlca) ( t l c a ) 1 w6 2 0 orclk watchdog reset signal w a t c h d o g t i m e r ( 1 6 ) q s q t d w d f 2 reset signal r q r s wef reset signal r wdf1 w r s t i n s t r u c t i o n i n s t c k + d w d t i n s t r u c t i o n w r s t i n s t r u c t i o n 1 - - - - - - - - - - - - - - - - - - - 1 6 instck : orclk : instruction clock (system clock divided by 3) prescaler output (instruction clock divided by 1 to 256) ( n o t e 4 ) ( n o t e 5 ) pwmout (to timer 2 and timer 3) 0 w 4 2 1 ??interval expansion (note 4) ( n o t e 6 ) (note 4) ( n o t e 8 ) (note 7) 1 / 2 r e g i s t e r a r e g i s t e r b reload register r4l (8) data is set automatically from each reload register when timer underflows (auto-reload function). notes 4: count source is stopped by clearing to ?. 5: x in cannot be used as count source when bit 1 (mr1) of register mr is set to ??and f(x in ) oscillation is stopped. 6: this timer is initialized (initial value = ffff 16 ) by stop of count source (w5 2 = ??. 7: flag wdf1 is cleared to ??and the next instruction is skipped when the wrst instruction is executed while flag wdf1 = ?? the next instruction is not skipped even when the wrst instruction is executed while flag wdf1 = ?? 8: flag wef is cleared to ??and watchdog timer reset does not occur when the dwdt instruction and wrst instruction are executed continuously. 9: the wef flag is set to ??at system reset or ram back-up mode. 1 i3 0 0 s i o f ( f r o m s e r i a l i / o ) ( n o t e 9 )
rev.2.00 jul 27, 2004 page 35 of 159 rej03b0091-0200z 4524 group w2 1 0 0 1 1 timer 1 underflow signal divided by 2 output timer 2 underflow signal divided by 2 output stop (state retained) operating count source system clock (stck) prescaler output (orclk) timer 1 underflow signal (t1udf) pwm signal (pwmout) cntr0 output control bit timer 2 control bit timer 2 count source selection bits 0 1 0 1 w2 0 0 1 0 1 timer control register w2 at power down : state retained at reset : 0000 2 notes 1: r represents read enabled, and w represents write enabled. 2: this function is valid only when the timer 1 count start synchronous circuit is selected (i1 0 = 1 ). 3: this function is valid only when the timer 3 count start synchronous circuit is selected (i2 0 = 1 ). 4: port c output is invalid when cntr1 input is selected for the timer 3 count source. w2 3 w2 2 w2 1 w2 0 0 1 stop (state initialized) operating prescaler control bit timer control register pa w tpaa at power down : 0 2 at reset : 0 2 pa 0 w1 1 0 0 1 1 timer 1 count auto-stop circuit not selected timer 1 count auto-stop circuit selected stop (state retained) operating count source instruction clock (instck) prescaler output (orclk) timer 5 underflow signal (t5udf) cntr0 input timer 1 count auto-stop circuit selection bit (note 2) timer 1 control bit timer 1 count source selection bits 0 1 0 1 w1 0 0 1 0 1 timer control register w1 r/w taw1/tw1a at power down : state retained at reset : 0000 2 w1 3 w1 2 w1 1 w1 0 w3 1 0 0 1 1 timer 3 count auto-stop circuit not selected timer 3 count auto-stop circuit selected stop (state retained) operating count source pwm signal (pwmout) prescaler output (orclk) timer 2 underflow signal (t2udf) cntr1 input timer 3 count auto-stop circuit selection bit (note 3) timer 3 control bit timer 3 count source selection bits (note 4) 0 1 0 1 w3 0 0 1 0 1 timer control register w3 at power down : state retained at reset : 0000 2 w3 3 w3 2 w3 1 w3 0 r/w taw2/tw2a r/w taw3/tw3a table 10 timer related registers
rev.2.00 jul 27, 2004 page 36 of 159 rej03b0091-0200z 4524 group stop (state retained) operating bit 4 (t5 4 ) of timer 5 prescaler output (orclk) cntr1 output auto-control circuit not selected cntr1 output auto-control circuit selected d 7 (i/o)/cntr0 input cntr0 input/output/d 7 (input) timer lc control bit timer lc count source selection bit cntr1 output auto-control circuit selection bit d 7 /cntr0 pin function selection bit (note 2) 0 1 0 1 0 1 0 1 timer control register w6 at power down : state retained at reset : 0000 2 w6 3 w6 2 w6 1 w6 0 cntr1 output invalid cntr1 output valid pwm signal h interval expansion function invalid pwm signal h interval expansion function valid stop (state retained) operating x in input prescaler output (orclk) divided by 2 cntr1 output control bit pwm signal h interval expansion function control bit timer 4 control bit timer 4 count source selection bit 0 1 0 1 0 1 0 1 w4 3 w4 2 w4 1 w4 0 w5 1 0 0 1 1 not used timer 5 control bit timer 5 count value selection bits 0 1 0 1 w5 0 0 1 0 1 timer control register w5 at power down : state retained at reset : 0000 2 w5 3 w5 2 w5 1 w5 0 notes 1: r represents read enabled, and w represents write enabled. 2: cntr0 input is valid only when cntr0 input is selected for the timer 1 count source. this bit has no function, but read/write is enabled. stop (state initialized) operating count value underflow occurs every 8192 counts underflow occurs every 16384 counts underflow occurs every 32768 counts underflow occurs every 65536 counts r/w taw4/tw4a timer control register w4 at power down : 0000 2 at reset : 0000 2 r/w taw5/tw5a r/w taw6/tw6a
rev.2.00 jul 27, 2004 page 37 of 159 rej03b0091-0200z 4524 group (1) timer control registers timer control register pa register pa controls the count operation of prescaler. set the contents of this register through register a with the tpaa instruc- tion. timer control register w1 register w1 controls the selection of timer 1 count auto-stop cir- cuit, and the count operation and count source of timer 1. set the contents of this register through register a with the tw1a instruc- tion. the taw1 instruction can be used to transfer the contents of register w1 to register a. timer control register w2 register w2 controls the selection of cntr0 output, and the count operation and count source of timer 2. set the contents of this register through register a with the tw2a instruction. the taw2 instruction can be used to transfer the contents of register w2 to register a. timer control register w3 register w3 controls the selection of timer 3 count auto-stop cir- cuit, and the count operation and count source of timer 3. set the contents of this register through register a with the tw3a instruc- tion. the taw3 instruction can be used to transfer the contents of register w3 to register a. timer control register w4 register w4 controls the cntr1 output, the expansion of h in- terval of pwm output, and the count operation and count source of timer 4. set the contents of this register through register a with the tw4a instruction. the taw4 instruction can be used to trans- fer the contents of register w4 to register a. timer control register w5 register w5 controls the count operation and count source of timer 5. set the contents of this register through register a with the tw5a instruction. the taw5 instruction can be used to trans- fer the contents of register w5 to register a. timer control register w6 register w6 controls the operation and count source of timer lc, the selection of cntr1 output auto-control circuit and the d 7 / cntr0 pin function. set the contents of this register through reg- ister a with the tw6a instruction. the taw6 instruction can be used to transfer the contents of register w6 to register a.. (2) prescaler (interrupt function) prescaler is an 8-bit binary down counter with the prescaler reload register prs. data can be set simultaneously in prescaler and the reload register rps with the tpsab instruction. data can be read from reload register rps with the tabps instruction. stop counting and then execute the tpsab or tabps instruction to read or set prescaler data. prescaler starts counting after the following process; ? ? 1. when a value set in reload register rps is n, prescaler divides the count source signal by n + 1 (n = 0 to 255). count source for prescaler is the instruction clock (instck). once count is started, when prescaler underflows (the next count pulse is input after the contents of prescaler becomes 0 ), new data is loaded from reload register rps, and count continues (auto-reload function). the output signal (orclk) of prescaler can be used for timer 1, 2, 3, 4 and lc count sources. (3) timer 1 (interrupt function) timer 1 is an 8-bit binary down counter with the timer 1 reload reg- ister (r1). data can be set simultaneously in timer 1 and the reload register (r1) with the t1ab instruction. data can be written to re- load register (r1) with the tr1ab instruction. data can be read from timer 1 with the tab1 instruction. stop counting and then execute the t1ab or tab1 instruction to read or set timer 1 data. when executing the tr1ab instruction to set data to reload regis- ter r1 while timer 1 is operating, avoid a timing when timer 1 underflows. timer 1 starts counting after the following process; ? ? ? 1. when a value set in reload register r1 is n, timer 1 divides the count source signal by n + 1 (n = 0 to 255). once count is started, when timer 1 underflows (the next count pulse is input after the contents of timer 1 becomes 0 ), the timer 1 interrupt request flag (t1f) is set to 1, new data is loaded from reload register r1, and count continues (auto-reload function). int0 pin input can be used as the start trigger for timer 1 count op- eration by setting the bit 0 of register i1 to 1. also, in this time, the auto-stop function by timer 1 underflow can be performed by setting the bit 3 of register w1 to 1. timer 1 underflow signal divided by 2 can be output from cntr0 pin by clearing bit 3 of register w2 to 0 and setting bit 0 of regis- ter w6 to 1 .
rev.2.00 jul 27, 2004 page 38 of 159 rej03b0091-0200z 4524 group (4) timer 2 (interrupt function) timer 2 is an 8-bit binary down counter with the timer 2 reload reg- ister (r2). data can be set simultaneously in timer 2 and the reload register (r2) with the t2ab instruction. data can be read from timer 2 with the tab2 instruction. stop counting and then execute the t2ab or tab2 instruction to read or set timer 2 data. timer 2 starts counting after the following process; ? ? ? 1. when a value set in reload register r2 is n, timer 2 divides the count source signal by n + 1 (n = 0 to 255). once count is started, when timer 2 underflows (the next count pulse is input after the contents of timer 2 becomes 0 ), the timer 2 interrupt request flag (t2f) is set to 1, new data is loaded from reload register r2, and count continues (auto-reload function). timer 2 underflow signal divided by 2 can be output from cntr0 pin by setting bit 3 of register w2 to 1 and setting bit 0 of register w6 to 1 . (5) timer 3 (interrupt function) timer 3 is an 8-bit binary down counter with the timer 3 reload reg- ister (r3). data can be set simultaneously in timer 3 and the reload register (r3) with the t3ab instruction. data can be written to re- load register (r3) with the tr3ab instruction. data can be read from timer 3 with the tab3 instruction. stop counting and then execute the t3ab or tab3 instruction to read or set timer 3 data. when executing the tr3ab instruction to set data to reload regis- ter r3 while timer 3 is operating, avoid a timing when timer 3 underflows. timer 3 starts counting after the following process; ? ? ? 1. when a value set in reload register r3 is n, timer 3 divides the count source signal by n + 1 (n = 0 to 255). once count is started, when timer 3 underflows (the next count pulse is input after the contents of timer 3 becomes 0 ), the timer 3 interrupt request flag (t3f) is set to 1, new data is loaded from reload register r3, and count continues (auto-reload function). int1 pin input can be used as the start trigger for timer 3 count op- eration by setting the bit 0 of register i2 to 1. also, in this time, the auto-stop function by timer 3 underflow can be performed by setting the bit 3 of register w3 to 1. (6) timer 4 (interrupt function) timer 4 is an 8-bit binary down counter with two timer 4 reload reg- isters (r4l, r4h). data can be set simultaneously in timer 4 and the reload register r4l with the t4ab instruction. data can be set in the reload register r4h with the t4hab instruction. the contents of reload register r4l set with the t4ab instruction can be set to timer 4 again with the t4r4l instruction. data can be read from timer 4 with the tab4 instruction. stop counting and then execute the t4ab or tab4 instruction to read or set timer 4 data. when executing the t4hab instruction to set data to reload regis- ter r4h while timer 4 is operating, avoid a timing when timer 4 underflows. timer 4 starts counting after the following process; ? ? ? 1. when a value set in reload register r4l is n, timer 4 divides the count source signal by n + 1 (n = 0 to 255). once count is started, when timer 4 underflows (the next count pulse is input after the contents of timer 4 becomes 0 ), the timer 4 interrupt request flag (t4f) is set to 1, new data is loaded from reload register r4l, and count continues (auto-reload function). when bit 3 of register w4 is set to 1 , timer 4 reloads data from re- load register r4l and r4h alternately each underflow. timer 4 generates the pwm signal (pwmout) of the l interval set as reload register r4l, and the h interval set as reload regis- ter r4h. the pwm signal (pwmout) is output from cntr1 pin. when bit 2 of register w4 is set to 1 at this time, the interval (pwm signal h interval) set to reload register r4h for the counter of timer 4 is extended for a half period of count source. in this case, when a value set in reload register r4h is n, timer 4 divides the count source signal by n + 1.5 (n = 1 to 255). when this function is used, set 1 or more to reload register r4h. when bit 1 of register w6 is set to 1 , the pwm signal output to cntr1 pin is switched to valid/invalid each timer 3 underflow. however, when timer 3 is stopped (bit 2 of register w3 is cleared to 0 ), this function is canceled. even when bit 1 of a register w4 is cleared to 0 in the h interval of pwm signal, timer 4 does not stop until it next timer 4 underflow. when clearing bit 1 of register w4 to 0 to stop timer 4, avoid a timing when timer 4 underflows.
rev.2.00 jul 27, 2004 page 39 of 159 rej03b0091-0200z 4524 group (7) timer 5 (interrupt function) timer 5 is a 16-bit binary down counter. timer 5 starts counting after the following process; ? ? 1. count source for timer 5 is the sub-clock input (x cin ). once count is started, when timer 5 underflows (the set count value is counted), the timer 5 interrupt request flag (t5f) is set to 1, and count continues. bit 4 of timer 5 can be used as the timer lc count source for the lcd clock generating. when bit 2 of register w5 is cleared to 0 , timer 5 is initialized to ffff 16 and count is stopped. timer 5 can be used as the counter for clock because it can be op- erated at clock operating mode (pof instruction execution). when timer 5 underflow occurs at clock operating mode, system returns from the power down state. (8) timer lc timer lc is a 4-bit binary down counter with the timer lc reload register (rlc). data can be set simultaneously in timer lc and the reload register (rlc) with the tlca instruction. data cannot be read from timer lc. stop counting and then execute the tlca in- struction to set timer lc data. timer lc starts counting after the following process; ? ? ? 1. when a value set in reload register rlc is n, timer lc divides the count source signal by n + 1 (n = 0 to 15). once count is started, when timer lc underflows (the next count pulse is input after the contents of timer lc becomes 0 ), new data is loaded from reload register rlc, and count continues (auto-re- load function). timer lc underflow signal divided by 2 can be used for the lcd clock. (9) timer input/output pin (d 7 /cntr0 pin, c/cntr1 pin) cntr0 pin is used to input the timer 1 count source and output the timer 1 and timer 2 underflow signal divided by 2. cntr1 pin is used to input the timer 3 count source and output the pwm signal generated by timer 4. when the pwm signal is output from c/cntr1 pin, set 0 to the output latch of port c. the d 7 /cntr0 pin function can be selected by bit 0 of register w6. the selection of cntr1 output signal can be controlled by bit 3 of register w4. when the cntr0 input is selected for timer 1 count source, timer 1 counts the rising waveform of cntr0 input. when the cntr1 input is selected for timer 3 count source, timer 3 counts the rising waveform of cntr1 input. also, when the cntr1 input is selected, the output of port c is invalid (high-im- pedance state). (10) timer interrupt request flags (t1f, t2f, t3f, t4f, t5f) each timer interrupt request flag is set to 1 when each timer underflows. the state of these flags can be examined with the skip instructions (snzt1, snzt2, snzt3, snzt4, snzt5). use the interrupt control register v1, v2 to select an interrupt or a skip instruction. an interrupt request flag is cleared to 0 when an interrupt occurs or when the next instruction is skipped with a skip instruction.
rev.2.00 jul 27, 2004 page 40 of 159 rej03b0091-0200z 4524 group (11) count start synchronization circuit (timer 1, timer 3) timer 1 and timer 3 have the count start synchronous circuit which synchronizes the input of int0 pin and int1 pin, and can start the timer count operation. timer 1 count start synchronous circuit function is selected by set- ting the bit 0 of register i1 to 1 and the control by int0 pin input can be performed. timer 3 count start synchronous circuit function is selected by set- ting the bit 0 of register i2 to 1 and the control by int1 pin input can be performed. when timer 1 or timer 3 count start synchronous circuit is used, the count start synchronous circuit is set, the count source is input to each timer by inputting valid waveform to int0 pin or int1 pin. the valid waveform of int0 pin or int1 pin to set the count start synchronous circuit is the same as the external interrupt activated condition. once set, the count start synchronous circuit is cleared by clearing the bit i1 0 or i2 0 to 0 or reset. however, when the count auto-stop circuit is selected, the count start synchronous circuit is cleared (auto-stop) at the timer 1 or timer 3 underflow. (12) count auto-stop circuit (timer 1, timer 3) timer 1 has the count auto-stop circuit which is used to stop timer 1 automatically by the timer 1 underflow when the count start syn- chronous circuit is used. the count auto-stop cicuit is valid by setting the bit 3 of register w1 to 1 . it is cleared by the timer 1 underflow and the count source to timer 1 is stopped. this function is valid only when the timer 1 count start synchronous circuit is selected. timer 3 has the count auto-stop circuit which is used to stop timer 3 automatically by the timer 3 underflow when the count start syn- chronous circuit is used. the count auto-stop cicuit is valid by setting the bit 3 of register w3 to 1 . it is cleared by the timer 3 underflow and the count source to timer 3 is stopped. this function is valid only when the timer 3 count start synchronous circuit is selected. (13) precautions note the following for the use of timers. prescaler stop counting and then execute the tabps instruction to read from prescaler data. stop counting and then execute the tpsab instruction to set prescaler data. timer count source stop timer 1, 2, 3, 4 and lc counting to change its count source. reading the count value stop timer 1, 2, 3 or 4 counting and then execute the data read instruction (tab1, tab2, tab3, tab4) to read its data. writing to the timer stop timer 1, 2, 3, 4 or lc counting and then execute the data write instruction (t1ab, t2ab, t3ab, t4ab, tlca) to write its data. writing to reload register r1, r3, r4h when writing data to reload register r1, reload register r3 or re- load regiser r4h while timer 1, timer 3 or timer 4 is operating, avoid a timing when timer 1, timer 3 or timer 4 underflows. timer 4 avoid a timing when timer 4 underflows to stop timer 4. when h interval extension function of the pwm signal is set to be valid , set 1 or more to reload register r4h. timer 5 stop timer 5 counting to change its count source. timer input/output pin set the port c output latch to 0 to output the pwm signal from c/cntr pin.
rev.2.00 jul 27, 2004 page 41 of 159 rej03b0091-0200z 4524 group fig. 27 timer 4 operation (reload register r4l: ?3 16 ? r4h: ?2 16 ? 0 ) timer 4 count source timer 4 count value (reload register) 02 16 01 16 00 16 03 16 02 16 01 16 00 16 03 16 02 16 01 16 00 16 03 16 02 16 01 16 00 16 03 16 02 16 01 16 00 16 03 16 (r4l) timer 4 underflow signal pwm signal (output invalid) timer 4 start pwm signal l fixed 02 16 03 16 01 16 00 16 02 16 01 16 00 16 03 16 02 16 01 16 00 16 02 16 01 16 00 16 03 16 02 16 01 16 00 16 02 16 01 16 (r4h) pwm period 7 clock pwm period 7 clock 03 16 01 16 00 16 02 16 02 16 01 16 00 16 02 16 01 16 00 16 03 16 02 16 01 16 00 16 02 16 01 16 00 16 03 16 02 16 (r4l) (r4h) (r4l) (r4h) (r4l) (r4h) pwm period 7.5 clock pwm period 7.5 clock 1 ) pwm signal h interval extension function: invalid (w4 2 = 0 ) timer 4 count source timer 4 count value (reload register) timer 4 underflow signal pwm signal timer 4 count source timer 4 count value (reload register) timer 4 underflow signal pwm signal timer 4 start timer 4 start 1 ) pwm signal h interval extension function: valid (w4 2 = 1 ) (note) note: at pwm signal h interval extension function: valid, set 01 16 or more to reload register r4h. (r4l) (r4h) (r4l) (r4h) (r4l) (r4l) (r4l) (r4l) (r4l) 3 clock 3 clock 3.5 clock 3.5 clock
rev.2.00 jul 27, 2004 page 42 of 159 rej03b0091-0200z 4524 group fig. 28 cntr1 output auto-control function by timer 3 c n t r 1 o u t p u t a u t o - c o n t r o l c i r c u i t b y t i m e r 3 i s s e l e c t e d . cntr1 output r e g i s t e r w 6 1 w h e n t h e c n t r 1 o u t p u t a u t o - c o n t r o l f u n c t i o n i s s e t t o b e i n v a l i d w h i l e t h e c n t r 1 o u t p u t i s i n v a l i d , t h e c n t r 1 o u t p u t i n v a l i d s t a t e i s r e t a i n e d . w h e n t h e c n t r 1 o u t p u t a u t o - c o n t r o l f u n c t i o n i s s e t t o b e i n v a l i d w h i l e t h e c n t r 1 o u t p u t i s v a l i d , t h e c n t r 1 o u t p u t v a l i d s t a t e i s r e t a i n e d . w h e n t i m e r 3 i s s t o p p e d , t h e c n t r 1 o u t p u t a u t o - c o n t r o l f u n c t i o n b e c o m e s i n v a l i d . n o t e : w h e n t h e p w m s i g n a l i s o u t p u t f r o m c / c n t r 1 p i n , s e t t h e o u t p u t l a t c h o f p o r t c t o 0 . 1 ) c n t r 1 o u t p u t a u t o - c o n t r o l c i r c u i t s e l e c t e d ( w 6 1 = 1 ) t i m e r 3 u n d e r f l o w s i g n a l pwm signal t i m e r 3 s t a r t c n t r 1 o u t p u t s t a r t ? ?? ? ? ?
rev.2.00 jul 27, 2004 page 43 of 159 rej03b0091-0200z 4524 group fig. 29 timer 4 count start/stop timing (r4l) (r4h) (r4l) timer 4 count start timing waveform extension function of cntr1 output h interval: invalid (w4 2 = 0 ), cntr1 output: valid (w4 3 = 1 ), count source: x in input selected (w4 0 = 0 ), reload register r4l: 03 16 reload register r4h: 02 16 timer 4 count start timing tw4a instruction execution cycle (w4 1 ) 1 02 16 01 16 00 16 02 16 03 16 02 16 01 16 00 16 03 16 02 16 00 16 00 16 02 16 01 16 00 16 03 16 02 16 01 16 02 16 (r4h) (r4l) 01 16 (r4h) (note 1) notes 1: in order to stop timer 4 at cntr1 output valid (w4 3 = 1 ), avoid a timing when timer 4 underflows. if these timings overlap, a hazard may occur in a cntr1 output waveform. 2: at cntr1 output valid, timer 4 stops after h interval of pwm signal set by reload register r4h is output. mi mi+1 mi+2 mi mi+1 mi+2 01 16 timer 4 count value (reload register) timer 4 underflow signal pwm signal machine cycle x in input (count source selected) system clock f(stck)=f(x in )/4 register w4 1 0 timer 4 count stop timing timer 4 count value (reload register) timer 4 underflow signal pwm signal machine cycle x in input (count source selected) system clock f(stck)=f(x in )/4 register w4 1
rev.2.00 jul 27, 2004 page 44 of 159 rej03b0091-0200z 4524 group watchdog timer watchdog timer provides a method to reset the system when a pro- gram run-away occurs. watchdog timer consists of timer wdt(16-bit binary counter), watchdog timer enable flag (wef), and watchdog timer flags (wdf1, wdf2). the timer wdt downcounts the instruction clocks as the count source from ?fff 16 ?after system is released from reset. after the count is started, when the timer wdt underflow occurs (after the count value of timer wdt reaches ?000 16 ,?the next count pulse is input), the wdf1 flag is set to ?. if the wrst instruction is never executed until the timer wdt un- derflow occurs (until timer wdt counts 65534), wdf2 flag is set to ?,?and the reset pin outputs ??level to reset the microcomputer. execute the wrst instruction at each period of less than 65534 machine cycle by software when using watchdog timer to keep the microcomputer operating normally. when the wef flag is set to ??after system is released from reset, the watchdog timer function is valid. when the dwdt instruction and the wrst instruction are ex- ecuted continuously, the wef flag is cleared to ??and the watchdog timer function is invalid. the wef flag is set to "1" at system reset or ram back-up mode. the wrst instruction has the skip function. when the wrst in- struction is executed while the wdf1 flag is ?? the wdf1 flag is cleared to ??and the next instruction is skipped. when the wrst instruction is executed while the wdf1 flag is ?? the next instruction is not skipped. the skip function of the wrst instruction can be used even when the watchdog timer function is invalid. fig. 30 watchdog timer function 6 5 5 3 4 c o u n t ( n o t e ) v a l u e o f 1 6 - b i t t i m e r ( w d t ) w d f 1 f l a g ? w r s t i n s t r u c t i o n e x e c u t e d ( s k i p e x e c u t e d ) r e s e t p i n o u t p u t wdf2 flag ? system reset ? reset released ? a f t e r s y s t e m i s r e l e a s e d f r o m r e s e t ( = a f t e r p r o g r a m i s s t a r t e d ) , t i m e r w d t s t a r t s c o u n t d o w n . ? w h e n t i m e r w d t u n d e r f l o w o c c u r s , w d f 1 f l a g i s s e t t o 1 . ? w h e n t h e w r s t i n s t r u c t i o n i s e x e c u t e d , w d f 1 f l a g i s c l e a r e d t o 0 , t h e n e x t i n s t r u c t i o n i s s k i p p e d . ? w h e n t i m e r w d t u n d e r f l o w o c c u r s w h i l e w d f 1 f l a g i s 1 , w d f 2 f l a g i s s e t t o 1 a n d t h e w a t c h d o g r e s e t s i g n a l i s o u t p u t . ? t h e o u t p u t t r a n s i s t o r o f r e s e t p i n i s t u r n e d o n b y t h e w a t c h d o g r e s e t s i g n a l a n d s y s t e m r e s e t i s e x e c u t e d . n o t e : t h e n u m b e r o f c o u n t i s e q u a l t o t h e n u m b e r o f c y c l e b e c a u s e t h e c o u n t s o u r c e o f w a t c h d o g t i m e r i s t h e i n s t r u c t i o n c l o c k . f f f f 1 6 0 0 0 0 1 6 ? ? ?
rev.2.00 jul 27, 2004 page 45 of 159 rej03b0091-0200z 4524 group fig. 31 program example to start/stop watchdog timer fig. 32 program example to enter the mode when using the watchdog timer wrst ; wdf1 flag cleared nop di ; interrupt disabled epof ; pof instruction enabled pof oscillation stop when the watchdog timer is used, clear the wdf1 flag at a cycle of less than 65534 machine cycles with the wrst instruction. when the watchdog timer is not used, execute the dwdt instruc- tion and the wrst instruction continuously (refer to figure 31). the watchdog timer is not stopped with only the dwdt instruction. the contents of wdf1 flag and timer wdt are initialized at the power down mode. when using the watchdog timer and the power down mode, initial- ize the wdf1 flag with the wrst instruction just before the system enters the power down state (refer to figure 32). the watchdog timer function is valid after system is returned from the power down. when not using the watchdog timer function, stop the watchdog timer function with the dwdt instruction and the wrst instruction continuously every system is returned from the power down. wrst ; wdf1 flag cleared di dwdt ; wat chdog timer function enabled/disabled wrst ; wef and wdf1 flags cleared
rev.2.00 jul 27, 2004 page 46 of 159 rej03b0091-0200z 4524 group v s s v dd i a p 2 ( p 2 0 p 2 3 ) i a p 3 ( p 3 0 p 3 3 ) o p 2 a ( p 2 0 p 2 3 ) o p 3 a ( p 3 0 p 3 3 ) t a b a d 1/6 q1 3 q2 1 q 2 0 q 2 2 t a d a b q1 2 q1 1 q1 0 0 1 4 4 4 4 8 8 8 01 1 8 10 q1 3 q1 3 0 1 q1 3 8 8 2 t a l a q1 3 q 2 3 taq2 tq2a t a q 1 t q 1 a a d f ( 1 ) p 2 0 / a i n 0 p 3 0 / a i n 4 p 3 1 / a i n 5 p 3 2 / a i n 6 p 3 3 / a i n 7 3 1 0 10 p 2 1 / a i n 1 p2 2 /a in2 p 2 3 / a i n 3 4 4 q3 1 q3 0 q3 2 q3 3 t a q 3 t q 3 a 4 d a c o n v e r t e r ( n o t e 1 ) r e g i s t e r a ( 4 ) register b (4) dac operation signal c o m p a r a t o r 8 - c h a n n el m u l t i - p l e x e d an a l o g s w i t c h i n s t r u c t i o n c l o c k a/d control circuit successive comparison register (ad) (10) a/d interrupt c o m p a r a t o r r e g i s t e r ( 8 ) n o t e s 1 : t h i s s w i t c h i s t u r n e d o n o n l y w h e n a / d c o n v e r t e r i s o p e r a t i n g a n d g e n e r a t e s t h e c o m p a r i s o n v o l t a g e . 2 : w r i t i n g / r e a d i n g d a t a t o t h e c o m p a r a t o r r e g i s t e r i s p o s s i b l e o n l y i n t h e c o m p a r a t o r m o d e ( q 1 3 = 1 ) . t h e v a l u e o f t h e c o m p a r a t o r r e g i s t e r i s r e t a i n e d e v e n w h e n t h e m o d e i s s w i t c h e d t o t h e a / d c o n v e r s i o n m o d e ( q 1 3 = 0 ) b e c a u s e i t i s s e p a r a t e d f r o m t h e s u c c e s s i v e c o m p a r i s o n r e g i s t e r ( a d ) . a l s o , t h e r e s o l u t i o n i n t h e c o m p a r a t o r m o d e i s 8 b i t s b e c a u s e t h e c o m p a r a t o r r e g i s t e r c o n s i s t s o f 8 b i t s . ( n o t e 2 ) a/d converter (comparator) the 4524 group has a built-in a/d conversion circuit that performs conversion by 10-bit successive comparison method. table 11 shows the characteristics of this a/d converter. this a/d converter can also be used as an 8-bit comparator to compare analog volt- ages input from the analog input pin with preset values. table 11 a/d converter characteristics characteristics successive comparison method 10 bits linearity error: 2lsb differential non-linearity error: 0.9lsb 31 s (high-speed through-mode at 6.0 mhz oscillation frequency) 8 parameter conversion format resolution relative accuracy conversion speed analog input pin fig. 33 a/d conversion circuit structure
rev.2.00 jul 27, 2004 page 47 of 159 rej03b0091-0200z 4524 group table 12 a/d control registers q1 2 0 0 0 0 1 1 1 1 a/d operation mode selection bit analog input pin selection bits q1 1 0 0 1 1 0 0 1 1 a/d control register q1 at power down : state retained at reset : 0000 2 q1 3 a/d conversion mode comparator mode r/w taq1/tq1a q1 0 0 1 0 1 0 1 0 1 q1 2 q1 1 q1 0 analog input pins a in0 a in1 a in2 a in3 a in4 a in5 a in6 a in7 p2 3 a in3 p2 2 a in2 p2 1 a in1 p2 0 a in0 p2 3 /a in3 pin function selection bit p2 2 /a in2 pin function selection bit p2 1 /a in1 pin function selection bit p2 0 /a in0 pin function selection bit 0 1 0 1 0 1 0 1 q2 3 q2 2 q2 1 q2 0 r/w taq2/tq2a a/d control register q2 at power down : state retained at reset : 0000 2 p3 3 a in7 p3 2 a in6 p3 1 a in5 p3 0 a in4 p3 3 /a in7 pin function selection bit p3 2 /a in6 pin function selection bit p3 1 /a in5 pin function selection bit p3 0 /a in4 pin function selection bit 0 1 0 1 0 1 0 1 q3 3 q3 2 q3 1 q3 0 r/w taq3/tq3a a/d control register q3 at power down : state retained at reset : 0000 2 note: r represents read enabled, and w represents write enabled.
rev.2.00 jul 27, 2004 page 48 of 159 rej03b0091-0200z 4524 group (1) a/d control register a/d control register q1 register q1 controls the selection of a/d operation mode and the selection of analog input pins. set the contents of this register through register a with the tq1a instruction. the taq1 instruc- tion can be used to transfer the contents of register q1 to register a. a/d control register q2 register q2 controls the selection of p2 0 /a in0 p2 3 /a in3 . set the contents of this register through register a with the tq2a instruc- tion. the taq2 instruction can be used to transfer the contents of register q2 to register a. a/d control register q3 register q3 controls the selection of p3 0 /a in4 p3 3 /a in7 . set the contents of this register through register a with the tq3a instruc- tion. the taq3 instruction can be used to transfer the contents of register q3 to register a. (2) operating at a/d conversion mode the a/d conversion mode is set by setting the bit 3 of register q1 to 0. (3) successive comparison register ad register ad stores the a/d conversion result of an analog input in 10-bit digital data format. the contents of the high-order 8 bits of this register can be stored in register b and register a with the tabad instruction. the contents of the low-order 2 bits of this reg- ister can be stored into the high-order 2 bits of register a with the tala instruction. however, do not execute these instructions dur- ing a/d conversion. when the contents of register ad is n, the logic value of the com- parison voltage v ref generated from the built-in da converter can be obtained with the reference voltage v dd by the following for- mula: logic value of comparison voltage v ref v ref = ? 1 when a/d con- version completes. the state of adf flag can be examined with the skip instruction (snzad). use the interrupt control register v2 to select the interrupt or the skip instruction. the adf flag is cleared to 0 when the interrupt occurs or when the next instruction is skipped with the skip instruction. (5) a/d conversion start instruction (adst) a/d conversion starts when the adst instruction is executed. the conversion result is automatically stored in the register ad. (6) operation description a/d conversion is started with the a/d conversion start instruction (adst). the internal operation during a/d conversion is as follows: ? 000 16 . ? 1, and the com- parison voltage v ref is compared with the analog input voltage v in . ? 1. when the comparison result is v ref > v in , it is cleared to 0. the 4524 group repeats this operation to the lowermost bit of the register ad to convert an analog value to a digital value. a/d con- version stops after 62 machine cycles (31 1 as soon as a/d conversion completes (figure 34). table 13 change of successive comparison register ad during a/d conversion comparison voltage (v ref ) value change of successive comparison register ad at starting conversion ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ------------- ------------- ------------- ------------- ------------- ------------- ------------- -------------
rev.2.00 jul 27, 2004 page 49 of 159 rej03b0091-0200z 4524 group fig. 35 setting registers a/d control register q2 a in4 pin function selected ??? ? ? ? ? ? ? ? ? ?
rev.2.00 jul 27, 2004 page 50 of 159 rej03b0091-0200z 4524 group (9) operation at comparator mode the a/d converter is set to comparator mode by setting bit 3 of the register q1 to 1. below, the operation at comparator mode is described. (10) comparator register in comparator mode, the built-in da comparator is connected to the 8-bit comparator register as a register for setting comparison volt- ages. the contents of register b is stored in the high-order 4 bits of the comparator register and the contents of register a is stored in the low-order 4 bits of the comparator register with the tadab in- struction. when changing from a/d conversion mode to comparator mode, the result of a/d conversion (register ad) is undefined. however, because the comparator register is separated from regis- ter ad, the value is retained even when changing from comparator mode to a/d conversion mode. note that the comparator register can be written and read at only comparator mode. if the value in the comparator register is n, the logic value of com- parison voltage v ref generated by the built-in da converter can be determined from the following formula: (11) comparison result store flag (adf) in comparator mode, the adf flag, which shows completion of a/d conversion, stores the results of comparing the analog input volt- age with the comparison voltage. when the analog input voltage is lower than the comparison voltage, the adf flag is set to 1. the state of adf flag can be examined with the skip instruction (snzad). use the interrupt control register v2 to select the inter- rupt or the skip instruction. the adf flag is cleared to 0 when the interrupt occurs or when the next instruction is skipped with the skip instruction. (12) comparator operation start instruction (adst instruction) in comparator mode, executing adst starts the comparator oper- ating. the comparator stops 8 machine cycles after it has started (4 1. (13) notes for the use of a/d conversion tala instruction when the tala instruction is executed, the low-order 2 bits of register ad is transferred to the high-order 2 bits of register a, si- multaneously, the low-order 2 bits of register a is 0. operation mode of a/d converter do not change the operating mode (both a/d conversion mode and comparator mode) of a/d converter with the bit 3 of register q1 while the a/d converter is operating. clear the bit 2 of register v2 to 0 to change the operating mode of the a/d converter from the comparator mode to a/d conver- sion mode. the a/d conversion completion flag (adf) may be set when the operating mode of the a/d converter is changed from the com- parator mode to the a/d conversion mode. accordingly, set a value to the register q1, and execute the snzad instruction to clear the adf flag. logic value of comparison voltage v ref v ref = ?
rev.2.00 jul 27, 2004 page 51 of 159 rej03b0091-0200z 4524 group (14) definition of a/d converter accuracy the a/d conversion accuracy is defined below (refer to figure 37). relative accuracy ? 0 to 1. ? 1023 to 1022. ? ? absolute accuracy this means a deviation from the ideal characteristics between 0 to v dd of actual a/d conversion characteristics. fig. 37 definition of a/d conversion accuracy v fst v 0t 1022 v dd 1024 vn: analog input voltage when the output data changes from n to n+1 (n = 0 to 1022) 1lsb at relative accuracy 1lsb at absolute accuracy a a [ l s b ] actual a/d conversion characteristics a : 1 l s b b y r e l a t i v e a c c u r a c y b : v n + 1 v n c : d i f f e r e n c e b e t w e e n i d e a l v n a n d a c t u a l v n zero transition voltage (v 0t ) a n a l o g v o l t a g e full-scale transition voltage (v fst ) i d e a l l i n e o f a / d c o n v e r s i o n b e t w e e n v 0 v 1 0 2 2
rev.2.00 jul 27, 2004 page 52 of 159 rej03b0091-0200z 4524 group serial i/o the 4524 group has a built-in clock synchronous serial i/o which can serially transmit or receive 8-bit data. serial i/o consists of; serial i/o register si serial i/o control register j1 serial i/o transmit/receive completion flag (siof) serial i/o counter registers a and b are used to perform data transfer with internal cpu, and the serial i/o pins are used for external data transfer. the pin functions of the serial i/o pins can be set with the register j1. table 14 serial i/o pins pin d 6 /s ck d 5 /s out d 4 /s in pin function when selecting serial i/o clock i/o (s ck ) serial data output (s out ) serial data input (s in ) fig. 38 serial i/o structure table 15 serial i/o control register note: r represents read enabled, and w represents write enabled. j1 3 0 0 1 1 j1 1 0 0 1 1 serial i/o synchronous clock selection bits serial i/o port function selection bits j1 2 0 1 0 1 j1 0 0 1 0 1 serial i/o control register j1 at power down : state retained at reset : 0000 2 j1 3 j1 2 j1 1 j1 0 synchronous clock instruction clock (instck) divided by 8 instruction clock (instck) divided by 4 instruction clock (instck) divided by 2 external clock (s ck input) port function d 6 , d 5 , d 4 selected/s ck , s out , s in not selected s ck , s out , d 4 selected/d 6 , d 5 , s in not selected s ck , d 5 , s in selected/d 6 , s out , d 4 not selected s ck , s out , s in selected/d 6 , d 5 , d 4 not selected r/w taj1/tj1a 1/8 1/4 1/2 00 01 10 11 synchronous circuit serial i/o counter (3) siof serial i/o interrupt instck d 6 /s ck s ck qs r msb serial i/o register (8) lsb s in j1 1 j1 0 j1 3 j1 2 register b (4) register a (4) tsiab tabsi tabsi s out d 5 /s out d 4 /s in sst instruction internal reset signal note: even when the s ck , s out , s in pin functions are used, the input of d 6 , d 5 , d 4 are valid.
rev.2.00 jul 27, 2004 page 53 of 159 rej03b0091-0200z 4524 group fig. 39 serial i/o register state when transfer (1) serial i/o register si serial i/o register si is the 8-bit data transfer serial/parallel conver- sion register. data can be set to register si through registers a and b with the tsiab instruction. the contents of register a is transmit- ted to the low-order 4 bits of register si, and the contents of register b is transmitted to the high-order 4 bits of register si. during transmission, each bit data is transmitted lsb first from the lowermost bit (bit 0) of register si, and during reception, each bit data is received lsb first to register si starting from the topmost bit (bit 7). when register si is used as a work register without using serial i/o, do not select the s ck pin. (2) serial i/o transmit/receive completion flag (siof) serial i/o transmit/receive completion flag (siof) is set to 1 when serial data transmit or receive operation completes. the state of siof flag can be examined with the skip instruction (snzsi). use the interrupt control register v2 to select the interrupt or the skip instruction. the siof flag is cleared to 0 when the interrupt occurs or when the next instruction is skipped with the skip instruction. (3) serial i/o start instruction (sst) when the sst instruction is executed, the siof flag is cleared to 0 and then serial i/o transmission/reception is started. (4) serial i/o control register j1 register j1 controls the synchronous clock, d 6 /s ck , d 5 /s out and d 4 /s in pin function. set the contents of this register through regis- ter a with the tj1a instruction. the taj1 instruction can be used to transfer the contents of register j1 to register a. d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a t t r a n s m i t ( d 7 d 0 : t r a n s f e r d a t a )a t r e c e i v e d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s i n p i n s o u t p i n s o u t p i n s i n p i n s e r i a l i / o r e g i s t e r ( s i ) serial i/o register (si) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 * d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 7 d 6 d 5 d 4 d 3 d 2 d 0 d 1 d 0 transfer data set t r a n s f e r s t a r t transfer complete * * * ** ** ** * ******** ******** ** ** ** * ******
rev.2.00 jul 27, 2004 page 54 of 159 rej03b0091-0200z 4524 group (5) how to use serial i/o figure 40 shows the serial i/o connection example. serial i/o inter- rupt is not used in this example. in the actual wiring, pull up the wiring between each pin with a resistor. figure 40 shows the data transfer timing and table 16 shows the data transfer sequence. fig. 40 serial i/o connection example s out s rdy signal s ck s in d 3 s c k s o u t s i n d 3 m a s t e r ( c l o c k c o n t r o l ) serial i/o interrupt enable bit ( s n z s i i n s t r u c t i o n v a l i d ) interrupt control register v2 serial i/o control register j1 serial i/o port s ck, s out, s in instruction clock/8 selected as synchronous clock slave (external clock) serial i/o interrupt enable bit ( s n z s i i n s t r u c t i o n v a l i d ) ? ? ? ? ?? ?
rev.2.00 jul 27, 2004 page 55 of 159 rej03b0091-0200z 4524 group fig. 41 timing of serial i/o data transfer m 0 m 7 : c o n t e n t s o f m a s t e r s e r i a l i / o r e g i s t e r s 0 s 7 : c o n t e n t s o f s l a v e s e r i a l i / o r e g i s t e r r i s i n g o f s c k : s e r i a l i n p u t f a l l i n g o f s c k : s e r i a l o u t p u t s i n s out m a s t e r s l a v e s ck s s t i n s t r u c t i o n s o u t s i n s 0 s 7 s 1 s 2 s 3 s 4 s 5 s 6 s 7 s s t i n s t r u c t i o n s r d y s i g n a l s 0 s 7 s 1 s 3 s 4 s 5 s 6 s 7 m 0 m 7 m 1 m 2 m 3 m 4 m 5 m 6 m 7 m 0 m 7 m 1 m 2 m 3 m 4 m 5 m 6 m 7 s 2
rev.2.00 jul 27, 2004 page 56 of 159 rej03b0091-0200z 4524 group table 16 processing sequence of data transfer from master to slave 1-byte data is serially transferred on this process. subsequently, data can be transferred continuously by repeating the process from *. when an external clock is selected as a synchronous clock, the clock is not controlled internally. control the clock externally be- cause serial transmit/receive is performed as long as clock is externally input. (unlike an internal clock, an external clock is not stopped when serial transfer is completed.) however, the siof flag is set to 1 when the clock is counted 8 times after executing the sst instruction. be sure to set the initial level of the external clock to h. master (transmission) [initial setting] setting the serial i/o mode register j1 and inter- rupt control register v2 shown in figure 40. tj1a and tv2a instructions setting the port received the reception enable signal (s rdy ) to the input mode. (port d 3 is used in this example) sd instruction * [transmission enable state] storing transmission data to serial i/o register si. tsiab instruction [transmission] check port d 3 is l level. szd instruction serial transfer starts. sst instruction check transmission completes. snzsi instruction wait (timing when continuously transferring) slave (reception) [initial setting] setting serial i/o mode register j1, and interrupt control register v2 shown in figure 40. tj1a and tv2a instructions setting the port transmitted the reception enable signal (s rdy ) and outputting h level (reception impossible). (port d 3 is used in this example) sd instruction *[reception enable state] the siof flag is cleared to 0. sst instruction l level (reception possible) is output from port d 3 . rd instruction [reception] check reception completes. snzsi instruction h level is output from port d 3 . sd instruction [data processing]
rev.2.00 jul 27, 2004 page 57 of 159 rej03b0091-0200z 4524 group lcd function the 4524 group has an lcd (liquid crystal display) controller/ driver. when the proper voltage is applied to lcd power supply in- put pins (v lc1 v lc3 ) and data are set in timer control register (w6), timer lc, lcd control registers (l1, l2), and lcd ram, the lcd controller/driver automatically reads the display data and con- trols the lcd display by setting duty and bias. 4 common signal output pins and 20 segment signal output pins can be used to drive the lcd. by using these pins, up to 80 seg- ments (when 1/4 duty and 1/3 bias are selected) can be controlled to display. the lcd power input pins (v lc1 v lc3 ) are also used as pins seg 0 seg 2 . when seg 0 seg 2 . the internal power (v dd ) is used for the lcd power. (1) duty and bias there are 3 combinations of duty and bias for displaying data on the lcd. use bits 0 and 1 of lcd control register (l1) to select the proper display method for the lcd panel being used. 1/2 duty, 1/2 bias 1/3 duty, 1/3 bias 1/4 duty, 1/3 bias table 17 duty and maximum number of displayed pixels (2) lcd clock control the lcd clock is determined by the timer lc count source selec- tion bit (w6 2 ), timer lc control bit (w6 3 ), and timer lc. accordingly, the lcd clock frequency (f) is obtained by the follow- ing formula. numbers ( ? ? when using the prescaler output (orclk) as timer lc count source (w6 2 = 1 ) f = orclk ?? when using the bit 4 of timer 5 as timer lc count source (w6 2 = 0 ) f = t5 4 ?? com 2 (note) com 0 com 3 maximum number of displayed pixels 40 segments 60 segments 80 segments note: leave unused com pins open. 1 lc + 1 1 2 ?? ? ?? ? 0 to this bit. timer lc 1/2 w6 3 0 1 (note) t5 4 w6 2 0 1 orclk lcd clock (4) reload register rlc (4) register a (tlca) (tlca) ? ? ?
rev.2.00 jul 27, 2004 page 58 of 159 rej03b0091-0200z 4524 group fig. 43 lcd controller/driver c o m m o n d r i v e r bias control multiplexer selector ram segment driver selector ram c o m 3 c o m 2 c o m 1 c o m 0 d e c o d e r s e g 1 9 1 / 2 , 1 / 3 , 1 / 4 c o u n t e r lcd clock (from timer block) l1 0 l1 1 l1 2 l1 3 r e g i s t e r a lcd on/off control control signal v l c 3 / s e g 0 s e g 3 . . . . . . . . . ... .. . segment driver . . . v lc2 / seg 1 v lc1 /seg 2 s e g 0 t o s e g 2 o u t p u t l2 0 l2 1 l2 2 l2 3 r r r r r r t o
rev.2.00 jul 27, 2004 page 59 of 159 rej03b0091-0200z 4524 group (3) lcd ram ram contains areas corresponding to the liquid crystal display. when 1 is written to this lcd ram, the display pixel correspond- ing to the bit is automatically displayed. (4) lcd drive waveform when 1 is written to a bit in the lcd ram data, the voltage differ- ence between common pin and segment pin which correspond to the bit automatically becomes lv lc3 l and the display pixel at the cross section turns on. when returning from reset, and in the ram back-up mode, a dis- play pixel turns off because every segment output pin and common output pin becomes v lc3 level. fig. 44 lcd ram map table 18 lcd control registers z x y b i t s 8 9 1 0 1 1 1 2 1 3 14 15 com 1 14 321032103210 s e g 1 s e g 2 s e g 3 s e g 4 s e g 5 seg 6 seg 7 c o m 3 s e g 1 s e g 2 s e g 3 s e g 4 s e g 5 seg 6 seg 7 c o m 2 s e g 1 s e g 2 s e g 3 s e g 4 s e g 5 seg 6 seg 7 com 1 seg 1 seg 2 seg 3 seg 4 seg 5 seg 6 seg 7 com 0 s e g 9 seg 10 seg 11 seg 12 seg 13 seg 14 seg 15 com 3 c o m 2 com 1 com 0 com 3 com 2 com 1 com 0 s e g 9 seg 10 seg 11 seg 12 seg 13 seg 14 seg 15 seg 9 s e g 1 0 s e g 1 1 s e g 1 2 s e g 1 3 seg 14 seg 15 s e g 0 s e g 0 s e g 0 seg 0 s e g 8 s e g 1 7 s e g 1 8 s e g 1 9 s e g 1 6 s e g 8 seg 8 seg 8 seg 9 s e g 1 0 s e g 1 1 s e g 1 2 s e g 1 3 seg 14 seg 15 seg 17 seg 18 seg 19 seg 16 s e g 1 7 s e g 1 8 s e g 1 9 s e g 1 6 s e g 1 7 s e g 1 8 s e g 1 9 s e g 1 6 1 2 13 note: the area marked is not the lcd display ram. internal dividing resistor for lcd power supply selection bit (note 2) lcd control bit lcd control register l1 l1 3 l1 2 l1 1 l1 0 at reset : 0000 2 at power down : state retained 0 1 0 1 l1 1 0 0 1 1 l1 0 0 1 0 1 duty 1/2 1/3 1/4 bias 1/2 1/3 1/3 lcd control register l2 at reset : 1111 2 at power down : state retained w tl2a 0 1 0 1 0 1 0 1 seg 0 v lc3 seg 1 v lc2 seg 2 v lc1 internal dividing resistor valid internal dividing resistor invalid l2 3 l2 2 l2 1 l2 0 v lc3 /seg 0 pin function switch bit (note 3) v lc2 /seg 1 pin function switch bit (note 4) v lc1 /seg 2 pin function switch bit (note 4) internal dividing resistor for lcd power supply control bit 2r ? ? ? ? r represents read enabled, and w represents write enabled. 2: r (resistor) multiplied by 3 is used at 1/3 bias, and r multiplied by 2 is used at 1/2 bias. 3: v lc3 is connected to v dd internally when seg 0 pin is selected. 4: use internal dividing resistor when seg 1 and seg 2 pins are selected. r/w tal1/tl1a lcd duty and bias selection bits
rev.2.00 jul 27, 2004 page 60 of 159 rej03b0091-0200z 4524 group fig. 45 lcd controller/driver structure c o m 1 c o m 0 s e g 1 6 v l c 3 v l c 1 = v l c 2 v s s v l c 3 v l c 1 = v l c 2 v s s 1 flame (2/f) 1/f o n o f f v o l t a g e l e v e l ( b i t 0 ) c o m 0 c o m 1 s e g 1 6 0 1 x x ( b i t 3 ) m ( 1 , 1 4 , 8 ) com 1 seg 16 c o m 0 s e g 1 6 1 flame (3/f) 1/f on off on com 2 v l c 3 v l c 2 v lc 1 v s s c o m 1 com 0 s e g 1 6 v lc 3 v lc 2 v l c 1 v ss v o l t a g e l e v e l (bit 0) com 0 c o m 1 c o m 2 s e g 1 6 1 0 1 x ( b i t 3 ) m ( 1 , 1 4 , 8 ) com 2 seg 16 com 1 seg 16 com 0 seg 16 1 f l a m e ( 4 / f ) 1 / f o no f f c o m 3 c o m 2 c o m 1 com 0 s e g 1 6 v lc 3 v lc 2 v lc 1 v ss v lc 3 v lc 2 v lc 1 v ss v o l tage l eve l (bit 0) c o m 0 com 1 c o m 2 com 3 seg 16 0 1 0 1 (bit 3) m ( 1 , 1 4 , 8 ) com 3 s e g 1 6 com 2 seg 16 com 1 seg 16 com 0 seg 16 f : l c d c l o c k f r e q u e n c y x: s e t a n a r b i t r a r y v a l u e . ( t h e s e b i t s a r e n o t r e l a t e d t o se t t h e d r i v e w a v e f o r m a t e a c h d u t y . ) o noff 1 / 2 d u t y , 1 / 2 b i a s : w h e n w r i t i n g ( x x 1 0 ) 2 t o a d d r e s s m ( 1 , 1 4 , 8 ) i n r a m . 1/3 duty, 1/3 bias: when writing (x101) 2 to address m (1, 14, 8) in ram. 1/4 duty, 1/3 bias: when writing (1010) 2 to address m (1, 14, 8) in ram.
rev.2.00 jul 27, 2004 page 61 of 159 rej03b0091-0200z 4524 group (5) lcd power supply circuit select the lcd power circuit suitable for the lcd panel. the lcd control circuit structure is fixed by the following setting. ? set the control of internal dividing resistor by bit 0 of register l2. ? select the internal dividing resistor by bit 3 of register l1. ? select the bias condition by bits 0 and 1 of register l1. internal dividing resistor the 4524 group has the internal dividing resistor for lcd power supply. when bit 0 of register l2 is set to ?? the internal dividing resis- tor is valid. however, when the lcd is turned off by setting bit 2 of register l1 to ?? the internal dividing resistor is turned off. the same six resistor (r) is prepared for the internal dividing re- sistor. according to the setting value of bit 3 of register l1 and using bias condition, the resistor is prepared as follows; ?l1 3 = ?? 1/3 bias used: 2r ? 3 = 6r ?l1 3 = ?? 1/2 bias used: 2r ? 2 = 4r ?l1 3 = ?? 1/3 bias used: r ? 3 = 3r ?l1 3 = ?? 1/2 bias used: r ? 2 = 2r ? lc3 /seg 0 pin the selection of v lc3 /seg 0 pin function is controlled with the bit 3 of register l2. when the v lc3 pin function is selected, apply voltage of v lc3 < v dd to the pin externally. when the seg 0 pin function is selected, v lc3 is connected to v dd internally. ?v lc2 /seg 1 , v lc1 /seg 2 pin the selection of v lc2 /seg 1 pin function is controlled with the bit 2 of register l2. the selection of v lc1 /seg 2 pin function is controlled with the bit 1 of register l2. when the v lc2 pin and v lc1 pin functions are selected and the in- ternal dividing resistor is not used, apply voltage of 0 rev.2.00 jul 27, 2004 page 62 of 159 rej03b0091-0200z 4524 group reset function system reset is performed by applying l level to reset pin for 1 machine cycle or more when the following condition is satisfied; the value of supply voltage is the minimum value or more of the recommended operating conditions. then when h level is applied to reset pin, program starts from address 0 in page 0. fig. 47 reset release timing fig. 48 reset pin input waveform and reset operation f(x in ) r e s e t program starts (address 0 in page 0 ) on-chip oscillator (internal oscillator) is counted 5400 to 5424 times. n o t e : t h e n u m b e r o f c l o c k c y c l e s d e p e n d s o n t h e i n t e r n a l s t a t e o f t h e m i c r o c o m p u t e r w h e n r e s e t i s p e r f o r m e d . r e s e t 0 . 3 v d d 0.85v dd ( n o t e ) n o t e : k e e p t h e v a l u e o f s u p p l y v o l t a g e t o t h e m i n i m u m v a l u e o r m o r e o f t h e r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s . reset input 1 machine cycle or more = program starts (address 0 in page 0) o n - c h i p o s c i l l a t o r ( i n t e r n a l o s c i l l a t o r ) i s c o u n t e d 5 4 0 0 t o 5 4 2 4 t i m e s .
rev.2.00 jul 27, 2004 page 63 of 159 rej03b0091-0200z 4524 group fig. 49 structure of reset pin and its peripherals,, and power-on reset operation name d 0 ? 3 d 4 /s in , d 5 /s out , d 6 /s ck d 7 /cntr0 d 8 /int0, d 9 /int1 p0 0 ?0 3 p1 0 ?1 3 p2 0 /a in0 ?2 3 /a in3 p3 0 /a in4 ?3 3 /a in7 p4 0 ?4 3 c/cntr1 notes 1: output latch is set to ?. 2: output structure is n-channel open-drain. 3: pull-up transistor is turned off. function d 0 ? 3 d 4 ? 6 d 7 d 8 , d 9 p0 0 ?0 3 p1 0 ?1 3 p2 0 ?2 3 p3 0 ?3 3 p4 0 ?4 3 c state high-impedance (notes 1, 2) high-impedance (notes 1, 2) high-impedance (notes 1, 2) high-impedance (note 1) high-impedance (notes 1, 2, 3) high-impedance (notes 1, 2, 3) high-impedance (note 1) high-impedance (note 1) high-impedance (notes 1, 2) ??(v ss ) level (1) power-on reset reset can be automatically performed at power on (power-on re- set) by the built-in power-on reset circuit. when the built-in power-on reset circuit is used, the time for the supply voltage to rise from 0 v must be set to 100 s or less. if the rising time ex- ceeds 100 s, connect a capacitor between the reset pin and v ss at the shortest distance, and input ??level to reset pin until the value of supply voltage reaches the minimum operating volt- age. table 19 port state at reset r e s e t p i n w e f watchdog reset signal ( n o t e 1 ) p u l l - u p t r a n s i s t o r ( n o t e 1 ) p o w e r - o n r e s e t c i r c u i t voltage drop detection circuit v dd (note 3) 1 0 0 s o r l e s s ( n o t e 2 ) i n t e r n a l r e s e t s i g n a l p o w e r - o n reset released internal reset signal r e s e t s t a t e notes 1: t h i s s y m b o l r e p r e s e n t s a p a r a s i t i c d i o d e . 2: applied potential to reset pin must be v dd or less. 3: keep the value of supply voltage to the minimum value or more of the recommended operating conditions. p o w e r - o n r e s e t c i r c u i t o u t p u t
rev.2.00 jul 27, 2004 page 64 of 159 rej03b0091-0200z 4524 group program counter (pc) .......................................................................................................... address 0 in page 0 is set to program counter. interrupt enable flag (inte) .................................................................................................. power down flag (p) ........................................................................................................... .. external 0 interrupt request flag (exf0) .............................................................................. external 1 interrupt request flag (exf1) .............................................................................. interrupt control register v1 ................................................................................................. . interrupt control register v2 ................................................................................................. . interrupt control register i1 ................................................................................................. .. interrupt control register i2 ................................................................................................. .. interrupt control register i3 ................................................................................................. .. timer 1 interrupt request flag (t1f) ..................................................................................... timer 2 interrupt request flag (t2f) ..................................................................................... timer 3 interrupt request flag (t3f) ..................................................................................... timer 4 interrupt request flag (t4f) ..................................................................................... timer 5 interrupt request flag (t5f) ..................................................................................... watchdog timer flags (wdf1, wdf2) .................................................................................. watchdog timer enable flag (wef) ...................................................................................... timer control register pa ..................................................................................................... . timer control register w1 ..................................................................................................... timer control register w2 ..................................................................................................... timer control register w3 ..................................................................................................... timer control register w4 ..................................................................................................... timer control register w5 ..................................................................................................... timer control register w6 ..................................................................................................... clock control register mr ..................................................................................................... serial i/o transmit/receive complation flag (siof) .............................................................. serial i/o mode register j1 .................................................................................................. serial i/o register si ........................................................................................................ ..... a/d conversion completion flag (adf) ................................................................................. a/d control register q1 ....................................................................................................... .. a/d control register q2 ....................................................................................................... .. a/d control register q3 ....................................................................................................... .. successive approximation register ad ................................................................................ comparator register ........................................................................................................... ... lcd control register l1 ....................................................................................................... . lcd control register l2 ....................................................................................................... . ? represents undefined. fig. 50 internal state at reset (2) internal state at reset figure 50 and 51 show internal state at reset (they are the same af- ter system is released from reset). the contents of timers, registers, flags and ram except shown in figure 50 are undefined, so set the initial value to them. 00000000000000 0 (interrupt disabled) 0 0 0 0 0 0 0 (interrupt disabled) 0 0 0 0 (interrupt disabled) 0000 0000 0 0 0 0 0 0 0 1 0 (prescaler stopped) 0 0 0 0 (timer 1 stopped) 0 0 0 0 (timer 2 stopped) 0 0 0 0 (timer 3 stopped) 0 0 0 0 (timer 4 stopped) 0 0 0 0 (timer 5 stopped) 0 0 0 0 (timer lc stopped) 1100 0 0 0 0 0 (external clock selected, serial i/o port not selected) ?????? ?????? ?????? ?? ? ??? ??
rev.2.00 jul 27, 2004 page 65 of 159 rej03b0091-0200z 4524 group key-on wakeup control register k0 ...................................................................................... key-on wakeup control register k1 ...................................................................................... key-on wakeup control register k2 ...................................................................................... pull-up control register pu0 ................................................................................................. pull-up control register pu1 ................................................................................................. port output structure control register fr0 ........................................................................... port output structure control register fr1 ........................................................................... port output structure control register fr2 ........................................................................... port output structure control register fr3 ........................................................................... carry flag (cy) ............................................................................................................... ....... register a .................................................................................................................... ......... register b .................................................................................................................... ......... register d .................................................................................................................... ......... register e .................................................................................................................... ......... register x .................................................................................................................... ......... register y .................................................................................................................... ......... register z .................................................................................................................... ......... stack pointer (sp) ............................................................................................................ .... operation source clock .......................................................... on-chip oscillator (operating) ceramic resonator circuit ..................................................................................... operating rc oscillation circuit ...................................................................................................... stop quartz-crystal oscillator ........................................................................................ operating ? represents undefined. fig. 51 internal state at reset 0000 0000 0000 0000 0000 0000 0000 0000 0000 0 0000 0000 ??? ?????? ?? ??
rev.2.00 jul 27, 2004 page 66 of 159 rej03b0091-0200z 4524 group voltage drop detection circuit the built-in voltage drop detection circuit is designed to detect a drop in voltage and to reset the microcomputer if the supply voltage drops below a set value. fig. 52 voltage drop detection reset circuit fig. 53 voltage drop detection circuit operation waveform e p o f i n s t r u c t i o n + p o f i n s t r u c t i o n e p o f i n s t r u c t i o n + p o f 2 i n s t r u c t i o n q s r s v d e i n s t r u c t i o n i n t e r n a l r e s e t s i g n a l voltage drop detection circuit reset signal v r s t v o l t a g e d r o p d e t e c t i o n c i r c u i t v d c e i n t e r n a l r e s e t s i g n a l t 5 f f l a g k e y - o n w a k e u p s i g n a l q s r + v dd v o l t a g e d r o p d e t e c t i o n c i r c u i t r e s e t s i g n a l microcomupter starts operation after on-chip oscillator (internal oscillator) clock is counted 5400 to 5424 times. v rst (detection voltage) r e s e t p i n note: detection voltage of voltage drop detection circuit does not have hysteresis. the voltage drop detection circuit is valid when cpu is active while the vdce pin is h . even after system goes into the power down mode, the voltage drop detection circuit is also valid with the svde instruction. execution of svde instruction is valid only at once. in order to release the execution of the svde instruction, system reset is not required. table 20 voltage drop detection circuit operation state vdce pin l h at cpu operating invalid valid at power down (svde instruction is not executed) invalid invalid at power down (svde instruction is executed) invalid valid
rev.2.00 jul 27, 2004 page 67 of 159 rej03b0091-0200z 4524 group table 21 functions and states retained at power down function program counter (pc), registers a, b, carry flag (cy), stack pointer (sp) (note 2) contents of ram interrupt control registers v1, v2 interrupt control registers i1 to i3 selected oscillation circuit clock control register mr timer 1 to timer 4 functions timer 5 function timer lc function watchdog timer function timer control registers pa, w4 timer control registers w1 to w3, w5, w6 serial i/o function serial i/o control register j1 a/d function a/d control registers q1 to q3 lcd display function lcd control registers l1, l2 voltage drop detection circuit port level pull-up control registers pu0, pu1 key-on wakeup control registers k0 to k2 port output format control registers fr0 to fr3 external interrupt request flags (exf0, exf1) timer interrupt request flags (t1f to t4f) timer interrupt request flag (t5f) a/d conversion completion flag (adf) serial i/o transmit/receive completion flag siof interrupt enable flag (inte) watchdog timer flags (wdf1, wdf2) watchdog timer enable flag (wef) ? ? ? ? ? ? ? ? ? ? ? ? o represents that the function can be retained, and ? repre- sents that the function is initialized. registers and flags other than the above are undefined at power down, and set an initial value after returning. 2: the stack pointer (sp) points the level of the stack register and is initialized to 7 at power down. 3: the state of the timer is undefined. 4: initialize the watchdog timer with the wrst instruction, and then go into the power down state. 5: lcd is turned off. 6: when the svde instruction is executed and h level is applied to the vdce pin, this function is valid at power down. 7: in the power down mode, c/cntr1 pin outputs l level. however, when the cntr input is selected (w1 1 , w1 0 = 11 ), c/ cntr1 pin is in an input enabled state (output=high-impedance). other ports retain their respective output levels. power down mode ? ? ? ? ? ? ? ? ? ? ? ? clock operating mode ...................... epof and pof instructions ram back-up mode ....................... epof and pof2 instructions when the epof instruction is not executed before the pof or pof2 instruction is executed, these instructions are equivalent to the nop instruction. (1) clock operating mode the following functions and states are retained. ram reset circuit x cin x cout oscillation lcd display timer 5 (2) ram back-up mode the following functions and states are retained. ram reset circuit (3) warm start condition the system returns from the power down state when; external wakeup signal is input timer 5 underflow occurs in the power down mode. in either case, the cpu starts executing the program from address 0 in page 0. in this case, the p flag is 1. (4) cold start condition the cpu starts executing the program from address 0 in page 0 when; reset pulse is input to reset pin, reset by watchdog timer is performed, or reset by the voltage drop detection circuit is performed. in this case, the p flag is 0. (5) identification of the start condition warm start or cold start can be identified by examining the state of the power down flag (p) with the snzp instruction. the warm start condition from the clock operating mode can be identified by exam- ining the state of t5f flag. clock operating ram back-up
rev.2.00 jul 27, 2004 page 68 of 159 rej03b0091-0200z 4524 group (6) return signal an external wakeup signal or timer 5 interrupt request flag (t5f) is used to return from the clock operating mode. an external wakeup signal is used to return from the ram back-up mode because the oscillation is stopped. table 22 shows the return condition for each return source. (7) control registers key-on wakeup control register k0 register k0 controls the port p0 key-on wakeup function. set the contents of this register through register a with the tk0a instruc- tion. in addition, the tak0 instruction can be used to transfer the contents of register k0 to register a. key-on wakeup control register k1 register k1 controls the port p1 key-on wakeup function. set the contents of this register through register a with the tk1a instruc- tion. in addition, the tak1 instruction can be used to transfer the contents of register k0 to register a. key-on wakeup control register k2 register k2 controls the int0 and int1 pin key-on wakeup func- tion. set the contents of this register through register a with the tk2a instruction. in addition, the tak2 instruction can be used to transfer the contents of register k2 to register a. table 22 return source and return condition remarks return condition external wakeup signal return source ports p0 0 p0 3 ports p1 0 p1 3 int0 pin int1 pin pull-up control register pu0 register pu0 controls the on/off of the port p0 pull-up transis- tor. set the contents of this register through register a with the tpu0a instruction. in addition, the tapu0 instruction can be used to transfer the contents of register pu0 to register a. pull-up control register pu1 register pu1 controls the on/off of the port p1 pull-up transis- tor. set the contents of this register through register a with the tpu1a instruction. in addition, the tapu1 instruction can be used to transfer the contents of register pu1 to register a. external interrupt control register i1 register i1 controls the valid waveform of the external 0 inter- rupt, the input control of int0 pin and the return input level. set the contents of this register through register a with the ti1a in- struction. in addition, the tai1 instruction can be used to transfer the contents of register i1 to register a. external interrupt control register i2 register i2 controls the valid waveform of the external 1 inter- rupt, the input control of int1 pin and the return input level. set the contents of this register through register a with the ti2a in- struction. in addition, the tai2 instruction can be used to transfer the contents of register i2 to register a. return by an external l level in- put. return by an external h level or l level input, or rising edge ( l h ) or falling edge ( h l ). when the return signal is input, the interrupt request flag (exf0, exf1) is not set to 1 . return by timer 5 underflow or by setting t5f to 1 . it can be used in the clock operat- ing mode. the key-on wakeup function can be selected by one port unit. set the port using the key-on wakeup function to h level before going into the power down state. select the return level ( l level or h level) with register i1 (i2) and return condition (return by level or edge) with register k2 according to the external state before going into the power down state. clear t5f with the snzt5 instruction before system enters into the power down state. when system enters into the power down state while t5f is 1 , system re- turns from the state immediately because it is recognized as return condition. timer 5 interrupt request flag (t5f)
rev.2.00 jul 27, 2004 page 69 of 159 rej03b0091-0200z 4524 group fig. 55 state transition fig. 56 set source and clear source of the p flag fig. 57 start condition identified example using the snzp instruction s r q power down flag p p o f o r p o f 2 i n s t r u c t i o n reset inpu t epof instruction + pof or pof2 instruction e p o f i n s t r u c t i o n + p r o g r a m s t a r t p = 1 ? yes w a r m s t a r t c o l d s t a r t no t 5 f = 1 ? yes n o return from timer 5 underflow r e t u r n f r o m e x t e r n a l w a k e u p s i g n a l reset b operation state operation source clock: f(x in ) oscillation circuit: ceramic resonator on-chip oscillator: stop rc oscillation circuit: stop a c e clock operating mode main clock: stop sub-clock: operating wakeup (stabilizing time c ) pof2 instruction execution f ram back-up mode pof2 instruction execution high-speed mode d operation clock: f(x cin ) oscillation circuit: quartz-crystal oscillation mr 0 operation source clock: f(ring) oscillation circuit: on-chip oscillator ceramic resonator: operating (note 2) rc oscillation circuit: stop crck instruction execution (note 3) operation state operation source clock: f(x in ) oscillation circuit: rc oscillation on-chip oscillator: stop ceramic resontor: stop operation state stabilizing time a : microcomputer starts its operation after counting the on-chip oscillator clock 5400 to 5424 times. stabilizing time b : in high-speed through-mode, microcomputer starts its operation after counting the f(ring) 675 times. in high-speed/2 mode, microcomputer starts its operation after counting the f(ring) 1350 times. in high-speed/4 mode, microcomputer starts its operation after counting the f(ring) 2700 times. in high-speed/8 mode, microcomputer starts its operation after counting the f(ring) 5400 times. stabilizing time c : in high-speed through-mode, microcomputer starts its operation after counting the f(x in ) 675 times. in high-speed/2 mode, microcomputer starts its operation after counting the f(x in ) 1350 times. in high-speed/4 mode, microcomputer starts its operation after counting the f(x in ) 2700 times. in high-speed/8 mode, microcomputer starts its operation after counting the f(x in ) 5400 times. stabilizing time d : in high-speed through-mode, microcomputer starts its operation after counting the f(x in ) 21 times. in high-speed/2 mode, microcomputer starts its operation after counting the f(x in ) 42 times. in high-speed/4 mode, microcomputer starts its operation after counting the f(x in ) 84 times. in high-speed/8 mode, microcomputer starts its operation after counting the f(x in ) 168 times. stabilizing time e : in low-speed through-mode, microcomputer starts its operation after counting the f(x cin ) 675 times. in low-speed/2 mode, microcomputer starts its operation after counting the f(x cin ) 1350 times. in low-speed/4 mode, microcomputer starts its operation after counting the f(x cin ) 2700 times. in low-speed/8 mode, microcomputer starts its operation after counting the f(x cin ) 5400 times. notes 1: continuous execution of the epof instruction and the pof instruction is required to go into the clock operating state. continuous execution of the epof instruction and the pof2 instruction is required to go into the ram back-up state. 2: through the ceramic resonator is operating, the on-chip oscillator clock is selected as the operation source clock. 3: the oscillator clock corresponding to each instruction is selected as the operation source clock, and the on-chip oscillator is stopped. 4: the main clock (f(x in ) or f(ring)) or sub-clock (f(x cin )) is selected for operation source clock by the bit 0 of clock control register mr. 5: the sub-clock (quartz-crystal oscillation) is operating except in state f. t5f t5f t5f t5f
rev.2.00 jul 27, 2004 page 70 of 159 rej03b0091-0200z 4524 group table 23 key-on wakeup control register, pull-up control register and interrupt control register k0 3 k0 2 k0 1 k0 0 key-on wakeup control register k0 key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used port p0 3 key-on wakeup control bit port p0 2 key-on wakeup control bit port p0 1 key-on wakeup control bit port p0 0 key-on wakeup control bit at reset : 0000 2 at power down : state retained 0 1 0 1 0 1 0 1 note: r represents read enabled, and w represents write enabled. k1 3 k1 2 k1 1 k1 0 key-on wakeup control register k1 key-on wakeup used key-on wakeup not used key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used port p1 3 key-on wakeup control bit port p1 2 key-on wakeup control bit port p1 1 key-on wakeup control bit port p1 0 key-on wakeup control bit at reset : 0000 2 at power down : state retained 0 1 0 1 0 1 0 1 k2 3 k2 2 k2 1 k2 0 key-on wakeup control register k2 return by level return by edge key-on wakeup not used key-on wakeup used return by level return by edge key-on wakeup not used key-on wakeup used int1 pin return condition selection bit int1 pin key-on wakeup control bit int0 pin return condition selection bit int0 pin key-on wakeup control bit at reset : 0000 2 at power down : state retained 0 1 0 1 0 1 0 1 r/w tak0/ tk0a r/w tak1/ tk1a r/w tak2/ tk2a
rev.2.00 jul 27, 2004 page 71 of 159 rej03b0091-0200z 4524 group pu0 3 pu0 2 pu0 1 pu0 0 pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on port p0 3 pull-up transistor control bit port p0 2 pull-up transistor control bit port p0 1 pull-up transistor control bit port p0 0 pull-up transistor control bit pull-up control register pu0 at reset : 0000 2 at power down : state retained 0 1 0 1 0 1 0 1 pu1 3 pu1 2 pu1 1 pu1 0 pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on port p1 3 pull-up transistor control bit port p1 2 pull-up transistor control bit port p1 1 pull-up transistor control bit port p1 0 pull-up transistor control bit pull-up control register pu1 at reset : 0000 2 at power down : state retained 0 1 0 1 0 1 0 1 i1 3 i1 2 i1 1 i1 0 int0 pin input control bit (note 2) interrupt valid waveform for int0 pin/ return level selection bit (note 2) int0 pin edge detection circuit control bit int0 pin timer 1 count start synchronous circuit selection bit interrupt control register i1 r/w tai1/ti1a at power down : state retained at reset : 0000 2 int0 pin input disabled int0 pin input enabled falling waveform/ l level ( l level is recognized with the snzi0 instruction) rising waveform/ h level ( h level is recognized with the snzi0 instruction) one-sided edge detected both edges detected timer 1 count start synchronous circuit not selected timer 1 count start synchronous circuit selected 0 1 0 1 0 1 0 1 i2 3 i2 2 i2 1 i2 0 int1 pin input control bit (note 2) interrupt valid waveform for int1 pin/ return level selection bit (note 2) int1 pin edge detection circuit control bit int1 pin timer 3 count start synchronous circuit selection bit interrupt control register i2 r/w tai2/ti2a at power down : state retained at reset : 0000 2 int1 pin input disabled int1 pin input enabled falling waveform/ l level ( l level is recognized with the snzi1 instruction) rising waveform/ h level ( h level is recognized with the snzi1 instruction) one-sided edge detected both edges detected timer 3 count start synchronous circuit not selected timer 3 count start synchronous circuit selected 0 1 0 1 0 1 0 1 notes 1: r represents read enabled, and w represents write enabled. 2: when the contents of i1 2 , i1 3 i2 2 and i2 3 are changed, the external interrupt request flag (exf0, exf1) may be set. r/w tapu0/ tpu0a r/w tapu1/ tpu1a
rev.2.00 jul 27, 2004 page 72 of 159 rej03b0091-0200z 4524 group clock control the clock control circuit consists of the following circuits. on-chip oscillator (internal oscillator) ceramic resonator rc oscillation circuit quartz-crystal oscillation circuit multi-plexer (clock selection circuit) frequency divider internal clock generating circuit fig. 58 clock control circuit structure the system clock and the instruction clock are generated as the source clock for operation by these circuits. figure 58 shows the structure of the clock control circuit. the 4524 group operates by the on-chip oscillator clock (f(ring)) which is the internal oscillator after system is released from reset. also, the ceramic resonator or the rc oscillation can be used for the main clock (f(x in )) of the 4524 group. the cmck instruction or crck instruction is executed to select the ceramic resonator or rc oscillator, respectively. the quartz-crystal oscillator can be used for sub-clock (f(x cin )). mr 3, mr 2 00 01 10 11 qs qr qs r crck instruction qs r cmck instruction qs r internal reset signal x out x in wait time control circuit (note 2) program start signal key-on wakeup signal notes 1: system operates by the on-chip oscillator clock (f(ring)) until the cmck or crck instruction is executed after system is released from reset. 2: the wait time control circuit is used to generate the time required to stabilize the f(x in ) or f(x cin ) oscillation. after the certain oscillation stabilizing wait time elapses, the program start signal is output. this circuit operates when system is released from reset or returned from power down. epof instruction pof2 instruction + x cout x cin qs r epof instruction pof instruction + t5f flag mr 1 1 mr 0 0 system clock (stck) instruction clock (instck) multi-plexer quartz-crystal oscillation circuit on-chip oscillator (internal oscillator) (note 1) ceramic oscillation circuit rc oscillation circuit internal clock generating circuit (divided by 3) divided by 2 divided by 4 divided by 8 division circuit
rev.2.00 jul 27, 2004 page 73 of 159 rej03b0091-0200z 4524 group fig. 59 switch to ceramic oscillation/rc oscillation fig. 60 handling of x in and x out when operating on-chip oscillator fig. 61 ceramic resonator external circuit fig. 62 external rc oscillation circuit execute the cmck instruc- tion in program. note: externally connect a damping resistor rd depending on the oscillation frequency. (a feedback resistor is built-in.) use the resonator manu- facturer s recommended value because constants such as ca- pacitance depend on the resonator. (1) main clock generating circuit (f(x in )) the ceramic resonator or rc oscillation can be used for the main clock of this mcu. after system is released from reset, the mcu starts operation by the clock output from the on-chip oscillator which is the internal os- cillator. when the ceramic resonator is used, execute the cmck instruc- tion. when the rc oscillation is used, execute the crck instruction. the oscillation circuit by the cmck or crck instruction is valid only at once. the oscillation circuit corresponding to the first executed one of these two instructions is valid. other oscillation cir- cuit and the on-chip oscillator stop. execute the cmck or the crck instruction in the initial setting routine of program (executing it in address 0 in page 0 is recommended). also, when the cmck or the crck instruction is not executed in pro- gram, this mcu operates by the on-chip oscillator. (2) on-chip oscillator operation when the mcu operates by the on-chip oscillator as the main clock (f(x in )) without using the ceramic resonator or the rc oscillation, connect x in pin to v ss and leave x out pin open (figure 60). the clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. be careful that margin of frequencies when designing application products. (3) ceramic resonator when the ceramic resonator is used as the main clock (f(x in )), con- nect the ceramic resonator and the external circuit to pins x in and x out at the shortest distance. then, execute the cmck instruction. a feedback resistor is built in between pins x in and x out (figure 61). (4) rc oscillation when the rc oscillation is used as the main clock (f(x in )), connect the x in pin to the external circuit of resistor r and the capacitor c at the shortest distance and leave x out pin open. then, execute the crck instruction (figure 62). the frequency is affected by a capacitor, a resistor and a micro- computer. so, set the constants within the range of the frequency limits. * reset on-chip oscillator operation c m c k i n s t r u c t i o n crck instruction ceramic resonator valid on-chip oscillator stop rc oscillation stop r c o s c i l l a t i o n v a l i d o n - c h i p o s c i l l a t o r s t o p c e r a m i c r e s o n a t o r s t o p m34524 x i n x o u t * do not use the cmck instruction and crck instruction in program. m34524 x in x out rd c i n c o u t m 3 4 5 2 4 x i n x o u t r c * e x e c u t e t h e c r c k i n s t r u c t i o n i n p r o g r a m .
rev.2.00 jul 27, 2004 page 74 of 159 rej03b0091-0200z 4524 group (5) external clock when the external clock signal is used as the main clock (f(x in )), connect the x in pin to the clock source and leave x out pin open. then, execute the cmck instruction (figure 63). be careful that the maximum value of the oscillation frequency when using the external clock differs from the value when using the ceramic resonator (refer to the recommended operating condition). also, note that the power down function (pof or pof2 instruction) cannot be used when using the external clock. (6) sub-clock generating circuit f(x cin ) the quartz-crystal oscillator can be used for the sub-clock signal f(x cin ). connect a quartz-crystal oscillator and this external circuit to pins x cin and x cout at the shortest distance. a feedback resis- tor is built in between pins x cin and x cout (figure 64). (7) clock control register mr register mr controls system clock. set the contents of this register through register a with the tmra instruction. in addition, the tamr instruction can be used to transfer the contents of register mr to register a. table 24 clock control register mr fig. 63 external clock input circuit note : r represents read enabled, and w represents write enabled. m 3 4 5 2 4 x in x o u t e x t e r n a l o s c i l l a t i o n c i r c u i t v d d v s s e x e c u t e t h e c m c k i n s t r u c t i o n i n p r o g r a m . * fig. 64 external quartz-crystal circuit m 3 4 5 2 4 x c in x c ou t rd c i n c o u t mr 3 clock control register mr operation mode through mode (frequency not divided) frequency divided by 2 mode frequency divided by 4 mode frequency divided by 8 mode main clock oscillation enabled main clock oscillation stop main clock (f(x in ) or f(ring)) sub-clock (f(x cin )) at reset : 1100 2 at power down : state retained mr 3 0 0 1 1 r/w tamr/ tmra main clock oscillation circuit control bit system clock selection bit operation mode selection bits 0 1 0 1 mr 2 0 1 0 1 mr 1 mr 0 mr 2 rom ordering method 1.mask rom order confirmation form ? ? ? renesas technology corp. homepage (http://www.renesas.com/en/rom). note: externally connect a damping resistor rd depending on the oscillation frequency. (a feedback resistor is built-in.) use the quartz-crystal manu- facturer s recommended value because constants such as ca- pacitance depend on the resonator.
rev.2.00 jul 27, 2004 page 75 of 159 rej03b0091-0200z 4524 group ? h interval extension function of the pwm signal is set to be valid , set 1 or more to reload register r4h. timer 5 stop timer 5 counting to change its count source. timer input/output pin set the port c output latch to 0 to output the pwm signal from c/cntr pin. watchdog timer the watchdog timer function is valid after system is released from reset. when not using the watchdog timer function, stop the watchdog timer function and execute the dwdt instruction, the wrst instruction continuously, and clear the wef flag to 0 . the watchdog timer function is valid after system is returned from the power down state. when not using the watchdog timer func- tion, stop the watchdog timer function and execute the dwdt instruction and the wrst instruction continuously every system is returned from the power down state. when the watchdog timer function and power down function are used at the same time, initialize the flag wdf1 with the wrst instruction before system enters into the power down state. multifunction be careful that the output of ports d 8 and d 9 can be used even when int0 and int1 pins are selected. be careful that the input of ports d 4 d 6 can be used even when s in , s out and s ck pins are selected. be careful that the input/output of port d 7 can be used even when input of cntr0 pin are selected. be careful that the input of port d 7 can be used even when out- put of cntr0 pin are selected. be careful that the h output of port c can be used even when output of cntr1 pin are selected. program counter make sure that the pc h does not specify after the last page of the built-in rom. list of precautions ? connect a bypass capacitor (approx. 0.1 equalize its wiring in width and length, and use relatively thick wire. in the one time prom version, cnv ss pin is also used as v pp pin. accordingly, when using this pin, connect this pin to v ss through a resistor about 5 k ? ? register z (2 bits) register d (3 bits) register e (8 bits) ? register z (2 bits) register x (4 bits) register y (4 bits) register d (3 bits) register e (8 bits) ? ? ? ? ?
rev.2.00 jul 27, 2004 page 76 of 159 rej03b0091-0200z 4524 group d 8 /int0 pin ? depending on the input state of the d 8 /int0 pin, the external 0 in- terrupt request flag (exf0) may be set when the bit 3 of register i1 is changed. in order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register v1 to 0 (refer to figure 65 ? 0 after executing at least one instruction (refer to figure 65 ? ? ??? ? ??? ? ? ? ? when the input of int0 pin is disabled, invalidate the key-on wakeup function of int0 pin (register k2 0 = 0 ) before system goes into the power down mode. (refer to figure 66 ? la 0 ; ( ??? ? ? ? depending on the input state of the d 8 /int0 pin, the external 0 in- terrupt request flag (exf0) may be set when the bit 2 of register i1 is changed. in order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register v1 to 0 (refer to figure 67 ? 0 after executing at least one instruction (refer to figure 67 ? ? ??? ? ? ?? ? ? ? 16
rev.2.00 jul 27, 2004 page 77 of 159 rej03b0091-0200z 4524 group d 9 /int1 pin ? depending on the input state of the d 9 /int1 pin, the external 1 in- terrupt request flag (exf1) may be set when the bit 3 of register i2 is changed. in order to avoid the occurrence of an unexpected interrupt, clear the bit 1 of register v1 to 0 (refer to figure 68 ? 0 after executing at least one instruction (refer to figure 68 ? ? ?? ? ? ??? ? ? ? ? when the input of int1 pin is disabled, invalidate the key-on wakeup function of int1 pin (register k2 2 = 0 ) before system goes into the power down mode. (refer to figure 69 ? la 0 ; ( ? ?? ? ? ? depending on the input state of the d 9 /int1 pin, the external 1 in- terrupt request flag (exf1) may be set when the bit 2 of register i2 is changed. in order to avoid the occurrence of an unexpected interrupt, clear the bit 1 of register v1 to 0 (refer to figure 70 ? 0 after executing at least one instruction (refer to figure 70 ? ? ?? ? ? ? ?? ? ? ? 17 a/d converter-1 when the tala instruction is executed, the low-order 2 bits of register ad is transferred to the high-order 2 bits of register a, si- multaneously, the low-order 2 bits of register a is 0. do not change the operating mode (both a/d conversion mode and comparator mode) of a/d converter with the bit 3 of register q1 while the a/d converter is operating. clear the bit 2 of register v2 to 0 to change the operating mode of the a/d converter from the comparator mode to a/d conver- sion mode. the a/d conversion completion flag (adf) may be set when the operating mode of the a/d converter is changed from the com- parator mode to the a/d conversion mode. accordingly, set a value to the register q1, and execute the snzad instruction to clear the adf flag. la 8 ; ( ? ?? ? ??? ? 18
rev.2.00 jul 27, 2004 page 78 of 159 rej03b0091-0200z 4524 group 23 25 21 22 24 fig. 72 analog input external circuit example-1 a/d converter-2 each analog input pin is equipped with a capacitor which is used to compare the analog voltage. accordingly, when the analog volt- age is input from the circuit with high-impedance and, charge/ discharge noise is generated and the sufficient a/d accuracy may not be obtained. therefore, reduce the impedance or, connect a capacitor (0.01 f to 1 f) to analog input pins (figure 72). when the overvoltage applied to the a/d conversion circuit may occur, connect an external circuit in order to keep the voltage within the rated range as shown the figure 73. in addition, test the application products sufficiently. s e n s o r a i n apply the voltage withiin the specifications to an analog input pin. sensor a i n a b o u t 1 k ? 19 fig. 73 analog input external circuit example-2 note on voltage drop detection circuit the voltage drop detection circuit detection voltage of this product is set up lower than the minimum value of the supply voltage of the recommended operating conditions. when the supply voltage of a microcomputer falls below to the minimum value of recommended operating conditions and re- goes up (ex. battery exchange of an application product), depending on the capacity value of the bypass capacitor added to the power supply pin, the following case may cause program failure (figure 74); supply voltage does not fall below to vrst, and its voltage re-goes up with no reset. in such a case, please design a system which supply voltage is once reduced below to vrst and re-goes up after that. pof and pof2 instructions when the pof or pof2 instruction is executed continuously af- ter the epof instruction, system enters the power down state. note that system cannot enter the power down state when ex- ecuting only the pof or pof2 instruction. be sure to disable interrupts by executing the di instruction be- fore executing the epof instruction and the pof or pof2 instruction continuously. power-on reset when the built-in power-on reset circuit is used, the time for the supply voltage to rise from 0 v to 2.0 v must be set to 100 s or less. if the ris- ing time exceeds 100 s, connect a capacitor between the reset pin and v ss at the shortest distance, and input ??level to reset pin until the value of supply voltage reaches the minimum operating voltage. clock control execute the cmck or the crck instruction in the initial setting routine of program (executing it in address 0 in page 0 is recommended). the oscillation circuit by the cmck or crck instruction can be selected only at once. the oscillation circuit corresponding to the first executed one of these two instruction is valid. other oscilla- tion circuits and the on-chip oscillator stop. on-chip oscillator the clock frequency of the on-chip oscillator depends on the sup- ply voltage and the operation temperature range. be careful that margin of frequencies when designing application products. also, the oscillation stabilize wait time after system is released from re- set is generated by the on-chip oscillator clock. when considering the oscillation stabilize wait time after system is released from reset, be careful that the margin of frequency of the on-chip oscillator clock. external clock when the external clock signal is used as the main clock (f(x in )), note that the power down mode (pof or pof2 instruction) cannot be used. difference between mask rom version and one time prom version mask rom version and one time prom version have some dif- ference of the following characteristics within the limits of an electrical property by difference of a manufacture process, built- in rom, and a layout pattern. ?a characteristic value ?the amount of noise-proof ?a margin of operation noise radiation, etc., accordingly, be careful of them when swithcing. note on power source voltage when the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. in a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the supply voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. fig. 74 v dd and v rst v dd recommended operatng condition min.value no reset program failure may occur. v rst v dd recommended operatng condition min.value v rst
rev.2.00 jul 27, 2004 page 79 of 159 rej03b0091-0200z 4524 group control registers i1 3 i1 2 i1 1 i1 0 int0 pin input control bit (note 2) interrupt valid waveform for int0 pin/ return level selection bit (note 2) int0 pin edge detection circuit control bit int0 pin timer 1 count start synchronous circuit selection bit interrupt control register i1 r/w tai1/ti1a at power down : state retained at reset : 0000 2 int0 pin input disabled int0 pin input enabled falling waveform/ l level ( l level is recognized with the snzi0 instruction) rising waveform/ h level ( h level is recognized with the snzi0 instruction) one-sided edge detected both edges detected timer 1 count start synchronous circuit not selected timer 1 count start synchronous circuit selected 0 1 0 1 0 1 0 1 interrupt disabled (snzt4, snzsi instruction is valid) interrupt enabled (snzt4, snzsi instruction is invalid) interrupt disabled (snzad instruction is valid) interrupt enabled (snzad instruction is invalid) interrupt disabled (snzt5 instruction is valid) interrupt enabled (snzt5 instruction is invalid) interrupt disabled (snzt3 instruction is valid) interrupt enabled (snzt3 instruction is invalid) v1 3 v1 2 v1 1 v1 0 v2 3 v2 2 v2 1 v2 0 timer 4, serial i/o interrupt enable bit a/d interrupt enable bit timer 5 interrupt enable bit timer 3 interrupt enable bit interrupt control register v2 at power down : 0000 2 at reset : 0000 2 0 1 0 1 0 1 0 1 interrupt control register v1 timer 2 interrupt enable bit timer 1 interrupt enable bit external 1 interrupt enable bit external 0 interrupt enable bit interrupt disabled (snzt2 instruction is valid) interrupt enabled (snzt2 instruction is invalid) interrupt disabled (snzt1 instruction is valid) interrupt enabled (snzt1 instruction is invalid) interrupt disabled (snz1 instruction is valid) interrupt enabled (snz1 instruction is invalid) interrupt disabled (snz0 instruction is valid) interrupt enabled (snz0 instruction is invalid) 0 1 0 1 0 1 0 1 at power down : 0000 2 at reset : 0000 2 r/w tav1/tv1a i2 3 i2 2 i2 1 i2 0 int1 pin input control bit (note 2) interrupt valid waveform for int1 pin/ return level selection bit (note 2) int1 pin edge detection circuit control bit int1 pin timer 3 count start synchronous circuit selection bit interrupt control register i2 r/w tai2/ti2a at power down : state retained at reset : 0000 2 int1 pin input disabled int1 pin input enabled falling waveform/ l level ( l level is recognized with the snzi1 instruction) rising waveform/ h level ( h level is recognized with the snzi1 instruction) one-sided edge detected both edges detected timer 3 count start synchronous circuit not selected timer 3 count start synchronous circuit selected 0 1 0 1 0 1 0 1 notes 1: r represents read enabled, and w represents write enabled. 2: when the contents of i1 2 , i1 3 i2 2 and i2 3 are changed, the external interrupt request flag (exf0, exf1) may be set to 1 . r/w tav2/tv2a i3 0 timer 4, serial i/o interrupt source selection bit interrupt control register i3 r/w tai3/ti3a at power down : state retained at reset : 0 2 timer 4 interrupt valid, serial i/o interrupt invalid serial i/o interrupt valid, timer 4 interrupt invalid 0 1
rev.2.00 jul 27, 2004 page 80 of 159 rej03b0091-0200z 4524 group w2 1 0 0 1 1 timer 1 underflow signal divided by 2 output timer 2 underflow signal divided by 2 output stop (state retained) operating count source system clock (stck) prescaler output (orclk) timer 1 underflow signal (t1udf) pwm signal (pwmout) cntr0 output control bit timer 2 control bit timer 2 count source selection bits 0 1 0 1 w2 0 0 1 0 1 timer control register w2 at power down : state retained at reset : 0000 2 notes 1: r represents read enabled, and w represents write enabled. 2: this function is valid only when the timer 1 count start synchronous circuit is selected (i1 0 = 1 ). 3: this function is valid only when the timer 3 count start synchronous circuit is selected (i2 0 = 1 ). 4: port c output is invalid when cntr1 input is selected for the timer 3 count source. w2 3 w2 2 w2 1 w2 0 mr 3 clock control register mr operation mode through mode (frequency not divided) frequency divided by 2 mode frequency divided by 4 mode frequency divided by 8 mode main clock oscillation enabled main clock oscillation stop main clock (f(x in ) or f(ring)) sub-clock (f(x cin )) at reset : 1100 2 at power down : state retained mr 3 0 0 1 1 r/w tamr/ tmra main clock oscillation circuit control bit system clock selection bit operation mode selection bits 0 1 0 1 mr 2 0 1 0 1 mr 1 mr 0 mr 2 0 1 stop (state initialized) operating prescaler control bit timer control register pa w tpaa at power down : 0 2 at reset : 0 2 pa 0 w1 1 0 0 1 1 timer 1 count auto-stop circuit not selected timer 1 count auto-stop circuit selected stop (state retained) operating count source instruction clock (instck) prescaler output (orclk) timer 5 underflow signal (t5udf) cntr0 input timer 1 count auto-stop circuit selection bit (note 2) timer 1 control bit timer 1 count source selection bits 0 1 0 1 w1 0 0 1 0 1 timer control register w1 r/w taw1/tw1a at power down : state retained at reset : 0000 2 w1 3 w1 2 w1 1 w1 0 w3 1 0 0 1 1 timer 3 count auto-stop circuit not selected timer 3 count auto-stop circuit selected stop (state retained) operating count source pwm signal (pwmout) prescaler output (orclk) timer 2 underflow signal (t2udf) cntr1 input timer 3 count auto-stop circuit selection bit (note 3) timer 3 control bit timer 3 count source selection bits (note 4) 0 1 0 1 w3 0 0 1 0 1 timer control register w3 at power down : state retained at reset : 0000 2 w3 3 w3 2 w3 1 w3 0 r/w taw2/tw2a r/w taw3/tw3a
rev.2.00 jul 27, 2004 page 81 of 159 rej03b0091-0200z 4524 group stop (state retained) operating bit 4 (t5 4 ) of timer 5 prescaler output (orclk) cntr1 output auto-control circuit not selected cntr1 output auto-control circuit selected d 7 (i/o)/cntr0 input cntr0 input/output/d 7 (input) timer lc control bit timer lc count source selection bit cntr1 output auto-control circuit selection bit d 7 /cntr0 pin function selection bit (note 2) 0 1 0 1 0 1 0 1 timer control register w6 at power down : state retained at reset : 0000 2 w6 3 w6 2 w6 1 w6 0 cntr1 output invalid cntr1 output valid pwm signal h interval expansion function invalid pwm signal h interval expansion function valid stop (state retained) operating x in input prescaler output (orclk) divided by 2 cntr1 output control bit pwm signal h interval expansion function control bit timer 4 control bit timer 4 count source selection bit 0 1 0 1 0 1 0 1 w4 3 w4 2 w4 1 w4 0 w5 1 0 0 1 1 not used timer 5 control bit timer 5 count value selection bits 0 1 0 1 w5 0 0 1 0 1 timer control register w5 at power down : state retained at reset : 0000 2 w5 3 w5 2 w5 1 w5 0 notes 1: r represents read enabled, and w represents write enabled. 2: cntr0 input is valid only when cntr0 input is selected for the timer 1 count source. this bit has no function, but read/write is enabled. stop (state initialized) operating count value underflow occurs every 8192 counts underflow occurs every 16384 counts underflow occurs every 32768 counts underflow occurs every 65536 counts r/w taw4/tw4a timer control register w4 at power down : 0000 2 at reset : 0000 2 r/w taw5/tw5a r/w taw6/tw6a
rev.2.00 jul 27, 2004 page 82 of 159 rej03b0091-0200z 4524 group j1 3 0 0 1 1 j1 1 0 0 1 1 serial i/o synchronous clock selection bits serial i/o port function selection bits j1 2 0 1 0 1 j1 0 0 1 0 1 serial i/o control register j1 at power down : state retained at reset : 0000 2 j1 3 j1 2 j1 1 j1 0 synchronous clock instruction clock (instck) divided by 8 instruction clock (instck) divided by 4 instruction clock (instck) divided by 2 external clock (s ck input) port function d 6 , d 5 , d 4 selected/s ck , s out , s in not selected s ck , s out , d 4 selected/d 6 , d 5 , s in not selected s ck , d 5 , s in selected/d 6 , s out , d 4 not selected s ck , s out , s in selected/d 6 , d 5 , d 4 not selected r/w taj1/tj1a q1 2 0 0 0 0 1 1 1 1 a/d operation mode selection bit analog input pin selection bits q1 1 0 0 1 1 0 0 1 1 a/d control register q1 at power down : state retained at reset : 0000 2 q1 3 a/d conversion mode comparator mode r/w taq1/tq1a q1 0 0 1 0 1 0 1 0 1 q1 2 q1 1 q1 0 analog input pins a in0 a in1 a in2 a in3 a in4 a in5 a in6 a in7 p2 3 a in3 p2 2 a in2 p2 1 a in1 p2 0 a in0 p2 3 /a in3 pin function selection bit p2 2 /a in2 pin function selection bit p2 1 /a in1 pin function selection bit p2 0 /a in0 pin function selection bit 0 1 0 1 0 1 0 1 q2 3 q2 2 q2 1 q2 0 r/w taq2/tq2a a/d control register q2 at power down : state retained at reset : 0000 2 p3 3 a in7 p3 2 a in6 p3 1 a in5 p3 0 a in4 p3 3 /a in7 pin function selection bit p3 2 /a in6 pin function selection bit p3 1 /a in5 pin function selection bit p3 0 /a in4 pin function selection bit 0 1 0 1 0 1 0 1 q3 3 q3 2 q3 1 q3 0 r/w taq3/tq3a a/d control register q3 at power down : state retained at reset : 0000 2 note: r represents read enabled, and w represents write enabled.
rev.2.00 jul 27, 2004 page 83 of 159 rej03b0091-0200z 4524 group internal dividing resistor for lcd power supply selection bit (note 2) lcd control bit lcd control register l1 l1 3 l1 2 l1 1 l1 0 at reset : 0000 2 at power down : state retained 0 1 0 1 l1 1 0 0 1 1 l1 0 0 1 0 1 duty 1/2 1/3 1/4 bias 1/2 1/3 1/3 lcd control register l2 at reset : 1111 2 at power down : state retained w tl2a 0 1 0 1 0 1 0 1 seg 0 v lc3 seg 1 v lc2 seg 2 v lc1 internal dividing resistor valid internal dividing resistor invalid l2 3 l2 2 l2 1 l2 0 v lc3 /seg 0 pin function switch bit (note 3) v lc2 /seg 1 pin function switch bit (note 4) v lc1 /seg 2 pin function switch bit (note 4) internal dividing resistor for lcd power supply control bit 2r ? ? ? ? r represents read enabled, and w represents write enabled. 2: r (resistor) multiplied by 3 is used at 1/3 bias, and r multiplied by 2 is used at 1/2 bias. 3: v lc3 is connected to v dd internally when seg 0 pin is selected. 4: use internal dividing resistor when seg 1 and seg 2 pins are selected. r/w tal1/tl1a pu0 3 pu0 2 pu0 1 pu0 0 pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on port p0 3 pull-up transistor control bit port p0 2 pull-up transistor control bit port p0 1 pull-up transistor control bit port p0 0 pull-up transistor control bit pull-up control register pu0 at reset : 0000 2 at power down : state retained 0 1 0 1 0 1 0 1 r/w tapu0/ tpu0a pu1 3 pu1 2 pu1 1 pu1 0 pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on port p1 3 pull-up transistor control bit port p1 2 pull-up transistor control bit port p1 1 pull-up transistor control bit port p1 0 pull-up transistor control bit pull-up control register pu1 at reset : 0000 2 at power down : state retained 0 1 0 1 0 1 0 1 r/w tapu1/ tpu1a lcd duty and bias selection bits
rev.2.00 jul 27, 2004 page 84 of 159 rej03b0091-0200z 4524 group fr0 3 fr0 2 fr0 1 fr0 0 n-channel open-drain output cmos output n-channel open-drain output cmos output n-channel open-drain output cmos output n-channel open-drain output cmos output ports p1 2 , p1 3 output structure selection bit ports p1 0 , p1 1 output structure selection bit ports p0 2 , p0 3 output structure selection bit ports p0 0 , p0 1 output structure selection bit port output structure control register fr0 at reset : 0000 2 at power down : state retained 0 1 0 1 0 1 0 1 fr1 3 fr1 2 fr1 1 fr1 0 n-channel open-drain output cmos output n-channel open-drain output cmos output n-channel open-drain output cmos output n-channel open-drain output cmos output port d 3 output structure selection bit port d 2 output structure selection bit port d 1 output structure selection bit port d 0 output structure selection bit port output structure control register fr1 at reset : 0000 2 at power down : state retained 0 1 0 1 0 1 0 1 fr2 3 fr2 2 fr2 1 fr2 0 n-channel open-drain output cmos output n-channel open-drain output cmos output n-channel open-drain output cmos output n-channel open-drain output cmos output port d 7 /cntr0 output structure selection bit port d 6 /s ck output structure selection bit port d 5 /s out output structure selection bit port d 4 /s in output structure selection bit port output structure control register fr2 at reset : 0000 2 at power down : state retained 0 1 0 1 0 1 0 1 note: r represents read enabled, and w represents write enabled. w tfr0a w tfr1a w tfr2a fr3 3 fr3 2 fr3 1 fr3 0 n-channel open-drain output cmos output n-channel open-drain output cmos output n-channel open-drain output cmos output n-channel open-drain output cmos output port p4 3 output structure selection bit port p4 2 output structure selection bit port p4 1 output structure selection bit port p4 0 output structure selection bit port output structure control register fr3 at reset : 0000 2 at power down : state retained 0 1 0 1 0 1 0 1 w tfr3a
rev.2.00 jul 27, 2004 page 85 of 159 rej03b0091-0200z 4524 group k0 3 k0 2 k0 1 k0 0 key-on wakeup control register k0 key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used port p0 3 key-on wakeup control bit port p0 2 key-on wakeup control bit port p0 1 key-on wakeup control bit port p0 0 key-on wakeup control bit at reset : 0000 2 at power down : state retained 0 1 0 1 0 1 0 1 r/w tak0/ tk0a note: r represents read enabled, and w represents write enabled. k1 3 k1 2 k1 1 k1 0 key-on wakeup control register k1 key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used port p1 3 key-on wakeup control bit port p1 2 key-on wakeup control bit port p1 1 key-on wakeup control bit port p1 0 key-on wakeup control bit at reset : 0000 2 at power down : state retained 0 1 0 1 0 1 0 1 k2 3 k2 2 k2 1 k2 0 key-on wakeup control register k2 returned by level returned by edge key-on wakeup invalid key-on wakeup valid returned by level returned by edge key-on wakeup invalid key-on wakeup valid int1 pin return condition selection bit int1 pin key-on wakeup control bit int0 pin return condition selection bit int0 pin key-on wakeup control bit at reset : 0000 2 at power down : state retained 0 1 0 1 0 1 0 1 r/w tak1/ tk1a r/w tak2/ tk2a
rev.2.00 jul 27, 2004 page 86 of 159 rej03b0091-0200z 4524 group symbol a b dr e v1 v2 i1 i2 i3 mr pa w1 w2 w3 w4 w5 w6 j1 q1 q2 q3 l1 l2 pu0 pu1 fr0 fr1 fr2 fr3 k0 k1 k2 x y z dp pc pc h pc l sk sp cy rps r1 r2 r3 r4l r4h rlc contents register a (4 bits) register b (4 bits) register dr (3 bits) register e (8 bits) interrupt control register v1 (4 bits) interrupt control register v2 (4 bits) interrupt control register i1 (4 bits) interrupt control register i2 (4 bits) interrupt control register i3 (1 bit) clock control register mr (4 bits) timer control register pa (1 bit) timer control register w1 (4 bits) timer control register w2 (4 bits) timer control register w3 (4 bits) timer control register w4 (4 bits) timer control register w5 (4 bits) timer control register w6 (4 bits) serial i/o control register j1 (4 bits) a/d control register q1 (4 bits) a/d control register q2 (4 bits) a/d control register q3 (4 bits) lcd control register l1 (4 bits) lcd control register l2 (4 bits) pull-up control register pu0 (4 bits) pull-up control register pu1 (4 bits) port output format control register fr0 (4 bits) port output format control register fr1 (4 bits) port output format control register fr2 (4 bits) port output format control register fr3 (4 bits) key-on wakeup control register k0 (4 bits) key-on wakeup control register k1 (4 bits) key-on wakeup control register k2 (4 bits) register x (4 bits) register y (4 bits) register z (2 bits) data pointer (10 bits) (it consists of registers x, y, and z) program counter (14 bits) high-order 7 bits of program counter low-order 7 bits of program counter stack register (14 bits ? ? contents of registers and memories negate, flag unchanged after executing instruction ram address pointed by the data pointer label indicating address a 6 a 5 a 4 a 3 a 2 a 1 a 0 label indicating address a 6 a 5 a 4 a 3 a 2 a 1 a 0 in page p 5 p 4 p 3 p 2 p 1 p 0 hex. c + hex. number x symbol ps t1 t2 t3 t4 t5 tlc t1f t2f t3f t4f t5f wdf1 wef inte exf0 exf1 p adf siof d p0 p1 p2 p3 p4 c x y z p n i j a 3 a 2 a 1 a 0 ? m(dp) a p, a c + x instructions the 4524 group has the 136 instructions. each instruction is de- scribed as follows; (1) index list of instruction function (2) machine instructions (index by alphabet) (3) machine instructions (index by function) (4) instruction code table note : some instructions of the 4524 group has the skip function to unexecute the next described instruction. the 4524 group jus t invalidates the next instruc- tion when a skip is performed. the contents of program counter is not increased by 2. accordingly, the number of cycles does no t change even if skip is not performed. however, the cycle count becomes 1 if the tabp p, rt, or rts instruction is skipped. symbol the symbols shown below are used in the following list of instruc- tion function and the machine instructions.
rev.2.00 jul 27, 2004 page 87 of 159 rej03b0091-0200z 4524 group index list of instruction function group- ing ram addresses mnemonic xami j tma j la n tabp p am amc a n and or sc rc szc cma rar function (a) dr 0 , a 3 a 0 ) (b) 4 (a) 0 (pc) 1 (a) e 4 ) e 0 ) e 4 ) (a) e 0 ) (dr 2 dr 0 ) a 0 ) (a 2 a 0 ) dr 0 ) (a 3 ) a 0 ) sp 0 ) (a 3 ) 1 (a) 1 ram to register transfer arithmetic operation ram to register transfer register to register transfer group- ing page 111, 132 121, 132 120, 132 130, 132 121, 132 112, 132 121, 132 113, 132 121, 132 120, 132 118, 132 98, 132 99, 132 98, 132 95, 132 116, 132 131, 132 131, 132 page 131, 132 125, 132 98, 134 113, 134 92, 134 92, 134 92, 134 93, 134 100, 134 104, 134 102, 134 109, 134 95, 134 101, 134 note: p is 0 to 63 for m34524m8, p is 0 to 95 for m34524mc and p is 0 to 127 for m34524ed.
rev.2.00 jul 27, 2004 page 88 of 159 rej03b0091-0200z 4524 group index list of instruction function (continued) group- ing function (mj(dp)) a 0 (pc h ) a 0 (pc h ) dr 0 , a 3 a 0 ) (sp) a 0 (sp) a 0 (sp) dr 0 , a 3 a 0 ) (pc) 1 (pc) 1 (pc) 1 comparison operation subroutine operation branch operation bit operation return operation mnemonic sb j rb j szb j seam sea n b a bl p, a bla p bm a bml p, a bmla p rti rt rts group- ing page 103, 134 101, 134 109, 134 105, 134 105, 134 93, 136 93, 136 93, 136 94, 136 94, 136 94, 136 103, 136 103, 136 103, 136 function (inte) h ? i1 2 = 0 : (int0) = l ? i2 2 = 1 : (int1) = h ? i2 2 = 0 : (int1) = l ? (a) a 1 )
rev.2.00 jul 27, 2004 page 89 of 159 rej03b0091-0200z 4524 group index list of instruction function (continued) group- ing group- ing function (a) tps 4 ) (a) tps 0 ) (rps 7 rps 4 ) tps 4 ) rps 0 ) tps 0 ) t1 4 ) (a) t1 0 ) (r1 7 r1 4 ) t1 4 ) r1 0 ) t1 0 ) t2 4 ) (a) t2 0 ) (r2 7 r2 4 ) t2 4 ) r2 0 ) t2 0 ) t3 4 ) (a) t3 0 ) (r3 7 r3 4 ) t3 4 ) r3 0 ) t3 0 ) t4 4 ) (a) t4 0 ) (r4l 7 r4l 4 ) t4 4 ) r4l 0 ) t4 0 ) r4h 4 ) r4h 0 ) r1 4 ) r1 0 ) r3 4 ) r3 0 ) t4 4 ) r4l 4 ) (t4 3 t4 0 ) r4l 0 ) (lc)
rev.2.00 jul 27, 2004 page 90 of 159 rej03b0091-0200z 4524 group index list of instruction function (continued) group- ing group- ing page 94, 142 102, 142 104, 142 109, 142 102, 142 104, 142 117, 142 126, 142 117, 142 126, 142 124, 144 115, 144 124, 144 115, 144 124, 144 115, 144 122, 144 122, 144 122, 144 122, 144 95, 144 95, 144 116, 144 125, 144 page 116, 144 124, 144 124, 144 113, 144 128, 144 108, 144 107, 144 115, 144 123, 144 112, 146 116, 146 114, 146 92, 146 106, 146 117, 146 127, 146 117, 146 127, 146 118, 146 127, 146 a/d operation serial i/o operation input/output operation function (d) si 4 ) (a) si 0 ) (si 7 si 4 ) si 0 ) ad 6 ) (a) ad 2 ) in comparator mode, (b) ad 4 ) (a) ad 0 ) (a 3 , a 2 ) ad 4 ) ad 0 )
rev.2.00 jul 27, 2004 page 91 of 159 rej03b0091-0200z 4524 group mnemonic nop pof pof2 epof snzp dwdt wrst rbk* sbk* svde function (pc)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.2.00 jul 27, 2004 page 92 of 159 rej03b0091-0200z 4524 group machine instructions (index by alphabet) a n (add n and accumulator) 000110nnnn 06n 11 overflow = 0 grouping: arithmetic operation description: adds the value n in the immediate field to register a, and stores a result in register a. the contents of carry flag cy remains unchanged. skips the next instruction when there is no overflow as the result of operation. executes the next instruction when there is overflow as the result of operation. operation: (a) grouping: a/d conversion operation description: clears (0) to a/d conversion completion flag adf, and the a/d conversion at the a/d conversion mode (q1 3 = 0) or the compara- tor operation at the comparator mode (q1 3 = 1) is started. operation: (adf) grouping: arithmetic operation description: adds the contents of m(dp) to register a. stores the result in register a. the contents of carry flag cy remains unchanged. operation: (a) grouping: arithmetic operation description: adds the contents of m(dp) and carry flag cy to register a. stores the result in regis- ter a and carry flag cy. operation: (a)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.2.00 jul 27, 2004 page 93 of 159 rej03b0091-0200z 4524 group and (logical and between accumulator and memory) 0000011000 018 11 grouping: arithmetic operation description: takes the and operation between the con- tents of register a and the contents of m(dp), and stores the result in register a. operation: (a) grouping: branch operation description: branch within a page : branches to address a in the identical page. note: specify the branch address within the page including this instruction. operation: (pc l ) grouping: branch operation description: branch out of a page : branches to address a in page p. note: p is 0 to 63 for m34524m8, and p is 0 to 95 for m34524mc, and p is 0 to 127 for m34524ed. operation: (pc h ) grouping: branch operation description: branch out of a page : branches to address (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) 2 specified by registers d and a in page p. note: p is 0 to 63 for m34524m8, and p is 0 to 95 for m34524mc, and p is 0 to 127 for m34524ed. 8 +a 2 16 1p 6 p 5 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a e +p operation: (pc h ) dr 0 , a 3 a 0 ) 2 16 1p 6 p 5 p 4 00p 3 p 2 p 1 p 0 pp machine instructions (index by alphabet) (continued) 2 +p p +a 2 +p
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.2.00 jul 27, 2004 page 94 of 159 rej03b0091-0200z 4524 group bm a (branch and mark to address a in page 2) 010a 6 a 5 a 4 a 3 a 2 a 1 a 0 1aa 11 grouping: subroutine call operation description: call the subroutine in page 2 : calls the subroutine at address a in page 2. note: subroutine extending from page 2 to an- other page can also be called with the bm instruction when it starts on page 2. be careful not to over the stack because the maximum level of subroutine nesting is 8. operation: (sp) a 0 bml p, a (branch and mark long to address a in page p) 00110p 4 p 3 p 2 p 1 p 0 0p 22 grouping: subroutine call operation description: call the subroutine : calls the subroutine at address a in page p. note: p is 0 to 63 for m34524m8, and p is 0 to 95 for m34524mc, and p is 0 to 127 for m34524ed. be careful not to over the stack because the maximum level of subroutine nesting is 8. operation: (sp) a 0 bmla p (branch and mark long to address (d) + (a) in page p) 0000110000 030 22 grouping: subroutine call operation description: call the subroutine : calls the subroutine at address (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) 2 speci- fied by registers d and a in page p. note: p is 0 to 63 for m34524m8, and p is 0 to 95 for m34524mc, and p is 0 to 127 for m34524ed. be careful not to over the stack because the maximum level of subroutine nesting is 8. cld (clear port d) 0000010001 011 11 grouping: input/output operation description: sets (1) to port d. operation: (d) dr 0 , a 3 a 0 ) 2 16 1p 6 p 5 p 4 00p 3 p 2 p 1 p 0 pp machine instructions (index by alphabet) (continued) 2 +p p +a 2 +p
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.2.00 jul 27, 2004 page 95 of 159 rej03b0091-0200z 4524 group cma (complement of accumulator) 0000011100 01c 11 grouping: arithmetic operation description: stores the one s complement for register a s contents in register a. operation: (a) grouping: other operation description: selects the ceramic oscillation circuit and stops the on-chip oscillator. operation: ceramic oscillation circuit selected crck (clock select: rc oscillation clock) 1010011011 29b 11 grouping: other operation description: selects the rc oscillation circuit and stops the on-chip oscillator. operation: rc oscillation circuit selected dey (decrement register y) 0000010111 017 11 (y) = 15 grouping: ram addresses description: subtracts 1 from the contents of register y. as a result of subtraction, when the con- tents of register y is 15, the next instruction is skipped. when the contents of register y is not 15, the next instruction is executed. operation: (y) 1 machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.2.00 jul 27, 2004 page 96 of 159 rej03b0091-0200z 4524 group di (disable interrupt) 0000000100 004 11 grouping: interrupt control operation description: clears (0) to interrupt enable flag inte, and disables the interrupt. note: interrupt is disabled by executing the di in- struction after executing 1 machine cycle. operation: (inte) grouping: other operation description: stops the watchdog timer function by the wrst instruction after executing the dwdt instruction. operation: stop of watchdog timer function enabled epof (enable pof instruction) 0001011011 05b 11 grouping: other operation description: makes the immediate after pof or pof2 instruction valid by executing the epof in- struction. operation: pof instruction, pof2 instruction valid ei (enable interrupt) 0000000101 005 11 grouping: interrupt control operation description: sets (1) to interrupt enable flag inte, and enables the interrupt. note: interrupt is enabled by executing the ei in- struction after executing 1 machine cycle. operation: (inte)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.2.00 jul 27, 2004 page 97 of 159 rej03b0091-0200z 4524 group iap0 (input accumulator from port p0) 1001100000 260 11 grouping: input/output operation description: transfers the input of port p0 to register a. iap1 (input accumulator from port p1) 1001100001 261 11 grouping: input/output operation description: transfers the input of port p1 to register a. operation: (a) grouping: input/output operation description: transfers the input of port p2 to register a. operation: (a) grouping: input/output operation description: transfers the input of port p3 to register a. operation: (a)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.2.00 jul 27, 2004 page 98 of 159 rej03b0091-0200z 4524 group iny (increment register y) 0000010011 013 11 (y) = 0 grouping: ram addresses description: adds 1 to the contents of register y. as a re- sult of addition, when the contents of register y is 0, the next instruction is skipped. when the contents of register y is not 0, the next instruction is executed. operation: (y) continuous description grouping: arithmetic operation description: loads the value n in the immediate field to register a. when the la instructions are continuously coded and executed, only the first la in- struction is executed and other la instructions coded continuously are skipped. operation: (a) continuous description grouping: ram addresses description: loads the value x in the immediate field to register x, and the value y in the immediate field to register y. when the lxy instruc- tions are continuously coded and executed, only the first lxy instruction is executed and other lxy instructions coded continu- ously are skipped. operation: (x) grouping: input/output operation description: transfers the input of port p4 to register a. operation: (a)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.2.00 jul 27, 2004 page 99 of 159 rej03b0091-0200z 4524 group lz z (load register z with z) 00010010z 1 z 0 04 11 grouping: ram addresses description: loads the value z in the immediate field to register z. operation: (z) grouping: other operation description: no operation; adds 1 to program counter value, and others remain unchanged. operation: (pc) grouping: input/output operation description: outputs the contents of register a to port p0. operation: (p0) grouping: input/output operation description: outputs the contents of register a to port p1. operation: (p1)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.2.00 jul 27, 2004 page 100 of 159 rej03b0091-0200z 4524 group or (logical or between accumulator and memory) 0000011001 019 11 grouping: arithmetic operation description: takes the or operation between the con- tents of register a and the contents of m(dp), and stores the result in register a. operation: (a) grouping: input/output operation description: outputs the contents of register a to port p4. operation: (p4) grouping: input/output operation description: outputs the contents of register a to port p2. operation: (p2) grouping: input/output operation description: outputs the contents of register a to port p3. operation: (p3)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.2.00 jul 27, 2004 page 101 of 159 rej03b0091-0200z 4524 group pof (power off1) 0000000010 002 11 grouping: other operation description: puts the system in clock operating state by executing the pof instruction after execut- ing the epof instruction. note: if the epof instruction is not executed before executing this instruction, this instruction is equivalent to the nop instruction. pof2 (power off2) 0000001000 008 11 grouping: other operation description: puts the system in ram back-up state by executing the pof2 instruction after ex- ecuting the epof instruction. note: if the epof instruction is not executed before executing this instruction, this instruction is equivalent to the nop instruction. operation: transition to ram back-up mode operation: transition to clock operating mode rar (rotate accumulator right) 0000011101 01d 11 0/1 grouping: arithmetic operation description: rotates 1 bit of the contents of register a in- cluding the contents of carry flag cy to the right. operation: grouping: bit operation description: clears (0) the contents of bit j (bit specified by the value j in the immediate field) of m(dp). operation: (mj(dp))
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.2.00 jul 27, 2004 page 102 of 159 rej03b0091-0200z 4524 group rd (reset port d specified by register y) 0000010100 014 11 grouping: input/output operation description: clears (0) to a bit of port d specified by reg- ister y. operation: (d(y)) grouping: arithmetic operation description: clears (0) to carry flag cy. operation: (cy) grouping: input/output operation description: clears (0) to port c. operation: (c) grouping: other operation description: sets referring data area to pages 0 to 63 when the tabp p instruction is executed. note: this instruction cannot be used in m34524m8. operation: when tabp p instruction is executed, p 6
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.2.00 jul 27, 2004 page 103 of 159 rej03b0091-0200z 4524 group rti (return from interrupt) 0001000110 046 11 grouping: return operation description: returns from interrupt service routine to main routine. returns each value of data pointer (x, y, z), carry flag, skip status, nop mode status by the continuous description of the la/lxy in- struction, register a and register b to the states just before interrupt. rts (return from subroutine and skip) 0001000101 045 12 skip at uncondition grouping: return operation description: returns from subroutine to the routine called the subroutine, and skips the next in- struction at uncondition. operation: (pc) 1 operation: (pc) 1 sb j (set bit) 00010111j j 05 11 grouping: bit operation description: sets (1) the contents of bit j (bit specified by the value j in the immediate field) of m(dp). operation: (mj(dp)) grouping: return operation description: returns from subroutine to the routine called the subroutine. operation: (pc) 1
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.2.00 jul 27, 2004 page 104 of 159 rej03b0091-0200z 4524 group scp (set port c) 1010001101 28d 11 grouping: input/output operation description: sets (1) to port c. operation: (c) grouping: input/output operation description: sets (1) to a bit of port d specified by regis- ter y. operation: (d(y)) grouping: arithmetic operation description: sets (1) to carry flag cy. operation: (cy) grouping: other operation description: sets referring data area to pages 64 to 127 when the tabp p instruction is executed. note: this instruction cannot be used in m34524m8. in m34524mc, referring data area is pages 64 to 95. operation: when tabp p instruction is executed, p 6
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.2.00 jul 27, 2004 page 105 of 159 rej03b0091-0200z 4524 group snz0 (skip if non zero condition of external 0 interrupt request flag) 0000111000 038 11 v1 0 = 0: (exf0) = 1 grouping: interrupt operation description: when v1 0 = 0 : skips the next instruction when external 0 interrupt request flag exf0 is 1. after skipping, clears (0) to the exf0 flag. when the exf0 flag is 0, executes the next instruction. when v1 0 = 1 : this instruction is equiva- lent to the nop instruction. operation: v1 0 = 0: (exf0) = 1 ? after skipping, (exf0) (a) = n grouping: comparison operation description: skips the next instruction when the con- tents of register a is equal to the value n in the immediate field. executes the next instruction when the con- tents of register a is not equal to the value n in the immediate field. operation: (a) = n ? n = 0 to 15 2 16 000111nnnn 07n seam (skip equal, accumulator with memory) 0000100110 026 11 (a) = (m(dp)) grouping: comparison operation description: skips the next instruction when the con- tents of register a is equal to the contents of m(dp). executes the next instruction when the con- tents of register a is not equal to the contents of m(dp). operation: (a) = (m(dp)) ? snz1 (skip if non zero condition of external 1 interrupt request flag) 0000111001 039 11 v1 1 = 0: (exf1) = 1 grouping: interrupt operation description: when v1 1 = 0 : skips the next instruction when external 1 interrupt request flag exf1 is 1. after skipping, clears (0) to the exf1 flag. when the exf1 flag is 0, executes the next instruction. when v1 1 = 1 : this instruction is equiva- lent to the nop instruction. operation: v1 1 = 0: (exf1) = 1 ? after skipping, (exf1)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.2.00 jul 27, 2004 page 106 of 159 rej03b0091-0200z 4524 group snzp (skip if non zero condition of power down flag) 0000000011 003 11 (p) = 1 grouping: other operation description: skips the next instruction when the p flag is 1 . after skipping, the p flag remains un- changed. executes the next instruction when the p flag is 0. operation: (p) = 1 ? snzad (skip if non zero condition of a/d conversion completion flag) 1010000111 287 11 v2 2 = 0: (adf) = 1 grouping: a/d conversion operation description: when v2 2 = 0 : skips the next instruction when a/d conversion completion flag adf is 1. after skipping, clears (0) to the adf flag. when the adf flag is 0, executes the next instruction. when v2 2 = 1 : this instruction is equiva- lent to the nop instruction. operation: v2 2 = 0: (adf) = 1 ? after skipping, (adf) i1 2 = 0 : (int0) = l i1 2 = 1 : (int0) = h grouping: interrupt operation description: when i1 2 = 0 : skips the next instruction when the level of int0 pin is l. executes the next instruction when the level of int0 pin is h. when i1 2 = 1 : skips the next instruction when the level of int0 pin is h. executes the next instruction when the level of int0 pin is l. operation: i1 2 = 0 : (int0) = l ? i1 2 = 1 : (int0) = h ? (i1 2 : bit 2 of the interrupt control register i1) snzi1 (skip if non zero condition of external 1 interrupt input pin) 0000111011 03b 11 i2 2 = 0 : (int1) = l i2 2 = 1 : (int1) = h grouping: interrupt operation description: when i2 2 = 0 : skips the next instruction when the level of int1 pin is l. executes the next instruction when the level of int1 pin is h. when i2 2 = 1 : skips the next instruction when the level of int1 pin is h. executes the next instruction when the level of int1 pin is l. operation: i2 2 = 0 : (int1) = l ? i2 2 = 1 : (int1) = h ? (i2 2 : bit 2 of the interrupt control register i2) machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.2.00 jul 27, 2004 page 107 of 159 rej03b0091-0200z 4524 group snzt1 (skip if non zero condition of timer 1 interrupt request flag) 1010000000 280 11 v1 2 = 0: (t1f) = 1 grouping: timer operation description: when v1 2 = 0 : skips the next instruction when timer 1 interrupt request flag t1f is 1. after skipping, clears (0) to the t1f flag. when the t1f flag is 0, executes the next instruction. when v1 2 = 1 : this instruction is equiva- lent to the nop instruction. operation: v1 2 = 0: (t1f) = 1 ? after skipping, (t1f) v1 3 = 0: (t2f) = 1 grouping: timer operation description: when v1 3 = 0 : skips the next instruction when timer 2 interrupt request flag t2f is 1. after skipping, clears (0) to the t2f flag. when the t2f flag is 0, executes the next instruction. when v1 3 = 1 : this instruction is equiva- lent to the nop instruction. operation: v1 3 = 0: (t2f) = 1 ? after skipping, (t2f) v2 0 = 0: (t3f) = 1 grouping: timer operation description: when v2 0 = 0 : skips the next instruction when timer 3 interrupt request flag t3f is 1. after skipping, clears (0) to the t3f flag. when the t3f flag is 0, executes the next instruction. when v2 0 = 1 : this instruction is equiva- lent to the nop instruction. operation: v2 0 = 0: (t3f) = 1 ? after skipping, (t3f) v2 3 = 0: (siof) = 1 grouping: serial i/o operation description: when v2 3 = 0 : skips the next instruction when serial i/o interrupt request flag siof is 1. after skipping, clears (0) to the siof flag. when the siof flag is 0, executes the next instruction. when v2 3 = 1 : this instruction is equiva- lent to the nop instruction. operation: v2 3 = 0: (siof) = 1 ? after skipping, (siof)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.2.00 jul 27, 2004 page 108 of 159 rej03b0091-0200z 4524 group snzt4 (skip if non zero condition of timer 4 inerrupt request flag) snzt5 (skip if non zero condition of timer 5 inerrupt request flag) sst (serial i/o transmission/reception start) svde (set voltage detector enable flag) 1010000011 283 11 v2 3 = 0: (t4f) = 1 grouping: timer operation description: when v2 3 = 0 : skips the next instruction when timer 4 interrupt request flag t4f is 1. after skipping, clears (0) to the t4f flag. when the t4f flag is 0, executes the next instruction. when v2 3 = 1 : this instruction is equiva- lent to the nop instruction. operation: v2 3 = 0: (t4f) = 1 ? after skipping, (t4f) v2 1 = 0: (t5f) = 1 grouping: timer operation description: when v2 1 = 0 : skips the next instruction when timer 5 interrupt request flag t5f is 1. after skipping, clears (0) to the t5f flag. when the t5f flag is 0, executes the next instruction. when v2 1 = 1 : this instruction is equiva- lent to the nop instruction. operation: v2 1 = 0: (t5f) = 1 ? after skipping, (t5f) grouping: serial i/o operation description: clears (0) to siof flag and starts serial i/o. operation: (siof) grouping: other operation description: validates the voltage drop detection circuit at power down (clock operating mode and ram back-up mode) when vdce pin is h . operation: at power down mode, voltage drop detection circuit valid machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.2.00 jul 27, 2004 page 109 of 159 rej03b0091-0200z 4524 group machine instructions (index by alphabet) (continued) szb j (skip if zero, bit) 00001000j j 02j 11 (mj(dp)) = 0 j = 0 to 3 grouping: bit operation description: skips the next instruction when the con- tents of bit j (bit specified by the value j in the immediate field) of m(dp) is 0. executes the next instruction when the con- tents of bit j of m(dp) is 1. operation: (mj(dp)) = 0 ? j = 0 to 3 szc (skip if zero, carry flag) 0000101111 02f 11 (cy) = 0 grouping: arithmetic operation description: skips the next instruction when the con- tents of carry flag cy is 0. after skipping, the cy flag remains un- changed. executes the next instruction when the con- tents of the cy flag is 1. operation: (cy) = 0 ? szd (skip if zero, port d specified by register y) 0000100100 024 22 (d(y)) = 0 (y) = 0 to 7 grouping: input/output operation description: skips the next instruction when a bit of port d specified by register y is 0. executes the next instruction when the bit is 1. t1ab (transfer data to timer 1 and register r1 from accumulator and register b) 1000110000 230 11 grouping: timer operation description: transfers the contents of register b to the high-order 4 bits of timer 1 and timer 1 re- load register r1. transfers the contents of register a to the low-order 4 bits of timer 1 and timer 1 reload register r1. operation: (t1 7 t1 4 ) r1 4 ) t1 0 ) r1 0 )
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.2.00 jul 27, 2004 page 110 of 159 rej03b0091-0200z 4524 group t2ab (transfer data to timer 2 and register r2 from accumulator and register b) 1000110001 231 11 grouping: timer operation description: transfers the contents of register b to the high-order 4 bits of timer 2 and timer 2 re- load register r2. transfers the contents of register a to the low-order 4 bits of timer 2 and timer 2 reload register r2. operation: (t2 7 t2 4 ) r2 4 ) t2 0 ) r2 0 ) grouping: timer operation description: transfers the contents of register b to the high-order 4 bits of timer 3 and timer 3 re- load register r3. transfers the contents of register a to the low-order 4 bits of timer 3 and timer 3 reload register r3. operation: (t3 7 t3 4 ) r3 4 ) t3 0 ) r3 0 ) grouping: timer operation description: transfers the contents of register b to the high-order 4 bits of timer 4 and timer 4 re- load register r4l. transfers the contents of register a to the low-order 4 bits of timer 4 and timer 4 reload register r4l. operation: (t4 7 t4 4 ) r4l 4 ) t4 0 ) r4l 0 ) grouping: timer operation description: transfers the contents of register b to the high-order 4 bits of timer 4 and timer 4 re- load register r4h. transfers the contents of register a to the low-order 4 bits of timer 4 and timer 4 reload register r4h. operation: (r4h 7 r4h 4 ) r4h 0 )
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.2.00 jul 27, 2004 page 111 of 159 rej03b0091-0200z 4524 group tab (transfer data to accumulator from register b) 0000011110 01e 11 grouping: register to register transfer description: transfers the contents of register b to reg- ister a. tab1 (transfer data to accumulator and register b from timer 1) 1001110000 270 11 grouping: timer operation description: transfers the high-order 4 bits (t1 7 t1 4 ) of timer 1 to register b. transfers the low-order 4 bits (t1 3 t1 0 ) of timer 1 to register a. operation: (b) t1 4 ) (a) t1 0 ) tab2 (transfer data to accumulator and register b from timer 2) 1001110001 271 11 grouping: timer operation description: transfers the high-order 4 bits (t2 7 t2 4 ) of timer 2 to register b. transfers the low-order 4 bits (t2 3 t2 0 ) of timer 2 to register a. operation: (b) t2 4 ) (a) t2 0 ) operation: (a) grouping: timer operation description: transfers the contents of reload register r4l to timer 4. operation: (t4 7 t4 4 ) r4l 4 ) (t4 3 t4 0 ) r4l 0 )
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.2.00 jul 27, 2004 page 112 of 159 rej03b0091-0200z 4524 group tabe (transfer data to accumulator and register b from register e) 0000101010 02a 11 grouping: register to register transfer description: transfers the high-order 4 bits (e 7 e 4 ) of register e to register b, and low-order 4 bits of register e to register a. operation: (b) e 4 ) (a) e 0 ) tabad (transfer data to accumulator and register b from register ad) 1001111001 279 11 grouping: a/d conversion operation description: in the a/d conversion mode (q1 3 = 0), trans- fers the high-order 4 bits (ad 9 ad 6 ) of register ad to register b, and the middle-or- der 4 bits (ad 5 ad 2 ) of register ad to register a. in the comparator mode (q1 3 = 1), transfers the middle-order 4 bits (ad 7 ad 4 ) of register ad to register b, and the low-order 4 bits (ad 3 ad 0 ) of register ad to register a. operation: in a/d conversion mode (q1 3 = 0), (b) ad 6 ) (a) ad 2 ) in comparator mode (q1 3 = 1), (b) ad 4 ) (a) ad 0 ) (q1 3 : bit 3 of a/d control register q1) tab4 (transfer data to accumulator and register b from timer 4) tab3 (transfer data to accumulator and register b from timer 3) 1001110010 272 11 grouping: timer operation description: transfers the high-order 4 bits (t3 7 t3 4 ) of timer 3 to register b. transfers the low-order 4 bits (t3 3 t3 0 ) of timer 3 to register a. operation: (b) t3 4 ) (a) t3 0 ) 1001110011 273 11 grouping: timer operation description: transfers the high-order 4 bits (t4 7 t4 4 ) of timer 4 to register b. transfers the low-order 4 bits (t4 3 t4 0 ) of timer 4 to register a. operation: (b) t4 4 ) (a) t4 0 ) machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.2.00 jul 27, 2004 page 113 of 159 rej03b0091-0200z 4524 group tabp p (transfer data to accumulator and register b from program memory in page p) 0010p 5 p 4 p 3 p 2 p 1 p 0 0p 13 grouping: arithmetic operation operation: (sp) dr 0 , a 3 a 0 ) (b) 4 (a) 0 (pc) 1 tad (transfer data to accumulator from register d) 0001010001 051 11 grouping: register to register transfer description: transfers the contents of register d to the low-order 3 bits (a 2 a 0 ) of register a. note: when this instruction is executed, 0 is stored to the bit 3 (a 3 ) of register a. operation: (a 2 a 0 ) dr 0 ) (a 3 ) grouping: serial i/o operation description: transfers the high-order 4 bits (si 7 si 4 ) of serial i/o register si to register b, and transfers the low-order 4 bits (si 3 si 0 ) of serial i/o register si to register a. operation: (b) si 4 ) (a) si 0 ) 1001110101 275 11 grouping: timer operation description: transfers the high-order 4 bits (tps 7 tps 4 ) of prescaler to register b, and transfers the low-order 4 bits (tps 3 tps 0 ) of prescaler to register a. operation: (b) tps 4 ) (a) tps 0 ) description: transfers bits 7 to 4 to register b and bits 3 to 0 to register a. these bits 7 to 0 are the rom pattern in address (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) 2 specified by reg- isters a and d in page p. the pages which can be referred as follows; after the sbk instruction: 64 to 127 after the rbk instruction: 0 to 63 after system is released from reset or returned from power down: 0 to 63. note: p is 0 to 63 for m34524m8, and p is 0 to 95 for m34524mc, and p is 0 to 127 for m34524ed. when this instruction is executed, be careful not to over the stack because 1 stage of stack register is used.
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.2.00 jul 27, 2004 page 114 of 159 rej03b0091-0200z 4524 group tadab (transfer data to register ad from accumulator from register b) 1000111001 239 11 grouping: a/d conversion operation description: in the a/d conversion mode (q1 3 = 0), this in- struction is equivalent to the nop instruction. in the comparator mode (q1 3 = 1), trans- fers the contents of register b to the high-order 4 bits (ad 7 ad 4 ) of comparator register, and the contents of register a to the low-order 4 bits (ad 3 ad 0 ) of compara- tor register. (q1 3 = bit 3 of a/d control register q1) operation: (ad 7 ad 4 ) ad 0 ) grouping: interrupt operation description: transfers the contents of interrupt control register i1 to register a. operation: (a) grouping: interrupt operation description: transfers the contents of interrupt control register i2 to register a. operation: (a) grouping: interrupt operation description: transfers the contents of interrupt control register i3 to the lowermost bit (a 0 ) of regis- ter a. note: when the tai3 instruction is executed, 0 is stored to the high-order 3 bits (a 3 a 1 ) of register a. operation: (a 0 ) a 1 )
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.2.00 jul 27, 2004 page 115 of 159 rej03b0091-0200z 4524 group tak0 (transfer data to accumulator from register k0) 1001010110 256 11 grouping: input/output operation description: transfers the contents of key-on wakeup control register k0 to register a. operation: (a) grouping: input/output operation description: transfers the contents of key-on wakeup control register k1 to register a. operation: (a) grouping: input/output operation description: transfers the contents of key-on wakeup control register k2 to register a. operation: (a) grouping: serial i/o operation description: transfers the contents of serial i/o control register j1 to register a. operation: (a)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.2.00 jul 27, 2004 page 116 of 159 rej03b0091-0200z 4524 group tala (transfer data to accumulator from register la) 1001001001 249 11 grouping: a/d conversion operation description: transfers the low-order 2 bits (ad 1 , ad 0 ) of register ad to the high-order 2 bits (a 3 , a 2 ) of register a. note: after this instruction is executed, 0 is stored to the low-order 2 bits (a 1 , a 0 ) of register a. operation: (a 3 , a 2 ) grouping: ram to register transfer description: after transferring the contents of m(dp) to register a, an exclusive or operation is performed between register x and the value j in the immediate field, and stores the re- sult in register x. tamr (transfer data to accumulator from register mr) 1001010010 252 11 grouping: clock operation description: transfers the contents of clock control reg- ister mr to register a. operation: (a) grouping: lcd control operation description: transfers the lcd control register l1 to register a. operation: (a)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.2.00 jul 27, 2004 page 117 of 159 rej03b0091-0200z 4524 group taq1 (transfer data to accumulator from register q1) 1001000100 244 11 grouping: a/d conversion operation description: transfers the contents of a/d control regis- ter q1 to register a. operation: (a) grouping: a/d conversion operation description: transfers the contents of a/d control regis- ter q2 to register a. operation: (a) grouping: input/output operation description: transfers the contents of pull-up control register pu0 to register a. operation: (a) grouping: input/output operation description: transfers the contents of pull-up control register pu1 to register a. operation: (a)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.2.00 jul 27, 2004 page 118 of 159 rej03b0091-0200z 4524 group tasp (transfer data to accumulator from stack pointer) 0001010000 050 11 grouping: register to register transfer description: transfers the contents of stack pointer (sp) to the low-order 3 bits (a 2 a 0 ) of register a. note: after this instruction is executed, 0 is stored to the bit 3 (a 3 ) of register a. tav1 (transfer data to accumulator from register v1) 0001010100 054 11 grouping: interrupt operation description: transfers the contents of interrupt control register v1 to register a. operation: (a) grouping: interrupt operation description: transfers the contents of interrupt control register v2 to register a. operation: (a) a 0 ) sp 0 ) (a 3 ) grouping: a/d conversion operation description: transfers the contents of a/d control regis- ter q3 to register a. operation: (a)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.2.00 jul 27, 2004 page 119 of 159 rej03b0091-0200z 4524 group taw2 (transfer data to accumulator from register w2) 1001001100 24c 11 grouping: timer operation description: transfers the contents of timer control reg- ister w2 to register a. operation: (a) grouping: timer operation description: transfers the contents of timer control reg- ister w1 to register a. operation: (a) grouping: timer operation description: transfers the contents of timer control reg- ister w4 to register a. operation: (a) grouping: timer operation description: transfers the contents of timer control reg- ister w3 to register a. operation: (a)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.2.00 jul 27, 2004 page 120 of 159 rej03b0091-0200z 4524 group taw5 (transfer data to accumulator from register w5) taw6 (transfer data to accumulator from register w6) 1001010000 250 11 grouping: timer operation description: transfers the contents of timer control reg- ister w6 to register a. tax (transfer data to accumulator from register x) 0001010010 052 11 grouping: register to register transfer description: transfers the contents of register x to reg- ister a. operation: (a) grouping: register to register transfer description: transfers the contents of register y to regis- ter a. operation: (a) grouping: timer operation description: transfers the contents of timer control reg- ister w5 to register a. operation: (a)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.2.00 jul 27, 2004 page 121 of 159 rej03b0091-0200z 4524 group tba (transfer data to register b from accumulator) 0000001110 00e 11 grouping: register to register transfer description: transfers the contents of register a to regis- ter b. tda (transfer data to register d from accumulator) 0000101001 029 11 grouping: register to register transfer description: transfers the contents of the low-order 3 bits (a 2 a 0 ) of register a to register d. operation: (dr 2 dr 0 ) a 0 ) teab (transfer data to register e from accumulator and register b) 0000011010 01a 11 grouping: register to register transfer description: transfers the contents of register b to the high-order 4 bits (e 7 e 4 ) of register e, and the contents of register a to the low-order 4 bits (e 3 e 0 ) of register e. operation: (e 7 e 4 ) e 0 ) grouping: register to register transfer description: transfers the contents of register z to the low-order 2 bits (a 1 , a 0 ) of register a. note: after this instruction is executed, 0 is stored to the high-order 2 bits (a 3 , a 2 ) of register a. operation: (a 1 , a 0 )
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.2.00 jul 27, 2004 page 122 of 159 rej03b0091-0200z 4524 group tfr3a (transfer data to register fr3 from accumulator) tfr2a (transfer data to register fr2 from accumulator) tfr1a (transfer data to register fr1 from accumulator) tfr0a (transfer data to register fr0 from accumulator) 1000101000 228 11 grouping: input/output operation description: transfers the contents of register a to the port output structure control register fr0. operation: (fr0) grouping: input/output operation description: transfers the contents of register a to the port output structure control register fr1. operation: (fr1) grouping: input/output operation description: transfers the contents of register a to the port output structure control register fr2. operation: (fr2) grouping: input/output operation description: transfers the contents of register a to the port output structure control register fr3. operation: (fr3)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.2.00 jul 27, 2004 page 123 of 159 rej03b0091-0200z 4524 group ti1a (transfer data to register i1 from accumulator) 1000010111 217 11 grouping: interrupt operation description: transfers the contents of register a to inter- rupt control register i1. operation: (i1) grouping: interrupt operation description: transfers the contents of register a to inter- rupt control register i2. operation: (i2) grouping: interrupt operation description: transfers the contents of the lowermost bit (a 0 ) of register a to interrupt control register i1. operation: (i3 0 ) grouping: serial i/o operation description: transfers the contents of register a to serial i/o control register j1. operation: (j1)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.2.00 jul 27, 2004 page 124 of 159 rej03b0091-0200z 4524 group tk0a (transfer data to register k0 from accumulator) 1000011011 21b 11 grouping: input/output operation description: transfers the contents of register a to key- on wakeup control register k0. operation: (k0) grouping: input/output operation description: transfers the contents of register a to key- on wakeup control register k1. tk2a (transfer data to register k2 from accumulator) 1000010101 215 11 grouping: input/output operation description: transfers the contents of register a to key- on wakeup control register k2. operation: (k2) grouping: lcd operation description: transfers the contents of register a to lcd control register l1. operation: (l1)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.2.00 jul 27, 2004 page 125 of 159 rej03b0091-0200z 4524 group tl2a (transfer data to register l2 from accumulator) tlca (transfer data to timer lc and register rlc from accumulator) tma j (transfer data to memory from accumulator) 101011 jjjj 2bj 11 grouping: ram to register transfer description: after transferring the contents of register a to m(dp), an exclusive or operation is per- formed between register x and the value j in the immediate field, and stores the result in register x. operation: (m(dp)) grouping: other operation description: transfers the contents of register a to clock control register mr. operation: (mr) grouping: lcd operation description: transfers the contents of register a to lcd control register l2. operation: (l2) grouping: timer operation description: transfers the contents of register a to timer lc and reload register rlc. operation: (lc)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.2.00 jul 27, 2004 page 126 of 159 rej03b0091-0200z 4524 group tpu0a (transfer data to register pu0 from accumulator) 1000101101 22d 11 grouping: input/output operation description: transfers the contents of register a to pull- up control register pu0. operation: (pu0) grouping: input/output operation description: transfers the contents of register a to pull- up control register pu1. operation: (pu1) grouping: timer operation description: transfers the contents of lowermost bit (a 0 ) register a to timer control register pa. operation: (pa 0 ) grouping: timer operation description: transfers the contents of register b to the high-order 4 bits of prescaler and prescaler reload register rps, and transfers the con- tents of register a to the low-order 4 bits of prescaler and prescaler reload register rps. operation: (rps 7 rps 4 ) tps 4 ) rps 0 ) tps 0 )
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.2.00 jul 27, 2004 page 127 of 159 rej03b0091-0200z 4524 group tq2a (transfer data to register q2 from accumulator) tr1ab (transfer data to register r1 from accumulator and register b) 1000111111 23f 11 grouping: timer operation description: transfers the contents of register b to the high-order 4 bits (r1 7 r1 4 ) of reload regis- ter r1, and the contents of register a to the low-order 4 bits (r1 3 r1 0 ) of reload regis- ter r1. operation: (r1 7 r1 4 ) r1 0 ) grouping: a/d conversion operation description: transfers the contents of register a to a/d control register q1. operation: (q1) grouping: a/d conversion operation description: transfers the contents of register a to a/d control register q2. operation: (q2) grouping: a/d conversion operation description: transfers the contents of register a to a/d control register q3. operation: (q3)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.2.00 jul 27, 2004 page 128 of 159 rej03b0091-0200z 4524 group machine instructions (index by alphabet) (continued) tv1a (transfer data to register v1 from accumulator) 0000111111 03f 11 grouping: interrupt operation description: transfers the contents of register a to inter- rupt control register v1. operation: (v1) grouping: interrupt operation description: transfers the contents of register a to inter- rupt control register v2. operation: (v2) grouping: timer operation description: transfers the contents of register b to the high-order 4 bits (r3 7 r3 4 ) of reload regis- ter r3, and the contents of register a to the low-order 4 bits (r3 3 r3 0 ) of reload regis- ter r3. operation: (r3 7 r3 4 ) r3 0 ) grouping: timer operation description: transfers the contents of register b to the high-order 4 bits (si 7 si 4 ) of serial i/o reg- ister si, and transfers the contents of register a to the low-order 4 bits (si 3 si 0 ) of serial i/o register si. operation: (si 7 si 4 ) si 0 )
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.2.00 jul 27, 2004 page 129 of 159 rej03b0091-0200z 4524 group tw3a (transfer data to register w3 from accumulator) tw4a (transfer data to register w4 from accumulator) tw1a (transfer data to register w1 from accumulator) 1000001110 20e 11 grouping: timer operation description: transfers the contents of register a to timer control register w1. operation: (w1) grouping: timer operation description: transfers the contents of register a to timer control register w2. operation: (w2) grouping: timer operation description: transfers the contents of register a to timer control register w3. operation: (w3) grouping: timer operation description: transfers the contents of register a to timer control register w4. operation: (w4)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.2.00 jul 27, 2004 page 130 of 159 rej03b0091-0200z 4524 group tya (transfer data to register y from accumulator) 0000001100 00c 11 grouping: register to register transfer description: transfers the contents of register a to regis- ter y. operation: (y) (wdf1) = 1 grouping: other operation description: skips the next instruction when watchdog timer flag wdf1 is 1. after skipping, clears (0) to the wdf1 flag. when the wdf1 flag is 0, executes the next instruction. also, stops the watchdog timer function when ex- ecuting the wrst instruction immediately after the dwdt instruction. operation: (wdf1) = 1 ? after skipping, (wdf1) grouping: timer operation description: transfers the contents of register a to timer control register w6. operation: (w6) grouping: timer operation description: transfers the contents of register a to timer control register w5. operation: (w5)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.2.00 jul 27, 2004 page 131 of 159 rej03b0091-0200z 4524 group xami j (exchange accumulator and memory data and increment register y and skip) 101110 jjjj 2ej 11 (y) = 0 grouping: ram to register transfer description: after exchanging the contents of m(dp) with the contents of register a, an exclusive or operation is performed between regis- ter x and the value j in the immediate field, and stores the result in register x. adds 1 to the contents of register y. as a re- sult of addition, when the contents of register y is 0, the next instruction is skipped. when the contents of register y is not 0, the next instruction is executed. operation: (a) grouping: ram to register transfer description: after exchanging the contents of m(dp) with the contents of register a, an exclusive or operation is performed between regis- ter x and the value j in the immediate field, and stores the result in register x. operation: (a) (y) = 15 grouping: ram to register transfer description: after exchanging the contents of m(dp) with the contents of register a, an exclusive or operation is performed between regis- ter x and the value j in the immediate field, and stores the result in register x. subtracts 1 from the contents of register y. as a result of subtraction, when the con- tents of register y is 15, the next instruction is skipped. when the contents of register y is not 15, the next instruction is executed. operation: (a) 1 machine instructions (index by alphabet) (continued)
parameter instruction code function number of cycles number of words mnemonic type of instructions d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecimal notation rev.2.00 jul 27, 2004 page 132 of 159 rej03b0091-0200z 4524 group (a) e 4 ) e 0 ) e 4 ) (a) e 0 ) (dr 2 dr 0 ) a 0 ) (a 2 a 0 ) dr 0 ) (a 3 ) a 0 ) sp 0 ) (a 3 ) 1 (a) 1 (a)
skip condition datailed description carry flag cy rev.2.00 jul 27, 2004 page 133 of 159 rej03b0091-0200z 4524 group continuous description (y) = 0 (y) = 15 (y) = 15 (y) = 0 transfers the contents of register b to register a. transfers the contents of register a to register b. transfers the contents of register y to register a. transfers the contents of register a to register y. transfers the contents of register b to the high-order 4 bits (e 7 e 4 ) of register e, and the contents of regis- ter a to the low-order 4 bits (e 3 e 0 ) of register e. transfers the high-order 4 bits (e 7 e 4 ) of register e to register b, and low-order 4 bits (e 3 e 0 ) of register e to register a. transfers the contents of the low-order 3 bits (a 2 a 0 ) of register a to register d. transfers the contents of register d to the low-order 3 bits (a 2 a 0 ) of register a. transfers the contents of register z to the low-order 2 bits (a 1 , a 0 ) of register a. transfers the contents of register x to register a. transfers the contents of stack pointer (sp) to the low-order 3 bits (a 2 a 0 ) of register a. loads the value x in the immediate field to register x, and the value y in the immediate field to register y. when the lxy instructions are continuously coded and executed, only the first lxy instruction is executed and other lxy instructions coded continuously are skipped. loads the value z in the immediate field to register z. adds 1 to the contents of register y. as a result of addition, when the contents of register y is 0, the next in- struction is skipped. when the contents of register y is not 0, the next instruction is executed. subtracts 1 from the contents of register y. as a result of subtraction, when the contents of register y is 15, the next instruction is skipped. when the contents of register y is not 15, the next instruction is executed. after transferring the contents of m(dp) to register a, an exclusive or operation is performed between reg- ister x and the value j in the immediate field, and stores the result in register x. after exchanging the contents of m(dp) with the contents of register a, an exclusive or operation is per- formed between register x and the value j in the immediate field, and stores the result in register x. after exchanging the contents of m(dp) with the contents of register a, an exclusive or operation is per- formed between register x and the value j in the immediate field, and stores the result in register x. subtracts 1 from the contents of register y. as a result of subtraction, when the contents of register y is 15, the next instruction is skipped. when the contents of register y is not 15, the next instruction is executed. after exchanging the contents of m(dp) with the contents of register a, an exclusive or operation is per- formed between register x and the value j in the immediate field, and stores the result in register x. adds 1 to the contents of register y. as a result of addition, when the contents of register y is 0, the next in- struction is skipped. when the contents of register y is not 0, the next instruction is executed. after transferring the contents of register a to m(dp), an exclusive or operation is performed between reg- ister x and the value j in the immediate field, and stores the result in register x.
parameter instruction code function number of cycles number of words mnemonic type of instructions d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecimal notation rev.2.00 jul 27, 2004 page 134 of 159 rej03b0091-0200z 4524 group machine instructions (index by types) (continued) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 07n 08p +p 00a 00b 06n 018 019 007 006 02f 01c 01d 05c +j 04c +j 02j 026 025 07n 000111nnnn 0010p 5 p 4 p 3 p 2 p 1 p 0 0000001010 0000001011 000110nnnn 0000011000 0000011001 0000000111 0000000110 0000101111 0000011100 0000011101 00010111j j 00010011j j 00001000j j 0000100110 0000100101 000111nnnn la n tabp p am amc a n and or sc rc szc cma rar sb j rb j szb j seam sea n 1 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 arithmetic operation comparison operation bit operation (a) dr 0 , a 3 a 0 ) (b) 4 (a) 0 (pc) 1 (a)
skip condition datailed description carry flag cy rev.2.00 jul 27, 2004 page 135 of 159 rej03b0091-0200z 4524 group continuous description overflow = 0 (cy) = 0 (mj(dp)) = 0 j = 0 to 3 (a) = (m(dp)) (a) = n 0/1 1 0 0/1 loads the value n in the immediate field to register a. when the la instructions are continuously coded and executed, only the first la instruction is executed and other la instructions coded continuously are skipped. transfers bits 7 to 4 to register b and bits 3 to 0 to register a. these bits 7 to 0 are the rom pattern in ad- dress (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) 2 specified by registers a and d in page p. when this instruction is executed, be careful not to over the stack because 1 stage of stack register is used. the pages which can be referred as follows; after the sbk instruction: 64 to 127 after the rbk instruction: 0 to 63 after system is released from reset or returned from power down: 0 to 63. adds the contents of m(dp) to register a. stores the result in register a. the contents of carry flag cy re- mains unchanged. adds the contents of m(dp) and carry flag cy to register a. stores the result in register a and carry flag cy. adds the value n in the immediate field to register a, and stores a result in register a. the contents of carry flag cy remains unchanged. skips the next instruction when there is no overflow as the result of operation. executes the next instruction when there is overflow as the result of operation. takes the and operation between the contents of register a and the contents of m(dp), and stores the re- sult in register a. takes the or operation between the contents of register a and the contents of m(dp), and stores the result in register a. sets (1) to carry flag cy. clears (0) to carry flag cy. skips the next instruction when the contents of carry flag cy is 0. stores the one s complement for register a s contents in register a. rotates 1 bit of the contents of register a including the contents of carry flag cy to the right. sets (1) the contents of bit j (bit specified by the value j in the immediate field) of m(dp). clears (0) the contents of bit j (bit specified by the value j in the immediate field) of m(dp). skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of m(dp) is 0. executes the next instruction when the contents of bit j of m(dp) is 1. skips the next instruction when the contents of register a is equal to the contents of m(dp). executes the next instruction when the contents of register a is not equal to the contents of m(dp). skips the next instruction when the contents of register a is equal to the value n in the immediate field. executes the next instruction when the contents of register a is not equal to the value n in the immediate field.
parameter instruction code function number of cycles number of words mnemonic type of instructions d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecimal notation rev.2.00 jul 27, 2004 page 136 of 159 rej03b0091-0200z 4524 group b a bl p, a bla p bm a bml p, a bmla p rti rt rts 011a 6 a 5 a 4 a 3 a 2 a 1 a 0 00111p 4 p 3 p 2 p 1 p 0 1p 6 p 5 a 6 a 5 a 4 a 3 a 2 a 1 a 0 0000010000 1p 6 p 5 p 4 00p 3 p 2 p 1 p 0 010a 6 a 5 a 4 a 3 a 2 a 1 a 0 00110p 4 p 3 p 2 p 1 p 0 1p 6 p 5 a 6 a 5 a 4 a 3 a 2 a 1 a 0 0000110000 1p 6 p 5 p 4 00p 3 p 2 p 1 p 0 0001000110 0001000100 0001000101 18a +a 0ep +p 2pa +p +a 010 2pp +p 1aa 0cp +p 2pa +p +a 030 2pp +p 046 044 045 1 2 2 1 2 2 1 1 1 1 2 2 1 2 2 1 2 2 subroutine operation return operation machine instructions (continued) (pc l ) a 0 (pc h ) a 0 (pc h ) dr 0 , a 3 a 0 ) (sp) a 0 (sp) a 0 (sp) dr 0 ,a 3 a 0 ) (pc) 1 (pc) 1 (pc) 1 branch operation note: p is 0 to 63 for m34524m8, p is 0 to 95 for m34524mc and p is 0 to 127 for m34524ed.
skip condition datailed description carry flag cy rev.2.00 jul 27, 2004 page 137 of 159 rej03b0091-0200z 4524 group skip at uncondition branch within a page : branches to address a in the identical page. branch out of a page : branches to address a in page p. branch out of a page : branches to address (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) 2 specified by registers d and a in page p. call the subroutine in page 2 : calls the subroutine at address a in page 2. call the subroutine : calls the subroutine at address a in page p. call the subroutine : calls the subroutine at address (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) 2 specified by registers d and a in page p. returns from interrupt service routine to main routine. returns each value of data pointer (x, y, z), carry flag, skip status, nop mode status by the continuous de- scription of the la/lxy instruction, register a and register b to the states just before interrupt. returns from subroutine to the routine called the subroutine. returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition.
parameter instruction code function number of cycles number of words mnemonic type of instructions d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecimal notation rev.2.00 jul 27, 2004 page 138 of 159 rej03b0091-0200z 4524 group di ei snz0 snz1 snzi0 snzi1 tav1 tv1a tav2 tv2a tai1 ti1a tai2 ti2a tai3 ti3a tpaa taw1 tw1a taw2 tw2a taw3 tw3a taw4 tw4a (inte) h ? i1 2 = 0 : (int0) = l ? i2 2 = 1 : (int1) = h ? i2 2 = 0 : (int1) = l ? (a) a 1 )
skip condition datailed description carry flag cy rev.2.00 jul 27, 2004 page 139 of 159 rej03b0091-0200z 4524 group v1 0 = 0: (exf0) = 1 v1 1 = 0: (exf1) = 1 (int0) = h however, i1 2 = 1 (int0) = l however, i1 2 = 0 (int1) = h however, i2 2 = 1 (int1) = l however, i2 2 = 0 skip condition datailed description carry flag cy clears (0) to interrupt enable flag inte, and disables the interrupt. sets (1) to interrupt enable flag inte, and enables the interrupt. when v1 0 = 0 : skips the next instruction when external 0 interrupt request flag exf0 is 1. after skipping, clears (0) to the exf0 flag. when the exf0 flag is 0, executes the next instruction. when v1 0 = 1 : this instruction is equivalent to the nop instruction. (v1 0 : bit 0 of interrupt control register v1) when v1 1 = 0 : skips the next instruction when external 1 interrupt request flag exf1 is 1. after skipping, clears (0) to the exf1 flag. when the exf1 flag is 0, executes the next instruction. when v1 1 = 1 : this instruction is equivalent to the nop instruction. (v1 1 : bit 1 of interrupt control register v1) when i1 2 = 1 : skips the next instruction when the level of int0 pin is h. (i1 2 : bit 2 of interrupt control reg- ister i1) when i1 2 = 0 : skips the next instruction when the level of int0 pin is l. when i2 2 = 1 : skips the next instruction when the level of int1 pin is h. (i2 2 : bit 2 of interrupt control reg- ister i2) when i2 2 = 0 : skips the next instruction when the level of int1 pin is l. transfers the contents of interrupt control register v1 to register a. transfers the contents of register a to interrupt control register v1. transfers the contents of interrupt control register v2 to register a. transfers the contents of register a to interrupt control register v2. transfers the contents of interrupt control register i1 to register a. transfers the contents of register a to interrupt control register i1. transfers the contents of interrupt control register i2 to register a. transfers the contents of register a to interrupt control register i2. transfers the contents of interrupt control register i3 to the lowermost bit (a 0 ) of register a. transfers the contents of the lowermost bit (a 0 ) of register a to interrupt control register i3. transfers the contents of register a to timer control register pa. transfers the contents of timer control register w1 to register a. transfers the contents of register a to timer control register w1. transfers the contents of timer control register w2 to register a. transfers the contents of register a to timer control register w2. transfers the contents of timer control register w3 to register a. transfers the contents of register a to timer control register w3. transfers the contents of timer control register w4 to register a. transfers the contents of register a to timer control register w4.
parameter instruction code function number of cycles number of words mnemonic type of instructions d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecimal notation rev.2.00 jul 27, 2004 page 140 of 159 rej03b0091-0200z 4524 group 1001001111 1000010010 1001010000 1000010011 1001110101 1000110101 1001110000 1000110000 1001110001 1000110001 1001110010 1000110010 1001110011 1000110011 1000110111 1000111111 1000111011 1010010111 1000001101 24f 212 250 213 275 235 270 230 271 231 272 232 273 233 237 23f 23b 297 20d (a) tps 4 ) (a) tps 0 ) (rps 7 rps 4 ) tps 4 ) rps 0 ) tps 0 ) t1 4 ) (a) t1 0 ) (r1 7 r1 4 ) t1 4 ) r1 0 ) t1 0 ) t2 4 ) (a) t2 0 ) (r2 7 r2 4 ) t2 4 ) r2 0 ) t2 0 ) t3 4 ) (a) t3 0 ) (r3 7 r3 4 ) t3 4 ) r3 0 ) t3 0 ) t4 4 ) (a) t4 0 ) (r4l 7 r4l 4 ) t4 4 ) r4l 0 ) t4 0 ) r4h 4 ) r4h 0 ) r1 4 ) r1 0 ) r3 4 ) r3 0 ) t4 0 ) r4l 0 ) (lc)
skip condition datailed description carry flag cy rev.2.00 jul 27, 2004 page 141 of 159 rej03b0091-0200z 4524 group transfers the contents of timer control register w5 to register a. transfers the contents of register a to timer control register w5. transfers the contents of timer control register w6 to register a. transfers the contents of register a to timer control register w6. transfers the high-order 4 bits of prescaler to register b, and transfers the low-order 4 bits of prescaler to register a. transfers the contents of register b to the high-order 4 bits of prescaler and prescaler reload register rps, and transfers the contents of register a to the low-order 4 bits of prescaler and prescaler reload register rps. transfers the high-order 4 bits of timer 1 to register b, and transfers the low-order 4 bits of timer 1 to regis- ter a. transfers the contents of register b to the high-order 4 bits of timer 1 and timer 1 reload register r1, and transfers the contents of register a to the low-order 4 bits of timer 1 and timer 1 reload register r1. transfers the high-order 4 bits of timer 2 to register b, and transfers the low-order 4 bits of timer 2 to regis- ter a. transfers the contents of register b to the high-order 4 bits of timer 2 and timer 2 reload register r2, and transfers the contents of register a to the low-order 4 bits of timer 2 and timer 2 reload register r2. transfers the high-order 4 bits of timer 3 to register b, and transfers the low-order 4 bits of timer 3 to regis- ter a. transfers the contents of register b to the high-order 4 bits of timer 3 and timer 3 reload register r3, and transfers the contents of register a to the low-order 4 bits of timer 3 and timer 3 reload register r3. transfers the high-order 4 bits of timer 4 to register b, and transfers the low-order 4 bits of timer 4 to regis- ter a. transfers the contents of register b to the high-order 4 bits of timer 4 and timer 4 reload register r4l, and transfers the contents of register a to the low-order 4 bits of timer 4 and timer 4 reload register r4l. transfers the contents of register b to the high-order 4 bits of timer 4 reload register r4h, and transfers the contents of register a to the low-order 4 bits of timer 4 reload register r4h. transfers the contents of register b to the high-order 4 bits of timer 1 reload register r1, and transfers the contents of register a to the low-order 4 bits of timer 1 reload register r1. transfers the contents of register b to the high-order 4 bits of timer 3 reload register r3, and transfers the contents of register a to the low-order 4 bits of timer 3 reload register r3. transfers the contents of timer 4 reload register r4l to timer 4. transfers the contents of register a to timer lc and timer lc reload register rlc.
parameter instruction code function number of cycles number of words mnemonic type of instructions d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecimal notation rev.2.00 jul 27, 2004 page 142 of 159 rej03b0091-0200z 4524 group 1010000000 1010000001 1010000010 1010000011 1010000100 1001100000 1000100000 1001100001 1000100001 1001100010 1000100010 1001100011 1000100011 1001100100 1000100100 0000010001 0000010100 0000010101 0000100100 0000101011 1010001100 1010001101 1001010111 1000101101 1001011110 1000101110 280 281 282 283 284 260 220 261 221 262 222 263 223 264 224 011 014 015 024 02b 28c 28d 257 22d 25e 22e 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 snzt1 snzt2 snzt3 snzt4 snzt5 iap0 op0a iap1 op1a iap2 op2a iap3 op3a iap4 op4a cld rd sd szd rcp scp tapu0 tpu0a tapu1 tpu1a v1 2 = 0: (t1f) = 1 ? after skipping, (t1f)
skip condition datailed description carry flag cy rev.2.00 jul 27, 2004 page 143 of 159 rej03b0091-0200z 4524 group skips the next instruction when the contents of bit 2 (v1 2 ) of interrupt control register v1 is 0 and the con- tents of t1f flag is 1. after skipping, clears (0) to t1f flag. skips the next instruction when the contents of bit 3 (v1 3 ) of interrupt control register v1 is 0 and the con- tents of t2f flag is 1. after skipping, clears (0) to t2f flag. skips the next instruction when the contents of bit 0 (v2 0 ) of interrupt control register v2 is 0 and the con- tents of t3f flag is 1. after skipping, clears (0) to t3f flag. skips the next instruction when the contents of bit 3 (v2 3 ) of interrupt control register v2 is 0 and the con- tents of t4f flag is 1. after skipping, clears (0) to t4f flag. skips the next instruction when the contents of bit 1 (v2 1 ) of interrupt control register v2 is 0 and the con- tents of t5f flag is 1. after skipping, clears (0) to t5f flag. transfers the input of port p0 to register a. outputs the contents of register a to port p0. transfers the input of port p1 to register a. outputs the contents of register a to port p1. transfers the input of port p2 to register a. outputs the contents of register a to port p2. transfers the input of port p3 to register a. outputs the contents of register a to port p3. transfers the input of port p4 to register a. outputs the contents of register a to port p4. sets (1) to all port d. clears (0) to a bit of port d specified by register y. sets (1) to a bit of port d specified by register y. skips the next instruction when a bit of port d specified by register y is 0. executes the next instruction when a bit of port d specified by register y is 1. clears (0) to port c. sets (1) to port c. transfers the contents of pull-up control register pu0 to register a. transfers the contents of register a to pull-up control register pu0. transfers the contents of pull-up control register pu1 to register a. transfers the contents of register a to pull-up control register pu1. v1 2 = 0: (t1f) = 1 v1 3 = 0: (t2f) =1 v2 0 = 0: (t3f) = 1 v2 3 = 0: (t4f) =1 v2 1 = 0: (t5f) =1 (d(y)) = 0 however, (y)=0 to 7
parameter instruction code function number of cycles number of words mnemonic type of instructions d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecimal notation rev.2.00 jul 27, 2004 page 144 of 159 rej03b0091-0200z 4524 group tak0 tk0a tak1 tk1a tak2 tk2a tfr0a tfr1a tfr2a tfr3a tal1 tl1a tl2a tabsi tsiab sst snzsi taj1 tj1a cmck crck tamr tmra 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 256 21b 259 214 25a 215 228 229 22a 22b 24a 20a 20b 278 238 29e 288 242 202 29a 29b 252 216 1001010110 1000011011 1001011001 1000010100 1001011010 1000010101 1000101000 1000101001 1000101010 1000101011 1001001010 1000001010 1000001011 1001111000 1000111000 1010011110 1010001000 1001000010 1000000010 1010011010 1010011011 1001010010 1000010110 input/output operation (a) si 4 ) (a) si 0 ) (si 7 si 4 ) si 0 )
skip condition datailed description carry flag cy rev.2.00 jul 27, 2004 page 145 of 159 rej03b0091-0200z 4524 group v2 3 = 0: (siof) = 1 transfers the contents of key-on wakeup control register k0 to register a. transfers the contents of register a to key-on wakeup control register k0 . transfers the contents of key-on wakeup control register k1 to register a. transfers the contents of register a to key-on wakeup control register k1. transfers the contents of key-on wakeup control register k2 to register a. transfers the contents of register a to key-on wakeup control register k2. transferts the contents of register a to port output format control register fr0. transferts the contents of register a to port output format control register fr1. transferts the contents of register a to port output format control register fr2. transferts the contents of register a to port output format control register fr3. transfers the contents of lcd control register l1 to register a. transfers the contents of register a to lcd control register l1. transfers the contents of register a to lcd control register l2. transfers the high-order 4 bits of serial i/o register si to register b, and transfers the low-order 4 bits of se- rial i/o register si to register a. transfers the contents of register b to the high-order 4 bits of serial i/o register si, and transfers the con- tents of register a to the low-order 4 bits of serial i/o register si. clears (0) to siof flag and starts serial i/o. skips the next instruction when the contents of bit 3 (v2 3 ) of interrupt control register v2 is 0 and contents of siof flag is 1. after skipping, clears (0) to siof flag. transfers the contents of serial i/o control register j1 to register a. transfers the contents of register a to serial i/o control register j1. selects the ceramic resonator for main clock, stops the on-chip oscillator (internal oscillator). selects the rc oscillation circuit for main clock, stops the on-chip oscillator (internal oscillator). transfers the contents of clock control regiser mr to register a. transfers the contents of register a to clock control register mr.
parameter instruction code function number of cycles number of words mnemonic type of instructions d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecimal notation rev.2.00 jul 27, 2004 page 146 of 159 rej03b0091-0200z 4524 group 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 279 249 239 29f 287 244 204 245 205 246 206 000 002 008 05b 003 2a0 29c 040 041 293 1001111001 1001001001 1000111001 1010011111 1010000111 1001000100 1000000100 1001000101 1000000101 1001000110 1000000110 0000000000 0000000010 0000001000 0001011011 0000000011 1010100000 1010011100 0001000000 0001000001 1010010011 a/d conversion operation other operation machine instructions (index by types) (continued) tabad tala tadab adst snzad taq1 tq1a taq2 tq2a taq3 tq3a nop pof pof2 epof snzp wrst dwdt rbk* sbk* svde q1 3 = 0: (b) ad 6 ) (a) ad 2 ) q1 3 = 1: (b) ad 4 ) (a) ad 0 ) (a 3 , a 2 ) ad 4 ) ad 0 )
skip condition datailed description carry flag cy rev.2.00 jul 27, 2004 page 147 of 159 rej03b0091-0200z 4524 group v2 2 = 0: (adf) = 1 (p) = 1 (wdf1) = 1 in the a/d conversion mode (q1 3 = 0), transfers the high-order 4 bits (ad 9 ad 6 ) of register ad to register b, and the middle-order 4 bits (ad 5 ad 2 ) of register ad to register a. in the comparator mode (q1 3 = 1), transfers the middle-order 4 bits (ad 7 ad 4 ) of register ad to register b, and the low-order 4 bits (ad 3 ad 0 ) of register ad to register a. (q1 3 : bit 3 of a/d control register q1) transfers the low-order 2 bits (ad 1 , ad 0 ) of register ad to the high-order 2 bits (ad 3 , ad 2 ) of register a. in the comparator mode (q1 3 = 1), transfers the contents of register b to the high-order 4 bits (ad 7 ad 4 ) of comparator register, and the contents of register a to the low-order 4 bits (ad 3 ad 0 ) of comparator register. (q1 3 = bit 3 of a/d control register q1) clears (0) to a/d conversion completion flag adf, and the a/d conversion at the a/d conversion mode (q1 3 = 0) or the comparator operation at the comparator mode (q1 3 = 1) is started. (q1 3 = bit 3 of a/d control register q1) when v2 2 = 0 : skips the next instruction when a/d conversion completion flag adf is 1. after skipping, clears (0) to the adf flag. when the adf flag is 0, executes the next instruction. (v2 2 : bit 2 of interrupt con- trol register v2) transfers the contents of a/d control register q1 to register a. transfers the contents of register a to a/d control register q1. transfers the contents of a/d control register q2 to register a. transfers the contents of register a to a/d control register q2. transfers the contents of a/d control register q3 to register a. transfers the contents of register a to a/d control register q3. no operation; adds 1 to program counter value, and others remain unchanged. puts the system in clock operating mode by executing the pof instruction after executing the epof instruc- tion. puts the system in ram back-up state by executing the pof2 instruction after executing the epof instruction. makes the immediate after pof or pof2 instruction valid by executing the epof instruction. skips the next instruction when the p flag is 1 . after skipping, the p flag remains unchanged. skips the next instruction when watchdog timer flag wdf1 is 1. after skipping, clears (0) to the wdf1 flag. also, stops the watchdog timer function when executing the wrst instruction immediately after the dwdt instruction. stops the watchdog timer function by the wrst instruction after executing the dwdt instruction. sets referring data area to pages 0 to 63 when the tabp p instruction is executed. this instruction is valid only for the tabp p instruction. sets referring data area to pages 64 to 127 when the tabp p instruction is executed. this instruction is valid only for the tabp p instruction. validates the voltage drop detection circuit at power down (clock operating mode and ram back-up mode) when vdce pin is h .
rev.2.00 jul 27, 2004 page 148 of 159 rej03b0091-0200z 4524 group instruction code table d 3 d 0 hex. notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 a b c d e f d 9 d 4 00 nop pof snzp di ei rc sc pof2 am amc tya tba 000001 01 bla cld iny rd sd dey and or teab cma rar tab tay 000010 02 szb 0 szb 1 szb 2 szb 3 szd sean seam tda tabe szc 000011 03 bmla snz0 snz1 snzi0 snzi1 tv2a tv1a 000100 04 rbk** sbk** rt rts rti lz 0 lz 1 lz 2 lz 3 rb 0 rb 1 rb 2 rb 3 000101 05 tasp tad tax taz tav1 tav2 epof sb 0 sb 1 sb 2 sb 3 000110 06 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 000111 07 la 0 la 1 la 2 la 3 la 4 la 5 la 6 la 7 la 8 la 9 la 10 la 11 la 12 la 13 la 14 la 15 001000 08 tabp 0 tabp 1 tabp 2 tabp 3 tabp 4 tabp 5 tabp 6 tabp 7 tabp 8 tabp 9 tabp 10 tabp 11 tabp 12 tabp 13 tabp 14 tabp 15 001001 09 tabp 16 tabp 17 tabp 18 tabp 19 tabp 20 tabp 21 tabp 22 tabp 23 tabp 24 tabp 25 tabp 26 tabp 27 tabp 28 tabp 29 tabp 30 tabp 31 001010 tabp 32* tabp 33* tabp 34* tabp 35* tabp 36* tabp 37* tabp 38* tabp 39* tabp 40* tabp 41* tabp 42* tabp 43* tabp 44* tabp 45* tabp 46* tabp 47* 001011 001100 0c 001101 0d 001110 0e 001111 0f bml bml bml bml bml bml bml bml bml bml bml bml bml bml bml bml bml bml bml bml bml bml bml bml bml bml bml bml bml bml bml bml bl bl bl bl bl bl bl bl bl bl bl bl bl bl bl bl bl bl bl bl bl bl bl bl bl bl bl bl bl bl bl bl bm bm bm bm bm bm bm bm bm bm bm bm bm bm bm bm 010000 010111 011000 011111 18 1f b b b b b b b b b b b b b b b b bl bml bla bmla sea szd the second word 1p paaa aaaa 1p paaa aaaa 1p pp00 pppp 1p pp00 pppp 00 0111 nnnn 00 0010 1011 ** (sbk and rbk instructions) cannot be used in the m34524m8. * cannot be used after the sbk instruction is executed in the m34524mc. a page referred by the tabp instruction can be switched by the sbk and rbk instructions in the m34524mc/ed. the pages which can be referred by the tabp instruction after the sbk instruction is executed are 64 to 95 in the m34524mc. the pages which can be referred by the tabp instruction after the sbk instruction is executed are 64 to 127 in the m34524ed. (ex. tabp 0 the pages which can be referred by the tabp instruction after the rbk instruction is executed are 0 to 63. when the sbk instruction is not used, the pages which can be referred by the tabp instruction are 0 to 63. 10 17 000000 the above table shows the relationship between machine language codes and machine language instructions. d 3 d 0 show the low-order 4 bits of the machine language code, and d 9 d 4 show the high-order 6 bits of the machine language code. the hexadecimal representa- tion of the code is also provided. there are one-word instructions and two-word instructions, but only the first word of each i nstruction is shown. do not use code marked . the codes for the second word of a two-word instruction are described below. 0a tabp 48* tabp 49* tabp 50* tabp 51* tabp 52* tabp 53* tabp 54* tabp 55* tabp 56* tabp 57* tabp 58* tabp 59* tabp 60* tabp 61* tabp 62* tabp 63* 0b
rev.2.00 jul 27, 2004 page 149 of 159 rej03b0091-0200z 4524 group instruction code table (continued) tj1a tq1a tq2a tq3a tl1a tl2a tlca tw1a tw2a tw3a tw4a tw5a tw6a tk1a tk2a tmra ti1a ti2a ti3a tk0a t1ab t2ab t3ab t4ab tpsab t4hab tsiab tadab tr3ab tr1ab taj1 taq1 taq2 taq3 tala tal1 taw1 taw2 taw3 taw4 taw5 taw6 tamr tai1 tai2 tai3 tak0 tapu0 tak1 tak2 tapu1 iap0 iap1 iap2 iap3 iap4 tab1 tab2 tab3 tab4 tabps tabsi tabad snzt1 snzt2 snzt3 snzt4 snzt5 snzad snzsi rcp scp svde t4r4l cmck crck dwdt sst adst wrst tpaa tam 0 tam 1 tam 2 tam 3 tam 4 tam 5 tam 6 tam 7 tam 8 tam 9 tam 10 tam 11 tam 12 tam 13 tam 14 tam 15 xam 0 xam 1 xam 2 xam 3 xam 4 xam 5 xam 6 xam 7 xam 8 xam 9 xam 10 xam 11 xam 12 xam 13 xam 14 xam 15 xami 0 xami 1 xami 2 xami 3 xami 4 xami 5 xami 6 xami 7 xami 8 xami 9 xami 10 xami 11 xami 12 xami 13 xami 14 xami 15 xamd 0 xamd 1 xamd 2 xamd 3 xamd 4 xamd 5 xamd 6 xamd 7 xamd 8 xamd 9 xamd 10 xamd 11 xamd 12 xamd 13 xamd 14 xamd 15 lxy lxy lxy lxy lxy lxy lxy lxy lxy lxy lxy lxy lxy lxy lxy lxy tma 0 tma 1 tma 2 tma 3 tma 4 tma 5 tma 6 tma 7 tma 8 tma 9 tma 10 tma 11 tma 12 tma 13 tma 14 tma 15 bl bml bla bmla sea szd the second word 1p paaa aaaa 1p paaa aaaa 1p pp00 pppp 1p pp00 pppp 00 0111 nnnn 00 0010 1011 op0a op1a op2a op3a op4a tfr0a tfr1a tfr2a tfr3a tpu0a tpu1a d 3 d 0 hex. notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 a b c d e f d 9 d 4 20 100001 21 100010 22 100011 23 100100 24 100101 25 100110 26 100111 27 101000 28 101001 29 101010 2a 101011 2b 101100 2c 101101 2d 101110 2e 101111 2f 110000 111111 30 3f 100000 the above table shows the relationship between machine language codes and machine language instructions. d 3 d 0 show the low- order 4 bits of the machine language code, and d 9 d 4 show the high-order 6 bits of the machine language code. the hexadecimal representation of the code is also provided. there are one-word instructions and two-word instructions, but only the first word of each instruction is shown. do not use code marked . the codes for the second word of a two-word instruction are described below.
rev.2.00 jul 27, 2004 page 150 of 159 rej03b0091-0200z 4524 group parameter supply voltage input voltage p0, p1, p2, p3, p4, d 0 d 7 , reset, x in , x cin , vdce input voltage s ck , s in , cntr0, cntr1, int0, int1 input voltage a in0 a in7 output voltage p0, p1, p2, p3, p4, d 0 d 9 , reset, s ck , s out , cntr0, cntr1 output voltage c, x out , x cout output voltage seg 0 seg 19 , com 0 com 3 power dissipation operating temperature range storage temperature range conditions output transistors in cut-off state ta = 25 c symbol v dd v i v i v i v o v o v o p d topr tstg unit v v v v v v v mw c c ratings 0.3 to 6.5 0.3 to v dd +0.3 0.3 to v dd +0.3 0.3 to v dd +0.3 0.3 to v dd +0.3 0.3 to v dd +0.3 0.3 to v dd +0.3 300 20 to 85 40 to 125 absolute maximum ratings
rev.2.00 jul 27, 2004 page 151 of 159 rej03b0091-0200z 4524 group recommended operating conditions 1 (mask rom version: ta = 20 c to 85 c, v dd = 2 to 5.5 v, unless otherwise noted) (one time prom version: ta = 20 c to 85 c, v dd = 2.5 to 5.5 v, unless otherwise noted) symbol v dd v dd v ram v ss v lc3 v ih v ih v ih v ih v il v il v il v il i oh (peak) i oh (peak) i oh (avg) i oh (avg) i ol (peak) i ol (peak) i ol (peak) i ol (avg) i ol (avg) i ol (avg) h level input voltage h level input voltage h level input voltage h level input voltage l level input voltage l level input voltage l level input voltage l level input voltage h level peak output current h level peak output current h level average output current (note 2) h level average output current (note 2) l level peak output current l level peak output current l level peak output current l level average output current (note 2) l level average output current (note 2) l level average output current (note 2) h level total average current l level total average current notes 1: at 1/2 bias: vlc1 = vlc2 = (1/2) vlc3 at 1/3 bias: vlc1 = (1/3) vlc3, vlc2 = (2/3) vlc3 2: the average output current is the average value during 100 ms. unit conditions mask rom version one time prom version f(stck) d 7 , vdce x in , x cin reset s ck , s in , cntr0, cntr1, int0, int1 p0, p1, p2, p3, p4, d 0 d 7 , vdce x in , x cin reset s ck , s in , cntr0, cntr1, int0, int1 p0, p1, p4, d 0 d 6 s ck , s out d 7 , c cntr0, cntr1 p0, p1, p4, d 0 d 6 s ck , s out d 7 , c cntr0, cntr1 p0, p1, p4 d 0 d 9 , c, s ck , s out , cntr0, cntr1 p2, p3, reset p0, p1, p4 d 0 d 9 , c, s ck , s out , cntr0, cntr1 p2, p3, reset p0, p1, d 0 d 6 , s ck , s out p4, d 7 , c, cntr0, cntr1 p0, p1, d 0 d 6 , s ck , s out p2, p3, p4, d 7 d 9 , c, reset , cntr0, cntr1 max. 5.5 5.5 5.5 5.5 5.5 5.5 5.5 v dd v dd v dd v dd v dd v dd 0.2v dd 0.3v dd 0.3v dd 0.15v dd 20 10 30 15 10 5 20 10 24 12 24 12 10 4 12 6 15 7 5 2 60 60 80 80 limits min. 4 2.7 2 4 2.7 2.5 2.7 1.8 2 2.5 0.8v dd 0.7v dd 0.85v dd 0.8v dd 0 0 0 0 typ. 0 f(stck)
rev.2.00 jul 27, 2004 page 152 of 159 rej03b0091-0200z 4524 group f(x in ) f(x in ) f(x in ) f(x cin ) f(cntr) tw(cntr) f(s ck ) tw(s ck ) tpon oscillation frequency (with a ceramic resonator) oscillation frequency (at rc oscillation) (note) oscillation frequency (with a ceramic resonator selected, external clock input) oscillation frequency (sub-clock) timer external input frequency timer external input period ( h and l pulse width) serial i/o external input frequency serial i/o external input frequency ( h and l pulse width) power-on reset circuit valid supply voltage rising time conditions mhz mhz mhz khz hz s hz s ? ? ? 20 c to 85 c, v dd = 2 to 5.5 v, unless otherwise noted) (one time prom version: ta = 20 c to 85 c, v dd = 2.5 to 5.5 v, unless otherwise noted)
rev.2.00 jul 27, 2004 page 153 of 159 rej03b0091-0200z 4524 group v oh v oh v ol v ol v ol i ih i il h level output voltage p0, p1, p4, d 0 d 6 , s ck , s out h level output voltage d 7 , c, cntr0, cntr1 l level output voltage p0, p1, p4 l level output voltage d 0 d 9 , c, s ck , s out , cntr0, cntr1 l level output voltage p2, p3, reset h level input current p0, p1, p2, p3, p4, d 0 d 7 , vdce, reset, cntr0, cntr1, int0, int1 l level input current p0, p1, p2, p3, p4, d 0 d 7 , vdce, s ck , s in , cntr0, cntr1, int0, int1 v v v v v 1 i oh = 10 ma i oh = 3 ma i oh = 5 ma i oh = 1 ma i oh = 20 ma i oh = 6 ma i oh = 10 ma i oh = 3 ma i ol = 12 ma i ol = 4 ma i ol = 6 ma i ol = 2 ma i ol = 15 ma i ol = 5 ma i ol = 9 ma i ol = 3 ma i ol = 5 ma i ol = 1 ma i ol = 2 ma min. 3 4.1 2.1 2.4 3 4.1 2.1 2.4 typ. symbol parameter unit electrical characteristics 1 (mask rom version: ta = 20 c to 85 c, v dd = 2 to 5.5 v, unless otherwise noted) (one time prom version: ta = 20 c to 85 c, v dd = 2.5 to 5.5 v, unless otherwise noted)
rev.2.00 jul 27, 2004 page 154 of 159 rej03b0091-0200z 4524 group electrical characteristics 2 (mask rom version: ta = 20 c to 85 c, v dd = 2 to 5.5 v, unless otherwise noted) (one time prom version: ta = 20 c to 85 c, v dd = 2.5 to 5.5 v, unless otherwise noted) i dd r pu v t+ v t v t+ v t f(ring) ? ? ? ? ? c v dd = 5 v v dd = 3 v v i = 0 v v dd = 5 v v dd = 3 v v dd = 5 v v dd = 3 v v dd = 5 v v dd = 3 v v dd = 5 v ?10 %, ta = 25 c v dd = 5 v ?10 %, ta = 25 c v dd = 5 v v dd = 3 v v dd = 5 v v dd = 3 v when dividing resistor 2r ? ? ? ?
rev.2.00 jul 27, 2004 page 155 of 159 rej03b0091-0200z 4524 group symbol v dd v ia f(x in ) parameter supply voltage analog input voltage oscillation frequency a/d converter characteristics (ta = 20 c to 85 c, unless otherwise noted) conditions unit v v mhz ta = 25 c ta = 20 to 85 c v dd = 2.7 to 5.5 v min. 2.7 3 0 0.8 0.4 0.2 0.1 typ. max. 5.5 5.5 v dd limits symbol v 0t v fst ia dd t conv parameter resolution linearity error differential non-linearity error zero transition voltage full-scale transition voltage a/d operating current (note 1) a/d conversion time comparator resolution comparator error (note 2) comparator comparison time test conditions unit ta = 25 c, v dd = 2.7 v to 5.5 v ta = 20 c to 85 c, v dd = 3 v to 5.5 v ta = 25 c, v dd = 2.7 v to 5.5 v ta = 20 c to 85 c, v dd = 3 v to 5.5 v v dd = 5.12 v v dd = 3.072 v v dd = 5.12 v v dd = 3.072 v v dd = 5 v v dd = 3 v f(x in ) = 6 mhz v dd = 5.12 v v dd = 3.072 v f(x in ) = 6 mhz min. 0 0 5110 3063 typ. 10 6 5120 3069 0.3 0.1 max. 10 ? ?.9 20 12 5130 3075 0.9 0.3 248 124 62 31 8 ?0 ?5 32 16 8 4 limits notes 1: when the a/d converter is used, ia dd is added to i dd (supply current). 2: as for the error from the ideal value in the comparator mode, when the contents of the comparator register is n, the logic v alue of the comparison voltage v ref which is generated by the built-in da converter can be obtained by the following formula. logic value of comparison voltage v ref v ref = ? 20 c to 85 c, unless otherwise noted)
rev.2.00 jul 27, 2004 page 156 of 159 rej03b0091-0200z 4524 group test conditions ta = 25 c at power down v dd = 5 v (note 2) v dd = 3 v v dd 0.1 v) (note 3) parameter detection voltage (note 1) operation current detection time symbol v rst i rst t rst limits unit min. 3.3 2.7 typ. 3.5 50 30 0.2 max. 3.7 4.2 100 60 1.2 v 0.1 v]. stck p a r a m e t e r p i n ( s i g n a l ) n a m e m a c h i n e c y c l e m im i + 1 d 0 d 9 system clock port d output p o r t d i n p u t p o r t s p 0 , p 1 , p 2 , p 3 , p 4 o u t p u t p o r t s p 0 , p 1 , p 2 , p 3 , p 4 i n p u t d 0 d 7 i n t 0 , i n t 1 i n t e r r u p t i n p u t p 0 0 p 0 3 p1 0 p1 3 p 0 0 p 0 3 p 1 0 p 1 3 p2 0 p2 3 p 3 0 p 3 3 p 2 0 p 2 3 p 3 0 p 3 3 p 4 0 p 4 3 p 4 0 p 4 3 basic timing diagram voltage drop detection circuit characteristics (ta = 20 c to 85 c, unless otherwise noted)
rev.2.00 jul 27, 2004 page 157 of 159 rej03b0091-0200z 4524 group table 25 product of built-in prom version prom size ( ? ?
rev.2.00 jul 27, 2004 page 158 of 159 rej03b0091-0200z 4524 group (1) prom mode the built-in prom version has a prom mode in addition to a nor- mal operation mode. the prom mode is used to write to and read from the built-in prom. in the prom mode, the programming adapter can be used with a general-purpose prom programmer to write to or read from the built-in prom as if it were m5m27c256k. programming adapter is listed in table 26. contact addresses at the end of this data sheet for the appropriate prom programmer. writing and reading of built-in prom programming voltage is 12.5 v. write the program in the prom of the built-in prom version as shown in figure 76. (2) notes on handling ? ?
rev.2.00 jul 27, 2004 page 159 of 159 rej03b0091-0200z 4524 group package outline qfp64-p-1414-0.80 1.11 weight(g) jedec code eiaj package code lead material alloy 42 64p6n-a plastic 64pin 14 ? symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.2 0.1 0.5 i 2 1.3 m d 14.6 m e 14.6 10 0 0.1 1.4 0.8 0.6 0.4 17.1 16.8 16.5 17.1 16.8 16.5 0.8 14.2 14.0 13.8 14.2 14.0 13.8 0.2 0.15 0.13 0.45 0.35 0.3 2.8 0 3.05 e e e e c h e 1 64 49 32 48 33 17 16 h d d m d m e a f b a 1 a 2 l 1 l y b 2 i 2 recommended mount pad detail f
revision history rev. date description page summary 4524 group data sheet 1.00 oct. 11, 2001 1.10 nov. 07, 2001 2.00 jul. 27, 2004 first edition issued note; f(ring) f(ring) /8 table 4; (th second) external 0 interrupt external 1 interrupt (13); ?prescaler; reload register rps prescaler data (2); timer 2 count source selection bit timer lc count source selection bit (5); ?internal dividing registor; by setting bit 2 of register l1 to ? fig. 53; stabilizing time e ; high low, note 1; power down clock operating ? prescaler ; reload register rps prescaler data tak0, tk0a, tak1, tk1a, tak2, tk2a instructions revised rbk; flag cy; ?? sbk ( reset bank flag) sbk ( set bank flag) tab; grouping; other operations register to register transfer tal1 (transfer data to accumulator from register l a) tal1 (transfer data to accumulator from register l 1) tak0, tk0a, tak1, tk1a, tak2, tk2a instructions revised wrst, dwdt instructions revised words standardized: on-chip oscillator, a/d converter power dissipation revised. ____________ description of reset pin revised. table 6: notes added. fig.26 : note 9 added. some description revised. fig.31: ?i?instruction added. table 11:revised. (5) lcd power supply circuit revised. fig.51: state of quartz-crystal oscillator added. voltage drop detection circuit revised. table 21: port level revised and note 7 added. fig.55: ?note 5 added, ??5f?added to the transitions between from state e to states b, a, c and d ??ey-on wakeup ?akeup note on voltage drop detection circuit added. note on difference between mask rom version and one time prom version added. note on power source voltage added. condition of i ol (peak) and i ol (avg) revised. 6 22 40 57 61 69 75 90 102 104 111 116 145 147 all pages 4 5 24 34 44 45 46 61 65 66 67 69 78 151
keep safety first in your circuit designs! 1. renesas technology corp. puts the maximum effort into making semiconductor products better and more reliable, but there is a lways the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placeme nt of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas t echnology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents i nformation on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvement s or other reasons. it is therefore recommended that customers contact renesas technology corp. or an authorized renesas technology corp. product distrib utor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies o r errors. please also pay attention to information published by renesas technology corp. by various means, including the renesas techn ology corp. semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, a nd algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under ci rcumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerosp ace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corp. is necessary to reprint or reproduce in whole or in part these materi als. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a lic ense from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corp. for further details on these materials or the products contained therein. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500 fax: <1> (408) 382-7501 renesas technology europe limited. dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, united kingdom tel: <44> (1628) 585 100, fax: <44> (1628) 585 900 renesas technology europe gmbh dornacher str. 3, d-85622 feldkirchen, germany tel: <49> (89) 380 70 0, fax: <49> (89) 929 30 11 renesas technology hong kong ltd. 7/f., north tower, world finance centre, harbour city, canton road, hong kong tel: <852> 2265-6688, fax: <852> 2375-6836 renesas technology taiwan co., ltd. fl 10, #99, fu-hsing n. rd., taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology (shanghai) co., ltd. 26/f., ruijin building, no.205 maoming road (s), shanghai 200020, china tel: <86> (21) 6472-1001, fax: <86> (21) 6415-2952 renesas technology singapore pte. ltd. 1, harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas sales offices ?2001 , 2004 . re nesas tec hnology corp ., all rights reserved. printed in japan . colophon .1.0

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