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this is information on a product in full production. may 2012 doc id 18290 rev 2 1/18 18 ST2S08B dual synchronous rectification, 1.5 a, 1.5 mhz adjustable step-down switching regulator datasheet ? production data features step-down current mode pwm (1.5 mhz) dc- dc converter adjustable output voltage from 0.8 v 2 % dc output voltage tolerance synchronous rectification integrated current limit inhibit function soft-start for start delay of 800 s typ. typical efficiency: > 80 % at v out = 1.2 v 1.5 a output current capability non-switching quiescent current: max 1.5 ma over temperature range r ds(on) 150 m (typ.) uses tiny capacitors and inductors available in qfn12l (4 x 4 mm) description the ST2S08B is a dual step-down dc-dc converter optimized for powering low-voltage digital cores in odd applications and, generally, to replace the high current linear solution when the power dissipation may cause a high heating of the application environment. it provides up to 1.5 a over an input voltage range of 3 v to 5.5 v. a high switching frequency of 1.5 mhz allows the use of tiny surface-mounted components as well as a resistor divider to set the output voltage value. only an inductor and two capacitors are required. a low output ripple is guaranteed by the current mode pwm topology and the utilization of low esr smd ceramic capacitors. the device is thermally protected and current limited. the ST2S08B is available in the qfn12l (4 x 4 mm) package. qfn12l (4 x 4 mm) table 1. device summary order code package packaging ST2S08Bpqr qfn12l (4 x 4 mm) tape and reel www.st.com
contents ST2S08B 2/18 doc id 18290 rev 2 contents 1 diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 general information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8.2 programming the output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8.3 inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8.4 input and output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8.5 layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 9 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
ST2S08B diagram doc id 18290 rev 2 3/18 1 diagram * not available on the ST2S08B version. figure 1. schematic diagram 2ef #/.42/, ,/')# 3oft3tart '.$ 37 37
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pin configuration ST2S08B 4/18 doc id 18290 rev 2 2 pin configuration figure 2. pin connections (top view) table 2. pin description pin n name function 1 hv programing pin. it must be floating or connected to gnd. 2 fb2 feedback voltage 3 gnd2 power ground 4 sw2 switching pin 5 vin_sw power input voltage pin 6 sw1 switching pin 7 gnd1 power ground 8 fb1 feedback voltage/output voltage 9 nc not connect 10 inh inhibit pin: - high device on - low device off 11 vin_a supply for analog circuit 12 gnd_a system ground
ST2S08B maximum ratings doc id 18290 rev 2 5/18 3 maximum ratings note: absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. table 3. absolute maximum ratings symbol parameter value unit v in_sw positive power supply voltage -0.3 to 7 v v in_a positive power supply voltage -0.3 to 7 v v inh inhibit voltage -0.3 to 7 v switch voltage max. voltage of output pin -0.3 to 7 v v fb1,2 feedback voltage/output voltage -0.3 to 2.5 v current into v fb pin common mode input voltage +1 to -1 ma t j max junction temperature 150 c t stg storage temperature range -65 to +150 c t lead lead temperature (soldering) 10 sec. 300 c table 4. thermal data symbol parameter value unit r thjc thermal resistance junction-case 10 c/w r thja thermal resistance junction-ambient 60 c/w table 5. esd performance symbol parameter test conditions value unit esd esd protection voltage hbm-dh11c 4 kv
electrical characteristics ST2S08B 6/18 doc id 18290 rev 2 4 electrical characteristics v in_sw = v in_a = 5 v, v o1,2 =1.2 v, c 1 = 4.7 f, c 2 = c 3 = 22 f, l1 = l2 = 3.3 h, t j = -30 to 125 c, unless otherwise specified. typical values refer to 25 c. table 6. electrical characteristics symbol parameter test conditions min. typ. max. unit fb 1,2 feedback voltage 784 800 816 mv i fb1,2 v fb pin bias current v fb = 1 v 600 na i q quiescent current v inh > 1.2 v, v fb = 1 v 1.5 ma v inh = gnd 20 a i o1,2 output current v in = 3.0 to 5.5 v (1) , t j = - 30 to 85 c 1.5 a i min minimum output current 1 ma v inh inhibit threshold 3.0 v < v in < 5 v 1.2 v 3.0 v < v in < 5.5 v 1.3 device off 0.4 i inh1,2 inhibit pin current 2 a %v o1,2 / v in reference line regulation 3.0 v < v in < 5.5 v 0.04 %v o / v in v o1,2 reference load regulation 10 ma < i o < 1.5 a 10 mv pwm f s pwm switching frequency v fb = 0.7 v, t a = 25 c 1.2 1.5 1.8 mhz d max maximum duty cycle v fb = 0.7 v, t a = 25 c 85 94 % i swl switching current limitation (2) 2a i lkn nmos leakage current v fb = 0.9 v, t a = 25 c 0.1 a i lkp pmos leakage current v fb = 0.9 v, t a = 25 c 0.1 a r dson -n nmos switch on resistance i sw = 250 ma 0.15 0.3 r dson -p pmos switch on resistance i sw = 250 ma 0.2 0.4 efficiency i o = 20 ma to 100 ma 75 % i o = 100 ma to 1.5 a 80 % t shdn thermal shutdown 150 c t hys thermal shutdown hysteresis 15 c i sc - v in short-circuit v in range (2) output short-circuit to ground 3 5.3 v 1. v o = 90 % of nominal value. 2. guaranteed by design, but not tested in production.
ST2S08B typical application doc id 18290 rev 2 7/18 5 typical application note: r1, r2 and r3, r4 are calculated according to the following equations: - v o1 = v fb1 (1 + r1 / r2) - v o2 = v fb2 (1 + r3 / r4) figure 3. application circuit am07 8 70v1 22 f c2 v o1 l1 v in vin_a vin_ s w c1 4.7 f s w2 r 3 r4 c 3 22 f v o2 3 . 3 f 3 . 3 h l2 gnd2 r1 r2 nc gnd_a vfb2 vfb1 s w1 gnd1 inh s t2 s 0 8 b hv
typical performance characteristics ST2S08B 8/18 doc id 18290 rev 2 6 typical performance characteristics figure 4. feedback voltage vs. temperature figure 5. efficiency vs. output current 1 figure 6. efficiency vs. output current 2 figure 7. switching frequency vs. temperature figure 8. duty cycle vs. temperature figure 9. inhibit threshold vs. temperature 0.76 0.77 0.7 8 0.79 0. 8 0. 8 1 0. 8 2 0. 83 0. 8 4 -50 -25 0 25 50 75 100 125 v fb [v] temperature [ c] am07 883 v1 v in = 5 v, v f b 1 ,v f b 2 connected to v o1-2 , i o1 = i o2 = 10 ma am07 88 4v1 0 10 20 3 0 40 50 60 70 8 0 90 100 0 0.25 0.5 0.75 1 1.25 1.5 efficiency [%] output current 1 [a] v in = 5 v, v o1 = 1.2 v, v o2 no load am07 88 5v1 0 10 20 3 0 40 50 60 70 8 0 90 100 0 0.25 0.5 0.75 1 1.25 1.5 efficiency [%] output current 2 [a] v in = 5 v, v o2 = 3 . 3 v, v o1 no load am07 88 6v1 1.1 1.2 1. 3 1.4 1.5 1.6 1.7 1. 8 1.9 -50 -25 0 25 50 75 100 125 frequency [mhz] temperature [ c] v in = 5 v, v fb1 = v fb2 = 0.7 v am07 88 7v1 8 0 8 2 8 4 8 6 88 90 92 94 96 9 8 100 -50 -25 0 25 50 75 100 125 duty cycle [%] temperature [ c] v in = 5 v, v fb1 = v fb2 = 0.7 v am07 88 9v1 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 -50 -25 0 25 50 75 100 125 v inh (v) t [ c] on off v in = 5.5 v , i o1 =i o2 = 100 ma
ST2S08B typical performance characteristics doc id 18290 rev 2 9/18 figure 10. switching current limitation vs. temperature figure 11. load transient response v in = 5 v, i o1 from 250 ma to 1.5 a v o1 @ 1.2 v figure 12. inhibit transient v inh = from 0 v to 2 v, v in = 5.5 v, i o1 = i o2 = 1.5 a am07 888 v1 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 2.2 2.4 -50 -25 0 25 50 75 100 125 i s w2 [a] temperature [ c] v in = 5 v, o u tp u t1 m a xim u m lo a d c u rrent inh
general information ST2S08B 10/18 doc id 18290 rev 2 7 general information the ST2S08B is a dual adjustable current mode pwm step-down dc-dc converter. it is a complete 1.5 a switching regulator with internal compensation that eliminates the need for additional components. the constant frequency, current mode, pwm architecture and stable operation with ceramic capacitors, results in low, predictable output ripple. to clamp the error amplifier reference voltage, a soft-start control block, generating a voltage ramp, has been implemented. other circuits fitted to the device protection are the thermal shut-down block, which turns off the regulator when the junction temperature exceeds 150 c (typ.), and cycle-by-cycle switching current limiting. operation of the device requires few components: 2 inductors, 3 capacitors, and a resistor divider. the chosen inductor must be capable of not saturating at the peak current level. its value should be selected keeping in mind that a large inductor value increases the efficiency at low output current and reduces output voltage ripple, while a smaller inductor can be chosen when it is important to reduce package size and total application cost. finally, the st2s08 has been designed to work properly with x5r or x7r smd ceramic capacitors both at input and at output. these types of capacitors, due to their very low series resistance (esr), minimize the output voltage ripple. other low esr capacitors can be used, according to the needs of the application, without compromising the correct functioning of the device.
ST2S08B application information doc id 18290 rev 2 11/18 8 application information 8.1 introduction the following technical information is used for estimating typical external component characteristics using standard equations. nevertheless, it is strongly recommended to validate the suitability of external components to the application requirements by thoroughly testing any solution at bench level on a real evaluation circuit. 8.2 programming the output voltage the output voltage for both channels can be adjusted from 0.8 v up to 85 % of the input voltage value by connecting a resistor divider between v o and gnd, the middle point of the divider must be connected to the feedback (fb) pin, as shown in figure 3 . the resistor divider must be chosen according to the following equations: equation 1 equation 2 using a resistor with a value in the range of 1 k to 50 k is recommended . lower values are also suitable, but increase current consumption. 8.3 inductor selection the inductor is the key passive component for switching converters. the critical inductance values can then be obtained according to the following formulas: equation 3 f sw = switching frequency i l = the peak-to-peak inductor ripple current. as a rule of thumb, the peak-to-peak ripple can be set at 20 % - 40 % of the output current. the peak current of the inductor can be calculated as: ? ? ? ? ? ? ? ? + = 2 r 1 r 1 v v 1 fb 1 o ? ? ? ? ? ? ? ? + = 4 r 3 r 1 v v 2 fb 2 o l sw max _ in o max _ in o min i f v ) v v ( v l ? =
application information ST2S08B 12/18 doc id 18290 rev 2 equation 4 in addition to the inductance value, in order to avoid saturation, the maximum saturation current of the inductor must be higher than that of the i peak . 8.4 input and output capacitor selection it is recommended to use ceramic capacitors with x5r or x7r dielectric and low esr as input and output capacitors, in order to filter any disturbance present in the input line and to obtain stable operation. the output capacitor is very important for satisfying the output voltage ripple requirements. the output voltage ripple (v o_ripple ), in continuous mode, for the step-down channel, can be calculated as: equation 5 where i l is the ripple current and f sw is the switching frequency. the use of ceramic capacitors with voltage ratings in the range higher than 1.5 times the maximum input or output voltage is recommended. 8.5 layout considerations due to the high switching frequency and peak current, the layout is an important design step for all switching power supplies. important parameters (efficiency, output voltage ripple, switching noise immunity, etc.) can be affected if the pcb layout is not designed paying close attention to the following dc-dc general layout rules: short, wide traces must be implemented for mains current and for power ground paths. the input capacitor must be placed as close as possible to the ic pins as well as the inductor and output capacitor. the fb pin connection to the external resistor divider is a high impedance node, so interference can be minimized by placing the routing of the feedback node as far as possible from the high current paths. to reduce pick-up noise, the resistor divider must be placed very close to the device. a common ground node minimizes ground noise. the exposed pad of the package must be connected to the common ground node. moreover, the exposed pad ground connection must be properly designed in order to facilitate heat dissipation from the exposed pad to the ground layer using pcb vias. l f v 2 ) v v ( v ) 8 . 0 / i ( i sw max _ in o max _ in o o peak ? + = ? ? ? ? ? ? + = sw out l ripple _ o f c 8 1 esr i v
ST2S08B package mechanical data doc id 18290 rev 2 13/18 9 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions, and product status are available at: www.st.com . ecopack is an st registered trademark.
package mechanical data ST2S08B 14/18 doc id 18290 rev 2 dim. mm. inch. min. typ. max. min. typ. max. a0. 8 00. 9 0 1.00 0.0 3 1 0.0 3 5 0.0 39 a1 0.02 0.05 0.001 0.002 a 3 0.20 0.00 8 b 0.25 0. 3 00. 3 5 0.010 0.012 0.014 d 3 . 9 0 4.00 4.10 0.154 0.157 0.161 d2 2.00 2.15 2.25 0.07 9 0.0 8 5 0.0 89 e 3 . 9 0 4.00 4.10 0.154 0.157 0.161 e2 2.00 2.15 2.25 0.07 9 0.0 8 5 0.0 89 e0. 8 00.0 3 1 l 0.45 0.55 0.65 0.01 8 0.022 0.026 qfn12l (4x4) mechanical data 7 93 6 3 61b
ST2S08B package mechanical data doc id 18290 rev 2 15/18 dim. mm. inch. min. typ. max. min. typ. max. a 33 0 12. 99 2 c 12. 8 1 3 .2 0.504 0.51 9 d 20.2 0.7 9 5 n 99 101 3 . 898 3 . 9 76 t 14.4 0.567 ao 4. 3 5 0.171 bo 4. 3 5 0.171 ko 1.1 0.04 3 po 4 0.157 p 8 0. 3 15 tape & reel qfnxx/dfnxx (4x4) mechanical data
package mechanical data ST2S08B 16/18 doc id 18290 rev 2 figure 13. qfn12l (4 x 4 mm) footprint recommended data
ST2S08B revision history doc id 18290 rev 2 17/18 10 revision history table 7. document revision history date revision changes 30-nov-2010 1 initial release. 18-may-2012 2 modified max 1.0 ma ==> max 1.5 ma : features on page 1 .
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