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cy2dl15110 1:10 differential lvds fanout buffer with selectable clock input cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-69398 rev. *c revised march 12, 2012 1:10 differential lvds fanout buffer with selectable clock input features select one of two low-voltage differential signal (lvds) input pairs to distribute to 10 lvds output pairs 40-ps maximum output-to-output skew 600-ps maximum propagation delay 0.11-ps maximum additive rms phase jitter at 156.25 mhz (12-khz to 20-mhz offset) up to 1.5-ghz operation asynchronous output enable function 32-pin thin quad flat pack (tqfp) package 2.5-v or 3.3-v operating voltage [1] commercial and industrial operating temperature range functional description the cy2dl15110 is an ultra-low noise, low skew, low propagation delay 1:10 lvds fanou t buffer targeted to meet the requirements of high speed clock distribution applications. the cy2dl15110 can select between two separate lvds input clock pairs using the in_sel pin. the output enable function allows the outputs to be asynchronously driven to a high-impedance state. the device has a fully differential internal architecture that is optimized to achieve low additive jitter and low skew at operating frequencies of up to 1.5 ghz. v bb q0 q0# q1 q1# q2 q2# q3 q3# q4 q4# q5 q5# q6 q6# q8 q8# q9 q9# q7 q7# in0 in0# in1 in1# r p in_sel v dd v ss v dd r p v dd oe logic block diagram note 1. input ac-coupling capacitors are requir ed for voltage-translation applications.
cy2dl15110 document number: 001-69398 rev. *c page 2 of 13 contents pinouts .............................................................................. 3 pin definitions .................................................................. 3 absolute maximum ratings ............................................ 4 operating conditions ....................................................... 4 dc electrical specifications ............................................ 5 ac electrical specifications ............................................ 6 ordering information ........................................................ 9 ordering code definitions ........................................... 9 package dimension ........................................................ 10 acronyms ........................................................................ 11 document conventions ................................................. 11 units of measure ....................................................... 11 document history page ................................................. 12 sales, solutions, and legal information ...................... 13 worldwide sales and design s upport ......... .............. 13 products .................................................................... 13 psoc solutions ......................................................... 13
cy2dl15110 document number: 001-69398 rev. *c page 3 of 13 pinouts figure 1. pin diagram - cy2dl15110 1234567 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 nc in0 in0# v bb in1 in1# oe q3 q3# q4 q4# q5 q5# q6 q6# q2# q2 q1# q1 q0# q0 v dd v dd q7 q7# q8 q8# q9 q9# v ss in_sel cy2dl15110 v ss pin definitions pin no. pin name pin type description 1 nc no connection 2 in_sel input input clock select pin. low-volta ge complementary metal oxide semiconductor (lvcmos)/low-voltage transistor-transistor-logic (lvttl). when in_sel = low, the in0/in0# differential input pair is active when in_sel = high, the in1/in1# differential input pair is active 3 in0 input lvds input clock. active when in_sel = low 4 in0# input lvds complementary input clock. active when in_sel = low 5v bb output lvds reference voltage output 6 in1 input lvds input clock. active when in_sel = high 7 in1# input lvds complementary input clock. active when in_sel = high 8 oe input output enable. lvcmos/lvttl; when oe = low, q(0:9) and q(0:9)# outputs are disabled 9, 25 v ss power ground 10, 12, 14, 17, 19, 21, 23, 26, 28, 30 q(0:9)# output lvds complementary output clocks 11, 13, 15, 18, 20, 22, 24, 27, 29, 31 q(0:9) output lvds output clocks 16, 32 v dd power power supply
cy2dl15110 document number: 001-69398 rev. *c page 4 of 13 absolute maximum ratings parameter description condition min max unit v dd supply voltage nonfunctional ?0.5 4.6 v v in [2] input voltage, relative to v ss nonfunctional ?0.5 lesser of 4.0 or v dd + 0.4 v v out [2] dc output or i/o voltage, relative to v ss nonfunctional ?0.5 lesser of 4.0 or v dd + 0.4 v t s storage temperature nonfunctional ?55 150 c esd hbm electrostatic discharge (esd) protection (human body model) jedec std 22-a114-b 2000 ? v l u latch up meets or exceeds jedec spec jesd78b ic latch up test ul?94 flammability rating at 1/8 in. v?0 msl moisture sensitivity level 3 operating conditions parameter description condition min max unit v dd supply voltage 2.5-v supply 2.375 2.625 v 3.3-v supply 3.135 3.465 v t a ambient operating temperature commercial 0 70 c industrial ?40 85 c t pu power ramp time po wer-up time for v dd to reach minimum supply voltage (power ramp must be monotonic.) 0.05 500 ms t startup start up time time taken from v dd reaching 95% of its minimum supply voltage to the device being operational. 1?ms note 2. the voltage on any i/o pin cannot exceed the power pi n during power-up. power supply sequencing is not required.
cy2dl15110 document number: 001-69398 rev. *c page 5 of 13 dc electrical specifications (v dd = 3.3 v 5% or 2.5 v 5%; t a = 0 c to 70 c (commercial) or ?40 c to 85 c (industrial)) parameter description condition min max unit i dd operating supply current all lvds outputs terminated with 100 ? ? load [3, 4] ?125ma v ih1 input high voltage, lvds input clocks, in0, in0#, in1, and in1# ?v dd + 0.3 v v il1 input low voltage, lvds input clocks, in0, in0#, in1, and in1# ?0.3 ? v v ih2 input high voltage, in_sel and oe v dd = 3.3 v 2.0 v dd + 0.3 v v il2 input low voltage, in_sel and oe v dd = 3.3 v ?0.3 0.8 v v ih3 input high voltage, in_sel and oe v dd = 2.5 v 1.7 v dd + 0.3 v v il3 input low voltage, in_sel and oe v dd = 2.5 v ?0.3 0.7 v v id [5] input differential amplitude see figure 3 on page 7 0.4 0.8 v v icm input common mode voltage see figure 3 on page 7 0.5 v dd ? 0.2 v i ih input high current, all inputs input = v dd [6] ?150 ? a i il input low current, all inputs input = v ss [6] ?150 ? ? a v pp lvds differential output voltage peak to peak, single-ended v dd = 3.3 v or 2.5 v, r term = 100 ? between q and q# pairs [3, 7] 250 470 mv ? v ocm change in v ocm between complementary output states v dd = 3.3 v or 2.5 v, r term = 100 ? between q and q# pairs [3, 7] ?50mv v bb output reference voltage 0 to 150 ? a output current 1.125 1.375 v i oz output leakage current oe = v ss, v out = 0.75 v to 1.75 v ?15 15 ? a r p internal pull-up / pull-down resistance, lvcmos logic input in_sel pin has pull-down only oe pin has pull-up only 60 140 k ? c in input capacitance measured at 10 mhz per pin ? 3 pf notes 3. refer to figure 2 on page 7 . 4. i dd includes current that is dissipated exte rnally in the output termination resistors. 5. v id minimum of 400 mv is required to meet all output ac el ectrical specifications. the device is functional with v id minimum of greater than 200 mv. 6. positive current flows into the input pin, negative current flows out of the input pin. 7. refer to figure 4 on page 7 .
cy2dl15110 document number: 001-69398 rev. *c page 6 of 13 ac electrical specifications (v dd = 3.3 v 5% or 2.5 v 5%; t a = 0 c to 70 c (commercial) or ?40 c to 85 c (industrial)) parameter description condition min typ max unit f in input frequency dc ? 1.5 ghz f out output frequency f out = f in dc ? 1.5 ghz t pd [8] propagation delay input pair to output pair input rise/fall time < 1.5 ns (20% to 80%) ? ? 600 ps t odc [9] output duty cycle 50% duty cycle at input frequency range up to 1 ghz 48 ? 52 % t sk1 [10] output-to-output skew any output to any output, with same load conditions at dut ??40ps t sk1 d [10] device-to-device output skew any out put to any output between two or more devices. devi ces must have the same input and have the same output load. ??150ps pn add additive rms phase noise 156.25-mhz input rise/fall time < 150 ps (20% to 80%) v id > 400 mv offset = 1 khz ? ? ?120 dbc/hz offset = 10 khz ? ? ?135 dbc/hz offset = 100 khz ? ? ?135 dbc/hz offset = 1 mhz ? ? ?150 dbc/hz offset = 10 mhz ? ? ?154 dbc/hz offset = 20 mhz ? ? ?155 dbc/hz t jit [11] additive rms phase jitter (random) 156.25 mhz, 12 khz to 20 mhz offset; input rise/fall time < 150 ps (20% to 80%), v id > 400 mv ??0.11ps t r , t f [12] output rise/fall time, single-ended 50% duty cycle at input, 20% to 80% of full swing (v ol to v oh ) input rise/fall time < 1.5 ns (20% to 80%) measured at 1 ghz ??300ps notes 8. refer to figure 5 on page 7 . 9. refer to figure 6 on page 7 . 10. refer to figure 7 on page 8 . 11. refer to figure 8 on page 8 . 12. refer to figure 9 on page 8 .
cy2dl15110 document number: 001-69398 rev. *c page 7 of 13 figure 2. lvds output termination figure 3. input differential and common mode voltages figure 4. output differential and common mode voltages figure 5. input to any output pair propagation delay figure 6. output duty cycle q x # z = 50 100 buf q x z = 50 in v a v b in# v icm = (v a + v b )/2 v id q x v a v b v ocm = (v a + v b )/2 q x # v pp ? v ocm = | v ocm1 ?v ocm2 | in# in t pd q x # q x t pw t odc = t pw t period t period q x # q x
cy2dl15110 document number: 001-69398 rev. *c page 8 of 13 figure 7. output-to-output and device-to-d evice skew figure 8. rms phase jitter figure 9. output rise/fall time q x # q x q y # q y q z # q z t sk1 t sk1 d device 1 device 2 phase noise phase noise mark offset frequency f1 f2 a rea under the masked phase noise plot noise powe r rms jitter ? 20% 80% t r t f 20% 80% v pp q x # q x
cy2dl15110 document number: 001-69398 rev. *c page 9 of 13 ordering code definitions ordering information part number type production flow pb-free cy2dl15110azc 32-pin tqfp commercial, 0 c to 70 c cy2dl15110azct 32-pin tqfp tape and reel commercial, 0 c to 70 c cy2dl15110azi 32-pin tqfp industrial, ?40 c to 85 c CY2DL15110AZIT 32-pin tqfp tape and reel industrial, ?40 c to 85 c x = blank or t blank = tube; t = tape and reel temperature grade: x = c or i c = commercial; i = industrial package type: az = 32-pin tqfp (pb-free) number of differential output pairs base part number company id: cy = cypress cy t 2dl151 x 10 az
cy2dl15110 document number: 001-69398 rev. *c page 10 of 13 package dimension figure 10. 32-pin tqfp (7 7 1.0 mm) a3210 package outline, 51-85063 51-85063 *d
cy2dl15110 document number: 001-69398 rev. *c page 11 of 13 acronyms document conventions units of measure acronym description esd electrostatic discharge hbm human body model i/o input/output jedec joint electron devices engineering council lvds low-voltage differential signal lvcmos low-voltage complementary metal oxide semiconductor lvttl low-voltage transistor-transistor logic oe output enable rms root mean square tqfp thin quad flat pack symbol unit of measure c degree celsius dbc decibels relative to the carrier ghz gigahertz hz hertz i/o input/output khz kilohertz k ? kilohm a microampere ma milliampere mm millimeter ms millisecond mv millivolt mhz megahertz ns nanosecond ? ohm % percent pf picofarad ps picosecond vvolt wwatt
cy2dl15110 document number: 001-69398 rev. *c page 12 of 13 document history page document title: cy2dl15110, 1:10 differential lvds fanout buffer with selectable clock input document number: 001-69398 revision ecn orig. of change submission date description of change ** 3269680 cxq 06/02/2011 new datasheet. *a 3292902 cxq 06/27/2011 minor edits in logic block diagram (changed the oe resistor value from 100k to r p ). minor edits in figure 2 and figure 4 (replaced ?q? and ?q#? with ?q x ? and ?q x #?). deleted the notes ?refer to figure 2 .? and ?refer to figure 4 .? in page 7 and their references in figure 2 and figure 4 . *b 3357978 bash 09/07/2011 updated operating conditions (added a parameter t startup and its details). updated package dimension . *c 3548521 bash 03/12/2012 changed st atus from advance to final. post to external web.
document number: 001-69398 rev. *c revised march 12, 2012 page 13 of 13 all products and company names mentioned in this document may be the trademarks of their respective holders. cy2dl15110 ? cypress semiconductor corporation, 2011-2012. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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