View CDP1854A3_4842655.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

5-42 features ? two operating modes - mode 0 - functionally compatible with industry types such as the tr1602a and cdp6402 - mode 1 - interfaces directly with cdp1800-series microprocessors without additional components ? full or half duplex operation ? parity, framing and overrun error detection ? baud rate - dc to 200k bits/s at v dd . . . . . . . . . . . . . . . . . . . . 5v - dc to 400k bits/s at v dd . . . . . . . . . . . . . . . . . . . . 10v ? fully programmable with externally selectable word length (5-8 bits), parity inhibit, even/odd parity, and 1, 1-1/2, or 2 stop bits ? false start bit detection description the cdp1854a and cdp1854ac are silicon-gate cmos universal asynchronous receiver/transmitter (uart) cir- cuits. they are designed to provide the necessary formatting and control for interfacing between serial and parallel data. for example, these uarts can be used to interface between a peripheral or terminal with serial i/o ports and the 8-bit cdp1800-series microprocessor parallel data bus system. the cdp1854a is capable of full duplex operation, i.e., simultaneous conversion of serial input data to parallel out- put data and parallel input data to serial output data. the cdp1854a uart can be programmed to operate in one of two modes by using the mode control input. when the input is high (mode = 1), the cdp1854a is directly compati- ble with the cdp1800-series microprocessor system without additional interface circuitry. when the mode input is low (mode = 0), the device is functionally compatible with indus- try standard uarts such as the tr1602a and cdp6402. it is also pin compatible with these types, except that pin 2 is used for the mode control input. the cdp1854a and the cdp1854ac are functionally identi- cal. the cdp1854a has a recommended operating voltage range of 4v to 10.5v, and the cdp1854ac has a recom- mended operating voltage range of 4v to 6.5v. ordering information package temp. range 5v/200k baud 10v/400k baud pkg. no. pdip -40 o c to +85 o c cdp1854ace cdp1854ae e40.6 burn-in cdp1854acex cdp1854aex e40.6 plcc -40 o c to +85 o c cdp1854acq cdp1854aq n44.65 sbdip -40 o c to +85 o c cdp1854acd cdp1854ad d40.6 burn-in cdp1854acdx - d40.6 march 1997 cdp1854a, cdp1854ac programmable universal asynchronous receiver/transmitter (uart) file number 1193.2 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. http://www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999
5-43 pinouts 40 lead sbdip, pdip (mode 0) top view 40 lead sbdip, pdip (mode 1) top view 44 lead plcc (q suffix) top view 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 v dd mode (v ss ) v ss rrd r bus 7 r bus 6 r bus 5 r bus 4 r bus 3 r bus 2 r bus 1 r bus 0 pe fe oe sfd r clock d ar da sdi 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 t clock epe wls 1 wls 2 sbs pi crl t bus 7 t bus 6 t bus 5 t bus 4 t bus 3 t bus 2 t bus 1 t bus 0 sd0 tsre thrl thre mr 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 v dd mode (v dd ) v ss cs2 r bus 7 r bus 6 r bus 5 r bus 4 r bus 3 r bus 2 r bus 1 r bus 0 int fe pe/oe rsel r clock tpb d a sdi 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 t clock cts es ps1 nc cs3 rd/ wr t bus 7 t bus 6 t bus 5 t bus 4 t bus 3 t bus 2 t bus 1 t bus 0 sd0 r ts cs1 thre clear nc = no connect 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 1 2 3 4 5 6 20 21 22 23 24 25 26 19 18 7 8 9 10 11 12 13 14 15 16 17 r bus 6 r bus 5 r bus 4 r bus 3 r bus 2 nc r bus 1 r bus 0 pe( int) fe oe(pe/oe) pi (cs3) crl(rd/ wr) t bus 7 t bus 6 t bus 5 nc t bus 4 t bus 3 t bus 2 t bus 1 t bus 0 r bus 7 rrd ( cs2) v ss mode v dd nc t clock epe ( cts) wls1 ( es) wls2 ( psi) sbs (nc) sfd (rsel) r clock (tpb) d ar da( d a) sdi nc mr( clear) thre( thre) thrl(cs1) tsre( r ts) sd0 note: mode 0(mode 1) cdp1854a, cdp1854ac
5-44 block diagram mode input high (mode = 1) note: 1. user interconnect figure 1. mode 1 block diagram (cdp1800-series microprocessor compatible) select logic 23 4 35 cs1 cs2 cs3 int 13 int status register 22 14 15 thre fe pe/oe 19 d a control reg transmitter holding register transmitter bus (26 - 33) (see note 1) transmitter shift register parity gen three-state drivers receiver bus (5-12) (see note 1) (see note 1) mux transmitter timing & control 40 24 39 t clock r ts cts transmitter section receiver timing & control 38 37 17 es psi r clock receiver section receiver holding register shift register cdp1802 interface 34 18 16 rd/ wr tpb rsel 20 sdi 25 sdo 1, 2 = v dd 3 = v ss 21 = clear 36 = nc cdp1854a, cdp1854ac
5-45 absolute maximum ratings thermal information dc supply-voltage range, (v dd ) (voltages referenced to v ss terminal) cdp1854a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to +11v cdp1854ac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to +7v input voltage range, all inputs . . . . . . . . . . . . . .-0.5 to v dd + 0.5v dc input current, any one input . . . . . . . . . . . . . . . . . . . . . . . . . 10ma device dissipation per output transistor t a = full package-temperature range . . . . . . . . . . . . . . 100mw operating-temperature range (t a ) package type d . . . . . . . . . . . . . . . . . . . . . . . . . -55 o c to +125 o c package type e and q . . . . . . . . . . . . . . . . . . . . . -40 o c to +85 o c thermal resistance (typical, note 1) q ja ( o c/w) q jc ( o c/w) sbdip package . . . . . . . . . . . . . . . . . . 55 15 pdip package . . . . . . . . . . . . . . . . . . . 50 n/a plcc package . . . . . . . . . . . . . . . . . . 46 n/a maximum junction temperature plastic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150 o c ceramic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 o c maximum storage temperature range (t stg ) . . .-65 o c to +150 o c maximum lead temperature (soldering 10s): at distance 1/16 1/32 inch (1.59 0.79mm) . . . . . . . . . . +265 o c note: printed circuit board mount: 57mm x 57mm minimum area x 1.6mm thick g10 epoxy glass, or equivalent. caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not impli ed. note: 1. q ja is measured with the component mounted on an evaluation pc board in free air. static electrical speci?cations at t a = -40 o c to +85 o c, unless otherwise noted parameter conditions limits units v o (v) v in (v) v dd (v) cdp1854a cdp1854ac min (note 1) typ max min (note 1) typ max quiescent device current i dd - 0, 5 5 - 0.01 50 - 0.02 200 m a - 0, 10 10 - 1 200 - - - m a output low drive (sink) current (except pins 24 and 25) i ol 0.4 0, 5 5 1 2 - 1 2 - ma 0.5 0, 10 10 2 4 - - - - ma output high drive (source) current i oh 4.6 0, 5 5 -0.55 -1.1 - -0.55 -1.1 - ma 9.5 0, 10 10 -1.3 -2.6 - - - - ma output low drive (sink) current (pins 24 and 25) i ol 0.4 0, 5 5 1.6 3.5 - 1.6 3.5 - ma 0.5 0, 10 10 3.2 7 - - - - ma output voltage low-level (note 2) v ol - 0, 5 5 - 0 0.1 - 0 0.1 v - 0, 10 10 - 0 0.1 - - - v output voltage high-level (note 2) v oh - 0, 5 5 4.9 5 - 4.9 5 - v - 0, 10 10 9.9 10 - - - - v input low voltage v il 0.5, 4.5 - 5 - - 1.5 - - 1.5 v 0.5, 9.5 - 10 - - 3 - - - v input high voltage v ih 0.5, 4.5 - 5 3.5 - - 3.5 - - v 0.5, 9.5 - 10 7 - - - - - v input current i in - 0, 5 5 - - 1- - 1 m a - 0, 10 10 - - 2- - - m a cdp1854a, cdp1854ac
5-46 three-state output leakage current i out 0, 5 0, 5 5 - - 1- - 1 m a 0, 10 0, 10 10 - - 10 - - - m a operating current (note 3) i dd1 - 0, 5 5 - 1.5 - - 1.5 - ma - 0, 10 10 - 6 - - - - ma input capacitance c in - - - - 5 7.5 - 5 7.5 pf output capacitance c out - - - - 10 15 - 10 15 pf notes: 1. typical values are for t a = 25 o c. 2. i ol = i oh = 1 m a. 3. operating current is measured at 200khz or v dd = 5v and 400khz for v dd = 10v in a cdp1800-series microprocessor system, with open outputs. operating conditions at t a = full package-temperature range. for maximum reliability, operating conditions should be selected so that operation is always within the following ranges: parameter conditions limits units v dd (v) cdp1854a cdp1854ac min max min max dc operating voltage range - 4 10.5 4 6.5 v input voltage range - v ss v dd v ss v dd v baud rate (receive or transmit) 5 - 200 - 200 k bits/s 10 - 400 - - k bits/s static electrical speci?cations at t a = -40 o c to +85 o c, unless otherwise noted (continued) parameter conditions limits units v o (v) v in (v) v dd (v) cdp1854a cdp1854ac min (note 1) typ max min (note 1) typ max cdp1854a, cdp1854ac
5-47 functional de?nitions for cdp1854a terminals mode 1 cdp1800-series microprocessor compatible signal: function v dd : positive supply voltage. mode select (mode): a high-level voltage at this input selects cdp1800-series microprocessor mode operation. v ss : ground chip select 2 ( cs2): a low-level voltage at this input together with cs1 and cs3 selects the cdp1854a uart. receiver bus (r bus 7 - r bus 0): receiver parallel data outputs (may be externally connected to corresponding transmitter bus terminals). interr upt ( int): a low-level voltage at this output indicates the presence of one or more of the interrupt conditions listed in table 1. framlng error (fe): a high-level voltage at this output indicates that the received character has no valid stop bit, i.e., the bit following the parity bit (if programmed) is not a high-level voltage. this output is updated each time a character is transferred to the receiver holding register. parity error or overrun error (pe/oe): a high-level voltage at this output indicates that either the pe or oe bit in the status register has been set (see status register bit assignment, table 2). register select (rsel): this input is used to choose either the control/status registers (high input) or the transmitter/receiver data registers (low input) according to the truth table in table 3. receiver clock (rclock): clock input with a frequency 16 times the desired receiver shift rate. tpb: a positive input pulse used as a data load or reset strobe. d a t a a v ailable ( d a): a low-level voltage at this output indicates that an entire character has been received and transferred to the receiver holding register. serial data in (sdl): serial data received on this input line enters the receiver shift register at a point determined by the character length. a high-level input voltage must be present when data is not being received. clear ( clear): a low-level voltage at this input resets the interrupt flip- flop, receiver holding register, control register, and status register, and sets serial data out (sdo) high. transmltter holding register empty ( thre): a low-level voltage at this output indicates that the transmitter holding register has transferred its contents to the transmitter shift register and may be reloaded with a new character. chip select 1 (cs1): a high-level voltage at this input together with cs2 and cs3 selects the uart. req uest t o send ( r ts): this output signal tells the peripherai to get ready to receive data. clear t o send ( cts) is the response from the peripheral. r ts is set to a low-level voltage when data is latched in the transmitter holding register or tr is set high, and is reset high when both the transmitter holding register and transmitter shift register are empty and tr is low. seral data output (sdo): the contents of the transmitter shift register [start bit, data bits, parity bit, and stop bit(s)] are serially shifted out on this output. when no character is being transmitted, a high level is maintained. start of transmission is de?ned as the transition of the start bit from a high-level to a low-level output voltage. transmltter bus (t bus 0 - t bus 7): transmitter parallel data input. these may be externally connected to corresponding receiver bus terminals. rd/ wr: a low-level voltage at this input gates data from the transmitter bus to the transmitter holding register or the control regis- ter as chosen by register select. a high-level voltage gates data from the receiver holding register or the status regis- ter, as chosen by register select, to the receiver bus. chip select 3 (cs3): with high-level voltage at this input together with cs1 and cs2 selects the uart. peripheral st a tus interr upt ( psi): a high-to-low transition on this input line sets a bit in the status register and causes an interr upt ( int = low). external st a tus ( es): a low-level voltage at this input sets a bit in the status register. cdp1854a, cdp1854ac
5-48 clear t o send ( cts): when this input from peripheral is high, transfer of a character to the transmitter shift register and shifting of serial data out is inhibited. transmitter clock (tclock): clock input with a frequency 16 times the desired transmitter shift rate. table 1. interrupt set and reset conditions (note 1) set (int = low) reset (int = high) cause condition time da (receipt of data) read of data tpb leading edge thre (note 2) (ability to reload) read of status or write of character tpb leading edge thre tsre (transmitter done) read of status or write of character tpb leading edge psi (negative edge) read of status tpb trailing edge cts (positive edge when thre tsre) read of status tpb leading edge notes: 1. interrupts will occur only after the ie bit in the control register (see table 4) has been set. 2. thre will cause an interrupt only after the tr bit in the control register (see table 4) has been set. table 2. status register bit assignment bit 76543210 signal thre tsre psi es fe pe oe da also available at terminal ? polarity reversed at output terminal. 22 ? - - - 14 15 15 19 ? bit signal: function 0 data available (da): when set high, this bit indicates that an entire character has been received and transferred to the receiv er holding register. this signal is also available at term. 19 but with its polarity reversed. 1 overrun error (oe): when set high, this bit indicates that the data available bit was not reset before the next character was transferred to the receiver holding register. this signal ored with pe is output at term. 15. 2 parity error (pe): when set high, this bit indicates that the received parity bit does not compare to that programmed by the ev en parity enable (epe) control. this bit is updated each time a character is transferred to the receiver holding register. this si gnal ored with oe is output at term. 15. 3 framlng error (fe): when set high, this bit indicates that the received character has no valid stop bit, i.e., the bit followin g the parity bit (if programmed) is not a high-level voltage. this bit is updated each time a character is transferred to the receive r holding register. this signal is also available at term. 14. 4 external status (es): this bit is set high by a low-level input at term. 38 ( es). 5 peripheral status interrupt (psi): this bit is set high by a high-to-low voltage transition of term. 37 ( psi). the interrupt output (term. 13) is also asserted ( lnt = iow) when this bit is set. 6 transmltter shift register empty (tsre): when set high, this bit indicates that the transmitter shift register has complet- ed serial transmission of a full character including stop bit(s). it remains set until the start of transmission of the next ch aracter. 7 transmltter holding register empty (thre): when set high, this bit indicates that the transmitter holding register has transferred its contents to the transmitter shift register and may be reloaded with a new character. setting this bit also sets the thre output (term. 22) low and causes an interrupt ( lnt = low), if tr is high. cdp1854a, cdp1854ac
5-49 description of mode 1 operation cdp1800-series microprocessor compatible (mode input = v dd ) initialization and controls in the cdp1800-series microprocessor compatible mode, the cdp1854a is con?gured to receive commands and send status via the microprocessor data bus. the register connected to the transmitter bus or the receiver bus is determined by the rd/ wr and rsel inputs as follows: in this mode the cdp1854a is compatible with a bidirectional bus system. the receiver and transmitter buses are connected to the bus. cdp1800-series microprocessor i/o control output signals can be connected directly to the cdp1854a inputs as shown in figure 2. the clear input is pulsed, resetting the control, status, and receiver holding registers and setting serial data out (sdo) high. the control register is loaded from the transmitter bus in order to determine the operating con?guration for the uart. data is transferred from the transmitter bus inputs to the control register during tpb when the uart is selected (cs1 cs2 cs3 = 1) and the control register is designated (rsel = h, rd/ wr = l). the cdp1854a also has a status register which can be read onto the receiver bus (r bus 0 - r bus 7) in order to determine the status of the uart. some of these status bits are also available at separate terminals as indicated in table 2. transmitter operation before beginning to transmit, the transmlt request (tr) bit in the control register (see bit assignment, table 4) is set. loading the control register with tr = 1 (bit 7 = high) inhibits changing the other control bits. therefore two loads are required: one to format the uart, the second to set tr. when tr has been set, a transmltter holding reg- ister empty ( thre) interrupt will occur, signalling the microprocessor that the transmitter holding register is empty and may be loaded. setting tr also causes assertion of a low-level on the request to send ( r ts) output to the peripheral. it is not necessary to set tr for proper opera- tion for the uart. if desired, it can be used to enable thre interrupts and to generate the r ts signal. the transmitter holding register is loaded from the bus by tpb during exe- cution of an output instruction. the cdp1854a is selected by cs1 cs2 cs3 = 1, and the holding register is selected by rsel = l and rd/ wr = l. when the clear t o send ( cts) input, which can be connected to a periph- eral device output, goes low, the transmitter shift register will be loaded from the transmitter holding register and data transmission will begin. if cts is always low, the trans- mitter shift register will be loaded on the ?rst high-to-low edge of the clock which occurs at least 1/2 clock period after the trailing edge of tpb and transmission of a start bit will occur 1/2 clock period later (see figure 3). parity (if pro- grammed) and stop bit(s) will be transmitted following the last data bit. if the word length selected is less than 8 bits, the most signi?cant unused bits in the transmitter shift regis- ter will not be transmitted. one transmitter clock period after the transmitter shift reg- ister is loaded from the transmitter holding register, the thre signal will go low and an interrupt will occur ( int goes low). the next character to be transmitted can then be loaded into the transmitter holding register for transmission with its start bit immediately following the last stop bit of the previous character. this cycle can be repeated until the last character is transmitted, at which time a ?nal thre tsre interrupt will occur. this interrupt signals the microprocessor that tr can be turned off. this is done by reloading the orig- inal control byte in the control register with the tr bit 0, thus terminating the req uest t o send ( r ts) signal. serial data out (sdo) can be held low by setting the break bit in the control register (see table 4). sdo is held low until the break bit is reset. receiver operation the receive operation begins when a start bit is detected at the serlal data in (sdl) input. after detection of the ?rst high-to-low transition on the sdl line, a valid start bit is veri?ed by checking for a low-level input 7-1/2 receiver clock periods later. when a valid start bit has been veri?ed, the fol- lowing data bits, parity bit (if programmed) and stop bit(s) are shifted into the receiver shift register by clock pulse 7-1/2 table 3. register selection summary rsel rd/ wr function low low load transmitter holding register from transmitter bus low high read receiver holding register from receiver bus high low load control register from transmitter bus high high read status register from receiver bus figure 2. recommended cdp1800-series connection, mode 1 (non-interrupt driven system) n0 n1 n2 mrd tpb int ef x ef x ef x ef x bus clear (8) cpu rsel cs1 cs2 rd/ wr tpb int thre d a t bus cs3 t clock r clock r ts cts es psi sdo sdi mode clear v dd fe pe/oe r bus peripheral v ss v dd uart cdp1854a cdp1854a, cdp1854ac
5-50 in each bit time. the parity bit (if programmed) is checked and receipt of a valid stop bit is veri?ed. on count 7-1/2 of the ?rst stop bit, the received data is loaded into the receiver holding register. if the word length is less than 8 bits, zeros (low output level) are loaded into the unused most signi?cant bits. if data available (da) has not been reset by the time the receiver holding register is loaded, the overrun error (oe) status bit is set. one half clock period later, the parity error (pe) and framlng error (fe) status bits become valid for the character in the receiver holding register. at this time, the data available status bit is also set and the data available (da) and interrupt (int) outputs go low, signalling the microprocessor that a received character is ready. the microprocessor responds by executing an input instruction. the uarts three-state bus drivers are enabled when the uart is selected (cs1 cs2 cs3 = 1) and rd/ wr = high. status can be read when rsel = high. data is read when rsel = iow. when reading data, tpb latches data in the microprocessor and resets d a t a a v ailable ( d a) in the uart. the preceding sequence is repeated for each serial character which is received from the peripheral. peripheral interface in addition to serial data in and out, four signals are provided for communication with a peripheral. the req uest t o send ( r ts) output signal alerts the peripheral to get ready to receive data. the clear t o send ( cts) input signal is the response, signalling that the peripheral is ready. the external st a tus ( es) input latches a peripheral status level, and the peripheral st a tus interr upt ( psi) input senses a status edge (high-to-low) and also generates an interrupt. for example, the modem d a t a carrier detect line could be connected to the psi input on the uart in order to signal the microprocessor that transmission failed because of loss of the carrier on the communications line. the psi and es bits are stored in the status register (see table 2). table 4. control register bit assignment bit 76543210 signal tr break ie wls2 wls1 sbs epe pi bit signal: function 0 parity inhibit (pi): when set high parity generation and veri?cation are inhibited and the pe status bit is held low. if parity is inhibited the stop bit(s) will immediately follow the last data bit on transmission, and epe is ignored. 1 even parity enable (epe): when set high, even parity is generated by the transmitter and checked by the receiver. when low, odd parity is selected. 2 stop bit select (sbs): see table below. 3 word length select 1 (wls1): see table below. 4 word length select 2 (wls2): see table below. 5 interrupt enable (le): when set high thre, da, thre tsre, cts, and psi interrupts are enabled (see interrupt conditions, table 1). 6 transmlt break (break): holds sdo low when set. once the break bit in the control register has been set high, sdo will stay low until the break bit is reset low and one of the following occurs: clear goes low; cts goes high; or a word is transmitted. (the transmitted word will not be valid since there can be no start bit if sdo is already low. sdo can be set high without intermedi ate transitions by transmitting a word consisting of all zeros). 7 transmlt request (tr): when set high, r ts is set low and data transfer through the transmitter is initiated by the initial thre interrupt. (when loading the control register from the bus, this (tr) bit inhibits changing of other control ?ip-?ops). bit 4 wls2 bit 3 wls1 bit 2 sbs function 0 0 0 5 data bits, 1 stop bit 0 0 1 5 data bits, 1.5 stop bits 0 1 0 6 data bits, 1 stop bit 0 1 1 6 data bits, 2 stop bits 1 0 0 7 data bits, 1 stop bit 1 0 1 7 data bits, 2 stop bits 1 1 0 8 data bits, 1 stop bit 1 1 1 8 data bits, 2 stop bits cdp1854a, cdp1854ac
5-51 dynamic electrical speci?cations t a = -40 o c to +85 o c, v dd 5%, t r , t f = 20ns, v ih = 0.7 v dd , v il = 0.3 v dd , c l = 100pf, (see figure 3) parameter v dd (v) limits units cdp1854a cdp1854ac (note 1) typ (note 2) max (note 1) typ (note 2) max transmitter timing - mode 1 minimum clock period t cc 5 250 310 250 310 ns 10 125 155 - - ns minimum pulse width clock low level t cl 5 100 125 100 125 ns 10 75 100 - - ns clock high level t ch 5 100 125 100 125 ns 10 75 100 - - ns tpb t tt 5 100 150 100 150 ns 10 50 75 - - ns minimum setup time tpb to clock t tc 5 175 225 175 225 ns 10 90 150 - - ns propagation delay time clock to data start bit t cd 5 300 450 300 450 ns 10 150 225 - - ns tpb to thre t tth 5 200 300 200 300 ns 10 100 150 - - ns clock to thre t cth 5 200 300 200 300 ns 10 100 150 - - ns notes: 1. typical values for t a = 25 o c and nominal voltages. 2. maximum limits of minimum characteristics are the values above which all devices function. notes: 1. the holding register is loaded on the trailing edge of tpb. 2. the transmitter shift register is loaded on the first high-to-low transition of the clock which occurs at least 1/2 clock per iod + t tc after the trailing edge of tpb and transmission of a start bit occurs 1/2 clock period + t cd later. 3. write is the overlap of tpb, cs1, and cs3 = 1 and cs3, rd/ wr = 0. figure 3. transmitter timing diagram - mode 1 t clock thre write (tpb) sdo t cc t cl t ch 12 t tth t cd t cd 1st data bit transmitter shift register loaded (note 2) transmitter holding register loaded (note 1) 34567141516123 4 t tt (note 3) t cth t tc cdp1854a, cdp1854ac
5-52 dynamic electrical speci?cations t a = -40 o c to +85 o c, v dd 5%, t r , t f = 20ns, v ih = 0.7 v dd , v il = 0.3 v dd , c l = 100pf, (see figure 4) parameter v dd (v) limits units cdp1854a cdp1854ac (note 1) typ (note 2) max (note 1) typ (note 2) max receiver timing - mode 1 minimum clock period t cc 5 250 310 250 310 ns 10 125 155 - - ns minimum pulse width clock low level t cl 5 100 125 100 125 ns 10 75 100 - - ns clock high level t ch 5 100 125 100 125 ns 10 75 100 - - ns tpb t tt 5 100 150 100 150 ns 10 50 75 - - ns minimum setup time data start bit to clock t dc 5 100 150 100 150 ns 10 50 75 - - ns propagation delay time tpb to d a t a a v ailable t tda 5 220 325 220 325 ns 10 110 175 - - ns clock to d a t a a v ailable t cda 5 220 325 220 325 ns 10 110 175 - - ns clock to overrun error t coe 5 210 300 210 300 ns 10 105 150 - - ns clock to parity error t cpe 5 240 375 240 375 ns 10 120 175 - - ns clock to framing error t cfe 5 200 300 200 300 ns 10 100 150 - - ns notes: 1. typical values for t a = 25 o c and nominal voltages. 2. maximum limits of minimum characteristics are the values above which all devices function. cdp1854a, cdp1854ac
5-53 notes: 1. if a start bit occurs at a time less than t dc before a high-to-low transition of the clock, the start bit may not be recognized until the next high-to-low transition of the clock. the start bit may be completely asynchronous with the clock. 2. read is the overlap of cs1, cs3, rd/ wr = 1 and cs2 = 0. if a pending da has not been cleared by a read of the receiver holding register by the time a new word is loaded into the receiver holding register, the oe signal will come true. 3. oe and pe share terminal 15 and are also available as two separate bits in the status register. figure 4. mode 1 receiver timing diagram r clock read t cc t cl t ch t dc 12 start bit t tda clock 7 1/2 sample 3456716 (note 1) sdi 123456789 stop bit 1 clock 7 1/2 load holding register t cda t tt t coe t cpe t cfe oe pe (note 3) fe parity d a (note 2) tpb (note 3) note: 1. write is the overlap of tpb, cs1, cs3 = 1 and cs2, rd/ wr = 0. figure 5. mode 1 cpu interface (write) timing diagram t rsw t wrs t tt t wd t dw tpb (note 1) t bus 0- t bus 7 rd/ wr, cs2 (note 1) cs3, cs1 (note 1) rsel cdp1854a, cdp1854ac
5-54 dynamic electrical speci?cations t a = -40 o c to +85 o c, v dd 5%, t r , t f = 20ns, v ih = 0.7 v dd , v il = 0.3 v dd , c l = 100pf, (see figure 5) parameter v dd (v) limits units cdp1854a cdp1854ac (note 1) typ (note 2) max (note 1) typ (note 2) max cpu interface - write timing - mode 1 minimum pulse width tpb t tt 5 100 150 100 150 ns 10 50 75 - - ns minimum setup time rsel to write t rsw 5 50755075ns 10 25 40 - - ns data to write t dw 5 -30 0 -30 0 ns 10 -15 0 - - ns minimum hold time rsel after write t wrs 5 50755075ns 10 25 40 - - ns data after write t wd 5 75 125 75 125 ns 10 40 60 - - ns notes: 1. typical values for t a = 25 o c and nominal voltages. 2. maximum limits of minimum characteristics are the values above which all devices function. dynamic electrical speci?cations t a = -40 o c to +85 o c, v dd 5%, t r , t f = 20ns, v ih = 0.7 v dd , v il = 0.3 v dd , c l = 100pf, (see figure 6) parameter v dd (v) limits units cdp1854a cdp1854ac min (note 1) typ (note 2) max min (note 1) typ (note 2) max cpu interface - read timing - mode 1 minimum pulse width tpb t tt 5 - 100 150 - 100 150 ns 10 - 50 75 - - - ns minimum setup time rsel to tpb t rst 5 - 50 75 - 50 75 ns 10 - 25 40 - - - ns minimum hold time rsel after tpb t trs 5 - 50 75 - 50 75 ns 10 - 25 40 - - - ns read to data access time t rdda 5 - 200 300 - 200 300 ns 10 - 100 150 - - - ns read to data valid time t rdv 5 - 200 300 - 200 300 ns 10 - 100 150 - - - resel to data valid time t rsdv 5 - 150 225 - 150 225 ns 10 - 75 125 - - - ns hold time data after read t rdh 5 50 150 - 50 150 - ns 102575----ns notes: 1. typical values for t a = 25 o c and nominal voltages. 2. maximum limits of minimum characteristics are the values above which all devices function. cdp1854a, cdp1854ac
5-55 mode input low (mode = 0) note: 1. read is the overlap of cs1, cs3, rd/ wr = 1 and cs2 = 0. figure 6. mode 1 cpu interface (read) timing diagram t rst t trs t tt t rsdv tpb r bus 0- r bus 7 cs2 rd/ wr, cs1, cs3 (note 1) rsel t rdv t rdda t rdh figure 7. mode 0 block diagram (industry standard compatible) control register 26 t bus 0 transmitter holding register transmitter bus transmitter shift register parity gen receiver bus transmitter timing and control 40 t clock transmitter section receiver timing and control 17 receiver section receiver holding register 20 sdi 25 sdo 27 t bus 1 28 t bus 2 29 t bus 3 30 t bus 4 31 t bus 5 32 t bus 6 33 t bus 7 35 pi 36 sbs 39 epe 38 wls1 37 wls2 23 thrl crl sfd status register 22 thre 24 tsre 13 pe 14 fe 15 oe d ar r clock receiver shift register 19 da 5 r bus 7 three-state drivers 6 r bus 6 7 r bus 5 8 r bus 4 9 r bus 3 10 r bus 2 11 r bus 1 12 r bus 0 rrd 4 18 16 34 1 = v dd 2, 3 = v ss 21 = mr cdp1854a, cdp1854ac
5-56 functional de?nitions for cdp1854a terminals standard mode 0 signal: function v dd : positive supply voltage. mode select (mode): a low-level voltage at this input selects standard mode 0 operation. v ss : ground. receiver register disconnect (rrd): a high-level voltage applied to this input disconnects the receiver holding register from the receiver bus. receiver bus (r bus 7 - r bus 0): receiver parallel data outputs. parity error (pe): a high-level voltage at this output indicates that the received parity does not compare to that programmed by the even parity enable (epe) control. this output is updated each time a character is transferred to the receiver holding reg- ister. pe lines from a number of arrays can be bused together since an output disconnect capability is provided by the status flag disconnect (sfd) line. framing error (fe): a high-level voltage at this output indicates that the received character has no valid stop bit, i.e., the bit following the parity bit (if programmed) is not a high-level voltage. this output is updated each time a character is transferred to the receiver holding register. fe lines from a number of arrays can be bused together since an output disconnect capability is pro- vided by the status flag disconnect (sfd) line. overrun error (oe): a high-level voltage at this output indicates that the data available (da) ?ag was not reset before the next charac- ter was transferred to the receiver holding register. oe lines from a number of arrays can be bused together since an output disconnect capability is provided by the status flag disconnect (sfd) line. status flag disconnect (sfd): a high-level voltage applied to this input disables the three- state output drivers for pe, fe, oe, da, and thre, allowing these status outputs to be bus connected. receiver clock (rclock): clock input with a frequency 16 times the desired receiver shift rate. d a t a a v ailable reset ( d ar): a low-level voltage applied to this input resets the da ?ip- ?op. data available (da): a high-level voltage at this output indicates that an entire character has been received and transferred to the receiver holding register. serial data in (sdl): serial data received at this input enters the receiver shift register at a point determined by the character length. a high-level voltage must be present when data is not being received. master reset (mr): a high-level voltage at this input resets the receiver holding register, control register, and status register, and sets the serial data output high. transmltter holding register empty (thre): a high-level voltage at this output indicates that the transmit- ter holding register has transferred its contents to the transmitter shift register and may be reloaded with a new character. transmltter holding register lo ad ( thrl): a low-level voltage applied to this input enters the character on the bus into the transmitter holding register. data is latched on the trailing edge of this signal. transmltter shift register empty (tsre): a high-level voltage at this output indicates that the transmit- ter shift register has completed serial transmission of a full character including stop bit(s). it remains at this level until the start of transmission of the next character. serial data output (sdo): the contents of the transmitter shift register (start bit, data bits, parity bit, and stop bit(s)) are serially shifted out on this output. when no character is being transmitted, a high-level is maintained. start of transmission is de?ned as the transition of the start bit from a high-level to a low-level output voltage. transmltter bus (t bus 0 - t bus 7): transmitter parallel data inputs. control register load (crl): a high-level voltage at this input loads the control register with the control bits (pi, epe, sbs, wls1, wls2). this line may be strobed or hardwired to a high-level input voltage. parity inhibit (pi): a high-level voltage at this input inhibits the parity generation and veri?cation circuits and will clamp the pe output low. if parity is inhibited the stop bit(s) will immediately follow the last data bit on transmission. stop bit select (sbs): this input selects the number of stop bits to be transmitted after the parity bit. a high-level selects two stop bits, a low- level selects one stop bit. selection of two stop bits with ?ve data bits programmed selects 1.5 stop bits. cdp1854a, cdp1854ac
5-57 word length select 2 (wls2): word length select 1 (wls1): these two inputs select the character length (exclusive of parity) as follows: even parity enable (epe): a high-level voltage at this input selects even parity to be generated by the transmitter and checked by the receiver. a low-level input selects odd parity. transmitter clock (tclock): clock input with a frequency 16 times the desired transmitter shift rate. description of standard mode 0 operation (mode input = v ss ) initialization and controls the master reset (mr) input is pulsed, resetting the control, status, and receiver holding registers and setting the serlal data output (sdo) signal high. timing is generated from the clock inputs, transmitter clock (tclock) and receiver clock (rclock), at a frequency equal to 16 times the serial data bit rate. when the receiver data input rate and the transmitter data output rate are the same, the tclock and rclock inputs may be connected together. the control register load (crl) input is pulsed to store the control inputs parity inhibit (pi), even parity enable (epe), stop bit select (sbs), and word length selects (wls1 and wls2). these inputs may be hardwired to the proper voltage levels (v ss or v dd ) instead of being dynamically set and crl may be hardwired to v dd . the cdp1854a is then ready for transmitter and/or receiver operation. transmitter operation for the transmitter timing diagram refer to figure 10. at the beginning of a typical transmitting sequence the transmitter holding register is empty (thre is high). a character is transferred from the transmitter bus to the transmitter hold- ing register by applying a low pulse to the transmitter holding register lo ad ( thrl) input causing thre to go low. if the transmitter shift register is empty (tsre is high) and the clock is low, on the next high-to-low transition of the clock the character is loaded into the transmitter shift register preceded by a start bit. serial data transmission begins 1/2 clock period later with a start bit and 5-8 data bits followed by the parity bit (if programmed) and stop bit(s). the thre output signal goes high 1/2 clock period later on the high-to-low transition of the clock. when thre goes high, another character can be loaded into the transmitter holding register for transmission beginning with a start bit immedi- ately following the last stop bit of the previous character. this process is repeated until all characters have been transmit- ted. when transmission is complete, thre and transmitter shift register empty (tsre) will both be high. the format of serial data is shown in figure 12. duration of each serial out- put data bit is determined by the transmitter clock frequency ( f clock) and will be 16/f clock. receiver operation the receive operation begins when a start bit is detected at the serial data in (sdl) input. after the detection of a high-to-low transition on the sd line, a divide-by-16 counter is enabled and a valid start bit is veri?ed by checking for a low-level input 7-1/2 receiver clock periods later. when a valid start bit has been veri?ed, the following data bits, parity bit (if programmed), and stop bit(s) are shifted into the receiver shift register at clock pulse 7-1/2 in each bit time. if programmed, the parity bit is checked, and receipt of a valid stop bit is veri?ed. on count 7-1/2 of the ?rst stop bit, the received data is loaded into the receiver holding regis- ter. if the word length is less than 8 bits, zeros (low output voltage level) are loaded into the unused most signi?cant bits. if data available (da) has not been reset by the time the receiver holding register is loaded, the overrun error (oe) signal is raised. one-half clock period later, the parity error (pe) and framlng error (fe) sig- nals become valid for the character in the receiver holding register. the da signal is also raised at this time. the three- state output drivers for da, oe, pe and fe are enabled when status flag disconnect (sfd) is low. when receiver register disconnect (rrd) goes low, the receiver bus three-state output drivers are enabled and data is available at the receiver bus (r bus 0 - r bus 7) out- puts. applying a negative pulse to the d a t a a v ailable reset ( d ar) resets da. the preceding sequence of opera- tion is repeated for each serial character received. a receiver timing diagram is shown in figure 11. wls2 wls1 word length low low 5 bits low high 6 bits high low 7 bits high high 8 bits figure 8. mode 0 connection diagram tpa sci tpb n0 ef3 dmai bus clear (8) cpu d ar rrd thrl t bus t clock r clock epe sdo sdi mode v ss tsre da r bus mr wls2 wls1 sbs pi uart cdp1854a cdp1800 cdp1854a, cdp1854ac
5-58 dynamic electrical speci?cations t a = -40 o c to +85 o c, v dd 5%, t r , t f = 20ns, v ih = 0.7 v dd , v il = 0.3 v dd , c l = 100pf, (see figure 9) parameter v dd (v) limits units cdp1854a cdp1854ac (note 1) typ (note 2) max (note 1) typ (note 2) max interface timing - mode 0 minimum pulse width crl t crl 5 100 150 100 150 ns 10 50 75 - - ns mr t mr 5 200 400 200 400 ns 10 100 200 - - ns minimum setup time control word to crl t cwc 5 40804080ns 10 20 50 - - ns minimum hold time control word after crl t ccw 5 100 150 100 150 ns 10 50 75 - - ns propagation delay time sfd high to sod t sfdh 5 200 300 200 300 ns 10 100 150 - - ns sfd low to sod t sfdl 5 75 120 75 120 ns 10 40 60 - - ns rrd high to receiver register high impedance t rrdh 5 200 300 200 300 ns 10 100 150 - - ns rrd low to receiver register active t rrdl 5 100 150 100 150 ns 10 50 75 - - ns notes: 1. typical values for t a = 25 o c and nominal voltages. 2. maximum limits of minimum characteristics are the values above which all devices function. figure 9. mode 0 interface timing diagram t cwc control input word timing control word input crl status outputs sfd status output timing t crl t sfdh r bus 0 r bus 7 receiver register disconnect timing t rrdh rrd t rrdl t sfdl t ccw cdp1854a, cdp1854ac
5-59 dynamic electrical speci?cations t a = -40 o c to +85 o c, v dd 5%, t r , t f = 20ns, v ih = 0.7 v dd , v il = 0.3 v dd , c l = 100pf, (see figure 10) parameter v dd (v) limits units cdp1854a cdp1854ac (note 1) typ (note 2) max (note 1) typ (note 2) max transmitter timing - mode 0 minimum clock period t cc 5 250 310 250 310 ns 10 125 155 - - ns minimum pulse width clock low level t cl 5 100 125 100 125 ns 10 75 100 - - ns clock high level t ch 5 100 125 100 125 ns 10 75 100 - - ns thrl t thth 5 100 150 100 150 ns 10 50 75 - - ns minimum setup time thrl to clock t thc 5 175 275 175 275 ns 10 90 150 - - ns data to thrl t dt 5 20502050ns 10 0 40 - - ns minimum hold time data after thrl t td 5 80 120 80 120 ns 10 40 60 - - ns propagation delay time clock to data start bit t cd 5 300 450 300 450 ns 10 150 225 - - ns clock to thre t ct 5 200 300 200 300 ns 10 100 150 - - ns thrl to thre t tthr 5 200 300 200 300 ns 10 100 150 - - ns clock to tsre t tts 5 200 300 200 300 ns 10 100 150 - - ns notes: 1. typical values for t a = 25 o c and nominal voltages. 2. maximum limits of minimum characteristics are the values above which all devices function. cdp1854a, cdp1854ac
5-60 dynamic electrical speci?cations t a = -40 o c to +85 o c, v dd 5%, t r , t f = 20ns, v ih = 0.7 v dd , v il = 0.3 v dd , c l = 100pf, (see figure 11) parameter v dd (v) limits units cdp1854a cdp1854ac (note 1) typ (note 2) max (note 1) typ (note 2) max receiver timing - mode 0 minimum clock period t cc 5 250 310 250 310 ns 10 125 155 - - ns minimum pulse width clock low level t cl 5 100 125 100 125 ns 10 75 100 - - ns clock high level t ch 5 100 125 100 125 ns 10 75 100 - - ns d a t a a v ailable reset t dd 5 50755075ns 10 25 40 - - ns minimum setup time data start bit to clock t dc 5 100 150 100 150 ns 10 50 75 - - ns propagation delay time d a t a a v ailable reset to data available t dda 5 150 225 150 225 ns 10 75 125 - - ns clock to data valid t cdv 5 225 325 225 325 ns 10 110 175 - - ns clock to data available t cda 5 225 325 225 325 ns 10 110 175 - - ns clock to overrun error t coe 5 210 300 210 300 ns 10 100 150 - - ns clock to parity error t cpe 5 240 375 240 375 ns 10 120 175 - - ns clock to framing error t cfe 5 200 300 200 300 ns 10 100 150 - - ns notes: 1. typical values for t a = 25 o c and nominal voltages. 2. maximum limits of minimum characteristics are the values above which all devices function. cdp1854a, cdp1854ac
5-61 notes: 1. the holding register is loaded on the trailing edge of thrl. 2. the transmitter shift register, if empty, is loaded on the first high-to-low transition of the clock which occurs at least 1/ 2 clock period + t thc after the trailing edge of thrl and transmission of a start bit occurs 1/2 clock period + t cd later. figure 10. mode 0 transmitter timing diagram t clock thrl sdo thre tsre t bus 0 t bus 7 t cc t cl t ch t thc 12 t thth t cd t ct t tts t tthr t td t dt data t cd 1st data bit transmitter shift register loaded (note 2) transmitter holding register loaded (note 1) 34567141516123 notes: 1. if a start bit occurs at a time less than t dc before a high-to-low transition of the clock, the start bit may not be recognized until the next high-to-low transition of the clock. the start bit may be completely asynchronous with the clock. 2. if a pending da has not been cleared by a read of the receiver holding register by the time a new word is loaded into the rec eiver holding register, the oe signal will come true. figure 11. mode 0 receiver timing diagram r clock r bus 7 da d ar t cc t cl t ch t dc 12 start bit t dda t cdv clock 7 1/2 sample 3456716 (note 1) sdi 123456789 stop bit 1 clock 7 1/2 load holding register t cda t dd t coe t cpe t cfe r bus 0 - oe pe (note 2) fe parity figure 12. serial data word format next data word stop bits 1, 1-1/2 or 2 parity bit data msb 5 - 8 data bits data lsb start bit 16 / f clock cdp1854a, cdp1854ac
5-62 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/o r speci?cations at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of p atents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see web site http://www.intersil.com sales of?ce headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (407) 724-7000 fax: (407) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil (taiwan) ltd. taiwan limited 7f-6, no. 101 fu hsing north road taipei, taiwan republic of china tel: (886) 2 2716 9310 fax: (886) 2 2715 3029 cdp1854a, cdp1854ac

▲Up To Search▲

Price & Availability of CDP1854A3

	To Download CDP1854A3 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .