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| 9zx21201 idt ? 12-output differential z-buffer for pcie gen2/3 and qpi 1682b - 12/08/11 12-output differential z-buffer for pcie gen2/3 and qpi 1 general description the idt9zx21201 is a 12-output db1200z suitable for pci-express gen3 or qpi applications. the part is backwards compatible to pcie gen1 and gen2. a fixed external feedback maintains low drift for critical qpi applications. in bypass mode, the idt9zx21201 can provide outputs up to 150mhz. key specifications features/benefits ? space-saving 64-pin packages ? fixed feedback path/ 0ps input-to-output delay ? 9 selectable smbus addresses/mulitple devices can share the same smbus segment ? 12 oe# pins/hardware control of each output ? pll or bypass mode/pll can dejitter incoming clock ? 100mhz or 133mhz pll mode operation/supports pcie and qpi applications ? selectable pll bandwidth/minimizes jitter peaking in downstream pll's ? spread spectrum compatible/tracks spreading input clock for low emi ? software control of pll bandwidth and bypass settings/ pll can dejitter incoming clock (b rev only) functional block diagram datasheet recommended application 12-output pcie gen3/ qpi differential buffer for romley and newer platforms output features ? 12 - 0.7v differential hcsl output pairs logic dif(11:0) hibw_bypm_lobw# smbdat smbclk ckpwrgd/pd# smb_a0_tri smb_a1_tri 100m_133m# z-pll (ss compatible) dfb_out dif_in dif_in# oe(11:0)# iref note: even though the feedback is fixed, dfb_out still needs a termination network for the part to function. ? cycle-to-cycle jitter <50ps ? output-to-output skew < 65 ps ? input-to-output delay variation <50ps ? pcie gen3 phase jitter < 1.0ps rms ? qpi 9.6gt/s 12ui phase jitter < 0.2ps rms
idt ? 12-output differential z-buffer for pcie gen2/3 and qpi 1682b- 12/08/11 9zx21201 12-output differential z-buffer for pcie gen2/3 and qpi 2 pin configuration functionality at power up (pll mode) 100m_133m# dif_in ( mhz ) dif 1 100.00 dif_in 0 133.33 dif_in pll operating mode readback table hibw_bypm_lobw# byte0, bit 7 byte 0, bit 6 low (low bw) 0 0 mid (bypass) 0 1 high (high bw) 1 1 pll operating mode hibw_bypm_lobw# mode low pll lo bw mid bypass high pll hi bw note: pll is off in bypass mode tri-level input thresholds level voltage low <0.8v mid 1.2 idt ? 12-output differential z-buffer for pcie gen2/3 and qpi 1682b- 12/08/11 9zx21201 12-output differential z-buffer for pcie gen2/3 and qpi 3 pin description pin # pin name type description 1 vdda pwr 3.3v power for the pll core. 2 gnd a pwr grou nd pin fo r the pll core. 3 iref out this pin establishes the reference for the differential current-mode o utput pairs. it requires a fixed p recision resist or to ground. 4 75ohm is the standard va lue for 100ohm diffe rentia l impedance. othe r impedances require diff erent values. se e dat a sheet. 4 100m_133m # in 3.3v inpu t to select operat ing frequen cy see functionality table for definition 5 h ibw_bypm_lobw# in trilevel in put to select high bw, bypass or low bw mode. see pll operating mode table for details. 6 c kpwrgd_pd# in notifies device to samp le latched inputs and start up on first high assertion, or exit power down mode on subsequent assert ions. low enters power down mode. 7 gnd pwr grou nd pin. 8 vddr pwr 3.3v power f or dif ferential input clock (receiver). this vd d should be treated as an an alog powe r rail and filtered a pp ro p riatel y . 9 dif_in in 0.7 v differential true in p ut 10 dif_in# in 0.7 v differential com p lementar y in p ut 11 smb_a0_tri in smbus addre ss bit. this is a tri-level input that works in conjunction with the smb_a1 to decode 1 of 9 smbus addresses. 12 smbdat i/o data p in of smbus circuitr y, 5v tolerant 13 smbclk in clock p in of smbus circuitr y , 5v tolerant 14 smb_a1_tri in smbus addre ss bit. this is a tri-level input that works in conjunction with the smb_a0 to decode 1 of 9 smbus addresses. 15 dfb_out# out complementary half of differential feedback output, provides feedback signal to the pll for synchronization with in p ut clock to eliminate p hase error. 16 d fb_out out tru e half of differential feedback output, provides fee dback signal to the pll for synchronization with the input clock t o elimi nate p hase error. 17 dif_0 out 0.7v differential true clock output 18 dif_0# out 0.7v differential complementary clock output 19 voe0# in active low input for ena bling dif pair 0. 1 =disable out p uts, 0 = enable out p uts 20 voe1# in active low input for ena bling dif pair 1. 1 =disable out p uts, 0 = enable out p uts 21 dif_1 out 0.7v differential true clock output 22 dif_1# out 0.7v differential complementary clock output 23 gnd pwr grou nd pin. 24 vdd pwr power supply, nominal 3.3v 25 vdd pwr power supply, nominal 3.3v 26 dif_2 out 0.7v differential true clock output 27 dif_2# out 0.7v differential complementary clock output 28 voe2# in active low input for ena bling dif pair 2. 1 =disable outputs, 0 = enable outputs 29 voe3# in active low input for ena bling dif pair 3. 1 =disable outputs, 0 = enable outputs 30 dif_3 out 0.7v differential true clock output 31 dif_3# out 0.7v differential complementary clock output 32 vdd pwr power supply, nominal 3.3v idt ? 12-output differential z-buffer for pcie gen2/3 and qpi 1682b- 12/08/11 9zx21201 12-output differential z-buffer for pcie gen2/3 and qpi 4 pin description (continued) 33 gnd pwr ground pin. 34 dif_4 out 0.7v differential true clock output 35 dif_4# out 0.7v differential complementary clock output 36 voe4# in active low input for enabling dif pair 4 1 =disable outputs, 0 = enable outputs 37 voe5# in active low input for enabling dif pair 5. this pin has an internal pull-down 1 =disable outputs, 0 = enable outputs 38 dif_5 out 0.7v differential true clock output 39 dif_5# out 0.7v differential complementary clock output 40 vdd pwr power supply, nominal 3.3v 41 gnd pwr ground pin. 42 dif_6 out 0.7v differential true clock output 43 dif_6# out 0.7v differential complementary clock output 44 voe6# in active low input for enabling dif pair 6. this pin has an internal pull-down 1 =disable outputs, 0 = enable outputs 45 voe7# in active low input for enabling dif pair 7. this pin has an internal pull-down 1 =disable outputs, 0 = enable outputs 46 dif_7 out 0.7v differential true clock output 47 dif_7# out 0.7v differential complementary clock output 48 gnd pwr ground pin. 49 vdd pwr power supply, nominal 3.3v 50 dif_8 out 0.7v differential true clock output 51 dif_8# out 0.7v differential complementary clock output 52 voe8# in active low input for enabling dif pair 8. this pin has an internal pull-down 1 =disable outputs, 0 = enable outputs 53 voe9# in active low input for enabling dif pair 9. this pin has an internal pull-down 1 =disable outputs, 0 = enable outputs 54 dif_9 out 0.7v differential true clock output 55 dif_9# out 0.7v differential complementary clock output 56 vdd pwr power supply, nominal 3.3v 57 vdd pwr power supply, nominal 3.3v 58 gnd pwr ground pin. 59 dif_10 out 0.7v differential true clock output 60 dif_10# out 0.7v differential complementary clock output 61 voe10# in active low input for enabling dif pair 10. this pin has an internal pull-down 1 =disable outputs, 0 = enable outputs 62 voe11# in active low input for enabling dif pair 11. this pin has an internal pull-down 1 =disable outputs, 0 = enable outputs 63 dif_11 out 0.7v differential true clock output 64 dif_11# out 0.7v differential complementary clock output idt ? 12-output differential z-buffer for pcie gen2/3 and qpi 1682b- 12/08/11 9zx21201 12-output differential z-buffer for pcie gen2/3 and qpi 5 electrical characteristics - absolute maximum ratings parameter symbol conditions min typ max units notes 3.3v core supply voltage vdd, vdda vdd for core logic and pll 4.6 v 1,2 input low voltage v il gnd-0.5 v 1 input high voltage v ih except for smbus interface v d d +0.5v v 1 input high voltage v ihsmb smbus clock and data pins 5.5v v 1 storage temperature ts -65 150 c 1 junction temperature tj 125 c 1 input esd protection esd prot human body model 2000 v 1 1 guaranteed by design and characterization, not 100% tested in production. 2 operation under these conditions is neither implied nor guaranteed. electrical characteristics - input/supply/common parameters t a = t com ; supply voltage v dd/ v dda = 3.3 v +/-5% parameter symbol conditions min typ max units notes ambient operating temperature t com commmercial range 0 70 c 1 input high voltage v ih single-ended inputs, except smbus, low threshold and tri-level inputs 2v dd + 0.3 v 1 input low voltage v il single-ended inputs, except smbus, low threshold and tri-level inputs gnd - 0.3 0.8 v 1 i in single-ended inputs, v in = gnd, v in = vdd -5 5 ua 1 i inp single-ended inputs v in = 0 v; inputs with internal pull-up resistors v in = vdd; inputs with internal pull-down resistors -200 200 ua 1 f ib yp v dd = 3.3 v, bypass mode 33 150 mhz 2 f i p ll v dd = 3.3 v, 100mhz pll mode 90 100.00 110 mhz 2 f i p ll v dd = 3.3 v, 133.33mhz pll mode 120 133.33 147 mhz 2 pin inductance l p in 7nh1 c in logic inputs, except dif_in 1.5 5 pf 1 c i ndi f_i n dif_in differential clock inputs 1.5 2.7 pf 1,4 c out output pin capacitance 6 pf 1 clk stabilization t stab from v dd power-up and after input clock stabilization or de-assertion of pd# to 1st clock 0.300 1 ms 1,2 input ss modulation frequency f modi n allowable frequency (triangular modulation) 30 33 khz 1 oe# latency t latoe# dif start after oe# assertion dif stop after oe# deassertion 4 6 12 clocks 1 tdrive_pd# t drvpd dif output enable after pd# de-assertion 16 300 us 1,3 tfall t f fall time of control inputs 10 ns 1,2 trise t r rise time of control inputs 10 ns 1,2 smbus input low voltage v ilsmb 0.8 v 1 smbus input high voltage v ihsmb 2.1 v ddsmb v1 smbus output low voltage v olsmb @ i pullup 0.4 v 1 smbus sink current i pullup @ v ol 4ma1 nominal bus voltage v ddsmb 3v to 5v +/- 10% 2.7 5.5 v 1 sclk/sdata rise time t rsmb (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata fall time t fsmb (min vih + 0.15) to (max vil - 0.15) 300 ns 1 smbus operating frequency f maxsmb maximum smbus operating frequency 100 khz 1,5 1 guaranteed by design and characterization, not 100% tested in production. 2 control input must be monotonic from 20% to 80% of input swing. 5 the differential in p ut clock must be runnin g for the smbus to be active input current 3 time from deassertion until out p uts are >200 mv 4 dif_in input capacitance input frequency idt ? 12-output differential z-buffer for pcie gen2/3 and qpi 1682b- 12/08/11 9zx21201 12-output differential z-buffer for pcie gen2/3 and qpi 6 electrical characteristics - clock input parameters t a = t com ; supply voltage v dd/ v dda = 3.3 v +/-5% parameter symbol conditions min typ max units notes input high voltage - dif_in v ihdif differential inputs (single-ended measurement) 600 800 1150 mv 1 input low voltage - dif_in v ildif differential inputs (single-ended measurement) v ss - 300 0 300 mv 1 input common mode voltage - dif_in v com common mode input voltage 300 1000 mv 1 input amplitude - dif_in v swing peak to peak value 300 1450 mv 1 input slew rate - dif_in dv/dt measured differentially 0.4 8 v/ns 1,2 input leakage current i in v in = v dd , v in = gnd -5 5 ua 1 input duty cycle d tin measurement from differential wavefrom 45 55 % 1 input jitter - cycle to cycle j di fi n differential measurement 0 125 ps 1 1 guaranteed by design and characterization, not 100% tested in production. 2 slew rate measured through +/-75mv window centered around differential zero electrical characteristics - dif 0.7v current mode differential outputs t a = t com ; supply voltage v dd/ v dda = 3.3 v +/-5% parameter symbol conditions min typ max units notes slew rate trf scope averaging on 1 2 4 v/ns 1, 2, 3 slew rate matchin g trf slew rate matchin g , scope avera g in g on 8 20 % 1, 2, 4 voltage high vhigh 660 705 850 1 voltage low vlow -150 1 150 1 max voltage vmax 725 1150 1 min voltage vmin -300 -22 1 vswin g vswin g scope avera g in g off 300 1407 mv 1, 2 crossing voltage (abs) vcross_abs scope averaging off 250 309 550 mv 1, 5 crossing voltage (var) -vcross scope averaging off 22 140 mv 1, 6 2 measured from differential waveform 6 the total variation of all vcross measurements in any particular system. note that this is a subset of v_cross_min/max (v_cros s absolute) allowed. the intent is to limit vcross induced modulation by setting v_cross_delta to be smaller than v_cross absolut e. mv statistical measurement on single-ended signal using oscilloscope math function. (scope averaging on) measurement on single ended signal using absolute value. (scope averaging off) mv 1 guaranteed by design and characterization, not 100% tested in production. iref = vdd/(3xr r ). for r r = 412 ? (1%), i ref = 2.7ma. i oh = 6.4 x i ref and v oh = 0.7v @ z o =85 ? differential impedance. 3 slew rate is measured through the vswing voltage range centered around differential 0v. this results in a +/-150mv window arou nd differential 0v. 4 matching applies to rising edge rate of clock / falling edge rate of clock#. it is measured in a +/-75mv window centered on the average cross point where clock rising meets clock# falling. the median cross point is used to calculate the voltage thresholds the oscilloscope uses for the edge rate calculations. 5 vcross is defined as voltage where clock = clock# measured on a component test board and only applies to the differential risi ng edge (i.e. clock rising and clock# falling). electrical characteristics - current consumption t a = t com ; supply voltage v dd/ v dda = 3.3 v +/-5% parameter symbol conditions min typ max units notes i ddvdd 133mhz, c l = full load; vdd rail, zo=85 ? 260 275 ma 1 i ddvdda 133mhz, c l = full load; vdd rail, zo=85 ? 13 20 ma 1 i ddvddpd power down, vdd rail, zo=85 ? 2 6ma1 i ddvddapd power down, vdd rail, zo=85 ? 1.3 2ma1 1 guaranteed by design and characterization, not 100% tested in production. operating current powerdown current idt ? 12-output differential z-buffer for pcie gen2/3 and qpi 1682b- 12/08/11 9zx21201 12-output differential z-buffer for pcie gen2/3 and qpi 7 electrical characteristics - skew and differential jitter parameters t a = t com ; supply voltage v dd/ v dda = 3.3 v +/-5% parameter symbol conditions min typ max units notes clk_in, dif[x:0] t spo_pll input-to-output skew in pll mode nominal value @ 25c, 3.3v -100 29 100 ps 1,2,4,5,8 clk_in, dif[x:0] t pd_byp input-to-output skew in bypass mode nominal value @ 25c, 3.3v 2.5 3.7 4.5 ns 1,2,3,5,8 clk_in, dif[x:0] t dspo_pll input-to-output skew varation in pll mode across voltage and temperature -50 50 ps 1,2,3,5,8 clk_in, dif[x:0] t dspo_byp input-to-output skew varation in bypass mode across voltage and temperature -250 250 ps 1,2,3,5,8 clk_in, dif[x:0] t dte random differential tracking error beween two 9zx devices in hi bw mode 2.9 5 ps (rms) 1,2,3,5,8 clk_in, dif[x:0] t dsste random differential spread spectrum tracking error beween two 9zx devices in hi bw mode 14 75 ps 1,2,3,5,8 dif{x:0] t skew_all output-to-output skew across all outputs (common to bypass and pll mode) 32 65 ps 1,2,3,8 pll jitter peaking j p eak-hib w lobw#_bypass_hibw = 1 0 1.8 2.5 db 7,8 pll jitter peaking j peak-lob w lobw#_bypass_hibw = 0 0 0.7 2 db 7,8 pll bandwidth pll hi bw lobw#_bypass_hibw = 1 2 3.1 4 mhz 8,9 pll bandwidth pll lobw lobw#_bypass_hibw = 0 0.7 1.1 1.4 mhz 8,9 duty cycle t dc measured differentially, pll mode 45 49.6 55 % 1 duty cycle distortion t dcd measured differentially, bypass mode @100mhz -2 -0.2 2 % 1,10 pll mode 15.7 50 ps 1,11 additive jitter in bypass mode 0.1 50 ps 1,11 notes for preceding table: 6. t is the period of the input clock 7 measured as maximum pass band gain. at frequencies within the loop bw, highest point of magnification is called pll jitter pe aking. 8. guaranteed by design and characterization, not 100% tested in production. 9 measured at 3 db down or half power point. 10 duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in by pass mode. 11 measured from differential waveform 3 all b yp ass mode in p ut-to-out p ut s p ecs refer to the timin g between an in p ut ed g e and the s p ecific out p ut ed g e created b y it. 4 this p arameter is deterministic for a g iven device 5 measured with sco p e avera g in g on to find mean value. jitter, cycle to cycle t jcyc-cyc 1 measured into fixed 2 pf load cap. input to output skew is measured at the first output edge following the corresponding inp ut. 2 measured from differential cross- p oint to differential cross- p oint. this p arameter can be tuned with external feedback p ath, if p resent. idt ? 12-output differential z-buffer for pcie gen2/3 and qpi 1682b- 12/08/11 9zx21201 12-output differential z-buffer for pcie gen2/3 and qpi 8 power management table outputs ckpwrgd?/pd# dif_in/ dif_in# smbus en bit oe# pin dif(11:0)/ dif(11:0)# dfb_out/ dfb_out# 0xxx hi-z 1 hi-z 1 off 0x hi-z 1 running on 1 0 running running on 11 hi-z 1 running on note: 1. due to external pull down resistors, hi-z results in low/low on the true/complement outputs inputs pll state 1 running control bits/pins electrical characteristics - phase jitter parameters t a = t com ; supply voltage v dd/ v dda = 3.3 v +/-5% paramete r symbol conditions min typ max units notes t jp hpcieg1 pcie gen 1 32 86 ps (p-p) 1,2,3 pcie gen 2 lo band 10khz < f < 1.5mhz 0.8 3 ps (rms) 1,2 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 1.9 3.1 ps (rms) 1,2 t jphpcieg3 pcie gen 3 (pll bw of 2-4mhz, cdr = 10mhz) 0.45 1 ps (rms) 1,2,4 qpi & smi (100mhz or 133mhz, 4.8gb/s, 6.4gb/s 12ui) 0.20 0.5 ps (rms) 1,5 qpi & smi (100mhz, 8.0gb/s, 12ui) 0.14 0.3 ps (rms) 1,5 qpi & smi (100mhz, 9.6gb/s, 12ui) 0.12 0.2 ps (rms) 1,5 t jp hpcieg1 pcie gen 1 0.10 10 ps (p-p) 1,2,3 pcie gen 2 lo band 10khz < f < 1.5mhz 0.13 0.3 ps (rms) 1,2,6 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 0.10 0.7 ps (rms) 1,2,6 t jphpcieg3 pcie gen 3 (pll bw of 2-4mhz, cdr = 10mhz) 0.10 0.3 ps (rms) 1,2,4,6 qpi & smi (100mhz or 133mhz, 4.8gb/s, 6.4gb/s 12ui) 0.09 0.3 ps (rms) 1,5,6 qpi & smi (100mhz, 8.0gb/s, 12ui) 0.09 0.1 ps (rms) 1,5,6 qpi & smi (100mhz, 9.6gb/s, 12ui) 0.09 0.1 ps (rms) 1,5,6 1 applies to all outputs. 6 for rms figures, additive jitter is calculated by solving the following equation: (additive jitter)^2 = (total ji ttter)^2 - (i nput jitter)^2 4 sub j ect to final radification b y pci sig. 5 calculated from intel-su pp lied clock jitter tool v 1.6.4 2 see htt p ://www. p cisi g .com for com p lete s p ecs additive phase jitter, bypass mode t jphpcieg2 t jphqpi_smi t jphqpi_smi phase jitter, pll mode t jphpcieg2 3 sam p le size of at least 100k c y cles. this fi g ures extra p olates to 108 p s p k- p k @ 1m c y cles for a ber of 1-12. idt ? 12-output differential z-buffer for pcie gen2/3 and qpi 1682b- 12/08/11 9zx21201 12-output differential z-buffer for pcie gen2/3 and qpi 9 clock periods - differential outputs with spread spectrum disabled 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average min 0 ppm period nominal + ppm long-term average max +ssc short-term average max +c2c jitter absper max 100.00 9.94900 9.99900 10.00000 10.00100 10.05100 ns 1,2,3 133.33 7.44925 7.49925 7.50000 7.50075 7.55075 ns 1,2,4 clock periods - differential outputs with spread spectrum enabled 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average min 0 ppm period nominal + ppm long-term average max +ssc short-term average max +c2c jitter absper max 99.75 9.94906 9.99906 10.02406 10.02506 10.02607 10.05107 10.10107 ns 1,2,3 133.00 7.44930 7.49930 7.51805 7.51880 7.51955 7.53830 7.58830 ns 1,2,4 notes: 1 guaranteed by design and characterization, not 100% tested in production. 3 driven by src output of main clock, 100 mhz pll mode or bypass mode 4 driven b y cpu output of main clock, 133 mhz pll mode or b y pass mode measurement windo w units ssc on center freq. mhz ssc off center freq. mhz 2 all long term accuracy specifications are guaranteed with the assumption that the input clock complies with ck420bq/ck410b+ accuracy requirements (+/-100ppm). the 9zx21201 itself does not contribute to ppm error. dif dif measurement windo w units notes notes differential output terminations dif zo ( ? )iref ( ? )rs ( ? )rp ( ? ) 100 475 33 50 85 412 27 43.2 dif zo=85ohms,10" rp rp hcsl output buffer 9zx21201 differential test loads rs rs 2pf 2pf idt ? 12-output differential z-buffer for pcie gen2/3 and qpi 1682b- 12/08/11 9zx21201 12-output differential z-buffer for pcie gen2/3 and qpi 10 general smbus serial interface information for the 9zx21201 how to write: ? controller (host) sends a start bit. ? controller (host) sends the write address xx (h) ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) sends the data byte count = x ? idt clock will acknowledge ? controller (host) starts sending byte n through byte n + x -1 ? idt clock will acknowledge each byte one at a time ? controller (host) sends a stop bit how to read: ? controller (host) will send start bit. ? controller (host) sends the write address xx (h) ? idt clock will acknowledge ? controller (host) sends the begining byte location = n ? idt clock will acknowledge ? controller (host) will send a separate start bit. ? controller (host) sends the read addressyy (h) ? idt clock will acknowledge ? idt clock will send the data byte count = x ? idt clock sends byte n + x -1 ? idt clock sends byte 0 through byte x (if x (h) was written to byte 8) . ? controller (host) will need to acknowledge each byte ? controllor (host) will send a not acknowledge bit ? controller (host) will send a stop bit idt (slave/receiver) t wr ack ack ack ack ack p byte n + x - 1 data byte count = x beginning byte n stop bit x byte index block write operation slave address xx ( h ) beginning byte = n write start bit controller (host) t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit idt ( slave/receiver ) controller (host) x byte ack ack data byte count = x ack slave address yy ( h ) index block read operation slave address xx ( h ) beginning byte = n ack ack note: xx (h) is defined by smbus address select pins. idt ? 12-output differential z-buffer for pcie gen2/3 and qpi 1682b- 12/08/11 9zx21201 12-output differential z-buffer for pcie gen2/3 and qpi 11 smbustable: pll mode, and frequency select register pin # name control function t yp e 0 1 default bit 7 pll mode 1 pll o p eratin g mode rd back 1 r latch bit 6 pll mode 0 pll o p eratin g mode rd back 0 r latch bit 5 0 bit 4 0 bit 3 pll_sw_en enable s/w control of pll bw rw hw latch s/w control 0 bit 2 pll mode 1 pll o p eratin g mode 1 rw 1 bit 1 pll mode 0 pll o p eratin g mode 1 rw 1 bit 0 100m_133m# fre q uenc y select readback r 133mhz 100mhz latch smbustable: output control register pin # name control function t yp e 0 1 default bit 7 dif_7_en out p ut control - '0' overrides oe# p in rw 1 bit 6 dif_6_en out p ut control - '0' overrides oe# p in rw 1 bit 5 dif_5_en out p ut control - '0' overrides oe# p in rw 1 bit 4 dif_4_en out p ut control - '0' overrides oe# p in rw 1 bit 3 dif_3_en out p ut control - '0' overrides oe# p in rw 1 bit 2 dif_2_en out p ut control - '0' overrides oe# p in rw 1 bit 1 dif_1_en out p ut control - '0' overrides oe# p in rw 1 bit 0 dif_0_en out p ut control - '0' overrides oe# p in rw 1 smbustable: output control register pin # name control function t yp e 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 dif_11_en out p ut control - '0' overrides oe# p in rw 1 bit 2 dif_10_en out p ut control - '0' overrides oe# p in rw 1 bit 1 dif_9_en out p ut control - '0' overrides oe# p in rw 1 bit 0 dif_8_en out p ut control - '0' overrides oe# p in rw 1 smbustable: reserved register pin # name control function t yp e 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 reserved reserved reserved reserved reserved reserved reserved see pll operating mode readback table see pll operating mode readback table low/low enable 30/31 b y te 3 50/51 59/60 54/55 b y te 2 b y te 0 5 5 4 these bits available in b rev onl y . b y te 1 47/46 64/63 26/27 21/22 17/18 43/42 39/38 35/34 low/low enable reserved reserved reserved reserved reserved reserved reserved idt ? 12-output differential z-buffer for pcie gen2/3 and qpi 1682b- 12/08/11 9zx21201 12-output differential z-buffer for pcie gen2/3 and qpi 12 smbustable: reserved register pin # name control function t yp e 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 smbustable: vendor & revision id register pin # name control function t yp e 0 1 default bit 7 rid3 r x bit 6 rid2 r x bit 5 rid1 r x bit 4 rid0 r x bit 3 vid3 r 0 bit 2 vid2 r 0 bit 1 vid1 r 0 bit 0 vid0 r 1 smbustable: device id pin # name control function t yp e 0 1 default bit 7 r1 bit 6 r1 bit 5 r0 bit 4 r0 bit 3 r1 bit 2 r0 bit 1 r0 bit 0 r1 smbustable: byte count register pin # name control function t yp e 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 bc4 rw 0 bit 3 bc3 rw 1 bit 2 bc2 rw 0 bit 1 bc1 rw 0 bit 0 bc0 rw 0 smbustable: reserved register pin # name control function t yp e 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 reserved reserved reserved reserved reserved reserved reserved reserved device id 5 device id 6 device id 0 default value is 8 hex, so 9 bytes (0 to 8) will be read back by default. reserved reserved - reserved 1201 is 201 decimal or c9 hex device id 7 ( msb ) b y te 7 - - - - - - - - b y te 5 b y te 6 b y te 4 - - reserved reserved reserved reserved reserved reserved - - - - b y te 8 - - - - - device id 2 device id 1 device id 4 revision id a rev = 0000 b rev = 0001 - reserved vendor id device id 3 0001 for idt/ics writing to this register configures how many bytes will be read back. reserved idt ? 12-output differential z-buffer for pcie gen2/3 and qpi 1682b- 12/08/11 9zx21201 12-output differential z-buffer for pcie gen2/3 and qpi 13 common recommendations for differential routing dimension or value unit figure l1 length, route as non-coupled 50ohm trace 0.5 max inch 1 l2 length, route as non-coupled 50ohm trace 0.2 max inch 1 l3 length, route as non-coupled 50ohm trace 0.2 max inch 1 rs 33 ohm 1 rt 49.9 ohm 1 down device differential routing l4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max inch 1 l4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max inch 1 differential routing to pci express connector l4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max inch 2 l4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max inch 2 dif reference clock hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express down device ref_clk input figure 1: down device routing hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express add-in board ref_clk input figure 2: pci express connector routing idt ? 12-output differential z-buffer for pcie gen2/3 and qpi 1682b- 12/08/11 9zx21201 12-output differential z-buffer for pcie gen2/3 and qpi 14 vdiff vp-p vcm r1 r2 r3 r4 note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ics874003i-02 input compatible 0.60 0.3 1.2 33 174 140 100 standard lvds r1a = r1b = r1 r2a = r2b = r2 alternative termination for lvds and other common differential signals (figure 3) hcsl output buffer l1 l1' r1b l2 l2' r1a l4' l4 l3 r2a r2b down device ref_clk input figure 3 l3' r3 r4 component value note r5a, r5b 8.2k 5% r6a, r6b 1k 5% cc 0.1 f vcm 0.350 volts cable connected ac coupled application (figure 4) pcie device ref_clk input figure 4 r5a l4' l4 3.3 volts r5b r6a r6b cc cc idt ? 12-output differential z-buffer for pcie gen2/3 and qpi 1682b- 12/08/11 9zx21201 12-output differential z-buffer for pcie gen2/3 and qpi 15 dimensions dimensions (mm) symbol min. max. a0.81.0 n64 a1 00.05 n d 16 a3 n e 16 b 0.18 0.3 e d x e basic d2 min. / max. 6.00 6.25 e2 min. / max. 6.00 6.25 l min. / max. 0.30 0.50 thermally enhanced, very thin, fine pitch quad flat / no lead plastic package symbol 64l 0.25 reference 0.50 basic 9.00 x 9.00 ordering information part / order number shipping package package temperature difference 9ZX21201AKLF trays 64-pin mlf 0 to +70c 9ZX21201AKLFt tape and reel 64-pin mlf 0 to +70c 9zx21201bklf trays 64-pin mlf 0 to +70c 9zx21201bklft tape and reel 64-pin mlf 0 to +70c "lf" designates pb-free configuration, rohs compliant. "a and b" are the device revision designators (will not correlate with the datasheet revision). w/o byte 0 pll control with byte 0 pll mode control 9zx21201 12-output differential z-buffer for pcie gen2/3 and qpi 16 innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support 408-284-6578 pcclockhelp@idt.com corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan idt singapore pte. ltd. 1 kallang sector #07-01/06 kolamayer industrial park singapore 349276 phone: 65-6-744-3356 fax: 65-6-744-1764 europe idt europe limited 321 kingston road leatherhead, surrey kt22 7tu england phone: 44-1372-363339 fax: 44-1372-378851 ? 2010 integrated device technology , inc. all rights reserved. product specifications subject to change without notice. idt, ic s, and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa revision history rev. issuer issue date description page # 0.1 rdw 7/15/2010 intial release 0.2 rdw 8/4/2010 1. reformat to z buffer ds format. 2. added in power management table 3. minor typo fixes. 1-3, 6-9, 11-12 0.3 rdw 8/26/2010 1. updated oe latency to be 4 to 12 clocks 0.4 rdw 4/14/2011 1. corrected pin description table. pin 37 was missing a rdw 9/13/2011 1. updated electrical tables with char data 2. fixed minor typographical errors 3. moved to final various b rdw 12/8/2011 1. added b rev functionality description to features, benefits 2. updated tdspo_byp parameter from +/-350ps to +/-250ps 3.updated smbus byte 0 with b rev functionality 4. updated ordering information to include b rev 1,7,11,15 |
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