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copyright ? cirrus logic, inc. 2010 (all rights reserved) http://www.cirrus.com cs5451a six-channel, delta-sigma analog-to-digital converter features ? synchronous sampling ? on-chip 1.2 v reference (25 ppm/c typ.) ? power supply configurations: - va+ = +3 v; va- = -2 v; vd+ = +3 v - supply tolerances: 10% ? power consumption - 23 mw typical at vd+ = +3 v ? simple four-wire serial interface ? charge pump driver output generates negative power supply. ? ground-referenced bipolar inputs description the cs5451a is a highly integrated delta-sigma ( ?) an- alog-to-digital converter (adc) developed for the power measurement industry. the cs5451a combines six ? adcs, decimation filters, and a serial interface on a sin- gle chip. the cs5451a interfaces directly to a current transformer or shunt to measure current, and to a resis- tive divider or transformer to measure voltage. the product features a serial interface for communication with a microcontroller or dsp. the product is initialized and fully functional upon reset, and includes a voltage reference. ordering in formation: see page 13. vrefin vrefout iin1+ iin1- vin1+ vin1- vin2+ vin2- vin3+ vin3- iin2+ iin2- iin3+ iin3- va+ vd+ agnd se fso sdo sclk voltage reference serial interface reset decimation filter decimation filter decimation filter decimation filter decimation filter decimation filter x1, 20 x1 4th order ? modulator x1 x1, 20 x1 x1, 20 x1 4th order ? modulator 4th order ? modulator 4th order ? modulator 4th order ? modulator 4th order ? modulator gain cpd owrs xin dgnd va- clock pulse output regulator feb ?10 ds635f3
cs5451a 2 ds635f3 table of contents 1. pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2. characteristics and specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3. theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.3 performing measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.4 serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.5 system initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.6 voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 4.7 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5. package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 6. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7. environmental, manufacturing, & handling information . . . . . . . . . . . . . . . 13 8. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 list of figures figure 1. serial port timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. typical connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 3. one data frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4. serial port data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. generating va- with a charge pump. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
cs5451a ds635f3 3 1. pin description clock generator master clock input 25 xin - external clock signal or oscillator input. control pins and serial data i/o serial clock output 1 sclk - serial port clock signal that determines the output data rate for sdo pin. rate of sclk is dependent on the xin frequency and state of owrs pin. serial data output 2 sdo -serial port data output pin. data will be output at a rate defined by sclk. frame sync 3 fso - framing signal indicates when data samples are about to be transmitted on the sdo pin. serial po rt enable 4 se - when se is low, the output pins of the serial port are tri-stated. current input gain 5 gain - a logic high sets current channel gain to 1, a logic low sets the gain to 20. if no connection is made to this pin, it will default to logic low level (through internal 200 k resistor to dgnd). output word rate select 23 owrs - a logic low sets the output word rate (owr) to xin/2048 (hz). a logic high sets the owr to xin/1024 (hz). if no connection is made to th is pin, then owrs will default to logic low level (through internal 200 k resistor to dgnd). reset 24 reset - low activates reset, all internal registers are set to their default states. analog inputs/outputs voltage reference input 7 vrefin - the input to this pin establishes the voltage reference for the on-chip modulator. voltage reference output 8 vrefout - the on-chip voltage reference output. t he voltage reference has a nominal magni- tude of 1.2 v and is referenced to the agnd pin on the converter. differential voltage inputs 11,12 18,17 22,21 vin3+, vin3- - differential analog input pins for the voltage channel 3. vin2+, vin2- - differential analog input pins for the voltage channel 2. vin1+, vin1- - differential analog input pins for the voltage channel 1. differential current inputs 13,14 16,15 20,19 iin3+, iin3- - differential analog input pins for the current channel 3. iin2+, iin2- - differential analog input pins for the current channel 2. iin1+, iin1- - differential analog input pins for the current channel 1. power supply connections analog ground 6 agnd - analog ground. positive analog supply 9 va+ - the positive analog supply. typical +3 v 10% relative to agnd. negative analog supply 10 va- - the negative analog supply. typica l -2 v 10% relative to agnd. charge pump drive 26 cpd - designed to drive external charge pump ci rcuitry that will produce a negative analog sup- ply (va-)voltage. digital ground 27 dgnd - digital ground. positive digital supply 28 vd + - the positive digital supply. typical +3 v 10% relative to agnd. 1 14 7 13 6 12 5 11 9 4 3 8 10 2 15 18 16 24 20 19 25 21 17 26 27 22 28 23 iin2- vin2+ iin2+ reset iin1+ iin1- xin vin1- vin2- cpd dgnd vin1+ vd+ owrs iin3- vin3+ iin3+ gain va+ va - se vrefout vin3- fso sdo vrefin sclk agnd differential current input 2 differential voltage input 2 differential current input 2 reset differential current input 1 differential current input 1 master clock differential voltage input 1 differential voltage input 2 charge pump drive digital ground differential voltage input 1 digital supply output word rate select differential current input 3 differential voltage input 3 differential current input 3 current input gain positive analog supply negative analog supply serial port enable reference output differential voltage input 3 frame sync serial data output reference input serial clock output analog ground cs5451a
cs5451a 4 ds635f3 2. characteristics and specifications recommended operating conditions analog characteristics ? min/max characteristics and specifications are guaranteed over all operating conditions. ? typical characteristics and specifications are meas ured at nominal supply voltages and ta = 25 c. ? va+ = vd+ = 3 v 10%; va- = -2 v 10%; agnd = dgnd = 0 v; vrefin = +1.2 v. all voltages with respect to 0 v. ? xin = 4.096 mhz. parameter symbol min typ max unit dc power supplies positive digital positive analog negative analog vd+ va+ va- 2.7 2.7 -2.2 3.0 3.0 -2.0 3.3 3.3 -1.8 v v v voltage reference input vref+ - 1.2 - v parameter symbol min typ max unit accuracy (all channels) total harmonic distortion thd 74 - - db common mode rejection (dc, 50, 60 hz) cmrr 80 - - db common mode + signal on input va- - va+ v input sampling rate - xin/8 - hz analog inputs (note 1) differential input voltage range gain=20 [(i in+ ) - (i in- )] or [(v in+ ) - (v in- )] gain=1 vin vin - - 80 1.6 - - mv p-p v p-p bipolar offset gain=20 gain=1 vos vos - - 11.5 0.5 20 4.0 mv mv crosstalk (channel-to-channel) (50, 60 hz) - -105 - db input capacitance gain = 20 gain = 1 ic ic - - - - 20 1 pf pf effective input impedance gain=20 gain=1 eii eii 50 500 60 600 - - k k noise (referred to input) 0-60 hz gain=20 gain=1 0-1 khz gain=20 gain=1 0-2 khz gain=20 gain=1 - - - - - - - - - - - - 1 20 2.5 50 3.75 75 v rms v rms v rms v rms v rms v rms reference output output voltage refout 1.15 1.2 1.25 v temperature coefficient - 25 50 ppm/c load regulation (output current 1 a source or sink) v r -610mv power supply rejection psrr 60 - - db reference input input voltage range vref+ 1.15 1.2 1.25 v input capacitance - - 10 pf input cvf current - - 1 a
cs5451a ds635f3 5 analog characteristics (continued) notes: 1. specifications for gain = 20 apply only to current channels. voltage channels are fixed to gain = 1 2. all outputs unloaded. all inputs cmos level. 3. definition for psrr: vrefin tied to vrefout, va+ = vd+ = 3 v, agnd = dgnd = 0 v, va- = -2 v (using charge- pump circuit with cpd). in addition, a 106.07 mv rms (60 hz) sinewave is imposed onto the va+ and vd+ pins. the ?+? and ?-? input pins of both input channels are shorted to va-. 2048 instantaneous digital output data words are collected for the channel under test. t he rms value of the digital sinusoidal output signal is calculated, and this rms value is converted into the rms value of the sinusoid al voltage (measured in mv) that would need to be applied at the channel?s inputs, in order to cause the same digi tal sinusoidal output. this vo ltage is then defined as veq. psrr is then (in db): digital characteristics (see note 4) ? min/max characteristics and specifications are guaranteed over all operating conditions. ? typical characteristics and specifications are meas ured at nominal supply voltages and ta = 25 c. ? va+ = vd+ = 3v 10%; va- = -2 v 10%; agnd = dgnd = 0 v. all voltages with respect to 0 v. ? xin = 4.096 mhz notes: 4. all measurements performed under static conditions. 5. for owrs and gain pins, input leakage current is 30 a (max). parameter symbol min typ max unit power supplies power supply currents i a+ typical va+=vd+=+3v; va-=-2v i d+ with cpd i d+ without cpd psca pscd pscd - - - 4.0 5.0 1.0 5.3 6.3 1.5 ma ma ma power consumption with cpd (note 2) without cpd pc pc - - 27 23 35 31 mw mw power supply rejection (dc) 50, 60 hz (note 3) voltage channel 50, 60 hz (note 3) current channel psrr psrr psrr 50 50 60 - 65 90 - - - db db db parameter symbol min typ max unit master clock characteristics master clock frequency xin 3 4.096 5 mhz master clock duty cycle 40 - 60 % filter characteristics high rate filter output word rate owrs = 0 owrs = 1 owr owr - - xin/2048 xin/1024 - - hz hz input/output characteristics high-level input voltage v ih 0.6 vd+ - vd+ v low-level input voltage v il 0.0 - 0.8 v high-level output voltage i out = -5.0 ma v oh (vd+) - 1.0 - - v low-level output voltage i out = 5.0 ma v ol --0.4v input leakage current (note 5) i in -110a 3-state leakage current i oz --10a digital output pin capacitance c out -9-pf psrr 20 106.07 v eq ----------------- - ?? ?? ?? log ? =
cs5451a 6 ds635f3 switching characteristics ? min/max characteristics and specifications are guaranteed over all operating conditions. ? typical characteristics and specifications are meas ured at nominal supply voltages and ta = 25 c. ? va+ = vd+ = 3 v 10%; va- = -2 v 10%; agnd = dgnd = 0 v. all voltages with respect to 0 v. ? logic levels: logic 0 = 0 v, logic 1 = vd+ notes: 6. specified using 10% and 90% points on wave-f orm of interest. output loaded with 50 pf. 7. device parameters are specified with xin = 4.096 mhz. 8. device parameters are specified with owrs = 1. 9. after se is asserted, the states of sdo and sclk are fso is undefined. parameter symbol min typ max unit rise times any digital input (except xin) (note 6) xin only any digital output t rise - - - - - 50 1.0 10 - s ns ns fall times any digital input (except xin) (note 6) xin only any digital output t fall - - - - - 50 1.0 10 - s ns ns serial port timing serial clock frequency owrs = ?0? (note 7) owrs = ?1? sclk sclk - - 500 1000 - - khz khz serial clock pulse width high (note 7 and 8) pulse width low t 1 t 2 - - 0.5 0.5 - - sclk sclk sclk falling to new data bit t 3 - - 50 ns fso falling to sclk rising delay (note 7 & 8) t 4 -0.5-sclk fso pulse width (note 7 & 8) t 5 -1-sclk se rising to output enabled (note 9) t 6 - - 50 ns se falling to output in tri-state t 7 - - 50 ns t 7 t 2 t 1 t 3 4 t 5 t msb(v1) msb(v1) - 1 lsb(i3) se 6 t sdo sclk fso figure 1. serial port timing
cs5451a ds635f3 7 absolute maximum ratings warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not gu aranteed at these extremes. notes: 10. applies to all pins including continuous over-vol tage conditions at the analog input (ain) pins. 11. transient current of up to 100 ma will not cause scr latch-up. maximum input current for a power supply pin is 50 ma. 12. total power dissipation, including all input currents and output currents. parameter symbol min typ max unit dc power supplies positive digital positive analog negative analog vd+ va+ va- -0.3 -0.3 -2.5 - - +3.5 +3.5 -0.3 v v v input current, any pin except supplies (note 10 and 11) i in --10ma output current i out --25ma power dissipation (note 12) pdn - - 500 mw analog input voltage all analog pins v ina (va-) - 0.3 - (va+) + 0.3 v digital input voltage all digital pins v ind -0.3 - (vd+) + 0.3 v ambient operating temperature t a -40 - 85 c storage temperature t stg -65 - 150 c
cs5451a 8 ds635f3 3. theory of operation the cs5451a is a six-channel analog-to-digital convert- er (adc) followed by a serial interface that allows com- munication with a target device. the analog inputs are structured for 3-phase po wer meter applications, with three dedicated voltage and current channels. figure 2 illustrates the cs5451a typica l inputs and power supply connections. the voltage-sensing element introduces a voltage waveform on the voltage channel inputs vin(1-3) and is subject to a fixed 1x gain amplifier. a fourth-order del- ta-sigma modulator samples the amplified signal for dig- itization. simultaneously, the current-sensing element introduces a voltage waveform on the current channel input iin(1-3) and is subject to two selectable gains of the programmable gain amplifier (pga). the amplified sig- nal is sampled by a fourth-order delta-sigma modulator for digitization. both conver ters sample at a rate of xin/8, the over-sampling provides a wide dynamic range and simplified anti-alias filter design. the decimating digital filters on all channels are sinc 3 filters. the single bit data is passed to the low-pass dec- imation filter and output at a fixed word rate. the deci- mation rate is selectable for two output word rates. the 16-bit output word is then transmitted via a master serial data port. the six-channel data is multiplexed on the serial data output and is preceded by a frame sync signal. va+ vd+ vin1+, vin2+, or vin3+ vin1-, vin2-, or vin3- iin1+, iin2+, or iin3+ iin1-, iin2-, or iin3- agnd dgnd refin refout optional external reference v phase + i -2 v phase va- +3 v 1.2 v note: current input channels actually measure voltage. figure 2. typical connection diagram
cs5451a ds635f3 9 4. functional description 4.1 analog inputs the cs5451a is equipped with six fully differential input channels. the inputs vin(1-3) and iin(1-3) are des- ignated as the voltage and current channel inputs, re- spectively. the full-scale di fferential input voltage for the current and voltage channel is 800 mv p (gain = 1x). 4.1.1 voltage channel the output of the line voltage resistive divider or trans- former is connected to the vin(1-3)+ and vin(1-3)- in- put pins of the cs5451a. the voltage channels are equipped with a 1x fixed gain amplifier. the full-scale signal level that can be applied to the voltage channel is 800 mv. if the input signal is a sine wave the maximum rms voltage is: which is approximately 70.7% of maximum peak volt- age. 4.1.2 current channel the output of the current sense resistor or transformer is connected to the iin(1-3)+ and iin(1-3)- input pins of the cs5451a. to accommodate different current-sens- ing devices the current channels incorporates a pro- grammable gain amplifier (pga) that can be set to one of two input ranges. input pin gain (see table 1) define the pga?s two gain selections and corresponding max- imum input signal level. 4.2 digital filters the decimating digital filter samples the modulator bit stream at xin/8 and produces a fixed output word rate. the digital filters are implemented as sinc 3 filters with the following transfer function: the decimation rate is determined by the exponent dr (see table 2). the output word rate (owr ) is selected by the owrs pin and defined by table 2. 4.3 performing measurements the adc outputs are transferred in 16-bit, signed (two?s complement) data formats. table 3 defines the relation- ship between the differential voltage applied to any one of the input channels and the corresponding output code. note that for the current channels, the state of the gain input pin is assumed to driven low such that the pga gain on the current channels is 1x. if the pga gain of the current channels is set to 20x, a +40 mv voltage is applied to any pair of iin(1-3) pins would cause an output code of 32767. table 3. differential input voltage vs. output code 4.4 serial interface the cs5451a communicates with a target device via a master serial data output po rt. output data is provided on the sdo output synchro nous with the sclk output. a third output, fso, is a framing signal used to signal the start of output data. these three outputs will be driv- en as long as the se (serial enable) input is held high. otherwise, thes e outputs will be high-impedance. data out (sdo) changes as a result of sclk falling, and always outputs valid data on the rising edge of sclk. when data is being transferred the sclk frequency is xin/8 when owrs is low or xin/4 when owrs is high. gain maximum input range 0 40mv 20x 1 800mv 1x table 1. current channel pga setting 800 mv p 2 -------- --------- 565.69 mv rms ? hz () 1z dr ? ? 1z 1 ? ? ---------------------- ?? ?? ?? 3 = owrs dr output word rate 0 256 xin/2048 1 128 xin/1024 table 2. decimation filter owr differential input voltage (mv) output code (hexadecimal) output code (decimal) +800 7fff 32767 0.0122 to 0.0366 0001 1 -0.0122 to 0.0122 0000 0 -0.0122 to -0.0366 ffff -1 -800 8000 -32768 notes: assume pga gain is set to 1x.
cs5451a 10 ds635f3 when data is not being transferred sclk is held low. (see figure 3.) the framing signal (fso) ou tput is normally low. fso goes high, with a pulse width equal to one sclk period, when the instantaneous voltage and current data sam- ples are about to be transmitted out of the serial inter- face (after each a/d conversion cycle). sclk is not active during fso high. for 96 sclk periods after fso falls, sclk is active and sdo provides valid output. six channels of 16-bit data are output, msb first. figure 4 illustrates how the volt- age and current measurements are output for the three phases. sclk will then be he ld low until the next sam- ple period. 4.5 system initialization a hardware reset is in itiated when the reset pin is forced low with a minimum pulse width of 50 ns. when reset is activated, all internal registers are set to a de- fault state. upon powering up, the reset pin must be held low (active) until after the power stabilizes. 4.6 voltage reference the cs5451a is specified for operation with a +1.2 v reference between the vrefin and agnd pins. the converter includes an internal 1.2 v reference that can be used by connecting the vrefout pin to the vre- fin pin of the device. the vrefin can be used to con- nect external filtering and/or references. 4.7 power supply the low, stable analog power consumption and superior supply rejection of the cs5451a allow for the use of a simple charge-pump negative supply generator. the use of a negative supply a lleviates the need for level sclk fso sdo 12 15 14 13 0 1 2 3 4 5 6 7 8 9 10 11 15 14 13 12 11 10 9 8 7 65 4321 channel 1 ( i ) channel 1 ( v ) 01514 . . . ch. 2 ( v ) ch. 2 ( i ) ch. 3 ( v ) ch. 3 ( i ) ... ... ... . . . . . . . . . [ low ] [ low ] . . . . . . . . . 0 1 2 3 96 sclks figure 3. one data frame sclk fso sdo channel 1 v channel 2 i channel 3 i channel 2 v channel 3 v channel 1 i each data segment is 16 bits long. 96 sclks figure 4. serial port data transfer
cs5451a ds635f3 11 shifting of the analog inputs. the cpd pin and capacitor c1 provide the necessary analog supply current as shown in figure 5. the schottky diodes d1 and d2 are chosen for their low forward voltages and high-speed capabilities. the capacitor c2 provides the required charge storage and bypassin g of the negative supply. the cpd output signal provides the charge pump driver signal. the frequency of the charge pump driver signal is synchronous to xin. th e nominal average frequency is 1 mhz. the level on the va- pin is fed back internally so that the cpd output will regulate the va- level to -2/3 of va+ level. the value of capacitor c1 (see figure 5) is dependent on the xin clock frequency. the 39 nf value for c1 was selected for a xin clock frequency equal to 4.096 mhz. for more information about th e operation of this type of charge pump circuit, the reader can refer to cirrus log- ic, inc.?s application note an152: using the cs5521/24/28, and cs5525/26 charge pump drive for external loads. agnd bat 85 d1 c1 39 nf c2 cpd va- bat 85 1f d2 figure 5. generating va- with a charge pump
cs5451a 12 ds635f3 5. package dimensions notes: 1. ?d? and ?e1? are reference datums and do not included mo ld flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flas h or protrusions shall not exceed 0.20 mm per side. 2. dimension ?b? does not include dambar protrusion/intru sion. allowable dambar protrusion shall be 0.13 mm total in excess of ?b? dimension at maximum mate rial condition. dambar intrusion shall not reduce dimension ?b? by more than 0.07 mm at least material condition. 3. these dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. inches millimeters note dim min nom max min nom max a -- -- 0.084 -- -- 2.13 a1 0.002 0.006 0.010 0.05 0.13 0.25 a2 0.064 0.069 0.074 1.62 1.75 1.88 b 0.009 -- 0.015 0.22 -- 0.38 2,3 d 0.390 0.4015 0.413 9.90 10.20 10.50 1 e 0.291 0.307 0.323 7.40 7.80 8.20 e1 0.197 0.209 0.220 5.00 5.30 5.60 1 e 0.022 0.026 0.030 0.55 0.65 0.75 l 0.025 0.0354 0.041 0.63 0.90 1.03 0 4 8 0 4 8 jedec #: mo-150 28l ssop package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view
cs5451a ds635f3 13 6. ordering information 7. environmental, manufacturi ng, & handling information * msl (moisture sensitivity level) as specified by ipc/jedec j-std-020. model temperature package cs5451a-is -40 to +85 c 28-pin ssop cs5451a-isz (lead free) model number peak reflow temp msl rating* max floor life cs5451a-is 240 c 2 365 days cs5451a-isz (lead free) 260 c 3 7 days
cs5451a 14 ds635f3 8. revision history revision date changes a1 jul 2003 initial release pp1 oct 2003 initial release for preliminary product information f1 feb 2005 update electrical specifications w/ most-current characterization data. f2 aug 2005 update electrical s pecifications w/ most-current characterization data. added msl data. f3 feb 2010 corrected typical input sampling rate from xin/4 to xin/8 (hz). contacting cirrus logic support for all product questions and inquiries cont act a cirrus logic sales representative. to find the one nearest to you go to www.cirrus.com important notice cirrus logic, inc. and its subsidiaries (?cirrus?) believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided ?as is? without warranty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectu al property rights. cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semiconductor products may involve potentia l risks of death, personal injury, or severe prop- erty or environmental damage (?critical applications?). ci rrus products are not designed, authorized or warranted for use in aircraft systems, military applications, products surg ically implanted into the body, automotive safety or security devices, life support products or other critical applicati ons. inclusion of cirrus product s in such applications is under- stood to be fully at the customer's risk and cirrus disclaims and makes no warranty, express, statutory or implied, includ- ing the implied warranties of merchantability and fitness for particular purpose, with re gard to any cirrus product that is used in such a manner. if the custo mer or customer's customer uses or permit s the use of cirrus products in critical applications, customer agrees, by such use, to fully indemnif y cirrus, its officers, directors, employees, distributors and other agents from any and all liability, i ncluding attorneys' fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners.

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