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hy57v168010d 2 banks x 1m x 8 bit synchronous dram this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied rev. 1.5/dec.98 description the hyundai hy57v168010d is a 16,777,216-bits cmos synchronous dram, ideally suited for the main memory applications which require large memory density and high bandwidth. hy57v168010d is organized as 2banks of 1,048,576x8. hy57v168010d is offering fully synchronous operation referenced to a positive edge clock. all inputs and outputs are synchronized with the rising edge of the clock input. the data paths are internally pipelined to achieve very high band- width. all input and output voltage levels are compatible with lvttl. programmable options include the length of pipeline (read latency of 1,2 or 3), the number of consecutive read or write cycles initiated by a single control command (burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). a burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (this pipeline design is not restricted by a `2n` rule.) features ? single 3.3v 0.3v power supply ? all device pins are compatible with lvttl interface ? jedec standard 400mil 44pin tsop-ii with 0.8mm of pin pitch ? all inputs and outputs referenced to positive edge of system clock ? data mask function by dqm ? internal two banks operation ? auto refresh and self refresh ? 4096 refresh cycles / 64ms ? programmable burst length and burst type - 1, 2, 4, 8 and full page for sequence burst - 1, 2, 4 and 8 for interleave burst ? programmable cas latency ; 1, 2, 3 clocks ordering information part no. clock frequency organization interface package hy57v168010dtc-8 125mhz 2banks x 1mbits x 8 lvttl 400mil 44pin tsop ii hy57v168010dtc-10p 100mhz HY57V168010DTC-10S 100mhz hy57v168010dtc-10 100mhz
hy57v168010d rev. 1.5/dec.98 2 vss dq7 vssq dq6 vddq dq5 vssq dq4 vddq nc nc dqm clk cke nc a9 a8 a7 a6 a5 a4 vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 44 pin tsop ii 400mil x 725mil 0.8mm pin pitch vdd dq0 vssq dq1 vddq dq2 vssq dq3 vddq nc nc we cas ras cs ba a10/ap a0 a1 a2 a3 vdd pin configuration pin description pin pin name description clk clock the system clock input. all other inputs are referenced to the sdram on the rising edge of clk. cke clock enable controls internal clock signal and when deactivated, the sdram will be one of the states among power down, suspend or self refresh. cs chip select command input enable or mask except clk, cke and dqm ba bank address select either one of banks during both ras and cas activity. a0 ~ a10 address row address : ra0 ~ ra10, column address : ca0 ~ ca8 auto-precharge flag : a10 ras , cas , we row address strobe, column address strobe, write enable ras , cas and we define the operation. refer function truth table for details dqm data input/output mask dqm control output buffer in read mode and mask input data in write mode dq0 ~ dq7 data input/output multiplexed data input / output pin v dd /v ss power supply/ground power supply for internal circuit and input buffer v ddq /v ssq data output power/ground power supply for dq nc no connection no connection
hy57v168010d rev. 1.5/dec.98 3 functional block diagram 2mx8 synchronous dram column addr. latch & counter burst length counter refresh interval timer refresh counter dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 address register i/o control test mode mode register self refresh counter column decoder sense amp & i/o gates 1mx8 bank 0 column decoder sense amp & i/o gates 1mx8 bank 1 ras cas cs we dqm cke precharge overflow column active row active address[0:10] clk ba(a11)
hy57v168010d rev. 1.5/dec.98 4 absolute maximum ratings note : operation at above absolute maximun rating can adversely affect device reliability. dc operating condition (ta=0 c to 70 c ) note : 1.all voltages are referenced to v ss = 0v. 2.v ih (max) is acceptable 4.6v ac pulse width with 10ns of duration. 3.v il (min) is acceptable -1.5v ac pulse width with 10ns of duration. ac operating condition (ta=0 c to 70 c , v dd =3.3v 0.3v, v ss =0v) note : 1. output load to measure access times (tac, toh, etc) varies to clock frequency. a load is equivalent to one ttl gate and one capacitance. parameter symbol rating unit ambient temperature t a 0 ~ 70 c storage temperature t stg -55 ~ 125 c voltage on any pin relative to v ss v in , v out -1.0 ~ 4.6 v voltage on v dd relative to v ss v dd -1.0 ~ 4.6 v short circuit output current i os 50 ma power dissipation p d 1 w soldering temperature time t solder 260 10 c sec parameter symbol min typ. max unit note power supply voltage v dd , v ddq 3.0 3.3 3.6 v 1 input high voltage v ih 2.0 3.0 v dd + 0.3 v 1, 2 input low voltage v il -0.5 0 0.8 v 1, 3 parameter symbol value unit note ac input high / low level voltage v ih / v il 2.4/0.4 v input timing measurement reference level voltage vtrip 1.4 v input rise / fall time tr / tf 1 ns output timing measurement reference level voutref 1.4 v output load capacitance for access time measurement cl 50 pf 1
hy57v168010d rev. 1.5/dec.98 5 capacitance (ta=25 c , f=1mhz) output load circuit dc characteristics i (ta=0 c to 70 c , v dd =3.3v 0.3v) note : 1.v in = 0 to 3.6v, all other pins are not under test = 0v 2.d out is disabled, v out =0 to 3.6v parameter pin symbol min max unit input capacitance clk c i1 2.5 4 pf a0 ~ a10, ba cke, cs , ras , cas , we ,dqm c i2 2.5 5 pf data input / output capacitance dq0 ~ dq7 c i/o 4 6.5 pf parameter symbol min. max unit note input leakage current il -1 1 ua 1 output leakage current io -1 1 ua 2 output high voltage v oh 2.4 - v i oh = -4ma output low voltage v ol - 0.4 v i ol =+4ma vtt =1.4v rt=250 w 50 pf output 50 pf output dc output load circuit ac output load circuit
hy57v168010d rev. 1.5/dec.98 6 dc characteristics ii (ta=0 c to 70 c , v dd =3.3v 0.3v, v ss =0v) note : 1.i dd1 and i dd4 depend on output loading and cycle rates. specified values are measured with the output open. parameter symbol test condition speed unit note -8 -10p -10s -10 operating current i dd1 burst length=1, one bank active tras 3 tras(min),trp 3 trp(min), io=0ma 110 110 110 90 ma 1 precharge standby current in power down mode i dd2p cke vil(max), tck = min. 1 ma i dd2ps cke vil(max), tck = 1 precharge standby current in non power down mode i dd2n cke 3 vih(min), cs 3 vih(min), tck = min input signals are changed one time during 2clks. all other pins 3 vdd-0.2v or 0.2v 20 ma i dd2ns cke 3 vih(min), tck = input signals are stable. 15 active standby current in power down mode i dd3p cke vil(max), tck = min 30 ma i dd3ps cke vil(max), tck = 30 active standby current in non power down mode i dd3n cke 3 vih(min), cs 3 vih(min), tck = min input signals are changed one time during 2clks. all other pins 3 vdd-0.2v or 0.2v 50 ma i dd3ns cke 3 vih(min), tck = input signals are stable 30 burst mode operating current idd4 tck 3 tck(min), tras 3 tras(min), io=0ma all banks active cl=3 110 90 90 75 ma 1 cl=2 90 75 75 65 auto refresh current i dd5 trrc 3 trrc(min), all banks active 110 110 110 90 ma self refresh current i dd6 cke 0.2v 2 ma
hy57v168010d rev. 1.5/dec.98 7 ac characteristics i (ta=0 c to 70 c , v dd =3.3v 0.3v, v ss =0v) note : 1.assume tr / tf (input rise and fall time ) is 1ns. 2.access times to be measured with input signals of 1v/ns edge rate, 0.8v to 2.0v paramter symbol -8 -10p -10s -10 unit note min max min max min max min max system clock cycle time cas latency = 3 tck3 8 - 10 - 10 - 10 - ns cas latency = 2 tck2 10 - 10 - 12 - 10 - clock high pulse width tchw 3 - 3 - 3 - 3 - ns 1 clock low pulse width tclw 3 - 3 - 3 - 3 - ns 1 access time from clock cas latency = 3 tac3 - 6 - 6 - 6 - 8 ns cas latency = 2 tac2 - 6 - 6 - 6 - 8 data-out hold time toh 3 - 3 - 3 - 3 - ns data-input setup time tds 2 - 2 - 2 - 3 - ns 1 data-input hold time tdh 1 - 1 - 1 - 1 - ns 1 address setup time tas 2 - 2 - 2 - 3 - ns 1 address hold time tah 1 - 1 - 1 - 1 - ns 1 cke setup time tcks 2 - 2 - 2 - 3 - ns 1 cke hold time tckh 1 - 1 - 1 - 1 - ns 1 command setup time tcs 2 - 2 - 2 - 3 - ns 1 command hold time tch 1 - 1 - 1 - 1 - ns 1 clk to data output in low z-time tolz 2 - 2 - 2 - 2 - ns clk to data output in high z-time cas latency = 3 tohz3 2 9 3 9 3 9 3 10 ns cas latency = 2 tohz2 2 9 3 9 3 9 3 10 ns
hy57v168010d rev. 1.5/dec.98 8 ac characteristics ii (ta=0 c to 70 c , v dd =3.3v 0.3v, v ss =0v) note : 1. a new command can be given trrc after self refresh exit. parameter symbol -8 -10p -10s -10 unit note min max min max min max min max ras cycle time operation trc 70 - 70 - 70 - 80 - ns auto refresh trrc 70 - 70 - 70 - 80 - ns ras to cas delay trcd 20 - 20 - 20 - 20 - ns ras active time tras 50 100k 50 100k 50 100k 50 100k ns ras precharge time trp 20 - 20 - 20 - 30 - ns ras to ras bank active delay trrd 20 - 20 - 20 - 20 - ns cas to cas bank active delay tccd 1 - 1 - 1 - 1 - clk write command to data-in delay twtl 0 - 0 - 0 - 0 - clk data-in to precharge command tdpl 1 - 1 - 1 - 1 - clk data-in to active command tdal 4 - 3 - 3 - 3 - clk dqm to data-in hi-z tdqz 2 - 2 - 2 - 2 - clk dqm to data mask tdqm 0 - 0 - 0 - 0 - clk mrs to new command tmrd 2 - 2 - 2 - 2 - clk precharge to data output hi-z cas latency = 3 tproz3 3 - 3 - 3 - 3 - clk cas latency = 2 tproz2 2 - 2 - 2 - 2 - clk power down exit time tpde 1 - 1 - 1 - 1 - clk self refresh exit time tsre 1 - 1 - 1 - 1 - clk 1 refresh time tref 64 - 64 - 64 - 64 - ms
hy57v168010d rev. 1.5/dec.98 9 device operating option table hy57v168010d-8 hy57v168010d-10p hy57v168010d-10s hy57v168010d-10 cas latency trcd tras trc trp tac toh 125mhz 3clks 3clks 6clks 9clks 3clks 6ns 3ns 100mhz 2clks 2clks 5clks 7clks 2clks 6ns 3ns 83mhz 2clks 2clks 4clks 6clks 2clks 6ns 3ns 66mhz 2clks 2clks 4clks 6clks 2clks 6ns 3ns cas latency trcd tras trc trp tac toh 100mhz 2clks 2clks 5clks 7clks 2clks 6ns 3ns 83mhz 2clks 2clks 4clks 6clks 2clks 6ns 3ns 66mhz 2clks 2clks 3clks 5clks 2clks 6ns 3ns 50mhz 2clks 1clk 3clks 4clks 1clk 6ns 3ns cas latency trcd tras trc trp tac toh 100mhz 3clks 2clks 5clks 7clks 2clks 6ns 3ns 83mhz 2clks 2clks 4clks 6clks 2clks 6ns 3ns 66mhz 2clks 2clks 3clks 5clks 2clks 6ns 3ns 50mhz 2clks 1clk 3clks 4clks 1clk 6ns 3ns cas latency trcd tras trc trp tac toh 100mhz 3clks 3clks 5clks 8clks 3clks 8ns 3ns 83mhz 2clks 2clks 5clks 7clks 2clks 8ns 3ns 66mhz 2clks 2clks 4clks 6clks 2clks 8ns 3ns 50mhz 2clks 2clks 3clks 4clks 1clk 8ns 3ns
hy57v168010d rev. 1.5/dec.98 10 command truth table note : 1. exiting self refresh occurs by asynchronously bringing cke from low to high. 2. x=do not care, l=low, h=high, ba=bank address, ra= row address, ca=column address, opcode=operand code, nop=no operation. command cken-1 cken cs ras cas we dqm a 0 ~a 9 a10/ ap ba note mode register set h x l l l l x op code no operation h x h x x x x x l h h h bank active h x l l h h x row address v read h x l h l h x column address l v read with auto precharge h write h x l h l l x column address l v write with auto precharge h precharge all bank h x l l h l x x h x precharge selected bank l v burst stop h x l h h l x x u/ldqm h x v x auto refresh h h l l l h x x self refresh 1 entry h l l l l h x x exit l h h x x x x l h h h precharge power down entry h l h x x x x x l h h h exit l h h x x x x l h h h clock suspend entry h l h x x x x x l v v v exit l h x x
hy57v168010d rev. 1.5/dec.98 11 package information 400mil 44pin thin small outline package (tc) 2mx8 synchronous dram unit : inch (mm)

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