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wideband synthesizer with integrated vco data sheet adf4351 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2012 analog devices, inc. all rights reserved. features output frequency range: 35 mhz to 4400 mhz fractional-n synthesizer and integer-n synthesizer low phase noise vco programmable divide-by-1/-2/-4/-8/-16/-32/-64 output typical jitter: 0.3 ps rms typical evm at 2.1 ghz: 0.4% power supply: 3.0 v to 3.6 v logic compatibility: 1.8 v programmable dual-modulus prescaler of 4/5 or 8/9 programmable output power level rf output mute function 3-wire serial interface analog and digital lock detect switched bandwidth fast lock mode cycle slip reduction applications wireless infrastructure (w-cdma, td-scdma, wimax, gsm, pcs, dcs, dect) test equipment wireless lans, catv equipment clock generation general description the adf4351 allows implementation of fractional-n or integer-n phase-locked loop (pll) frequency synthesizers when used with an external loop filter and external reference frequency. the adf4351 has an integrated voltage controlled oscillator (vco) with a fundamental output frequency ranging from 2200 mhz to 4400 mhz. in addition, divide-by- 1/-2/-4/-8/-16/-32/-64 circuits allow the user to generate rf output frequencies as low as 35 mhz. for applications that require isolation, the rf output stage can be muted. the mute function is both pin- and software-controllable. an auxiliary rf output is also available, which can be powered down when not in use. control of all on-chip registers is through a simple 3-wire interface. the device operates with a power supply ranging from 3.0 v to 3.6 v and can be powered down when not in use. functional block diagram muxout cp out ld sw v com temp ref in clk data le av dd sdv dd dv dd v p agnd ce dgnd cp gnd sd gnd a gndvco r set v vco v tune v ref rf out a+ rf out a? rf out b+ rf out b? phase comparator fast lock switch charge pump output stage output stage pdb rf multiplexer multiplexer 10-bit r counter 2 divider 2 doubler function latch data register integer value n counter fraction value third-order fractional interpolator modulus value multiplexer lock detect 1/2/4/8/16/ 32/64 adf4351 vco core 09800-001 figure 1.
adf4351 data sheet rev. 0 | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing characteristics ................................................................ 5 absolute maximum ratings ............................................................ 6 transistor count ........................................................................... 6 thermal resistance ...................................................................... 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 9 circuit description ......................................................................... 11 reference input section ............................................................. 11 rf n divider ............................................................................... 11 phase frequency detector (pfd) and charge pump ............ 11 muxout and lock detect ...................................................... 12 input shift registers ................................................................... 12 program modes .......................................................................... 12 vco .............................................................................................. 12 o utput stage ................................................................................ 13 register maps .................................................................................. 14 register 0 ..................................................................................... 18 register 1 ..................................................................................... 18 register 2 ..................................................................................... 18 register 3 ..................................................................................... 19 register 4 ..................................................................................... 20 register 5 ..................................................................................... 20 register initialization sequence ............................................... 20 rf synthesizer a worked example ...................................... 21 reference doubler and reference divider ............................. 21 12- bit programmable modulus ................................................ 21 cycle slip reduction for faster lock times ........................... 22 spurious optimization and fast lock ..................................... 22 fast lock timer and register sequences ................................ 22 fast lock example ..................................................................... 22 fast lock loop filter topology ................................................ 23 spur mechanisms ....................................................................... 23 spur consistency and fractional spur optimization ........... 24 phase resync ............................................................................... 24 applications information .............................................................. 25 direct conversion modulator .................................................. 25 interfacing to the aduc70xx and the adsp - bf527 ............. 26 pcb design guidelines for a chip scale package ................. 26 output matching ........................................................................ 27 outline dimensions ....................................................................... 28 ordering guide .......................................................................... 28 revision history 5 / 12 r evision 0 : initial versi on
data sheet adf4351 rev. 0 | page 3 of 28 specifications av dd = dv dd = v v co = sd v dd = v p = 3.3 v 10% ; agnd = dgnd = 0 v; t a = t min to t max , unless otherwise noted. operating temperature range is ?40c to +85 c. table 1 . parameter min typ max unit test conditions/comments ref in characteristics input frequency 10 250 mhz fo r f < 10 mhz , ensure slew rate > 21 v/s input sensitivity 0.7 av dd v p -p biased at av dd /2 ; ac coupling ensures av dd /2 bias input capacitance 10 pf input current 60 a phase frequency detector (pfd) phase detector frequency 3 2 mhz f ract ional -n 45 mhz integer - n (band select enabled) 90 mhz integer - n (band select disabled) charge pump i cp sink/source 1 r set = 5.1 k ? high value 5 ma low value 0.312 ma r set range 3.9 10 k? sink and source current matching 2 % 0.5 v v cp 2. 5 v i cp vs. v cp 1.5 % 0.5 v v cp 2.5 v i cp vs. temperature 2 % v cp = 2.0 v logic inputs input high voltage, v inh 1. 5 v input low voltage, v inl 0.6 v input current, i inh /i inl 1 a input capacitance, c in 3.0 pf logic outputs output high voltage, v oh dv dd ? 0.4 v cmos output selected output high current, i oh 500 a output low voltage, v ol 0 .4 v i ol = 500 a power supplies av dd 3.0 3.6 v dv dd , v vco , sd v dd , v p av dd these voltages must equal av dd di dd + ai dd 2 21 27 ma output dividers 6 to 36 ma each output divide -by - 2 consumes 6 ma i vco 2 70 80 ma i rfout 2 21 26 ma rf output stage is programmable low power sleep mode 7 10 a rf output characteristics vco output frequency 2200 4400 mhz fundamental vco mode minimum vco output frequency using dividers 34. 37 5 mhz 2200 mhz fundamental output and divide -by -64 selected vco sensitivity , k v 40 mhz/v frequency pushing (open - loop) 1 mhz/v fr equency pulling (open - loop) 90 khz into 2.00 vswr load harmonic content (second ) ?19 dbc fundamental vco output ?20 dbc divided vco output harmonic content (third) ?13 dbc fundamental vco output ?10 dbc divided vco output
adf4351 data sheet rev. 0 | page 4 of 28 parameter min typ max unit test conditions/comments minimum rf output power 3 ?4 dbm programmable in 3 db steps maximum rf output power 3 5 dbm output power variation 1 db minimum vco tuning voltage 0.5 v maximum vco tuning voltage 2.5 v noise characteristics vco phase noise performance vco noise is measured in open - loop conditions ?89 dbc/hz 10 khz offset from 2.2 ghz carrier ?114 dbc/hz 100 khz offset from 2.2 ghz carrier ?134 dbc/hz 1 mhz offset from 2.2 ghz carrier ?148 dbc/hz 5 mhz offset from 2.2 ghz carrier ?86 dbc/hz 10 khz offset from 3.3 ghz carrier ?111 dbc/hz 100 khz offset from 3.3 ghz carrier ?134 dbc/hz 1 mhz offset from 3.3 ghz carrier ?145 dbc/hz 5 mhz offset from 3.3 ghz carrier ?83 dbc/hz 10 khz offset from 4.4 ghz carrier ?110 dbc/hz 100 khz offset from 4.4 ghz carrier ?131 dbc/hz 1 mhz offset from 4.4 ghz carrier ?145 dbc/hz 5 mhz offset from 4.4 ghz carrier normalized phase noise floor (pn synth ) 4 pll loop bw = 500 khz ?2 20 dbc/hz abp = 6 ns ?2 21 dbc/hz abp = 3 ns normalized 1/f noise (pn 1_f ) 5 10 khz of fset; normalized to 1 ghz ? 116 dbc/hz abp = 6 ns ? 118 dbc/hz abp = 3 ns in - band phase noise ? 100 dbc/hz 3 khz from 2111.28 mhz carrier integrated rms jitter 6 0. 27 ps spurious signals d ue to pfd frequency ? 8 0 dbc level of signal w ith rf mute enabled ?40 dbm 1 i cp is internally modified to maintain constant loop gain over the frequency range. 2 t a = 25c; av dd = dv dd = v vco = 3.3 v; prescaler = 8/9; f refin = 100 mhz; f pfd = 25 mh z; f rf = 4.4 ghz. 3 using 50 ? resistors to v vco , into a 50 ? load. power measured with auxiliary rf output disabled. the current consumption of the auxiliary output is the same as for the main output. 4 the synthesizer phase noise floor is estimated by me asuring the in - band phase noise at the output of the vco and subtracting 20 log n (where n is the n divider value) and 10 log f pfd . to calculate in - band phase noise performance as seen at the vco output, use the following formula: pn synth = pn tot ? 10 log( f pfd ) ? 20 log n . 5 the pll phase noise is composed of flicker (1/f) noise plus the normalized pll noise floor. the formula for calculating the 1 /f noise contribution at an rf frequency (f rf ) and at a frequency offset (f) is given by pn = pn 1_f + 10 log(10 khz/ f ) + 20 log( f rf /1 ghz). both the normalized phase noise floor and flicker noise are modeled in adisimpll . 6 f refin = 1 22.88 mhz; f pfd = 30.72 mhz; vco frequency = 4222.56 mhz; rf out = 2111.28 mhz; n = 1 37; loop bw = 6 0 khz ; i cp = 2.5 m a ; low noise mode. the noise was measured with an eval - adf4351eb1z and the rohde & schwarz fsup signal source analyzer.
data sheet adf4351 rev. 0 | page 5 of 28 timing characteristi cs av dd = dv dd = v vco = sdv dd = v p = 3.3 v 10%; agnd = dgnd = 0 v; 1.8 v and 3 v logic levels used; t a = t min to t max , unless otherwise noted. table 2 . parameter limit unit descript ion t 1 20 ns min le setup time t 2 10 ns min data to clk setup time t 3 10 ns min data to clk hold time t 4 25 ns min clk high duration t 5 25 ns min clk low duration t 6 10 ns min clk to le setup time t 7 20 ns min le pulse width timing diagram clk data le le db31 (msb) db30 db1 (control bit c2) db2 (control bit c3) db0 (lsb) (control bit c1) t 1 t 2 t 3 t 7 t 6 t 4 t 5 09800-002 figu re 2 . timing diagram
adf4351 data sheet rev. 0 | page 6 of 28 absolute maximum rat ings t a = 25c, unless otherwise noted. table 3 . parameter rating av dd to gnd 1 ?0.3 v to +3.9 v av dd to dv dd ?0.3 v to +0.3 v v vco to gnd 1 ?0.3 v to +3.9 v v vco to av dd ?0.3 v to +0.3 v digital i/o voltage to gnd 1 ?0.3 v to v dd + 0.3 v analog i/o voltage to gnd 1 ?0.3 v to v dd + 0.3 v ref in to gnd 1 ?0.3 v to v dd + 0.3 v operati ng temperature range ?40c to +85c storage temperature range ?65c to +125c maximum junction temperature 150c reflow soldering peak temperature 260c time at peak temperature 40 sec 1 gnd = agnd = dgnd = cp gnd = sd gnd = a gndvco = 0 v . stresses a bove those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specificat ion is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. this device is a high performance rf integrated circuit with an esd rating of < 1 .5 kv and is esd sensitive. proper precautions should be taken for handling and assembly. transistor count the transistor count for the adf4351 is 36,955 (cmos) and 986 (bipolar). thermal resistance thermal impedance ( ja ) is specified for a device with the exposed pad soldered to gnd. table 4 . thermal resistance package type ja unit 32 - lead lfcsp (cp - 32 - 2) 27.3 c/w esd caution
data sheet adf4351 rev. 0 | page 7 of 28 pin configuration an d function descripti ons 1 clk 2 data 3 le 4 ce 5 sw 6 7 24 v ref 23 v com 22 21 20 19 18 17 8 sdv dd adf4351 top view (not to scale) 9 agnd 10 av dd 11 ref in 12 dgnd 13 dv dd 14 15 16 32 31 30 29 28 sd gnd 27 26 25 pin 1 indicator v p cp out cp gnd muxout r set rf out a+ rf out b+ rf out b? rf out a? v vco v tune a gndvco a gndvco tem p pdb rf ld a gndvco v vco notes 1. the lfcsp has an exposed pad that must be connected to gnd. 09800-003 figure 3 . pin configuration ta ble 5 . pin function descriptions pin no. mnemonic description 1 clk serial clo ck input. d ata is clocked into the 32- bit shift register on the clk rising edge. this input is a high impedance cmos input. 2 data serial data input. th e serial data is loaded msb first with the three lsbs as the control bits. this input is a high impedance cmos input. 3 le load enable . when le goes high, the data stored in the 32- bit shift register is loaded into the register that is selected by the thr ee control bits . this input is a high impedance cmos input. 4 ce chip enable. a logic low on this pin powers down the device and puts the charge pump into three - state mode. a logic high on this pin powers up the device , depending on the status of the powe r - down bits. 5 sw fast lock switch. a connection should be made from the loop filter to this pin when using the fast lock mode. 6 v p charge pump power supply. v p must have the same value as av dd . place d ecoupling capacitors to the ground plane as close t o this pin as possible . 7 cp out charge pump output. when enabled, this output provides i cp to the external loop filter. the output of the loop filter is connected to v tune to drive the internal vco. 8 cp gnd charge pump ground. this output is the ground return pin for cp out . 9 a gnd analog ground. g round return pin for av dd . 10 av dd analog power supply. this pin ranges from 3.0 v to 3.6 v. place d ecoupling capacitors to the analog ground plane as close to this pin as possible . av dd must have the same val ue as dv dd . 11, 18, 21 a gndvco vco analog g round. g round return pins for the vco. 12 rf out a+ vco output. the output level is programmable. the vco fundamental output or a divided - down version is available. 13 rf out a? complementary vco output. the output level is programmable. the vco fundamental output or a divided - down version is available. 14 rf out b+ auxil iary vco output. the output level is programmable. the vco fundamental output or a divided - down version is available. 15 rf out b? complementary auxi liary vco output. the output level is programmable. the vco fundamental output or a divided - down version is available. 16, 17 v vco power supply for the vco. this pin ranges from 3.0 v to 3.6 v. place d ecoupling capacitors to the analog ground plane as clo se to these pins as possible . v vco must have the same value as av dd . 19 temp temperature compensation output. place decoupling capacitors to the ground plane as close to this pin as possible . 20 v tune control input to the vco. this voltage determines the output frequency and is derived from filtering the cp out output voltage.
adf4351 data sheet rev. 0 | page 8 of 28 pin no. mnemonic description 22 r set connecting a resistor between this pin and ground sets the charge pump output current. the nominal voltage bias at the r set pin is 0.55 v. the relationship between i cp and r set is as follows: i cp = 25.5/ r set where: r set = 5.1 k? . i cp = 5 ma . 23 v com internal compensation node . biased at h alf the t uning r ange. place decoupling capacitors to the ground plane as close to this pin as possible. 24 v ref reference voltage. place decoupling capacitors to the ground plane as close to this pin as possible. 25 ld lock detect output pin. a logic high output on this pin indicate s pll lock. a logic low output indicates loss of pll lock. 26 pdb rf rf power - down. a logic low on this pin mutes the rf outputs. this function is also softwa re controllable. 27 d gnd digital ground. ground return pin for dv dd . 28 dv dd digital power supply. dv dd must have the same value as av dd . place decoupling capacitors to the ground plane as close to this pin as possible. 29 ref in reference input. this cm os input has a nominal threshold of a v dd /2 and a dc equivalent input resistance of 100 k? . this input can be driven from a ttl or cmos crystal oscillator , or it can be ac - coupled. 30 mux out multiplexer output. th e multiplexer output allows the lock detect value , the n divider value, or the r counter value to be accessed externally. 31 sd gnd digital - modulator ground. ground return pin for the - modulator. 32 sdv dd power supply pin for the digital - modulator . sdv dd must have the same value as av dd . place decoupling capacitors to the ground plane as close to this pin as possible . ep e xposed pad exposed pad. the lfcsp has an exposed pad that must be connected to gnd.
data sheet adf4351 rev. 0 | page 9 of 28 typical performance characteristics ?160 ?150 ?140 ?120 ?100 ?80 ?130 ?110 ?90 ?70 ?60 ?50 ?40 1k 10k 100k 1m 10m phase noise (dbc/hz) frequency (hz) 09800-104 figure 4. open - l oop vco phase noise , 2.2 ghz ?160 ?150 ?140 ?120 ?100 ?80 ?130 ?110 ?90 ?70 ?60 ?50 ?40 1k 10k 100k 1m 10m phase noise (dbc/hz) frequency (hz) 09800-105 figure 5 . open - l oop vco phase noise , 3.3 ghz ?160 ?150 ?140 ?120 ?100 ?80 ?130 ?110 ?90 ?70 ?60 ?50 ?40 1k 10k 100k 1m 10m phase noise (dbc/hz) frequency (hz) 09800-106 figure 6 . open - l oop vco phase noise , 4.4 ghz ?170 ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 1k 10k 100k 1m 10m phase noise (dbc/hz) frequency (hz) div1 div2 div4 div8 div16 div32 div64 09800-107 figure 7 . closed - loop phase noise, fundamental vc o and dividers , vco = 2.2 ghz, pfd = 25 mhz, loop filter bandwidth = 63 khz ?170 ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 1k 10k 100k 1m 10m phase noise (dbc/hz) frequency (hz) div1 div2 div4 div8 div16 div32 div64 09800-108 figure 8 . closed - loop phase noise, fundamental vco and dividers , vco = 3.3 ghz, pfd = 25 mhz, loop filter bandwidth = 63 khz ?170 ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 1k 10k 100k 1m 10m phase noise (dbc/hz) frequency (hz) div1 div2 div4 div8 div16 div32 div64 09800-109 figure 9 . closed - loop phase noise, fundamen tal vco and dividers, vco = 4.4 ghz, pfd = 25 mhz, loop filter bandwidth = 63 khz
adf4351 data sheet rev. 0 | page 10 of 28 ?160 ?150 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 1k 10k 100k 1m 10m phase noise (dbc/hz) frequency (hz) 09800- 1 10 figure 10 . fractional - n spur performance, low noise mode, w - cdma band; rf out = 2111.28 mhz, ref i n = 122.88 mhz , pfd = 30.72 mhz , output divide - by - 2 selected; loop filter bandwidth = 6 0 khz, channel spacing = 24 0 khz ; rms phase error = 0.2 1 , rms jitter = 0. 27 ps, evm = 0.37 % ?160 ?150 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 1k 10k 100k 1m 10m phase noise (dbc/hz) frequency (hz) 09800- 11 1 figure 11 . fractional - n spur performance, low spur mode, w - cdma band; rf out = 2111.28 mhz, ref in = 122.88 mhz , pfd = 30.72 mhz , output divide - by - 2 selected; loop filter bandwidth = 6 0 khz, channel spacing = 24 0 khz ; rms phase error = 0.37 , rms jitter = 0.4 9 ps, evm = 0.64 % ?160 ?150 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 1k 10k 100k 1m 10m phase noise (dbc/hz) frequency (hz) 09800- 1 12 figure 12 . fractional - n spur performance, low noise mode, w - cdma band; rf out = 2111.28 mhz, ref in = 122.88 mhz , pfd = 30.72 mhz , output divide - by - 2 selected; loop filter bandwidth = 2 0 khz, channel spacing = 24 0 khz ; rms phase error = 0. 25 , rms jitter = 0. 32 ps, evm = 0. 44 % ?160 ?150 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 1k 10k 100k 1m 10m phase noise (dbc/hz) frequency (hz) 09800- 1 13 figure 13 . fractional - n spur performance, low noise mode, lte band; rf out = 2 646 . 96 mhz, ref in = 122.88 mhz , pfd = 30.72 mhz ; loop filter bandwidth = 6 0 khz, channel spacing = 24 0 khz ; phase word = 9, rms phase error = 0. 28 , rms jitter = 0. 29 ps, evm = 0. 49 % ?160 ?150 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 1k 10k 100k 1m 10m phase noise (dbc/hz) frequency (hz) 09800- 1 14 figure 14 . fractional - n spur performance, low spur mode, lte band; rf out = 2 646 . 96 mhz, ref in = 122.88 mhz , pfd = 30.72 mhz ; loop filter bandwidth = 6 0 khz, channel spacing = 24 0 khz ; rms phase error = 0. 56 , rms jitter = 0. 59 ps, evm = 0.98 % ?160 ?150 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 1k 10k 100k 1m 10m phase noise (dbc/hz) frequency (hz) 09800- 1 15 figure 15 . fractional - n spur performance, low noise mode, w - cdma band ; rf out = 2 646 . 96 mhz, ref in = 122.88 mhz , pfd = 30.72 mhz ; loop filter bandwi dth = 2 0 khz, channel spacing = 24 0 khz ; rms phase error = 0. 35 , rms jitter = 0. 36 ps, evm = 0. 61 %
data sheet adf4351 rev. 0 | page 11 of 28 circuit descrip tion reference input sect ion the reference input stage is shown in figure 16. the sw1 and sw2 s witches are normally closed. the sw3 switch is normally open. when power - down is initiated, sw3 is closed, and sw1 and sw2 are opened. in this way, no loading of the ref in pin occurs during power - down. buffer to r counter ref in 100k ? nc sw2 sw3 no nc sw1 power-down control 09800-005 figure 16 . reference input stage rf n divider the rf n divider allows a division ratio in the pll feedback path . the division ratio is determined by the in t, f rac , and mod values, which build up this divider (see figure 17) . third-order fractional interpolator mod value frac value int value rf n divider n = int + frac/mod from vco output/ output dividers to pfd n counter 09800-006 figure 17 . rf n divider int, frac, mod, and r counter relationship the int, frac, and mod values, in conjunction with the r counter, make it possible to generate output frequencies that are spaced by fractions of the pfd frequency. for more informa - tion, see th e rf synthesizer a worked example section. the rf vco frequency (rf out ) equation is rf out = f pfd ( int + ( frac / mod )) (1) where : rf out is the output frequency of the voltage co n trolled oscillator (vco). int is the preset divide ra tio of the binary 16 - bit counter (23 to 65,535 for the 4/5 prescaler ; 75 to 65,535 for the 8/9 prescaler ). frac is the numerator of the fractional division (0 to mod ? 1). mod is the preset fractional modulus (2 to 4095). the pfd frequency (f pfd ) equation is f pfd = ref in [ (1 + d )/( r (1 + t ))] ( 2 ) where: ref in is the reference input frequency. d is the ref i n doubler bit (0 or 1). r is the preset divide ratio of the binary 10- bit programmable refe r ence counter (1 to 1023 ). t is the ref in divide - by - 2 bit (0 or 1). int eger - n m ode if frac = 0 and the db8 (ldf) bit in register 2 is set to 1, the synthesizer opera tes in integer - n mode. the db8 bit in register 2 should be set to 1 for integer - n digital lock detect. r counter the 10 - bit r counter allows the input reference frequency (ref in ) to be divided down to produce the reference clock to the p fd. division ratio s from 1 to 1023 are allowed. phase frequency dete ctor (pfd) and charge pump the phase frequency detector (pfd) takes inputs from the r counter and n counter and produces an output proportional to the phase and frequency difference between them. figure 18 is a simplified schematic of the phase frequency detector. u3 clr2 q2 d2 u2 down up high high cp out ?in +in charge pump delay clr1 q1 d1 u1 09800-007 figure 18 . pfd simplified schematic the pfd includes a programmable delay element that sets the width of the antibacklash pulse (abp). this pulse ensures that there is no dead zone in the pfd transfer function. bit db22 in register 3 (r3) is used to set the abp as follows: ? when bit db22 is set to 0, the abp width is programmed to 6 ns, the recommended value for fractional - n applic ations . ? w hen bit db22 is set to 1, the abp width is programmed to 3 ns, the recommended value for integer - n applications. for integer - n applications, the in - band phase noise is improved by enabling the shorter pulse width. the pfd frequency can operate up to 90 mhz in this mode . to operate with pfd frequencies higher than 45 mhz , vco band select must be dis - abled by setting the phase a djust bit (db28) to 1 in register 1.
adf4351 data sheet rev. 0 | page 12 of 28 muxout and lock detect the multiplexer output on the adf4351 allows the user to access various internal points on the chip. the state of muxout is controlled by the m3, m2, and m1 bits in register 2 (see figure 26 ). figure 19 shows the muxout section in block diagram form. dgnd dv dd control mux muxout analog lock detect digital lock detect r counter output n divider output dgnd reserved three-state output dv dd 09800-008 figure 19 . muxout schematic input shift register s the adf4351 digital section includes a 10 - bit rf r counter, a 16 - bit r f n counter, a 12 - bit frac counter, and a 12 - bit modulus counter. data is clocked into the 32 - bit shift regi s ter on each rising edge of clk. the data is clocked in msb first. data is transferred from the shift register to one of six latches on the rising e dge of le. the destination latch is d e termined by the state of the three control bits (c3, c2, and c1) in the shift register. a s shown in figure 2 , the control bits are the three lsbs: db2, db1, and db0. table 6 shows t he truth table for these bits . figure 23 summarizes how the latches are pr o grammed. table 6 . truth table for the c3, c2, and c1 control bits con trol bits register c3 c2 c1 0 0 0 register 0 ( r0 ) 0 0 1 register 1 ( r1 ) 0 1 0 register 2 ( r2 ) 0 1 1 register 3 ( r3 ) 1 0 0 register 4 ( r4 ) 1 0 1 register 5 ( r 5) program modes table 6 and figure 23 through figure 29 show how the pr o gram modes are set up in the adf4351 . the following settings in the adf4351 are doub le buffered : phase value, modulus value, reference doubler, reference divide - by - 2, r counter value, and c harge pump c urrent setting. before the part uses a new value for any double - buffered setting, the following two events must occur: 1. t he new value is lat ched into the device by writi ng to the appropriate register. 2. a new write is performed on register 0 ( r0 ) . for example, any time that the modulus value is updated, register 0 (r0) must be written to, to ensure that the modulus value is loaded correctly. the divider select value in register 4 (r4) is also double buffered, but only if the db13 bit of register 2 (r2) is set to 1 . vco the vco core in the adf4351 consists of three separate vcos , each of which uses 16 overlapping bands, as shown in figure 20, to allow a wide frequency range to be covered without a large vco sensitivity (k v ) and resu l tant poor phase noise and spur - ious performance. 3.0 2.5 2.0 1.5 1.0 0.5 0 2.0 2.5 3.0 3.5 4.0 4.5 v tune (v) frequency (ghz) 09800-120 figure 20 . v tune vs. frequency the correct vco and band are selected automatically by the vco and band select logic at power - up or whenever register 0 (r0) is updated. vco and band selection take 10 pfd cycles multiplied by the value of the band select clock divider. the vco v tune is discon - nected from the output of the loop filter and is connected to an internal re f erence voltage.
data sheet adf4351 rev. 0 | page 13 of 28 the r counter output is used as the clock for the band select logic. a programmable divider is provided at the r counter outp ut to allow division by an integer from 1 to 255 ; the divider value is set using bits[ db19 : db12 ] in register 4 (r4). when the required pfd frequency is higher than 125 khz, the divide ratio should be set to allow enough time for correct band selection. ban d select ion takes 10 cycles of th e pfd frequency, equal to 8 0 s. if faster lock times are required, b it db23 in register 3 ( r3 ) must be set to 1 . this setting allows the user to select a higher band select clock frequency of up to 500 khz, which speeds up the minimum band select time to 20 s. for phase adjustments and small (<1 mhz) frequency adjustments, the user can disable vco band selection by setting bit db28 in register 1 (r1) to 1. this setting selects the phase adjust feature. after band sele c tion , normal pll action resumes. the nominal value of k v is 40 mhz/v when the n divider is driven from the vco output or from this value divided by d. d is th e output divider value if the n divider is driven from the rf divider output ( selected by programming bits[ d b2 2:d b20 ] in register 4 ) . the adf4351 contains lineariz a tion circuitry to minimize any vari - ation of the product of i cp and k v to keep the loop bandwidth constant. the vco shows variation of k v as the v t une varie s within the band and from band to band. f or wideband applications cover - ing a wide frequency range (and changing output dividers) , a value of 40 mhz/v provides the most accurate k v because this value is closest to an average value. figure 21 shows how k v varies with fundamental vco frequency , along with an average value for the frequency band. users may prefer this figure when using narrow - band designs. 80 70 60 50 40 30 20 10 0 2.0 2.5 3.0 3.5 4.0 4.5 vco sensitivity (mhz/v) frequency (ghz) 09800-121 figure 21 . vco sensitivity (k v ) vs. frequency output stage the rf out a+ and rf out a? pins of the adf4351 are connected to the collectors of an npn differential pair driven by buffered outputs of the vco, as shown in figure 22. vco rf out a+ rf out a? buffer/ divide-by-1/-2/-4/-8/ -16/-32/-64 09800-010 figure 22 . output stage to allow the user to optimize the power dissipation vs. the output power requirements, the tail current of the differential pair is programmable using bits[db4:db3] in register 4 (r4). four current levels can be set. these lev els give output pow er levels of ?4 dbm, ?1 dbm, +2 dbm, and +5 dbm, using a 50 ? resistor to av dd and ac coupling into a 50 ? load. alternatively, both outputs can be combined in a 1 + 1:1 transformer or a 180 microstrip coupler (see the output matching section). if the outputs are used individually, the optimum output stage consists of a shunt inductor to v vco . the unused complementary output must be terminated with a similar circuit to the used output. an auxiliary output stage ex ists on the rf out b+ and rf out b? pins , providing a second set of differential outputs that can be used to drive another circuit . the auxiliary output stage can be used only if the primary outputs are enabled. if the auxiliary output stage is not used, it can be powered down. another fe ature of the adf4351 is that the supply current to the rf output stage can be shut down until the part achieves lock , as measured by the digital lock detect circuitry. this feature is enabled by setting the mu te ti l l lock detect (mtld) bit in register 4 (r4).
adf4351 data sheet rev. 0 | page 14 of 28 register maps db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 n16 n15 n14 n13 n12 n11 n10 n9 reserved 16-bit integer value (int) 12-bit fractional value (frac) control bits n8 n7 n6 n5 n4 n3 n2 n1 f12 f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 c3(0) c2(0) c1(0) db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 ph1 pr1 p12 p11 p10 p9 12-bit phase value (phase) 12-bit modulus value (mod) control bits p8 p7 p6 p5 p4 p3 p2 p1 m12 m11 m10 m9 m8 m7 m6 m5 m4 m3 m2 m1 c3(0) c2(0) c1(1) db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 l2 l1 m3 m2 m1 rd2 rd1 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 d1 cp4 cp3 cp2 cp1 u6 u5 u4 u3 u2 u1 c3(0) c2(1) c1(0) csr rdiv2 reference doubler charge pump current setting 10-bit r counter control bits db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 f4 f3 f2 0 0 f1 0 c2 c1 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 c3(0) c2(1) c1(1) control bits 12-bit clock divider value ldp pd polarity power-down cp three- state counter reset output power clk div mode dbr 1 1 dbr = double-buffered register?buffered by the write to register 0. 2 dbb = double-buffered bits?buffered by the write to register 0, if and only if db13 of register 2 is high. reserved ldf reserved charge cancel abp band select clock mode reserved register 4 vco power- down db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 d13 d12 d11 d10 bs8 bs7 bs6 bs5 bs4 bs3 bs2 bs1 d9 d8 d7 d6 d5 d4 d3 d2 d1 c3(1) c2(0) c1(0) control bits 8-bit band select clock divider value rf output enable ld pin mode aux output enable aux output select mtld rf divider select feedback select register 0 register 1 register 2 register 3 register 5 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 d15 d14 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c3(1) c2(0) c1(1) control bits reserved reserved dbb 2 double buffer reserved reserved dbr 1 dbr 1 dbr 1 dbr 1 dbr 1 aux output power reserved reserved reserved prescaler phase adjust low noise and low spur modes muxout 09800-023 figure 23 . register summary
data sheet adf4351 rev. 0 | page 15 of 28 n16 n15 ... n5 n4 n3 n2 n1 integer value (int) 0 0 ... 0 0 0 0 0 not allowed 0 0 ... 0 0 0 0 1 not allowed 0 0 ... 0 0 0 1 0 not allowed . . ... . . . . . ... 0 0 ... 1 0 1 1 0 not allowed 0 0 ... 1 0 1 1 1 23 0 0 ... 1 1 0 0 0 24 . . ... . . . . . ... 1 1 ... 1 1 1 0 1 65,533 1 1 ... 1 1 1 1 0 65,534 1 1 ... 1 1 1 1 1 65,535 f12 f11 ... f2 f1 fractional value (frac) 0 0 ... 0 0 0 0 0 ... 0 1 1 0 0 ... 1 0 2 0 0 ... 1 1 3 . . ... . . . . . ... . . . . . ... . . . 1 1 ... 0 0 4092 1 1 ... 0 1 4093 1 1 ... 1 0 4094 1 1 ... 1 1 4095 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 n16 n15 n14 n13 n12 n11 n10 n9 reserved 16-bit integer value (int) 12-bit fractional value (frac) control bits n8 n7 n6 n5 n4 n3 n2 n1 f12 f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 c3(0) c2(0) c1(0) intmin = 75 with prescaler = 8/9 09800-012 figure 24 . re g ister 0 (r0) p12 p11 ... p2 p1 phase value (phase) 0 0 ... 0 0 0 0 0 ... 0 1 1 (recommended) 0 0 ... 1 0 2 0 0 ... 1 1 3 . . ... . . . . . ... . . . . . ... . . . 1 1 ... 0 0 4092 1 1 ... 0 1 4093 1 1 ... 1 0 4094 1 1 ... 1 1 4095 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 ph1 pr1 p12 p11 p10 p9 12-bit phase value (phase) 12-bit modulus value (mod) control bits p8 p7 p6 p5 p4 p3 p2 p1 m12 m11 m10 m9 m8 m7 m6 m5 m4 m3 m2 m1 c3(0) c2(0) c1(1) reserved m12 m11 ... ... ... ... ... ... ... ... ... ... m2 m1 interpolator modulus (mod) 0 0 1 0 2 0 0 1 1 3 . . . . . . . . . . . . . . . 1 1 0 0 4092 1 1 0 1 4093 1 1 1 0 4094 1 1 1 1 4095 prescaler phase adjust pr1 prescaler 0 4/5 1 8/9 ph1 phase adj 0 off 1 on dbr dbr 09800-013 figure 25 . register 1 (r1)
adf4351 data sheet rev. 0 | page 16 of 28 rd2 reference doubler 0 disabled 1 enabled rd1 reference divide-by-2 0 disabled 1 enabled c p4 c p3 c p2 c p1 i cp (ma) 5.1k? 0 0 0 0 0.31 0 0 0 1 0.63 0 0 1 0 0.94 0 0 1 1 1.25 0 1 0 0 1.56 0 1 0 1 1.88 0 1 1 0 2.19 0 1 1 1 2.50 1 0 0 0 2.81 1 0 0 1 3.13 1 0 1 0 3.44 1 0 1 1 3.75 1 1 0 0 4.06 1 1 0 1 4.38 1 1 1 0 4.69 1 1 1 1 5.00 r10 r9 ... ... ... ... ... ... ... ... ... ... r2 r1 r counter (r) 0 0 0 1 1 0 0 1 0 2 . . . . . . . . . . . . . . . 1 1 0 0 1020 1 1 0 1 1021 1 1 1 0 1022 1 1 1 1 1023 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 l2 l1 m3 m2 m1 rd2 rd1 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 d1 cp4 cp3 cp2 cp1 u6 u5 u4 u3 u2 u1 c3(0) c2(1) c1(0) rdiv2 dbr reference doubler dbr charge pump current setting 10-bit r counter dbr control bits ldp pd polarity power-down cp three- state counter reset ldf muxout double buffer u5 ldp 0 10ns 1 6ns u4 pd polarity 0 negative 1 positive u3 power-down 0 disabled 1 enabled u2 cp three-state 0 disabled 1 enabled u1 counter reset 0 disabled 1 enabled d1 double buffer r4 [db22:db20] 0 disabled 1 enabled u6 ldf 0 frac-n 1 int-n reserved m3 m2 m1 output 0 0 0 three-state output 0 0 1 dv dd 0 1 0 dgnd 0 1 1 r counter output 1 0 0 n divider output 1 0 1 analog lock detect 1 1 0 digital lock detect 1 1 1 reserved l2 l1 noise mode 0 0 low noise mode 0 1 reserved 1 0 reserved 1 1 low spur mode low noise and low spur modes 09800-014 figure 26 . register 2 (r2) c 2 c 1 clock divider mode 0 0 clock divider off 0 1 fast lock enable 1 0 resync enable 1 1 reserved d12 d11 ... d2 d1 clock divider value 0 0 ... 0 0 0 0 0 ... 0 1 1 0 0 ... 1 0 2 0 0 ... 1 1 3 . . ... . . . . . ... . . . . . ... . . . 1 1 ... 0 0 4092 1 1 ... 0 1 4093 1 1 ... 1 0 4094 1 1 ... 1 1 4095 csr db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 f4 f3 f2 f1 0 c2 c1 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 c3(0) c2(1) c1(1) control bits 12-bit clock divider value clk div mode reserved f1 cycle slip reduction 0 disabled 1 enabled f2 charge cancelation 0 disabled 1 enabled f4 band select clock mode 0 low 1 high f3 antibacklash pulse width 0 6ns (frac-n) 1 3ns (int-n) reserved 0 0 reserved charge cancel abp band select clock mode 09800-015 figure 27 . register 3 (r3)
data sheet adf4351 rev. 0 | page 17 of 28 bs8 bs7 ... ... ... ... ... ... ... ... ... ... bs2 bs1 band select clock divider 0 0 0 1 1 0 0 1 0 2 . . . . . . . . . . . . . . . 1 1 0 0 252 1 1 0 1 253 1 1 1 0 254 1 1 1 1 255 d3 rf out 0 disabled 1 enabled output power vco power- down db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 d13 d12 d11 d10 bs8 bs7 bs6 bs5 bs4 bs3 bs2 bs1 d9 d8 d7 d6 d5 d4 d3 d2 d1 c3(1) c2(0) c1(0) control bits 8-bit band select clock divider value rf output enable aux output power aux output enable aux output select mtld rf divider select feedback select reserved d 2 d 1 output power 0 0 ?4dbm 0 1 ?1dbm 1 0 +2dbm 1 1 +5dbm d5 d4 aux output power 0 0 ?4dbm 0 1 ?1dbm 1 0 +2dbm 1 1 +5dbm d6 aux out 0 disabled 1 enabled d7 aux output select 0 fundamental 1 divided output d8 mute till lock detect 0 mute disabled 1 mute enabled d9 vco power-down 0 vco powered up 1 vco powered down d12 d11 rf divider select 0 0 1 0 0 2 0 1 4 d10 0 1 0 0 1 8 1 1 0 16 0 1 0 32 1 1 1 64 0 d13 feedback select 0 fundamental 1 divided dbb 09800-016 figure 28 . register 4 (r4) db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 d15 d14 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c3(1) c2(0) c1(1) reserved reserved ld pin mode reserved control bits reserved d15 d14 lock detect pin operation 0 0 low 0 1 digital lock detect 1 0 low 1 1 high 09800-017 figure 29 . register 5 (r5)
adf4351 data sheet rev. 0 | page 18 of 28 register 0 control bits when bits[c3:c1] are set to 0 00 , register 0 is programmed. figure 24 shows the input data for mat for programming this regi s ter . 16- bit integer value (int) the 16 int bits (bits[db30:db15]) set the int value, which determines the i n teger part of the feedback d ivision factor. the int value is used in equation 1 (s ee the int, frac, mod, and r counter relationship section ) . i nteger values from 23 to 65,535 are allowed for the 4/5 prescaler ; f or the 8/9 prescaler, the minimum integer value is 75. 12- bit fractional value (frac) the 12 frac bits (bits[db14:db3]) set the numerator of the fraction that is input to the - mod u lator. this fraction , along with the int value , specifies the new frequency channel that the synthesizer locks to, as shown in the rf synthesizer a worked example sect ion. frac values from 0 to ( mod ? 1 ) cover channels over a frequency range equal to the pfd refer - ence frequency. r egister 1 control bits when bits[c3:c1] are set to 00 1, register 1 is programmed. figure 25 shows the input data fo r mat for programming this regi s ter . phase adjust the phase adjust bit (bit db28) enables adjust ment of the output phase of a given output frequency . when phase adjustment is enabled (bit db28 is set to 1) , the part does n ot perform vco band select ion or ph ase resync when register 0 is updated . when phase adjustment is disabled (bit db28 is set to 0 ), the part performs vco band selection and phase resync (if phase resync is enabled in register 3 , bits[db16:db15] ) when register 0 is updated . disabling vco ban d select ion is recommended only for fixed frequency applications or for frequency deviations of < 1 mhz from the originally selected frequency. prescaler value the dual - modulus prescaler (p/p + 1), along with the int, frac, and mod values , determines the ov erall division ratio from the vco output to the pfd input. the pr1 bit (db27) in register 1 set s the prescaler value. operating at cml lev els, the prescaler tak es the c lock from the vco output and divides it down for the counters. the prescaler is based o n a synchronous 4/5 core. when the prescaler is set to 4/5, the maximum rf frequency allowed is 3.6 ghz. therefore, when opera t ing the adf4351 above 3 .6 ghz, the prescaler must be set to 8/9. the pr e scaler lim its the int value as follows: ? p rescaler = 4/5: n min = 23 ? prescaler = 8/9 : n min = 75 12- bit phase value bits[db26:db15] control the phase word. the phase word must be less than the mod value programmed in register 1. the phase word is used to program the rf ou t put phase from 0 to 360 with a resolution of 360 /mod (s ee the p hase r esync section). in most appl i cations, the phase relationship between the rf signal and the reference is not important. in such applications, t he phase value can be used to optimize the fractional and sub - fractional spur le v els. for more information, s ee the spur consistency and fractional spur optimization section. if neither the phase resync nor the spurious optimizati on func - tion i s used, it is recommended th at the phase word be set to 1. 12- bit modulus value (mod) the 12 mod bits (bits[db14:db3]) set the fractional modulus. th e fractional modulus is the ratio of the pfd frequency to the channel step resolution on the rf output. for more inform a tion, s ee the 12- bit programmable modulus section. r egister 2 control bits when bits[c3:c1] are set to 0 1 0, register 2 is programmed. figure 26 shows the input data for mat for p rogramming this regi s ter . low noise and low spur mode s the noise mode on t he adf4351 is controlled by setting bits[db30: db29 ] in r egister 2 (s ee figure 26) . the noise mode allow s the user to optimize a design either for improved spurious performance or for improved phase noise pe r formance. when the low spur mode is selected , dither is enabled. dither randomizes the fractional quantization noise so that it rese m bles whit e noise rather than spurious noise. as a result, the part is optimized for improved spurious performance. l ow spur mode is normally used for fast - locking applications when the pll closed - loop bandwidth is wide . wide loop ban d width is a loop bandwidth great er than 1/10 of the rf out channel step resolu - tion (f res ). a wide loop filter does not att e nuate the spurs to the same level as a narrow loop bandwidth. for best noise performance, use the low noise mode option. when the low noise mode is selected, dither is disabled. t his mode ensures that the charge pump operates in an optimum region for noise performance. low noise mode is extremely useful when a narrow loop filter bandwidth is available. the synthesizer ensures extremely low noise, and the filter atten uates the spurs. figure 10 through figure 12 show the trade - offs in a typical w - cdma setup for different noise and spur settings. muxout the on - chip multiplexer is controlled by bits[ db28: db26] (s ee figure 26) . note that n counter output must be disabled for vco band selection to operate correctly.
data sheet adf4351 rev. 0 | page 19 of 28 reference doubler setting the db25 bit to 0 disables the doubler and feeds the ref in signal directly in to the 10 - bi t r counter. setting this bit to 1 multi - p lies the ref in frequency by a facto r of 2 before feeding it into the 10 - bit r counter. when the doubler is disabled, the ref in fal l ing edge is the active edge at the pfd input to the fractional synthesizer. when th e doubler is enabled, both the rising and falling edges of ref in become active edges at the pfd input. when the doubler is enabled and the low spur mode is selected , the in - band phase noise performance is sensitive to the ref in duty cycle. the phase noise degradation can be as much as 5 db for ref in duty cycles outside a 45% to 55% range. the phase noise is insensitive to the ref in duty cyc le in the low noise mode and when the doubler is disabled. the maximum allowable ref in frequency when the doubler is en abled is 30 mhz. rdiv 2 setting the db24 bit to 1 inserts a divide - by - 2 toggle flip - flop between the r counter and the pfd , which extends the maximum ref in input rate. this function allows a 50% duty cycle signal to appear at the pfd input, which is necessa ry for cycle slip reduction. 10- bit r counter the 10 - bit r counter (bits[db23:db14]) allows the input reference frequency (r e f in ) to be divided down to produce the reference clock to the pfd . division ratios from 1 to 1023 are allowed. double buffer the db 13 bit enables or disables double buffering of bits[ db22:db20] in register 4. for information about how double buffering works, see t he program modes section. charge pump current setting bits[ db12:db 9] set the charge pump current. this value should be set to the charge pump current that the loop filter is designed with (see figure 26). lock detect function ( ldf ) the db8 bit configures the lock detect function (ldf). the ldf controls the number of pfd cycle s monitored by the lock detect circuit to ascertain whether lock has been achieved. when db8 is set to 0, the number of pfd cycles monitored is 40. when db8 is set to 1, the number of pfd cycles monitored is 5. it is recom - mended that the db8 bit be set to 0 for fractional - n mode and to 1 for integer - n mode. lock detect precision (ldp) the lock detect precision bit (bit db7) sets the comparison window in the lock detect circuit. when db7 is set to 0, the comparison window is 10 ns; when db7 is set to 1, the window is 6 ns. the lock detect circuit goes high when n consecutive pfd cycles are less than the comparison window value; n is set by the ldf bit (db8). for example, with db8 = 0 and db7 = 0, 40 consecutive pfd cycles of 10 ns or less must occur before d igital lock detect goes high. for f ractional - n applications, the recommended setting for bits [db8:db7] is 00; f or integer - n applications , the recom - mended setting for bits [db8:db7] is 1 1. phase detector polarity the db6 bit sets the phase detector polarity . when a passive loop filter or a noninverting active loop filter is used, this bit should be set to 1. if an active filter with an inverting charac - teristic is used, this bit should be set to 0. power - down (pd) the db5 bit provides the programmable power - down mode. setting this bit to 1 performs a power - down. setting this bit to 0 returns the synthesizer to normal operation. i n software power - down mode, the part retains all information in its registers. t he register contents are lost only if the supply vol tages are removed . when power - down is activated, the following events occur: ? s ynthesizer counters are forced to their load state co n ditions. ? vco is powered down. ? c harge pump is forced into three - state mode. ? d igital lock detect circuitry is reset. ? rf out buf fers are disabled . ? i nput register s remain active and capable of loading and latching data. charge pump three - state setting the db4 bit to 1 puts the ch arge pump into three - state mode . this bit should be set to 0 for normal operation. counter reset the db3 bit is the reset bit for the r counter and the n counter of the adf4351 . when this bit is set to 1, the rf synthesizer n counter and r counter are held in reset. for normal opera - tion, this bit should be set t o 0. r egister 3 control bits when bits[c3:c1] are set to 0 1 1, register 3 is programmed. figure 27 shows the input data for mat for programming this regi s ter. band select clock mode setting the db23 bit to 1 selects a faster logic s equence of band select ion, which is suitable for high pfd frequencies and is necessary for fast lock applications. setting the db23 bit to 0 is recommended for low pfd (<125 khz) values. for the faster band select logic modes (db23 set to 1), t he value of the band select clock divider must be less than or equal to 254. anti backlash p ulse w idth (abp) bit db22 sets the pfd antibacklash pulse width. when bit db22 is set to 0, the pfd anti backlash pulse width is 6 ns. this setting is recommended for fractional - n use. when bit db22 is set to 1, the pfd anti backlash pulse width is 3 ns , which result s in phase noise and spur improvement s in integer - n operation. for fractional - n operation, the 3 ns setting is not recommended .
adf4351 data sheet rev. 0 | page 20 of 28 charge cancelation setting the db21 bit to 1 enables charge p ump charge cancel - ation. this has the effect of reducing pfd spurs in integer - n mode. in fractional - n mode, this bit should be set to 0. csr enable setting the db18 bit to 1 enables cycle slip reduction. csr is a me thod for improving lock times . note that the signal at the phase frequency detector (pfd) must have a 50% duty cycle for cycle slip reduction to work. the charge pump current se t ting must also be set to a minimum. f or more information , s ee the cycle slip reduction for faster lock times section . clock divider mode bits[ db16:db15] must be set to 10 to activat e phase resync (see the p hase r esync section). t hese bits must be set to 0 1 to activate fast lock ( see the fast lock timer and register sequences section ) . setting bits[ db16 :db15] to 0 0 disables the clock divider (s ee figure 27). 12- bit clock divider value bits[db14:db3] se t the 12 - bit clock divider value. this value is the timeout counter for act i vation of phase r esync (see th e p hase r esync section ) . the clock divider value also sets the timeout counter for fast lock (see the fast lock timer and register sequences section) . r egister 4 control bits when bits[c3:c1] are set to 1 00 , register 4 is programmed. figure 28 shows the input data for mat for programming this reg i s ter . feedback s elect the db23 bit selects the feedback from the vco output to the n counter. when this bit is set to 1, the signal is taken directly from the vco. when this bit is set to 0, the signal is taken from the output of the output dividers. the dividers enable cover age of the wide frequency band ( 34. 37 5 mhz to 4.4 ghz). when the divider s are enabled and the feedback signal is taken from the output, the rf output signals of two separately configured plls are in phase. this is useful in some applic ations where the positive interference of signals is required to increase the power. rf divider select bits[ db22:db20] select the value of the rf output divider (see figure 28 ). band select clock divider value bits [ db19:db12] set a divider for the band select logic clock input. by default, t he output of the r counter is the value used to clock the band select logic, but, if this value is too high (>125 khz), a divider can be switched on to divide the r counter outpu t to a smaller value (see figure 28 ). vco power - down setting the db11 bit to 0 powers the vco up; setting this bit to 1 powers the vco down . mute til l lock detect (mtld) when the db10 bit is set to 1, the supply cu rrent to the rf output stage is shut down until the part achieves lock , as measured by the digital lock detect circuitry. aux output select the db9 bit sets the auxiliary rf output. if db9 is set to 0, the auxiliary rf output is the output of the rf divide rs; if db9 is set to 1, the auxiliary rf output is the fundamental vco frequency. aux output enable the db8 bit enables or disables the auxiliary rf output . if db8 is set to 0, the auxiliary rf outpu t is disabled; if db8 is set to 1, the auxiliary rf outpu t is enabled . aux output power bits[ db7:db6] set the valu e of the auxiliary rf output power level (see figure 28). rf output enable the db5 bit enables or disables the primary rf output . if db5 is set to 0, the primary rf outpu t i s disabled; if db5 is set to 1, the primary rf outpu t is enabled . output power bits[ db4:db3] set the value of the primary rf output power level (see figure 28). register 5 control bits when bits[c3:c1] are set to 10 1, register 5 i s programmed. figure 29 shows the input data form at for programming this register. lock detect pin operation bits[ db 23: db22 ] set the o peration of the lock detect (ld) pin (see figure 29). register initialization seque nce at initial power - up, after the correct application of voltages to the supply pins, the adf4351 registers should be started in the following sequence: 1. register 5 2. register 4 3. regi ster 3 4. register 2 5. register 1 6. register 0
data sheet adf4351 rev. 0 | page 21 of 28 rf synthesizer a worked example the following equations are used to program the adf4351 synthesizer: rf out = [ int + ( frac / mod )] ( f pfd / rf d ivider ) (3 ) where: rf out is the rf frequency output. int is the integer division factor. frac is the numerator of the fractional division (0 to mod ? 1). mod is the preset fractional modulus (2 to 4095). rf d ivider is the output divider that divides down the vco frequency. f pfd = ref in [ (1 + d )/( r (1 + t ))] ( 4 ) where: ref in is the reference frequency input. d is the rf ref in doubler bit (0 or 1) . r is the rf reference division factor (1 to 1023) . t is the refe rence divide - by - 2 bit (0 or 1) . as an example, a umts system requires a 2112.6 mhz rf frequency output (rf out ) ; a 10 mhz reference frequency input (ref in ) is available and a 200 khz c hannel resolution (f resout ) is required on the rf output. note that the adf4351 vco operates in the frequency range of 2.2 ghz to 4.4 ghz. therefore, the rf divider of 2 should be used (vco frequency = 4225.2 mhz, rf out = vco frequency/ rf divider = 4225.2 mhz/2 = 2112.6 mhz). it is also important where the loop is closed. in this example, the loop is closed before the output divider (see figure 30). f pfd pfd vco n divider 2 rf out 09800-027 figure 30 . loop closed before output divider channel resolution (f resout ) of 200 khz is required at the output of the rf divider. therefore, the channel resolution at the output of the vco ( f res ) needs to be 2 f resout , that is , 400 khz. mod = ref in / f res mod = 1 0 mhz / 40 0 khz = 25 from equation 4, f pfd = [10 mhz (1 + 0 )/ 1] = 10 mhz (5) 2112.6 mhz = 10 mhz [( int + ( frac /25))/2] (6) where: int = 422. frac = 13. reference doubler an d reference divider the on - chip reference doubler allows the input reference si gnal to be doubled. doubling the reference signal doubles the pfd comparison frequency, which improves the noise performance of the system. doubling the pfd frequency usually improves noise performance by 3 db. n ote that in fractional - n mode , the pfd canno t operate above 32 mhz due to a limitation in the sp eed of the - circuit of the n divider. for integer - n applications, the pfd can operate up to 90 mhz. the reference divide - by - 2 divides the reference signal by 2, resulting in a 50% duty cycle pfd freque ncy. this is necessary for the correct operation of the cycle slip reduction (csr) function. f or more information , s ee the cycle slip reduction for faster lock times section. 12- bit programmable mod ulus the choice of modulus (mod) depends on the reference signal (ref in ) available and the channel resolution (f res ) required at the rf ou t put. for example, a gsm system with 13 mhz ref in sets the modulus to 65. this means th at th e rf output resolution (f res ) is the 200 khz (13 mhz/65) n ecessary for gsm. with dither off, the fractional spur interval depends on the selected modulus values (see table 7 ). unlike most other fractional - n plls, the adf4351 allows the user to program the modulus over a 12 - bit range. w hen com - bined with the reference do ubler and the 10 - bit r counter, the 12- bit modulus allows the user to set up the part in many different configurations for the application. for example , conside r an application that requires a 1.75 ghz rf frequency output with a 200 khz channel step resolution. the system has a 13 mhz reference signal. one possible setup is to feed the 13 mhz reference signal directly in to the pfd and to program the modulus to di vide by 65. this results in the required 200 khz resolution. another possible setup is to use the reference doubler to create 26 mhz from the 13 mhz input signal. th e 26 mhz is then fed into the pfd , and the modulus is programmed to divide by 130. this se tup also results in 200 khz resolution but offers superior phase noise performance over the first setup. the programmable modulus is also very useful fo r multi - standard applications. for example, i f a dual - mode phone requires pdc and gsm 1800 standards, th e programmable modulus is of great benefit. pdc requires 25 khz channel step resolution, whereas gsm 1800 requires 200 khz channel step resolution. a 13 mhz reference signal can be fed directly to the pfd, and the modulus can be programmed to 520 when in p dc mode (13 mhz/520 = 25 khz). the modulus must be reprogrammed to 65 for gsm 1800 opera - tion (13 mhz/65 = 200 khz).
adf4351 data sheet rev. 0 | page 22 of 28 it is important that the pfd frequency remain constant ( in this example, 13 mhz). this allows the user to design one loop filter for both setups without encountering stability issues. note that the ratio of the rf frequency to the pfd frequency principally affects the loop filter design, not the actual channel spacing. cycle slip reduction for faster lock time s as described in the low noise and low spur modes section, the adf4351 contains a number of features that allow optimization for noise performance. however, in fast - locking applications, the loop b andwidth generally needs to be wide and, therefore, the filter does not provide much attenuation of the spurs. if the cycle slip reduction feature i s enabled, the narrow loop band - width is maintained for spur attenuation, but faster lock times are still po ssible. cycle slips cycle slips occur in integer - n/fractional - n synthesizers when the loop bandwidth is narrow compared to the pfd frequency. the phase error at the pfd inputs accumulates too fast for the pll to correct, and the charge pump temporarily pum ps in the wrong direction. this slows down the lock time dramatically. the adf4351 contains a cycle slip reduction feature that extends the linear range of the pfd, allowing faster lock times without modificat ions to the loop filter circuitry. when the circuitry detects that a cycle slip is about to occur, it turns on an extra charge pump current cell. this cell outputs a constant cu r rent to the loop filter or removes a constant current from the loop filter (de pending on whether the vco tuning voltage needs to increase or decrease to acquire the new frequency). the effect is that the linear range of the pfd is i n creased. loop s tability is maintained because the current is constant and is not a pulsed current. if the phase error increases again to a point where another cycle slip is likely, the adf4351 turns on another charge pump cell. this continues until the adf4351 de tects that the vco fre - quency has exceeded the desired frequency. the extra charge pump cells are turned off one by one until all the extra charge pump cells are disabled and the frequency settles to the original loop filter bandwidth. up to seven extra ch arge pump cells can be turned on. in most applications, seven cells are enough to eliminate cycle slips altogether, providing much faster lock times. setting bit db18 in register 3 to 1 enables cycle slip reduction. note that the pfd requires a 45% to 55% dut y cycle f or csr to operate correctly. if the ref in frequency does not have a suitable duty cycle, enabling the rdiv2 mode (bit db24 in register 2) ensures that the input to the pfd has a 50 % dut y cycle. spurious optimizatio n and fast lock narrow loop bandwidths can filter unwanted s purious signals , but these bandwidths usually have a long lock time. a wider loop bandwidth achieve s fast er lock times but may lead to increased spurious signals inside the loop bandwidth . the fast lock feature can achieve the same fast lo ck time as the wider bandwidth but with the advantage of a narrow final loop bandwidth to keep spurs low. fast lock timer and regis ter sequences if the fast lo ck mode is used, a timer value must be loaded into the pll to determine the durat ion of the wide bandwidth mode. when bits[db16:db15] in register 3 are set to 01 (fast lock enable) , the timer value is loaded by the 12 - bit clock divider value (bits[db14:db3] in register 3) . t he following sequence must be programmed to use fast lock : 1. sta rt the initialization sequence (see the register initialization sequence section) . this sequence occurs only once after powering up the part. 2. load register 3 by setting bits[db16:db15] to 0 1 and by setting the sele cted fast lo ck timer value (bits [db14:db3] ) . t he duration that the pll remains in wide bandwidth mode is equal to the fast lo ck timer/f pfd . fast lock example if a pll has a reference frequency of 13 mhz, f pfd of 13 mhz, and a required lock time of 6 0 s, t he pll is set to wide band width mode for 2 0 s . this example assumes a modulus of 65 for channel spacing of 200 khz. the vco calibration time of 20 s must also be taken into account (achieved by programming the higher band select clock mode using bit db23 of register 3). if the time set for the pll lock time in wide bandwidth mode is 2 0 s , then fast lock timer value = ( vco band select t ime + pll lock time in wide bandwidth ) f pfd / mod fast lock timer value = ( 2 0 s + 2 0 s ) 13 mhz /65 = 8 therefore, a v alue of 8 m ust be loaded into the clock divider value in r egister 3 (see step 2 in the fast lock timer and register sequences section ) .
data sheet adf4351 rev. 0 | page 23 of 28 fast lock loop filter topology to use fast lock mode, the damping resistor in the loop filter is reduced to one-fourth its value while in wide bandwidth mode. to achieve the wider loop filter bandwidth, the charge pump current increases by a factor of 16; to maintain loop stability, the damping resistor must be reduced by a factor of one-fourth. to enable fast lock, the sw pin is shorted to the agnd pin by setting bits[db16:db15] in register 3 to 01. the following two topologies are available: ? the damping resistor (r1) is divided into two values (r1 and r1a) that have a ratio of 1:3 (see figure 31). ? an extra resistor (r1a) is connected directly from sw, as shown in figure 32. the extra resistor is calculated such that the parallel combination of the extra resistor and the damping resistor (r1) is reduced to one-fourth the original value of r1 (see figure 32). adf4351 cp out sw c1 c2 r2 r1 r1a c3 vco 09800-018 figure 31. fast lock loop filter topology 1 adf4351 cp out sw c1 c2 r2 r1 r1a c3 vco 09800-019 figure 32. fast lock loop filter topology 2 spur mechanisms this section describes the three different spur mechanisms that arise with a fractional-n synthesizer and how to minimize them in the adf4351 . fractional spurs the fractional interpolator in the adf4351 is a third-order - modulator with a modulus (mod) that is programmable to any integer value from 2 to 4095. in low spur mode (dither on), the minimum allowable value of mod is 50. the - modulator is clocked at the pfd reference rate (f pfd ), which allows pll output frequencies to be synthesized at a channel step resolution of f pfd /mod. in low noise mode (dither off), the quantization noise from the - modulator appears as fractional spurs. the interval between spurs is f pfd /l, where l is the repeat length of the code sequence in the digital - modulator. for the third-order - modulator used in the adf4351 , the repeat length depends on the value of mod (see table 7). table 7. fractional spurs with dither off (low noise mode) mod value (dither off) repeat length spur interval mod is divisible by 2, but not by 3 2 mod channel step/2 mod is divisible by 3, but not by 2 3 mod channel step/3 mod is divisible by 6 6 mod channel step/6 mod is not divisible by 2, 3, or 6 mod channel step in low spur mode (dither on), the repeat length is extended to 2 21 cycles, regardless of the value of mod, which makes the quantization error spectrum look like broadband noise. this may degrade the in-band phase noise at the pll output by as much as 10 db. for lowest noise, dither off is a better choice, particularly when the final loop bandwidth is low enough to attenuate even the lowest frequency fractional spur. integer boundary spurs another mechanism for fractional spur creation is the inter- actions between the rf vco frequency and the reference frequency. when these frequencies are not integer related (the purpose of a fractional-n synthesizer), spur sidebands appear on the vco output spectrum at an offset frequency that corre- sponds to the beat note, or difference frequency, between an integer multiple of the reference and the vco frequency. these spurs are attenuated by the loop filter and are more noticeable on channels close to integer multiples of the reference, where the difference frequency can be inside the loop bandwidth (thus the name integer boundary spurs). reference spurs reference spurs are generally not a problem in fractional-n synthesizers because the reference offset is far outside the loop bandwidth. however, any reference feedthrough mechanism that bypasses the loop may cause a problem. feedthrough of low levels of on-chip reference switching noise, coupling to the vco, can result in reference spur levels as high as ?80 dbc. the pcb layout must ensure adequate isolation between vco circuitry and the input reference to avoid a possible feedthrough path on the board.
adf4351 data sheet rev. 0 | page 24 of 28 spur consistency and fractional spur optimization with dither off, the fractional spur pattern due t o the quantiz a - tion noise of the - modulator also depends on the particular phase word with which the modulator is seeded. the phase word can be varied to optimize the fractional and subfractional spur levels on any par ticular frequency. thus, a look up table of phase values corresponding to each frequency can be c rea ted for use when programming the adf4351 . if a look up table is not used, keep the phase word at a co n stant value to ensure consistent spur level s on any particular frequency. p hase r esync the output of a fractional - n pll can settle to any one of the mod phase offsets with respect to the input reference, where mod is the fractional modulus. the phase resync feature of the adf4351 produces a consistent output phase offset with respect to the input reference. this phase offset is necessary in applic a tions where the output phase and frequency are important, such as digital beamforming. see the p hase programmability section to program a specific rf output phase when u s ing phase resync. phase resyn c is enabled by setting bits[db16:db15] in register 3 to 10 . when phase resync is enabled, an inte r nal timer generates s ync signals at intervals of t sync given by the following formula: t sync = clk_div_value mod t pfd where: clk_div_value is the decim al value programmed in bits[db14:db3 ] of register 3 . this value can be any integer from 1 to 4095. mod is the modulus valu e pr ogrammed in bits[db 14: db 3] of register 1 (r1) . t pfd is the pfd reference period. when a new frequency is programmed, the second sync pulse after the le rising edge is used to resynchronize the output phase to the reference. the t sync time must be prog rammed to a value that is a t least as long as the worst - case lock time. this guarantees th at th e phase resync occurs after the last cycle slip in the pll settling transient. in the example shown in figure 33 , the pfd reference is 25 mhz and mod = 125 for a 200 khz channel spacing. t sync is set to 400 s by programming clk_div_value = 80. le phase frequency sync (internal) ?100 0 100 200 1000 300 400 500 600 700 800 900 time (s) pll settles to correct phase after resync t sync last cycle slip pll settles to incorrect phase 09800-020 figure 33 . phase resync example p hase programmability the phase word in register 1 controls the r f output phase. as this word is swept from 0 to mod, the rf output phase sweeps over a 360 range in steps of 360/mod. in many applications, it is advisable to disable vco band selec tion by setting bit db28 in register 1 (r1) to 1. this setting selects th e phase adjust feature. high pfd frequencies vco band select ion is required to ensure that the correct vco band is chosen for the relevant frequency. vco band select ion can operat e with pfd frequencies up to 45 mhz using the high vco band select mode ( set bit db23 in register 3 to 1) . for pfd frequencies higher than 45 mhz , it is recommended that the user perform the following steps: 1. program the desired vco frequency with phase adjust ment disabled ( set bit db28 in register 1 to 0 ). ensure that the pfd frequ ency is less than 45 mhz. 2. after the correct frequency is achieved, enable phase adjust - ment ( set bit db28 in register 1 to 1) . 3. pfd frequencies higher than 32 mhz are permissible only with integer - n applications; therefore, set the antibacklash pulse width to 3 ns (set bit db22 in register 3 to 1). 4. using the desired pfd frequency , program the a ppropriate values for the r eference r and feedback n counters. using this procedure , the lowest rms in - band phase noise can be achieved.
data sheet adf4351 rev. 0 | page 25 of 28 applications informa tion direct conversion mo dulator direct conversion architectures are increasingly being used to implement base station transmitters. figure 34 shows how analog devices, inc., parts can be u sed to implement such a syste m. figure 34 shows the ad9788 t xdac? used with the adl5375 . the use of dual int egrated dacs, such as the ad9788 with i ts specified 2% fsr and 0.001 % fsr gain and offset character - istics, ensures minimum error contr i bution (over temperature) from this portion of the signal chain. the local oscillator (lo) is implemented using the adf4351 . the low - pass filter was designed using adisimpll ? for a channel spacing of 200 khz and a c losed - loop bandwidth of 35 khz. the lo ports of the adl5375 can be driven differentially from the complementary rf out a outputs of the adf4351 . this setup provides better performance than a single - ended lo driver and elimina tes the use of a balun to convert from a single - ended lo input to the more desirable differential lo input for the adl5375 . the typical rms phase noise (100 hz to 5 mhz) of the lo in this configuration is 0.61 rms. the adl5375 accepts lo drive levels from ? 6 dbm to +6 dbm. the optimum lo power can be soft ware programmed on the adf4351 , which allows levels from ?4 dbm to +5 dbm from each output. the rf output is designed to drive a 50 ? load , but it must be ac - coupled, as shown in figure 34 . if the i and q inputs are driven in quadrature by 2 v p - p signals, the resulting output power from the adl5375 modulator is approximately 2 dbm. 09800-034 ad9788 txdac modulated digital data out2_n out1_p out1_n out2_p low-pass filter low-pass filter 2700pf 1200pf 39nf 680 ? 360 ? ibbp ibbn qbbp qbbn loip loin spi-compatible serial bus adf4351 v vco v vco cp gnd agnd dgnd rf out b? rf out b+ cp out 1nf 1nf 4.7k ? r set le data clk ref in f refin v tune dv dd av dd ce muxout 10 28 16 29 1 2 3 22 8 31 9 11 18 21 27 v dd lock detect 51 ? 51 ? 51 ? 51 ? 51 ? a gndvco 14 15 19 23 24 25 30 ld 17 20 7 pdb rf 26 sd gnd temp v com v ref 6 32 sdv dd v p 5 sw 10pf 0.1 f 10pf 0.1 f 10pf 0.1 f 4 adl5375 rfout quadrature phase splitter dsop rf out a? rf out a+ 13 12 1nf 1nf 3.9nh 3.9nh v vco lpf lpf figure 34 . direct conversion modulator
adf4351 data sheet rev. 0 | page 26 of 28 interfacing to the ad u c70 xx and the adsp - bf527 the adf4351 has a simple spi - compatible serial interface for writing to the device. the clk, data, and le pins control the data transfer. when le goes high, the 32 bits that were clocked into the appropriate register on each ri sing edge of clk are transferred to the appropriate latch. see figure 2 for the timing diagram and table 6 for the register address table. aduc70xx interface figure 35 shows the interface between the adf4351 and the aduc70xx family of analog microcontrollers . t he aduc70xx family is based on an amr7 core, but th e same interface can be used with any 8051 - based mi crocontroller. aduc70xx adf4351 clk data le ce muxout (lock detect) sclock mosi i/o ports 09800-035 figure 35 . aduc70xx to adf4351 interface the m i crocontroller is set up for spi master mode with cpha = 0. to initiate the operation, the i/o port driving le is broug ht low. each latch of the adf4351 needs a 32 - bit word, wh ich is accomplished by w riting four 8 - bit bytes from the m i cro - controller to the device. after the fourth byte is written, the le input should be brought high to co m plete the transfer. when power is first applied to the adf4351 , the part requires six writes (one each to r5, r4, r3, r2, r1, and r0) for the output to become active. i/o port lines on the microcontroller are also used to control the power - down input (ce) and to detect lock (muxout configured as lo ck detect and polled by the port input). when operating in the mode described, the maximum spi transfer rate of the aduc70xx is 20 mbps. this means that the maximum rate at which the output frequency can be cha nged is 833 khz. if using a faster spi clock , make sure th at th e spi timing requirements listed in table 2 are adhered to. adsp - bf527 interface figure 36 shows the interface between the adf4351 and the blackfin ? adsp - bf527 digital signal processo r (dsp) . the adf4351 needs a 32 - bit serial word for each latch write. the easiest way to accomplish this using the blackfin family is to use the autobuffered transmit mode of operation with alternate framing. this mode provides a means for transmitting an en tire block of serial data before an interrupt is ge n erated. adsp-bf527 adf4351 ce muxout (lock detect) i/o ports clk sck data mosi le gpio 09800-036 figure 36 . adsp - bf527 to adf4351 interface set up the word length for ei ght bits and use four memory loc a tions for each 32 - bit word. to program each 32 - bit latch, store the four 8 - bit bytes, enable the autobuffered mode, and write to the transmit register of the dsp. this last operation initiates the autobu f fer transfer. make sure that the spi timing requirements listed in table 2 are adhered to. pcb design guideline s for a chip scale package the lands on the chip scale package (cp - 32- 2 ) are rectangu lar. the pcb pad for these lands must be 0.1 mm longe r than the package land length and 0.05 mm wider than the package land width. each land must be centered on the pad to ensure t h at th e sol der joint size is maximized. the bottom of the chip scale package has a central exposed thermal pad. the thermal pad o n the pcb must be at least as large as the exposed pad. on the pcb, there must be a minimum clearance of 0.25 mm between the thermal pad and the inner edges of the pad pattern to ensure that shorting is avoided. thermal vias can be used on the pcb thermal pad to improve the thermal performance of the package. if vias are used, they must be incorporated in to the thermal pad at 1.2 mm pitch grid. the via diameter must be between 0.3 mm and 0.33 mm, and the via barrel must be plated with 1 oz. of copper to plu g the via.
data sheet adf4351 rev. 0 | page 27 of 28 output matching for optimum operation, the output of the adf4351 can be matched in a number of ways; the most basic method is to con - nect a 50 ? resistor to v vco . a dc bypass capacitor of 100 pf is co n nected in series , as shown in figure 37 . because the resistor is not frequency dependent, this method provides a good broad - band match. when connected to a 50 ? load, this circuit typically gives a differential output power equal to the value selected by bits[db4:db3] in register 4 (r4) . 100pf 09800-037 rf out v vco 50? 50? figure 37 . simple output stage a better solution is to use a shunt inductor (acting as an rf choke) to v vco . this solution gives a better match and, t herefore, more ou t put power. experiments have shown th at th e circuit shown in figure 38 provides an e x cellent match to 50 ? for the w - cdma umts band 1 (2110 mhz to 2170 mhz) . the maximum outp ut power in th is case i s approximately 5 dbm. both single - ended archi - tec tures can b e examined using the eval - adf4351 eb1z evalu a tion board. 3.9nf 1nf 09800-038 rf out v vco 50? figure 38 . opt imum output stage if differential outputs are not need ed , the unused ou t put can be terminate d , or both outputs can be combine d using a balun . a balun using discrete inductors and capacitors can be imple - mented with the architecture shown in figure 39. the lc balun comprises component l1 and component c1. l2 provides a dc path for rf out a?, and capacitor c2 is used for dc blocking. l1 l1 c1 c1 50? rf out a+ rf out a? v vco c2 l2 09800-039 figure 39 . lc balun for the adf4351 table 8 . lc balun components frequency range (mhz) inductor l1 (nh) capacitor c1 (pf) rf choke inductor l2 (nh) dc blocking capacitor c2 (pf) measured output power (dbm) 137 to 300 100 10 390 1000 9 300 to 460 51 5.6 180 120 10 400 to 600 30 5.6 120 120 10 600 to 900 18 4 68 120 10 860 to 1240 12 2.2 39 10 9 1200 to 1600 5.6 1.2 15 10 9 1600 to 3600 3.3 0.7 10 10 8 2800 to 3800 2.2 0.5 10 10 8
adf4351 data sheet rev. 0 | page 28 of 28 outline dimensions 3.25 3.10 sq 2.95 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. compliant t o jedec s t andards mo-220-vhhd-2 1 32 8 9 25 24 17 16 coplanarit y 0.08 3.50 ref 0.50 bsc pin 1 indic a t or pin 1 indic a t or 0.30 0.25 0.18 0.20 ref 12 max 0.80 max 0.65 ty p 1.00 0.85 0.80 0.05 max 0.02 nom sea ting plane 0.50 0.40 0.30 5.00 bsc sq 4.75 bsc sq 0.60 max 0.60 max 0.25 min 03-28-2012- a t op view exposed p ad bot t om view figure 40 . 32 - lead lead frame chip scale package [lfcsp_vq] 5 mm 5 mm body, very thin quad (cp - 32 - 2) dimensions show n in millimeters ordering guide model 1 temperature range package description package option adf4351 bcpz ?40c to +85c 32- lead lead frame chip scale package [lfcsp_vq] cp -32-2 adf4351 bcpz - rl7 ? 40c to +85c 32- lead lead frame chip scale package [lfcsp_v q] cp -32-2 eval - adf4351 eb1z evaluation board 1 z = rohs compliant part. ? 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09800 - 0 - 5/12(0)

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