UM10562 lpc408x/407x user manual rev. 1 ? 13 september 2012 user manual document information info content keywords lpc4088fbd208, lpc4088fet208, lpc4088fet180, lpc4088fbd144, lpc4078fbd208, lpc4078fet208, lpc4078fbd144, lpc4078fbd80, lpc4076fet180, lpc4074fbd144, lpc4074fbd80, arm, arm cortex-m4 , 32-bit, usb, ethernet, lcd, can, i 2 c, i 2 s, flash, eeprom, microcontroller abstract lpc408x/407x user manual
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 2 of 942 contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com nxp semiconductors UM10562 lpc408x/407x user manual revision history rev date description 1 20120913 inital lpc408x/407x user manual version.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 3 of 942 1.1 introduction the lpc408x/407x is an arm cortex-m4 based microcontroller for embedded applications requiring a high level of integration and low power dissipation. the cortex-m4 processor is a high-performance 32-bit processor with a 3-stage pipeline harvard architecture with separate local instruction and data buses, as well as a third bus with slightly lower performance for peri pherals. the cortex-m4 uses the thumb? instruction set, providing high code densit y and reduced program memory requirements. the cortex-m4 cpu also includes an internal prefetch unit that supports speculative branches. the lpc408x/407x adds a specializ ed flash memory accelerator to give optimal performance when executing code from flash. the lpc408x/407x is targeted to operate at up to a 120 mhz cpu frequency under worst case commercial conditions. the peripheral complement of the lpc408x/407x includes up to 512 kb of flash memory, up to 96 kb of data memory, 4,032 bytes of eeprom memory, an external memory controller for sdram and static memory access, an lcd panel controller, an ethernet mac, a high speed spi flash memory interface (spifi), a general purpose dma controller, a usb device/host/otg interf ace, 5 uarts, 3 ssp controllers, 3 i 2 c interfaces, an i 2 s serial audio interface, a 2-channel can interface, an sd card interface, an 8 channel 12-bit adc, a 10-bit dac, analog comparators, a motor control pwm, a quadrature encoder interface, 4 general purpose timers, a 6-output general purpose pwm, an ultra-low power rtc with separate battery supply and event monitor/recorder, a windowed watchdog timer, a crc calculation engine, up to 165 general purpose i/o pins, and more. UM10562 chapter 1: introductory information rev. 1 ? 13 september 2012 user manual
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 4 of 942 nxp semiconductors UM10562 chapter 1: introductory information 1.2 features refer to section 1.4 for details of features for specific part numbers. ? functional replacement for lpc23xx and 24xx family devices. ? arm cortex-m4 processor, running at freque ncies of up to 120 mhz. the cortex-m4 executes the thumb?-2 instruction set for optimal performance and code size, including hardware division, single cycle multiply, and bit-field manipulation. a memory protection unit (mpu) sup porting eight regions is included. ? cortex-m4 built-in nested vector ed interrupt controller (nvic). ? cortex-m4 floating point unit (fpu), supporting single-precision floating-point computation functionality in compliance with the ansi/ieee stan dard 754-200 8. the fpu provides add, subtract, multiply, divide, multiply and accumulate, and square root operations. it also performs a variet y of conversions between fixed-point, floating-point, and integer data formats. the fpu is not available on lpc4074 devices. ? up to 512 kb on-chip flash program memory with in-system programming (isp) and in-application programming (iap) capabilitie s. the combination of an enhanced flash memory accelerator and location of the flash memory on the cpu local code/data bus provides high code performance from flash. ? up to 96 kb on-chip sram includes: ? up to 64 kb of main sram on the cpu code/data bus for high-performance cpu access. ? up to two 16 kb sram blocks with separa te access paths for higher throughput. these sram blocks may be used for ethe rnet, usb, lcd, and dma memory, as well as for general purpose instruction and data storage. ? up to 4,032 bytes of on-chip eeprom. ? external memory controller provides suppor t for asynchronous st atic memory devices such as ram, rom and flash up to 64 mb, as well as dynamic memories such as single data rate sdram. ? eight channel general purpose dma controller (gpdma) on the ahb multilayer matrix that can be used with the ssp, i 2 s, uart, sd/mmc, crc engine, analog-to-digital and digital-to-analog conv erter peripherals, timer match signals, gpio, and for memory-to-memory transfers. ? multilayer ahb matrix interconnect prov ides a separate bus for each ahb master. ahb masters include the cpu, general purp ose dma controller, ethernet mac, lcd controller, and the usb interface. this inte rconnect provides communication with no arbitration delays unless two masters attempt to access the same slave at the same time. ? split apb bus allows for higher throughput with fewer stalls between the cpu and dma. a single level of write buffering allows the cpu to continue without waiting for completion of apb writes if the apb was not already busy. ? lcd controller, supporting both super-twisted nematic (stn) and thin-film transistor (tft) displays. the lcd controller is not available on lpc407x devices. ? dedicated dma controller. ? selectable display resolution (up to 1024 768 pixels).
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 5 of 942 nxp semiconductors UM10562 chapter 1: introductory information ? supports up to 24-bit true-color mode. ? serial interfaces: ? ethernet mac with mii/rmii interface and dedicated dma controller. ? usb 2.0 full-speed controller that can be configured for either device, host, or otg operation with an on-chip phy for dev ice and host functions and a dedicated dma controller. usb host and otg are not available on lpc4074 devices. ? five uarts with fractional baud rate generation, internal fifos, irda, dma support, and rs-485/eia-485 support on most lpc408x/407x devices. uart1 also has a full set of modem handshaking signals. uart4 includes a synchronous mode and a smart card mode supporting iso 7816-3. uart4 is not available on lpc4074 devices. ? three ssp controllers with fifo and mu lti-protocol capa bilities. the ssp interfaces can be used with the gpdma controller. ? three enhanced i 2 c-bus interfaces, one with an open-drain output supporting the full i 2 c specification and fast mode plus with data rates of 1mbit/s, two with standard port pins. enhancements include multiple address recognition and monitor mode. ? two-channel can controller. ? i 2 s (inter-ic sound) interface for digital audio input or output, with fractional rate control. the i 2 s interface can be used with the gpdma. the i 2 s interface supports 3-wire data transmit and receive or 4-wire combined transmit and receive connections, as well as master clock output. ? spifi (spi flash interface). this interfac e uses an spi bus superset with 4 data lines to access off-chip quad spi flash memory at a much higher rate than is possible using standard spi or ssp interfaces. the spif i function allows memory mapping the contents of the off-chip spi flash memory such that it can be executed as if it were on-chip code memo ry. supports spi memories with 1 or 4 data lines. ? other peripherals: ? sd card interface that also supports mmc cards. the sd card interface is not available on lpc4074 devices. ? general purpose i/o (gpio) pins with configurable pull-up/down resistors, open drain mode, and repeater mode. all gpios are located on an ahb bus for fast access, and support cortex-m4 bit-banding. gpios can be accessed by the general purpose dma controller. any pin of ports 0 and 2 can be used to generate an interrupt. there are 165 gpios on 208-pin packages, 141 gpios on 180-pin packages, and 109 gpios on 144-pin packages. ? 12-bit analog-to-digital co nverter (adc) with input multiplexing among eight pins, conversion rates up to 400 khz, and multip le result registers. the 12-bit adc can be used with the gpdma controller. ? 10-bit digital-to-analog converter (dac) with dedicated conversion timer and dma support. ? dual analog comparator with multiple selectable input s, selectable internal reference voltages, and versatile interr upt generation. the comparators are not available on lpc4074 devices.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 6 of 942 nxp semiconductors UM10562 chapter 1: introductory information ? four general purpose timers/counters, with a total of eight capture inputs and ten compare outputs. each timer block has an external count input. specific timer events can be selected to generate dma requests. ? one motor control pwm with support for thre e-phase motor control. ? quadrature encoder interface that can monitor one external quadrature encoder. the qei is not available on lpc4074 devices. ? two standard pwm/timer blocks wit h external count input option. ? real-time clock (rtc) with a separate po wer domain. the rtc is clocked by a dedicated rtc oscillator. the rtc block includes 20 bytes of battery-powered backup registers, allowing system status to be stored when the rest of the chip is powered off. battery power can be supplied from a standard 3 v lithium button cell. the rtc will continue working when the battery voltage drops to as low as 2.1 v. an rtc interrupt can wake up the cpu from any reduced power mode. ? event monitor/recorder that can capture the rtc value when an event occurs on any of 3 inputs. the event identification and the time it occurred are stored in registers. the event monitor/recorder is in the rtc power domain, and can therefore operate as long as there is rtc power. ? windowed watchdog timer (wwdt). windowed operation, dedicated internal oscillator, watchdog warning in terrupt, and safety features. ? crc engine block can calculate a crc on supplied data using 1 of 3 standard polynomials. the crc engine can be used in conjunction with the dma controller to generate a crc witho ut cpu involvement in the data transfer. ? cortex-m4 system tick timer, including an external clock input option. ? standard jtag test/debug interface as well as serial wire debug and serial wire trace port options. ? emulation trace module supports real-time trace. ? single 3.3 v power supply (2.4 v to 3.6 v). temperature range of -40 c to 85 c. ? four reduced power modes: sleep, deep-sleep, power-down, and deep power-down. ? power savings for operation at or below 100 mhz by reducing on-chip regulator output. ? four external interrupt inputs configurable as edge/level sensitive. all pins on port0 and port2 can be used as edge sensitive interrupt sources. ? non-maskable inte rrupt (nmi) input. ? clock output function th at can reflect the main oscillator clock, irc clock, rtc clock, cpu clock, usb clock, spifi clock, or the watchdog timer clock. ? the wakeup interrupt controlle r (wic) allows the cpu to automatically wake up from any priority interrupt that can occur while the clocks are stopped in deep sleep, power-down, and deep power-down modes. ? processor wake-up from power-down mode via any interrupt able to operate during power-down mode (includes external interrupts, rtc interrupt, usb activity, ethernet wake-up interrupt, can bus activity , port0/2 pin interrupt, and nmi). ? brownout detect with separate threshold for interrupt and forced reset. ? on-chip power-on reset (por). ? on-chip crystal oscillator with an op erating range of 1 mhz to 25 mhz.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 7 of 942 nxp semiconductors UM10562 chapter 1: introductory information ? 12 mhz internal rc oscillator (irc) trimmed to 1% accuracy that can optionally be used as a system clock. ? an on-chip pll allows cpu operation up to the maximum cpu rate without the need for a high-frequency crystal. may be run from the main oscillator or the internal rc oscillator. ? a second, dedicated pll may be used for the usb and/or spifi interfaces in order to allow added flexibility for the main pll settings. ? versatile pin function selection feature a llows many possibilities for using on-chip peripheral functions. ? boundary scan for simplified board testing. ? unique device serial number for identification purposes. ? available as 208-pin lqfp, 208-pin tfbga, 180-pin tfbga, 144-pin lqfp, 80-pin lqfp packages. 1.3 applications ? communications ? point-of-sale terminals, web servers, multi-protocol bridges ? industrial/medical ? automation controllers, application control, robotic controls, hvac, plc, inverters, circuit breakers, medical scanning, security monitoring, motor drive, video intercom ? consumer/appliance ? audio, mp3 decoders, alarm systems, displays, printers, scanners, small appliances, fitness equipment ? automotive ? aftermarket, car alarms , gps/fleet monitor
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 8 of 942 nxp semiconductors UM10562 chapter 1: introductory information 1.4 ordering information 1.4.1 part options summary [1] all types include spifi, event recorder , 2 can channels, 3 ssp interfaces, 3 i 2 c interfaces, i2s, dac, and an 8-channel 12-bit adc. [2] 96kb = 64kb main + 32kb peripheral sram; 80kb = 64kb main + 16kb peripheral sram; 40kb = 32kb main + 8kb peripheral sram. [3] devices that include ethernet in packages with 180 pins and greater support both mii and rmii. smaller packages support only rmii. [4] maximum data bus width for each package, smaller widths may al so be used. on 180-pin packages, the external bus is limited t o 16 bits. on 144-pin packages, the external bus is limited to 8 bits. 80-pin devic es do not support an external bus. table 1. ordering information type number package name description version lpc4088 lpc4088fbd208 lqfp208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm sot459-1 lpc4088fet208 tfbga208 plastic thin fine-pitch ball grid array package; 208 balls; body 15 15 0.7 mm sot950-1 lpc4088fet180 tfbga180 thin fine-pitch ball grid array package; 180 balls; body 12 12 0.8 mm sot570-2 lpc4088fbd144 lqfp144 plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm sot486-1 lpc4078 lpc4078fbd208 lqfp208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm sot459-1 lpc4078fet180 tfbga180 thin fine-pitch ball grid array package; 180 balls; body 12 12 0.8 mm sot570-2 lpc4078fbd144 lqfp144 plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm sot486-1 lpc4078fbd80 lqfp80 plastic low profile quad flat package; 80 leads; body 12 12 1.4 mm sot315-1 lpc4076 lpc4076fet180 tfbga180 thin fine-pitch ball grid array package; 180 balls; body 12 12 0.8 mm sot570-2 lpc4074 lpc4074fbd144 lqfp144 plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm sot486-1 lpc4074fbd80 lqfp80 plastic low profile quad flat package; 80 leads; body 12 12 1.4 mm sot315-1 table 2. ordering options for lpc408x/407x parts type number [1] flash kb sram kb [2] eeprom bytes fpu ether- net [3] usb ext. bus [4] lcd uart qei sd comp- arators pack- age(s) lpc4088 512 96 4,032 y y h/o/d 32-bit/ 16-bit/ 8-bit y5yyy208, 180, 144 lpc4078 512 96 4,032 y y h/o/d 32-bit/ 16-bit/ 8-bit/ none n5yyy 208, 180, 144, 80 lpc4076 256 80 4,032 y y h/o/d 16-bit n 5 y y y 180 lpc4074 128 40 2,048 n n d none n 4 n n n 144, 80
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 9 of 942 nxp semiconductors UM10562 chapter 1: introductory information 5. simplified block diagram fig 1. lpc408x/407x simplified block diagram arm cortex-m4 with fpu jtag interface test/debug interface general purpose dma controller system bus d-code bus i-code bus clock generation, power control, and other system functions sram up to 96 kb boot rom 8 kb flash up to 512 kb rst xtalin xtalout clocks and controls flash accelerator ethernet 10/100 mac usb otg/ host/ device lcd panel interface ethernet phy interface usb bus or tranceiver lcd panel crc engine general purpose i/o ports eeprom up to 4 kb 120229 multilayer ahb matrix static / dynamic memory controller ethernet registers usb registers lcd registers 26-bit addr 32-bit data apb slave group 0 capture/match timer 0 & 1 watchdog osc illator windowed watchdog ssp1 uarts 0 & 1 can 1 & 2 12-bit adc pin connect block gpio interrupt control i 2 c 0 & 1 pwm0 & 1 apb slave group 1 note: - orange shaded peripheral blocks support general purpose dma. - yellow shaded peripheral blocks include a dedicated dma controller . uarts 2, 3, & 4 ssp0 & 2 system control dac external interrupts motor control pwm i 2 s i 2 c 2 sd card interface capture/match timer 2 & 3 quadrature encoder i/f rtc power domain 32 khz oscillator backup registers (20 bytes) ultra-low power regulator vbat alarm real time clock event inputs event monitor/ recorder spi flash interface analog comparators
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 10 of 942 nxp semiconductors UM10562 chapter 1: introductory information 1.6 architectural overview the arm cortex-m4 includes three ahb-lite buses, one system bus and the i-code and d-code buses which are faster and are used similarly to tightly coupled memory interfaces: one bus dedicated for instructio n fetch (i-code) and one bus for data access (d-code). the use of two core buses allows for simultaneous operations if concurrent operations target different devices. the lpc408x/407x uses a multi-layer ahb ma trix to connect the cortex-m4 buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals on different slaves ports of the matrix to be accessed simultaneously by different bus masters. details of the multilayer matrix connections are shown in figure 2 . apb peripherals are connected to the cpu via two apb buses using separate slave ports from the multilayer ahb matrix. this allows for better perfor mance by reducing collisions between the cpu and the dma controller. the apb bus bridge s are configured to buffer writes so that the cpu or dma controller can write to apb devices without always waiting for apb write completion. 1.7 arm cortex-m4 processor the arm cortex-m4 is a general purpose 32-bit microprocessor, which offers high performance and very low power consumpt ion. the cortex-m4 offers a thumb-2 instruction set, low in terrupt latency, interruptible/cont inuable multiple load and store instructions, automatic state save and restore for interrupts, tightly integrated interrupt controller, and multiple core buses capable of simultaneous accesses. pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. information about cortex-m4 config uration options can be found in section 40.1 . 1.8 on-chip flash memory system the lpc408x/407x contains up to 512 kb of on-chip flash memory. a flash memory accelerator maximizes performance for cpu accesses. this memory may be used for both code and data storage. programming of the flash memory may be accomplished in several ways. it may be pr ogrammed in system via the serial port. the application program may also erase and/or program the flash while the application is running, allowing a great degree of flexibility for data storage field fi rmware upgrades, etc. 1.9 on-chip static ram the lpc408x/407x contains up to 96 kb of on-chip static ram memory. up to 64 kb of sram, accessible by the cpu and the general purpose dma controller, is on a higher-speed bus. up to 32 kb sram is provided in up to two additional 16 kb sram blocks for use primarily for peripheral da ta. when both srams are present, they are situated on separate slave ports on the ahb multilayer matrix.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 11 of 942 nxp semiconductors UM10562 chapter 1: introductory information this architecture allows the possibility for cpu and dma accesses to be separated in such a way that there are few or no delays for the bus masters. it also allows separation of data for different peripherals functions, in order to improve system performance. for example, lcd dma can be occurring in one sram while ethernet dma is occurring in another, all while the cpu is using the main sram for data and/or instruction access. 1.10 on-chip eeprom the lpc408x/407x contains up to 4,03 2 bytes of on-chip eeprom memory. the eeprom is accessible only by the cpu.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 12 of 942 nxp semiconductors UM10562 chapter 1: introductory information 1.11 detailed block diagram fig 2. lpc408x/407x block diagram, cpu and buses multilayer ahb matrix arm cortex-m4 with fpu ahb to apb bridge ahb to apb bridge jtag interface periph. sram up to 16 kb test/debug interface general purpose dma controller system bus d-code bus i-code bus clock generation, power control, and other system functions main sram up to 64 kb boot rom 8 kb flash up to 512 kb rst xtalin xtalout apb slave group 1 note: - orange shaded peripheral blocks support general purpose dma. - yellow shaded peripheral blocks include a dedicated dma controller. apb slave group 0 voltage regulator clocks and controls internal power vdd clk out capture/match timer 0 & 1 flash accelerator driver rom 16 kb ethernet 10/100 mac usb otg/ host/dev lcd panel interface static / dynamic memory controller d[31:0] a[25:0] control periph. sram up to 16 kb ethernet phy interface usb bus or tranceiver lcd panel watchdog osc illator windowed watchdog ethernet registers gpdma registers crc engine usb registers lcd registers hs gpio mem ctl registers ssp1 uarts 0 & 1 can 1 & 2 12-bit adc pin connect block gpio interrupt control i 2 c 0 & 1 pwm0 & 1 uarts 2, 3, & 4 ssp0 & 2 system control dac external interrupts motor control pwm i 2 s i 2 c 2 sd card interface capture/match timer 2 & 3 quadrature encoder i/f eeprom up to 4 kb 120621 rtc power domain 32 khz oscillator backup registers (20 bytes) ultra-low power regulator vbat alarm real time clock event inputs event monitor/ recorder spi flash interface
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 13 of 942 2.1 memory map and peripheral addressing the arm cortex-m4 processor has a single 4 gb address space. the following table shows how this space is used on the lpc408x/407x. [1] can be up to 256 mb, upper address 0x8fff ffff, if the address shift mode is enabled. see scs register bit 0 ( section 3.3.7.1 ). [2] can be up to 128 mb, upper address 0x97ff ffff, if t he address shift mode is enabled. see scs register bit 0 ( section 3.3.7.1 ). UM10562 chapter 2: lpc408x/407x memory map rev. 1 ? 13 september 2012 user manual table 3. memory usage and details address range general use address range details and description 0x0000 0000 to 0x1fff ffff on-chip non-volatile memory 0x0000 0000 - 0x0007 ffff for devices with 512 kb of flash memory. 0x0000 0000 - 0x0003 ffff for devices with 256 kb of flash memory. 0x0000 0000 - 0x0001 ffff for devices with 128 kb of flash memory. on-chip sram 0x1000 0000 - 0x1000 ffff for devices with 64 kb of main sram. 0x1000 0000 - 0x1000 7fff for devices with 32 kb of main sram. boot rom 0x1fff 0000 - 0x1fff 7fff 8 kb boot rom with flash services. driver rom 0x1fff 8000 - 0x1fff 1fff 16 kb driver rom 0x2000 0000 to 0x3fff ffff on-chip sram (typically used for peripheral data) 0x2000 0000 - 0x2000 1fff peripheral sram - bank 0 (first 8 kb) 0x2000 2000 - 0x2000 3fff peripheral sram - bank 0 (second 8 kb) 0x2000 4000 - 0x2000 7fff peripheral sram - bank 1 (16 kb) ahb peripherals 0x2008 0000 - 0x200b ffff see section 2.3.1 for details spifi buffer space 0x2800 0000 - 0x28ff ffff spifi memory mapped access space 0x4000 0000 to 0x7fff ffff apb peripherals 0x4000 0000 - 0x4007 ffff apb0 peripherals, up to 32 peripheral blocks of 16 kb each. 0x4008 0000 - 0x400f ffff apb1 peripherals, up to 32 peripheral blocks of 16 kb each. 0x8000 0000 to 0xdfff ffff off-chip memory via the external memory controller four static memory chip selects: 0x8000 0000 - 0x83ff ffff static memory chip select 0 (up to 64 mb) [1] 0x9000 0000 - 0x93ff ffff static memory chip select 1 (up to 64 mb) [2] 0x9800 0000 - 0x9bff ffff static memory chip select 2 (up to 64 mb) 0x9c00 0000 - 0x9fff ffff static memory chip select 3 (up to 64 mb) four dynamic memory chip selects: 0xa000 0000 - 0xafff ffff dynamic memory chip select 0 (up to 256mb) 0xb000 0000 - 0xbfff ffff dynamic memory chip select 1 (up to 256mb) 0xc000 0000 - 0xcfff ffff dynamic memory chip select 2 (up to 256mb) 0xd000 0000 - 0xdfff ffff dynamic memory chip select 3 (up to 256mb) 0xe000 0000 to 0xe00f ffff cortex-m4 private peripheral bus 0xe000 0000 - 0xe00f ffff cortex-m4 related functions, includes the nvic and system tick timer.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 14 of 942 nxp semiconductors UM10562 chapter 2: lpc408x/407x memory map 2.2 memory maps the lpc408x/407x incorporates several distinct memory regions, shown in the following figures. figure 3 shows the overall map of the entire address space from the user program viewpoint following reset. the interrupt vector area supports address remapping, which is described later in this section. figure 3 and ta b l e 5 show different views of the peripheral address space. the ahb peripheral area is 2 megabyte in size, and is divided to allow for up to 128 peripherals. the apb peripheral area is 1 megabyte in size and is divided to allow for up to 64 peripherals. each peripheral of either type is allocated 16 kilobytes of space. this allows simplifying the address decoding for each peripheral.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 15 of 942 nxp semiconductors UM10562 chapter 2: lpc408x/407x memory map fig 3. system memory map 31-24 23 22-19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x4008 0000 0x4006 0000 0x4005 c000 0x4004 c000 0x4004 8000 0x4004 4000 0x4004 0000 0x4003 c000 0x4003 8000 0x4003 4000 0x4003 0000 0x4002 c000 0x4002 8000 0x4002 4000 0x4002 0000 0x4001 c000 0x4001 8000 0x4001 4000 0x4001 0000 0x4000 c000 0x4000 8000 0x4000 4000 0x4000 0000 reserved i2c1 reserved can 2 can 1 can common can af registers can af ram adc ssp1 pin connect gpio interrupts rtc comparators i2c0 pwm1 pwm0 uart1 uart0 timer1 timer0 watchdog timer apb0 peripherals 7 6 5 4 3 2 1 0 0x200a 0000 0x2009 c000 0x2009 8000 0x2009 4000 0x2009 0000 0x2008 c000 0x2008 8000 0x2008 4000 0x2008 0000 emc registers gpio spifi registers crc engine usb lcd controller ethernet gp dma ctlr ahb peripherals i-code and d-code memory space 31 30-17 16 15 14 13-12 11 10 9 8 7 6 5 4 3 2 1-0 0x4010 0000 0x400f c000 0x400c 4000 0x400c 0000 0x400b c000 0x400b 8000 0x400b 0000 0x400a c000 0x400a 8000 0x400a 4000 0x400a 0000 0x4009 c000 0x4009 8000 0x4009 4000 0x4009 0000 0x4008 c000 0x4008 8000 0x4008 0000 system control reserved sd card qei motor ctl pwm reserved ssp2 i2s uart4 i2c2 uart3 uart2 timer3 timer2 dac ssp0 reserved apb1 peripherals 0.5 gb 1 gb 2 gb 4 gb active interrupt vectors 0x0400 0x0000 reserved private peripheral bus external memory (4 dynamic chip selects) apb peripheral group 1 apb peripheral group 0 reserved reserved reserved reserved reserved reserved reserved reserved ahb peripherals boot rom and driver rom external memory (4 static chip selects) apb peripheral bit-band addressing spifi memory mapped space peripheral sram 1 peripheral sram 0 64 kb main sram 512 kb flash memory memory space 0xffff ffff 0xe010 0000 0xe004 0000 0xe000 0000 0xa000 0000 0x8000 0000 0x4400 0000 0x4200 0000 0x4010 0000 0x4008 0000 0x4000 0000 0x2900 0000 0x2800 0000 0x200c 0000 0x2000 4000 0x2000 0000 0x1fff 0000 0x1001 0000 0x1000 0000 0x0008 0000 0x0000 0000 0x2400 0000 0x2200 0000 0x2008 0000 peripheral sram bit-band addressing 120420
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 16 of 942 nxp semiconductors UM10562 chapter 2: lpc408x/407x memory map 2.3 on-chip peripherals all peripheral register addresses are word aligned (to 32-bit boundaries) regardless of their size. this eliminates the need for byte lane mapping hardware that would be required to allow byte (8-bit) or half-word (16-bit) accesses to occur at smaller boundaries. an implication of this is that word and half-word registers must be accessed all at once. for example, it is not possible to read or write the upper byte of a word register separately. 2.3.1 ahb peripherals the following table shows the addresses of periph eral functions that reside directly on the ahb bus matrix. complete register descripti ons may be found in the relevant chapters. 2.3.2 apb peripheral addresses the following table shows the address maps of the 2 apb buses. apb peripherals do not use all of the 16 kb space allocated to them. typically each device?s registers are "aliased" or repeated at multiple locations within each 16 kb range. table 4. ahb peripherals and base addresses ahb peripheral address range peripheral name 0 0x2008 0000 to 0x2008 3fff general purpose dma controller 1 0x2008 4000 to 0x2008 7fff ethernet mac 2 0x2008 8000 to 0x2008 bfff lcd controller 3 0x2008 c000 to 0x2008 ffff usb interface 4 0x2009 0000 to 0x2009 3fff crc engine 5 0x2009 4000 to 0x2009 7fff spifi 6 0x2009 8000 to 0x2009 bfff gpio 7 0x2009 c000 to 0x2009 ffff external memory controller 8 to 15 0x200a 0000 to 0x200b ffff reserved table 5. apb0 peripherals and base addresses apb0 peripheral base address peripheral name 0 0x4000 0000 watchdog timer 1 0x4000 4000 timer 0 2 0x4000 8000 timer 1 3 0x4000 c000 uart0 4 0x4001 0000 uart1 5 0x4001 4000 pwm0 6 0x4001 8000 pwm1 7 0x4001 c000 i 2 c0 8 0x4002 0000 comparators 9 0x4002 4000 rtc and event monitor/recorder 10 0x4002 8000 gpio interrupts 11 0x4002 c000 pin connect block 12 0x4003 0000 ssp1 13 0x4003 4000 adc
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 17 of 942 nxp semiconductors UM10562 chapter 2: lpc408x/407x memory map 2.4 memory re-mapping the cortex-m4 incorporates a me chanism that allows remapping the interrupt vector table to alternate locations in the memory map. th is is controlled via the vector table offset register contained in the cortex-m4. refer to the nvic description in section 5.4 and to the arm cortex-m4 user guide referr ed to in section 40.1 . boot rom re-mapping following a hardware reset, the boot rom is temporarily mapp ed to address 0. this is normally transparent to the user. however, if execution is halted immediately after reset by a debugger, it should correct the mapping for the user. see section 39.8 . 14 0x4003 8000 can acceptance filter ram 15 0x4003 c000 can acceptance filter registers 16 0x4004 0000 can common registers 17 0x4004 4000 can controller 1 18 0x4004 8000 can controller 2 19 to 22 0x4004 c000 to 0x4005 8000 reserved 23 0x4005 c000 i 2 c1 24 to 31 0x4006 0000 to 0x4007 c000 reserved table 6. apb1 peripherals and base addresses apb1 peripheral base address peripheral name 0 to 1 0x4008 0000 to 0x4008 4000 reserved 2 0x4008 8000 ssp0 3 0x4008 c000 dac 4 0x4009 0000 timer 2 5 0x4009 4000 timer 3 6 0x4009 8000 uart2 7 0x4009 c000 uart3 8 0x400a 0000 i 2 c2 9 0x400a 4000 uart4 10 0x400a 8000 i 2 s 11 0x400a c000 ssp2 12 to 13 0x400b 0000 to 0x400b 4000 reserved 14 0x400b 8000 motor control pwm 15 0x400b c000 quadrature encoder interface 16 0x400c 0000 sd card interface 17 to 30 0x400d 0000 to 0x400f 8000 reserved 31 0x400f c000 system control table 5. apb0 peripherals and base addresses apb0 peripheral base address peripheral name
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 18 of 942 nxp semiconductors UM10562 chapter 2: lpc408x/407x memory map 2.5 ahb arbitration the multilayer ahb matrix arbitrates between several masters, only if they attempt to access the same matrix slave port at the sa me time. by default, the cortex-m4 d-code bus has the highest priority, followed by the i-code bus. all other masters share a lower priority. the default priority can be altered by the user if care is taken. this may be particularly useful if the lcd interface is used and it has difficulty getting sufficient data. 2.5.1 matrix arbitration register the matrix arbitration regist er provides the ability to c hange the default ahb matrix arbitration priorities. the values used for the various priorities are 3 = highest, 0 = lowest. an example of a way to give priority to the lcd dma is to use the value 0x0000 0c09. the gives the lcd highest priority, d-code second priority, i-code third priority, and all others lowest priority. where in the memory space code and various types of data are located can be managed to help minimize the need for arbitration and possible starvation of any of the bus masters, as well as a need for changing the default priorities. for instance, lcd refresh from off-chip memory connected to the emc, while also executing off-chip code via the emc can cause a great deal of arbitration. table 7. matrix arbitration register (ma trix_arb - 0x400f c188) bit description bit symbol description reset value 1:0 pri_icode i-code bus priority. should be lower than pri_dcode for proper operation. 0x1 3:2 pri_dcode d-code bus priority. 0x3 5:4 pri_sys system bus priority. 0 7:6 pri_gpdma general purpose dma controller priority. 0 9:8 pri_eth ethernet dma priority. 0 11:10 pri_lcd lcd dma priority. 0 13:12 pri_usb usb dma priority. 0 15:14 - reserved. read value is undefined, only zero should be written. na 16 rom_lat rom latency select. should always be 0. 0 31:17 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 19 of 942 3.1 introduction the system control block includes several sy stem features and control registers for a number of functions that are not related to specific peripheral devices. these include: ? chip reset (see section 3.4 ) ? peripheral reset control (see section 3.5 ) ? brown-out detection (see section 3.6 ) ? external interrupt inputs (see section 3.7 ) each type of function has its own registers if any are required and unneeded bits are defined as reserved in orde r to allow future expansion. 3.1.1 summary of clocking and power control functions this section describes the generation of th e various clocks needed for device operation, and options of clock source selection, as we ll as power control and wake-up from reduced power modes. functions described in the following subsections include: ? oscillators (see section 3.8 ) ? plls (see section 3.10 ) ? clock selection and dividers (see section 3.11 ) ? power control (see section 3.12 ) ? wake-up timer (see section 3.13 ) ? external clock output (see section 3.14 ) UM10562 chapter 3: lpc408x/407x system and clock control rev. 1 ? 13 september 2012 user manual
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 20 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.2 pin description ta b l e 8 shows pins that are associated with system control block functions. fig 4. clock generation cclk pclk divide select pclksel[4:0] pclk usb_clk spifi_clk pll1 settings pll1con, pll1cfg alt_pll_clk pll0 settings pll0con, pll0cfg sysclk pll_clk system clock select clksrcsel[0] 1 0 irc_clk osc_clk cpu divide select cclksel[4:0] usb divide select usbclksel[4:0] spifi divide select spificlksel[4:0] emc_clk emc divide select emcclksel[0] 01 10 00 usb clock select usbclksel[9:8] sysclk pll_clk alt_pll_clk cpu clock divider peripheral clock divider emc clock divider usb clock divider spifi clock divider pll1 (alt pll) pll0 (main pll) cpu clock select cclksel[8] sysclk pll_clk 1 0 01 10 00 spifi clock select spificlksel[9:8) sysclk pll_clk alt_pll_clk 120601
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 21 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control table 8. pin summary pin name pin direction pin description eint0 input external inte rrupt input 0 - an active low/high level or falling/rising edge general purpose interrupt input. this pin may be used to wake up the processor from sleep, deep-sleep, or power-down modes. eint1 input external inte rrupt input 1 - see the eint0 description above. eint2 input external inte rrupt input 2 - see the eint0 description above. eint3 input external inte rrupt input 3 - see the eint0 description above. reset input external reset input - a low on this pin resets the chip, causing i/o ports and peripherals to take on their default states, and the processor to begin execution at address 0x0000 0000.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 22 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.3 register description all registers, regardless of si ze, are on word address boundaries. details of the registers appear in the description of each function. table 9. register overview: system control (base address 0x400f c000) name access address offset description reset value refer- ence pll registers 3.3.1 pllcon0:1 r/w 0x080; 0xa0 pll0 and pll1 control registers 0 3.3.1.1 pllcfg0:1 r/w 0x084; 0xa4 pll0 and pll1 configuration registers 0 3.3.1.2 pllstat0:1 ro 0x088; 0xa8 pll0 and pll1 status registers 0 3.3.1.3 pllfeed0:1 wo 0x08c; 0xac pll0 and pll1 feed registers na 3.3.1.5 power control 3.3.2 pcon r/w 0x0c0 power control register 0 3.3.2.1 pconp r/w 0x0c4 power control for peripherals 0x0408 829e 3.3.2.2 pconp1 r/w 0x0c8 power control for peripherals 1 0x8 3.3.2.2 pboost r/w 0x1b0 power boost register 0x3 3.3.2.3 clock selection and divider registers 3.3.3 emcclksel r/w 0x100 external memory controller clock selection register 0 3.3.3.1 cclksel r/w 0x104 cpu clock selection register 1 3.3.3.2 usbclksel r/w 0x108 usb clock selection register 0 3.3.3.3 clksrcsel r/w 0x10c clock so urce select register 0 3.3.3.4 pclksel r/w 0x1a8 peripheral clock selection register 0x10 3.3.3.5 spificlksel r/w 0x1b4 spifi cl ock selection register 0 3.3.3.6 external interrupts 3.3.4 extint r/w 0x140 external interrupt flag register 0 3.3.4.1 extmode r/w 0x148 external interrupt mode register 0 3.3.4.2 extpolar r/w 0x14c external interrupt polarity register 0 3.3.4.3 device and peripheral reset 3.3.5 rsid r/w 0x180 reset source identification register see ta b l e 2 8 3.3.5.1 rstcon0 r/w 0x1cc individual peripheral reset control bits 0 3.3.5.2 rstcon1 r/w 0x1d0 individual peripheral reset control bits 0 3.3.5.3 emc delay control and calibration 3.3.6 emcdlyctl r/w 0x1dc values for the 4 programmable delays associated with sdram operation. 0x210 3.3.6.1 emccal r/w 0x1e0 controls the calibration counter for programmable delays and returns the result value. 0x1f00 3.3.6.2 miscellaneous system control registers 3.3.7 scs r/w 0x1a0 system control and status 0 3.3.7.1 lcd_cfg r/w 0x1b8 lcd clock configuration register 0 3.3.7.2 cansleepclr r/w 0x110 allows clearing the current can channel sleep state as well as reading back that state. 0 3.3.7.3 canwakeflags r/w 0x114 indicates the wake-up state of the can channels. 0 3.3.7.4
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 23 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control usbintst r/w 0x1c0 usb interrupt status 0x8000 0000 3.3.7.5 dmacreqsel r/w 0x1c4 selects between alternative requests on dma channels 0 through 7 and 10 through 15. 0 3.3.7.6 clkoutcfg r/w 0x1c8 clock output configuration register 0 3.3.7.7 table 9. register overview: system control (base address 0x400f c000) name access address offset description reset value refer- ence
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 24 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.3.1 pll registers 3.3.1.1 pll control registers the pllcon registers contains the bits that enable and connect each pll. enabling a pll allows it to attempt to lock to the curr ent settings of the multiplier and divider values. changes to a pllcon register do not take ef fect until a correct pll feed sequence has been given for that pll (see section 3.3.1.5 and section 3.3.1.2 ). each pll must be set up, enabled, and lock established before it may be used as a clock source. the hardware does not insure that the pll is locked before it is selected nor does it automatically disconnect the pll if lock is lost during operation. 3.3.1.2 pll configuration registers the pllcfg register contains the pll multiplier and divider values. changes to the pllcfg register do not take effect until a correct pll feed sequence has been given (see section 3.3.1.5 ). calculations for the pll frequency, and multiplier and divider values are found in section 3.10.5 . table 10. pll control registers (pllcon[0:1] - ad dresses 0x400f c080 (pllcon0) and 0x400f c0a0 (pllcon1)) bit description bit symbol description reset value 0 plle pll enable. when one, and after a valid pll feed, this bit will activate the related pll and allow it to lock to the requested frequency. see pllstat register, table 12 . 0 31:1 - reserved. read value is undefined, only zero should be written. na table 11. pll configuration registers (pllcfg[0 :1] - addresses 0x400f c084 (pllcfg0) and 0x400f c0a4 (pllcfg1)) bit description bit symbol description reset value 4:0 msel pll multiplier value. supplies the value "m" in the pll frequency calculations. the value stored here is the m value minus 1. note: for details on selecting the right value for msel see section 3.10.4 . 0 6:5 psel pll divider value. supplies the value "p" in the pll frequency calculations. this value is encoded as follows: 00 (0x0) = divide by 1 01 (0x1) = divide by 2 10 (0x2) = divide by 4 11 (0x3) = divide by 8 note: for details on selecting th e right value for psel see section 3.10.4 . 0 31:7 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 25 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.3.1.3 pll status registers the read-only pllstat register provides the actual pll parameters that are in effect at the time it is read, as well as the pll status. pllstat may disagree with values found in pllcon and pllcfg because changes to those registers do not take effect until a proper pll feed has occurred (see section 3.3.1.5 ? pll feed registers ? ). 3.3.1.4 pll interrupts: plock0 and plock1 the plock bit in the pllstat regist er reflects the lock status of the related pll1. when the pll is first enabled, or when its parameters are changed, the pll requires some time to establish lock under the new conditions. the related plock bit can be monitored to determine when the pll may be connected for use. each plock bit is connected to the interrupt cont roller. this allows for software to turn on the pll and continue with other functions wi thout having to wait for the pll to achieve lock. when the interrupt occurs, the pll ma y be selected as a clock source, and the interrupt disabled. plock0 and plock1 appear as exception numbers 32 and 48 respectively in ta b l e 5 0 . note that each plock bit remains asserted whenever the related pll is locked, so if th e interrupt is used, the interrupt service routine must disable the interrupt prior to exiting. 3.3.1.5 pll feed registers a correct feed sequence must be written to the related pllfeed register in order for changes to the related pllcon and pllcfg registers to take effect. the feed sequence is: 1. write the value 0xaa to pllfeed. 2. write the value 0x55 to pllfeed. the two writes must be in the correct seq uence, and there must be no other register access in the same address space (0x400f c000 to 0x400f ffff) between them. because of this, it may be necessary to disable interrupts for the duration of the pll feed operation, if there is a poss ibility that an interrupt service routine coul d write to another table 12. pll status registers (pllstat[0:1] - addresses 0x400f c088 (pllstat0) and 0x400f c0a8 (pllstat1)) bit description bit symbol description reset value 4:0 msel read-back for the pll multiplier value. this is the value currently used by the related pll. 0 6:5 psel read-back for the pll divider value. this is the va lue currently used by the related pll. 0 7 - reserved. the value read from a reserved bit is not defined. na 8 plle_stat read-back for the pll enable bit. when one, the related pll is currently activated. when zero, the related pll is turned off. this bit is automatically cleared when power-down mode is activated. 0 9 - reserved. the value read from a reserved bit is not defined. na 10 plock reflects the pll lock status. when zero, the related pll is not locked. when one, the related pll is locked onto the requested frequency. 0 31:11 - reserved. the value read from a reserved bit is not defined. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 26 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control register in that space. if eith er of the feed values is incorrect, or one of the previously mentioned conditions is not me t, any changes to the pllcon or pllcfg register will not become effective. table 13. pll feed registers (pllfeed[0:1] - addresses 0x400f c08c (pllfeed0) and 0x400f c0ac (pllfeed1)) bit description bit symbol description reset value 7:0 pllfeed the pll feed sequence must be written to this register in order for the related pll?s configuration and control register changes to take effect. 0x00 31:8 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 27 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.3.2 power control 3.3.2.1 power mode control register controls for some reduced power modes and other power related controls are contained in the pcon register, as described in ta b l e 1 4 . [1] only one of these flags will be valid at a specific time. [2] hardware reset value only for a power-up of core power or by a brownout detect event. [3] hardware reset value only for a power-up event on vbat. table 14. power mode control register (pcon - address 0x400f c0c0) bit description bit symbol description reset value 0 pm0 power mode control bit 0. this bit controls entry to the power-down mode. see section 3.3.2.1.1 below for details. 0 1 pm1 power mode control bit 1. this bit controls entry to the deep power-down mode. see section 3.3.2.1.1 below for details. 0 2 bodrpm brown-out reduced power mode. when bodrpm is 1, the brown-out detect circuitry will be turned off when chip power-down mode or deep sleep mode is entered, resulting in a further reduction in power usage. however, the possibility of using brown-out detect as a wake-up source from the reduced power mode will be lost. when 0, the brown-out detect function remains active during power-down and deep sleep modes. see the system control block chapter for details of brown-out detection. 0 3 bogd brown-out global disable. when bogd is 1, the brown-out detect circuitry is fully disabled at all times, and does not consume power. when 0, the brown-out detect circuitry is enabled. see the system control block chapter for details of brown-out detection. note: the brown-out reset disable (bord, in this register) and the brown-out interrupt (see section 5.1 ) must be disabled when software changes the value of this bit. 0 4 bord brown-out reset disable. when bord is 1, the bod will not reset the device when the v dd(reg)(3v3) voltage dips goes below the bod reset trip level. the brown-out interrupt is not affected. when bord is 0, the bod reset is enabled. see the section 3.6 for details of brown-out detection. 0 7:3 - reserved. read value is undefined, only zero should be written. na 8 smflag sleep mode entry flag. set when the sleep mode is successfully entered. cleared by software writing a one to this bit. 0 [1] [2] 9 dsflag deep sleep entry flag. set when the deep sl eep mode is successfully entered. cleared by software writing a one to this bit. 0 [1] [2] 10 pdflag power-down entry flag. set when the power-down mode is successfully entered. cleared by software writing a one to this bit. 0 [1] [2] 11 dpdflag deep power-down entry flag. set when the deep power-down mode is successfully entered. cleared by software writing a one to this bit. 0 [1] [3] 31:12 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 28 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.3.2.1.1 encoding of reduced power modes the pm1and pm0 bits in pcon allow entering reduced power modes as needed. the encoding of these bits allows backward comp atibility with devices th at previously only supported sleep and power-down modes. ta b l e 1 5 below shows the encoding for the three reduced power modes. 3.3.2.2 power control for peripherals registers the pconp registers allow turning off select ed peripheral functions for the purpose of saving power. this is accomplished by gating off the clock source to the specified peripheral blocks. a few peripheral functions cannot be turned off (i.e. the watchdog timer and the system control block). some peripherals, particularly those that include analog functions, may consume power that is not clock dependent. these peripherals may contain a separate disable control that turns off additional circuitry to reduce power. when this is the case, the peripheral should be disabled internally first, then turned off using pconp, in order to get the greatest power savings. information on peripheral specific power saving features may be found in the chapter describing that peripheral. each bit in pconp controls one peripheral as shown in table 16 . if a peripheral control bit is 1, that peripheral is enabled. if a peripheral control bit is 0, that peripheral?s clock is disabled (gated off) to conserve power. for example if bit 19 is 1, the i 2 c1 interface is enabled. if bit 19 is 0, the i 2 c1 interface is disabled. important: valid data reads from a peripheral register and valid data writes to a peripheral register are possible only if that peripheral is enabled in the pconp register! table 15. encoding of reduced power modes pm1, pm0 description 00 execution of wfi or wfe enters either sleep or deep sleep mode as defined by the sleepdeep bit in the cortex-m4 system control register. 01 execution of wfi or wfe enters powe r-down mode if the sleepdeep bit in the cortex-m4 system control register is 1. 10 reserved, this setting should not be used. 11 execution of wfi or wfe enters deep power-down mode if the sleepdeep bit in the cortex-m4 system control register is 1.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 29 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control table 16. power control for peripherals register (pconp - address 0x400f c0c4) bit description bit symbol description reset value 0 pclcd lcd controller power/clock control bit. 0 1 pctim0 timer/counter 0 power/clock control bit. 1 2 pctim1 timer/counter 1 power/clock control bit. 1 3 pcuart0 uart0 power/clock control bit. 1 4 pcuart1 uart1 power/clock control bit. 1 5 pcpwm0 pwm0 power/clock control bit. 0 6 pcpwm1 pwm1 power/clock control bit. 0 7pci2c0i 2 c0 interface power/clock control bit. 1 8 pcuart4 uart4 power/clock control bit. 0 9 pcrtc rtc and event monitor/recorder power/clock control bit. 1 10 pcssp1 ssp 1 interface power/clock control bit. 0 11 pcemc external memory controller power/clock control bit. 0 12 pcadc a/d converter (adc) power/clock control bit. note: clear the pdn bit in the ad0cr before clearing this bit, and set this bit before attempting to set pdn. 0 13 pccan1 can controller 1 power/clock control bit. 0 14 pccan2 can controller 2 power/clock control bit. 0 15 pcgpio power/clock control bit for iocon, gpio, and gpio interrupts. 1 16 pcspifi spi flash interface power/clock control bit. 0 17 pcmcpwm motor control pwm power/clock control bit. 0 18 pcqei quadrature encoder interface power/clock control bit. 0 19 pci2c1 i 2 c1 interface power/clock control bit. 1 20 pcssp2 ssp2 interface power/clock control bit. 0 21 pcssp0 ssp0 interface power/clock control bit. 0 22 pctim2 timer 2 power/clock control bit. 0 23 pctim3 timer 3 power/clock control bit. 0 24 pcuart2 uart 2 power/clock control bit. 0 25 pcuart3 uart 3 power/clock control bit. 0 26 pci2c2 i 2 c interface 2 power/clock control bit. 1 27 pci2s i 2 s interface power/clock control bit. 0 28 pcsdc sd card interface power/clock control bit. 0 29 pcgpdma gpdma function power/clock control bit. 0 30 pcenet ethernet block power/clock control bit. 0 31 pcusb usb interface power/clock control bit. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 30 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control note that the dac peripheral does not have a control bit in pconp. to enable the dac, its output must be selected to appear on the related pin, p0[26], by configuring the relevant iocon register. see section 7.4.1 . 3.3.2.3 power boost control register the power boost control register allows choosing between high-speed operation above 100 mhz, or power savings wh en operation is at 100 mhz or lower, by controlling the output of the main on-chip regulator. the boost feature is turned on when user code is first executed following reset. it ca n then be turned off by user code if th e cpu clock rate will always be at or below 100 mhz, thus savi ng power that is only needed for operation above 100 mhz. details are show in table 18 . table 17. power control for peripherals register (pconp1 - address 0x400f c0c8) bit description bit symbol description reset value 2:0 - reserved. read value is undefined, only zero should be written. na 3 pccmp comparator power/clock control bit. 1 31:4 - reserved. read value is undefined, only zero should be written. na table 18. power boost control register (pboost - address 0x400f c1b0) bit description bit symbol description reset value 1:0 boost boost control bits. 00 : boost is off, operation must be below 100 mhz. 11 : boost is on, operation up to 120 mhz is supported. other values are not allowed. 0x3 31:2 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 31 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.3.3 clock selection a nd divider registers 3.3.3.1 emc clock selection register the emcclksel register controls division of the clock before it is used by the emc. the emc uses the same base clock as the cp u and the apb peripherals. the emc clock can be the same as the cpu clock, or half that. this is intended to be used primarily when the cpu is running faster than the external bus can support. 3.3.3.2 cpu clock selection register the cclksel register controls selection of the clock used as the main pll input, and also controls the division of the pll0 output before it is used by the cpu. when pll0 is bypassed, the division may be by 1. when pll0 is running, the output must be divided in order to bring the cpu clock frequency (cclk) within operating limits. a 5-bit divider allows a range of options, including slowing cpu operation to a low rate for temporary power savings without turning off pll0. note that the cpu clock rate should not be set lower than the peripheral clock rate. the two clock sources that may be chosen to drive pll0 and ultimately the cpu and on-chip peripheral devices ar e the main oscillator and the inter nal rc oscillator. the clock source selection for pll0 can only be changed safely when pll0 is not being used. for a detailed description of how to cha nge the clock source in a system using pll0 see section 3.10.7 ? pll configuration examples ? . note the following restrictions rega rding the choice of clock sources: ? the irc oscillator should not be used (via pll0 ) as the clock s ource for the usb subsystem. ? the irc oscillator should not be used (via pll0 ) as the clock s ource for the can controllers if the can baud rate is higher than 100 kbit/s. table 19. emc clock selection register (emcclksel - address 0x400f c100) bit description bit symbol value description reset value 0 emcdiv selects the emc clock rate relative to the cpu clock. 0 0 the emc uses the same clock as the cpu. 1 the emc uses a clock at half the rate of the cpu. 31:1 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 32 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.3.3.3 usb clock selection register the usbclksel register controls selection of the clock used for the usb subsystem, and also controls the division of the that clock before it is used by the usb. the output of the selected pll must be divided in order to bring the usb clock frequency to 48 mhz with a 50% duty cycle. a divider allows obtaining the correct usb clock from any even multiple of 48 mhz (i.e. any multiple of 96 mhz) within the pll operating range. remark: a clock derived from the internal rc osc illator should not be used to clock the usb subsystem. table 20. cpu clock selection register (cclksel - address 0x400f c104) bit description bit symbol value description reset value 4:0 cclkdiv selects the divide value for creating the cpu clock (cclk) from the selected clock source. 0 = the divider is turned off., no clock will be provided to the cpu. this setting should typically not be used, the cpu w ill be halted and a reset will be required to restore operation. 1 = the input clock is divided by 1 to produce the cpu clock. 2 = the input clock is divided by 2 to produce the cpu clock. 3 = the input clock is divided by 3 to produce the cpu clock. ... 31 = the input clock is divided by 31 to produce the cpu clock. 0x01 7:5 - reserved. read value is undefined, only zero should be written. na 8 cclksel selects the input clock for the cpu clock divider. 0 0 sysclk is used as the input to the cpu clock divider. 1 the output of the main pll is used as the input to the cpu clock divider. 31:9 - reserved. read value is undefined, only zero should be written. na table 21. usb clock selection register (usb clksel - address 0x400f c108) bit description bit symbol value description reset value 4:0 usbdiv selects the divide value for creating the usb clock from the selected pll output. only the values shown below can produce even number multiples of 48 mhz from the pll. warning: improper setting of this value will result in incorrect operation of the usb interface. only the main oscillator in conjunction with either pll0 or pll1 can provide a clock that meets usb accuracy and jitter specifications. other values cannot produce the 48 mhz clock required for usb operation. 0 0x0 the divider is turned off, no clock will be provided to the usb subsystem. 0x1 the selected output is divided by 1. the pll output must be 48 mhz. 0x2 the selected output is divided by 2. the pll output must be 96 mhz. 0x3 the selected output is divided by 3. the pll output must be 144 mhz. 7:5 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 33 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.3.3.4 clock source selection register the clksrcsel register controls selecti on of the clock used for sysclk and pll0. 3.3.3.5 peripheral clock selection register the pclksel register contro ls the base clock used fo r all apb peripherals. a clock divider allows a range of frequencies to be used. note that the peripheral clock rate should not be set higher than the cpu clock rate. 3.3.3.6 spifi clock selection register the spificlksel register controls selection of the clock used for the spifi, and also controls the division of that clock before it is used by the spifi. if a pll is used as the spifi clock source, its output must be divided in order to bring the frequency down to one that will work with the spifi. a 5-bit divide r allows a range of fr equencies to be used. 9:8 usbsel selects the input clock for the usb clock divider. 0 0x0 sysclk is used as the input to the u sb clock divider. when this clock is selected, the usb can be accessed by software but cannot perform usb functions. 0x1 the output of the main pll is used as the input to the usb clock divider. 0x2 the output of the alt pll is used as the input to the usb clock divider. 0x3 reserved, this setting should not be used. 31:10 - reserved. read value is undefined, only zero should be written. na table 21. usb clock selection register (usb clksel - address 0x400f c108) bit description bit symbol value description reset value table 22. clock source selection register (clksrcsel - address 0x400f c10c) bit description bit symbol value description reset value 0 clksrc selects the clock source for sysclk and pll0 as follows: 0 0 selects the internal rc oscillator as the sysclk and pll0 clock source (default). 1 selects the main oscillator as the sysclk and pll0 clock source. 31:1 - reserved. read value is undefined, only zero should be written. na table 23. peripheral clock selection register (pclksel - address 0x400f c1a8) bit description bit symbol description reset value 4:0 pclkdiv selects the divide value for the clock used for all apb peripherals. 0 = the divider is turned off., no clo ck will be provided to apb peripherals. 1 = the input clock is divided by 1 to produce the apb peripheral clock. 2 = the input clock is divided by 2 to produce the apb peripheral clock. 3 = the input clock is divided by 3 to produce the apb peripheral clock. 4 = the input clock is divided by 4 to produce the apb peripheral clock. other values = not supported. 0x04 31:5 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 34 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control table 24. spifi clock selection register (spi ficlksel - address 0x400f c1b4) bit description bit symbol value description reset value 4:0 spifidiv selects the divide value for creating the spifi clock from the selected clock source. 0 = the divider is turned off., no clock will be provided to the spifi. 1 = the input clock is divided by 1 to produce the spifi clock. 2 = the input clock is divided by 2 to produce the spifi clock. 3 = the input clock is divided by 3 to produce the spifi clock. ... 31 = the input clock is divided by 31 to produce the spifi clock. 0 7:5 - reserved. read value is undefined, only zero should be written. na 9:8 spifisel selects the input clock for the usb clock divider. 0 0x0 sysclk is used as the input to the spifi clock divider. 0x1 the output of the main pll is used as the input to the spifi clock divider. 0x2 the output of the alt pll is used as the input to the spifi clock divider. 0x3 reserved, this setting should not be used. 31:10 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 35 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.3.4 external interrupts 3.3.4.1 external interrupt flag register when a pin is selected for its external interrupt function, the level or edge on that pin (selected by its bits in the extpolar and extmode registers) will set its interrupt flag in this register. this asserts the corresponding in terrupt r equest to the nvic, which will cause an interrupt if interrupts from the pin are enabled. writing ones to bits eint0 through eint3 in extint register clears the corresponding bits. in level-sensitive mode the interrupt is cleared only when the pin is in its inactive state. once a bit from eint0 to eint3 is set and an appropriate code starts to execute (handling wake-up and/or external interrupt), this bit in extint register must be cleared. otherwise event that was just triggered by activity on the eint pin will not be recognized in future. important: whenever a change of external interrupt operating mode (i.e. active level/edge) is performed (including the initialization of an external interrupt), the corresponding bit in the extint register must be cleared! for details see section 3.3.4.2 ? external interrupt mode register ? and section 3.3.4.3 ? external interrupt polarity register ? . for example, if a system wakes up from powe r-down using low level on external interrupt 0 pin, its post wake-up code must reset eint0 bit in order to allow future entry into the power-down mode. if eint0 bit is left set to 1, any subsequent attempt to invoke power-down mode will fail. the same g oes for external interrupt handling. more details on powe r-down mode will be discussed in the following chapters. table 25. external interrupt flag register (extint - address 0x400f c140) bit description bit symbol description reset value 0 eint0 in level-sensitive mode, this bit is set if the eint0 function is selected for its pin, and the pin is in its active state. in edge-sensitive mode, this bit is set if the eint0 function is selected for its pin, and the selected edge occurs on the pin. this bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state. [1] 0 1 eint1 in level-sensitive mode, this bit is set if the eint1 function is selected for its pin, and the pin is in its active state. in edge-sensitive mode, this bit is set if the eint1 function is selected for its pin, and the selected edge occurs on the pin. this bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state. [1] 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 36 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control [1] example: e.g. if the eintx is selected to be low level sensitive and low level is present on corresponding pin, this bit can not be cleared; this bit can be cleared only when signal on the pin becomes high. 3.3.4.2 external interrupt mode register the bits in this register select whether each ei nt pin is level- or edge-sensitive. only pins that are selected for the eint function (see section 7.3 ) and enabled in the appropriate nvic register) can cause interrupts from the ex ternal interrupt function (though of course pins selected for other functions may cause interrupts from those functions). note: software should only change a bit in this register when its interrupt is disabled in the nvic (state readable in the isern/icern registers), and should write the corresponding 1 to extint before enabling (initializing) or re-enabling the interrupt. an extraneous interrupt could be set by changing the mode and not having the extint cleared. 2 eint2 in level-sensitive mode, this bit is set if the eint2 function is selected for its pin, and the pin is in its active state. in edge-sensitive mode, this bit is set if the eint2 function is selected for its pin, and the selected edge occurs on the pin. this bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state. [1] 0 3 eint3 in level-sensitive mode, this bit is set if the eint3 function is selected for its pin, and the pin is in its active state. in edge-sensitive mode, this bit is set if the eint3 function is selected for its pin, and the selected edge occurs on the pin. this bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state. [1] 0 31:4 - reserved. read value is undefined, only zero should be written. na table 25. external interrupt flag register (extint - address 0x400f c140) bit description bit symbol description reset value table 26. external interrupt mode register (extmode - address 0x400f c148) bit description bit symbol value description reset value 0 extmode0 level or edge sensitivity select for eint0. 0 0 level sensitive. 1 edge sensitive. 1 extmode1 level or edge sensitivity select for eint1. 0 0 level sensitive. 1 edge sensitive. 2 extmode2 level or edge sensitivity select for eint2. 0 0 level sensitive. 1 edge sensitive. 3 extmode3 level or edge sensitivity select for eint3. 0 0 level sensitive. 1 edge sensitive. 31:4 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 37 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.3.4.3 external interrupt polarity register in level-sensitive mode, the bits in this register select whether the corresponding pin is high- or low-active. in edge-s ensitive mode, they select whether the pin is rising- or falling-edge sensitive. only pins that are selected for the eint function only pins that are selected for the eint function (see section 7.3 ) and enabled in the appropriate nvic register) can cause interrupts from the extern al interrupt function (t hough of course pins selected for other functions may caus e interrupts from those functions). note: software should only change a bit in this register when its interrupt is disabled in the nvic (state readable in the isern/icern registers), and should write the corresponding 1 to extint before enabling (initializing) or re-enabling the interrupt. an extraneous interrupt could be set by changing the polarity and not having the extint cleared. table 27. external interrupt polarity register (extpolar - address 0x400f c14c) bit description bit symbol value description reset value 0 extpolar0 external interru pt polarity for eint0 . 0 0 low-active or falling-edge sensitive (depending on extmode0). 1 high-active or rising-edge sensitive (depending on extmode0). 1 extpolar1 external interru pt polarity for eint1 . 0 0 low-active or falling-edge sensitive (depending on extmode1). 1 high-active or rising-edge sensitive (depending on extmode1). 2 extpolar2 external interru pt polarity for eint2 . 0 0 low-active or falling-edge sensitive (depending on extmode2). 1 high-active or rising-edge sensitive (depending on extmode2). 3 extpolar3 external interru pt polarity for eint3 . 0 0 low-active or falling-edge sensitive (depending on extmode3). 1 high-active or rising-edge sensitive (depending on extmode3). 31:4 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 38 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.3.5 device and peripheral reset 3.3.5.1 reset source identification register this register contains one bit for each source of reset. writing a 1 to any of these bits clears the corresponding read-side bit to 0. the interactions among the four sources are described below. table 28. reset source identification regist er (rsid - address 0x400f c180) bit description bit symbol description reset value 0 por assertion of the por signal sets this bit, and clears all of the other bits in this register. but if another reset signal (e.g., external reset) remains asserted after the por signal is negated, then its bit is set. this bit is not affected by any of the other sources of reset. see description 1 extr assertion of the external reset signal sets this bit. this bit is cleared only by software or por. see description 2 wdtr this bit is set when the watchdog timer times out and the wdtreset bit in the watchdog mode register is 1. this bit is cleared only by software or por. see description 3 bodr this bit is set when the v dd(reg)(3v3) voltage reaches a level below the bod reset trip level (typically 1.85 v under nominal room temperature conditions). if the v dd(reg)(3v3) voltage dips from the normal operating range to below the bod reset trip level and recovers, the bodr bit will be set to 1. if the v dd(reg)(3v3) voltage dips from the normal operating range to below the bod reset trip level and continues to decline to the level at which por is asserted (nominally 1 v), the bodr bit is cleared. if the v dd(reg)(3v3) voltage rises continuously from below 1 v to a level above the bod reset trip level, the bodr will be set to 1. this bit is cleared only by software or por. note: only in the case where a reset occurs and the por = 0, the bodr bit indicates if the v dd(reg)(3v3) voltage was below the bod reset trip level or not. see description 4 sysreset this bit is set if the processor has been reset due to a system reset request. setting the sysresetreq bit in the cortex-m4 aircr register causes a chip reset. this bit is cleared only by software or por. see description 5 lockup this bit is set if the processor has been reset due to a lockup of the cpu (see cortex-m4 documentation for details). the lockup state causes a chip reset. this bit is cleared only by software or por. see description 31:6 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 39 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.3.5.2 reset control register 0 many peripherals may be given a hardware reset using the rstcon0 register. some additional peripherals may be reset using the rstcon1 register following. table 29. reset control register 0 (rstco n0 - address 0x400f c1cc) bit description bit symbol description reset value 0 rstlcd lcd controller reset control bit. 0 1 rsttim0 timer/counter 0 reset control bit. 0 2 rsttim1 timer/counter 1 reset control bit. 0 3 rstuart0 uart0 reset control bit. 0 4 rstuart1 uart1 reset control bit. 0 5 rstpwm0 pwm0 reset control bit. 0 6 rstpwm1 pwm1 reset control bit. 0 7rsti2c0 the i 2 c0 interface reset control bit. 0 8 rstuart4 uart4 reset control bit. 0 9 rstrtc rtc and event monitor/recorder reset control bit. rtc reset is limited, see table 626 ? register overview: real-time clock (base address 0x4002 4000) ? for details. 0 10 rstssp1 the ssp 1 interface reset control bit. 0 11 rstemc external memory cont roller reset control bit. 0 12 rstadc a/d converter (adc) reset control bit. 0 13 rstcan1 can controller 1 reset control bit. note: the can acceptance filter may be reset by a separate bit in the rstcon1 register. 0 14 rstcan2 can controller 2 reset control bit. note: the can acceptance filter may be reset by a separate bit in the rstcon1 register. 0 15 rstgpio reset control bit for gpio, and gpio interrupts. note: iocon may be reset by a separate bit in the rstcon1 register. 0 16 rstspifi spi flash interface reset control bit. 0 17 rstmcpwm motor control pwm reset control bit. 0 18 rstqei quadrature encoder interface reset control bit. 0 19 rsti2c1 the i 2 c1 interface reset control bit. 0 20 rstssp2 the ssp2 interface reset control bit. 0 21 rstssp0 the ssp0 interface reset control bit. 0 22 rsttim2 timer 2 reset control bit. 0 23 rsttim3 timer 3 reset control bit. 0 24 rstuart2 uart 2 reset control bit. 0 25 rstuart3 uart 3 reset control bit. 0 26 rsti2c2 i 2 c interface 2 reset control bit. 0 27 rsti2s i 2 s interface reset control bit. 0 28 rstsdc sd card interface reset control bit. 0 29 rstgpdma gpdma function reset control bit. 0 30 rstenet ethernet block reset control bit. 0 31 rstusb usb interface reset control bit. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 40 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.3.5.3 reset control register 1 some additional peripherals may be given a hardware reset using the rstcon1 register, as shown in ta b l e 3 0 below. table 30. reset control register 1 (rstco n1 - address 0x400f c1d0) bit description bit symbol description reset value 0 rstiocon reset control bit for the iocon registers. 0 1 rstdac d/a converter (dac) reset control bit. 0 2 rstcanacc can acceptance filter reset control bit. 0 31:3 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 41 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.3.6 emc delay control and calibration 3.3.6.1 emc delay control register the emcdlyctl register controls on-chip programmable delays that can b used to fine tune timing to external sdram memories. dela ys can be configured in increments of approximately 250 picoseconds up to a maximum of roughly 7.75 ns. see section 9.5.6 for an overview of the programmable delays. figure 5 shows the detailed connections of the programmable delays. ta b l e 3 1 shows the bit assignments in emcdlyctl. fig 5. emc programmable delays 100811 0 1 0 1 0 1 0 1 programmable delay block emcdelayctl[4:0] emc_clk emcclkdelay 0.25 ns 0.5 ns 2 ns 1 ns programmable delay block clkout[0] or clkout[1] fbclkin emcdelayctl[12:8] programmable delay block clkout[0] emc_clkout[0] emcdelayctl[20:16] programmable delay block clkout[1] emc_clkout[1] emcdelayctl[28:24] 0 1 4 ns table 31. delay control register (emcdlyctl - 0x400f c1dc) bit description bit symbol description reset value 4:0 cmddly programmable delay value for emc outputs in command delayed mode. see section 9.13.6 . the delay amount is roughly (cmddly+1) * 250 picoseconds. this field applies only when the command delayed read strategy is selected in the emcdynamicreadconfig register. in this mode, all control outputs from the emc are delayed, but the output clock is not. delaying the control outputs changes dynamic characteristics defined in the device data sheet. 0x10 7:5 - reserved. read value is undefined, only zero should be written. na 12:8 fbclkdly programmable delay value for the feedback clock that controls input data sampling. see section 9.5.3 . the delay amount is roughly (fbclkdly+1) * 250 picoseconds. 0x02 15:13 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 42 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.3.6.2 emc calibration register the emccal register allows calibration of the emc programmable delays by providing a real-time representation of the value of those delays. delay settings that are in use in the application can be calibrated to compensate for intrinsic differences between devices, and for changes in ambient conditions. figure 6 below shows the delay calibration circuit. ta b l e 3 2 shows the bit assignments in emccal. 20:16 clkout0dly programmable delay value for the clkout0 output. this would typically be used in clock delayed mode. see section 9.13.6 the delay amount is roughly (clkout0dly+1) * 250 picoseconds. dela ying the clock outp ut changes dynamic characteristics defined in the device data sheet. 0 23:21 - reserved. read value is undefined, only zero should be written. na 28:24 clkout1dly programmable delay value for the clkout1 output. this would typically be used in clock delayed mode. see section 9.13.6 the delay amount is roughly (clkout1dly+1) * 250 picoseconds. 0 31:29 - reserved. read value is undefined, only zero should be written. na table 31. delay control register (emcdlyctl - 0x400f c1dc) bit description bit symbol description reset value fig 6. emc delay calibration 100813 8-bit counter 5-bit counter clear enable ring oscillator emccal register control clear enable overflow irc reference clock (factory calibrated to 12 mhz) 0 78 1314 15 31 16 ~50 mhz (varies with process, voltage, and temperature) calvalue (reserved) start done (reserved) table 32. emc calibration register (emccal - 0x400f c1e0) bit description bit symbol description reset value 7:0 calvalue returns the count of the approximatel y 50 mhz ring oscillator that occur during 32 clocks of the irc oscillator. this represents the co mposite effect of processing variation, internal regulator supply voltage, and ambient temperature. 0 13:8 - reserved. read value is undefined, only zero should be written. na 14 start start control bit for the emc calibration counter. writing a 1 to this bit begins the measurement process. this bit is cleare d automatically when the measurement is complete. 0 15 done measurement completion flag. this bit is set when a calibration measurement is completed. this bit is cleared automatically when the start bit is set. 0 31:16 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 43 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control procedure for calibrating programmable delays 1. write 1 to the start bit of the emccal register. 2. wait until the done bit of the same register becomes 1. other operations can be done during this time, the calibration requires 32 clocks of the 12 mhz irc clock, or about 2.7 microseconds. 3. read the calibration value from the bottom 8 bits of the emccal register. a typical value at room temperature is 0x86. 4. adjust one or more programmable delays if needed based on the calibration result. the calibration procedure should typically be repeated periodically, depending on how rapidly ambient conditions may change in the application environment.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 44 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.3.7 miscellaneous system control registers 3.3.7.1 system controls and status register the scs register contains special control and status bits related to various aspects of chip operation. these functi ons are described in ta b l e 3 3 . several of these bits apply to the main oscillator. since chip operation always begins using the internal rc oscillato r, and the main oscillator may not be used at all in some applications, it w ill only be started by software request. this is accomplished by setting the oscen bit in the scs register, as described in table 3-13. t he main oscillator provides a status flag (the oscstat bit in the scs re gister) so that software can determine when the oscillator is running and stable. at that point, software can cont rol switching to the main oscillator as a clock sour ce. prior to starting the main oscillator, a frequenc y range must be selected by configuring th e oscrange bit in the scs register. table 33. system controls and status register (scs - address 0x400f c1a0) bit description bit function value description access reset value 0 emcsc emc shift control. controls how addresses are output on the emc address pins for static memories. also see section 9.9 in the emc chapter. r/w 1 0 static memory addresses are shifted to match the data bus width. for example, when accessing a 32-bit wide data bus, the address is shifted right 2 places such that bit 2 is the lsb. in this mode, address bit 0 for the this device is connected to address bit 0 of the memory device, thus simplifying memory connections. this also makes a larger memory address range possible, because additional upper address bits can appear on the higher address pins due to the shift. 1 static memory addresses are always output as byte addresses regardless of the data bus width. for example, when word data is accessed on a 32-bit bus, address bits 1 and 0 will always be 0. in this mode, one or both lower address bits may not be connected to memories that are part of a bus that is wider than 8 bits. this mode matches the operation of lpc23xx and lpc24xx devices. 1 emcrd emc reset disable [1] . external memory controller reset disable. also see section 9.8 in the emc chapter. r/w 0 0 both emc resets are asserted when any type of chip reset event occurs. in this mode, all registers and functions of the emc are initialized upon any reset condition. 1 many portions of the emc are only rese t by a power-on or brown-out event, in order to allow the emc to retain its state through a warm reset (external reset or watchdog reset). if the emc is configured correctly, auto-refresh can be maintained through a warm reset. 2 emcbc external memory controller burst control. also see section 9.10 in the emc chapter. r/w 0 0 burst enabled. 1 burst disabled. this mode can be used to prevent multiple sequential accesses to memory mapped i/o devices connected to emc static memory chip selects. these unrequested accesses can cause issues with some i/o devices.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 45 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control [1] the state of this bit is preserved through a software reset, and only a por or a bod event will reset it to its default valu e. 3.3.7.2 lcd configuration register the lcd_cfg register controls the prescalin g of the clock used for lcd data generation. the contents of the lcd_cfg register are described in ta b l e 3 4 . 3 mcipwral mcipwr active level [1] . selects the active level of the sd card interface signal sd_pwr. r/w 1 0 sd_pwr is active low (inverted output of the sd card interface block). 1 sd_pwr is active high (follows the output of the sd card interface block). 4 oscrs main oscillator range select. r/w 0 0 the frequency range of the main oscillator is 1 mhz to 20 mhz. 1 the frequency range of the main oscillator is 15 mhz to 25 mhz. 5 oscen main oscillator enable. r/w 0 0 the main oscillator is disabled. 1 the main oscillator is enabled, and will start up if the correct external circuitry is connected to the xtal1 and xtal2 pins. 6 oscstat main oscillator status. ro 0 0 the main oscillator is not ready to be used as a clock source. 1 the main oscillator is ready to be used as a clock source. the main oscillator must be enabled via the oscen bit. 31:7 - reserved. read value is undefined, only zero should be written. - na table 33. system controls and status register (scs - address 0x400f c1a0) bit description bit function value description access reset value table 34. lcd configuration register (lcd_cf g, address - 0x400f c1b8) bit description bits symbol description reset value 4:0 clkdiv lcd panel clock prescaler selection. the value in the this register plus 1 is used to divide the selected input clock (see the clksel bit in the lcd_pol register), to produce the panel clock. 0 31:5 - reserved. read value is undefined, only zero should be written. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 46 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.3.7.3 can sleep clear register this register provides the cu rrent sleep state of the two can channels and provides a means to restore the clocks to that channel following wake-up. refer to section 20.8.2 ? sleep mode ? for more information on the can sleep feature. 3.3.7.4 can wake-up flags register this register provides the wake-up status for the two can channels and allows clearing wake-up events. refer to section 20.8.2 ? sleep mode ? for more information on the can sleep feature. table 35. can sleep clear register (cansl eepclr - address 0x400f c110) bit description bit symbol function reset value 0 - reserved. read value is undefined, only zero should be written. na 1 can1sleep sleep status and control for can channel 1. read: when 1, indicates that can channel 1 is in the sleep mode. write: writing a 1 causes clocks to be restored to can channel 1. 0 2 can2sleep sleep status and control for can channel 2. read: when 1, indicates that can channel 2 is in the sleep mode. write: writing a 1 causes clocks to be restored to can channel 2. 0 31:3 - reserved. read value is undefined, only zero should be written. na table 36. can wake-up flags register (canwakeflags - address 0x400f c114) bit description bit symbol function reset value 0 - reserved. read value is undefined, only zero should be written. na 1 can1wake wake-up status for can channel 1 . read: when 1, indicates that a falling edge has occurred on the receive data line of can channel 1. write: writing a 1 clears this bit. 0 2 can2wake wake-up status for can channel 2 . read: when 1, indicates that a falling edge has occurred on the receive data line of can channel 2. write: writing a 1 clears this bit. 0 31:3 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 47 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.3.7.5 usb interrupt status register the usb otg controller has seven interrupt lines. only the first three interrupts (usb_int_req_lp, usb_int_req_hp, and usb_int_req_hp) and the usb_need_clk signal are used for the device controller. the interrupt lines are ored together to a single channel of the vectored interrupt controller. th is register allows software to determine their status with a single read operation. table 37. usb interrupt status register - (u sbintst - address 0x400f c1c0) bit description bit symbol description reset value 0 usb_int_req_lp low priority interrupt line status. this bit is read-only. 0 1 usb_int_req_hp high priority interrupt line status. this bit is read-only. 0 2 usb_int_req_dma dma interrupt line status. this bit is read-only. 0 3 usb_host_int usb host interrupt line status. this bit is read-only. 0 4 usb_atx_int external atx interrupt line status. this bit is read-only. 0 5 usb_otg_int otg interrupt line status. this bit is read-only. 0 6 usb_i2c_int i 2 c module interrupt line status. this bit is read-only. 0 7 - reserved. read value is undefined, only zero should be written. na 8 usb_need_clk usb need clock indicator. this bit is read-only. this bit is set to 1 when usb activity or a change of state on the usb data pins is detected, and it indicates that a pll supplied clock of 48 mhz is needed. once usb_need_clk becomes one, it resets to zero 5 ms after the last packet has been received/sent, or 2 ms after the suspend change (sus_ch) interrupt has occurred. a change of this bit from 0 to 1 can wake up the microcontroller if activity on the usb bus is selected to wake up the part from the power-down mode (see section 3.12.8 ? wake-up from reduced power modes ? for details). also see section 3.10.3 ? plls and power-down mode ? and section 3.3.2.2 ? power control for peripherals registers ? for considerations about the pll and invoking the power-down mode. this bit is read-only. 1 30:9 - reserved. read value is undefined, only zero should be written. na 31 en_usb_ints enable all usb interrupts. when this bit is cleared, the nvic does not see the ored output of the usb interrupt lines. 1
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 48 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.3.7.6 dma request select register dmacreqsel is a read/write register that allows selecting between potential dma requests for dma inputs 0 through 7 and 10 through 15. table 38 shows the bit assignments of the dmacreqsel register. table 38. dma request select register bit description bit name description reset value 0 dmasel00 selects the dma request for gpdma input 0: 0 - (unused) 1 - timer 0 match 0 is selected. 0 1 dmasel01 selects the dma request for gpdma input 1: 0 - sd card interface is selected. 1 - timer 0 match 1 is selected. 0 2 dmasel02 selects the dma request for gpdma input 2: 0 - ssp0 transmit is selected. 1 - timer 1 match 0 is selected. 0 3 dmasel03 selects the dma request for gpdma input 3: 0 - ssp0 receive is selected. 1 - timer 1 match 1 is selected. 0 4 dmasel04 selects the dma request for gpdma input 4: 0 - ssp1 transmit is selected. 1 - timer 2 match 0 is selected. 0 5 dmasel05 selects the dma request for gpdma input 5: 0 - ssp1 receive is selected. 1 - timer 2 match 1 is selected. 0 6 dmasel06 selects the dma request for gpdma input 6: 0 - ssp2 transmit is selected. 1 - i 2 s channel 0 is selected. 0 7 dmasel07 selects the dma request for gpdma input 7: 0 - ssp2 receive is selected. 1 - i 2 s channel 1 is selected. 0 9:8 - reserved. read value is undefined, only zero should be written. - 10 dmasel10 selects the dma request for gpdma input 10: 0 - uart0 transmit is selected. 1 - uart3 transmit is selected. 0 11 dmasel11 selects the dma request for gpdma input 11: 0 - uart0 receive is selected. 1 - uart3 receive is selected. 0 12 dmasel12 selects the dma request for gpdma input 12: 0 - uart1 transmit is selected. 1 - uart4 transmit is selected. 0 13 dmasel13 selects the dma request for gpdma input 13: 0 - uart1 receive is selected. 1 - uart4 receive is selected. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 49 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.3.7.6.1 timer dma requests timer dma requests are generated by the timer when the timer value matches the related match register (see section 24.6.12 ). if the dma controller is configured so that a timer dma request is selected as an input to a dma channel, and the dma channel is enabled, the dma controller will act on that request. 3.3.7.7 clock output configuration register the clkoutcfg register controls the selection of the internal clock that appears on the clkout pin and allows dividing the clock by an integer value up to 16. the divider can be used to produce a system clock that is related to one of the on-chip clocks. for most clock sources, the division may be by 1. when the cpu clock is selected and is higher than approximately 50 mhz, the output must be divi ded in order to bring the frequency within the ability of the pin to switch wi th reasonable logic levels. if a clock is selected that is not running, there will be no signal on clkout. note: the clkout multiplexer is designed to switch cleanly, without glitches, between the possible clock sources. the divider is also designed to allow changing the divide value without glitches. 14 dmasel14 selects the dma request for gpdma input 14: 0 - uart2 transmit is selected. 1 - timer 3 match 0 is selected. 0 15 dmasel15 selects the dma request for gpdma input 15: 0 - uart2 receive is selected. 1 - timer 3 match 1 is selected. 0 31:16 - reserved. read value is undefined, only zero should be written. - table 38. dma request select register bit description ?continued bit name description reset value
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 50 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control table 39. clock output configuration register (clkoutcfg - 0x400f c1c8) bit description bit symbol description reset value 3:0 clkoutsel selects the clock source for the clkout function. 0x0 = selects the cpu clock as the clkout source. 0x1 = selects the main oscillator as the clkout source. 0x2 = selects the internal rc oscillator as the clkout source. 0x3 = selects the usb clock as the clkout source. 0x4 = selects the rtc oscillator as the clkout source. 0x5 = selects the spifi clock as the clkout source. 0x6 = selects the watchdog oscillator as the clkout source. other settings are reserved. do not use. 0 7:4 clkoutdiv integer value to divide the output clock by, minus one. 0x0 = clock is divided by 1. 0x1 = clock is divided by 2. 0x2 = clock is divided by 3. ... 0xf = clock is divided by 16. 0 8 clkout_en clkout enable control, allows switching the clkout source without glitches. clear to stop clkout on the next falling edge. set to enable clkout. 0 9 clkout_act clkout activity indication. reads as 1 when clkout is enabled. read as 0 when clkout has been disabled via the clkout_en bit and the clock has completed being stopped. 0 31:10 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 51 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.4 chip reset reset has 6 sources: the reset pin, watchdog reset, power on reset (por), brown out detect (bod), sy stem reset, and lockup. the reset pin is a schmitt trigger input pin. assertion of chip reset by any source, once the operating voltage attains a usable level, starts the wake-up timer (see description in section 3.13 ? wake-up timer ? in this chapter), causing reset to remain asserted until the external reset is de-a sserted, the oscillator is running, a fi xed number of clocks have passed, and the flash controller has completed it s initialization. the reset logic is shown in the following block diagram (see figure 7 ). on the assertion of a reset source external to the cpu (por, bod reset, external reset, and watchdog reset), the irc starts up. afte r the irc-start-up time (maximum of 60 ? s on power-up) and after the irc provides a stable clock output, the reset signal is latched and synchronized on the irc clock. then the following two sequences start simultaneously: 1. the 2-bit irc wake-up timer starts counting when the synchronized reset is de-asserted. the boot code in the rom starts when the 2-bit irc wake-up timer times out. the boot code performs the boot tasks an d may jump to the flash. if the flash is not ready to acce ss, the flash accelerato r will insert wait cycles until the flash is ready. 2. the flash wake-up timer (9-bit) starts counting when the synchronized reset is de-asserted. the flash wakeup-timer generates the 100 ? s flash start-up time. once it times out, the flash initialization sequence is started, which takes about 250 cycles. when it?s done, the flas h accelerator will be gran ted access to the flash. when the internal reset is removed, the proc essor begins executing at address 0, which is initially the reset vector mapped from the bo ot block. at that point, all of the processor and peripheral registers have been in itialized to predetermined values. figure 8 shows an example of the re lationship between the reset , the irc, and the processor status when the device starts up after reset. see section 3.8.2 ? main oscillator ? for start-up of the main oscillato r if selected by the user code. fig 7. reset block diagram 120601 watchdog reset por bod external reset clr q set reset to on-chip circuitry wake-up complete system reset lockup to wake-up logic
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 52 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control fig 8. example of start-up after reset valid threshold processor status v dd(reg)(3v3) irc status reset gnd 60 s 1 s; irc stability count boot time boot code executing user code boot code execution finishes; user code starts irc starts irc stable supply ramp-up time
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 53 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.5 peripheral reset control most peripheral functions can have a hardware reset initiated by software by setting appropriate bits in the rstcon0 and rstc on1 registers. software must clear the rstcon register after this in order to a llow the peripheral to function. a peripheral remains in a hardware reset state as long as the corresponding bit in rstcon = 1.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 54 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.6 brown-out detection a brown-out detector (bod) is included that provides 2-stage monitoring of the voltage on the v dd(reg)(3v3) pins. if this voltage falls below the bod interrupt trip level (typically 2.2 v under nominal room temperature conditions), the bod asserts an interrupt signal to the nvic. this signal can be enabled for interrupt in the interrupt enable register in the nvic in order to cause a cpu interrupt; if not, software can monitor the signal by reading the raw interrupt status register. the second stage of low-voltage detection asserts reset to inactivate the device when the voltage on the v dd(reg)(3v3) pins falls below the bod rese t trip level (typically 1.85 v under nominal room temperature conditions). this reset prevents alteration of the flash as operation of the various elements of th e chip would otherwise become unreliable due to low voltage. the bod circuit maintains this reset down below 1 v, at which point the power-on reset circuitry maintains the overall reset. both the bod reset interrupt level and the bo d reset trip level thresholds include some hysteresis. in normal operatio n, this hysteresis allows the bod reset interrupt level detection to reliably interrupt, or a regularly -executed event loop to sense the condition. but when brown-out detection is enabled to bring the device out of power-down mode (which is itself not a guaranteed operation -- see section 3.3.2.1 ? power mode control register ? ), the supply voltage may recover from a transient before the wake-up timer has completed its delay. in this case, the net result of the transient bod is that the part wakes up and continues operation after the instructions that set power-down mode, without any interrupt occurring and with the bod bit in the rsid being 0. since all other wake-up conditions have latching flags (see section 3.3.4.1 ? external interrup t flag register ? and section 29.6.2 ), a wake-up of this type, without any apparent cause, can be assumed to be a brown-out that was too short to be fully captured.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 55 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.7 external interrupt inputs four external interrupt inputs are included as selectable pin functions. the logic of an individual external interrupt is represented in figure 9 . in addition, extern al interrupts have the ability to wake up the cpu from power-down mode. refer to section 3.12.8 ? wake-up from reduced power modes ? for details. fig 9. external interrupt logic interrupt flag (one bit of extint) write to extinti internal reset einti to wake-up logic einti pin extmodei pclk to interrupt controller extpolari einti interrupt enable pclk 1 glitch filter apb read of extinti q s r q s r q s d 120601
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 56 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.7.1 register description the external interrupt function has four regist ers associated with it. the extint register contains the interrupt flags. the extmode and extpolar registers specify the level and edge sensitivity parameters. [1] reset value reflects the data stored in used bits only. it does not include reserved bits content. table 40. external interrupt registers name description access reset value [1] address extint the external interrupt flag register contains interrupt flags for eint0, eint1, eint2 and eint3. see table 25 . r/w 0x00 0x400f c140 extmode the external interrupt mode regist er controls whether each pin is edge- or level-sensitive. see ta b l e 2 6 . r/w 0x00 0x400f c148 extpolar the external interrupt polarity register controls which level or edge on each pin will cause an interrupt. see ta b l e 2 7 . r/w 0x00 0x400f c14c
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 57 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.8 oscillators three indepen dent oscillators are included. these are the main oscillator, the internal rc oscillator, and the rtc oscillator. each oscillator can be used for more than one purpose as required in a particular application. this can be seen in figure 4 . following reset, the device will operate from the internal rc oscillato r until switched by software. this allows systems to operate wit hout any external crystal, and allows the boot loader code to operate at a known frequency. 3.8.1 internal rc oscillator the internal rc oscillator (irc) may be us ed as the clock that drives pll0 and subsequently the cpu. the precision of t he irc does not allow for use of the usb interface, which requires a much more precise time base in order to comply with the usb specification (only the main o scillator can meet that specif ication). also, the irc should not be used with the can1/2 block if the can baud rate is higher than 100 kbit/s.the irc frequency is 12 mhz, factory tr immed to within 1% accuracy. upon power-up or any chip rese t, the irc is used as the cl ock source. software may later switch to one of the other available clock sources. 3.8.2 main oscillator the main oscillator can be used as the clock source for the cpu, with or without using pll0. the main oscillato r operates at frequencies of 1 mhz to 25 mhz. this frequency can be boosted to a higher frequency, up to the maximum cpu operating frequency, by the main pll (pll0). th e oscillator ou tput is called osc_clk. t he clock selected as the pll0 input is pllclkin and the arm processo r clock frequency is referred to as cclk for purposes of rate equations, etc. elsewh ere in this document. the frequencies of pllclkin and cclk are the same value unless the pll0 is active and connected. refer to section 3.10 for details. the on-board oscillator can ope rate in one of two modes: slave mode and oscillation mode. in slave mode the input clock signal should be coupled by means of a capacitor of 100 pf (c c in figure 10 , drawing a), with an amplitude between 200 mvrms and 1000 mvrms. this corresponds to a square wave signal with a signal swing of between 280 mv and 1.4 v. the xtal2 pin in this configuration can be left unconnected. external components and models used in oscillation mode are shown in figure 10 , drawings b and c, and in ta b l e 4 1 and ta b l e 4 2 . since the feedback resistance is integrated on chip, only a crys tal and the capacitances c x1 and c x2 need to be connected externally in case of fund amental mode oscillation (the fundamental frequency is represented by l, c l and r s ). capacitance c p in figure 10 , drawing c, represents the parallel package capacitance and should not be larger than 7 pf. parameters f c , c l , r s and c p are supplied by the crystal manufacturer.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 58 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control fig 10. oscillator modes and models: a) slave mode of oper ation, b) oscillation mode of operation, c) external crystal model used for c x1 / x2 evaluation microcontroller microcontroller clock c c c x1 c x2 c l c p l r s < = > a) b) c) xtal xtal1 xtal2 xtal1 xtal2 table 41. recommended values for c x1/x2 in oscillation mode (crystal and external components parameters) low frequency mode (oscrange = 0, see table 33 ) fundamental oscillation frequency f osc crystal load capacitance c l maximum crystal series resistance r s external load capacitors c x1 , cx2 1mhz - 5mhz 10 pf < 300 ? 18 pf, 18 pf 20 pf < 300 ? 39 pf, 39 pf 30 pf < 300 ? 57 pf, 57 pf 5 mhz - 10 mhz 10 pf < 300 ? 18 pf, 18 pf 20 pf < 200 ? 39 pf, 39 pf 30 pf < 100 ? 57 pf, 57 pf 10 mhz - 15 mhz 10 pf < 160 ? 18 pf, 18 pf 20 pf < 60 ? 39 pf, 39 pf 15 mhz - 20 mhz 10 pf < 80 ? 18 pf, 18 pf table 42. recommended values for c x1/x2 in oscillation mode (crystal and external components parameters) high fr equency mode (oscrange = 1, see table 33 ) fundamental oscillation frequency f osc crystal load capacitance c l maximum crystal series resistance r s external load capacitors c x1 , cx2 15 mhz - 20 mhz 10 pf < 180 ? 18 pf, 18 pf 20 pf < 100 ? 39 pf, 39 pf 20 mhz - 25 mhz 10 pf < 160 ? 18 pf, 18 pf 20 pf < 80 ? 39 pf, 39 pf
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 59 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.8.2.1 main oscillator startup since chip operation always begins using th e internal rc oscillator, and the main oscillator may not be used at a ll in some applications, it will only be started by software request. this is accomplished by setting the oscen bit in the scs register, as described in ta b l e 3 3 . the main oscillato r provides a status flag (t he oscstat bit in the scs register) so that software can determine when the oscillator is running and stable. at that point, software can cont rol switching to the main oscilla tor as a clock source. prior to starting the main oscillator, a frequency range must be selected by configuring the oscrange bit in the scs register. 3.8.3 rtc oscillator the rtc oscillator provides a 1 hz clock to the rtc and a 32 khz cl ock output that can be output on the clkout pin in order to allow trimming the rtc oscillator without interference from a probe. 3.8.4 watchdog oscillator the watchdog timer has a dedicated oscilla tor that provides a 500 khz clock to the watchdog timer that is always running if the watchdog timer is enabled. the watchdog oscillator clock can be output on the clkout pin in order to allow observe its frequency. in order to allow watchdog timer operation with minimum power consumption, which can be important in reduced power modes, the watchdog oscillator frequ ency is not tightly controlled. the watchdog osc illator frequency will vary over temperat ure and power supply within a particular pa rt, and may vary by processing across different parts. this variation should be taken into account when determining watchdog reload values. within a particular part, temperature and power supply variations can produce up to a 17% frequency variation. frequency variation between devices under the same operating conditions can be up to 30%.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 60 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.9 clock source selection multiplexer two clock sources may be chosen to drive the system clock (sysclk) and pll0. these are the internal rc oscillator and the main oscillator. the clock source selection should only be ch anged safely when pll0 is not connected. for a detailed description of how to change the clock source in a system using pll0 see section 3.10.6 ? pll configuration sequence ? .
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 61 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.10 pll0 and pll1 (phase locked loops) pll0 (also called the main pll) and pll1 (also called the alt pll) are functionally identical, but have somewhat di fferent input possibilities and output connec tions. these possibilities are shown in figure 4 . the main pll can receive its input from either the irc or the main oscillator, and can potentially be used to pr ovide the clocks to nearly everything on the devi ce. the alt pll receives its input only from the main oscillator and is intended to be used as an alternate source of clocking to the usb and the spifi. this peripheral has timing needs that may not always be filled by the main pll. both plls are disabled and powered off on re set. if the alt pll is left disabled, the usb and spifi clocks can be supplied by pll0 if ev erything is set up to provide 48 mhz to the usb clock and the desired spifi clock through that route. the source for each clock must be selected via the clksel registers (see section 3.11 ), and can be further reduced by clock dividers as needed. pll activation is controlled via the pllcon registers. pll multiplier and divider values are controlled by the pllcfg registers. the pllcfg registers are protected in order to prevent accidental deactivation of plls or accidental alteration pll operating parameters. the protection is accomplished by a feed sequence similar to that of the watchdog timer. details are provided in t he descriptions of the pllfeed registers. pll0 accepts an input clock fre quency from either the irc or the main oscilla tor. if only the main pll is used, then its output frequency must be an integer multiple of all other clocks needed in the system. pl l1 takes its input only from th e main oscillator, requiring an external crystal in the range of 10 to 25 mhz. in each pll, the current controlled oscillator (cco) operates in the range of 156 mhz to 320 mhz, so there are additional dividers to bring the output down to the de sired frequencies. the minimum output divider value is 2, insuring that the output of the plls have a 50% duty cycle. figure 11 shows a block diagram of pll internal connections. if the usb is used, the possibilities for the cp u clock and other clocks will be limited by the requirements that the frequency be precise and very low jitter, and that the pll0 output must be a multiple of 48 mhz. even multiples of 48 mhz that are within the operating range of the pll f cco are 192 and 288 mhz. also, only the main oscillator in conjunction with the pll can meet the precision and jitter specifications for usb. it is due to these limitations that the alt pll is provided. the alt pll accepts an input clock frequency from the main oscillator in the range of 10 mhz to 25 mhz only. when used as the usb clock, the input frequency is multiplied up to a multiple of 48 mhz (192 or 288 mhz as described above). the alt pll can also provide the clock to the spifi through a separate divider, if needed. 3.10.1 pll and startup/b oot code interaction when there is no valid user code (determined by the checksum word) in the user flash or the isp enable pin (p2[10]) is pulled low on startup, the isp mode will be entered and the boot code will setup the main pll with the irc. therefore it ca n not be assumed that the main pll is disabled when the user opens a debug session to debug the application code. the user startup code must follow the st eps described in this chapter to disconnect the main pll.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 62 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.10.2 pll register description the plls are controlled by the registers shown in ta b l e 4 3 . more detailed descriptions follow. warning: improper setting of pll values may result in incorrect operation of the usb subsystem! [1] reset value reflects the data stored in used bits only. it does not include reserved bits content. table 43. pll1 registers generic name description access reset value [1] plln register name and address table pllcon pll control register. holding register for updating pll control bits. values written to this register do not take effect until a valid pll feed sequence has taken place. r/w 0 pll0con - 0x400f c080 pll1con - 0x400f c0a0 10 pllcfg pll configuration register. holding register for updating pll configuration values. values written to this register do not take effect until a valid pll feed sequence has taken place. r/w 0 pll0cfg - 0x400f c084 pll1cfg - 0x400f c0a4 11 pllstat pll status register. read-back register for pll control and configuration information. if pllcon or pllcfg have been written to, but a pll feed sequence has not yet occurred, they will not reflect the current pll state. reading this register provides the actual values controlling pll, as well as pll status. ro 0 pll0stat - 0x400f c088 pll1stat - 0x400f c0a8 12 pllfeed pll feed register. this register enables loading of pll control and configuration information from the pllcon and pllcfg registers into the shadow registers that actually affect pll operation. wo na pll0feed - 0x400f c08c pll1feed - 0x400f c0ac 13 fig 11. pll0 and pll1 block diagram 120601 pll output clock divide by 2p phase detector plock pllstat[10] current- controlled oscillator fcco psel pllstat[6:5] pll input clock divide by m msel pllstat[4:0]
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 63 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.10.3 plls and power-down mode power-down mode automatically turns off and disconnects activated plls, while subsequent wake-up from power-down mode d oes not automatically restore pll settings. this must be done in software. typically, a ro utine to activate a pl l, wait for lock, and then select the pll can be called at the begi nning of any interrupt service routine that might be called due to the wake-up. if activity on the usb data lines is not se lected to wake the microcontroller from power-down mode (see section 3.12.8 for details of wake up from reduced modes), both the main pll (pll0) and the alt pll (pll1) will be automatically be turned off and disconnected when power-down mode is invoked, as described above. however, if the usb activity interrupt is enab led and usb_need_clk = 1 (see ta b l e 2 5 3 for a description of usb_need_clk), it is not possible to go into power-down mode and any attempt to set the pd bit will fail, leaving the plls in the current state.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 64 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.10.4 pll frequency calculation equations for both the main and alt plls use the following parameters: the pll output frequency (when the pll is active and locked) is given by: pll_out_clk = m ? pll_in_clk - or - pll_out_clk = f cco / (2 ? p) the cco frequency can be computed as: f cco = pll_out_clk ? 2 ? p- or -f cco = pll_in_clk ? m ? 2 ? p the pll inputs and settings must meet the following criteria: ? m is in the range of 1 to 32. ? p is one of 1, 2, 4, 8. ? pll_in_clk is in the ra nge of 10 mhz to 25 mhz. ? f cco is in the range of 156 mhz to 320 mhz. ? pll_out_clk is in the range of 9.75 mhz to 160 mhz. 3.10.5 procedure for determining pll settings in general, pll configuration values may be found as follows: 1. based on the desired pll output freque ncy, choose an oscillator frequency (f osc ). if the usb interface is to be used, an external crystal of either 12 mhz, 16 mhz, or 24 mhz must be provided. 12 mhz is recommen ded for this purpose in order to save power and have more flexibility with pll settings. 2. if the usb interface is used in the system, and if a pll output of 96 mhz or 144 mhz can provide the desired cpu clock frequency, it is probably possible to use only pll0. 3. calculate the value of m to configure the msel1 bits to obtain the desired pll output frequency. m = pll_out_clk / pll_in_clk. the value written to the msel bits in the pllcfg register is m ? 1 (or see ta b l e 4 5 ). this is done for both plls if they are both used. table 44. elements determining pll frequency element description pll_in_clk the frequency of the input to the pll f cco the frequency of the pll cu rrent controlled oscillator pll_out_clk the pll output frequency m pll multiplier value from the msel bits in the pllcfg register p pll divider value from the psel bits in the pllcfg register
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 65 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 4. find a value for p to configure the psel bits, such that f cco is within its defined operating frequency limits of 156 mhz to 320 mhz. f cco is calculated using f cco = pll_out_clk ? 2 ? p. the value written to the psel bits in pllcfg can be found in ta b l e 4 6 . table 45. pll multiplier values value of m msel bits (pllcfg bits [4:0]) msel hex 1 00000 0 2 00001 0x01 3 00010 0x02 4 00011 0x03 5 00100 0x04 6 00101 0x05 7 00110 0x06 8 00111 0x07 9 01000 0x08 10 01001 0x09 11 01010 0x0a 12 01011 0x0b 13 01100 0x0c 14 01101 0x0d 15 01110 0x0e 16 01111 0x0f 17 10000 0x10 18 10001 0x11 19 10010 0x12 20 10011 0x13 21 10100 0x14 22 10101 0x15 23 10110 0x16 24 10111 0x17 25 11000 0x18 26 11001 0x19 27 11010 0x1a 28 11011 0x1b 29 11100 0x1c 30 11101 0x1d 31 11110 0x1e 32 11111 0x1f
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 66 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.10.6 pll configuration sequence the following discussions refer to plls and pll related registers generically (e.g. pllcfg rather than pll0cfg or pll1cfg). th e instructions have to be adapted to the specific case being addressed in the application. to set up a pll and switch clocks to its output: 1. make sure that the pll output is not already being used. the cclksel, usbclksel, and spificlksel registers must not select the pll being set up (see ? to switch clocks away from a pll output: ? below). clock dividers included in these registers may also be set up at this time if writing to any of the noted registers. 2. if the main pll is being set up, and the main clock source is being changed (irc versus main oscillator), change this firs t by writing the correct value to the clksrcsel register. 3. write pll new setup values to the pllcfg register. write a 1 to the plle bit in the pllcon register. perform a pll feed sequence by writing first the value 0xaa, then the value 0x55 to the pllfeed register. 4. set up the necessary cloc k dividers. these may incl ude the cclksel, pclksel, emcclksel, usbclksel, and th e spificlksel registers. 5. wait for the pll to lock. this may be a ccomplished by polling th e pllstat register and testing for plock = 1, or by using the pll lock interrupt. 6. connect the pll by selecting it output in the appropriate places. this may include the cclksel, usbclksel, and spificlksel registers. to switch clocks away from a pll output: 1. to switch back to the mode of not using a pll, write values to any or all of the cclksel, usbclksel, and spificl ksel registers in order to select a different clock source. 2. the related pll may now be turned off by writing to the pllcon register and performing a pll feed sequence, reconfigured by writing to the pllcfg register, etc. table 46. pll divider values value of p psel bits (pllcfg bits [6:5]) psel hex 10 00 20 10 x 1 41 00 x 2 81 10 x 3
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 67 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.10.7 pll configuration examples the following examples illustrate selectin g pll values based on different system requirements. example 1) . assumptions: ? the system design is planned to use the irc to generate the cpu clock. ? a frequency as close to 80 mhz as po ssible is desired for the cpu clock. of the two plls, only pll0 can supply the cp u clock, so this example is for pll0. the nearest multiple of the 12 mhz irc frequency to 80 mhz is 84 mhz. since pll_out_clk = m ? pll_in_clk, m = pl l_out_clk / pll_in_clk = 84 / 12 = 7. now a value for p must be found that puts f cco within the pll operating range of 156 mhz to 320 mhz. f cco = pll_out_clk ? 2 ? p. start by finding the value of f cco with p = 1, which is 84 mhz ? 2 = 168 mhz. since that is within the pll operating range, no further work is needed. set up the pll for m = 7and p = 1. this requires putting the value 6 (m - 1, or see table 45 ? pll multiplier values ? ) in the msel field of the pll0cfg register. a value of 0 (see table 46 ? pll divider values ? ) is needed in the psel field of pll0cfg. a single write of both values would be pll0cfg = 0x06. see section 3.10.6 for a description of the pll setup sequence. example 2) . assumptions: ? the system design is planned to use a 12 mhz crystal generate both the cpu clock and the usb clock. ? a frequency close to 100 mhz is desired for the cpu clock. of the two plls, only pll0 can supply both the cpu clock and the usb clock, so this example is for pll0. the pll output must be an even integer multiple of 48 mhz for the usb to operate correctly (i.e. a multiple of 96 mhz). two multiples of 96 mhz fit within the pll operating range: 192 mhz (2 ? 96 mhz), and 288 mhz (3 ? 96 mhz). of these, only 192 mhz can produce a cpu clock near 100 mhz (96 mhz). so, a 96 mhz pll output can be used to obtain the 2 needed frequencies. since pll_out_clk = m ? pll_in_clk, m = pll_out_clk / pll_in_clk = 96 / 12 = 8. now a value for p must be found that puts f cco within the pll operating range of 156 mhz to 320 mhz. f cco = pll_out_clk ? 2 ? p. start by finding the value of f cco with p = 1, which is 96 mhz ? 2 = 192 mhz. since that is within the pll operating range, no further work is needed. set up the pll for m = 8 and p = 1. this requires putting the value 7 (m - 1, or see ta b l e 4 5 ) in the msel field of the pll0cfg register. a value of 0 (see table 46 ) is needed in the psel field of pll0cfg. a single write of both values would be pll0cfg = 0x07. see section 3.10.6 for a description of the pll setup sequence. example 3)
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 68 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control assumptions: ? the system design will use the usb interface. ? it is desired that the cpu clock remain flexible and able to operate at frequencies unrelated to the usb clock. in order to keep the cpu clo ck separate form the usb clock, the cpu will use pll0. for usb, pll1 may be configured with the same values used in the last example. pll0 can be operated from ei ther the irc or the main oscillator to obtain whatever frequency is needed, and the pll0 setup can be changed without compromising usb operation. 3.11 clock selection and division the output of each pll that is used must be divided down to whatever frequency is needed by each subsystem. there are separa te clocks for the cpu, external memory controller, usb interface, spifi, and peri pherals on the apb buses. separate clock selection multiplexers and cl ock dividers provide flexibilit y in the generation of these clocks. 3.12 power control a variety of power control features are supported: sleep mode, deep sleep mode, power-down mode, and deep power-down mode. the cpu clock rate may also be controlled as needed by changing clock so urces, re-configuring pll values, and/or altering the cpu clock divider value. this a llows a trade-off of po wer versus processing speed based on application requirements. in addition, peripheral power control allows shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. a power boost feature a llows operation up to 120 mhz, or power savings when operation is at or below 100 mhz. entry to any reduced power mode begins with the execution of either a wfi (wait for interrupt) or wfe (wait for exception) instruction by th e cpu. the cpu internally supports two reduced power modes: sleep an d deep sleep. these are selected by the sleepdeep bit in the cortex-m4 system co ntrol register. power-down and deep power-down modes are selected by bits in the pcon register. see table 14 . the same register contains flags that indicate whether entry into each reduced power mode actually occurred. a separate power domain is implemented in order to allow turning off power to the bulk of the device while maintaining operation of the real time clock. reduced power modes have some limitation during debug, see section 39.7 for more information. 3.12.1 sleep mode note: sleep mode on these devices corresponds to the idle mode on older lpc2xxx series devices. the name is changed because arm has incorporated portions of reduced power mode control into the cortex-m4.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 69 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control when sleep mode is entered, the clock to the core is stopped, and the smflag bit in pcon is set, see ta b l e 1 4 .resumption from the sleep mode does not need any special sequence but re-enabling the clock to the arm core. in sleep mode, execution of instructions is su spended until either a reset or an interrupt occurs. peripheral functions continue operation during sleep mode and may generate interrupts to cause the processor to resume execution. sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. the dma controller can continue to work in sleep mode, and has access to the peripheral srams and all peripheral registers. the fl ash memory and the main sram are not available in sleep mode, they are disabled in order to save power. wake-up from sleep mode will occur wh enever any enabled interrupt occurs. 3.12.2 deep sleep mode note: deep sleep mode on these devices corresponds to the sleep mode on older lpc23xx and lpc24xx series devices. the name is changed because arm has incorporated portions of reduced power mode control into the cortex-m4. when the chip enters the deep sleep mode, the main oscillator is powered down, nearly all clocks are stopped, and the dsflag bit in pcon is set, see ta b l e 1 4 . the irc remains running for fast startup. the 32 khz rtc oscillator is not stoppe d and rtc interrupts may be used as a wake-up source. the flash is left in the standby mode allowing a quick wake-up. the plls are automatically turned off and the clock selection multiplexers are set to use sysclk (the reset state). the clock divider control registers are automatically reset to zero. the processor state and registers, peripheral registers, and internal sram values are preserved throughout deep sleep mode and the logic levels of chip pins remain static. the deep sleep mode can be terminated and normal operation resumed by either a reset or certain specific interrupts that ar e able to function without clocks. since all dynamic operation of the chip is suspend ed, deep sleep mode reduces chip power consumption to a very low value. on the wake-up of deep sleep mode, if the irc was used before entering deep sleep mode, a 2-bit irc timer starts counting and t he code execution and peripherals activities will resume after the timer expire s (4 cycles). if the main oscillator is used, the 12-bit main oscillator timer starts counting and the code execution will resume when the timer expires (4096 cycles). the user must remember to re-configure any required plls and clock dividers after the wake-up. wake-up from deep sleep mode can be brought about by nmi, external interrupts eint0 through eint3, gpio interrupts, the ether net wake-on-lan interrupt, brownout detect, an rtc alarm interrupt, a usb input pin trans ition (usb activity in terrupt), a can input pin transition, or a watchdog timer timeout, when the related interrupt is enabled. wake-up will occur wh enever any enabled interrupt occurs.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 70 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.12.3 power-down mode power-down mode does everythi ng that deep sleep mode does, but also turns off the flash memory. entry to power-down mode causes the pdflag bit in pcon to be set, see ta b l e 1 4 . this saves more power, but requires waiting for resumption of flash operation before execution of code or data access in the flash memory can be accomplished. when the chip enters power-do wn mode, the irc, the main oscillator, and all clocks are stopped. the rtc remains running if it has been enabled and rtc interrupts may be used to wake up the cpu. the flash is fo rced into power-down mode. the plls are automatically turned off and the clock select ion multiplexers are se t to use sysclk (the reset state). the clock divider control regist ers are automatically re set to zero. if the watchdog timer is running, it will co ntinue running in power-down mode. upon wake-up from power-down mode, if t he irc was used before entering power-down mode, after irc-start-up time (about 60 ? s), the 2-bit irc timer starts counting and expiring in 4 cycles. code execution can then be resumed immediately following the expiration of the irc timer if the code was running from sram. in the meantime, the flash wake-up timer measures flash start-up time of about 100 ? s. when it times out, access to the flash is enabled. the user must remember to re-configure any required plls and clock dividers after the wake-up. wake-up from power-down mode can be brought about by nmi, external interrupts eint0 through eint3, gpio interrupts, the ether net wake-on-lan interrupt, brownout detect, an rtc alarm interrupt, a usb input pin transi tion (usb activity interrupt), or a can input pin transition, when the related interrupt is enabled. 3.12.4 deep power-down mode in deep power-down mode, power is shut off to the entire chip with the exception of the real-time clock, the reset pin, the wic, and the rtc backup registers. entry to deep power-down mode causes the dpdflag bit in pcon to be set, see ta b l e 1 4 . to optimize power conservation, the user ha s the additional option of turning off or retaining power to the 32 khz osc illator. it is also possible to use external circ uitry to turn off power to the on-chip regulator via the v dd(reg)(3v3) pins and/or the i/o power via the v dd(3v3) pins after entering deep power-down mode. power must be restored before device operation can be restarted. wake-up from deep power-do wn mode will occur when an external rese t signal is applied, or the rtc interrupt is enabled and an rtc interrupt is generated. 3.12.5 peripheral power control a power control for peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings. this is detailed in the description of the pconp register. 3.12.6 power boost a power boost feature allows operation above 100 mhz, to the upper limit for this device of 120 mhz. this boost is on by default when user code begins after a chip reset. power can be saved by turning of th is mode when operat ion will be at 100 mhz or lower. see section 3.3.2.3 .
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 71 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.12.7 register description the power control function uses registers shown in ta b l e 4 7 . more detailed descriptions follow. [1] reset value reflects the data stored in used bi ts only. it does not include reserved bits content. 3.12.8 wake-up from re duced power modes any enabled interrupt can wake up the cpu from sleep mode. certain interrupts can wake up the processor if it is in eith er deep sleep mode or power-down mode. interrupts that can o ccur during deep sleep or power-down mo de will wake up the cpu if the interrupt is en abled. after wake-up, ex ecution will continue to th e appropriate interrupt service routine. these interrupts are nmi, ex ternal interrupts eint 0 through eint3, gpio interrupts, ethernet wake-on- lan interrupt, brownout detect, rtc alarm, can activity interrupt, usb activity interrupt, and watch dog timer timeout. for the wake-up process to take place, the corresponding interrupt must be enabled in the nvic. for pin-related peripheral functions, the related functions must also be mapped to pins. the can activity interrupt is generated by activity on the can bus pins, and the usb activity interrupt is generated by activity on the usb bus pins. these interrupts are only useful to wake up the cpu when it is on deep sleep or power-down mode, when the peripheral functions are powered up, but not ac tive. typically, if these interrupts are used, their flags should be polled just before enabling the interrupt and entering the desired reduced power mode. this can save time and power by avoiding an immediate wake-up. upon wake-up, the interrupt service can turn off the related activity interrupt, do any application specific setup, and exit to await a normal peripheral interrupt. in deep power-down mode, intern al power to most of the device is removed, which limits the possibilities for waking up from this m ode. external reset ca n wake-up the device. also, of the rtc is running and has been set up to cause an interrupt, that event can wake-up the device. 3.12.9 power control usage notes after every reset, the pconp register contains the value that enables selected interfaces and peripherals controlled by the pconp to be enabled. therefore, apart from proper configuring via peripheral dedicated registers, the user?s application might have to access the pconp in order to start using some of the on-board peripherals. table 47. power control registers name description access reset value [1] address table pcon power control register. this register contains control bits that enable some reduced power operating modes. see ta b l e 1 4 . r/w 0 0x400f c0c0 14 pconp power control for peripherals register. this register contains control bits that enable and disable individual peripheral functions, allowing elimination of power consumption by peripherals that are not needed. see table 16 . r/w 0x0408 829e 0x400f c0c4 16 pboost power boost control register. th is register controls the output of the main on-chip regulator, allowing a choice between high-speed operation above 100 mhz, or power savings when operation is at 100 mhz or lower. r/w 0x3 0x400f c1b0 18
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 72 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control power saving oriented systems should have 1s in the pconp register only in positions that match peripherals that are actually used in the application. all other bits, declared to be "reserved" or dedicated to the peripherals not used in the current application, must be cleared to 0. 3.12.10 power domains two independent power domains are provided that allow the bulk of the device to have power removed while maintaining op eration of the real time clock. the v bat pin supplies power only to the rtc domain. the rtc requires a minimum of power to operate, which can be supplied by an external battery. whenever the device core power is greater than v bat , that power is used to operate the rtc. 3.13 wake-up timer at power-up and when awaken ed from power-down mode, op eration begins by using the 12 mhz irc oscillator as the clo ck source. this allows chip op eration to begin quickly. if the main oscillator or one or both plls are needed by the app lication, software will need to enable these features and wait for them to stabilize before they are used as a clock source. when the main oscillator is init ially activated, the wake-up timer allows software to ensure that the main oscillator is fully functional before the processor uses it as a clock source and starts to execute instructions. this is im portant at power-on, all types of reset, and whenever any of the aforemen tioned functions are turned off for any reason. since the oscillator and other functions are turned off during power- down mode, any wake-up of the processor from power-down mode makes use of the wake-up timer. the wake-up timer monitors the crystal oscillator as the means of checki ng whether it is safe to begin code execution. when power is applied to the chip, or some event caused the chip to exit powe r-down mode, some time is required for the os cillator to produce a signal of sufficient amplitude to drive the clock logic. the amount of time depends on many factors, including the rate of v dd(reg)(3v3) ramp (in the case of power on), the type of crystal and its electrical char acteristics (if a quartz crystal is used), as well as any other external circuitry (e.g. capacito rs), and the char acteristics of the osc illator itself under the existing ambient conditions. once a clock is detected, the wake-up timer counts a fixed number of clocks (4,096), then sets the flag (oscstat bit in the scs r egister) that indicates th at the main oscillator is ready for use. software can then switch to the main oscillator and start any required plls. refer to the main oscillator description in this chapter for details.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 73 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.14 external clock output pin for system test and developm ent purposes, any one of seve ral internal clocks may be brought out on the clkout function available on the p1[25] or p1[27] pins, as shown in figure 12 . clocks that may be ob served via clkout are the cpu cl ock (cclk), the main oscillator (osc_clk), the internal rc oscillator (irc_osc), the usb cl ock (usb_clk), the rtc clock (rtc_clk), the spifi clock (spifi_clk), and the watchdog oscillator (wdt_clk). fig 12. clkout selection clkoutcfg[3:0] clkout divider clkoutcfg[7:4] clock enable syncronizer clkoutcfg[8] clkout clkoutcfg[9] cclk osc_clk irc_osc usb_clk rtc_clk spifi_clk wdt_clk 000 001 010 011 100 101 110 120601
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 74 of 942 4.1 introduction the flash accelerator block allows maximization of the performance of the cpu when it is running code from flash memory, while also saving power. the flash accelerator also provides speed and power improvements for data accesses to the flash memory. 4.2 flash accelerator blocks the flash accelerator is divided into several functional blocks: ? ahb-lite bus interface, accessible by the i-code and d-code buses of the cpu, as well as by the general purpose dma controller ? an array of eight 128-bit buffers ? flash accelerator control logic, including address compare and flash control ? a flash memory interface figure 13 shows a simplified diagram of the flash accelerator blocks and data paths. in the following descriptions, the term ?fetch? applies to an explicit flash read request from the cpu. ?prefetch? is used to denote a fl ash read of instructions beyond the current processor fetch address. 4.2.1 flash memory bank flash programming operations are not controlle d by the flash accelerator, but are handled as a separate function. a boot rom contains flash programming algorithms that may be called as part of the application program, and a loader that may be run to allow programming of the flash memory. UM10562 chapter 4: lpc408x/407x flash accelerator rev. 1 ? 13 september 2012 user manual fig 13. simplified block diagram of the flash accelerator showing potential bus connections flash accelerator control flash interface ahb-lite bus interface instruction/ data buffers flash memory bus matrix dcode bus icode bus general purpose dma controller dma master port combined ahb flash accelerator 120601 cpu
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 75 of 942 nxp semiconductors UM10562 chapter 4: lpc408x/407x flash accelerator 4.2.2 flash programming issues since the flash memory does not allow accesses during programming and erase operations, it is necessary for the flash accele rator to force the cpu to wait if a memory access to a flash address is requested while the flash memory is busy with a programming operation. under some conditions, this delay could result in a watchdog time-out. the user will ne ed to be aware of this possibility an d take steps to insure that an unwanted watchdog reset does not cause a syst em failure while programming or erasing the flash memory. in order to preclude the possibility of stale data being read from the flash memory, the flash accelerator buffers are automatically invalidated at the beginning of any flash programming or erase operatio n. any subseque nt read from a flash address will cause a new fetch to be initiated after the flash operation has completed.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 76 of 942 nxp semiconductors UM10562 chapter 4: lpc408x/407x flash accelerator 4.3 register description the flash accelerator is contro lled by the register shown in table 48 . more detailed descriptions follow. [1] reset value reflects the data stored in defined bits only. it does not include reserved bits content. 4.4 flash accelerator configuration register configuration bits select the flash access time, as shown in ta b l e 4 9 . the lower bits of flashcfg control internal flash accelerator functions and should not be altered. following reset, flash accelerator functions are enabled and flash access timing is set to a default value of 4 clocks. changing the flashcfg register value causes the flash accelerator to invalidate all of the holding latches, resulting in new reads of flash information as required. this guarantees synchronization of the flash accelerator to cpu operation. table 48. summary of flash accelerator registers name description access reset value [1] address flashcfg flash accelerator configuration register. controls flash access timing. see table 49 . r/w 0x303a 0x400f c000 table 49. flash accelerator configuration register (flashcfg - address 0x400f c000) bit description bit symbol value description reset value 11:0 - - reserved, user software should not change these bits from the reset value. 0x03a 15:12 flashtim flash access time. the value of this field plus 1 give s the number of cpu clocks used for a flash access. warning: improper setting of this value may result in incorrect operation of the device. 0x3 0000 flash accesses use 1 cpu clock. use for up to 20 mhz cpu clock with power boost off (see section 3.12.6 ). 0001 flash accesses use 2 cpu clocks. use for up to 40 mhz cpu clock with power boost off (see section 3.12.6 ). 0010 flash accesses use 3 cpu clocks. use for up to 60 mhz cpu clock with power boost off (see section 3.12.6 ). 0011 flash accesses use 4 cpu clocks. use for up to 80 mhz cpu clock with power boost off (see section 3.12.6 ). use this setting for operation from 100 to 120 mhz operation with power boost on. 0100 flash accesses use 5 cpu clocks. use for up to 100 mhz cpu clock with power boost off (see section 3.12.6 ). 0101 flash accesses use 6 cpu clocks. ?safe? setting for any allowed conditions. other intended for potential future higher speed devices. 31:16 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 77 of 942 nxp semiconductors UM10562 chapter 4: lpc408x/407x flash accelerator 4.5 operation simply put, the flash accelera tor attempts to have the next instruction that will be needed in its latches in time to prevent cpu fetch stalls. the flash accelerator includes an array of eight 128-bit buffers to store both instructions and data in a configurable manner. each 128-bit buffer in the array can include four 32-bi t instructions, eight 16 -bit instructions or some combination of the two. during sequentia l code execution, a buffer typically contains the current instruction and the entire flash line that contains that instruction, or one flash line of data containing a previously requeste d address. buffers are marked according to how they are used (as instruction or data buffers), and when they have been accessed. this information is used to carry out the buffer replacement strategy. the cpu provides a separate bus for inst ruction access (i-code) and data access (d-code) in the code memory space. these buses, plus the general purpose dma controllers?s master port, are arbitrated by the ahb multilayer matrix. any access to the flash memory?s address space is presented to the flash accelerator. if a flash instruction fetch and a flash data a ccess from the cpu occu r at the same time, the multilayer matrix gives precedence to the data access. this is because a stalled data access always slows down exec ution, while a stalled instruction fetch often does not. when the flash data access is concluded, any flash fetch or prefetch that had been in progress is re-initiated. branches and other program flow changes ca use a break in the sequential flow of instruction fetches described above. buffer replacement strategy in the flash accelerator attempts to maximize the chances that potent ially reusable information is retained until it is needed again. if an attempt is made to write directly to t he flash memory without using the normal flash programming interface (via boot rom function calls), the flash accelerator generates an error condition. the cpu treats this error as a data abort. the gpdma handles error conditions as described in section 35.4.1.6.3 . when an instruction fetch is not satisfied by ex isting contents of the buffer array, nor has a prefetch been initiated for that flash line, the cpu will be stalled while a fetch is initiated for the related 128-bit flash line. if a prefetch has been initiated but not yet completed, the cpu is stalled for a shorter time since the re quired flash access is already in progress. typically, a flash prefetch is begun whenever an access is made to a just prefetched address, or to a buffer whose immediate successor is not already in another buffer. a prefetch in progress may be aborted by a da ta access, in order to minimize cpu stalls. a prefetched flash line is latched within the flash memory, but the flash accelerator does not capture the line in a buffer until the cpu presents an address that is contained within the prefetched flash line. if the core presents an instruction address that is not already buffered and is not contained in the prefetched flash line, the prefetched line will be discarded. some special cases include the possibility that the cpu will request a data access to an address already contained in an instruction buffer. in this case, the data w ill be read from the buffer as if it was a data buffer. the reverse case, if the cpu requests an instruction address that can be satisfied from an existing data buffer, causes the instruction to be
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 78 of 942 nxp semiconductors UM10562 chapter 4: lpc408x/407x flash accelerator supplied from the data buffer, and the buffer to be changed into an instruction buffer. this causes the buffer to be handled differently when the flash accelerator is determining which buffer is to be overwritten next.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 79 of 942 5.1 features ? nested vectored interrupt controller that is an integral part of the arm cortex-m4 ? tightly coupled interrupt controller provides low interrupt latency ? controls system exceptions and peripheral interrupts ? the nvic supports 40 vectored interrupts in these devices ? 32 programmable interrupt priority levels , with hardware priority level masking ? relocatable vector table ? non-maskable interrupt ? software interr upt generation 5.2 description the nested vectored interrupt controller (nvic) is an integral part of the cortex-m4. the tight coupling to the cpu allows for low interr upt latency and efficient processing of late arriving interrupts. the nvic handles inte rrupts in addition to system exceptions. exceptions include reset, nmi, hard fault, memmanage fault, bus fault, usage fault, svcall, debug monitor, pendsv, and systick. see the arm cortex-m4 user guide referred to in section 40.1 for details of nvic operation. 5.3 interrupt sources ta b l e 5 0 lists the interrupt sources for each pe ripheral function. each peripheral device may have one or more interrupt lines to the vectored interrupt controller. each line may represent more than one interrupt source, as noted. exception numbers relate to where entries ar e stored in the exception vector table. interrupt numbers are used in some other contexts, such as software interrupts. note that system exceptions are hard-wired into the cortex-m4 and are not shown in the table. some other information about the systi ck interrupt can be found in the system tick timer chapter, section 25.1 in addition, the nvic handles the non-maskab le interrupt (nmi). in order for nmi to operate from an external signal, the nmi func tion must be connected to the related device pin (p2[10] / eint0n / nmi). wh en connected, a logic 1 on the pin will cause the nmi to be processed. for details, refer to the cortex-m4 user guide that is an appendix to this user manual. UM10562 chapter 5: lpc408x/407x n ested vectored interrupt controller (nvic) rev. 1 ? 13 september 2012 user manual
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 80 of 942 nxp semiconductors UM10562 chapter 5: lpc408x/407x nested vectored interrupt controller (nvic) table 50. connection of interrupt sources to the vectored interrupt controller interrupt id exception number vector offset function flag(s) 0 16 0x40 wdt watchdog interrupt (wdint) 1 17 0x44 timer 0 match 0 - 1 (mr0, mr1) capture 0 - 1 (cr0, cr1) 2 18 0x48 timer 1 match 0 - 2 (mr0, mr1, mr2) capture 0 - 1 (cr0, cr1) 3 19 0x4c timer 2 match 0-3 capture 0-1 4 20 0x50 timer 3 match 0-3 capture 0-1 5 21 0x54 uart0 rx line status (rls) transmit holding register empty (thre) rx data available (rda) character time-out indicator (cti) end of auto-baud (abeo) auto-baud time-out (abto) 6 22 0x58 uart1 rx line status (rls) transmit holding register empty (thre) rx data available (rda) character time-out indicator (cti) modem control change end of auto-baud (abeo) auto-baud time-out (abto) 7 23 0x5c uart 2 rx line status (rls) transmit holding register empty (thre) rx data available (rda) character time-out indicator (cti) end of auto-baud (abeo) auto-baud time-out (abto) 8 24 0x60 uart 3 rx line status (rls) transmit holding register empty (thre) rx data available (rda) character time-out indicator (cti) end of auto-baud (abeo) auto-baud time-out (abto) 9 25 0x64 pwm1 match 0 - 6 of pwm1 capture 0-1 of pwm1 10 26 0x68 i 2 c0 si (state change) 11 27 0x6c i 2 c1 si (state change) 12 28 0x70 i 2 c2 si (state change) 13 29 0x74 (unused) -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 81 of 942 nxp semiconductors UM10562 chapter 5: lpc408x/407x nested vectored interrupt controller (nvic) 14 30 0x78 ssp0 tx fifo half empty of ssp0 rx fifo half full of ssp0 rx timeout of ssp0 rx overrun of ssp0 15 31 0x7c ssp 1 tx fifo half empty rx fifo half full rx timeout rx overrun 16 32 0x80 pll0 (main pll) pll0 lock (plock0) 17 33 0x84 rtc and event monitor/recorder counter increment (rtccif), alarm (rtcalf) ev0, ev1, ev2 18 34 0x88 external interrupt external interrupt 0 (eint0) 19 35 0x8c external interrupt external interrupt 1 (eint1) 20 36 0x90 external interrupt external interrupt 2 (eint2) 21 37 0x94 external interrupt external interrupt 3 (eint3) 22 38 0x98 adc a/d converter end of conversion 23 39 0x9c bod brown out detect 24 40 0xa0 usb usb_int_req_lp, usb_int_req_hp, usb_int_req_dma, usb_host_int, usb_atx_int, usb_otg_int, usb_i2c_int 25 41 0xa4 can can common, can 0 tx, can 0 rx, can 1 tx, can 1 rx 26 42 0xa8 dma controller interrupt status of all dma channels 27 43 0xac i 2 s irq, dmareq1, dmareq2 28 44 0xb0 ethernet wakeupint, softint, txdoneint, txfinishedint, txerrorint, txunderrunint, rxdoneint, rxfinishedint, rxerrorint, rxoverrunint. 29 45 0xb4 sd card interface rxdataavlbl, txdataavlbl, rxfifoempty, txfifoempty, rxfifofull, txfifofull, rxfifohalffull, txfifohalfempty, rxactive, txactive, cmdactive, datablockend, startbiterr, dataend, cmdsent, cmdrespend, rxoverrun, txunderrun, datatimeout, cmdtimeout, datacrcfail, cmdcrcfail 30 46 0xb8 motor control pwm iper[2:0], ipw[2:0], icap[2:0], fes 31 47 0xbc quadrature encoder inx_int, tim_int, velc_int, dir_int, err_int, enclk_int, pos0_int, pos1_int, pos2_int , rev_int, pos0rev_int, pos1rev_int, pos2rev_int 32 48 0xc0 pll1 (alt pll) pll1 lock (plock1) 33 49 0xc4 usb activity interrupt usb_need_clk 34 50 0xc8 can activity interrupt can1wake, can2wake 35 51 0xcc uart4 rx line status (rls) transmit holding register empty (thre) rx data available (rda) character time-out indicator (cti) end of auto-baud (abeo) auto-baud time-out (abto) table 50. connection of interrupt sources to the vectored interrupt controller interrupt id exception number vector offset function flag(s)
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 82 of 942 nxp semiconductors UM10562 chapter 5: lpc408x/407x nested vectored interrupt controller (nvic) 5.4 vector table remapping the cortex-m4 incorporates a mechanism that allows remapping the interrupt vector table to alternate locations in the memory map. th is is controlled via the vector table offset register (vtor) contained in the cortex-m4. the vector table may be located anywhere wi thin the bottom 1 gb of cortex-m4 address space. the vector table should be located on a 256 word (1024 byte) boundary to insure alignment. see the arm cortex-m4 user guide referred to in section 40.1 for details of the vector table offset feature. arm describes bit 29 of the vtor (tbloff) as selecting a memory region, either code or sram. for simplicity, this bit can be thought as simply part of the address offset since the split between the ?code? space and t he ?sram? space occurs at the location corresponding to bit 29 in a memory address. examples: to place the vector table at the beginning of the main sram, starting at address 0x1000 0000, place the value 0x1000 0000 in the vtor register. this indicates address 0x1000 0000 in the code space, since bit 29 of the vtor equals 0. to place the vector table at the beginning of the peripheral sram, starting at address 0x2000 0000, place the value 0x2000 0000 in the vtor register. this indicates address 0x2000 0000 in the sram space, since bit 29 of the vtor equals 1. 36 52 0xd0 ssp2 tx fifo half empty of ssp2 rx fifo half full of ssp2 rx timeout of ssp2 rx overrun of ssp2 37 53 0xd4 lcd controller ber, vcompi, lnbui, fufi, crsri 38 54 0xd8 gpio interrupts p0xrei, p2xrei, p0xfei, p2xfei 39 55 0xdc pwm0 match 0 - 6 of pwm0 capture 0-1 of pwm0 40 56 0xe0 eeprom ee_prog_done, ee_rw_done table 50. connection of interrupt sources to the vectored interrupt controller interrupt id exception number vector offset function flag(s)
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 83 of 942 nxp semiconductors UM10562 chapter 5: lpc408x/407x nested vectored interrupt controller (nvic) 5.5 register description the following table summarizes the registers in the nvic as implemented in lpc408x/407x devices. see the arm cortex-m4 user guide referred to in section 40.1 for functional details of the nvic. table 51. nvic register map name description access reset value address table iser0 to iser1 interrupt set-enable registers. these registers allow enabling interrupts and reading back the interrupt enables for specific peripheral functions. rw 0 iser0 - 0xe000 e100 iser1 - 0xe000 e104 52 53 icer0 to icer1 interrupt clear-enable registers. these registers allow disabling interrupts and reading back the interrupt enables for specific peripheral functions. rw 0 icer0 - 0xe000 e180 icer1 - 0xe000 e184 54 55 ispr0 to ispr1 interrupt set-pending registers. these registers allow changing the interrupt state to pending and reading back the interrupt pending state for specific peripheral functions. rw 0 ispr0 - 0xe000 e200 ispr1 - 0xe000 e204 56 57 icpr0 to icpr1 interrupt clear-pending registers. these registers allow changing the interrupt state to not pending and reading back the interrupt pending state for specific peripheral functions. rw 0 icpr0 - 0xe000 e280 icpr1 - 0xe000 e284 58 59 iabr0 to iabr1 interrupt active bit registers. these registers allow reading the current interrupt active state for specific peripheral functions. ro 0 iabr0 - 0xe000 e300 iabr1 - 0xe000 e304 60 61 ipr0 to ipr10 interrupt priority registers. these registers allow assigning a priority to each interrupt. each register contains the 5-bit priority fields for 4 interrupts. rw 0 ipr0 - 0xe000 e400 ipr1 - 0xe000 e404 ipr2 - 0xe000 e408 ipr3 - 0xe000 e40c ipr4 - 0xe000 e410 ipr5 - 0xe000 e414 ipr6 - 0xe000 e418 ipr7 - 0xe000 e41c ipr8 - 0xe000 e420 ipr9 - 0xe000 e424 ipr10 - 0xe000 e428 62 63 64 65 66 67 68 69 70 71 72 stir software trigger interrupt register. this register allows software to generate an interrupt. wo - stir - 0xe000 ef00 73
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 84 of 942 nxp semiconductors UM10562 chapter 5: lpc408x/407x nested vectored interrupt controller (nvic) 5.5.1 interrupt set-enab le register 0 register the iser0 register allows enabling the first 32 peripheral interrupts, or for reading the enabled state of those interrupts. the remaining interrupts are enabled via the iser1 register ( section 5.5.2 ). disabling interrupts is do ne through the icer0 and icer1 registers ( section 5.5.3 and section 5.4 ). table 52. interrupt set-ena ble register 0 register bit name function 0 ise_wdt watchdog timer interrupt enable. write: writing 0 has no effect, writing 1 enables the interrupt. read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled. 1 ise_timer0 timer 0 interrupt enable. see functional description for bit 0. 2 ise_timer1 timer 1 interrupt enable. see functional description for bit 0. 3 ise_timer2 timer 2 interrupt enable. see functional description for bit 0. 4 ise_timer3 timer 3 interrupt enable. see functional description for bit 0. 5 ise_uart0 uart0 interrupt enable. see functional description for bit 0. 6 ise_uart1 uart1 interrupt enable. see functional description for bit 0. 7 ise_uart2 uart2 interrupt enable. see functional description for bit 0. 8 ise_uart3 uart3 interrupt enable. see functional description for bit 0. 9 ise_pwm1 pwm1 interrupt enable. see functional description for bit 0. 10 ise_i2c0 i 2 c0 interrupt enable. see functional description for bit 0. 11 ise_i2c1 i 2 c1 interrupt enable. see functional description for bit 0. 12 ise_i2c2 i 2 c2 interrupt enable. see functional description for bit 0. 13 - reserved. read value is undefined, only zero should be written. 14 ise_ssp0 ssp0 interrupt enable. see functional description for bit 0. 15 ise_ssp1 ssp1 interrupt enable. see functional description for bit 0. 16 ise_pll0 pll0 (main pll) interrupt enable. see functional description for bit 0. 17 ise_rtc real time clock (rtc) and event monitor/recorder interrupt enable. see description of bit 0. 18 ise_eint0 external interrupt 0 interrupt enable. see functional description for bit 0. 19 ise_eint1 external interrupt 1 interrupt enable. see functional description for bit 0. 20 ise_eint2 external interrupt 2 interrupt enable. see functional description for bit 0. 21 ise_eint3 external interrupt 3 interrupt enable. see functional description for bit 0. 22 ise_adc adc interrupt enable. see functional description for bit 0. 23 ise_bod bod interrupt enable. see functional description for bit 0. 24 ise_usb usb interrupt enable. see functional description for bit 0. 25 ise_can can interrupt enable. see functional description for bit 0. 26 ise_dma gpdma interrupt enable. see functional description for bit 0. 27 ise_i2s i 2 s interrupt enable. see functional description for bit 0. 28 ise_enet ethernet interrupt enable. see functional description for bit 0. 29 ise_sd sd card interface interrupt enable. see functional description for bit 0. 30 ise_mcpwm motor control pwm interrupt enable. see functional description for bit 0. 31 ise_qei quadrature encoder interface interrupt enable. see functional description for bit 0.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 85 of 942 nxp semiconductors UM10562 chapter 5: lpc408x/407x nested vectored interrupt controller (nvic) 5.5.2 interrupt set-enab le register 1 register the iser1 register allows enabling the seco nd group of peripheral interrupts, or for reading the enabled state of those interrupts. disabling interrupts is done through the icer0 and icer1 registers ( section 5.5.3 and section 5.4 ). table 53. interrupt set-ena ble register 1 register bit name function 0 ise_pll1 pll1 (alt pll) interrupt enable. write: writing 0 has no effect, writing 1 enables the interrupt. read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled. 1 ise_usbact usb activity interrupt enable. see functional description for bit 0. 2 ise_canact can activity interrupt enable. see functional description for bit 0. 3 ise_uart4 uart4 interrupt enable. see functional description for bit 0. 4 ise_ssp2 ssp2 interrupt enable. see functional description for bit 0. 5 ise_lcd lcd interrupt enable. see functional description for bit 0. 6 ise_gpio gpio interrupt enable. see functional description for bit 0. 7 ise_pwm0 pwm0 interrupt enable. see functional description for bit 0. 8 ise_flash flash and eeprom interrupt enable. see functional description for bit 0. 31:9 - reserved. read value is undefined, only zero should be written.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 86 of 942 nxp semiconductors UM10562 chapter 5: lpc408x/407x nested vectored interrupt controller (nvic) 5.5.3 interrupt clear-enable register 0 the icer0 register allows disabling the first 32 peripheral interrupts, or for reading the enabled state of those interrupts. the remain ing interrupts are disabled via the icer1 register ( section 5.4 ). enabling interrupts is done th rough the iser0 and iser1 registers ( section 5.5.1 and section 5.5.2 ). table 54. interrupt clear-enable register 0 bit name function 0 ice_wdt watchdog timer interrupt disable. write: writing 0 has no effect, writing 1 disables the interrupt. read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled. 1 ice_timer0 timer 0 interrupt disable. see functional description for bit 0. 2 ice_timer1 timer 1 interrupt disable. see functional description for bit 0. 3 ice_timer2 timer 2 interrupt disable. see functional description for bit 0. 4 ice_timer3 timer 3 interrupt disable. see functional description for bit 0. 5 ice_uart0 uart0 interrupt disable. see functional description for bit 0. 6 ice_uart1 uart1 interrupt disable. see functional description for bit 0. 7 ice_uart2 uart2 interrupt disable. see functional description for bit 0. 8 ice_uart3 uart3 interrupt disable. see functional description for bit 0. 9 ice_pwm1 pwm1 interrupt disable. see functional description for bit 0. 10 ice_i2c0 i 2 c0 interrupt disable. see functional description for bit 0. 11 ice_i2c1 i 2 c1 interrupt disable. see functional description for bit 0. 12 ice_i2c2 i 2 c2 interrupt disable. see functional description for bit 0. 13 - reserved. read value is undefined, only zero should be written. 14 ice_ssp0 ssp0 interrupt disable. s ee functional descr iption for bit 0. 15 ice_ssp1 ssp1 interrupt disable. s ee functional descr iption for bit 0. 16 ice_pll0 pll0 (main pll) interrupt disable. see functional description for bit 0. 17 ice_rtc real time clock (rtc) and event monitor/recorder interrupt disable. see description of bit 0. 18 ice_eint0 external interrupt 0 interrupt disable. see functional description for bit 0. 19 ice_eint1 external interrupt 1 interrupt disable. see functional description for bit 0. 20 ice_eint2 external interrupt 2 interrupt disable. see functional description for bit 0. 21 ice_eint3 external interrupt 3 interrupt disable. see functional description for bit 0. 22 ice_adc adc interrupt disable. see functional description for bit 0. 23 ice_bod bod interrupt disable. see functional description for bit 0. 24 ice_usb usb interrupt disable. see functional description for bit 0. 25 ice_can can interrupt disable. see functional description for bit 0. 26 ice_dma gpdma interrupt disable. see functional description for bit 0. 27 ice_i2s i 2 s interrupt disable. see functional description for bit 0. 28 ice_enet ethernet interrupt disable. see functional description for bit 0. 29 ice_sd sd card interface interrupt disable. see functional description for bit 0. 30 ice_mcpwm motor control pwm interrupt disable. see functional description for bit 0. 31 ice_qei quadrature encoder interface interrupt disable. see functional description for bit 0.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 87 of 942 nxp semiconductors UM10562 chapter 5: lpc408x/407x nested vectored interrupt controller (nvic) 5.4 interrupt clear-enable register 1 register the icer1 register allows disabling the second group of peripheral interrupts, or for reading the enabled state of those interrupts. enabling interrupts is done through the iser0 and iser1 registers ( section 5.5.1 and section 5.5.2 ). table 55. interrupt clear-enable register 1 register bit name function 0 ice_pll1 pll1 (alt pll) interrupt disable. write: writing 0 has no effect, writing 1 disables the interrupt. read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled. 1 ice_usbact usb activity interrupt disabl e. see functional description for bit 0. 2 ice_canact can activity interrupt disable. see functional description for bit 0. 3 ice_uart4 uart4 interrupt disable. see functional description for bit 0. 4 ice_ssp2 ssp2 interrupt disable. s ee functional descr iption for bit 0. 5 ice_lcd lcd interrupt disable. see functional description for bit 0. 6 ice_gpio gpio interrupt disable. see functional description for bit 0. 7 ice_pwm0 pwm0 interrupt disable. see functional description for bit 0. 8 ice_eeprom eeprom interrupt disable. se e functional description for bit 0. 31:9 - reserved. read value is undefined, only zero should be written.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 88 of 942 nxp semiconductors UM10562 chapter 5: lpc408x/407x nested vectored interrupt controller (nvic) 5.5.5 interrupt set-pend ing register 0 register the ispr0 register allows setting the pending st ate of the first 32 peripheral interrupts, or for reading the pending state of those interrupts. the remaining interrupts can have their pending state set via the ispr1 register ( section 5.5.6 ). clearing the pending state of interrupts is done through the icpr0 and icpr1 registers ( section 5.5.7 and section 5.5.8 ). table 56. interrupt set-pen ding register 0 register bit name function 0 isp_wdt watchdog timer interrupt pending set. write: writing 0 has no effect, writing 1 changes the interrupt state to pending. read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending. 1 isp_timer0 timer 0 interrupt pending set. see functional description for bit 0. 2 isp_timer1 timer 1 interrupt pending set. see functional description for bit 0. 3 isp_timer2 timer 2 interrupt pending set. see functional description for bit 0. 4 isp_timer3 timer 3 interrupt pending set. see functional description for bit 0. 5 isp_uart0 uart0 interrupt pending set. see functional description for bit 0. 6 isp_uart1 uart1 interrupt pending set. see functional description for bit 0. 7 isp_uart2 uart2 interrupt pending set. see functional description for bit 0. 8 isp_uart3 uart3 interrupt pending set. see functional description for bit 0. 9 isp_pwm1 pwm1 interrupt pending set. see functional description for bit 0. 10 isp_i2c0 i 2 c0 interrupt pending set. see functional description for bit 0. 11 isp_i2c1 i 2 c1 interrupt pending set. see functional description for bit 0. 12 isp_i2c2 i 2 c2 interrupt pending set. see functional description for bit 0. 13 - reserved. read value is undefined, only zero should be written. 14 isp_ssp0 ssp0 interrupt pending set. s ee functional descr iption for bit 0. 15 isp_ssp1 ssp1 interrupt pending set. s ee functional descr iption for bit 0. 16 isp_pll0 pll0 (main pll) interrupt pending set. see functional description for bit 0. 17 isp_rtc real time clock (rtc) and event monitor/recorder interrupt pending set. see description of bit 0. 18 isp_eint0 external interrupt 0 interrupt pending set. see functional description for bit 0. 19 isp_eint1 external interrupt 1 interrupt pending set. see functional description for bit 0. 20 isp_eint2 external interrupt 2 interrupt pending set. see functional description for bit 0. 21 isp_eint3 external interrupt 3 interrupt pending set. see functional description for bit 0. 22 isp_adc adc interrupt pending set. see functional description for bit 0. 23 isp_bod bod interrupt pending set. see functional description for bit 0. 24 isp_usb usb interrupt pending set. see functional description for bit 0. 25 isp_can can interrupt pending set. see functional description for bit 0. 26 isp_dma gpdma interrupt pending set. see functional description for bit 0. 27 isp_i2s i 2 s interrupt pending set. see functional description for bit 0. 28 isp_enet ethernet interrupt pending set. see functional description for bit 0. 29 isp_sd sd card interface interrupt pending set. see functional description for bit 0. 30 isp_mcpwm motor control pwm interrupt pending set. see functional description for bit 0. 31 isp_qei quadrature encoder interface interrupt pending set. see functional description for bit 0.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 89 of 942 nxp semiconductors UM10562 chapter 5: lpc408x/407x nested vectored interrupt controller (nvic) 5.5.6 interrupt set-pend ing register 1 register the ispr1 register allows setting the pendin g state of the second group of peripheral interrupts, or for reading the pending state of those interrupts. clearing the pending state of interrupts is done through the icpr0 and icpr1 registers ( section 5.5.7 and section 5.5.8 ). table 57. interrupt set-pen ding register 1 register bit name function 0 isp_pll1 pll1 (alt pll) interrupt pending set. write: writing 0 has no effect, writing 1 changes the interrupt state to pending. read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending. 1 isp_usbact usb activity interrupt pending se t. see functional de scription for bit 0. 2 isp_canact can activity interrupt pending set. see functional description for bit 0. 3 isp_uart4 uart4 interrupt pending set. see functional description for bit 0. 4 isp_ssp2 ssp2 interrupt pending set. see functional description for bit 0. 5 isp_lcd lcd interrupt pending set. see functional description for bit 0. 6 isp_gpio gpio interrupt pending set. see functional description for bit 0. 7 isp_pwm0 pwm0 interrupt pending set. see functional description for bit 0. 8 isp_eeprom eeprom interrupt pending set. see functional description for bit 0. 31:9 - reserved. read value is undefined, only zero should be written.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 90 of 942 nxp semiconductors UM10562 chapter 5: lpc408x/407x nested vectored interrupt controller (nvic) 5.5.7 interrupt clear-pe nding register 0 register the icpr0 register allows clearing the pending state of the first 32 peripheral interrupts, or for reading the pending state of those interrupts. the remaining interrupts can have their pending state cleared via the icpr1 register ( section 5.5.8 ). setting the pending state of interrupts is done through the ispr0 and ispr1 registers ( section 5.5.5 and section 5.5.6 ). table 58. interrupt clear-pending register 0 register bit name function 0 icp_wdt watchdog timer interrupt pending clear. write: writing 0 has no effect, writing 1 changes the interrupt state to not pending. read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending. 1 icp_timer0 timer 0 interrupt pending clear. see functional description for bit 0. 2 icp_timer1 timer 1 interrupt pending clear. see functional description for bit 0. 3 icp_timer2 timer 2 interrupt pending clear. see functional description for bit 0. 4 icp_timer3 timer 3 interrupt pending clear. see functional description for bit 0. 5 icp_uart0 uart0 interrupt pending clear. see functional description for bit 0. 6 icp_uart1 uart1 interrupt pending clear. see functional description for bit 0. 7 icp_uart2 uart2 interrupt pending clear. see functional description for bit 0. 8 icp_uart3 uart3 interrupt pending clear. see functional description for bit 0. 9 icp_pwm1 pwm1 interrupt pending clear. see functional description for bit 0. 10 icp_i2c0 i 2 c0 interrupt pending clear. see functional description for bit 0. 11 icp_i2c1 i 2 c1 interrupt pending clear. see functional description for bit 0. 12 icp_i2c2 i 2 c2 interrupt pending clear. see functional description for bit 0. 13 - reserved. read value is undefined, only zero should be written. 14 icp_ssp0 ssp0 interrupt p ending clear. see functiona l description for bit 0. 15 icp_ssp1 ssp1 interrupt p ending clear. see functiona l description for bit 0. 16 icp_pll0 pll0 (main pll) interrupt pending clear. see functional description for bit 0. 17 icp_rtc real time clock (rtc) and event monitor/recorder interrupt pending clear. see description of bit 0. 18 icp_eint0 external interrupt 0 interrupt pending clear. see functional description for bit 0. 19 icp_eint1 external interrupt 1 interrupt pending clear. see functional description for bit 0. 20 icp_eint2 external interrupt 2 interrupt pending clear. see functional description for bit 0. 21 icp_eint3 external interrupt 3 interrupt pending clear. see functional description for bit 0. 22 icp_adc adc interrupt pending clear. see functional description for bit 0. 23 icp_bod bod interrupt pending clear. see functional description for bit 0. 24 icp_usb usb interrupt pending clear. see functional description for bit 0. 25 icp_can can interrupt pending clear. see functional description for bit 0. 26 icp_dma gpdma interrupt pending clear. see functional description for bit 0. 27 icp_i2s i 2 s interrupt pending clear. see functional description for bit 0. 28 icp_enet ethernet interrupt pending clear. see functional description for bit 0. 29 icp_sd sd card interface interrupt pending clear. see functional description for bit 0. 30 icp_mcpwm motor control pwm interrupt pending clear. see functional description for bit 0. 31 icp_qei quadrature encoder interface interrupt pending clear. see functional description for bit 0.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 91 of 942 nxp semiconductors UM10562 chapter 5: lpc408x/407x nested vectored interrupt controller (nvic) 5.5.8 interrupt clear-pe nding register 1 register the icpr1 register allows clearing the pendi ng state of the second group of peripheral interrupts, or for reading the pending state of those interrupts. setting the pending state of interrupts is done through the ispr0 and ispr1 registers ( section 5.5.5 and section 5.5.6 ). table 59. interrupt clear-pending register 1 register bit name function 0 icp_pll1 pll1 (alt pll) interrupt pending clear. write: writing 0 has no effect, writing 1 changes the interrupt state to not pending. read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending. 1 icp_usbact usb activity interrupt pending clear. see functional description for bit 0. 2 icp_canact can activity interrupt pending clear. see functional description for bit 0. 3 icp_uart4 uart4 interrupt pending clear. see functional description for bit 0. 4 icp_ssp2 ssp2 interrupt pending clear. see functional description for bit 0. 5 icp_lcd lcd interrupt pending clear. see functional description for bit 0. 6 icp_gpio gpio interrupt pending clear. see functional description for bit 0. 7 icp_pwm0 pwm0 interrupt pending clear. see functional description for bit 0. 8 icp_eeprom eeprom interrupt pending clear. see functional description for bit 0. 31:9 - reserved. read value is undefined, only zero should be written.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 92 of 942 nxp semiconductors UM10562 chapter 5: lpc408x/407x nested vectored interrupt controller (nvic) 5.5.9 interrupt acti ve bit register 0 the iabr0 register is a read-onl y register that allows reading the active state of the first 32 peripheral interrupts. bits in iabr are set while the corresponding interrupt service routines are in progress. additional interrupt s can have their active state read via the iabr1 register ( section 5.5.10 ). table 60. interrupt ac tive bit register 0 bit name function 0 iab_wdt watchdog timer interrupt active. read: 0 indicates that the interrupt is not active, 1 indicates that the interrupt is active. 1 iab_timer0 timer 0 interrupt active. see functional description for bit 0. 2 iab_timer1 timer 1 interrupt active. see functional description for bit 0. 3 iab_timer2 timer 2 interrupt active. see functional description for bit 0. 4 iab_timer3 timer 3 interrupt active. see functional description for bit 0. 5 iab_uart0 uart0 interrupt active. see functional description for bit 0. 6 iab_uart1 uart1 interrupt active. see functional description for bit 0. 7 iab_uart2 uart2 interrupt active. see functional description for bit 0. 8 iab_uart3 uart3 interrupt active. see functional description for bit 0. 9 iab_pwm1 pwm1 interrupt active. see functional description for bit 0. 10 iab_i2c0 i 2 c0 interrupt active. see functional description for bit 0. 11 iab_i2c1 i 2 c1 interrupt active. see functional description for bit 0. 12 iab_i2c2 i 2 c2 interrupt active. see functional description for bit 0. 13 - reserved. read value is undefined, only zero should be written. 14 iab_ssp0 ssp0 interrupt active. see functional description for bit 0. 15 iab_ssp1 ssp1 interrupt active. see functional description for bit 0. 16 iab_pll0 pll0 (main pll) interrupt active. see functional description for bit 0. 17 iab_rtc real time clock (rtc) and event monitor/recorder interrupt active. see description of bit 0. 18 iab_eint0 external interrupt 0 interrupt active. see functional description for bit 0. 19 iab_eint1 external interrupt 1 interrupt active. see functional description for bit 0. 20 iab_eint2 external interrupt 2 interrupt active. see functional description for bit 0. 21 iab_eint3 external interrupt 3 interrupt active. see functional description for bit 0. 22 iab_adc adc interrupt active. see functional description for bit 0. 23 iab_bod bod interrupt active. see functional description for bit 0. 24 iab_usb usb interrupt active. see functional description for bit 0. 25 iab_can can interrupt active. see functional description for bit 0. 26 iab_dma gpdma interrupt active. see functional description for bit 0. 27 iab_i2s i 2 s interrupt active. see functional description for bit 0. 28 iab_enet ethernet interrupt active. see functional description for bit 0. 29 iab_sd repetitive interrupt timer interrupt active. see functional description for bit 0. 30 iab_mcpwm motor control pwm interrupt active. see functional description for bit 0. 31 iab_qei quadrature encoder interface interrupt active. see functional description for bit 0.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 93 of 942 nxp semiconductors UM10562 chapter 5: lpc408x/407x nested vectored interrupt controller (nvic) 5.5.10 interrupt acti ve bit register 1 the iabr1 register is a read-o nly register that allows reading the active state of the second group of peripheral interrupts. bits in iabr are set while the corresponding interrupt service routin es are in progress. table 61. interrupt ac tive bit register 1 bit name function 0 iab_pll1 pll1 (alt pll) interrupt active. read: 0 indicates that the interrupt is not active, 1 indicates that the interrupt is active. 1 iab_usbact usb activity interrupt active . see functional description for bit 0. 2 iab_canact can activity interrupt active. see functional description for bit 0. 3 iab_uart4 uart4 interrupt active. see functional description for bit 0. 4 iab_ssp2 ssp2 interrupt active. see functional description for bit 0. 5 iab_lcd lcd interrupt active. see functional description for bit 0. 6 iab_gpio gpio interrupt active. see functional description for bit 0. 7 iab_pwm0 pwm0 interrupt active. see functional description for bit 0. 8 iab_eeprom eeprom interrupt active. see functional description for bit 0. 31:9 - reserved. the value read from a reserved bit is not defined.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 94 of 942 nxp semiconductors UM10562 chapter 5: lpc408x/407x nested vectored interrupt controller (nvic) 5.5.11 interrupt priority register 0 the ipr0 register controls the priority of the first 4 peripheral interrupts. each interrupt can have one of 32 priorities, where 0 is the highest priority. 5.5.12 interrupt priority register 1 the ipr1 register controls the priority of th e second group of 4 peripheral interrupts. each interrupt can have one of 32 priorities, where 0 is the highest priority. 5.5.13 interrupt priority register 2 the ipr2 register controls the priority of t he third group of 4 peripheral interrupts. each interrupt can have one of 32 priorities, where 0 is the highest priority. table 62. interrupt priority register 0 bit name function 2:0 unimplemented these bits ignore writes, and read as 0. 7:3 ip_wdt watchdog timer interrupt priority. 0 = highest priority. 31 (0x1f) = lowest priority. 10:8 unimplemented these bits ignore writes, and read as 0. 15:11 ip_timer0 timer 0 interrupt priority. see functional description for bits 7-3. 18:16 unimplemented these bits ignore writes, and read as 0. 23:19 ip_timer1 timer 1 interrupt priority. see functional description for bits 7-3. 26:24 unimplemented these bits ignore writes, and read as 0. 31:27 ip_timer2 timer 2 interrupt priority. see functional description for bits 7-3. table 63. interrupt priority register 1 bit name function 2:0 unimplemented these bits ignore writes, and read as 0. 7:3 ip_timer3 timer 3 interrupt priority. 0 = highest priority. 31 (0x1f) = lowest priority. 10:8 unimplemented these bits ignore writes, and read as 0. 15:11 ip_uart0 uart0 interrupt priority. see functional description for bits 7-3. 18:16 unimplemented these bits ignore writes, and read as 0. 23:19 ip_uart1 uart1 interrupt priority. see functional description for bits 7-3. 26:24 unimplemented these bits ignore writes, and read as 0. 31:27 ip_uart2 uart2 interrupt priority. see functional description for bits 7-3. table 64. interrupt priority register 2 bit name function 2:0 unimplemented these bits ignore writes, and read as 0. 7:3 ip_uart3 uart3 interrupt priority. 0 = highest priority. 31 (0x1f) = lowest priority. 10:8 unimplemented these bits ignore writes, and read as 0. 15:11 ip_pwm1 pwm1 interrupt priority. see functional description for bits 7-3. 18:16 unimplemented these bits ignore writes, and read as 0. 23:19 ip_i2c0 i 2 c0 interrupt priority. see functional description for bits 7-3. 26:24 unimplemented these bits ignore writes, and read as 0. 31:27 ip_i2c1 i 2 c1 interrupt priority. see functional description for bits 7-3.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 95 of 942 nxp semiconductors UM10562 chapter 5: lpc408x/407x nested vectored interrupt controller (nvic) 5.5.14 interrupt priority register 3 the ipr3 register controls the priority of t he fourth group of 4 peripheral interrupts. each interrupt can have one of 32 priorities, where 0 is the highest priority. 5.5.15 interrupt priority register 4 the ipr4 register controls the priority of t he fifth group of 4 peripheral interrupts. each interrupt can have one of 32 priorities, where 0 is the highest priority. 5.5.16 interrupt priority register 5 the ipr5 register controls the priority of t he sixth group of 4 peripheral interrupts. each interrupt can have one of 32 priorities, where 0 is the highest priority. table 65. interrupt priority register 3 bit name function 2:0 unimplemented these bits ignore writes, and read as 0. 7:3 ip_i2c2 i 2 c2 interrupt priority. 0 = highest priority. 31 (0x1f) = lowest priority. 10:8 unimplemented these bits ignore writes, and read as 0. 15:11 - reserved. read value is undefined, only zero should be written. 18:8 unimplemented these bits ignore writes, and read as 0. 23:19 ip_ssp0 ssp0 interrupt pr iority. see functional description for bits 7-3. 26:24 unimplemented these bits ignore writes, and read as 0. 31:27 ip_ssp1 ssp1 interrupt pr iority. see functional description for bits 7-3. table 66. interrupt priority register 4 bit name function 2:0 unimplemented these bits ignore writes, and read as 0. 7:3 ip_pll0 pll0 (main pll) interrupt priority. 0 = highest priority. 31 (0x1f) = lowest priority. 10:8 unimplemented these bits ignore writes, and read as 0. 15:11 ip_rtc real time clock (rtc) interrupt priority. see functional description for bits 7-3. 18:16 unimplemented these bits ignore writes, and read as 0. 23:19 ip_eint0 external interrupt 0 interrupt priority. see functional description for bits 7-3. 26:24 unimplemented these bits ignore writes, and read as 0. 31:27 ip_eint1 external interrupt 1 interrupt priority. see functional description for bits 7-3. table 67. interrupt priority register 5 bit name function 2:0 unimplemented these bits ignore writes, and read as 0. 7:3 ip_eint2 external interrupt 2 interrupt priority. 0 = highest priority. 31 (0x1f) = lowest priority. 10:8 unimplemented these bits ignore writes, and read as 0. 15:11 ip_eint3 external interrupt 3 interrupt priority. see functional description for bits 7-3. 18:16 unimplemented these bits ignore writes, and read as 0. 23:19 ip_adc adc interrupt priority. see functional description for bits 7-3. 26:24 unimplemented these bits ignore writes, and read as 0. 31:27 ip_bod bod interrupt priority. see functional description for bits 7-3.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 96 of 942 nxp semiconductors UM10562 chapter 5: lpc408x/407x nested vectored interrupt controller (nvic) 5.5.17 interrupt priority register 6 the ipr6 register controls the priority of the seventh group of 4 peripheral interrupts. each interrupt can have one of 32 priorities, where 0 is the highest priority. 5.5.18 interrupt priority register 7 the ipr7 register controls the priority of the eighth group of 4 peripheral interrupts. each interrupt can have one of 32 priorities, where 0 is the highest priority. 5.5.19 interrupt priority register 8 the ipr8 register controls the priority of the ninth and last group of 4 peripheral interrupts. each interrupt can have one of 32 prio rities, where 0 is the highest priority. table 68. interrupt priority register 6 bit name function 2:0 unimplemented these bits ignore writes, and read as 0. 7:3 ip_usb usb interrupt priority. 0 = highest priority. 31 (0x1f) = lowest priority. 10:8 unimplemented these bits ignore writes, and read as 0. 15:11 ip_can can interrupt priority. see functional description for bits 7-3. 18:16 unimplemented these bits ignore writes, and read as 0. 23:19 ip_dma gpdma interrupt priority. see functional description for bits 7-3. 26:24 unimplemented these bits ignore writes, and read as 0. 31:27 ip_i2s i 2 s interrupt priority. see functional description for bits 7-3. table 69. interrupt priority register 7 bit name function 2:0 unimplemented these bits ignore writes, and read as 0. 7:3 ip_enet ethernet interrupt priority. 0 = highest priority. 31 (0x1f) = lowest priority. 10:8 unimplemented these bits ignore writes, and read as 0. 15:11 ip_sd sd card interface interrupt priority. see functional description for bits 7-3. 18:16 unimplemented these bits ignore writes, and read as 0. 23:19 ip_mcpwm motor control pwm interrupt priority. see functional description for bits 7-3. 26:24 unimplemented these bits ignore writes, and read as 0. 31:27 ip_qei quadrature encoder interface interrupt pr iority. see functional description for bits 7-3. table 70. interrupt priority register 8 bit name function 2:0 unimplemented these bits ignore writes, and read as 0. 7:3 ip_pll1 pll1 (alt pll) interrupt priority. 0 = highest priority. 31 (0x1f) = lowest priority. 10:8 unimplemented these bits ignore writes, and read as 0. 15:11 ip_usbact usb activity inte rrupt priority. see functio nal description for bits 7-3. 18:16 unimplemented these bits ignore writes, and read as 0. 23:19 ip_canact can activity interrupt priority. see functional description for bits 7-3. 26:24 unimplemented these bits ignore writes, and read as 0. 31:27 ip_uart4 uart4 interrupt priority. see functional description for bits 7-3.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 97 of 942 nxp semiconductors UM10562 chapter 5: lpc408x/407x nested vectored interrupt controller (nvic) 5.5.20 interrupt priority register 9 the ipr9 register controls the priority of t he tenth group of 4 peripheral interrupts. each interrupt can have one of 32 priorities, where 0 is the highest priority. 5.5.21 interrupt priority register 10 the ipr10 register controls the priority of th e eleventh group of 4 peripheral interrupts. each interrupt can have one of 32 prio rities, where 0 is the highest priority. 5.5.22 software trigge r interrupt register the stir register provides an alternate way for software to generate an interrupt, in addition to using the ispr registers. th is mechanism can only be used to generate peripheral interrupts, not system exceptions. by default, only privileged software can writ e to the stir register. unprivileged software can be given this ab ility if privileged software sets the usersetmpend bit in the ccr register (see the arm cortex-m4 user guide referred to in section 40.1 for details). table 71. interrupt priority register 9 bit name function 2:0 unimplemented these bits ignore writes, and read as 0. 7:3 ip_ssp2 ssp2 interrupt priority . 0 = highest priority. 31 (0x1f) = lowest priority. 10:8 unimplemented these bits ignore writes, and read as 0. 15:11 ip_lcd lcd controller interrupt priority. see functional description for bits 7-3. 18:16 unimplemented these bits ignore writes, and read as 0. 23:19 ip_gpio priority of gpio interrupts. see functional description for bits 7-3. 26:24 unimplemented these bits ignore writes, and read as 0. 31:27 ip_pwm0 pwm0 interrupt priority. see functional description for bits 7-3. table 72. interrupt priority register 10 bit name function 2:0 unimplemented these bits ignore writes, and read as 0. 7:3 ip_eeprom eeprom programming in terrupt. 0 = highest priority. 31 (0x1f) = lowest priority. 31:8 unimplemented these bits ignore writes, and read as 0. table 73. software trigger interrupt register bit name function 8:0 intid writing a value to this field generates an interrupt for the specified interrupt id (see ta b l e 5 0 ). 31:9 - reserved. read value is undefined, only zero should be written.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 98 of 942 6.1 pin configuration for information about the individual lpc408x/407 x devices, refer to specific data sheets. ta b l e 7 4 lists pins in order by pin name, and in cludes description of each potential pin function. see the iocon registers ( section 7.4.1 ) to configure pins for the desired function. i/o pins are 5v tolerant and have input hyster esis unless otherwise indicated in the table below. crystal pins, power pins, and reference voltage pins are not 5v tolerant. in addition, when pins are selected to be a to d converter inputs, they are no longer 5v tolerant and must be limited to the voltage at the adc positive reference pin (vrefp). UM10562 chapter 6: lpc408x/407x pin configuration rev. 1 ? 13 september 2012 user manual table 74. pin description symbol type iocon select [1] description p0[0] to p0[31] i/o port 0: port 0 provides up to 32 i/o pins, depending on the package. each pin has individual direction control, pin mode configuration, and function selection. p0[0]/ can_rd1/ u3_txd/ i2c1_sda/ u0_txd i/o 0 p0[0] ? general purpose digital input/output pin. i1 can_rd1 ? can1 receiver input. o2 u3_txd ? transmitter output for uart 3. i/o 3 i2c1_sda ? i 2 c1 data input/output (this pin does not use a specialized i 2 c pad, see section 22.1 for details). i/o 4 u0_txd ? transmitter output for uart 0. p0[1]/ can1_td/ u3_rxd/ i2c1_scl/ u0_rxd i/o 0 p0[1] ? general purpose digital input/output pin. o1 can1_td ? can1 transmitter output. i2 u3_rxd ? receiver input for uart 3. i/o 3 i2c1_scl ? i 2 c1 clock input/output (this pin does not use a specialized i 2 c pad, see section 22.1 for details). i4 u0_rxd ? receiver input for uart 0. p0[2]/ u0_txd/ u3_txd i/o 0 p0[2] ? general purpose digital input/output pin. o1 u0_txd ? transmitter output for uart 0. used for isp communication, see section 38.1 . o2 u3_txd ? transmitter output for uart 3. p0[3]/ u0_rxd/ u3_rxd i/o 0 p0[3] ? general purpose digital input/output pin. i1 u0_rxd ? receiver input for uart 0. used for isp communication, see section 38.1 . i2 u3_rxd ? receiver input for uart 3.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 99 of 942 nxp semiconductors UM10562 chapter 6: lpc408x/407x pin configuration p0[4]/ i2s_rx_sck/ can_rd2/ t2_cap0/ cmp_rosc/ lcd_vd[0] i/o 0 p0[4] ? general purpose digital input/output pin. i/o 1 i2s_rx_sck ? i 2 s receive clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus specification . i2 can_rd2 ? can2 receiver input. i3 t2_cap0 ? capture input for timer 2, channel 0. o5 cmp_rosc ? comparator relaxation oscillator output. o7 lcd_vd[0] ? lcd data. p0[5]/ i2s_rx_ws/ can_td2/ t2_cap1/ cmp_reset/ lcd_vd[1] i/o 0 p0[5] ? general purpose digital input/output pin. i/o 1 i2s_rx_ws ? i 2 s receive word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus specification . o2 can_td2 ? can2 transmitter output. i3 t2_cap1 ? capture input for timer 2, channel 1. o5 cmp_reset ? comparator reset input. o7 lcd_vd[1] ? lcd data. p0[6]/ i2s_rx_sda/ ssp1_ssel/ t2_mat0/ u1_rts/ cmp_rosc/ lcd_vd[8] i/o 0 p0[6] ? general purpose digital input/output pin. i/o 1 i2s_rx_sda ? i 2 s receive data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus specification . i/o 2 ssp1_ssel1 ? slave select for ssp1. o3 t2_mat0 ? match output for timer 2, channel 0. o4 u1_rts ? request to send output for uart 1. can also be configured to be an rs-485/eia-485 output enable signal for uart 1. o5 cmp_rosc ? comparator relaxation oscillator output. o7 lcd_vd[8] ? lcd data. p0[7]/ i2s_tx_sck/ ssp1_sck/ t2_mat1/ rtc_ev0/ cmp_vref/ lcd_vd[9] i/o 0 p0[7] ? general purpose digital input/output pin. i/o 1 i2s_tx_sck ? i 2 s transmit clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus specification . i/o 2 ssp1_sck ? serial clock for ssp1. o3 t2_mat1 ? match output for timer 2, channel 1. i4 rtc_ev0 ? event input 0 to event monitor/recorder. o5 cmp_vref ? comparator voltage reference input. o7 lcd_vd[9] ? lcd data. p0[8]/ i2s_tx_ws/ ssp1_miso/ t2_mat2/ rtc_ev1/ cmp1_in[4]/ lcd_vd[16] i/o 0 p0[8] ? general purpose digital input/output pin. i/o 1 i2s_tx_ws ? i 2 s transmit word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus specification . i/o 2 ssp1_miso ? master in slave out for ssp1. o3 t2_mat2 ? match output for timer 2, channel 2. i4 rtc_ev1 ? event input 1 to event monitor/recorder. o5 cmp1_in[4] ? comparator input. o7 lcd_vd[16] ? lcd data. table 74. pin description ?continued symbol type iocon select [1] description
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 100 of 942 nxp semiconductors UM10562 chapter 6: lpc408x/407x pin configuration p0[9]/ i2s_tx_sda/ ssp1_mosi/ t2_mat3/ rtc_ev2/ cmp1_in[3]/ lcd_vd[17] i/o 0 p0[9] ? general purpose digital input/output pin. i/o 1 i2s_tx_sda ? i 2 s transmit data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus specification . i/o 2 ssp1_mosi ? master out slave in for ssp1. o3 t2_mat3 ? match output for timer 2, channel 3. i4 rtc_ev2 ? event input 2 to event monitor/recorder. o5 cmp1_in[3] ? comparator input. o7 lcd_vd[17] ? lcd data. p0[10]/ u2_txd/ i2c2_sda/ t3_mat0/ lcd_vd[5] i/o 0 p0[10] ? general purpose digital input/output pin. o1 u2_txd ? transmitter output for uart 2. i/o 2 i2c2_sda ? i 2 c2 data input/output (this pin does not use a specialized i 2 c pad, see section 22.1 for details). o3 t3_mat0 ? match output for timer 3, channel 0. o7 lcd_vd[5] ? lcd data. p0[11]/ u2_rxd/ i2c2_scl/ t3_mat1/ lcd_vd[10] i/o 0 p0[11] ? general purpose digital input/output pin. i1 u2_rxd ? receiver input for uart 2. i/o 2 i2c2_scl ? i 2 c2 clock input/output (this pin does not use a specialized i 2 c pad, see section 22.1 for details). o3 t3_mat1 ? match output for timer 3, channel 1. o7 lcd_vd[10] ? lcd data. p0[12]/ usb_ppwr2 / ssp1_miso/ ad0[6] i/o 0 p0[12] ? general purpose digital input/output pin. o1 usb_ppwr2 ? port power enable signal for usb port 2. i/o 2 ssp1_miso ? master in slave out for ssp1. i3 ad0[6] ? a/d converter 0, input 6. when configured as an adc input, the digital function of the pin must be disabled (see section 7.4.1 ). p0[13]/ usb_up_led2/ ssp1_mosi/ ad0[7] i/o 0 p0[13] ? general purpose digital input/output pin. o1 usb_up_led2 ? usb port 2 goodlink led indicator. it is low when device is configured (non-control endpoints enabled) or when host is enabled and has detected a device on the bus. it is high when the device is not configured, when host is enabled and has not detected a device on the bus, or during global suspend. it toggles between low and high when host is enabled and detects activity on the bus. i/o 2 ssp1_mosi ? master out slave in for ssp1. i3 ad0[7] ? a/d converter 0, input 7. when configured as an adc input, the digital function of the pin must be disabled (see section 7.4.1 ). p0[14]/ usb_hsten2 / ssp1_ssel/ usb_connect2 i/o 0 p0[14] ? general purpose digital input/output pin. o1 usb_hsten2 ? host enabled status for usb port 2. i/o 2 ssp1_ssel ? slave select for ssp1. o3 usb_connect2 ? softconnect control for usb port 2. the usb_connect pin indicates when the pull-up resistor must be enabled when running in usb device mode. if it is used in usb device mode, this function can be implemented by using another gpio pin. if the chip is only used in usb host mode, there is no need to use this pin. table 74. pin description ?continued symbol type iocon select [1] description
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 101 of 942 nxp semiconductors UM10562 chapter 6: lpc408x/407x pin configuration p0[15]/ u1_txd/ ssp0_sck/ spifi_io[2] i/o 0 p0[15] ? general purpose digital input/output pin. o1 u1_txd ? transmitter output for uart 1. i/o 2 ssp0_sck ? serial clock for ssp0. i/o 5 spifi_io[2] ? data bit 2 for spifi. p0[16]/ u1_rxd/ ssp0_ ssel/ spifi_io[3] i/o 0 p0 [16] ? general purpose digital input/output pin. i1 u1_rxd ? receiver input for uart 1. i/o 2 ssp0_ssel ? slave select for ssp0. i/o 5 spifi_io[3] ? data bit 3 for spifi. p0[17]/ u1_cts/ ssp0_miso/ spifi_io[1] i/o 0 p0[17] ? general purpose digital input/output pin. i1 u1_cts ? clear to send input for uart 1. i/o 2 ssp0_miso ? master in slave out for ssp0. i/o 5 spifi_io[1] ? data bit 1 for spifi. p0[18]/ u1_dcd/ ssp0_mosi/ spifi_io[0] i/o 0 p0[18] ? general purpose digital input/output pin. i1 u1_dcd ? data carrier detect input for uart 1. i/o 2 ssp0_mosi ? master out slave in for ssp0. i/o 5 spifi_io[0] ? data bit 0 for spifi. p0[19]/ u1_dsr/ sd_clk/ i2c1_sda/ lcd_vd[13] i/o 0 p0[19] ? general purpose digital input/output pin. i1 u1_dsr ? data set ready input for uart 1. o2 sd_clk ? clock output line for sd card interface. i/o 3 i2c1_sda ? i 2 c1 data input/output (this pin does not use a specialized i 2 c pad, see section 22.1 for details). o7 lcd_vd[13] ? lcd data. p0[20]/ u1_dtr/ sd_cmd/ i2c1_scl/ lcd_vd[14] i/o 0 p0[20] ? general purpose digital input/output pin. o1 u1_dtr ? data terminal ready output for uart 1. can also be configured to be an rs-485/eia-485 output enable signal for uart 1. i/o 2 sd_cmd ? command line for sd card interface. i/o 3 i2c1_scl ? i 2 c1 clock input/output (this pin does not use a specialized i 2 c pad, see section 22.1 for details). o7 lcd_vd[14] ? lcd data. p0[21]/ u1_ri/ sd_pwr/ u4_oe/ can_rd1 i/o 0 p0[21] ? general purpose digital input/output pin. i1 u1_ri ? ring indicator input for uart 1. o2 sd_pwr ? power supply enable for external sd card power supply. o3 u4_oe ? rs-485/eia-485 output enable signal for uart 4. i4 can_rd1 ? can1 receiver input. i/o 5 u4_sclk ? uart 4 clock input or output in synchronous mode. table 74. pin description ?continued symbol type iocon select [1] description
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 102 of 942 nxp semiconductors UM10562 chapter 6: lpc408x/407x pin configuration p0[22]/ u1_rts/ sd_dat[0]/ u4_txd/ can_td1/ spifi_clk i/o 0 p0[22] ? general purpose digital input/output pin. o1 u1_rts ? request to send output for uart 1. can also be configured to be an rs-485/eia-485 output enable signal for uart 1. i/o 2 sd_dat[0] ? data line 0 for sd card interface. o3 u4_txd ? transmitter output for uart 4 (input/output in smart card mode). o4 can_td1 ? can1 transmitter output. o5 spifi_clk ? clock output for spifi. p0[23]/ ad0[0]/ i2s_rx_sck/ t3_cap0 i/o 0 p0[23] ? general purpose digital input/output pin. i1 ad0[0] ? a/d converter 0, input 0. when configured as an adc input, the digital function of the pin must be disabled (see section 7.4.1 ). i/o 2 i2s_rx_sck ? receive clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus specification . i3 t3_cap0 ? capture input for timer 3, channel 0. p0[24]/ ad0[1]/ i2s_rx_ws/ t3_cap1 i/o 0 p0[24] ? general purpose digital input/output pin. i1 ad0[1] ? a/d converter 0, input 1. when configured as an adc input, the digital function of the pin must be disabled (see section 7.4.1 ). i/o 2 i2s_rx_ws ? receive word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus specification . i3 t3_cap1 ? capture input for timer 3, channel 1. p0[25]/ ad0[2]/ i2s_rx_sda/ u3_txd i/o 0 p0[25] ? general purpose digital input/output pin. i1 ad0[2] ? a/d converter 0, input 2. when configured as an adc input, the digital function of the pin must be disabled (see section 7.4.1 ). i/o 2 i2s_rx_sda ? receive data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus specification . o3 u3_txd ? transmitter output for uart 3. p0[26]/ ad0[3]/ dac_out/ u3_rxd i/o 0 p0[26] ? general purpose digital input/output pin. i1 ad0[3] ? a/d converter 0, input 3. when configured as an adc input, the digital function of the pin must be disabled (see section 7.4.1 ). o2 dac_out ? d/a converter output. when configured as the dac output, the digital function of the pin must be disabled (see section 7.4.1 ). i3 u3_rxd ? receiver input for uart 3. p0[27]/ i2c0_sda/ usb_sda i/o 0 p0[27] ? general purpose digital input/output pin. i/o 1 i2c0_sda ? i 2 c0 data input/output. (this pin uses a specialized i 2 c pad, see section 22.1 for details). i/o 2 usb_sda ? i 2 c serial data for communication with an external usb transceiver. p0[28]/ i2c0_scl/ usb_scl i/o 0 p0[28] ? general purpose digital input/output pin. i/o 1 i2c0_scl0 ? i 2 c0 clock input/output (this pin uses a specialized i 2 c pad, see section 22.1 for details). i/o 2 usb_scl ? i 2 c serial clock for communication with an external usb transceiver. p0[29]/ usb_d+1/ eint0 i/o 0 p0[29] ? general purpose digital input/output pin. when used as gpio, p0[29] shares a direction control with p0[30]. i/o 1 usb_d+1 ? usb port 1 bidirectional d+ line. i2 eint0 ? external interrupt 0 input. table 74. pin description ?continued symbol type iocon select [1] description
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 103 of 942 nxp semiconductors UM10562 chapter 6: lpc408x/407x pin configuration p0[30]/ usb_d ? 1/ eint1 i/o 0 p0[30] ? general purpose digital input/output pin. when used as gpio, p0[30] shares a direction control with p0[29]. i/o 1 usb_d ? 1 ? usb port 1 bidirectional d ? line. i2 eint1 ? external interrupt 1 input. p0[31]/ usb_d+2 i/o 0 p0[31] ? general purpose digital input/output pin. i/o 1 usb_d+2 ? usb port 2 bidirectional d+ line. p1[0] to p1[31] i/o port 1: port 1 provides up to 32 i/o pins, depending on the package. each pin has individual direction control, pin mode configuration, and function selection. p1[0]/ enet_txd0/ t3_cap1/ ssp2_sck i/o 0 p1[0] ? general purpose digital input/output pin. o1 enet_txd0 ? ethernet transmit data 0 (rmii/mii interface). i3 t3_cap1 ? capture input for timer 3, channel 1. i/o 4 ssp2_sck ? serial clock for ssp2. p1[1]/ enet_txd1/ t3_mat3/ ssp2_mosi i/o 0 p1[1] ? general purpose digital input/output pin. o1 enet_txd1 ? ethernet transmit data 1 (rmii/mii interface). o3 t3_mat3 ? match output for timer 3, channel 3. i/o 4 ssp2_mosi ? master out slave in for ssp2. p1[2]/ enet_txd2/ sd_clk/ pwm0[1] i/o 0 p1[2] ? general purpose digital input/output pin. o1 enet_txd2 ? ethernet transmit data 2 (mii interface). o2 sd_clk ? clock output line for sd card interface. o3 pwm0[1] ? pulse width modulator 0, output 1. p1[3]/ enet_txd3/ sd_cmd/ pwm0[2] i/o 0 p1[3] ? general purpose digital input/output pin. o1 enet_txd3 ? ethernet transmit data 3 (mii interface). i/o 2 sd_cmd ? command line for sd card interface. o3 pwm0[2] ? pulse width modulator 0, output 2. p1[4]/ enet_tx_en / t3_mat2/ ssp2_miso i/o 0 p1[4] ? general purpose digital input/output pin. o1 enet_tx_en ? ethernet transmit data enable (rmii/mii interface). o3 t3_mat2 ? match output for timer 3, channel 2. i/o 4 ssp2_miso ? master in slave out for ssp2. p1[5]/ enet_tx_er/ sd_pwr/ pwm0[3]/ cmp1_in[2] i/o 0 p1[5] ? general purpose digital input/output pin. o1 enet_tx_er ? ethernet transmit error (mii interface). o2 sd_pwr ? power supply enable for external sd card power supply. o3 pwm0[3] ? pulse width modulator 0, output 3. o5 cmp1_in[2] ? comparator input. p1[6]/ enet_tx_clk/ sd_dat[0]/ pwm0[4]/ cmp0_in[4] i/o 0 p1[6] ? general purpose digital input/output pin. i1 enet_tx_clk ? ethernet transmit clock (mii interface). i/o 2 sd_dat[0] ? data line 0 for sd card interface. o3 pwm0[4] ? pulse width modulator 0, output 4. o5 cmp0_in[4] ? comparator input. table 74. pin description ?continued symbol type iocon select [1] description
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 104 of 942 nxp semiconductors UM10562 chapter 6: lpc408x/407x pin configuration p1[7]/ enet_col/ sd_dat[1]/ pwm0[5] / cmp1_in[1] i/o 0 p1[7] ? general purpose digital input/output pin. i1 enet_col ? ethernet collision detect (mii interface). i/o 2 sd_dat[1] ? data line 1 for sd card interface. o3 pwm0[5] ? pulse width modulator 0, output 5. o5 cmp1_in[1] ? comparator input. p1[8]/ enet_crs (enet_crs_dv)/ t3_mat1/ ssp2_ssel i/o 0 p1[8] ? general purpose digital input/output pin. i1 enet_crs (enet_crs_dv) ? ethernet carrier sense (mii interface) or ethernet carrier sense/data valid (rmii interface). o3 t3_mat1 ? match output for timer 3, channel 1. i/o 4 ssp2_ssel ? slave select for ssp2. p1[9]/ enet_rxd0/ t3_mat0 i/o 0 p1[9] ? general purpose digital input/output pin. i1 enet_rxd0 ? ethernet receive data 0 (rmii/mii interface). o3 t3_mat0 ? match output for timer 3, channel 0. p1[10]/ enet_rxd1/ t3_cap0 i/o 0 p1[10] ? general purpose digital input/output pin. i1 enet_rxd1 ? ethernet receive data 1 (rmii/mii interface). i3 t3_cap0 ? capture input for timer 3, channel 0. p1[11]/ enet_rxd2/ sd_dat[2]/ pwm0[6] i/o 0 p1[11] ? general purpose digital input/output pin. i1 enet_rxd2 ? ethernet receive data 2 (mii interface). i/o 2 sd_dat[2] ? data line 2 for sd card interface. o3 pwm0[6] ? pulse width modulator 0, output 6. p1[12]/ enet_rxd3/ sd_dat[3]/ pwm0_cap0/ cmp1_out i/o 0 p1[12] ? general purpose digital input/output pin. i1 enet_rxd3 ? ethernet receive data (mii interface). i/o 2 sd_dat[3] ? data line 3 for sd card interface. i3 pwm0_cap0 ? capture input for pwm0, channel 0. o5 cmp1_out ? comparator 1 output. p1[13]/ enet_rx_dv i/o 0 p1[13] ? general purpose digital input/output pin. i1 enet_rx_dv ? ethernet receive data valid (mii interface). p1[14]/ enet_rx_er/ t2_cap0/ cmp0_in[1] i/o 0 p1[14] ? general purpose digital input/output pin. i1 enet_rx_er ? ethernet receive erro r (rmii/mii interface). i3 t2_cap0 ? capture input for timer 2, channel 0. o5 cmp0_in[1] ? comparator input. p1[15]/ enet_rx_clk (enet_ref_clk)/ i2c2_sda i/o 0 p1[15] ? general purpose digital input/output pin. i1 enet_rx_clk (enet_ref_clk) ? ethernet receive clock (mii interface) or ethernet reference clock (rmii interface). i/o 3 i2c2_sda ? i 2 c2 data input/output (this pin does not use a specialized i 2 c pad, see section 22.1 for details). p1[16]/ enet_mdc/ i2s_tx_mclk/ cmp0_in[2] i/o 0 p1[16] ? general purpose digital input/output pin. o1 enet_mdc ? ethernet miim clock. o2 i2s_tx_mclk ? i 2 s transmitter master clock output. o5 cmp0_in[2] ? comparator input. table 74. pin description ?continued symbol type iocon select [1] description
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 105 of 942 nxp semiconductors UM10562 chapter 6: lpc408x/407x pin configuration p1[17]/ enet_mdio/ i2s_rx_mclk/ cmp0_in[3] i/o 0 p1[17] ? general purpose digital input/output pin. i/o 1 enet_mdio ? ethernet miim data input and output. o2 i2s_rx_mclk ? i 2 s receiver master clock output. o5 cmp0_in[3] ? comparator input. p1[18]/ usb_up_led1/ pwm1[1]/ t1_cap0/ ssp1_miso i/o 0 p1[18] ? general purpose digital input/output pin. o1 usb_up_led1 ? usb port 1 goodlink led indicator. it is low when device is configured (non-control endpoints enabled) or when host is enabled and has detected a device on the bus. it is high when the device is not configured, when host is enabled and has not detected a device on the bus, or during global suspend. it toggles between low and high when host is enabled and detects activity on the bus. o2 pwm1[1] ? pulse width modulator 1, channel 1 output. i3 t1_cap0 ? capture input for timer 1, channel 0. i/o 5 ssp1_miso ? master in slave out for ssp1. p1[19]/ usb_tx_e1 / usb_ppwr1 / t1_cap1/ mc_0a/ ssp1_sck/ u2_oe i/o 0 p1[19] ? general purpose digital input/output pin. o1 usb_tx_e1 ? transmit enable signal for usb port 1 (otg transceiver). o2 usb_ppwr1 ? port power enable signal for usb port 1. i3 t1_cap1 ? capture input for timer 1, channel 1. o4 mc_0a ? motor control pwm channel 0, output a. i/o 5 ssp1_sck ? serial clock for ssp1. o6 u2_oe ? rs-485/eia-485 output enable signal for uart 2. p1[20]/ usb_tx_dp1/ pwm1[2]/ qei_pha/ mc_fb0/ ssp0_sck/ lcd_vd[6]/ lcd_vd[10] i/o 0 p1[20] ? general purpose digital input/output pin. o1 usb_tx_dp1 ? d+ transmit data for usb port 1 (otg transceiver). o2 pwm1[2] ? pulse width modulator 1, channel 2 output. i3 qei_pha ? quadrature encoder interface pha input. i4 mc_fb0 ? motor control pwm channel 0 feedback input. i/o 5 ssp0_sck0 ? serial clock for ssp0. o6 lcd_vd[6] ? lcd data. o7 lcd_vd[10] ? lcd data. p1[21]/ usb_tx_dm1/ pwm1[3]/ ssp0_ssel/ mc_abort / lcd_vd[7]/ lcd_vd[11] i/o 0 p1[21] ? general purpose digital input/output pin. o1 usb_tx_dm1 ? d ? transmit data for usb port 1 (otg transceiver). o2 pwm1[3] ? pulse width modulator 1, channel 3 output. i/o 3 ssp0_ssel ? slave select for ssp0. i4 mc_abort ? motor control pwm, active low fast abort. o6 lcd_vd[7] ? lcd data. o7 lcd_vd[11] ? lcd data. table 74. pin description ?continued symbol type iocon select [1] description
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 106 of 942 nxp semiconductors UM10562 chapter 6: lpc408x/407x pin configuration p1[22]/ usb_rcv1/ usb_pwrd1/ t1_mat0/ mc_0b/ ssp1_mosi/ lcd_vd[8]/ lcd_vd[12] i/o 0 p1[22] ? general purpose digital input/output pin. i1 usb_rcv1 ? differential receive data for usb port 1 (otg transceiver). i2 usb_pwrd1 ? power status for usb port 1 (host power switch). when using the chip in usb host mode, the usb_pwrd input must be enabled. the usb host controller will only detect a device connect event when the port power bit is set in the ohci and the usb_pwrd bit is asserted for the corresponding port. o3 t1_mat0 ? match output for timer 1, channel 0. o4 mc_0b ? motor control pwm channel 0, output b. i/o 5 ssp1_mosi ? master out slave in for ssp1. o6 lcd_vd[8] ? lcd data. o7 lcd_vd[12] ? lcd data. p1[23]/ usb_rx_dp1/ pwm1[4]/ qei_phb/ mc_fb1/ ssp0_miso/ lcd_vd[9]/ lcd_vd[13] i/o 0 p1[23] ? general purpose digital input/output pin. i1 usb_rx_dp1 ? d+ receive data for usb port 1 (otg transceiver). o2 pwm1[4] ? pulse width modulator 1, channel 4 output. i3 qei_phb ? quadrature encoder interface phb input. i4 mc_fb1 ? motor control pwm channel 1 feedback input. i/o 5 ssp0_miso ? master in slave out for ssp0. o6 lcd_vd[9] ? lcd data. o7 lcd_vd[13] ? lcd data. p1[24]/ usb_rx_dm1/ pwm1[5]/ qei_idx/ mc_fb2/ ssp0_mosi/ lcd_vd[10]/ lcd_vd[14] i/o 0 p1[24] ? general purpose digital input/output pin. i1 usb_rx_dm1 ? d ? receive data for usb po rt 1 (otg transceiver). o2 pwm1[5] ? pulse width modulator 1, channel 5 output. i3 qei_idx ? quadrature en coder interface index input. i4 mc_fb2 ? motor control pwm channel 2 feedback input. i/o 5 ssp0_mosi ? master out slave in for ssp0. o6 lcd_vd[10]/lcd_vd[14] ? lcd data. o7 lcd_vd[10]/lcd_vd[14] ? lcd data. p1[25]/ usb_ls1 / usb_hsten1 / t1_mat1/ mc_1a/ clkout/ lcd_vd[11]/ lcd_vd[15] i/o 0 p1[25] ? general purpose digital input/output pin. o1 usb_ls1 ? low speed status for usb port 1 (otg transceiver). o2 usb_hsten1 ? host enabled status for usb port 1. o3 t1_mat1 ? match output for timer 1, channel 1. o4 mc_1a ? motor control pwm channel 1, output a. o5 clkout ? selectable clock output. o6 lcd_vd[11] ? lcd data. o7 lcd_vd[15] ? lcd data. table 74. pin description ?continued symbol type iocon select [1] description
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 107 of 942 nxp semiconductors UM10562 chapter 6: lpc408x/407x pin configuration p1[26]/ usb_sspnd1 / pwm1[6]/ t0_cap0/ mc_1b/ ssp1_ssel/ lcd_vd[12]/ lcd_vd[20] i/o 0 p1[26] ? general purpose digital input/output pin. o1 usb_sspnd1 ? usb port 1 bus suspend status (otg transceiver). o2 pwm1[6] ? pulse width modulator 1, channel 6 output. i3 t0_cap0 ? capture input for timer 0, channel 0. o4 mc_1b ? motor control pwm channel 1, output b. i/o 5 ssp1_ssel ? slave select for ssp1. o6 lcd_vd[12] ? lcd data. o7 lcd_vd[20] ? lcd data. p1[27]/ usb_int1 / usb_ovrcr1 / t0_cap1/ clkout/ lcd_vd[13]/ lcd_vd[21] i/o 0 p1[27] ? general purpose digital input/output pin. i1 usb_int1 ? usb port 1 otg transceiver interrupt (otg transceiver). i2 usb_ovrcr1 ? usb port 1 over-current status. the usb_ovrcr pin is used to set status in the ohci controller to inform the host firmware that there is an overcurrent condition. it is possible to use instead a gpio pin and observe that pin for overcurrent situations. i3 t0_cap1 ? capture input for timer 0, channel 1. o4 clkout ? selectable clock output. o6 lcd_vd[13] ? lcd data. o7 lcd_vd[21] ? lcd data. p1[28]/ usb_scl1/ pwm1_cap0/ t0_mat0/ mc_2a/ ssp0_ssel/ lcd_vd[14]/ lcd_vd[22] i/o 0 p1[28] ? general purpose digital input/output pin. i/o 1 usb_scl1 ? usb port 1 i 2 c serial clock (o tg transceiver). i2 pwm1_cap0 ? capture input for pwm1, channel 0. o3 t0_mat0 ? match output for timer 0, channel 0. o4 mc_2a ? motor control pwm channel 2, output a. i/o 5 ssp0_ssel ? slave select for ssp0. o6 lcd_vd[14] ? lcd data. o7 lcd_vd[22] ? lcd data. p1[29]/ usb_sda1/ pwm1_cap1/ t0_mat1/ mc_2b/ u4_txd/ lcd_vd[15]/ lcd_vd[23] i/o 0 p1[29] ? general purpose digital input/output pin. i/o 1 usb_sda1 ? usb port 1 i 2 c serial data (otg transceiver). i2 pwm1_cap1 ? capture input for pwm1, channel 1. o3 t0_mat1 ? match output for timer 0, channel 1. o4 mc_2b ? motor control pwm channel 2, output b. o5 u4_txd ? transmitter output for uart 4 (input/output in smart card mode). o6 lcd_vd[15] ? lcd data. o7 lcd_vd[23] ? lcd data. table 74. pin description ?continued symbol type iocon select [1] description
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 108 of 942 nxp semiconductors UM10562 chapter 6: lpc408x/407x pin configuration p1[30]/ usb_pwrd2/ usb_vbus/ ad0[4]/ i2c0_sda/ u3_oe i/o 0 p1[30] ? general purpose digital input/output pin. i1 usb_pwrd2 ? power status for usb port 2. when using the chip in usb host mode, the usb_pwrd input must be enabled. the usb host controller will only detect a device connect event when the port power bit is set in the ohci and the usb_pwrd bit is asserted for the corresponding port. i2 usb_vbus ? monitors the presence of usb bus power. note: this signal must be high for usb reset to occur. i3 ad0[4] ? a/d converter 0, input 4. when configured as an adc input, the digital function of the pin must be disabled (see section 7.4.1 ). i/o 4 i2c0_sda ? i 2 c0 data input/output (this pin does not use a specialized i 2 c pad, see section 22.1 for details). o5 u3_oe ? rs-485/eia-485 output enable signal for uart 3. p1[31]/ usb_ovrcr2 / ssp1_sck/ ad0[5]/ i2c0_scl i/o 0 p1[31] ? general purpose digital input/output pin. i1 usb_ovrcr2 ? over-current status for usb port 2. the usb_ovrcr pin is used to set status in the ohci controller to inform the host firmware that there is an overcurrent condition. it is possible to use instead a gpio pin and observe that pin for overcurrent situations. i/o 2 ssp1_sck ? serial clock for ssp1. i3 ad0[5] ? a/d converter 0, input 5. when configured as an adc input, the digital function of the pin must be disabled (see section 7.4.1 ). i/o 4 i2c0_scl ? i 2 c0 clock input/output (this pin does not use a specialized i 2 c pad, see section 22.1 for details). p2[0] to p2[31] i/o port 2: port 2 provides up to 32 i/o pins, depending on the package. each pin has individual direction control, pin mode configuration, and function selection. p2[0]/ pwm1[1]/ u1_txd/ lcd_pwr i/o 0 p2[0] ? general purpose digital input/output pin. o1 pwm1[1] ? pulse width modulator 1, channel 1 output. o2 u1_txd ? transmitter output for uart 1. o7 lcd_pwr ? lcd panel power enable. p2[1]/ pwm1[2]/ u1_rxd/ lcd_le i/o 0 p2[1] ? general purpose digital input/output pin. o1 pwm1[2] ? pulse width modulator 1, channel 2 output. i2 u1_rxd ? receiver input for uart 1. o7 lcd_le ? line end signal. p2[2]/ pwm1[3]/ u1_cts/ t2_mat3/ tracedata[3]/ lcd_dclk i/o 0 p2[2] ? general purpose digital input/output pin. o1 pwm1[3] ? pulse width modulator 1, channel 3 output. i2 u1_cts ? clear to send input for uart 1. o3 t2_mat3 ? match output for timer 2, channel 3. o5 tracedata[3] ? trace data, bit 3. o7 lcd_dclk ? lcd panel clock. table 74. pin description ?continued symbol type iocon select [1] description
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 109 of 942 nxp semiconductors UM10562 chapter 6: lpc408x/407x pin configuration p2[3]/ pwm1[4]/ u1_dcd/ t2_mat2/ tracedata[2]/ lcd_fp i/o 0 p2[3] ? general purpose digital input/output pin. o1 pwm1[4] ? pulse width modulator 1, channel 4 output. i2 u1_dcd ? data carrier detect input for uart 1. o3 t2_mat2 ? match output for timer 2, channel 2. o5 tracedata[2] ? trace data, bit 2. o7 lcd_fp ? frame pulse (stn). vertical synchronization pulse (tft). p2[4]/ pwm1[5]/ u1_dsr/ t2_mat1/ tracedata[1]/ lcd_enab_m i/o 0 p2[4] ? general purpose digital input/output pin. o1 pwm1[5] ? pulse width modulator 1, channel 5 output. i2 u1_dsr ? data set ready input for uart 1. o3 t2_mat1 ? match output for timer 2, channel 1. o5 tracedata[1] ? trace data, bit 1. o7 lcd_enab_m ? stn ac bias drive or tft data enable output. p2[5]/ pwm1[6]/ u1_dtr/ t2_mat0/ tracedata[0]/ lcd_lp i/o 0 p2[5] ? general purpose digital input/output pin. o1 pwm1[6] ? pulse width modulator 1, channel 6 output. o2 u1_dtr ? data terminal ready output for uart 1. can also be configured to be an rs-485/eia-485 output enable signal for uart 1. o3 t2_mat0 ? match output for timer 2, channel 0. o5 tracedata[0] ? trace data, bit 0. o7 lcd_lp ? line synchronization pulse (stn). horizontal synchronization pulse (tft). p2[6]/ pwm1_cap0/ u1_ri/ t2_cap0/ u2_oe/ traceclk/ lcd_vd[0]/ lcd_vd[4] i/o 0 p2[6] ? general purpose digital input/output pin. i1 pwm1_cap0 ? capture input for pwm1, channel 0. i2 u1_ri ? ring indicator input for uart 1. i3 t2_cap0 ? capture input for timer 2, channel 0. o4 u2_oe ? rs-485/eia-485 output enable signal for uart 2. o5 traceclk ? trace clock. o6 lcd_vd[0] ? lcd data. o7 lcd_vd[4] ? lcd data. p2[7]/ can_rd2/ u1_rts/ spifi_cs / lcd_vd[1]/ lcd_vd[5] i/o 0 p2[7] ? general purpose digital input/output pin. i1 can_rd2 ? can2 receiver input. o2 u1_rts ? request to send output for uart 1. can also be configured to be an rs-485/eia-485 output enable signal for uart 1. o5 spifi_cs ? chip select output for spifi. o6 lcd_vd[1] ? lcd data. o7 lcd_vd[5] ? lcd data. table 74. pin description ?continued symbol type iocon select [1] description
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 110 of 942 nxp semiconductors UM10562 chapter 6: lpc408x/407x pin configuration p2[8]/ can_td2/ u2_txd/ u1_cts/ enet_mdc/ lcd_vd[2]/ lcd_vd[6] i/o 0 p2[8] ? general purpose digital input/output pin. o1 can_td2 ? can2 transmitter output. o2 u2_txd ? transmitter output for uart 2. i3 u1_cts ? clear to send input for uart 1. o4 enet_mdc ? ethernet miim clock. o6 lcd_vd[2] ? lcd data. o7 lcd_vd[6] ? lcd data. p2[9]/ usb_connect1/ u2_rxd/ u4_rxd/ enet_mdio/ lcd_vd[3]/ lcd_vd[7] i/o 0 p2[9] ? general purpose digital input/output pin. o1 usb_connect1 ? usb1 softconnect contro l. the usb_connect pin indicates when the pull-up resistor must be enabled when running in usb device mode. if it is used in usb device mode, this function can be implemented by using another gpio pin. if the chip is only used in usb host mode, there is no need to use this pin. i2 u2_rxd ? receiver input for uart 2. i3 u4_rxd ? receiver input for uart 4. i/o 4 enet_mdio ? ethernet miim data input and output. i6 lcd_vd[3] ? lcd data. i7 lcd_vd[7] ? lcd data. p2[10]/ eint0/ nmi i/o 0 p2[10] ? general purpose digital input/output pin. this pin includes a 5 ns input glitch filter. note: a low on this pin while reset is low forces the on-chip boot loader to take over control of the part after a reset and go into isp mode. see section 38.3 . i1 eint0 ? external interrupt 0 input. i2 nmi ? non-maskable interrupt input. p2[11]/ eint1/ sd_dat[1]/ i2s_tx_sck/ lcd_clkin i/o 0 p2[11] ? general purpose digital input/output pin. this pin includes a 5 ns input glitch filter. i1 eint1 ? external interrupt 1 input. i/o 2 sd_dat[1] ? data line 1 for sd card interface. i/o 3 i2s_tx_sck ? transmit clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus specification . o7 lcd_clkin ? lcd clock. p2[12]/ eint2/ sd_dat[2]/ i2s_tx_ws/ lcd_vd[4]/ lcd_vd[3]/ lcd_vd[8]/ lcd_vd[18] i/o 0 p2[12] ? general purpose digital input/output pin. this pin includes a 5 ns input glitch filter. i1 eint2 ? external interrupt 2 input. i/o 2 sd_dat[2] ? data line 2 for sd card interface. i/o 3 i2s_tx_ws ? transmit word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus specification . o4 lcd_vd[4] ? lcd data. o5 lcd_vd[3] ? lcd data. o6 lcd_vd[8] ? lcd data. o7 lcd_vd[18] ? lcd data. table 74. pin description ?continued symbol type iocon select [1] description
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 111 of 942 nxp semiconductors UM10562 chapter 6: lpc408x/407x pin configuration p2[13]/ eint3/ sd_dat[3]/ i2s_tx_sda/ lcd_vd[5]/ lcd_vd[9]/ lcd_vd[19] i/o 0 p2[13] ? general purpose digital input/output pin. this pin includes a 5 ns input glitch filter. i1 eint3 ? external interrupt 3 input. i/o 2 sd_dat[3] ? data line 3 for sd card interface. i/o 3 i2s_tx_sda ? transmit data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus specification . o5 lcd_vd[5] ? lcd data. o6 lcd_vd[9] ? lcd data. o7 lcd_vd[19] ? lcd data. p2[14]/ emc_cs2 / i2c1_sda/ t2_cap0 i/o 0 p2[14] ? general purpose digital input/output pin. o1 emc_cs2 ? low active chip select 2 signal. i/o 2 i2c1_sda ? i 2 c1 data input/output (this pin does not use a specialized i 2 c pad, see section 22.1 for details). i3 t2_cap0 ? capture input for timer 2, channel 0. p2[15]/ emc_cs3 / i2c1_scl/ t2_cap1 i/o 0 p2[15] ? general purpose digital input/output pin. o1 emc_cs3 ? low active chip select 3 signal. i/o 2 i2c1_scl ? i 2 c1 clock input/output (this pin does not use a specialized i 2 c pad, see section 22.1 for details). i3 t2_cap1 ? capture input for timer 2, channel 1. p2[16]/ emc_cas i/o 0 p2[16] ? general purpose digital input/output pin. o1 emc_cas ? low active sdram column address strobe. p2[17]/ emc_ras i/o 0 p2[17] ? general purpose digital input/output pin. o1 emc_ras ? low active sdram row address strobe. p2[18]/ emc_clk0 i/o 0 p2[18] ? general purpose digital input/output pin. o1 emc_clk0 ? sdram clock 0. p2[19]/ emc_clk1 i/o 0 p2[19] ? general purpose digital input/output pin. o1 emc_clk1 ? sdram clock 1. p2[20]/ emc_dycs0 i/o 0 p2[20] ? general purpose digital input/output pin. o1 emc_dycs0 ? sdram chip select 0. p2[21]/ emc_dycs1 i/o 0 p2[21] ? general purpose digital input/output pin. o1 emc_dycs1 ? sdram chip select 1. p2[22]/ emc_dycs2 / ssp0_sck/ t3_cap0 i/o 0 p2[22] ? general purpose digital input/output pin. o1 emc_dycs2 ? sdram chip select 2. i/o 2 ssp0_sck ? serial clock for ssp0. i3 t3_cap0 ? capture input for timer 3, channel 0. p2[23]/ emc_dycs3 / ssp0_ssel/ t3_cap1 i/o 0 p2[23] ? general purpose digital input/output pin. o1 emc_dycs3 ? sdram chip select 3. i/o 2 ssp0_ssel ? slave select for ssp0. i3 t3_cap1 ? capture input for timer 3, channel 1. p2[24]/ emc_cke0 i/o 0 p2[24] ? general purpose digital input/output pin. o1 emc_cke0 ? sdram clock enable 0. table 74. pin description ?continued symbol type iocon select [1] description
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 112 of 942 nxp semiconductors UM10562 chapter 6: lpc408x/407x pin configuration p2[25]/ emc_cke1 i/o 0 p2[25] ? general purpose digital input/output pin. o1 emc_cke1 ? sdram clock enable 1. p2[26]/ emc_cke2/ ssp0_miso/ t3_mat0 i/o 0 p2[26] ? general purpose digital input/output pin. o1 emc_cke2 ? sdram clock enable 2. i/o 2 ssp0_miso ? master in slave out for ssp0. o3 t3_mat0 ? match output for timer 3, channel 0. p2[27]/ emc_cke3/ ssp0_mosi/ t3_mat1 i/o 0 p2[27] ? general purpose digital input/output pin. o1 emc_cke3 ? sdram clock enable 3. i/o 2 ssp0_mosi ? master out slave in for ssp0. o3 t3_mat1 ? match output for timer 3, channel 1. p2[28]/ emc_dqm0 i/o 0 p2[28] ? general purpose digital input/output pin. o1 emc_dqm0 ? data mask 0 used with sdram and static devices. p2[29]/ emc_dqm1 i/o 0 p2[29] ? general purpose digital input/output pin. o1 emc_dqm1 ? data mask 1 used with sdram and static devices. p2[30]/ emc_dqm2/ i2c2_sda/ t3_mat2 i/o 0 p2[30] ? general purpose digital input/output pin. o1 emc_dqm2 ? data mask 2 used with sdram and static devices. i/o 2 i2c2_sda ? i 2 c2 data input/output (this pin does not use a specialized i 2 c pad, see section 22.1 for details). o3 t3_mat2 ? match output for timer 3, channel 2. p2[31]/ emc_dqm3/ i2c2_scl/ t3_mat3 i/o 0 p2[31] ? general purpose digital input/output pin. o1 emc_dqm3 ? data mask 3 used with sdram and static devices. i/o 2 i2c2_scl ? i 2 c2 clock input/output (this pin does not use a specialized i 2 c pad, see section 22.1 for details). o3 t3_mat3 ? match output for timer 3, channel 3. p3[0] to p3[31] i/o port 3: port 3 provides up to 32 i/o pins, depending on the package. each pin has individual direction control, pin mode configuration, and function selection. p3[0]/ emc_d[0] i/o 0 p3[0] ? general purpose digital input/output pin. i/o 1 emc_d[0] ? external memory data line 0. p3[1]/ emc_d[1] i/o 0 p3[1] ? general purpose digital input/output pin. i/o 1 emc_d[1] ? external memory data line 1. p3[2]/ emc_d[2] i/o 0 p3[2] ? general purpose digital input/output pin. i/o 1 emc_d[2] ? external memory data line 2. p3[3]/ emc_d[3] i/o 0 p3[3] ? general purpose digital input/output pin. i/o 1 emc_d[3] ? external memory data line 3. p3[4]/ emc_d[4] i/o 0 p3[4] ? general purpose digital input/output pin. i/o 1 emc_d[4] ? external memory data line 4. p3[5]/ emc_d[5] i/o 0 p3[5] ? general purpose digital input/output pin. i/o 1 emc_d[5] ? external memory data line 5. p3[6]/ emc_d[6] i/o 0 p3[6] ? general purpose digital input/output pin. i/o 1 emc_d[6] ? external memory data line 6. table 74. pin description ?continued symbol type iocon select [1] description
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 113 of 942 nxp semiconductors UM10562 chapter 6: lpc408x/407x pin configuration p3[7]/ emc_d[7] i/o 0 p3[7] ? general purpose digital input/output pin. i/o 1 emc_d[7] ? external memory data line 7. p3[8]/ emc_d[8] i/o 0 p3[8] ? general purpose digital input/output pin. i/o 1 emc_d[8] ? external memory data line 8. p3[9]/ emc_d[9] i/o 0 p3[9] ? general purpose digital input/output pin. i/o 1 emc_d[9] ? external memory data line 9. p3[10]/ emc_d[10] i/o 0 p3[10] ? general purpose digital input/output pin. i/o 1 emc_d[10] ? external memory data line 10. p3[11]/ emc_d[11] i/o 0 p3[11] ? general purpose digital input/output pin. i/o 1 emc_d[11] ? external memory data line 11. p3[12]/ emc_d[12] i/o 0 p3[12] ? general purpose digital input/output pin. i/o 1 emc_d[12] ? external memory data line 12. p3[13]/ emc_d[13] i/o 0 p3[13] ? general purpose digital input/output pin. i/o 1 emc_d[13] ? external memory data line 13. p3[14]/ emc_d[14] i/o 0 p3[14] ? general purpose digital input/output pin. i/o 1 emc_d[14] ? external memory data line 14. on por, this pin serves as the boot0 pin (see p3[15] description below. p3[15]/ emc_d[15] i/o 0 p3[15] ? general purpose digital input/output pin. i/o 1 emc_d[15] ? external memory data line 15. boot[1:0] = 00 selects 8-bit external memory on emc_cs1 . boot[1:0] = 01 is reserved. do not use. boot[1:0] = 10 selects 32-bit external memory on emc_cs1 . boot[1:0] = 11 selects 16-bit external memory on emc_cs1 . p3[16]/ emc_d[16]/ pwm0[1]/ u1_txd i/o 0 p3[16] ? general purpose digital input/output pin. i/o 1 emc_d[16] ? external memory data line 16. o2 pwm0[1] ? pulse width modulator 0, output 1. o3 u1_txd ? transmitter output for uart 1. p3[17]/ emc_d[17]/ pwm0[2]/ u1_rxd i/o 0 p3[17] ? general purpose digital input/output pin. i/o 1 emc_d[17] ? external memory data line 17. o2 pwm0[2] ? pulse width modulator 0, output 2. i3 u1_rxd ? receiver input for uart 1. p3[18]/ emc_d[18]/ pwm0[3]/ u1_cts i/o 0 p3[18] ? general purpose digital input/output pin. i/o 1 emc_d[18] ? external memory data line 18. o2 pwm0[3] ? pulse width modulator 0, output 3. i3 u1_cts ? clear to send input for uart 1. p3[19]/ emc_d[19]/ pwm0[4]/ u1_dcd i/o 0 p3[19] ? general purpose digital input/output pin. i/o 1 emc_d[19] ? external memory data line 19. o2 pwm0[4] ? pulse width modulator 0, output 4. i3 u1_dcd ? data carrier detect input for uart 1. table 74. pin description ?continued symbol type iocon select [1] description
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 114 of 942 nxp semiconductors UM10562 chapter 6: lpc408x/407x pin configuration p3[20]/ emc_d[20]/ pwm0[5]/ u1_dsr i/o 0 p3[20] ? general purpose digital input/output pin. i/o 1 emc_d[20] ? external memory data line 20. o2 pwm0[5] ? pulse width modulator 0, output 5. i3 u1_dsr ? data set ready input for uart 1. p3[21]/ emc_d[21]/ pwm0[6]/ u1_dtr i/o 0 p3[21] ? general purpose digital input/output pin. i/o 1 emc_d[21] ? external memory data line 21. o2 pwm0[6] ? pulse width modulator 0, output 6. o3 u1_dtr ? data terminal ready output for uart 1. can also be configured to be an rs-485/eia-485 output enable signal for uart 1. p3[22]/ emc_d[22]/ pwm0_cap0/ u1_ri i/o 0 p3[22] ? general purpose digital input/output pin. i/o 1 emc_d[22] ? external memory data line 22. i2 pwm0_cap0 ? capture input for pwm0, channel 0. i3 u1_ri ? ring indicator input for uart 1. p3[23]/ emc_d[23]/ pwm1_cap0/ t0_cap0 i/o 0 p3[23] ? general purpose digital input/output pin. i/o 1 emc_d[23] ? external memory data line 23. i2 pwm1_cap0 ? capture input for pwm1, channel 0. i3 t0_cap0 ? capture input for timer 0, channel 0. p3[24]/ emc_d[24]/ pwm1[1]/ t0_cap1 i/o 0 p3[24] ? general purpose digital input/output pin. i/o 1 emc_d[24] ? external memory data line 24. o2 pwm1[1] ? pulse width modulator 1, output 1. i3 t0_cap1 ? capture input for timer 0, channel 1. p3[25]/ emc_d[25]/ pwm1[2]/ t0_mat0 i/o 0 p3[25] ? general purpose digital input/output pin. i/o 1 emc_d[25] ? external memory data line 25. o2 pwm1[2] ? pulse width modulator 1, output 2. o3 t0_mat0 ? match output for timer 0, channel 0. p3[26]/ emc_d[26]/ pwm1[3]/ t0_mat1/ stclk i/o 0 p3[26] ? general purpose digital input/output pin. i/o 1 emc_d[26] ? external memory data line 26. o2 pwm1[3] ? pulse width modulator 1, output 3. o3 t0_mat1 ? match output for timer 0, channel 1. i4 stclk ? system tick timer clock input. p3[27]/ emc_d[27]/ pwm1[4]/ t1_cap0 i/o 0 p3[27] ? general purpose digital input/output pin. i/o 1 emc_d[27] ? external memory data line 27. o2 pwm1[4] ? pulse width modulator 1, output 4. i3 t1_cap0 ? capture input for timer 1, channel 0. p3[28]/ emc_d[28]/ pwm1[5]/ t1_cap1 i/o 0 p3[28] ? general purpose digital input/output pin. i/o 1 emc_d[28] ? external memory data line 28. o2 pwm1[5] ? pulse width modulator 1, output 5. i3 t1_cap1 ? capture input for timer 1, channel 1. table 74. pin description ?continued symbol type iocon select [1] description
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 115 of 942 nxp semiconductors UM10562 chapter 6: lpc408x/407x pin configuration p3[29]/ emc_d[29]/ pwm1[6]/ t1_mat0 i/o 0 p3[29] ? general purpose digital input/output pin. i/o 1 emc_d[29] ? external memory data line 29. o2 pwm1[6] ? pulse width modulator 1, output 6. o3 t1_mat0 ? match output for timer 1, channel 0. p3[30]/ emc_d[30]/ u1_rts/ t1_mat1 i/o 0 p3[30] ? general purpose digital input/output pin. i/o 1 emc_d[30] ? external memory data line 30. o2 u1_rts ? request to send output for uart 1. can also be configured to be an rs-485/eia-485 output enable signal for uart 1. o3 t1_mat1 ? match output for timer 1, channel 1. p3[31]/ emc_d[31]/ t1_mat2 i/o 0 p3[31] ? general purpose digital input/output pin. i/o 1 emc_d[31] ? external memory data line 31. o3 t1_mat2 ? match output for timer 1, channel 2. p4[0] to p4[31] i/o port 4: port 4 provides up to 32 i/o pins, depending on the package. each pin has individual direction control, pin mode configuration, and function selection. p4[0]/ emc_a[0] i/o 0 p4[0] ? ]general purpose digital input/output pin. i/o 1 emc_a[0] ? external memory address line 0. p4[1]/ emc_a[1] i/o 0 p4[1] ? general purpose digital input/output pin. i/o 1 emc_a[1] ? external memory address line 1. p4[2]/ emc_a[2] i/o 0 p4[2] ? general purpose digital input/output pin. i/o 1 emc_a[2] ? external memory address line 2. p4[3]/ emc_a[3] i/o 0 p4[3] ? general purpose digital input/output pin. i/o 1 emc_a[3] ? external memory address line 3. p4[4]/ emc_a[4] i/o 0 p4[4] ? general purpose digital input/output pin. i/o 1 emc_a[4] ? external memory address line 4. p4[5]/ emc_a[5] i/o 0 p4[5] ? general purpose digital input/output pin. i/o 1 emc_a[5] ? external memory address line 5. p4[6]/ emc_a[6] i/o 0 p4[6] ? general purpose digital input/output pin. i/o 1 emc_a[6] ? external memory address line 6. p4[7]/ emc_a[7] i/o 0 p4[7] ? general purpose digital input/output pin. i/o 1 emc_a[7] ? external memory address line 7. p4[8]/ emc_a[8] i/o 0 p4[8] ? general purpose digital input/output pin. i/o 1 emc_a[8] ? external memory address line 8. p4[9]/ emc_a[9] i/o 0 p4[9] ? general purpose digital input/output pin. i/o 1 emc_a[9] ? external memory address line 9. p4[10]/ emc_a[10] i/o 0 p4[10] ? general purpose digital input/output pin. i/o 1 emc_a[10] ? external memory address line 10. p4[11]/ emc_a[11] i/o 0 p4[11] ? general purpose digital input/output pin. i/o 1 emc_a[11] ? external memory address line 11. p4[12]/ emc_a[12] i/o 0 p4[12] ? general purpose digital input/output pin. i/o 1 emc_a[12] ? external memory address line 12. table 74. pin description ?continued symbol type iocon select [1] description
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 116 of 942 nxp semiconductors UM10562 chapter 6: lpc408x/407x pin configuration p4[13]/ emc_a[13] i/o 0 p4[13] ? general purpose digital input/output pin. i/o 1 emc_a[13] ? external memory address line 13. p4[14]/ emc_a[14] i/o 0 p4[14] ? general purpose digital input/output pin. i/o 1 emc_a[14] ? external memory address line 14. p4[15]/ emc_a[15] i/o 0 p4[15] ? general purpose digital input/output pin. i/o 1 emc_a[15] ? external memory address line 15. p4[16]/ emc_a[16] i/o 0 p4[16] ? general purpose digital input/output pin. i/o 1 emc_a[16] ? external memory address line 16. p4[17]/ emc_a[17] i/o 0 p4[17] ? general purpose digital input/output pin. i/o 1 emc_a[17] ? external memory address line 17. p4[18]/ emc_a[18] i/o 0 p4[18] ? general purpose digital input/output pin. i/o 1 emc_a[18] ? external memory address line 18. p4[19]/ emc_a[19] i/o 0 p4[19] ? general purpose digital input/output pin. i/o 1 emc_a[19] ? external memory address line 19. p4[20]/ emc_a[20]/ i2c2_sda/ ssp1_sck i/o 0 p4[20] ? general purpose digital input/output pin. i/o 1 emc_a[20] ? external memory address line 20. i/o 2 i2c2_sda ? i 2 c2 data input/output ((this pin does not use a specialized i 2 c pad, see section 22.1 for details). i/o 3 ssp1_sck ? serial clock for ssp1. p4[21]/ emc_a[21]/ i2c2_scl/ ssp1_ssel i/o 0 p4[21] ? general purpose digital input/output pin. i/o 1 emc_a[21] ? external memory address line 21. i/o 2 i2c2_scl ? i 2 c2 clock input/output (this pin does not use a specialized i 2 c pad, see section 22.1 for details). i/o 3 ssp1_ssel ? slave select for ssp1. p4[22]/ emc_a[22]/ u2_txd/ ssp1_miso i/o 0 p4[22] ? general purpose digital input/output pin. i/o 1 emc_a[22] ? external memory address line 22. o2 u2_txd ? transmitter output for uart 2. i/o 3 ssp1_miso ? master in slave out for ssp1. p4[23]/ emc_a[23]/ u2_rxd/ ssp1_mosi i/o 0 p4[23] ? general purpose digital input/output pin. i/o 1 emc_a[23] ? external memory address line 23. i2 u2_rxd ? receiver input for uart 2. i/o 3 ssp1_mosi ? master out slave in for ssp1. p4[24]/ emc_oe i/o 0 p4[24] ? general purpose digital input/output pin. o1 emc_oe ? low active output enable signal. p4[25]/ emc_we i/o 0 p4[25] ? general purpose digital input/output pin. o1 emc_we ? low active write enable signal. p4[26]/ emc_bls0 i/o 0 p4[26] ? general purpose digital input/output pin. o1 emc_bls0 ? low active byte lane select signal 0. p4[27]/ emc_bls1 i/o 0 p4[27] ? general purpose digital input/output pin. o1 emc_bls1 ? low active byte lane select signal 1. table 74. pin description ?continued symbol type iocon select [1] description
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 117 of 942 nxp semiconductors UM10562 chapter 6: lpc408x/407x pin configuration p4[28]/ emc_bls2 / u3_txd/ t2_mat0/ lcd_vd[6]/ lcd_vd[10]/ lcd_vd[2] i/o 0 p4 [28] ? general purpose digital input/output pin. o1 emc_bls2 ? low active byte lane select signal 2. o2 txd3 ? transmitter output for uart 3. o3 t2_mat0 ? match output for timer 2, channel 0. o5 lcd_vd[6] ? lcd data. o6 lcd_vd[10] ? lcd data. o7 lcd_vd[2] ? lcd data. p4[29]/ emc_bls3 / u3_rxd/ t2_mat1/ i2c2_scl/ lcd_vd[7]/ lcd_vd[11]/ lcd_vd[3] i/o 0 p4[29] ? general purpose digital input/output pin. o1 emc_bls3 ? low active byte lane select signal 3. i2 u3_rxd ? receiver input for uart 3. o3 t2_mat1 ? match output for timer 2, channel 1. i/o 4 i2c2_scl ? i 2 c2 clock input/output (this pin does not use a specialized i 2 c pad, see section 22.1 for details). o5 lcd_vd[7] ? lcd data. o6 lcd_vd[11] ? lcd data. o7 lcd_vd[3] ? lcd data. p4[30]/ emc_cs0 / cmp0_out i/o 0 p4[30] ? general purpose digital input/output pin. o1 emc_cs0 ? low active chip select 0 signal. o5 cmp0_out ? comparator 0 output. p4[31]/ emc_cs1 i/o 0 p4[31] ? general purpose digital input/output pin. o1 emc_cs1 ? low active chip select 1 signal. p5[0] to p5[4] i/o port 5: port 5 provides up to 5 i/o pins, depending on the package. each pin has individual direction control, pin mode configuration, and function selection. p5[0]/ emc_a[24]/ t2_mat2 i/o 0 p5[0] ? general purpose digital input/output pin. i/o 1 emc_a[24] ? external memory address line 24. o3 t2_mat2 ? match output for timer 2, channel 2. p5[1]/ emc_a[25]/ t2_mat3 i/o 0 p5[1] ? general purpose digital input/output pin. i/o 1 emc_a[25] ? external memory address line 25. o3 t2_mat3 ? match output for timer 2, channel 3. p5[2]/ t3_mat2/ i2c0_sda i/o 0 p5[2] ? general purpose digital input/output pin. o3 t3_mat2 ? match output for timer 3, channel 2. i/o 5 i2c0_sda ? i 2 c0 data input/output (this pin uses a specialized i 2 c pad that supports i 2 c fast mode plus). p5[3]/ u4_rxd/ i2c0_scl i/o 0 p5[3] ? general purpose digital input/output pin. i4 u4_rxd ? receiver input for uart 4. i/o 5 i2c0_scl0 ? i 2 c0 clock input/output (this pin uses a specialized i 2 c pad that supports i 2 c fast mode plus. p5[4]/ u0_oe/ t3_mat3/ u4_txd i/o 0 p5[4] ? general purpose digital input/output pin. o1 u0_oe ? rs-485/eia-485 output enable signal for uart 0. o3 t3_mat3 ? match output for timer 3, channel 3. o4 u4_txd ? transmitter output for uart 4 (input/output in smart card mode). table 74. pin description ?continued symbol type iocon select [1] description
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 118 of 942 nxp semiconductors UM10562 chapter 6: lpc408x/407x pin configuration [1] these values are used in the func field of the iocon registers, described in section 7.4.1 . [2] these pins provide s pecial analog functionality. rtc_alarm o rtc_alarm ? rtc controlled output. this pin has a low drive strength and is powered by v bat (see data sheet for details). it is driven high when an rtc alarm is generated. usb_d ? 2i / o usb_d ? 2 ? usb port 2 bidirectional d ? line. jtag_tdo (swo) o jtag_tdo ? test data out for jtag interface. swo ? serial wire trace output. jtag_tdi i tdi ? test data in for jtag interface. this pin includes an internal pull-up, see section 39.1 . jtag_tms (swdio) i tms ? test mode select for jtag interface. this pin includes an internal pull-up, see section 39.1 . swdio ? serial wire debug data input/output. jtag_ trst i trst ? test reset for jtag interface. this pin includes an internal pull-up, see section 39.1 . jtag_tck (swdclk) i tck ? test clock for jtag interface. this clock must be slower than 1 6 of the cpu clock (cclk) for the jtag interface to operate. swdclk ? serial wire clock. rstout o reset status output. a low output on this pin indicates that the device is in the reset state, for any reason . this reflects the reset input pin and all internal reset sources. reset i external reset input. a low on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor execution to begin at address 0. this pin includes a 20 ns input glitch filter. xtal1 [2] i input to the oscillator circuit and internal clock generator circuits. xtal2 [2] o output from the oscillator amplifier. rtcx1 [2] i input to the rtc 32 khz ultra-low power oscillator circuit. rtcx2 [2] o output from the rtc 32 khz ultra-low power oscillator circuit. v ss [2] i ground: 0 v reference for digital io pins. v ssreg [2] i ground: 0 v reference for internal logic. v ssa [2] i analog ground: 0 v power supply and reference for the adc and dac. this should be the same voltage as v ss , but should be isolated to minimize noise and error. v dd(3v3) [2] i 3.3 v supply voltage: this is the power supply voltage for i/o other than pins in the vbat domain. v dd(reg)(3v3) [2] i 3.3 v regulator supply voltage: this is the power supply for the on-chip voltage regulator that supplies internal logic. v dda [2] i analog 3.3 v pad supply voltage: this can be connected to the same supply as v dd(3v3) but should be isolated to minimize noise and error. this voltage is used to power the adc and dac. note: this pin should be ti ed to 3.3v if the adc and dac are not used. vrefp [2] i adc positive reference voltage: this should be the same voltage as v dda , but should be isolated to minimize noise and error. the voltage level on this pin is used as a reference for adc and dac. note: this pin should be tied to 3.3v if the adc and dac are not used. vbat [2] i rtc power supply: 3.3 v on this pin supplies power to the rtc. table 74. pin description ?continued symbol type iocon select [1] description
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 119 of 942 7.1 introduction a separate register is provided to configure each gpio pin. this configuration includes which internal function is connected to the pi n, the output mode (plain, pull-up, pull-down, or repeater), open drain mode control, hysteres is enable, slew rate control, and buffer setup for analog functions. some pins include additional special controls, such as for i 2 c buffer modes. these registers are summarized in table 75 . [1] which pins are available depends on the part number and package combination. 7.2 description the pin connect block allows most pins of the microcontroller to have more than one potential function. configuration registers co ntrol the multiplexers to allow connection between the pin and the on-chip peripherals. peripherals should be connected to the appropr iate pins prior to being activated and prior to any related interrupt(s) being enabled. activi ty of any enabled peripheral function that is not mapped to a related pin should be considered undefined. selection of a single function on a port pin excludes other peripheral functions available on the same pin. however, the gpio input stays connected and may be read by software or used to contribute to the gpio interrupt feature. 7.3 iocon registers the iocon registers control the functions of device pins. each gpio pin has a dedicated control register to select its function and characteristics. each pin has a unique set of functional capabilities. not all pin characterist ics are selectable on all pins. for instance, pins that have an i 2 c function can be configured for different i 2 c-bus modes, while pins that have an analog alternate function have an analog mode can be selected.details of the iocon registers are in section 7.4.1 . the following sections describe specific characteristics of pins. UM10562 chapter 7: lpc408x/40 7x i/o configuration rev. 1 ? 13 september 2012 user manual table 75. summary of i/o pin configuration registers port registers detail table port 0 pins iocon_p0_nn, where nn is the port pin number, from 0 to 31 [1] table 76 port 1 pins iocon_p1_nn, where nn is the port pin number, from 0 to 31 [1] table 77 port 2 pins iocon_p2_nn, where nn is the port pin number, from 0 to 31 [1] table 78 port 3 pins iocon_p3_nn, where nn is the port pin number, from 0 to 31 [1] table 79 port 4 pins iocon_p4_nn, where nn is the port pin number, from 0 to 31 [1] table 80 port 5 pins iocon_p5_nn, where nn is the port pin number, from 0 to 4 [1] table 81
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 120 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration multiple connections since a particular peripheral function may be allowed on more than one pin, it is possible to configure more than one pin to perform the same function. if a peripheral output function is configured to appear on more than one pin, it will in fact be routed to those pins. if a peripheral input function is defined as coming from more than one source, the values will be logically combined, possib ly resulting in incorrec t peripheral operation. therefore care should be taken to avoid this situation. 7.3.1 pin function the func bits in the iocon registers can be set to gpio (typically value 000) or to a special function. for pins set to gpio, the fi ondir registers determi ne whether the pin is configured as an input or output (see section 8.5.1.1 ). for any special function, the pin direction is controlled automatically depending on the function. the fiondir registers have no effect for special functions. fig 14. i/o configurations 100818 pin configured as digital output px[y] esd esd v dd data output output enable open-drain enable strong pull-up strong pull-down weak pull-up weak pull-down pull-down enable pull-up enable repeater mode enable 10 ns glitch filter enable input invert pin configured as digital input enable glitch filter digital input pin configured as analog input analog input v dd v dd enable analog input
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 121 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration 7.3.2 pin mode the mode bits in the iocon register allow the selection of on-chip pull-up or pull-down resistors for each pin or select the repeater mode. the possible on-chip resistor configurations are pull-up enabled, pull-down enabled, or no pull-up/pull-down. the default value is pull-up enabled. the repeater mode enables the pull-up resistor if the pin is high and enables the pull-down resistor if the pin is low. this causes the pin to re tain its last know n state if it is configured as an input and is not driven externally. such state retention is not applicable to the deep power-down mode. repeater mode may typically be used to prevent a pin from floating (and potentially using significant power if it floats to an indeterm inate state) if it is temporarily not driven. 7.3.3 hysteresis the input buffer for digital functions can be configured with or without hysteresis. see the appropriate specific device data sheet for quantitative details. 7.3.4 input inversion this option is included to save users from having to include an external inverter on an input that is only available in the opposite pola rity from an external source. do not set this option on a gpio output. doing so can result in inadvertent toggling of an output with input inversion selected, as a result of operations on other pins in the same port. for example, if software reads a gpio port register, modifies other bits/outputs in the value, and writes the result back to the port regi ster, any output in the port that has input inversion selected will change state. 7.3.5 analog/digital mode in analog mode, the analog input connection is enabled. in digital mode, the analog input connection is disabled. this protects the a nalog input from voltages outside the range of the analog power supply and reference that may sometimes be present on digital pins, since they are typically 5v tolerant. if analog mode is selected, the mode field should be ?inactive? (00); the hys, inv, filtr, slew, and od settings have no effect. for an unconnected pin that has an analog function, keep the admode bit set to 1 (digital mode), and pull-up or pull-down mode selected in the mode field. 7.3.6 input filter type a and w pins include a filter that can be selectively enabled. the filter suppresses input pulses smaller than about 10 ns. 7.3.7 output slew rate the slew bits of digital outputs that do not need to switch state very quickly should be set to ?standard?. this settin g allows multiple outputs to switch simultaneously without noticeably degrading the power/ground distribu tion of the device, and has only a small effect on signal transition time . this is particularly import ant if analog accuracy is significant to the application. see the relevant specific device data sheet for more details.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 122 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration 7.3.8 i 2 c modes pins that support i 2 c with specialized pad electronics (p 0[27], p0[28], p5[2], and p5[3]) have additional configuration bits. these are not hardwired so that the pins can be more easily used for non-i 2 c functions. the hs bit applies to standard, fast-mode, and fast-mode plus i 2 c, and is available for all the pins noted above. the hidrive bit applies only to pins p5[2] and p5[3], and is used to select between standard mode and fast-mode i 2 c or fast-mode plus i 2 c. ? for any i 2 c mode, clear the hs bit so that the input glitch filter is enabled. clear the hidrive bit if it exists for that pin to se lect the correct drive strength for standard mode or fast-mode i 2 c ? for fast-mode plus i 2 c operation, set the hidrive bit to select the correct drive strength for fast-mode plus i 2 c. ? for non-i 2 c operation, these pins remain open-drain and can only drive low, regardless of how hs and hidrive are set. they would typically be used with an external pull-up resistor if they are used as outputs unless they are used only to sink current. leave hs = 1 and hidrive = 0 (if ap plicable) to maximize compatibility with other gpio pins. 7.3.9 open-drain mode when output is selected, either by selecting a special function in the func field, or by selecting the gpio function for a pin having a 1 in its fiondir register, a 1 in the od bit selects open-drain operation, that is, a 1 disables the high-drive transistor. this option has no effect on the primary i 2 c pins. note that the properties of a pin in this simulated open-drain mode are somewhat different t han those of a true open drain output. 7.3.10 dac enable the pin that includes the dac output as a potential function includes an enable for the function that must be set if the dac output is used.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 123 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration 7.4 register description the pin connect block contains an i/o control register (iocon) for each pin that has programmable attributes, and selects peripheral functions associated with that pin. these registers are shown by gpio port number in tables 7?76 through 7?81 . [1] reset value reflects the data stored in used bi ts only. it does not include reserved bits content. [2] iocon types are d (standard digital pin), and other pins with a speciali zed function: a (analog), u (usb), i (i2c), and w. table 76. i/o control registers for port 0 port pin register access reset value [1] address iocon type [2] 208-pin 180-pin 144-pin 80-pin p0[0] iocon_p0_00 r/w 0x030 0x4002 c000 d (tables 82 , 83 )xxxx p0[1] iocon_p0_01 r/w 0x030 0x4002 c004 d (tables 82 , 83 )xxxx p0[2] iocon_p0_02 r/w 0x030 0x4002 c008 d (tables 82 , 83 )xxxx p0[3] iocon_p0_03 r/w 0x030 0x4002 c00c d (tables 82 , 83 )xxxx p0[4] iocon_p0_04 r/w 0x030 0x4002 c010 d (tables 82 , 83 )x x x - p0[5] iocon_p0_05 r/w 0x030 0x4002 c014 d (tables 82 , 83 )x x x - p0[6] iocon_p0_06 r/w 0x030 0x4002 c018 d (tables 82 , 83 )xxxx p0[7] iocon_p0_07 r/w 0x0a0 0x4002 c01c w (tables 90 , 91 )xxxx p0[8] iocon_p0_08 r/w 0x0a0 0x4002 c020 w (tables 90 , 91 )xxxx p0[9] iocon_p0_09 r/w 0x0a0 0x4002 c024 w (tables 90 , 91 )xxxx p0[10] iocon_p0_10 r/w 0x030 0x4002 c028 d (tables 82 , 83 )xxxx p0[11] iocon_p0_11 r/w 0x030 0x4002 c02c d (tables 82 , 83 )xxxx p0[12] iocon_p0_12 r/w 0x1b0 0x4002 c030 a (tables 84 , 85 )x x x - p0[13] iocon_p0_13 r/w 0x1b0 0x4002 c034 a (tables 84 , 85 )x x x - p0[14] iocon_p0_14 r/w 0x030 0x4002 c038 d (tables 82 , 83 )x x x - p0[15] iocon_p0_15 r/w 0x030 0x4002 c03c d (tables 82 , 83 )xxxx p0[16] iocon_p0_16 r/w 0x030 0x4002 c040 d (tables 82 , 83 )xxxx p0[17] iocon_p0_17 r/w 0x030 0x4002 c044 d (tables 82 , 83 )xxxx p0[18] iocon_p0_18 r/w 0x030 0x4002 c048 d (tables 82 , 83 )xxxx p0[19] iocon_p0_19 r/w 0x030 0x4002 c04c d (tables 82 , 83 )x x x - p0[20] iocon_p0_20 r/w 0x030 0x4002 c050 d (tables 82 , 83 )x x x - p0[21] iocon_p0_21 r/w 0x030 0x4002 c054 d (tables 82 , 83 )x x x - p0[22] iocon_p0_22 r/w 0x030 0x4002 c058 d (tables 82 , 83 )xxxx p0[23] iocon_p0_23 r/w 0x1b0 0x4002 c05c a (tables 84 , 85 )x x x - p0[24] iocon_p0_24 r/w 0x1b0 0x4002 c060 a (tables 84 , 85 )x x x - p0[25] iocon_p0_25 r/w 0x1b0 0x4002 c064 a (tables 84 , 85 )xxxx p0[26] iocon_p0_26 r/w 0x1b0 0x4002 c068 a (tables 84 , 85 )xxxx p0[27] iocon_p0_27 r/w 0 0x4002 c06c i (tables 88 , 89 )x x x - p0[28] iocon_p0_28 r/w 0 0x4002 c070 i (tables 88 , 89 )x x x - p0[29] iocon_p0_29 r/w 0 0x4002 c074 u (tables 86 , 87 )xxxx p0[30] iocon_p0_30 r/w 0 0x4002 c078 u (tables 86 , 87 )xxxx p0[31] iocon_p0_31 r/w 0 0x4002 c07c u (tables 86 , 87 )x x x -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 124 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration [1] reset value reflects the data stored in used bi ts only. it does not include reserved bits content. table 77. i/o control registers for port 1 port pin register access reset value [1] address iocon type 208-pin 180-pin 144-pin 80-pin p1[0] iocon_p1_00 r/w 0x030 0x4002 c080 d (tables 82 , 83 )xxxx p1[1] iocon_p1_01 r/w 0x030 0x4002 c084 d (tables 82 , 83 )xxxx p1[2] iocon_p1_02 r/w 0x030 0x4002 c088 d (tables 82 , 83 )x x - - p1[3] iocon_p1_03 r/w 0x030 0x4002 c08c d (tables 82 , 83 )x x - - p1[4] iocon_p1_04 r/w 0x030 0x4002 c090 d (tables 82 , 83 )xxxx p1[5] iocon_p1_05 r/w 0x030 0x4002 c094 w (tables 90 , 91 )x x - - p1[6] iocon_p1_06 r/w 0x030 0x4002 c098 w (tables 90 , 91 )x x - - p1[7] iocon_p1_07 r/w 0x030 0x4002 c09c w (tables 90 , 91 )x x - - p1[8] iocon_p1_08 r/w 0x030 0x4002 c0a0 d (tables 82 , 83 )xxxx p1[9] iocon_p1_09 r/w 0x030 0x4002 c0a4 d (tables 82 , 83 )xxxx p1[10] iocon_p1_10 r/w 0x030 0x4002 c0a8 d (tables 82 , 83 )xxxx p1[11] iocon_p1_11 r/w 0x030 0x4002 c0ac d (tables 82 , 83 )x x - - p1[12] iocon_p1_12 r/w 0x030 0x4002 c0b0 d (tables 82 , 83 )x x - - p1[13] iocon_p1_13 r/w 0x030 0x4002 c0b4 d (tables 82 , 83 )x x - - p1[14] iocon_p1_14 r/w 0x030 0x4002 c0b8 w (tables 90 , 91 )xxxx p1[15] iocon_p1_15 r/w 0x030 0x4002 c0bc d (tables 82 , 83 )xxxx p1[16] iocon_p1_16 r/w 0x030 0x4002 c0c0 w (tables 90 , 91 )x x x - p1[17] iocon_p1_17 r/w 0x030 0x4002 c0c4 w (tables 90 , 91 )x x x - p1[18] iocon_p1_18 r/w 0x030 0x4002 c0c8 d (tables 82 , 83 )xxxx p1[19] iocon_p1_19 r/w 0x030 0x4002 c0cc d (tables 82 , 83 )xxxx p1[20] iocon_p1_20 r/w 0x030 0x4002 c0d0 d (tables 82 , 83 )xxxx p1[21] iocon_p1_21 r/w 0x030 0x4002 c0d4 d (tables 82 , 83 )x x x - p1[22] iocon_p1_22 r/w 0x030 0x4002 c0d8 d (tables 82 , 83 )xxxx p1[23] iocon_p1_23 r/w 0x030 0x4002 c0dc d (tables 82 , 83 )xxxx p1[24] iocon_p1_24 r/w 0x030 0x4002 c0e0 d (tables 82 , 83 )xxxx p1[25] iocon_p1_25 r/w 0x030 0x4002 c0e4 d (tables 82 , 83 )xxxx p1[26] iocon_p1_26 r/w 0x030 0x4002 c0e8 d (tables 82 , 83 )xxxx p1[27] iocon_p1_27 r/w 0x030 0x4002 c0ec d (tables 82 , 83 )x x x - p1[28] iocon_p1_28 r/w 0x030 0x4002 c0f0 d (tables 82 , 83 )xxxx p1[29] iocon_p1_29 r/w 0x030 0x4002 c0f4 d (tables 82 , 83 )xxxx p1[30] iocon_p1_30 r/w 0x1b0 0x4002 c0f8 a (tables 84 , 85 )xxxx p1[31] iocon_p1_31 r/w 0x1b0 0x4002 c0fc a (tables 84 , 85 )xxxx
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 125 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration [1] reset value reflects the data stored in used bi ts only. it does not include reserved bits content. table 78. i/o control registers for port 2 port pin register access reset value [1] address iocon type 208-pin 180-pin 144-pin 80-pin p2[0] iocon_p2_00 r/w 0x030 0x4002 c100 d (tables 82 , 83 )xxxx p2[1] iocon_p2_01 r/w 0x030 0x4002 c104 d (tables 82 , 83 )xxxx p2[2] iocon_p2_02 r/w 0x030 0x4002 c108 d (tables 82 , 83 )xxxx p2[3] iocon_p2_03 r/w 0x030 0x4002 c10c d (tables 82 , 83 )xxxx p2[4] iocon_p2_04 r/w 0x030 0x4002 c110 d (tables 82 , 83 )xxxx p2[5] iocon_p2_05 r/w 0x030 0x4002 c114 d (tables 82 , 83 )xxxx p2[6] iocon_p2_06 r/w 0x030 0x4002 c118 d (tables 82 , 83 )xxxx p2[7] iocon_p2_07 r/w 0x030 0x4002 c11c d (tables 82 , 83 )xxxx p2[8] iocon_p2_08 r/w 0x030 0x4002 c120 d (tables 82 , 83 )xxxx p2[9] iocon_p2_09 r/w 0x030 0x4002 c124 d (tables 82 , 83 )xxxx p2[10] iocon_p2_10 r/w 0x030 0x4002 c128 d (tables 82 , 83 )xxxx p2[11] iocon_p2_11 r/w 0x030 0x4002 c12c d (tables 82 , 83 )x x x - p2[12] iocon_p2_12 r/w 0x030 0x4002 c130 d (tables 82 , 83 )x x x - p2[13] iocon_p2_13 r/w 0x030 0x4002 c134 d (tables 82 , 83 )x x x - p2[14] iocon_p2_14 r/w 0x030 0x4002 c138 d (tables 82 , 83 )x - - - p2[15] iocon_p2_15 r/w 0x030 0x4002 c13c d (tables 82 , 83 )x - - - p2[16] iocon_p2_16 r/w 0x030 0x4002 c140 d (tables 82 , 83 )x x - - p2[17] iocon_p2_17 r/w 0x030 0x4002 c144 d (tables 82 , 83 )x x - - p2[18] iocon_p2_18 r/w 0x030 0x4002 c148 d (tables 82 , 83 )x x - - p2[19] iocon_p2_19 r/w 0x030 0x4002 c14c d (tables 82 , 83 )x x - - p2[20] iocon_p2_20 r/w 0x030 0x4002 c150 d (tables 82 , 83 )x x - - p2[21] iocon_p2_21 r/w 0x030 0x4002 c154 d (tables 82 , 83 )x x - - p2[22] iocon_p2_22 r/w 0x030 0x4002 c158 d (tables 82 , 83 )x - - - p2[23] iocon_p2_23 r/w 0x030 0x4002 c15c d (tables 82 , 83 )x - - - p2[24] iocon_p2_24 r/w 0x030 0x4002 c160 d (tables 82 , 83 )x x - - p2[25] iocon_p2_25 r/w 0x030 0x4002 c164 d (tables 82 , 83 )x x - - p2[26] iocon_p2_26 r/w 0x030 0x4002 c168 d (tables 82 , 83 )x - - - p2[27] iocon_p2_27 r/w 0x030 0x4002 c16c d (tables 82 , 83 )x - - - p2[28] iocon_p2_28 r/w 0x030 0x4002 c170 d (tables 82 , 83 )x x - - p2[29] iocon_p2_29 r/w 0x030 0x4002 c174 d (tables 82 , 83 )x x - - p2[30] iocon_p2_30 r/w 0x030 0x4002 c178 d (tables 82 , 83 )x - - - p2[31] iocon_p2_31 r/w 0x030 0x4002 c17c d (tables 82 , 83 )x - - -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 126 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration [1] reset value reflects the data stored in used bi ts only. it does not include reserved bits content. table 79. i/o control registers for port 3 port pin register access reset value [1] address iocon type 208-pin 180-pin 144-pin 80-pin p3[0] iocon_p3_00 r/w 0x030 0x4002 c180 d (tables 82 , 83 )x x x - p3[1] iocon_p3_01 r/w 0x030 0x4002 c184 d (tables 82 , 83 )x x x - p3[2] iocon_p3_02 r/w 0x030 0x4002 c188 d (tables 82 , 83 )x x x - p3[3] iocon_p3_03 r/w 0x030 0x4002 c18c d (tables 82 , 83 )x x x - p3[4] iocon_p3_04 r/w 0x030 0x4002 c190 d (tables 82 , 83 )x x x - p3[5] iocon_p3_05 r/w 0x030 0x4002 c194 d (tables 82 , 83 )x x x - p3[6] iocon_p3_06 r/w 0x030 0x4002 c198 d (tables 82 , 83 )x x x - p3[7] iocon_p3_07 r/w 0x030 0x4002 c19c d (tables 82 , 83 )x x x - p3[8] iocon_p3_08 r/w 0x030 0x4002 c1a0 d (tables 82 , 83 )x x - - p3[9] iocon_p3_09 r/w 0x030 0x4002 c1a4 d (tables 82 , 83 )x x - - p3[10] iocon_p3_10 r/w 0x030 0x4002 c1a8 d (tables 82 , 83 )x x - - p3[11] iocon_p3_11 r/w 0x030 0x4002 c1ac d (tables 82 , 83 )x x - - p3[12] iocon_p3_12 r/w 0x030 0x4002 c1b0 d (tables 82 , 83 )x x - - p3[13] iocon_p3_13 r/w 0x030 0x4002 c1b4 d (tables 82 , 83 )x x - - p3[14] iocon_p3_14 r/w 0x030 0x4002 c1b8 d (tables 82 , 83 )x x - - p3[15] iocon_p3_15 r/w 0x030 0x4002 c1bc d (tables 82 , 83 )x x - - p3[16] iocon_p3_16 r/w 0x030 0x4002 c1c0 d (tables 82 , 83 )x - - - p3[17] iocon_p3_17 r/w 0x030 0x4002 c1c4 d (tables 82 , 83 )x - - - p3[18] iocon_p3_18 r/w 0x030 0x4002 c1c8 d (tables 82 , 83 )x - - - p3[19] iocon_p3_19 r/w 0x030 0x4002 c1cc d (tables 82 , 83 )x - - - p3[20] iocon_p3_20 r/w 0x030 0x4002 c1d0 d (tables 82 , 83 )x - - - p3[21] iocon_p3_21 r/w 0x030 0x4002 c1d4 d (tables 82 , 83 )x - - - p3[22] iocon_p3_22 r/w 0x030 0x4002 c1d8 d (tables 82 , 83 )x - - - p3[23] iocon_p3_23 r/w 0x030 0x4002 c1dc d (tables 82 , 83 )x x x - p3[24] iocon_p3_24 r/w 0x030 0x4002 c1e0 d (tables 82 , 83 )x x x - p3[25] iocon_p3_25 r/w 0x030 0x4002 c1e4 d (tables 82 , 83 )x x x - p3[26] iocon_p3_26 r/w 0x030 0x4002 c1e8 d (tables 82 , 83 )x x x - p3[27] iocon_p3_27 r/w 0x030 0x4002 c1ec d (tables 82 , 83 )x - - - p3[28] iocon_p3_28 r/w 0x030 0x4002 c1f0 d (tables 82 , 83 )x - - - p3[29] iocon_p3_29 r/w 0x030 0x4002 c1f4 d (tables 82 , 83 )x - - - p3[30] iocon_p3_30 r/w 0x030 0x4002 c1f8 d (tables 82 , 83 )x - - - p3[31] iocon_p3_31 r/w 0x030 0x4002 c1fc d (tables 82 , 83 )x - - -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 127 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration [1] reset value reflects the data stored in used bi ts only. it does not include reserved bits content. table 80. i/o control registers for port 4 port pin register access reset value [1] address iocon type 208-pin 180-pin 144-pin 80-pin p4[0] iocon_p4_00 r/w 0x030 0x4002 c200 d (tables 82 , 83 )x x x - p4[1] iocon_p4_01 r/w 0x030 0x4002 c204 d (tables 82 , 83 )x x x - p4[2] iocon_p4_02 r/w 0x030 0x4002 c208 d (tables 82 , 83 )x x x - p4[3] iocon_p4_03 r/w 0x030 0x4002 c20c d (tables 82 , 83 )x x x - p4[4] iocon_p4_04 r/w 0x030 0x4002 c210 d (tables 82 , 83 )x x x - p4[5] iocon_p4_05 r/w 0x030 0x4002 c214 d (tables 82 , 83 )x x x - p4[6] iocon_p4_06 r/w 0x030 0x4002 c218 d (tables 82 , 83 )x x x - p4[7] iocon_p4_07 r/w 0x030 0x4002 c21c d (tables 82 , 83 )x x x - p4[8] iocon_p4_08 r/w 0x030 0x4002 c220 d (tables 82 , 83 )x x x - p4[9] iocon_p4_09 r/w 0x030 0x4002 c224 d (tables 82 , 83 )x x x - p4[10] iocon_p4_10 r/w 0x030 0x4002 c228 d (tables 82 , 83 )x x x - p4[11] iocon_p4_11 r/w 0x030 0x4002 c22c d (tables 82 , 83 )x x x - p4[12] iocon_p4_12 r/w 0x030 0x4002 c230 d (tables 82 , 83 )x x x - p4[13] iocon_p4_13 r/w 0x030 0x4002 c234 d (tables 82 , 83 )x x x - p4[14] iocon_p4_14 r/w 0x030 0x4002 c238 d (tables 82 , 83 )x x x - p4[15] iocon_p4_15 r/w 0x030 0x4002 c23c d (tables 82 , 83 )x x x - p4[16] iocon_p4_16 r/w 0x030 0x4002 c240 d (tables 82 , 83 )x x - - p4[17] iocon_p4_17 r/w 0x030 0x4002 c244 d (tables 82 , 83 )x x - - p4[18] iocon_p4_18 r/w 0x030 0x4002 c248 d (tables 82 , 83 )x x - - p4[19] iocon_p4_19 r/w 0x030 0x4002 c24c d (tables 82 , 83 )x x - - p4[20] iocon_p4_20 r/w 0x030 0x4002 c250 d (tables 82 , 83 )x - - - p4[21] iocon_p4_21 r/w 0x030 0x4002 c254 d (tables 82 , 83 )x - - - p4[22] iocon_p4_22 r/w 0x030 0x4002 c258 d (tables 82 , 83 )x - - - p4[23] iocon_p4_23 r/w 0x030 0x4002 c25c d (tables 82 , 83 )x - - - p4[24] iocon_p4_24 r/w 0x030 0x4002 c260 d (tables 82 , 83 )x x x - p4[25] iocon_p4_25 r/w 0x030 0x4002 c264 d (tables 82 , 83 )x x x - p4[26] iocon_p4_26 r/w 0x030 0x4002 c268 d (tables 82 , 83 )x x - - p4[27] iocon_p4_27 r/w 0x030 0x4002 c26c d (tables 82 , 83 )x x - - p4[28] iocon_p4_28 r/w 0x030 0x4002 c270 d (tables 82 , 83 )xxxx p4[29] iocon_p4_29 r/w 0x030 0x4002 c274 d (tables 82 , 83 )xxxx p4[30] iocon_p4_30 r/w 0x030 0x4002 c278 d (tables 82 , 83 )x x x - p4[31] iocon_p4_31 r/w 0x030 0x4002 c27c d (tables 82 , 83 )x x x -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 128 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration [1] reset value reflects the data stored in used bi ts only. it does not include reserved bits content. table 81. i/o control registers for port 5 port pin register access reset value [1] address iocon type 208-pin 180-pin 144-pin 80-pin p5[0] iocon_p5_00 r/w 0x030 0x4002 c280 d (tables 82 , 83 )x x x - p5[1] iocon_p5_01 r/w 0x030 0x4002 c284 d (tables 82 , 83 )x x x - p5[2] iocon_p5_02 r/w 0 0x4002 c288 i (tables 88 , 89 )x x x - p5[3] iocon_p5_03 r/w 0 0x4002 c28c i (tables 88 , 89 )x x x - p5[4] iocon_p5_04 r/w 0x030 0x4002 c290 d (tables 82 , 83 )x x x -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 129 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration 7.4.1 i/o configuration regi ster contents (iocon) the functions of bits in the iocon register for each gpio port pin is described in the following sections. there are some differences in iocon for special port pins compared to most other port pins. these include pins that support analog fu nctions (such as adc inputs and the dac output), the usb d+/d- pins, and specialized i 2 c pins: ? ? type d iocon registers (applies to most gpio port pins) ? ? ? type a iocon registers (applies to pins that include an analog function) ? ? ? type u iocon registers (applies to pins that include a usb d+ or d- function) ? ? ? type i iocon registers (applies to pins that include a specialized i 2 c function) ? ? ? type w iocon registers (these pins are otherwise the same as type d, but include a selectable input glitch filter, and default to pull-down/pull-up disabled). ?
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 130 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration 7.4.1.1 type d iocon registers (applies to most gpio port pins) this iocon table applies to all port pins except p0[7 to 9], p0[12 to 13], p0[23 to 31], p1[30 to 31], and p5[2 to 3]. those pins include dac, adc, usb, i 2 c, or input glitch filter functions that alter the contents of the related iocon registers. table 82. type d iocon registers bit description bit symbol value description reset value 2:0 func selects pin function. see ta b l e 8 3 for specific values. 000 4:3 mode selects function mode (on-chip pull-up/pull-down resistor control). see section 7.3.2 ? pin mode ? . 10 00 inactive (no pull-down/pull-up resistor enabled). 01 pull-down resistor enabled. 10 pull-up resistor enabled. 11 repeater mode. 5 hys hysteresis. see section 7.3.3 ? hysteresis ? .1 0disable. 1 enable. 6 inv input polarity. see section 7.3.4 ? input inversion ? .0 0 input is not inverted (a high on the pin reads as 1) 1 input is inverted (a high on the pin reads as 0) 8:7 - reserved. read value is undefined, only zero should be written. na 9 slew driver slew rate. see section 7.3.7 ? output slew rate ? .0 0 standard mode, output slew rate control is enabled. more outputs can be switched simultaneously. 1 fast mode, slew rate control is disabled. re fer to the appropriate specific device data sheet for details. 10 od controls open-drain mode. see section 7.3.9 ? open-drain mode ? .0 0 normal push-pull output 1 simulated open-drain output (high drive disabled) 31:11 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 131 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration table 83. type d i/o control regist ers: func values and pin functions value of func field in iocon register register 000 001 010 011 100 101 110 111 iocon_p0_0 p0[0] can_rd1 u3_txd i2c1_sda u0_txd iocon_p0_1 p0[1] can_td1 u3_rxd i2c1_scl u0_rxd iocon_p0_2 p0[2] u0_txd u3_txd iocon_p0_3 p0[3] u0_rxd u3_rxd iocon_p0_4 p0[4] i2s_rx_sck can_rd2 t2_cap0 cmp_rosc lcd_vd[0] iocon_p0_5 p0[5] i2s_rx_ws can_td2 t2_cap1 cmp_reset lcd_vd[1] iocon_p0_6 p0[6] i2s_rx_sda ssp1_ssel t2_mat0 u1_rts cmp_rosc lcd_vd[8] iocon_p0_10 p0[10] u2_txd i2c2_sda t3_mat0 lcd_vd[5] iocon_p0_11 p0[11] u2_rxd i2c2_scl t3_mat1 lcd_vd[10] iocon_p0_14 p0[14] usb_hsten2 ssp1_ssel usb_connect2 iocon_p0_15 p0[15] u1_txd ssp0_sck spifi_io[2] iocon_p0_16 p0[16] u1_rxd ssp0_ssel spifi_io[3] iocon_p0_17 p0[17] u1_cts ssp0_miso spifi_io[1] iocon_p0_18 p0[18] u1_dcd ssp0_mosi spifi_io[0] iocon_p0_19 p0[19] u1_dsr sd_clk i2c1_sda lcd_vd[13] iocon_p0_20 p0[20] u1_dtr sd_cmd i2c1_scl lcd_vd[14] iocon_p0_21 p0[21] u1_ri sd_pwr u4_oe can_rd1 u4_clk iocon_p0_22 p0[22] u1_rts sd_dat[0] u4_txd can_td1 spifi_clk iocon_p1_0 p1[0] enet_txd0 t3_cap1 ssp2_sck iocon_p1_1 p1[1] enet_txd1 t3_mat3 ssp2_mosi iocon_p1_2 p1[2] enet_txd2 sd_clk pwm0[1] iocon_p1_3 p1[3] enet_ txd3 sd_cmd pwm0[2] iocon_p1_4 p1[4] enet_tx_en t3_mat2 ssp2_miso iocon_p1_8 p1[8] enet_crs t3_mat1 ssp2_ssel iocon_p1_9 p1[9] enet_rxd0 t3_mat0 iocon_p1_10 p1[10] enet_rxd1 t3_cap0 iocon_p1_11 p1[11] enet_rxd2 sd_dat[2] pwm0[6] iocon_p1_12 p1[12] enet_rxd3 sd_dat[3] pwm0_cap0 cmp1_out iocon_p1_13 p1[13] enet_rx_dv
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 132 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration iocon_p1_15 p1[15] enet_rx_clk i2c2_sda iocon_p1_18 p1[18] usb_up_led1 pwm1[1] t1_cap0 ssp1_miso iocon_p1_19 p1[19] usb_tx_e1 usb_ppwr1 t1_cap1 mc_0a ssp1_sck u2_oe iocon_p1_20 p1[20] usb_tx_d p1 pwm1[2] qei_pha mc_fb0 ssp 0_sck lcd_vd[6] lcd_vd[10] iocon_p1_21 p1[21] usb_tx_d m1 pwm1[3] ssp0_ssel mc_abort lcd_vd[7] lcd_vd[11] iocon_p1_22 p1[22] usb_rcv1 usb_pwrd1 t1_mat0 mc_0b ssp1_mosi lcd_vd[8] lcd_vd[12] iocon_p1_23 p1[23] usb_rx_dp1 pwm1[4] qei_phb mc_fb1 ssp0_miso lcd_vd[9] lcd_vd[13] iocon_p1_24 p1[24] usb_rx_dm1 pwm1[5] qei_idx mc_fb2 ssp0_mosi lcd_vd[10] lcd_vd[14] iocon_p1_25 p1[25] usb_ls1 usb_hsten1 t1_mat1 mc_1a clkout lcd_vd[11] lcd_vd[15] iocon_p1_26 p1[26] usb_sspnd1 pwm1[6] t0_cap0 mc_1b ssp1_ ssel lcd_vd[12] lcd_vd[20] iocon_p1_27 p1[27] usb_int1 usb_ovrcr1 t0_cap1 clkout lcd_vd[13] lcd_vd[21] iocon_p1_28 p1[28] usb_scl1 pwm1_cap0 t0_mat0 mc_2a ssp0_ ssel lcd_vd[14] lcd_vd[22] iocon_p1_29 p1[29] usb_sda1 pwm1_cap1 t0_mat1 mc_2b u4_txd lcd_vd[15] lcd_vd[23] iocon_p2_0 p2[0] pwm1[1] u1_txd lcd_pwr iocon_p2_1 p2[1] pwm1[2] u1_rxd lcd_le iocon_p2_2 p2[2] pwm1[3] u1_cts t2_mat3 tracedata[3] lcd_dclk iocon_p2_3 p2[3] pwm1[4] u1_dcd t2_mat2 tracedata[2] lcd_fp iocon_p2_4 p2[4] pwm1[5] u1_dsr t2_mat1 tracedata[1] lcd_enab_m iocon_p2_5 p2[5] pwm1[6] u1_dtr t2_mat0 tracedata[0] lcd_lp iocon_p2_6 p2[6] pwm1_cap0 u1_ri t2_cap0 u2_oe traceclk lcd_vd[0] lcd_vd[4] iocon_p2_7 p2[7] can_rd2 u1_rts spifi_cs lcd_vd[1] lcd_vd[5] iocon_p2_8 p2[8] can_td2 u2_txd u1_cts enet_mdc lcd_vd[2] lcd_vd[6] iocon_p2_9 p2[9] usb_connec t1 u2_rxd u4_rxd enet_mdio lcd_vd[3] lcd_vd[7] iocon_p2_10 p2[10] eint0 nmi iocon_p2_11 p2[11] eint1 sd_dat[1] i2s_tx_sck lcd_clkin iocon_p2_12 p2[12] eint2 sd_dat[2] i2s_tx_ws lcd_vd[4] lcd_vd[3] lcd_vd[8] lcd_vd[18] iocon_p2_13 p2[13] eint3 sd_dat[3] i2s_tx_sda lcd_vd[5] lcd_vd[9] lcd_vd[19] iocon_p2_14 p2[14] emc_cs2 i2c1_sda t2_cap0 iocon_p2_15 p2[15] emc_cs3 i2c1_scl t2_cap1 iocon_p2_16 p2[16] emc_cas table 83. type d i/o control regist ers: func values and pin functions value of func field in iocon register register 000 001 010 011 100 101 110 111
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 133 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration iocon_p2_17 p2[17] emc_ras iocon_p2_18 p2[18] emc_clk0 iocon_p2_19 p2[19] emc_clk1 iocon_p2_20 p2[20] emc_dycs0 iocon_p2_21 p2[21] emc_dycs1 iocon_p2_22 p2[22] emc_dycs2 ssp0_sck t3_cap0 iocon_p2_23 p2[23] emc_dycs3 ssp0_ssel t3_cap1 iocon_p2_24 p2[24] emc_cke0 iocon_p2_25 p2[25] emc_cke1 iocon_p2_26 p2[26] emc_cke2 ssp0_miso t3_mat0 iocon_p2_27 p2[27] emc_cke3 ssp0_mosi t3_mat1 iocon_p2_28 p2[28] emc_dqm0 iocon_p2_29 p2[29] emc_dqm1 iocon_p2_30 p2[30] emc_dqm2 i2c2_sda t3_mat2 iocon_p2_31 p2[31] emc_dqm3 i2c2_scl t3_mat3 iocon_p3_0 p3[0] emc_d[0] iocon_p3_1 p3[1] emc_d[1] iocon_p3_2 p3[2] emc_d[2] iocon_p3_3 p3[3] emc_d[3] iocon_p3_4 p3[4] emc_d[4] iocon_p3_5 p3[5] emc_d[5] iocon_p3_6 p3[6] emc_d[6] iocon_p3_7 p3[7] emc_d[7] iocon_p3_8 p3[8] emc_d[8] iocon_p3_9 p3[9] emc_d[9] iocon_p3_10 p3[10] emc_d[10] iocon_p3_11 p3[11] emc_d[11] iocon_p3_12 p3[12] emc_d[12] iocon_p3_13 p3[13] emc_d[13] iocon_p3_14 p3[14] emc_d[14] table 83. type d i/o control regist ers: func values and pin functions value of func field in iocon register register 000 001 010 011 100 101 110 111
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 134 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration iocon_p3_15 p3[15] emc_d[15] iocon_p3_16 p3[16] emc_d[16] pwm0[1] u1_txd iocon_p3_17 p3[17] emc_d[17] pwm0[2] u1_rxd iocon_p3_18 p3[18] emc_d[18] pwm0[3] u1_cts iocon_p3_19 p3[19] emc_d[19] pwm0[4] u1_dcd iocon_p3_20 p3[20] emc_d[20] pwm0[5] u1_dsr iocon_p3_21 p3[21] emc_d[21] pwm0[6] u1_dtr iocon_p3_22 p3[22] emc_d[22] pwm0_cap0 u1_ri iocon_p3_23 p3[23] emc_d[23] pwm1_cap0 t0_cap0 iocon_p3_24 p3[24] emc_d[24] pwm1[1] t0_cap1 iocon_p3_25 p3[25] emc_d[25] pwm1[2] t0_mat0 iocon_p3_26 p3[26] emc_d[26] pwm1[3] t0_mat1 stclk iocon_p3_27 p3[27] emc_d[27] pwm1[4] t1_cap0 iocon_p3_28 p3[28] emc_d[28] pwm1[5] t1_cap1 iocon_p3_29 p3[29] emc_d[29] pwm1[6] t1_mat0 iocon_p3_30 p3[30] emc_d[30] u1_rts t1_mat1 iocon_p3_31 p3[31] emc_d[31] t1_mat2 iocon_p4_0 p4[0] emc_a[0] iocon_p4_1 p4[1] emc_a[1] iocon_p4_2 p4[2] emc_a[2] iocon_p4_3 p4[3] emc_a[3] iocon_p4_4 p4[4] emc_a[4] iocon_p4_5 p4[5] emc_a[5] iocon_p4_6 p4[6] emc_a[6] iocon_p4_7 p4[7] emc_a[7] iocon_p4_8 p4[8] emc_a[8] iocon_p4_9 p4[9] emc_a[9] iocon_p4_10 p4[10] emc_a[10] iocon_p4_11 p4[11] emc_a[11] iocon_p4_12 p4[12] emc_a[12] table 83. type d i/o control regist ers: func values and pin functions value of func field in iocon register register 000 001 010 011 100 101 110 111
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 135 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration iocon_p4_13 p4[13] emc_a[13] iocon_p4_14 p4[14] emc_a[14] iocon_p4_15 p4[15] emc_a[15] iocon_p4_16 p4[16] emc_a[16] iocon_p4_17 p4[17] emc_a[17] iocon_p4_18 p4[18] emc_a[18] iocon_p4_19 p4[19] emc_a[19] iocon_p4_20 p4[20] emc_a[20] i2c2_sda ssp1_sck iocon_p4_21 p4[21] emc _a[21] i2c2_scl ssp1_ssel iocon_p4_22 p4[22] emc_a[22] u2_txd ssp1_miso iocon_p4_23 p4[23] emc_a[23] u2_rxd ssp1_mosi iocon_p4_24 p4[24] emc_oe iocon_p4_25 p4[25] emc_we iocon_p4_26 p4[26] emc_bls0 iocon_p4_27 p4[27] emc_bls1 iocon_p4_28 p4[28] emc_bls2 u3_txd t2_mat0 lcd_vd[6] lcd_vd[10] lcd_vd[2] iocon_p4_29 p4[29] emc_bls3 u3_rxd t2_mat1 i2c2_scl lcd_vd[7] lcd_vd[11] lcd_vd[3] iocon_p4_30 p4[30] emc_cs0 cmp0_out iocon_p4_31 p4[31] emc_cs1 iocon_p5_0 p5[0] emc_a[24] t2_mat2 iocon_p5_1 p5[1] emc_a[25] t2_mat3 iocon_p5_4 p5[4] u0_oe t3_mat3 u4_txd table 83. type d i/o control regist ers: func values and pin functions value of func field in iocon register register 000 001 010 011 100 101 110 111
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 136 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration 7.4.1.2 type a iocon registers (applies to pins that include an analog function) this iocon table applies to pins p0[12 to 13], p0[23 to 26], and p1[30 to 31]. the presence of the dac output on p0[26] makes th at pin slightly different, see the description of bit 16 below. table 84. type a iocon registers bit description bit symbol value description reset value 2:0 func selects pin function. see table 85 for specific values. 0 4:3 mode selects function mode (on-chip pull-up/pull-down resistor control). see section 7.3.2 ? pin mode ? . 10 00 inactive (no pull-down/pull-up resistor enabled). 01 pull-down resistor enabled. 10 pull-up resistor enabled. 11 repeater mode. 5 - reserved. read value is undefined, only zero should be written. na 6 invert input polarity. see section 7.3.4 ? input inversion ? .0 0 input is not inverted (a high on the pin reads as 1) 1 input is inverted (a high on the pin reads as 0) 7 admode select analog/digital mode. see section 7.3.5 ? analog/digital mode ? .1 0 analog mode. 1digital mode. 8 filter controls glitch filter. see section 7.3.6 ? input filter ? .1 0 noise pulses below approximately 10 ns are filtered out 1 no input filtering is done 9 - reserved. read value is undefined, only zero should be written. na 10 od controls open-drain mode. see section 7.3.9 ? open-drain mode ? .0 0 normal push-pull output 1 simulated open-drain output (high drive disabled) 14:11 - reserved. read value is undefined, only zero should be written. na 16 dacen dac enable control. this bit applies only to p0[26], which includes the dac output function dac_out. see section 7.3.10 ? dac enable ? . 0 0 dac is disabled 1 dac is enabled 31:17 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 137 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration table 85. type a i/o control registers: func values and pin functions value of func field in iocon register register 000 001 010 011 100 101 110 111 iocon_p0_12 p0[12] usb_ppwr2 ssp1_miso adc0[6] iocon_p0_13 p0[13] usb_up_led2 ssp1_mosi adc0[7] iocon_p0_23 p0[23] adc0[0] i2s_rx_sck t3_cap0 iocon_p0_24 p0[24] adc0[1] i2s_rx_ws t3_cap1 iocon_p0_25 p0[25] adc0[2] i2s_rx_sda u3_txd iocon_p0_26 p0[26] adc0[3] dac_out u3_rxd iocon_p1_30 p1[30] usb_pwrd2 u sb_vbus adc[4] i2c0_sda u3_oe iocon_p1_31 p1[31] usb_ovrcr2 ssp1_sck adc[5] i2c0_scl
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 138 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration 7.4.1.3 type u iocon registers (applies to pins that include a usb d+ or d- function) this iocon table applies to pins p0[29], p0[30], and p0[31]. these special function pins do not include the selectable modes and options of other pins. table 86. type u iocon registers bit description bit symbol description reset value 2:0 func selects pin function. see table 87 for specific values. 000 31:3 - reserved. read value is undefined, only zero should be written. na table 87. type u i/o control registers: func values and pin functions value of func field in iocon register register 000 001 010 011 100 101 110 111 iocon_p0_29 p0[29] usb_d+1 eint0 iocon_p0_30 p0[30] usb_d-1 eint1 iocon_p0_31 p0[31] usb_d+2
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 139 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration 7.4.1.4 type i iocon registers (applies to pins that include a specialized i 2 c function) this iocon table applies to pins p0[27 to 28] and p5[2 to 3]. table 88. type i iocon re gisters bit description bit symbol value description reset value 2:0 func selects pin function. see table 89 for specific values. 0 5:3 - reserved. read value is undefined, only zero should be written. na 6 invert input polarity. see section 7.3.4 ? input inversion ? .0 0 input is not inverted (a high on the pin reads as 1) 1 input is inverted (a high on the pin reads as 0) 7 - reserved. read value is undefined, only zero should be written. na 8 hs configures i 2 c features for standard mode, fast mode, and fast mode plus operation. see section 7.3.8 ? i 2 c modes ? . 0 0i 2 c 50ns glitch filter and slew rate control enabled. 1i 2 c 50ns glitch filter and slew rate control disabled. 9 hidrive controls sink current capability of the pin, only for p5[2] and p5[3]. see section 7.3.8 ? i 2 c modes ? . 0 0 output drive sink is 4 ma. this is sufficient for standard and fast mode i 2 c. 1 output drive sink is 20 ma. this is needed for fast mode plus i 2 c. refer to the appropriate specific device data sheet for details. 31:10 - reserved. read value is undefined, only zero should be written. na table 89. type i i/o control register s: func values and pin functions value of func field in iocon register register 000 001 010 011 100 101 110 111 iocon_p0_27 p0[27] i2c0_sda usb_sda1 iocon_p0_28 p0[28] i2c0_scl usb_scl1 iocon_p5_2 p5[2] t3_mat2 i2c0_sda iocon_p5_3 p5[3] u4_rxd i2c0_scl
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 140 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration 7.4.1.5 type w iocon registers (these pins are otherwise the same as type d, but include a selectable input glitch filter, and default to pull-down/pull-up disabled). this iocon table applies to pi ns p0[7], p0[8], and p0[9]. table 90. type w iocon registers bit description bit symbol value description reset value 2:0 func selects pin function. see table 91 for specific values. 000 4:3 mode selects the output functional mode for the pin (on-chip pull-up/pull-down resistor control). see section 7.3.2 ? pin mode ? . 00 00 inactive (no pull-down/pull-up resistor enabled). 01 pull-down resistor enabled. 10 pull-up resistor enabled. 11 repeater mode. 5 hys hysteresis. see section 7.3.3 ? hysteresis ? .1 0 disable. 1 enable. 6 inv input polarity. see section 7.3.4 ? input inversion ? .0 0 input is not inverted (a high on the pin reads as 1) 1 input is inverted (a high on the pin reads as 0) 7 admode select analog/digital mode. see section 7.3.5 ? analog/digital mode ? .1 0 analog mode. 1digital mode. 8 filter controls glitch filter. see section 7.3.6 ? input filter ? .0 0 noise pulses below approximately 10 ns are filtered out 1 no input filtering is done 9 slew driver slew rate. see section 7.3.7 ? output slew rate ? .0 0 standard mode, output slew rate control is enabled. more outputs can be switched simultaneously. 1 fast mode, slew rate control is disabled. refer to the appropriate specific device data sheet for details. 10 od controls open-drain mode. see section 7.3.9 ? open-drain mode ? .0 0 normal push-pull output 1 simulated open-drain output (high drive disabled) 31:11 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 141 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration table 91. type w i/o control regist ers: func values an d pin functions value of func field in iocon register register 000 001 010 011 100 101 110 111 iocon_p0_7 p0[7] i2s_tx_sck ssp1_sck t2_mat1 rtc_ev0 cmp_vref lcd_vd[9] iocon_p0_8 p0[8] i2s_tx_ws ssp1_miso t2_mat2 rtc_ev1 cmp1_in[4] lcd_vd[16] iocon_p0_9 p0[9] i2s_tx_sda ssp1_mosi t2_mat3 rtc_ev2 cmp1_in[3] lcd_vd[17] iocon_p1_5 p1[5] enet_tx_er sd_pwr pwm0[3] cmp1_in[2] iocon_p1_6 p1[6] enet_tx_clk sd_dat[0] pwm0[4] cmp0_in[4] iocon_p1_7 p1[7] enet_col sd_dat[1] pwm0[5] cmp1_in[1] iocon_p1_14 p1[14] enet_rx_er t2_cap0 cmp0_in[1] iocon_p1_16 p1[16] enet_mdc i2s_tx_mclk cmp0_in[2] iocon_p1_17 p1[17] enet_mdio i2s_rx_mclk cmp0_in[3]
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 142 of 942 8.1 basic configuration gpios are configured using the following registers: 1. power: in the pconp register ( section 3.3.2.2 ), set bit pcgpio. this enables the gpios themselves, gpio inte rrupts, and the iocon block. 2. pins: see section 7.4.1 for gpio pins and their modes. 3. wake-up: gpio ports 0 and 2 can be used for wake-up if needed, see ( section 3.12.8 ). 4. interrupts: enable gpio interrupts in enr ( ta b l e 1 0 4 or table 109 ) and enf ( table 105 or table 110 ). interrupts are enabled in the nvic using the appropriate interrupt set enable register. 8.2 features 8.2.1 digital i/o ports ? accelerated gpio functions: ? gpio registers are located on a peripheral ahb bus for fast i/o timing. ? mask registers allow treating sets of port bits as a group, leaving other bits unchanged. ? all gpio registers are byte, hal f-word, and word addressable. ? entire port value can be written in one instruction. ? gpio registers are accessible by the gpdma. ? bit-level set and clear registers allow a single instruction set or clear of any number of bits in one port. ? all gpio registers support bit-banding operations by the cpu. ? gpio registers are accessible by the gpdma controller to allow dma of data to or from gpios, synchronized to any dma request. ? direction control of individual port bits. ? all i/os default to input with pull-up after reset. 8.2.2 interrupt generating digital ports ? port 0 and port 2 can provide a single interrupt for any combination of port pins. ? each port pin can be programmed to genera te an interrupt on a rising edge, a falling edge, or both. ? edge detection is asynchronous, so it may operate when clocks are not present, such as during power-down mode. with this feature, level tr iggered interrupts are not needed. ? each enabled interrupt contributes to a wake -up signal that can be used to bring the part out of power-down mode. UM10562 chapter 8: lpc408x/407x gpio rev. 1 ? 13 september 2012 user manual
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 143 of 942 nxp semiconductors UM10562 chapter 8: lpc408x/407x gpio ? registers provide a software view of pending rising edge interrupts, pending falling edge interrupts, and overall pending gpio interrupts. ? the gpio interrupt function does not require that the pin be configured for gpio. this allows interrupting on a change to a pin that is part of an operating peripheral interface. 8.3 applications ? general purpose i/o ? driving leds or other indicators ? controlling off-chip devices ? sensing digital inputs, detecting edges ? bringing the part out of power-down mode 8.4 pin description table 92. gpio pin description pin name type description p0[31:0]; p1[31:0]; p2[31:0]; p3[31:0]; p4[31:0]; p5[4:0] input/ output general purpose input/output. these are typically s hared with other peripherals functions and will therefore not all be available in an application. packaging options may affect the number of gpios available in a particular device. some pins may be limited by requirements of the alternate functions of the pin. for example, some pins that can be used for i 2 c are special pins, and some of that behavior is inherited by any other function selected on that pin. details may be found in section 6.1 .
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 144 of 942 nxp semiconductors UM10562 chapter 8: lpc408x/407x gpio 8.5 register description the registers represent the enhanced gpio feat ures available on all of the gpio ports. these registers are located on an ahb bus for fa st read and write timing. they can all be accessed in byte, half-word, and word sizes. a mask register allows access to a group of bits in a single gpio port independently from other bits in the same port. table 93. register overview: gpio (base address 0x2009 8000) name access address offset description reset value table dir0 r/w 0x000 gpio port0 direction control register. 0 95 mask0 r/w 0x010 mask register for port0. 0 96 pin0 r/w 0x014 port0 pin value register using fiomask. 0 97 set0 r/w 0x018 port0 output set register using fiomask. 0 98 clr0 wo 0x01c port0 output clear register using fiomask. - 99 dir1 r/w 0x020 gpio port1 direction control register. 0 95 mask1 r/w 0x030 mask register for port1. 0 96 pin1 r/w 0x034 port1 pin value register using fiomask. 0 97 set1 r/w 0x038 port1 output set register using fiomask. 0 98 clr1 wo 0x03c port1 output clear register using fiomask. - 99 dir2 r/w 0x040 gpio port2 direction control register. 0 95 mask2 r/w 0x050 mask register for port2. 0 96 pin2 r/w 0x054 port2 pin value register using fiomask. 0 97 set2 r/w 0x058 port2 output set register using fiomask. 0 98 clr2 wo 0x05c port2 output clear register using fiomask. - 99 dir3 r/w 0x060 gpio port3 direction control register. 0 95 mask3 r/w 0x070 mask register for port3. 0 96 pin3 r/w 0x074 port3 pin value register using fiomask. 0 97 set3 r/w 0x078 port3 output set register using fiomask. 0 98 clr3 wo 0x07c port3 output clear register using fiomask. - 99 dir4 r/w 0x080 gpio port4 direction control register. 0 95 mask4 r/w 0x090 mask register for port4. 0 96 pin4 r/w 0x094 port4 pin value register using fiomask. 0 97 set4 r/w 0x098 port4 output set register using fiomask. 0 98 clr4 wo 0x09c port4 output clear register using fiomask. - 99 dir5 r/w 0x0a0 gpio port5 direction control register. 0 95 mask5 r/w 0x0b0 mask register for port5. 0 96 pin5 r/w 0x0b4 port5 pin value register using fiomask. 0 97 set5 r/w 0x0b8 port5 output se t register using fiomask. 0 98 clr5 wo 0x0bc port5 output clear register using fiomask. - 99
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 145 of 942 nxp semiconductors UM10562 chapter 8: lpc408x/407x gpio [1] reset value reflects the data stored in used bi ts only. it does not include reserved bits content. table 94. register overview: gpio interrupt (base address 0x4002 8000) name access address offset description reset value [1] table status ro 0x080 gpio overall interrupt status. 0 100 statr0 ro 0x084 gpio interrupt status for rising edge for port 0. 0 101 statf0 ro 0x088 gpio interrupt status for falling edge for port 0. 0 102 clr0 wo 0x08c gpio interrupt clear. - 103 enr0 r/w 0x090 gpio interrupt enable for rising edge for port 0. 0 104 enf0 r/w 0x094 gpio interrupt enable for falling edge for port 0. 0 105 statr2 ro 0x0a4 gpio interrupt status for rising edge for port 0. 0 106 statf2 ro 0x0a8 gpio interrupt status for falling edge for port 0. 0 107 clr2 wo 0x0ac gpio interrupt clear. - 108 enr2 r/w 0x0b0 gpio interrupt enable for rising edge for port 0. 0 109 enf2 r/w 0x0b4 gpio interrupt enable for falling edge for port 0. 0 110
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 146 of 942 nxp semiconductors UM10562 chapter 8: lpc408x/407x gpio 8.5.1 gpio port registers 8.5.1.1 gpio port direction register this word accessible register is used to c ontrol the direction of the pins when they are configured as gpio port pins. direction bit for any pin must be set according to the pin functionality. note that gpio pins p0[29] and p0[30] ar e shared with the usb_d+ and usb_d- pins and must have the same direction. if either fi o0dir bit 29 or 30 are configured as zero, both p0[29] and p0[30] will be inputs. if both fio0dir bits 29 and 30 ar e ones, both p0[29] and p0[30] will be outputs. aside from the 32-bit long and word only acce ssible dirx register, every fast gpio port can also be controlled via byte and half-word access. 8.5.1.2 fast gpio port mask register this register is used to select port pins that will and w ill not be affected by write accesses to the pinx, setx or clrx register. mask regist er also filters out port?s content when the pinx register is read. a zero in this register?s bit enables an access to the corresponding physical pin via a read or write access. if a bit in this register is one, corresponding pin w ill not be changed with write access and if read, will not be reflected in the updated pinx register. for software examples, see section 8.6 . aside from the 32-bit long and word only acce ssible maskx register, every fast gpio port can also be controlled via byte and half-word access. 8.5.1.3 gpio port pin value register this register provides the value of port pins that are configured to perform only digital functions. the register will give the logic value of the pin re gardless of whether the pin is configured for input or output, or as gpio or an alternate digital function. as an example, table 95. gpio port direction register (dir[0:5] - addresses 0x2009 8000 (dir0) to 0x200980a0 (dir5)) bit description bit symbol description reset value 31:0 pindir fast gpio direction portx control bits. bit 0 in dirx controls pin px[0], bit 31 in dirx controls pin px[31]. 0 = controlled pin is input. 1 = controlled pin is output. 0x0 table 96. fast gpio port mask register (mask[0:5] - addresses 0x2009 8010 (mask0) to 0x2009 80b0 (mask5)) bit description bit symbol description reset value 31:0 pinmask fast gpio physical pin access control. 0 = controlled pin is affected by writes to th e port?s setx, clrx, and pinx registers. current state of the pin can be read from the pinx register. 1 = controlled pin is not affected by writes into the port?s setx, clrx and pinx registers. when the pinx register is read, this bit will not be updated with the state of the physical pin. 0x0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 147 of 942 nxp semiconductors UM10562 chapter 8: lpc408x/407x gpio a particular port pin may have gpio input, gpio output, uart receive, and pwm output as selectable functions. any configuration of that pin will allo w its current logic state to be read from the corresponding pinx register. if a pin has an analog function as one of its options, the pin state cannot be read if the analog configuration is selected. selecting the pin as an a/d input disconnects the digital features of the pin. in that case, the pin value read in the pinx register is not valid. writing to the pinx register st ores the value in the port output register, bypassing the need to use both the setx and clrx registers to ob tain the entire written value. this feature should be used carefully in an application since it affects the entire port. access to a port pin via the pinx register is conditioned by the corresponding bit of the maskx register (see section 8.5.1.2 ). only pins masked with zeros in the mask register (see section 8.5.1.2 ) will be correlated to the current content of the fast gpio port pin value register. aside from the 32-bit long and word only acce ssible pinx register, every fast gpio port can also be controlled via byte and half-word access. 8.5.1.4 gpio port output set register this register is used to produce a high level output at the port pins configured as gpio in an output mode. writing 1 produces a high level at the corresponding port pins. writing 0 has no effect. if any pin is configured as an input or a secondary function, writing 1 to the corresponding bit in the setx has no effect. reading the setx register returns the value of this register, as determined by previous writes to setx and clrx (or pi nx as noted above). this value does not reflect the effect of any outside world influence on the i/o pins. access to a port pin via the setx register is conditioned by the corresponding bit of the maskx register (see section 8.5.1.2 ). aside from the 32-bit long and word only acce ssible setx register, every fast gpio port can also be controlled via byte and half-word access. table 97. fast gpio port pin value register (pin[0:5] - addresses 0x2009 8014 (pin0) to 0x2009 80b4 (pin5)) bit description bit symbol description reset value 31:0 pinval fast gpio output value set bits. bit 0 in clrx corresponds to pin px[0], bit 31 in clrx corresponds to pin px[31]. 0 = controlled pin output is set to low. 1 = controlled pin output is set to high. 0x0 table 98. fast gpio port output set register (set[0:5] - addresses 0x2009 8018 (set0) to 0x2009 80b8 (set5)) bit description bit symbol description reset value 31:0 pinset fast gpio output value set bits. bit 0 in setx controls pin px[0], bit 31 in setx controls pin px[31]. 0 = controlled pin output is unchanged. 1 = controlled pin output is set to high. 0x0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 148 of 942 nxp semiconductors UM10562 chapter 8: lpc408x/407x gpio 8.5.1.5 gpio port output clear register this register is used to produce a low level ou tput at port pins configured as gpio in an output mode. writing 1 produces a low level at the corresponding port pin and clears the corresponding bit in the setx register. writ ing 0 has no effect. if any pin is configured as an input or a secondary function, writing to clrx has no effect. access to a port pin via the clrx register is conditioned by the corresponding bit of the maskx register (see section 8.5.1.2 ). aside from the 32-bit long and word only ac cessible clrx register, every fast gpio port can also be controlled via byte and half-word access. table 99. fast gpio port output clear register (clr[0:5] - addresses 0x2009 801c (clr0) to 0x2009 80bc (clr5)) bit description bit symbol description 31:0 pinclr fast gpio output value clear bits. bit 0 in clrx controls pin px[0], bit 31 controls pin px[31]. 0 = controlled pin output is unchanged. 1 = controlled pin output is set to low.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 149 of 942 nxp semiconductors UM10562 chapter 8: lpc408x/407x gpio 8.5.2 gpio interrupt registers the following registers configure the pins of port 0 and port 2 to generate interrupts. 8.5.2.1 gpio overall interrupt status register this read-only register indicates the presence of interrupt pending on all of the gpio ports that support gpio interrupts. only st atus one bit per port is required. fig 15. gpio interrupt block diagram apb bus rising edge enable register (gpiointenr) apb bus d q r d q r 1 1 write 1 to gpiointcl gpiointstatr register (read only) falling edge enable register (gpiointenf) gpiointstatus register gpiointstatf register (read only) gpiowake (from intwake register) for each supported gpio pin other pinj ints for each supported gpio port to nvic other port ints plus one existing interrupt to wakeup other port wakeups port wakeup port int one per device pin 120608 pin int table 100. gpio overall interrupt status register (status - address 0x4002 8080) bit description bit symbol value description reset value 0 p0int port 0 gpio interrupt pending. 0 0 no pending interrupts on port 0. 1 at least one pending interrupt on port 0. 1 - reserved. the value read from a reserved bit is not defined. na 2 p2int port 2 gpio interrupt pending. 0 0 no pending interrupts on port 2. 1 at least one pending interrupt on port 2. 31:2 - reserved. the value read from a reserved bit is not defined. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 150 of 942 nxp semiconductors UM10562 chapter 8: lpc408x/407x gpio 8.5.2.2 gpio interrupt status for port 0 rising edge interrupt each bit in these read-only registers indicates the rising edge interrupt status for port 0. table 101. gpio interrupt status for port 0 ri sing edge interrupt (statr0 - 0x4002 8084) bit description bit symbol description reset value 0 p0_0rei rising edge interrupt status for p0[0]. 0 = no rising edge detected. 1 = rising edge interrupt generated. 0 1 p0_1rei rising edge interrupt status for p0[1]. see bit 0 description. 0 2 p0_2rei rising edge interrupt status for p0[2]. see bit 0 description. 0 3 p0_3rei rising edge interrupt status for p0[3]. see bit 0 description. 0 4 p0_4rei rising edge interrupt status for p0[4]. see bit 0 description. 0 5 p0_5rei rising edge interrupt status for p0[5]. see bit 0 description. 0 6 p0_6rei rising edge interrupt status for p0[6]. see bit 0 description. 0 7 p0_7rei rising edge interrupt status for p0[7]. see bit 0 description. 0 8 p0_8rei rising edge interrupt status for p0[8]. see bit 0 description. 0 9 p0_9rei rising edge interrupt status for p0[9]. see bit 0 description. 0 10 p0_10rei rising edge interrupt status for p0[10]. see bit 0 description. 0 11 p0_11rei rising edge interrupt status for p0[11]. see bit 0 description. 0 12 p0_12rei rising edge interrupt status for p0[12]. see bit 0 description. 0 13 p0_13rei rising edge interrupt status for p0[13]. see bit 0 description. 0 14 p0_14rei rising edge interrupt status for p0[14]. see bit 0 description. 0 15 p0_15rei rising edge interrupt status for p0[15]. see bit 0 description. 0 16 p0_16rei rising edge interrupt status for p0[16]. see bit 0 description. 0 17 p0_17rei rising edge interrupt status for p0[17]. see bit 0 description. 0 18 p0_18rei rising edge interrupt status for p0[18]. see bit 0 description. 0 19 p0_19rei rising edge interrupt status for p0[19]. see bit 0 description. 0 20 p0_20rei rising edge interrupt status for p0[20]. see bit 0 description. 0 21 p0_21rei rising edge interrupt status for p0[21]. see bit 0 description. 0 22 p0_22rei rising edge interrupt status for p0[22]. see bit 0 description. 0 23 p0_23rei rising edge interrupt status for p0[23]. see bit 0 description. 0 24 p0_24rei rising edge interrupt status for p0[24]. see bit 0 description. 0 25 p0_25rei rising edge interrupt status for p0[25]. see bit 0 description. 0 26 p0_26rei rising edge interrupt status for p0[26]. see bit 0 description. 0 27 p0_27rei rising edge interrupt status for p0[27]. see bit 0 description. 0 28 p0_28rei rising edge interrupt status for p0[28]. see bit 0 description. 0 29 p0_29rei rising edge interrupt status for p0[29]. see bit 0 description. 0 30 p0_30rei rising edge interrupt status for p0[30]. see bit 0 description. 0 31 p0_31rei rising edge interrupt status for p0[31]. see bit 0 description. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 151 of 942 nxp semiconductors UM10562 chapter 8: lpc408x/407x gpio 8.5.2.3 gpio interrupt status for port 0 falling edge interrupt each bit in these read-only re gisters indicates the falling ed ge interrupt status for port 0. table 102. gpio interrupt status for port 0 falling edge interrupt (statf0 - 0x4002 8088) bit description bit symbol description reset value 0 p0_0fei falling edge interrupt status for p0[0]. 0 = no falling edge detected. 1 = falling edge interrupt generated. 0 1 p0_1fei falling edge interrupt status for p0[1]. see bit 0 description. 0 2 p0_2fei falling edge interrupt status for p0[2]. see bit 0 description. 0 3 p0_3fei falling edge interrupt status for p0[3]. see bit 0 description. 0 4 p0_4fei falling edge interrupt status for p0[4]. see bit 0 description. 0 5 p0_5fei falling edge interrupt status for p0[5]. see bit 0 description. 0 6 p0_6fei falling edge interrupt status for p0[6]. see bit 0 description. 0 7 p0_7fei falling edge interrupt status for p0[7]. see bit 0 description. 0 8 p0_8fei falling edge interrupt status for p0[8]. see bit 0 description. 0 9 p0_9fei falling edge interrupt status for p0[9]. see bit 0 description. 0 10 p0_10fei falling edge interrupt status for p0[10]. see bit 0 description. 0 11 p0_11fei falling edge interrupt status for p0[11]. see bit 0 description. 0 12 p0_12fei falling edge interrupt status for p0[12]. see bit 0description. 0 13 p0_13fei falling edge interrupt status for p0[13]. see bit 0 description. 0 14 p0_14fei falling edge interrupt status for p0[14]. see bit 0 description. 0 15 p0_15fei falling edge interrupt status for p0[15]. see bit 0 description. 0 16 p0_16fei falling edge interrupt status for p0[16]. see bit 0 description. 0 17 p0_17fei falling edge interrupt status for p0[17]. see bit 0 description. 0 18 p0_18fei falling edge interrupt status for p0[18]. see bit 0 description. 0 19 p0_19fei falling edge interrupt status for p0[19]. see bit 0 description. 0 20 p0_20fei falling edge interrupt status for p0[20]. see bit 0 description. 0 21 p0_21fei falling edge interrupt status for p0[21]. see bit 0 description. 0 22 p0_22fei falling edge interrupt status for p0[22]. see bit 0 description. 0 23 p0_23fei falling edge interrupt status for p0[23]. see bit 0 description. 0 24 p0_24fei falling edge interrupt status for p0[24]. see bit 0 description. 0 25 p0_25fei falling edge interrupt status for p0[25]. see bit 0 description. 0 26 p0_26fei falling edge interrupt status for p0[26]. see bit 0 description. 0 27 p0_27fei falling edge interrupt status for p0[27]. see bit 0 description. 0 28 p0_28fei falling edge interrupt status for p0[28]. see bit 0 description. 0 29 p0_29fei falling edge interrupt status for p0[29]. see bit 0 description. 0 30 p0_30fei falling edge interrupt status for p0[30]. see bit 0 description. 0 31 p0_31fei falling edge interrupt status for p0[31]. see bit 0 description. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 152 of 942 nxp semiconductors UM10562 chapter 8: lpc408x/407x gpio 8.5.2.4 gpio interrupt clear register for port 0 writing a 1 into a bit in this write-only register clears any interrupts for the corresponding port 0 pin. table 103. gpio interrupt clear register for port 0 (clr0 - 0x4002 808c) bit description bit symbol description 0 p0_0ci clear gpio port interrupts for p0[0]. 0 = no effect. 1 = clear corresponding bits in ionintstatr and ionstatf. 1 p0_1ci clear gpio port interrupts for p0[1]. see bit 0 description. 2 p0_2ci clear gpio port interrupts for p0[2]. see bit 0 description. 3 p0_3ci clear gpio port interrupts for p0[3]. see bit 0 description. 4 p0_4ci clear gpio port interrupts for p0[4]. see bit 0 description. 5 p0_5ci clear gpio port interrupts for p0[5]. see bit 0 description. 6 p0_6ci clear gpio port interrupts for p0[6]. see bit 0 description. 7 p0_7ci clear gpio port interrupts for p0[7]. see bit 0 description. 8 p0_8ci clear gpio port interrupts for p0[8]. see bit 0 description. 9 p0_9ci clear gpio port interrupts for p0[9]. see bit 0 description. 10 p0_10ci clear gpio port interrupts for p0[10]. see bit 0 description. 11 p0_11ci clear gpio port interrupts for p0[11]. see bit 0 description. 12 p0_12ci clear gpio port interrupts for p0[12]. see bit 0 description. 13 p0_13ci clear gpio port interrupts for p0[13]. see bit 0 description. 14 p0_14ci clear gpio port interrupts for p0[14]. see bit 0 description. 15 p0_15ci clear gpio port interrupts for p0[15]. see bit 0 description. 16 p0_16ci clear gpio port interrupts for p0[16]. see bit 0 description. 17 p0_17ci clear gpio port interrupts for p0[17]. see bit 0 description. 18 p0_18ci clear gpio port interrupts for p0[18]. see bit 0 description. 19 p0_19ci clear gpio port interrupts for p0[19]. see bit 0 description. 20 p0_20ci clear gpio port interrupts for p0[20]. see bit 0 description. 21 p0_21ci clear gpio port interrupts for p0[21]. see bit 0 description. 22 p0_22ci clear gpio port interrupts for p0[22]. see bit 0 description. 23 p0_23ci clear gpio port interrupts for p0[23]. see bit 0 description. 24 p0_24ci clear gpio port interrupts for p0[24]. see bit 0 description. 25 p0_25ci clear gpio port interrupts for p0[25]. see bit 0 description. 26 p0_26ci clear gpio port interrupts for p0[26]. see bit 0 description. 27 p0_27ci clear gpio port interrupts for p0[27]. see bit 0 description. 28 p0_28ci clear gpio port interrupts for p0[28]. see bit 0 description. 29 p0_29ci clear gpio port interrupts for p0[29]. see bit 0 description. 30 p0_30ci clear gpio port interrupts for p0[30]. see bit 0 description. 31 p0_31ci clear gpio port interrupts for p0[31]. see bit 0 description.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 153 of 942 nxp semiconductors UM10562 chapter 8: lpc408x/407x gpio 8.5.2.5 gpio interrupt enable for port 0 rising edge each bit in these read-write registers enables the rising edge interrupt for the corresponding port 0 pin. which pins are available depends on the part number and package combination. see the specific device data sheet for details. table 104. gpio interrupt enable for port 0 rising edge (enr0 - 0x4002 8090) bit description bit symbol description reset value 0 p0_0er enable rising edge interrupt for p0[0]. 0 = disable rising edge interrupt. 1 = enable rising edge interrupt. 0 1 p0_1er enable rising edge interrupt for p0[1]. see bit 0 description. 0 2 p0_2er enable rising edge interrupt for p0[2]. see bit 0 description. 0 3 p0_3er enable rising edge interrupt for p0[3]. see bit 0 description. 0 4 p0_4er enable rising edge interrupt for p0[4]. see bit 0 description. 0 5 p0_5er enable rising edge interrupt for p0[5]. see bit 0 description. 0 6 p0_6er enable rising edge interrupt for p0[6]. see bit 0 description. 0 7 p0_7er enable rising edge interrupt for p0[7]. see bit 0 description. 0 8 p0_8er enable rising edge interrupt for p0[8]. see bit 0 description. 0 9 p0_9er enable rising edge interrupt for p0[9]. see bit 0 description. 0 10 p0_10er enable rising edge interrupt for p0[10]. see bit 0 description. 0 11 p0_11er enable rising edge interrupt for p0[11]. see bit 0 description. 0 12 p0_12er enable rising edge interrupt for p0[12]. see bit 0 description. 0 13 p0_13er enable rising edge interrupt for p0[13]. see bit 0 description. 0 14 p0_14er enable rising edge interrupt for p0[14]. see bit 0 description. 0 15 p0_15er enable rising edge interrupt for p0[15]. see bit 0 description. 0 16 p0_16er enable rising edge interrupt for p0[16]. see bit 0 description. 0 17 p0_17er enable rising edge interrupt for p0[17]. see bit 0 description. 0 18 p0_18er enable rising edge interrupt for p0[18]. see bit 0 description. 0 19 p0_19er enable rising edge interrupt for p0[19]. see bit 0 description. 0 20 p0_20er enable rising edge interrupt for p0[20]. see bit 0 description. 0 21 p0_21er enable rising edge interrupt for p0[21]. see bit 0 description. 0 22 p0_22er enable rising edge interrupt for p0[22]. see bit 0 description. 0 23 p0_23er enable rising edge interrupt for p0[23]. see bit 0 description. 0 24 p0_24er enable rising edge interrupt for p0[24]. see bit 0 description. 0 25 p0_25er enable rising edge interrupt for p0[25]. see bit 0 description. 0 26 p0_26er enable rising edge interrupt for p0[26]. see bit 0 description. 0 27 p0_27er enable rising edge interrupt for p0[27]. see bit 0 description. 0 28 p0_28er enable rising edge interrupt for p0[28]. see bit 0 description. 0 29 p0_29er enable rising edge interrupt for p0[29]. see bit 0 description. 0 30 p0_30er enable rising edge interrupt for p0[30]. see bit 0 description. 0 31 p0_31er enable rising edge interrupt for p0[31]. see bit 0 description. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 154 of 942 nxp semiconductors UM10562 chapter 8: lpc408x/407x gpio 8.5.2.6 gpio interrupt enable for port 0 falling edge each bit in these read-wri te registers enables the fa lling edge interrupt for the corresponding gpio port 0 pin. table 105. gpio interrupt enable for port 0 falling edge (enf0 - address 0x4002 8094) bit description bit symbol description reset value 0 p0_0ef enable falling edge interrupt for p0[0]. 0 = disable falling edge interrupt. 1 = enable falling edge interrupt. 0 1 p0_1ef enable falling edge interrupt for p0[1]. see bit 0 description. 0 2 p0_2ef enable falling edge interrupt for p0[2]. see bit 0 description. 0 3 p0_3ef enable falling edge interrupt for p0[3]. see bit 0 description. 0 4 p0_4ef enable falling edge interrupt for p0[4]. see bit 0 description. 0 5 p0_5ef enable falling edge interrupt for p0[5]. see bit 0 description. 0 6 p0_6ef enable falling edge interrupt for p0[6]. see bit 0 description. 0 7 p0_7ef enable falling edge interrupt for p0[7]. see bit 0 description. 0 8 p0_8ef enable falling edge interrupt for p0[8]. see bit 0 description. 0 9 p0_9ef enable falling edge interrupt for p0[9]. see bit 0 description. 0 10 p0_10ef enable falling edge interrupt for p0[10]. see bit 0 description. 0 11 p0_11ef enable falling edge interrupt for p0[11]. see bit 0 description. 0 12 p0_12ef enable falling edge interrupt for p0[12]. see bit 0 description. 0 13 p0_13ef enable falling edge interrupt for p0[13]. see bit 0 description. 0 14 p0_14ef enable falling edge interrupt for p0[14]. see bit 0 description. 0 15 p0_15ef enable falling edge interrupt for p0[15]. see bit 0 description. 0 16 p0_16ef enable falling edge interrupt for p0[16]. see bit 0 description. 0 17 p0_17ef enable falling edge interrupt for p0[17]. see bit 0 description. 0 18 p0_18ef enable falling edge interrupt for p0[18]. see bit 0 description. 0 19 p0_19ef enable falling edge interrupt for p0[19]. see bit 0 description. 0 20 p0_20ef enable falling edge interrupt for p0[20]. see bit 0 description. 0 21 p0_21ef enable falling edge interrupt for p0[21]. see bit 0 description. 0 22 p0_22ef enable falling edge interrupt for p0[22]. see bit 0 description. 0 23 p0_23ef enable falling edge interrupt for p0[23]. see bit 0 description. 0 24 p0_24ef enable falling edge interrupt for p0[24]. see bit 0 description. 0 25 p0_25ef enable falling edge interrupt for p0[25]. see bit 0 description. 0 26 p0_26ef enable falling edge interrupt for p0[26]. see bit 0 description. 0 27 p0_27ef enable falling edge interrupt for p0[27]. see bit 0 description. 0 28 p0_28ef enable falling edge interrupt for p0[28]. see bit 0 description. 0 29 p0_29ef enable falling edge interrupt for p0[29]. see bit 0 description. 0 30 p0_30ef enable falling edge interrupt for p0[30]. see bit 0 description. 0 31 p0_31ef enable falling edge interrupt for p0[31]. see bit 0 description. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 155 of 942 nxp semiconductors UM10562 chapter 8: lpc408x/407x gpio 8.5.2.7 gpio interrupt status for port 2 rising edge interrupt each bit in these read-only registers indicates the rising edge interrupt status for port 2. table 106. gpio interrupt status for port 2 rising edge interrupt (statr2 - 0x4002 80a4) bit description bit symbol description reset value 0 p2_0rei status of rising edge interrupt for p2[0]. 0 = no rising edge detected. 1 = rising edge interrupt generated. 0 1 p2_1rei status of rising edge interrupt for p2[1]. see bit 0 description. 0 2 p2_2rei status of rising edge interrupt for p2[2]. see bit 0 description. 0 3 p2_3rei status of rising edge interrupt for p2[3]. see bit 0 description. 0 4 p2_4rei status of rising edge interrupt for p2[4]. see bit 0 description. 0 5 p2_5rei status of rising edge interrupt for p2[5]. see bit 0 description. 0 6 p2_6rei status of rising edge interrupt for p2[6]. see bit 0 description. 0 7 p2_7rei status of rising edge interrupt for p2[7]. see bit 0 description. 0 8 p2_8rei status of rising edge interrupt for p2[8]. see bit 0 description. 0 9 p2_9rei status of rising edge interrupt for p2[9]. see bit 0 description. 0 10 p2_10rei status of rising edge interrupt for p2[10]. see bit 0 description. 0 11 p2_11rei status of rising edge interrupt for p2[11]. see bit 0 description. 0 12 p2_12rei status of rising edge interrupt for p2[12]. see bit 0 description. 0 13 p2_13rei status of rising edge interrupt for p2[13]. see bit 0 description. 0 14 p2_14rei status of rising edge interrupt for p2[14]. see bit 0 description. 0 15 p2_15rei status of rising edge interrupt for p2[15]. see bit 0 description. 0 16 p2_16rei status of rising edge interrupt for p2[16]. see bit 0 description. 0 17 p2_17rei status of rising edge interrupt for p2[17]. see bit 0 description. 0 18 p2_18rei status of rising edge interrupt for p2[18]. see bit 0 description. 0 19 p2_19rei status of rising edge interrupt for p2[19]. see bit 0 description. 0 20 p2_20rei status of rising edge interrupt for p2[20]. see bit 0 description. 0 21 p2_21rei status of rising edge interrupt for p2[21]. see bit 0 description. 0 22 p2_22rei status of rising edge interrupt for p2[22]. see bit 0 description. 0 23 p2_23rei status of rising edge interrupt for p2[23]. see bit 0 description. 0 24 p2_24rei status of rising edge interrupt for p2[24]. see bit 0 description. 0 25 p2_25rei status of rising edge interrupt for p2[25]. see bit 0 description. 0 26 p2_26rei status of rising edge interrupt for p2[26]. see bit 0 description. 0 27 p2_27rei status of rising edge interrupt for p2[27]. see bit 0 description. 0 28 p2_28rei status of rising edge interrupt for p2[28]. see bit 0 description. 0 29 p2_29rei status of rising edge interrupt for p2[29]. see bit 0 description. 0 30 p2_30rei status of rising edge interrupt for p2[30]. see bit 0 description. 0 31 p2_31rei status of rising edge interrupt for p2[31]. see bit 0 description. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 156 of 942 nxp semiconductors UM10562 chapter 8: lpc408x/407x gpio 8.5.2.8 gpio interrupt status for port 2 falling edge interrupt each bit in these read-only re gisters indicates the falling ed ge interrupt status for port 2. table 107. gpio interrupt status for port 2 falling edge interrupt (statf2 - 0x4002 80a8) bit description bit symbol description reset value 0 p2_0fei status of falling edge interrupt for p2[0]. 0 = no falling edge detected. 1 = falling edge interrupt generated. 0 1 p2_1fei status of falling edge interrupt for p2[1]. see bit 0 description. 0 2 p2_2fei status of falling edge interrupt for p2[2]. see bit 0 description. 0 3 p2_3fei status of falling edge interrupt for p2[3]. see bit 0 description. 0 4 p2_4fei status of falling edge interrupt for p2[4]. see bit 0 description. 0 5 p2_5fei status of falling edge interrupt for p2[5]. see bit 0 description. 0 6 p2_6fei status of falling edge interrupt for p2[6]. see bit 0 description. 0 7 p2_7fei status of falling edge interrupt for p2[7]. see bit 0 description. 0 8 p2_8fei status of falling edge interrupt for p2[8]. see bit 0 description. 0 9 p2_9fei status of falling edge interrupt for p2[9]. see bit 0 description. 0 10 p2_10fei status of falling edge interrupt for p2[10]. see bit 0 description. 0 11 p2_11fei status of falling edge interrupt for p2[11]. see bit 0 description. 0 12 p2_12fei status of falling edge interrupt for p2[12]. see bit 0 description. 0 13 p2_13fei status of falling edge interrupt for p2[13]. see bit 0 description. 0 14 p2_14fei status of falling edge interrupt for p2[14]. see bit 0 description. 0 15 p2_15fei status of falling edge interrupt for p2[15]. see bit 0 description. 0 16 p2_16fei status of falling edge interrupt for p2[16]. see bit 0 description. 0 17 p2_17fei status of falling edge interrupt for p2[17]. see bit 0 description. 0 18 p2_18fei status of falling edge interrupt for p2[18]. see bit 0 description. 0 19 p2_19fei status of falling edge interrupt for p2[19]. see bit 0 description. 0 20 p2_20fei status of falling edge interrupt for p2[20]. see bit 0 description. 0 21 p2_21fei status of falling edge interrupt for p2[21]. see bit 0 description. 0 22 p2_22fei status of falling edge interrupt for p2[22]. see bit 0 description. 0 23 p2_23fei status of falling edge interrupt for p2[23]. see bit 0 description. 0 24 p2_24fei status of falling edge interrupt for p2[24]. see bit 0 description. 0 25 p2_25fei status of falling edge interrupt for p2[25]. see bit 0 description. 0 26 p2_26fei status of falling edge interrupt for p2[26]. see bit 0 description. 0 27 p2_27fei status of falling edge interrupt for p2[27]. see bit 0 description. 0 28 p2_28fei status of falling edge interrupt for p2[28]. see bit 0 description. 0 29 p2_29fei status of falling edge interrupt for p2[29]. see bit 0 description. 0 30 p2_30fei status of falling edge interrupt for p2[30]. see bit 0 description. 0 31 p2_31fei status of falling edge interrupt for p2[31]. see bit 0 description. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 157 of 942 nxp semiconductors UM10562 chapter 8: lpc408x/407x gpio 8.5.2.9 gpio interrupt clear register for port 2 writing a 1 into a bit in this write-only register clears any interrupts for the corresponding port 2 pin. table 108. gpio interrupt clear register for port 0 (clr2 - 0x4002 80ac) bit description bit symbol description 0 p2_0ci clear gpio port interrupts for p2[0]. 0 = no effect. 1 = clear corresponding bits in ionintstatr and ionstatf. 1 p2_1ci clear gpio port interrupts for p2[1]. see bit 0 description. 2 p2_2ci clear gpio port interrupts for p2[2]. see bit 0 description. 3 p2_3ci clear gpio port interrupts for p2[3]. see bit 0 description. 4 p2_4ci clear gpio port interrupts for p2[4]. see bit 0 description. 5 p2_5ci clear gpio port interrupts for p2[5]. see bit 0 description. 6 p2_6ci clear gpio port interrupts for p2[6]. see bit 0 description. 7 p2_7ci clear gpio port interrupts for p2[7]. see bit 0 description. 8 p2_8ci clear gpio port interrupts for p2[8]. see bit 0 description. 9 p2_9ci clear gpio port interrupts for p2[9]. see bit 0 description. 10 p2_10ci clear gpio port interrupts for p2[10]. see bit 0 description. 11 p2_11ci clear gpio port interrupts for p2[11]. see bit 0 description. 12 p2_12ci clear gpio port interrupts for p2[12]. see bit 0 description. 13 p2_13ci clear gpio port interrupts for p2[13]. see bit 0 description. 14 p2_14ci clear gpio port interrupts for p2[14]. see bit 0 description. 15 p2_15ci clear gpio port interrupts for p2[15]. see bit 0 description. 16 p2_16ci clear gpio port interrupts for p2[16]. see bit 0 description. 17 p2_17ci clear gpio port interrupts for p2[17]. see bit 0 description. 18 p2_18ci clear gpio port interrupts for p2[18]. see bit 0 description. 19 p2_19ci clear gpio port interrupts for p2[19]. see bit 0 description. 20 p2_20ci clear gpio port interrupts for p2[20]. see bit 0 description. 21 p2_21ci clear gpio port interrupts for p2[21]. see bit 0 description. 22 p2_22ci clear gpio port interrupts for p2[22]. see bit 0 description. 23 p2_23ci clear gpio port interrupts for p2[23]. see bit 0 description. 24 p2_24ci clear gpio port interrupts for p2[24]. see bit 0 description. 25 p2_25ci clear gpio port interrupts for p2[25]. see bit 0 description. 26 p2_26ci clear gpio port interrupts for p2[26]. see bit 0 description. 27 p2_27ci clear gpio port interrupts for p2[27]. see bit 0 description. 28 p2_28ci clear gpio port interrupts for p2[28]. see bit 0 description. 29 p2_29ci clear gpio port interrupts for p2[29]. see bit 0 description. 30 p2_30ci clear gpio port interrupts for p2[30]. see bit 0 description. 31 p2_31ci clear gpio port interrupts for p2[31]. see bit 0 description.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 158 of 942 nxp semiconductors UM10562 chapter 8: lpc408x/407x gpio 8.5.2.10 gpio interrupt enable for port 2 rising edge each bit in these read-write registers enables the rising edge interrupt for the corresponding port 2 pin. which pins are available depends on the part number and package combination. see the specific device data sheet for details. table 109. gpio interrupt enable for port 2 rising edge (enr2 - 0x4002 80b0) bit description bit symbol description reset value 0 p2_0er enable rising edge interrupt for p2[0]. 0 = disable rising edge interrupt. 1 = enable rising edge interrupt. 0 1 p2_1er enable rising edge interrupt for p2[1]. see bit 0 description. 0 2 p2_2er enable rising edge interrupt for p2[2]. see bit 0 description. 0 3 p2_3er enable rising edge interrupt for p2[3]. see bit 0 description. 0 4 p2_4er enable rising edge interrupt for p2[4]. see bit 0 description. 0 5 p2_5er enable rising edge interrupt for p2[5]. see bit 0 description. 0 6 p2_6er enable rising edge interrupt for p2[6]. see bit 0 description. 0 7 p2_7er enable rising edge interrupt for p2[7]. see bit 0 description. 0 8 p2_8er enable rising edge interrupt for p2[8]. see bit 0 description. 0 9 p2_9er enable rising edge interrupt for p2[9]. see bit 0 description. 0 10 p2_10er enable rising edge interrupt for p2[10]. see bit 0 description. 0 11 p2_11er enable rising edge interrupt for p2[11]. see bit 0 description. 0 12 p2_12er enable rising edge interrupt for p2[12]. see bit 0 description. 0 13 p2_13er enable rising edge interrupt for p2[13]. see bit 0 description. 0 14 p2_14er enable rising edge interrupt for p2[14]. see bit 0 description. 0 15 p2_15er enable rising edge interrupt for p2[15]. see bit 0 description. 0 16 p2_16er enable rising edge interrupt for p2[16]. see bit 0 description. 0 17 p2_17er enable rising edge interrupt for p2[17]. see bit 0 description. 0 18 p2_18er enable rising edge interrupt for p2[18]. see bit 0 description. 0 19 p2_19er enable rising edge interrupt for p2[19]. see bit 0 description. 0 20 p2_20er enable rising edge interrupt for p2[20]. see bit 0 description. 0 21 p2_21er enable rising edge interrupt for p2[21]. see bit 0 description. 0 22 p2_22er enable rising edge interrupt for p2[22]. see bit 0 description. 0 23 p2_23er enable rising edge interrupt for p2[23]. see bit 0 description. 0 24 p2_24er enable rising edge interrupt for p2[24]. see bit 0 description. 0 25 p2_25er enable rising edge interrupt for p2[25]. see bit 0 description. 0 26 p2_26er enable rising edge interrupt for p2[26]. see bit 0 description. 0 27 p2_27er enable rising edge interrupt for p2[27]. see bit 0 description. 0 28 p2_28er enable rising edge interrupt for p2[28]. see bit 0 description. 0 29 p2_29er enable rising edge interrupt for p2[29]. see bit 0 description. 0 30 p2_30er enable rising edge interrupt for p2[30]. see bit 0 description. 0 31 p2_31er enable rising edge interrupt for p2[31]. see bit 0 description. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 159 of 942 nxp semiconductors UM10562 chapter 8: lpc408x/407x gpio 8.5.2.11 gpio interrupt enable for port 2 falling edge each bit in these read-wri te registers enables the fa lling edge interrupt for the corresponding gpio port 2 pin. table 110. gpio interrupt enable for port 2 falling edge (enf2 - 0x4002 80b4) bit description bit symbol description reset value 0 p2_0ef enable falling edge interrupt for p2[0]. 0 = disable falling edge interrupt. 1 = enable falling edge interrupt. 0 1 p2_1ef enable falling edge interrupt for p2[1]. see bit 0 description. 0 2 p2_2ef enable falling edge interrupt for p2[2]. see bit 0 description. 0 3 p2_3ef enable falling edge interrupt for p2[3]. see bit 0 description. 0 4 p2_4ef enable falling edge interrupt for p2[4]. see bit 0 description. 0 5 p2_5ef enable falling edge interrupt for p2[5]. see bit 0 description. 0 6 p2_6ef enable falling edge interrupt for p2[6]. see bit 0 description. 0 7 p2_7ef enable falling edge interrupt for p2[7]. see bit 0 description. 0 8 p2_8ef enable falling edge interrupt for p2[8]. see bit 0 description. 0 9 p2_9ef enable falling edge interrupt for p2[9]. see bit 0 description. 0 10 p2_10ef enable falling edge interrupt for p2[10]. see bit 0 description. 0 11 p2_11ef enable falling edge interrupt for p2[11]. see bit 0 description. 0 12 p2_12ef enable falling edge interrupt for p2[12]. see bit 0 description. 0 13 p2_13ef enable falling edge interrupt for p2[13]. see bit 0 description. 0 14 p2_14ef enable falling edge interrupt for p2[14]. see bit 0 description. 0 15 p2_15ef enable falling edge interrupt for p2[15]. see bit 0 description. 0 16 p2_16ef enable falling edge interrupt for p2[16]. see bit 0 description. 0 17 p2_17ef enable falling edge interrupt for p2[17]. see bit 0 description. 0 18 p2_18ef enable falling edge interrupt for p2[18]. see bit 0 description. 0 19 p2_19ef enable falling edge interrupt for p2[19]. see bit 0 description. 0 20 p2_20ef enable falling edge interrupt for p2[20]. see bit 0 description. 0 21 p2_21ef enable falling edge interrupt for p2[21]. see bit 0 description. 0 22 p2_22ef enable falling edge interrupt for p2[22]. see bit 0 description. 0 23 p2_23ef enable falling edge interrupt for p2[23]. see bit 0 description. 0 24 p2_24ef enable falling edge interrupt for p2[24]. see bit 0 description. 0 25 p2_25ef enable falling edge interrupt for p2[25]. see bit 0 description. 0 26 p2_26ef enable falling edge interrupt for p2[26]. see bit 0 description. 0 27 p2_27ef enable falling edge interrupt for p2[27]. see bit 0 description. 0 28 p2_28ef enable falling edge interrupt for p2[28]. see bit 0 description. 0 29 p2_29ef enable falling edge interrupt for p2[29]. see bit 0 description. 0 30 p2_30ef enable falling edge interrupt for p2[30]. see bit 0 description. 0 31 p2_31ef enable falling edge interrupt for p2[31]. see bit 0 description. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 160 of 942 nxp semiconductors UM10562 chapter 8: lpc408x/407x gpio 8.6 gpio usage notes 8.6.1 example: an instantaneous out put of 0s and 1s on a gpio port solution 1: using 32-bit (word) access ible fast gpio registers fio0mask = 0xffff00ff ; fio0pin = 0x0000a500; solution 2: using 16-bit (half-word) accessible fast gpio registers fio0maskl = 0x00ff; fio0pinl = 0xa500; solution 3: using 8-bit (byte) accessible fast gpio registers fio0pin1 = 0xa5; 8.6.2 writing to fioset/fioclr vs. fiopin writing to the fioset/fioclr registers allow a program to easily change a port?s output pin(s) to both high and low levels at the same time. when fioset or fioclr are used, only pin/bit(s) written with 1 will be change d, while those writte n as 0 will remain unaffected. writing to the fiopin register enables instantaneous output of a desired value on the parallel gpio. data written to the fiopin regist er will affect all pins configured as outputs on that port: zeroes in the value will produce low level pin outputs and ones in the value will produce high level pin outputs. a subset of a port?s pins may be changed by using the fiomask register to define which pins are affected. fiomask is set up to contai n zeroes in bits corresponding to pins that will be changed, and ones for all others. solution 2 from section 8.6.1 above illustrates output of 0xa5 on port0 pins 15 to 8 while preserving all other port0 output pins as they were before.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 161 of 942 9.1 how to read this chapter this chapter describes the external memory controller for devices that support external memory. emc configurations vary with diff erent packages for devices that support external memory, see table 111 . [1] in addition to the registers that are common to all emc operations: emccontrol and emcconfig. UM10562 chapter 9: lpc408x/407x extern al memory controller (emc) rev. 1 ? 13 september 2012 user manual table 111. emc configuration device package data bus widths supported pins available dynamic memory configuration registers [1] [2] static memory configuration registers [1] [3] external memory connections 144-pin 8-bit emc_a[15:0] emc_d[7:0] emc_oe emc_we emc_cs1:0 emcstaticconfig1/0 emcstaticwaitwen1/0 emcstaticwaitoen1/0 emcstaticwaitrd1/0 emcstaticwaitpage1/0 emcstaticwaitwr1/0 emcstaticwaitturn1/0 section 9.14.3 180-pin 16-bit, 8-bit emc_a[19:0] emc_d[15:0] emc_oe emc_we emc_bls1:0 emc_cs1:0 emc_dycs1:0 emc_cas emc_ras emc_clk1:0 emc_cke1:0 emc_dqm1:0 emcdynamicconfig1/0 emcdynamicrascas1/0 emcstaticconfig1/0 emcstaticwaitwen1/0 emcstaticwaitoen1/0 emcstaticwaitrd1/0 emcstaticwaitpage1/0 emcstaticwaitwr1/0 emcstaticwaitturn1/0 section 9.14.2 section 9.14.3 208-pin 32-bit, 16-bit, 8-bit emc_a[25:0] emc_d[31:0] emc_oe emc_we emc_bls3:0 emc_cs3:0 emc_dycs3:0 emc_cas emc_ras emc_clk1:0 emc_cke3:0 emc_dqm3:0 emcdynamicconfig3/2/1/0 emcdynamicrascas3/2/1/0 emcstaticconfig3/2/1/0 emcstaticwaitwen3/2/1/0 emcstaticwaitoen3/2/1/0 emcstaticwaitrd3/2/1/0 emcstaticwaitpage3/2/1/0 emcstaticwaitwr3/2/1/0 emcstaticwaitturn3/2/1/0 section 9.14.1 section 9.14.2 section 9.14.3
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 162 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x extern al memory controller (emc) [2] in addition to the registers that are common to a ll emc dynamic chip selects: emcdynamiccontrol, emcdynamicrefresh, emcdynamicreadconf ig, emcdynamicrp, emcdynamicras, emcdynamicsrex, emcdynamicapr, emcdynam icdal, emcdynamicwr, emcdynamicrc, emcdynamicrfc, emcdynamicxsr, emcdynamicrrd, and emcdynamicmrd [3] in addition to the emcstaticextendedwait register which applies to all static chip selects. 9.2 basic configuration the emc is configured using the following registers: 1. power: in the pconp register ( section 3.3.2.2 ), set bit pcemc. remark: the emc is enabled on reset (pcemc = 1). on por and warm reset, the emc is enabled as well, see table 115 and table 118 . 2. clock: the emc clock can be the same as the cpu clock (the default), or half that. the lower rate is intended to be used primarily when the cpu is running faster than the external bus can support. clock selection for the emc is described in section 3.3.3.1 . 3. pins: select emc pins and pin modes through the relevant iocon registers ( section 7.4.1 ). 4. configuration: see ta b l e 11 5 to table 118 . also see additional emc configurations in section 3.3.7.1 ? system controls and status register ? . in particular make sure that the address shift mode is configured correctly for the application hardware. 5. mpu: default memory space permissions for the cpu do not allow program execution from the address range that includes the dynamic memory chip selects. these permissions can be changed by programming the mpu (see the arm cortex-m4 user guide refe rred to in section 40.1 for details of mpu operation. 6. to set the emc delay clock see the emc del ay clock register in the system control block (see section 3.3.6.1 ). 7. to calibrate the emc clock, see section 3.3.6.2 . 9.3 introduction the external memory controller (emc) is an arm primecell? multiport memory controller peripheral offering support for as ynchronous static memory devices such as ram, rom and flash, as well as dynamic memories such as single data rate sdram. the emc is an advanced microcontroller bus ar chitecture (amba) compliant peripheral.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 163 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x extern al memory controller (emc) 9.4 features ? static chip selects each support up to 64 mb of data. by enabling the address shift mode, static chip select 0 can support up to 256 mb, and static chip select 1 can support up to 128 mb (see scs register bit 0 ( section 3.3.7.1 ) ? dynamic chip selects each supp ort up to 256 mb of data. ? dynamic memory interface support in cluding single data rate sdram. ? asynchronous static memory device support including ram, rom, and flash, with or without asynchronous page mode. ? low transaction latency. ? read and write buffers to reduce la tency and to improve performance. ? 8-bit, 16-bit, and 32-bit wide static memory support. ? 16-bit and 32-bit wide chip select sdram memory support. ? static memory features include: ? asynchronous page mode read ? programmable wait states ? bus turnaround delay ? output enable and write enable delays ? extended wait ? four chip selects for synchro nous memory and four chip selects for static memory devices. ? power-saving modes dynamically co ntrol cke and clkout to sdrams. ? dynamic memory self-refresh mode controlled by software. ? controller supports 2 kbit, 4 kbit, and 8 kbit row address synchronous memory parts. that is typical 512 mbit, 256 mbit, and 128 mbit parts, with 4, 8, 16, or 32 data bits per device. ? separate reset domains allow the for auto-r efresh through a chip reset if desired. ? programmable delay elements allow fine-tuning emc timing. note: synchronous static memory devices ( synchronous burst mode) are not supported.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 164 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x extern al memory controller (emc) 9.5 emc functional description figure 16 shows a block diagram of the emc. the functions of the emc blocks are described in the following sections: ? ahb slave register interface. ? ahb slave memory interfaces. ? data buffers. ? memory controller state machine. ? pad interface. note: for 32 bit wide chip selects data is tr ansferred to and from dynamic memory in sdram bursts of four. for 16 bit wide chip selects sdram bursts of eight are used. fig 16. emc block diagram programmable delay pad interface ahb bus 120524 emc_d[31:0] emc_a[25:0] emc_we emc_oe emc_bls3:0 emc_cke3:0 emc_dqm3:0 programmable delay memory controller state machine data buffers (4 x 16 word) shared signals static memory signals dynamic memory signals emc_cs3:0 emc_dycs3:0 emc_cas emc_ras fbclkin ahb slave memory interface ahb slave register interface programmable delay emcdlyctl[4:0] emcdlyctl[28:24] emcdlyctl[20:16] emcdlyctl[12:8] programmable delay emcclkdelay emcclk hclk emc_clkout0 emc_clkout1
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 165 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x extern al memory controller (emc) 9.5.1 ahb slave register interface the ahb slave register interface block enables the registers of the emc to be programmed. this module also contains most of the registers and performs the majority of the register address decoding. to eliminate the possibility of endianness prob lems, all data transf ers to and from the registers of the emc must be 32 bits wide. note: if an access is attempted with a size other than a word (32 bits), it causes an error response to the ahb bus and the transfer is terminated. 9.5.2 ahb slave memory interface the ahb slave memory interface allo ws access to external memories. 9.5.2.1 memory transaction endianness the endianness of the data transfers to and fr om the external memories is determined by the endian mode (n) bit in the emcconfig register. note: the memory controller must be idle (see the busy field of the emcstatus register) before endianness is changed, so that the data is transferred correctly. 9.5.2.2 memory transaction size memory transactions can be 8, 16, or 32 bits wide. any access attempted with a size greater than a word (32 bits) causes an e rror response to the ahb bus and the transfer is terminated. 9.5.2.3 write protected memory areas write transactions to write-protected memory areas generate an error response to the ahb bus and the transfer is terminated. 9.5.3 pad interface the pad interface block provides the interf ace to the pads. the pad interface uses a feedback clock, fbclkin, from the clkout0 output of the emc to resynchronize sdram read data from the off-chip to on-chip domains. 9.5.4 data buffers the ahb interface reads and writes via buffers to improve memory bandwidth and reduce transaction latency. the emc contains four 16-word buffers. the buffers can be used as read buffers, write buffers, or a combination of both. the buffers are allocated automatically. the buffers must be disabled during sdram initialization. the buffers must be enabled during normal operation. the buffers can be enabled or disabled fo r static memory using the emcstaticconfig registers. 9.5.4.1 write buffers write buffers are used to:
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 166 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x extern al memory controller (emc) ? merge write transactions so that the number of external transactions are minimized. buffer data until the emc can complete the write transaction, improving ahb write latency. convert all dynamic memory write transactions into quadword bursts on the external memory interface. this enhances tran sfer efficiency for dynamic memory. ? reduce external memory traffic. this improves memory bandwidth and reduces power consumption. write buffer operation: ? if the buffers are enabled, an ahb write operation writes into the least recently used (lru) buffer, if empty. if the lru buffer is not empty, the contents of the buffer are flushed to memory to make space for the ahb write data. ? if a buffer contains write data it is marked as dirty, and its contents are written to memory before the buffer can be reallocated. the write buffers are flushed whenever: ? the memory controller state machine is not busy performing accesses to external memory. the memory controller state machine is not busy performing accesses to external memory, and an ahb interface is writing to a different buffer. note: for dynamic memory, the sm allest buffer flush is a quadword of data. for static memory, the smallest buffer flush is a byte of data. 9.5.4.2 read buffers read buffers are used to: ? buffer read requests from memory. future re ad requests that hit the buffer read the data from the buffer rather than memory, reducing transaction latency. convert all read transactions into quadword bursts on the external memory interface. this enhances transfer efficiency for dynamic memory. ? reduce external memory traffic. this improves memory bandwidth and reduces power consumption. read buffer operation: ? if the buffers are enabled and the read data is contained in one of the buffers, the read data is provided directly from the buffer. ? if the read data is not contained in a buffer, the lru buffer is selected. if the buffer is dirty (contains write data), the write data is flushed to memory. when an empty buffer is available the read command is posted to the memory. a buffer filled by performing a r ead from memory is marked as not-dirty (not containing write data) and its contents are not flushed back to the memory controller unless a subsequent ahb transfer performs a write that hits the buffer.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 167 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x extern al memory controller (emc) 9.5.5 memory controller state machine the memory controller state machine comprises a static memory controller and a dynamic memory controller. 9.5.6 timing control with pr ogrammable delay elements programmable delay elements are provided to allow fine-tuning the timing of various aspects of emc operation in connection with sdram memory. ? for the clock delayed operating mode, separate programmable delays are provided for each potential clock output, clkout0 and clkout1. ? for the command delayed operating mode, a programmable delay is provided to control delay of all command outputs. ? for both operating modes, a programmable delay is provided to control the time at which input data from sdram memory is sampled. the locations of the programmable delays are shown in the emc overall block diagram ( figure 16 ). see descriptions of the emcdlyctl and emccal registers for more information.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 168 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x extern al memory controller (emc) 9.6 low-power operation in many systems, the contents of the me mory system have to be maintained during low-power sleep modes. the emc provides a mechanism to place the dynamic memories into self-refresh mode. self-refresh mode can be entered by soft ware by setting the srefreq bit in the emcdynamiccontrol register and polling the srefack bit in the emcstatus register. any transactions to memory that are generated while the memory controller is in self-refresh mode are rejected and an error response is generated to the ahb bus. clearing the srefreq bit in the emcdynamiccontrol register returns the memory to normal operation. see the memory data sheet for refresh requirements. note: the static memory can be accessed as normal when the sdram memory is in self-refresh mode. 9.6.1 low-power sdra m deep-sleep mode the emc supports jedec low-power sdram deep-sleep mode. deep-sleep mode can be entered by setting the deep-sleep mode (dp) bit, the dynamic memory clock enable bit (ce), and the dynamic clock control bit (cs) in the emcdynamiccontrol register. the device is then put into a low-power mode where the device is powered down and no longer refreshed. all data in the memory is lost. 9.6.2 low-power sdram partial array refresh the emc supports jedec low-power sdram part ial array refresh. partial array refresh can be programmed by initializing the sdram memory device appropriately. when the memory device is put into self-refresh mode only the memory banks specified are refreshed. the memory banks that are not refreshed lose their data contents.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 169 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x extern al memory controller (emc) 9.7 memory bank select eight independently-configurable memory chip selects are supported: ? pins emc_cs3 to emc_cs0 are used to select static memory devices. ? pins emc_dycs3 to emc_dycs0 are used to select dynamic memory devices. static memory chip select ranges are each 64 megabytes in size, while dynamic memory chip selects cover a range of 256 megabytes each. table 112 shows the address ranges of the chip selects. 9.8 emc reset the emc receives two reset signals. one is power-on reset (por), asserted when chip power is applied, and when a brown-out condition is detected (see the system control block chapter for details of br own-out detect). the other reset is from the external reset pin and the watchdog timer. a configuration bit in the scs register, called emc_reset_disable, allows control of how the emc is reset (see section 3.3.7.1 ? system controls and status register ? ). the default configuration (emc_reset_disabl e = 0) is that both emc resets are asserted when any type of reset event occurs. in this mode, all registers and functions of the emc are initialized upon any reset condition. if emc_reset_disable is set to 1, many portio ns of the emc are only reset by a power-on or brown-out event, in order to allow the emc to retain its state through a warm reset (external reset or watchdog reset). if the emc is configured correctly, auto-refresh can be maintained through a warm reset. table 112. memory bank selection chip select pin address range memory type size of range emc_cs0 0x8000 0000 - 0x83ff ffff static 64 mb emc_ cs1 0x9000 0000 - 0x93ff ffff static 64 mb emc_ cs2 0x9800 0000 - 0x9bff ffff static 64 mb emc_ cs3 0x9c00 0000 - 0x9fff ffff static 64 mb emc_ dycs0 0xa000 0000 - 0xafff ffff dynamic 256 mb emc_ dycs1 0xb000 0000 - 0xbfff ffff dynamic 256 mb emc_ dycs2 0xc000 0000 - 0xcfff ffff dynamic 256 mb emc_ dycs3 0xd000 0000 - 0xdfff ffff dynamic 256 mb
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 170 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x extern al memory controller (emc) 9.9 address shift mode the emc supports an optional address shift mode for static memories that can simplify board design and potentially increase external memory addressing range in some cases. the latter cases are described in footnotes of ta b l e 3 ? memory usage and details ? in the memory map chapter of this manual. address shift mode is controlled by a configuration bit in the scs register, called emc shift control (see section 3.3.7.1 ? system controls and status register ? ). when the address shift mode is not activated (the emc shift control bit in the scs register = 1), static memory addresses are outp ut as byte addresses. this means that for memories wider than a byte, one or two addr ess lines are not used, and that address connections to memory devices must be shifted in the board design. for example, if a 32-bit wide memory system is connected, the lowest line address of the memory device(s) would be connected to emc address line 2, skipping bits 0 and 1. when the address shift mode is activated (the emc shift control bit in the scs register = 0), static memory addresses are shifted to match the lowest address bit needed for bus width. in this case, the lowest address lin e of the memory device(s) is always to emc address line 0. 9.10 memory mapped i/o and burst disable by default, the emc uses buffering to obtain better external memory access performance. however, in the case of memory mapped i/o devices, the read-ahead operations that occur due to the buffering can cause issues with some such devices. this could be from a change of status in one register caused by reading another register, or could simply cause an unplanned read of a data fifo when another register in the device is read intentionally. to prevent this issue, the use of buffering to read ahead of actual cpu memory read requests can be disabled. the configuration bit that controls this function is called emc burst control, and is found in the scs register (see section 3.3.7.1 ? system controls and status register ? ).
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 171 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x extern al memory controller (emc) 9.11 using the emc with sdram 9.11.1 mode register setup when using the emc with sdram, the sdram devices must be configured appropriately for the emc. this includes setting up t he sdrams for a 128-bit sequential burst. the burst configuration is done through a mode register in the sdram memory. figure 17 shows the layout for a jedec standard sdram mode register. fig 17. sdram mode register a10 a11 a9a8a7a6a5a4a3a2a1a0 burst length m2 m1 m0 m3=0 m3=1 000 1 1 001 2 2 010 4 4 011 8 8 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 full page reserved burst type m3 type 0 sequenctial 1 interleaved cas latency m6 m5 m4 cas latency 000 reserved 001 reserved 010 2 011 3 100 reserved 101 reserved 110 reserved 111 reserved operating mode m8 m7 m6-m0 mode 0 0 defined standard operation - - - others reserved write burst mode m9 mode 0 programmed burst length 1 single location access reserved - address bus 120515 bl cl bt opmode - mode register wb
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 172 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) the mode register is loaded by first se nding the ?set mode? command to the sdram using the dynamiccontrol register?s sdra m initialization bits to send a mode command, and then reading the sdram at an address that is partially formed from the new mode register value. the actual value loaded into the mode register is taken by the sdram from the address lines of the emc wh ile they are sending the row address during the read. example to determine the address to read from to l oad the mode register, the portion of the emc address bits that map to the ro w address must be id entified. in this ex ample, we will use: ? a single 8m by 16-bit external sdram chip in row, bank, column mode on cs0 ? cas latency of 2 since the emc uses bursts of 8 for a 16-bit external memory, we need to load the mode register with a burst length of 8 (8 x 16 bits memory width = 128 bits). the mode register configuration needed is 0x023. to load the mode register, we need to do a read from the address constructed as follows: information needed: ? base address for dynamic ch ip select 0, found in ta b l e 3 . for this device, the address is 0xa000 0000. ? mode register value, based on information from both the sdram data sheet, as in figure 17 , and the emc. in this example, the value will be 0x23. this represents a programmed burst length, cas latency of 2, sequential burst type, and a burst length of 8, as described in section 9.5 . ? bank bits and column bits, look up in table 134 . in this example, it is 4 banks and 9 column bits. ? bus width, defined in this example to be 16 bits. the mode register value calculation is: base address + (mode register value << (bank bits + column bits + bus width/16) the shift operation aligns the mode register value with the row address bits. in this example: 0xa000 0000 + (0x23 << (2 + 9 + 1)) = 0xa000 0000 + 0x23000 = 0xa002 3000
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 173 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.12 pin description table 113 shows the interface and control signal pins for the emc. table 113. pad interface and control signal descriptions name type value on por reset value during self-refresh description emc_a[23:0] output 0 depends on static memory accesses external memory address output. used for both static and sdram devices. sdram memories use only bits [14:0]. emc_d[31:0] input/ output data outputs = 0 depends on static memory accesses external memory data lines. these are inputs when data is read from external memory and outputs when data is written to external memory. emc_oe output 1 depends on static memory accesses low active output enable for static memory devices. emc_bls3:0 output 0xf depends on static memory accesses low active byte lane selects. used for static memory devices. emc_we output 1 depends on static memory accesses low active write enable. used for sdram and static memories. emc_cs3:0 output 0xf depends on static memory accesses static memory chip selects. default active low. used for static memory devices. emc_dycs3:0 output 0xf 0xf sdram chip selects. used for sdram devices. emc_cas output 1 1 column address strobe. used for sdram devices. emc_ras output 1 1 row address strobe. used for sdram devices. emc_clk1:0 output follows cclk follows cclk sdram clocks. used for sdram devices. emc_cke3:0 output 0xf 0x0 sdram clock enabl es. used for sdram devices. one is allocated for each chip select. emc_dqm3:0 output 0xf 0xf data mask output to sdrams. used for sdram devices and static memories.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 174 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.13 register description this chapter describes the emc register s and provides details required when programming the microcontroller. . the emc clock configuration and clock calibration registers are located in the system control block. see section 3.3.6.1 and section 3.3.6.2 . table 114. register overview: emc (base address 0x2009 0000) register name access address offset description warm reset value [1] por reset value [1] table control r/w 0x000 controls operation of the memory controller. 0x1 0x3 115 status ro 0x004 provides emc status information. - 0x5 116 config r/w 0x008 configures operation of the memory controller - 0x0 117 dynamiccontrol r/w 0x020 controls dynamic memory operation. - 0x006 118 dynamicrefresh r/w 0x024 configures dynamic memory refresh. - 0x0 119 dynamicreadconfig r/w 0x028 configures dynamic memory read strategy. - 0x0 120 dynamicrp r/w 0x030 precharge command period. - 0x0f 121 dynamicras r/w 0x034 active to precharge command period. - 0xf 122 dynamicsrex r/w 0x038 self-refresh exit time. - 0xf 123 dynamicapr r/w 0x03c last-data-out to active command time. - 0xf 124 dynamicdal r/w 0x040 data-in to active command time. - 0xf 125 dynamicwr r/w 0x044 write recovery time. - 0xf 126 dynamicrc r/w 0x048 selects the active to active command period. - 0x1f 127 dynamicrfc r/w 0x04c selects the auto-refresh period. - 0x1f 128 dynamicxsr r/w 0x050 time for exit self-refresh to active command. - 0x1f 129 dynamicrrd r/w 0x054 latency for active bank a to active bank b. - 0xf 130 dynamicmrd r/w 0x058 time for load mode register to active command. -0xf 131 staticextendedwait r/w 0x080 time for long static memory read and write transfers. -0x0 132 dynamicconfig0 r/w 0x100 configuration information for emc_dycs0 .-0x0 133 dynamicrascas0 r/w 0x104 ras and cas latencies for emc_dycs0 . - 0x303 135 dynamicconfig1 r/w 0x120 configuration information for emc_dycs1 .-0x0 133 dynamicrascas1 r/w 0x124 ras and cas latencies for emc_dycs1 . - 0x303 135 dynamicconfig2 r/w 0x140 configuration information for emc_dycs2 .-0x0 133 dynamicrascas2 r/w 0x144 ras and cas latencies for emc_dycs2 . - 0x303 135 dynamicconfig3 r/w 0x160 configuration information for emc_dycs3 .-0x0 133 dynamicrascas3 r/w 0x164 ras and cas latencies for emc_dycs3 . - 0x303 135 staticconfig0 r/w 0x200 configuration for emc_cs0 .- 0 x 0 136 staticwaitwen0 r/w 0x204 delay from emc_cs0 to write enable. - 0x0 137 staticwaitoen0 r/w 0x208 delay from emc_cs0 or address change, whichever is later, to output enable. -0x0 138 staticwaitrd0 r/w 0x20c delay from emc_cs0 to a read access. - 0x1f 139
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 175 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) [1] reset value reflects the data stored in used bits only. it does not include reserved bits content. staticwaitpage0 r/w 0x210 delay for asynchronous page mode sequential accesses for emc_cs0 . -0x1f 140 staticwaitwr0 r/w 0x214 delay from emc_cs0 to a write access. - 0x1f 141 staticwaitturn0 r/w 0x218 number of bus turnaround cycles emc_cs0. -0xf 142 staticconfig1 r/w 0x220 memory configuration for emc_cs1 .-0 x 0 136 staticwaitwen1 r/w 0x224 delay from emc_cs1 to write enable. - 0x0 137 staticwaitoen1 r/w 0x228 delay from emc_cs1 or address change, whichever is later, to output enable. -0x0 138 staticwaitrd1 r/w 0x22c delay from emc_cs1 to a read access. - 0x1f 139 staticwaitpage1 r/w 0x230 delay for asynchronous page mode sequential accesses for emc_cs1 . -0x1f 140 staticwaitwr1 r/w 0x234 delay from emc_cs1 to a write access. - 0x1f 141 staticwaitturn1 r/w 0x238 bus turnaround cycles for emc_cs1 .-0 x f 142 staticconfig2 r/w 0x240 memory configuration for emc_cs2 .-0 x 0 136 staticwaitwen2 r/w 0x244 delay from emc_cs2 to write enable. - 0x0 137 staticwaitoen2 r/w 0x248 delay from emc_cs2 or address change, whichever is later, to output enable. -0x0 138 staticwaitrd2 r/w 0x24c delay from emc_cs2 to a read access. - 0x1f 139 staticwaitpage2 r/w 0x250 delay for asynchronous page mode sequential accesses for emc_cs2 . -0x1f 140 staticwaitwr2 r/w 0x254 delay from emc_cs2 to a write access. - 0x1f 141 emcstaticwaitturn2 r/w 0x258 bus turnaround cycles for emc_cs2 .-0 x f 142 staticconfig3 r/w 0x260 memory configuration for emc_cs3 .-0 x 0 136 staticwaitwen3 r/w 0x264 delay from emc_cs3 to write enable. - 0x0 137 staticwaitoen3 r/w 0x268 delay from emc_cs3 or address change, whichever is later, to output enable. -0x0 138 staticwaitrd3 r/w 0x26c delay from emc_cs3 to a read access. - 0x1f 139 staticwaitpage3 r/w 0x270 delay for asynchronous page mode sequential accesses for emc_cs3 . -0x1f 140 staticwaitwr3 r/w 0x274 delay from emc_cs3 to a write access. - 0x1f 141 staticwaitturn3 r/w 0x278 bus turnaround cycles for emc_cs3 .-0 x f 142 table 114. register overview: emc (base address 0x2009 0000) ?continued register name access address offset description warm reset value [1] por reset value [1] table
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 176 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.13.1 emc control register the emccontrol register is a read/write register that controls operation of the memory controller. the control bits can be altered during normal operation. table 115 shows the bit assignments for the emccontrol register. [1] the external memory cannot be accessed in low-power or disabled state. if a memo ry access is performed an ahb error response is generated. the emc register s can be programmed in low-power and/or disabled state. table 115. emc control register (control - address 0x2009 c000) bit description bit symbol value description reset value 0 e emc enable. indicates if the emc is enabled or disabled: 1 0 disabled 1 enabled (por and warm reset value). disabling the emc reduces power consumption. when the memory controller is disabled the memory is not refreshed. the memory controller is enabled by setting the enable bit, or by reset. this bit must only be modified when the emc is in idle state. [1] 1 m address mirror. indicates normal or reset memory map: 1 0 normal memory map. 1 reset memory map. static memory emc_cs1 is mirrored onto emc_cs0 and emc_dycs0 (por reset value). on por, emc_cs1 is mirrored to both emc_cs0 and emc_dycs0 memory areas. clearing the m bit enables emc_cs0 and emc_dycs0 memory to be accessed. 2 l low-power mode. indicates normal, or low-power mode: 0 0 normal mode (warm reset value). 1 low-power mode. entering low-power mode reduces memory controller power consumption. dynamic memory is refreshed as necessary. the memo ry controller returns to normal functional mode by clearing the low-power mode bit (l), or by por. this bit must only be modified when the emc is in idle state. [1] 31:3 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 177 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.13.2 emc status register the read-only emcstatus register provides emc status information. 9.13.3 emc configuration register the emcconfig register configures the ope ration of the memory controller. it is recommended that this register is modified during system in itialization, or when there are no current or outstanding transactions. this can be ensured by waiting until the emc is idle, and then entering low-power, or disabled mode. this register is accessed with one wait state. table 116. emc status register (status - address 0x2009 c008) bit description bit symbol value description reset value 0 b busy. this bit is used to ensure that th e memory controller enters the low-power or disabled mode cleanly by determining if the memory controller is busy or not. 1 0 emc is idle (warm reset value). 1 emc is busy performing memory transacti ons, commands, auto-ref resh cycles, or is in self-refresh mode (por reset value). 1 s write buffer status.this bit enables the emc to enter low-power mode or disabled mode cleanly. 0 0 write buffers empt y (por reset value) 1 write buffers contain data. 2 sa self-refresh acknowledge. this bit indicates the operating mode of the emc. 1 0 normal mode 1 self-refresh mode (por reset value). 31:3 - reserved. the value read from a reserved bit is not defined. na table 117. emc configuration register (config - address 0x2009 c008) bit description bit symbol value description reset value 0 em endian mode. on power-on reset, the value of the endian bit is 0. all data must be flushed in the emc before switching between little-endian and big-endian modes. 0 0 little-endian mode (por reset value). 1 big-endian mode. 7:1 - reserved. read value is undefined, only zero should be written. na 8 clkr cclk: clkout ratio. this bit must contain 0 for proper operation of the emc. 0 0 1:1 (por reset value) 1 1:2 (this option is not available) 31:9 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 178 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.13.4 dynamic memory control register the emcdynamiccontrol register controls dy namic memory operation. the control bits can be altered during normal operation. [1] clock enable must be high during sdram initialization. [2] the memory controller exits from power-on reset with the self-refresh bit high. to enter normal functional mode set this bit low. [3] disabling clkout can be performed if there are no sdram memory transactions. when enabled this bit can be used in conjunction wi th the dynamic memory clock control (cs) field. remark: deep-sleep mode can be entered by sett ing the deep-sleep mode (dp) bit, the dynamic memory clock enable bit (ce), and the dynamic clock control bit (cs) to one. the device is then put into a low-power mode where the device is powered down and no longer refreshed. all data in the memory is lost. table 118. dynamic control register (dynamiccontrol - address 0x2009 c020) bit description bit symbol value description reset value 0 ce dynamic memory clock enable. 0 0 clock enable of idle devices are deasserted to save power (por reset value). 1 all clock enables are driven high continuously. [1] 1 cs dynamic memory clock control. when clock control is low the output clock clkout is stopped when there are no sdram transactions. the clock is also stopped during self-refresh mode. 1 0 clkout stops when all sdrams are idle and during self-refresh mode. 1 clkout runs continuously (por reset value). 2 sr self-refresh request, emcsrefreq. by writing 1 to this bit self-refresh can be entered under software control. writing 0 to this bit returns the emc to normal mode. the self-refresh acknowledge bit in the status register must be polled to discover the current operating mode of the emc. [2] 1 0 normal mode. 1 enter self-refresh mo de (por reset value). 4:3 - - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. - 5 mmc memory clock control. 0 0 clkout enabled (por reset value). 1 clkout disabled. [3] 6 - - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. - 8:7 i sdram initialization. 00 0x0 issue sdram normal operation command (por reset value). 0x1 issue sdram mode command. 0x2 issue sdram pall (precharge all) command. 0x3 issue sdram nop (no operation) command) 13:9 - - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. - 31:14 - - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 179 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.13.5 dynamic memory re fresh timer register the emcdynamicrefresh register configures dynamic memory operation. it is recommended that this register is modified during system in itialization, or when there are no current or outstanding transactions. this can be ensured by waiting until the emc is idle, and then entering low-power, or disabled mode. however, these control bits can, if necessary, be altered during normal operation. this register is accessed with one wait state. note: this register is used fo r all four dynamic memory chip selects. therefore the worst case value for all of the chip selects must be programmed. . for example, for the refresh period of 16 s, and a cclk frequency of 50 mhz, the following value must be prog rammed into this register: (16 x 10-6 x 50 x 106) / 16 = 50 or 0x32 if auto-refresh through warm reset is requested (by setting the emc_reset_disable bit), the timing of auto-refresh must be adjusted to allow a sufficient refresh rate when the clock rate is reduced during the wake-up peri od of a reset cycle. during this period, the emc (and all other portions of the device that are being clocked) run from the irc oscillator at 12 mhz. so, 12 mhz must be considered th e cclk rate for refresh calculations if auto-refresh through warm reset is requested. note: the refresh cycles are evenly distributed. however, there might be slight variations when the auto-refresh command is issued depending on the status of the memory controller. table 119. dynamic memory refresh timer register (dynamicrefresh - address 0x2009 c024) bit description bit symbol description reset value 10:0 refresh refresh timer. indicates the mult iple of 16 cclks between sdram refresh cycles. 0x0 = refresh disabled (por reset value). 0x1 - 0x7ff = n x16 = 16n cclks between sdram refresh cycles. for example: 0x1 = 1 x 16 = 16 cclks between sdram refresh cycles. 0x8 = 8 x 16 = 128 cclks between sdram refresh cycles 0 31:11 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 180 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.13.6 dynamic memory read configuration register the emcdynamicreadconfig register config ures the dynamic memory read strategy. this register must only be modified during s ystem initialization. this register is accessed with one wait state. note: this register is used fo r all four dynamic memory chip selects, so a single read strategy must be used for all dynamic memories. table 120 shows the bit assignments for the emcdynamicreadconfig register. when using command delayed strategy, programmable delays can be used to adjust the timing of the control signals output by the emc. see section 9.5.6 and section 3.3.6.1 . 9.13.7 dynamic memory precharge command period register the emcdynamictrp register enables you to program the precharge command period, trp. this register must only be modified durin g system initialization. this value is normally found in sdram data sheets as trp. this register is accessed with one wait state. note: this register is used fo r all four dynamic memory chip selects. therefore the worst case value for all of the chip selects must be programmed. table 120. dynamic memory read configuration regi ster (dynamicreadconfig - address 0x2009 c028) bit description bit symbol value description reset value 1:0 rd read data strategy 0x0 0x0 clock out delayed strategy, using clkout (command not delayed, clock out delayed). por reset value. 0x1 command delayed strategy, using emcclkdelay (command delayed, clock out not delayed). 0x2 command delayed strategy plus one clock cycle, using emcclkdelay (command delayed, clock out not delayed). 0x3 command delayed strategy plus two clock cycles, using emcclkdelay (command delayed, clock out not delayed). 31:2 - reserved. read value is undefined, only zero should be written. na table 121. dynamic memory precharge command period register (dynamicrp - address 0x2009 c030) bit description bit symbol description reset value 3:0 trp precharge command period. 0x0 - 0xe = n + 1 clock cycles. the delay is in cclk cycles. 0xf = 16 clock cycles (por reset value). 0xf 31:4 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 181 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.13.8 dynamic memory active to pr echarge command pe riod register the emcdynamictras register enables you to program the active to precharge command period, tras. it is recommended that this register is modified during system initialization, or when there are no curren t or outstanding transactions. this can be ensured by waiting until the emc is idle, and then entering low-power, or disabled mode. this value is normally found in sdram data sheets as tras. this register is accessed with one wait state. note: this register is used fo r all four dynamic memory chip selects. therefore the worst case value for all of the chip selects must be programmed. 9.13.9 dynamic memory self-ref resh exit time register the emcdynamictsrex register enables you to program the self-refresh exit time, tsrex. it is recommended that this register is modified du ring system initialization, or when there are no current or outstanding tr ansactions. this can be ensured by waiting until the emc is idle, and then entering low-power, or disabled mode. this value is normally found in sdram data sheets as tsrex, for devices without this parameter you use the same value as txsr. this register is accessed with one wait state. note: this register is used fo r all four dynamic memory chip selects. therefore the worst case value for all of the chip selects must be programmed. table 122. dynamic memory active to precha rge command period register (dynamicras - address 0x2009 c034) bit description bit symbol description reset value 3:0 tras active to precharge command period. 0x0 - 0xe = n + 1 clock cycles. the delay is in cclk cycles. 0xf = 16 clock cycles (por reset value). 0xf 31:4 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. - table 123. dynamic memory self refresh exit time register (dynamicsrex - address 0x2009 c038) bit description bit symbol description reset value 3:0 tsrex self-refresh exit time. 0x0 - 0xe = n + 1 clock cycles. the delay is in cclk cycles. 0xf = 16 clock cycles (por reset value). 0xf 31:4 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 182 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.13.10 dynamic memory last data out to active time register the emcdynamictapr register enables you to program the last-data-out to active command time, tapr. it is recommended that this register is modified during system initialization, or when there are no curren t or outstanding transactions. this can be ensured by waiting until the emc is idle, and then entering low-power, or disabled mode. this value is normally found in sdram data sheets as tapr. this register is accessed with one wait state. note: this register is used fo r all four dynamic memory chip selects. therefore the worst case value for all of the chip selects must be programmed. 9.13.11 dynamic memory data-in to active command time register the emcdynamictdal register enables you to program the data-in to active command time, tdal. it is recommended that this register is modified during syst em initialization, or when there are no current or outstanding tr ansactions. this can be ensured by waiting until the emc is idle, and then entering low-power, or disabled mode. this value is normally found in sdram data sheets as tdal, or tapw. this register is accessed with one wait state. note: this register is used fo r all four dynamic memory chip selects. therefore the worst case value for all of the chip selects must be programmed. table 124. dynamic memory last data out to active time register (dynamicapr - address 0x2009 c03c) bit description bit symbol description reset value 3:0 tapr last-data-out to active command time. 0x0 - 0xe = n + 1 clock cycles. the delay is in cclk cycles. 0xf = 16 clock cycles (por reset value). 0xf 31:4 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. - table 125. dynamic memory data in to active command time register (dynamicdal - address 0x2009 c040) bit description bit symbol description reset value 3:0 tdal data-in to active command. 0x0 - 0xe = n clock cycles. the delay is in cclk cycles. 0xf = 15 clock cycles (por reset value). 0xf 31:4 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 183 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.13.12 dynamic memory writ e recovery time register the emcdynamictwr register enables you to pr ogram the write recove ry time, twr. it is recommended that this register is modified during system in itialization, or when there are no current or outstanding transactions. this can be ensured by waiting until the emc is idle, and then entering low-power, or disabl ed mode. this value is normally found in sdram data sheets as twr, tdpl, trwl, or trdl. this register is accessed with one wait state. note: this register is used fo r all four dynamic memory chip selects. therefore the worst case value for all of the chip selects must be programmed. 9.13.13 dynamic memory active to active command period register the emcdynamictrc register enables you to program the active to active command period, trc. it is recommended that this register is modified during s ystem initialization, or when there are no current or outstanding tr ansactions. this can be ensured by waiting until the emc is idle, and then entering low-power, or disabled mode. this value is normally found in sdram data sheets as trc. this register is accessed with one wait state. note: this register is used fo r all four dynamic memory chip selects. therefore the worst case value for all of the chip selects must be programmed. table 126. dynamic memory write recovery time register (dynamicwr - address 0x2009 c044) bit description bit symbol description reset value 3:0 twr write recovery time. 0x0 - 0xe = n + 1 clock cycles. the delay is in cclk cycles. 0xf = 16 clock cycles (por reset value). 0xf 31:4 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. - table 127. dynamic memory active to active command period re gister (dynamicrc - address 0x2009 c048) bit description bit symbol description reset value 4:0 trc active to active command period. 0x0 - 0x1e = n + 1 clock cycles. the delay is in cclk cycles. 0x1f = 32 clock cycles (por reset value). 0x1f 31:5 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 184 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.13.14 dynamic memory auto -refresh period register the emcdynamictrfc register enables you to program the auto-refresh period, and auto-refresh to active command period, trfc. it is recommend ed that this register is modified during system initialization, or when there are no current or outstanding transactions. this can be ensured by waiting until the emc is idle, and then entering low-power, or disabled mode. this value is normally found in sdram data sheets as trfc, or sometimes as trc. this regi ster is accessed with one wait state. note: this register is used fo r all four dynamic memory chip selects. therefore the worst case value for all of the chip selects must be programmed. 9.13.15 dynamic memory exit self-refresh register the emcdynamictxsr register enables you to program the exit self-refresh to active command time, txsr. it is recommended that this register is modified during system initialization, or when there are no curren t or outstanding transactions. this can be ensured by waiting until the emc is idle, and then entering low-power, or disabled mode. this value is normally found in sdram data sheets as txsr. this register is accessed with one wait state. note: this register is used fo r all four dynamic memory chip selects. therefore the worst case value for all of the chip selects must be programmed. table 128. dynamic memory auto refresh period register (dynamicrfc - address 0x2009 c04c) bit description bit symbol description reset value 4:0 trfc auto-refresh period and auto-refresh to active command period. 0x0 - 0x1e = n + 1 clock cycles. the delay is in cclk cycles. 0x1f = 32 clock cycles (por reset value). 0x1f 31:5 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. - table 129. dynamic memory exit self refresh register (dynamicxsr - address 0x2009 c050) bit description bit symbol description reset value 4:0 txsr exit self-refresh to active command time. 0x0 - 0x1e = n + 1 clock cycles. the delay is in cclk cycles. 0x1f = 32 clock cycles (por reset value). 0x1f 31:5 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 185 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.13.16 dynamic memory ac tive bank a to active ba nk b time register the emcdynamictrrd register enables you to program the active bank a to active bank b latency, trrd. it is recommended that this register is modified during system initialization, or when there are no curren t or outstanding transactions. this can be ensured by waiting until the emc is idle, and then entering low-power, or disabled mode. this value is normally found in sdram data sheets as trrd. this register is accessed with one wait state. note: this register is used fo r all four dynamic memory chip selects. therefore the worst case value for all of the chip selects must be programmed. 9.13.17 dynamic memory load mode register to active command time the emcdynamictmrd register enables you to pr ogram the load mode register to active command time, tmrd. it is reco mmended that this register is modified during system initialization, or when there are no curren t or outstanding transactions. this can be ensured by waiting until the emc is idle, and then entering low-power, or disabled mode. this value is normally found in sdram data sheets as tmrd, or trsa. this register is accessed with one wait state. note: this register is used fo r all four dynamic memory chip selects. therefore the worst case value for all of the chip selects must be programmed. table 130. dynamic memory active bank a to active bank b time register (dynamicrrd - address 0x2009 c054) bit description bit symbol description reset value 3:0 trrd active bank a to active bank b latency 0x0 - 0xe = n + 1 clock cycles. the delay is in cclk cycles. 0xf = 16 clock cycles (por reset value). 0xf 31:4 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. - table 131. dynamic memory load mode register to active command time (dynamicmrd - address 0x2009 c058) bit description bit symbol description reset value 3:0 tmrd load mode register to active command time. 0x0 - 0xe = n + 1 clock cycles. the delay is in cclk cycles. 0xf = 16 clock cycles (por reset value). 0xf 31:4 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 186 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.13.18 static memory extended wait register extendedwait (ew) bit in the emcstaticconfig register is set. it is recommended that this register is modified during system initia lization, or when there are no current or outstanding transactions. however, if necessary, these control bits can be altered during normal operation. this register is accessed with one wait state. for example, for a static memory read/write transfer time of 16 s, and a cclk frequency of 50 mhz, the following value must be progra mmed into this register: (16 x 10-6 x 50 x 106) / 16 - 1 = 49 table 132. static memory extended wait register (staticextendedwait - address 0x2009 c080) bit description bit symbol description reset value 9:0 extendedwait extended wait time out. 16 clock cycles (por reset va lue). the delay is in cclk cycles. 0x0 = 16 clock cycles. 0x1 - 0x3ff = (n+1) x16 clock cycles. 0x0 31:10 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 187 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.13.19 dynamic memory c onfiguration registers the emcdynamicconfig0-3 registers enable you to program the configuration information for the relevant dynamic memory chip select . these registers are normally only modified during system initialization. these registers are accessed with one wait state. table 133 shows the bit assignments for th e emcdynamicconfig0-3 registers. [1] the sdram column and row width and number of banks are computed automatically from the address mapping. [2] the buffers must be disabled during sdram initia lization. the buffers must be enabled during normal operation. table 133. dynamic memory configuration registers (dynamicconfig[0:3], address 0x2009 c100 (dynamicconfig0), 0x2009 c120 (dynamicconfig 1), 0x2009 c140 (dynamicconfig2), 0x2009 c160 (dynamicconfig3)) bit description bit symbol value description reset value 2:0 - reserved. read value is undefined, only zero should be written. na 4:3 md memory device. 0 0x0 sdram (por reset value). 0x1 low-power sdram. 0x2 reserved. 0x3 reserved. 6:5 - reserved. read value is undefined, only zero should be written. na 12:7 am0 see table 134 . 000000 = reset value. [1] 0 13 - reserved. read value is undefined, only zero should be written. na 14 am1 see table 134 . 0 = reset value. 0 18:15 - reserved. read value is undefined, only zero should be written. na 19 b buffer enable. 0 0 buffer disabled for accesses to this chip select (por reset value). 1 buffer enabled for accesse s to this chip select. [2] 20 p write protect. 0 0 writes not protected (por reset value). 1 writes protected. 31:21 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 188 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) address mappings that are not shown in table 134 are reserved. table 134. address mapping 14 12 11:9 8:7 description banks row length column length 16 bit bus width (row, bank, column) 0 0 000 00 16 mbits (2m x 8) 2 11 9 0 0 000 01 16 mbits (1m x 16) 2 11 8 0 0 001 00 64 mbits (8m x 8) 4 12 9 0 0 001 01 64 mbits (4m x 16) 4 12 8 0 0 010 00 128 mbits (16m x 8) 4 12 10 0 0 010 01 128 mbits (8m x 16) 4 12 9 0 0 011 00 256 mbits (32m x 8) 4 13 10 0 0 011 01 256 mbits (16m x 16) 4 13 9 0 0 100 00 512 mbits (64m x 8) 4 13 11 0 0 100 01 512 mbits (32m x 16) 4 13 10 16 bit bus width (bank, row, column) 0 1 000 00 16 mbits (2m x 8) 2 11 9 0 1 000 01 16 mbits (1m x 16) 2 11 8 0 1 001 00 64 mbits (8m x 8) 4 12 9 0 1 001 01 64 mbits (4m x 16) 4 12 8 0 1 010 00 128 mbits (16m x 8) 4 12 10 0 1 010 01 128 mbits (8m x 16) 4 12 9 0 1 011 00 256 mbits (32m x 8) 4 13 10 0 1 011 01 256 mbits (16m x 16) 4 13 9 0 1 100 00 512 mbits (64m x 8) 4 13 11 0 1 100 01 512 mbits (32m x 16) 4 13 10 32 bit bus width (row, bank, column) 1 0 000 00 16 mbits (2m x 8) 2 11 9 1 0 000 01 16 mbits (1m x 16) 2 11 8 1 0 001 00 64 mbits (8m x 8) 4 12 9 1 0 001 01 64 mbits (4m x 16) 4 12 8 1 0 001 10 64 mbits (2m x 32) 4 11 8 1 0 010 00 128 mbits (16m x 8) 4 12 10 1 0 010 01 128 mbits (8m x 16) 4 12 9 1 0 010 10 128 mbits (4m x 32) 4 12 8 1 0 011 00 256 mbits (32m x 8) 4 13 10 1 0 011 01 256 mbits (16m x 16) 4 13 9 1 0 011 10 256 mbits (8m x 32) 4 13 8 1 0 100 00 512 mbits (64m x 8) 4 13 11 1 0 100 01 512 mbits (32m x 16) 4 13 10 32 bit bus width (bank, row, column) 1 1 000 00 16 mbits (2m x 8) 2 11 9 1 1 000 01 16 mbits (1m x 16) 2 11 8
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 189 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) a chip select can be connected to a single memo ry device, in this case the chip select data bus width is the same as the device width. alternatively the chip select can be connected to a number of external devices. in this case the chip select data bus width is the sum of the memory device data bus widths. for example, for a chip select connected to: ? a 32 bit wide memory device, choose a 32 bit wide address mapping. ? a 16 bit wide memory device, choose a 16 bit wide address mapping. ? four x 8 bit wide memory devices, choose a 32 bit wide address mapping. ? two x 8 bit wide memory devices, choose a 16 bit wide address mapping. the sdram bank select pins ba1 and ba0 ar e connected to address lines a14 and a13, respectively. 9.13.20 dynamic memory ras & cas delay registers the emcdynamicrascas0-3 registers enable you to program the ras and cas latencies for the relevant dynamic memory. it is recommended that these registers are modified during system initialization, or when there are no current or outstanding transactions. this can be ensured by waiting until the emc is idle, and then entering low-power, or disabled mode. these regi sters are accessed with one wait state. note: the values programmed into these regist ers must be consistent with the values used to initialize the sdram memory device. 1 1 001 00 64 mbits (8m x 8) 4 12 9 1 1 001 01 64 mbits (4m x 16) 4 12 8 1 1 001 10 64 mbits (2m x 32) 4 11 8 1 1 010 00 128 mbits (16m x 8) 4 12 10 1 1 010 01 128 mbits (8m x 16) 4 12 9 1 1 010 10 128 mbits (4m x 32) 4 12 8 1 1 011 00 256 mbits (32m x 8) 4 13 10 1 1 011 01 256 mbits (16m x 16) 4 13 9 1 1 011 10 256 mbits (8m x 32) 4 13 8 1 1 100 00 512 mbits (64m x 8) 4 13 11 1 1 100 01 512 mbits (32m x 16) 4 13 10 table 134. address mapping 14 12 11:9 8:7 description banks row length column length
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 190 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) table 135. dynamic memory rascas delay regi sters (dynamicrascas[0:3], address 0x2009 c104 (dynamicrascas0), 0x2009 c124 (dynamicras cas1), 0x2009 c144 (dynamicrascas2), 0x2009 c164 (dynamicrascas3)) bit description bit symbol value description reset value 1:0 ras ras latency (active to read/write delay). 11 0x0 reserved. 0x1 one cclk cycle. 0x2 two cclk cycles. 0x3 three cclk cycles (por reset value). 7:2 - - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. - 9:8 cas cas latency. 11 0x0 reserved. 0x1 one cclk cycle. 0x2 two cclk cycles. 0x3 three cclk cycles (por reset value). 31:10 - - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 191 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.13.21 static memory configuration registers the emcstaticconfig0-3 registers configure th e static memory configuration. it is recommended that these registers are modified during system initializat ion, or when there are no current or outstanding transactions. th is can be ensured by waiting until the emc is idle, and then entering low-power, or disabled mode. these registers are accessed with one wait state. table 136 shows the bit assignments for the emcstaticconfig0-3 registers. note that synchronous burst mode memory devices are not supported. table 136. static memory configuration registers (s taticconfig[0:3], address 0x2009 c200 (staticconfig0), 0x2009 c220 (staticconfig1), 0x2009 c240 (staticconfig2), 0x2009 c260 (staticconfig3)) bit description bit symbol value description reset value 1:0 mw memory width. 0 0x0 8 bit (por reset value). 0x1 16 bit. 0x2 32 bit. 0x3 reserved. 2 - reserved. read value is undefined, only zero should be written. na 3 pm page mode. in page mode the emc can burst up to four external accesses. therefore devices with asynchronous page mode burst four or higher devices are supported. asynchronous page mode burst two devices are not supported and must be accessed normally. 0 0 disabled (por reset value). 1 asynchronous page mode enabled (page length four). 5:4 - reserved. read value is undefined, only zero should be written. na 6 pc chip select polarity. the value of the chip select polarity on power-on reset is 0. 0 0 active low chip select. 1 active high chip select. 7 pb byte lane state. the byte lane state bit, pb, enables different types of memory to be connected. for byte-wide static memories the bls3:0 signal from the emc is usually connected to we (write enable). in this case for reads all the bls3:0 bits must be high. this means that the byte lane state (pb) bit must be low. 16 bit wide static memory devices usually have the bls3:0 signals connected to the ubn and lbn (upper byte and lower byte) signals in the static memory. in this case a write to a particular byte must assert the appropriate ubn or lbn signal low. for reads, all the ub and lb signals must be asserted low so that the bus is driven. in this case the byte lane state (pb) bit must be high. 0 0 for reads all the bits in bls3:0 are high. for writes the respective active bits in bls3:0 are low (por reset value). 1 for reads the respective active bits in bls3:0 are low. for writes the respective active bits in bls3:0 are low.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 192 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) [1] extended wait and page mode cannot be selected simultaneously. [2] emc may perform burst read access even when the buffer enable bit is cleared. 9.13.22 static memory writ e enable delay registers the emcstaticwaitwen0-3 registers enable you to program the delay from the chip select to the write enable. it is recommended that these registers are mo dified during system initialization, or when there are no curren t or outstanding transactions. this can be ensured by waiting until the emc is idle, and then entering low-power, or disabled mode. these registers are accessed with one wait state. 8 ew extended wait (ew) uses the emcstaticextendedwait register to time both the read and write transfers rather than the emcstaticwaitrd and emcstaticwaitwr registers. this enables much longer transactions. [1] 0 0 extended wait disabled (por reset value). 1 extended wait enabled. 18:9 - reserved. read value is undefined, only zero should be written. na 19 b buffer enable [2] 0 0 buffer disabled (por reset value). 1 buffer enabled. 20 p write protect 0 0 writes not protected (por reset value). 1 write protected. 31:21 - reserved. read value is undefined, only zero should be written. na table 136. static memory configuration registers (s taticconfig[0:3], address 0x2009 c200 (staticconfig0), 0x2009 c220 (staticconfig1), 0x2009 c240 (staticconfig2), 0x2009 c260 (staticconfig3)) bit description bit symbol value description reset value table 137. static memory write enable delay registers (staticwaitwen[0:3], address 0x2009 c204 (staticwaitwen0), 0x2009 c224 (staticwaitwen1),0x2009 c244 (staticwaitwen2), 0x2009 c264 (staticwaitwen3)) bit description bit symbol description reset value 3:0 waitwen wait write enable. delay from chip select assertion to write enable. 0x0 = one cclk cycle delay between assertion of chip select and write enable (por reset value). 0x1 - 0xf = (n + 1) cclk cycle delay. the delay is (waitwen +1) x tcclk. 0x0 31:4 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 193 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.13.23 static memory output enable delay registers the emcstaticwaitoen0-3 registers enable you to program the delay from the chip select or address change, whichever is later, to the output enable. it is recommended that these registers are modified during system initializ ation, or when there are no current or outstanding transactions. this can be ensured by waiting until the emc is idle, and then entering low-power, or disabled mode. these registers are accessed with one wait state. 9.13.24 static memory read delay registers the emcstaticwaitrd0-3 registers enable you to program the delay from the chip select to the read access. it is recommended that these registers are mo dified during system initialization, or when there are no curren t or outstanding transactions. this can be ensured by waiting until the emc is idle, and then entering low-power, or disabled mode. it is not used if the extended wait bit is enabl ed in the emcstaticconfig0-3 registers. these registers are accessed with one wait state. [1] the reset value depends on the boot mode. table 138. static memory output enable delay registers (staticwaitoen[0:3], address 0x2009 c208 (staticwaitoen0), 0x0x2009 c228 (staticwaitoen1), 0x0x2009 c248 (staticwaitoen2), 0x0x2009 c268 (staticwaitoen3)) bit description bit symbol description reset value 3:0 waitoen wait output enable. delay from chip select assertion to output enable. 0x0 = no delay (por reset value). 0x1 - 0xf = n cycle delay. the delay is waitoen x tcclk. 0x0 31:4 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. - table 139. static memory read delay registers (staticwaitrd[0:3], address 0x2009 c20c (staticwaitrd0), 0x2009 c22c (staticwaitrd1), 0x2009 c24c (staticwaitrd2), 0x2009 c26c (s taticwaitrd3)) bit description bit symbol description reset value 4:0 waitrd non-page mode read wait states or asynchronous page mode read first access wait state. non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1e = (n + 1) cclk cycl es for read accesses. for non-sequential reads, the wait state time is (waitrd + 1) x tcclk. 0x1f = 32 cclk cycles for re ad accesses (por reset value). 0x1f [1] 31:5 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 194 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.13.25 static memory page mode read delay registers the emcstaticwaitpage0-3 registers enable you to program the delay for asynchronous page mode sequential accesses. it is reco mmended that these registers are modified during system initialization, or when there are no current or outstanding transactions. this can be ensured by waiting until the emc is idle, and then entering low-power, or disabled mode. this register is accessed with one wait state. 9.13.26 static memory write delay registers the emcstaticwaitwr0-3 registers enable you to program the delay from the chip select to the write access. it is recommended that these registers are modified during system initialization, or when there are no curren t or outstanding transactions. this can be ensured by waiting until the emc is idle, and then entering low-power, or disabled mode.these registers are not used if the extended wait (ew) bit is enabled in the emcstaticconfig register. these register s are accessed with one wait state. table 140. static memory page mode read delay registers (staticwaitpage[0:3], address 0x2009 c210 (staticwaitpage0), 2009 c230 (staticwaitpage1), 0x2009 c250 (staticwaitpage2), 0x2009 c270 (s taticwaitpage3)) bit description bit symbol description reset value 4:0 waitpage asynchronous page mode read after the first read wait states. number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1e = (n+ 1) cclk cycle read access time. for asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (waitpage + 1) x tcclk. 0x1f = 32 cclk cycle read access time (por reset value). 0x1f 31:5 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. - table 141. static memory write delay registers (staticwaitwr[0:3], address 0x2009 c214 (staticwaitwr0), 0x2009 c234 (staticwaitwr1), 0x2009 c254 (staticwaitwr2), 0x2009 c274 (staticwaitwr3)) bit description bit symbol description reset value 4:0 waitwr write wait states. sram wait state time for writ e accesses after the first read: 0x0 - 0x1e = (n + 2) cclk cycle writ e access time. the wait state time for write accesses after the first read is waitwr (n + 2) x tcclk. 0x1f = 33 cclk cycle write ac cess time (por reset value). 0x1f 31:5 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 195 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.13.27 static memory turn round delay registers the emcstaticwaitturn0-3 registers enable you to program the number of bus turnaround cycles. it is recommended that these registers are modified during system initialization, or when there are no curren t or outstanding transactions. this can be ensured by waiting until the emc is idle, and then entering low-power, or disabled mode. these registers are accessed with one wait state. to prevent bus contention on the external me mory data bus, the waitturn field controls the number of bus turnaround cycles added between static memory read and write accesses. the waitturn field also controls the number of turnaround cycles between static memory and dy namic memory accesses. table 142. static memory turn-around delay registers (staticwaitturn[0:3], address 0x2009 c218 (staticwaitturn0),0x2009 c238 (staticwaitturn1), 0x2009 c258 (staticwaitturn2), 0x2009 c278 (staticwaitturn3)) bit description bit symbol description reset value 3:0 waitturn bus turn-around cycles. 0x0 - 0xe = (n + 1) cclk turn-around cycles. bus turn-around time is (waitturn + 1) x tcclk. 0xf = 16 cclk turn-around cycles (por reset value). 0xf 31:4 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 196 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.14 external memory interface external memory interfacing depends on the bank width (32, 16 or 8 bit selected via mw bits in corresponding emcstaticconfig register). if a memory bank is configured to be 32 bits wide, address lines a0 and a1 can be used as non-address lines. if a memory bank is configured to 16 bits wide, a0 is not required. however, 8 bit wide memory banks do require all address lines down to a0. configuring the a1 and/or a0 lines to provide address or non-address function is accomplished using the iocon registers (see section 7.4.1 ). symbol "a_b" in the following figures refers to the highest order address line in the data bus. symbol "a_m" refers to the highest order address line of the memory chip used in the external memory interface. 9.14.1 32-bit wide memory bank connection a. 32 bit wide memory bank interfaced to four 8 bit memory chips b. 32 bit wide memory bank interfaced to two 16 bit memory chips a[a_b:2] bls[1] d[15:8] ce oe we io[7:0] a[a_m:0] bls[0] d[7:0] ce oe we io[7:0] a[a_m:0] oe cs bls[3] d[31:24] ce oe we io[7:0] a[a_m:0] bls[2] d[23:16] ce oe we io[7:0] a[a_m:0] oe cs we ce oe we ub lb io[15:0] a[a_m:0] d[31:16] bls[2] ce oe we ub lb io[15:0] a[a_m:0] d[15:0] bls[0] a[a_b:2] bls[3] bls[1]
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 197 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.14.2 16-bit wide memory bank connection c. 32 bit wide memory bank interfaced to one 8 bit memory chip fig 18. 32 bit bank external memory interfaces ( bits mw = 10) oe cs we ce oe we b3 b2 b1 b0 io[31:0] a[a_m:0] d[31:0] bls[2] a[a_b:2] bls[3] bls[0] bls[1] a. 16 bit wide memory bank interfaced to two 8 bit memory chips b. 16 bit wide memory bank interfaced to a 16 bit memory chip fig 19. 16 bit bank external memory interfaces (bits mw = 01) oe cs bls[1] d[15:8] ce oe we io[7:0] a[a_m:0] bls[0] d[7:0] ce oe we io[7:0] a[a_m:0] a[a_b:1] oe cs we ce oe we ub lb io[15:0] a[a_m:0] d[15:0] bls[0] a[a_b:1] bls[1]
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 198 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.14.3 8-bit wide memory bank connection fig 20. 8 bit bank external memory interface (bits mw = 00) oe cs we d[7:0] ce oe we io[7:0] a[a_m:0] a[a_b:0]
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 199 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.14.4 memory configuration example fig 21. typical memory configuration diagram nce noe q[31:0] a[20:0] nce noe io[15:0] a[15:0] nwe nub nlb nce noe io[15:0] a[15:0] nwe nub nlb nce noe io[7:0] a[16:0] nwe nce noe io[7:0] a[16:0] nwe nce noe io[7:0] a[16:0] nwe nce noe io[7:0] a[16:0] nwe 2mx32 burst mask rom 64kx16 sram, two off 128kx8 sram, four off a[20:0] a[20:0] d[31:0] d[31:0] cs0 oe cs1 cs2 we bls3 bls2 bls1 bls0 a[16:0] a[16:0] a[16:0] a[16:0] a[15:0] a[15:0] d[31:16] d[15:0] d[31:24] d[23:16] d[15:8] d[7:0]
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 200 of 942 10.1 basic configuration the ethernet controller is configur ed using the following registers: 1. power: in the pconp register ( section 3.3.2.2 ), set bit pcenet. remark: on reset, the ethernet block is disabled (pcenet = 0). 2. clock: see section 3.3.3.2 . 3. pins: enable ethernet pins and select th eir modes through the iocon registers, see section 7.4.1 . 4. wake-up: activity on the ethernet po rt can wake up the microcontroller from power-down mode, see section 3.12.8 . 5. interrupts: inte rrupts are enabled in the nvic using the appropriate interrupt set enable register. 6. initialization: see section 10.13.2 . 10.2 introduction the ethernet block contains a full featured 10 mbps or 100 mbps ethernet mac (media access controller) designed to provide opti mized performance thro ugh the use of dma hardware acceleration. features include a generous suite of control registers, half or full duplex operation, flow control, control fram es, hardware acceleration for transmit retry, receive packet filtering and wake-up on lan activity. automatic frame transmission and reception with scatter-gather dma off-loads many operations from the cpu. the ethernet block is an ahb master that dr ives the ahb bus matrix . through the matrix, it has access to all on-chip ram memories. a recommended use of ram by the ethernet is to use one of the ram blocks exclusively for ethernet traffic. that ram would then be accessed only by the ethernet and the cpu, and possibly the gpdma, giving maximum bandwidth to the ethernet function. the ethernet block interfaces between an off-chip ethernet phy using the mii (media independent interface) or rmii (reduced mii) protocol and the on-chip miim (media independent interface management) serial bus, also referred to as mdio (management data input/output). UM10562 chapter 10: lpc408x/407x ethernet rev. 1 ? 13 september 2012 user manual table 143. ethernet acronyms, abbreviations, and definitions acronym or abbreviation definition ahb advanced high-performance bus crc cyclic redundancy check dma direct memory access double-word 64-bit entity fcs frame check sequence (crc) fragment a (part of an) ethernet frame; one or multip le fragments can add up to a single ethernet frame.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 201 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.3 features ? ethernet standards support: ? supports 10 or 100 mbps phy devices including 10 base-t, 100 base-tx, 100 base-fx, and 100 base-t4. ? fully compliant with ieee standard 802.3. ? fully compliant with 802.3x full duplex flow control and half duplex back pressure. ? flexible transmit and receive frame options. ? vlan frame support. ? memory management: ? independent transmit and receive buffers memory mapped to shared sram. ? dma managers with scatter/gather dma and arrays of frame descriptors. ? memory traffic optimized by buffering and prefetching. ? enhanced ethernet features: ? receive filtering. ? multicast and broadcast frame suppor t for both transmit and receive. ? optional automatic fcs inse rtion (crc) for transmit. ? selectable automatic transmit frame padding. frame an ethernet frame consists of destination address, source address, length type field, payload and frame check sequence. half-word 16-bit entity lan local area network mac media access control sublayer mii media independent interface miim mii management octet an 8-bit data entity, used in lieu of "byte" by ieee 802.3 packet a frame that is transported across ethernet; a packet consists of a preamble, a start of frame delimiter and an ethernet frame. phy ethernet physical layer rmii reduced mii rx receive tcp/ip transmission control protocol / internet protocol. the most common high-level protocol used with ethernet. tx transmit vlan virtual lan wol wake-up on lan word 32-bit entity table 143. ethernet acronyms, abbreviations, and definitions acronym or abbreviation definition
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 202 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet ? over-length frame support for both transmit and receive allows any length frames. ? promiscuous receive mode. ? automatic collision backoff and frame retransmission. ? includes power management by clock switching. ? wake-on-lan power management support allows system wake-up: using the receive filters or a magic frame detection filter. ? physical interface: ? attachment of external phy chip thro ugh standard media independent interface (mii) or standard reduced mii (rmii) interface, soft ware selectable. ? phy register access is available via t he media independent interface management (miim) interface. 10.4 architecture and operation figure 22 shows the internal architecture of the ethernet block. the block diagram for the ethernet block consists of: ? the host registers module containing the registers in the software view and handling ahb accesses to the ethernet block. the ho st registers connect to the transmit and receive data path as well as the mac. ? the dma to ahb interface. this provides an ahb master connection that allows the ethernet block to access on-chip sram for re ading of descriptors, writing of status, and reading and writing data buffers. ? the ethernet mac, which interfaces to the off-chip phy via an mii or rmii interface. ? the transmit data path, including: fig 22. ethernet block diagram register interface (ahb slave) dma interface (ahb master) bus interface receive dma transmit dma receive buffer receive filter transmit retry transmit flow control ethernet mac rmii a dap ter rmii miim host registers ahb bus ethernet block et he rn et phy bus interface
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 203 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet ? the transmit dma manager which reads descriptors and data from memory and writes status to memory. ? the transmit retry module handling ethernet retry and abort situations. ? the transmit flow control module whic h can insert ethernet pause frames. ? the receive data path, including: ? the receive dma manager which reads desc riptors from memory and writes data and status to memory. ? the ethernet mac which detects frame types by parsing pa rt of the frame header. ? the receive filter which can filter out certain ethernet frames by applying different filtering schemes. ? the receive buffer implementing a delay fo r receive frames to allow the filter to filter out certain frames before storing them to memory. 10.5 dma engine functions the ethernet block is designed to provi de optimized performance via dma hardware acceleration. independent scatter/gather dma engines connected to the ahb bus off-load many data transfers from the cpu. descriptors, which are stored in memory, contain information about fragments of incoming or outgoing ethernet frames. a fragment may be an entire frame or a much smaller amount of data. each descriptor contains a pointer to a memory buffer that holds data associated with a fragment, the size of the fragment buffer, and details of how the fragment will be tr ansmitted or received. descriptors are stored in arrays in memory, which are located by pointer registers in the ethernet block. other registers determine t he size of the arrays, point to the next descriptor in each array that will be used by the dma engine, and point to the next descriptor in each array that will be used by the ethern et device driver. 10.6 overview of dma operation the dma engine makes use of a receive descriptor array and a transmit descriptor array in memory. all or part of an ethernet frame may be contained in a memory buffer associated with a descriptor. when transmitting, the transmit dma engine uses as many descriptors as needed (one or more) to obtain (gather) all of the parts of a frame, and sends them out in sequence. when receiving, the receive dma engine also uses as many descriptors as needed (one or more) to find plac es to store (scatter) all of the data in the received frame. the base address registers for the descriptor array, registers indicating the number of descriptor array entries, and descriptor arra y input/output pointers are contained in the ethernet block. the descriptor entries and all transmit and receive packet data are stored in memory which is not a part of the ether net block. the descriptor entries tell where related frame data is stored in memory, certai n aspects of how the data is handled, and the result status of each ethernet transaction.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 204 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet hardware in the dma engine controls how data incoming from the ethernet mac is saved to memory, causes fragment related status to be saved, and advances the hardware receive pointer for incomi ng data. driver software must handle the disposition of received data, changing of descriptor data addresses (to avoid unnecessary data movement), and advancing the software receive pointer. the tw o pointers create a circular queue in the descriptor array and allow both the dma hardwa re and the driver software to know which descriptors (if any) are available for their use, including whether the descriptor array is empty or full. similarly, driver software must set up pointe rs to data that will be transmitted by the ethernet mac, giving instructions for each fr agment of data, and advancing the software transmit pointer for outgoing data. hardware in the dma engine reads this information and sends the data to the ethernet mac interface when possible, updating the status and advancing the hardware transmit pointer. 10.7 ethernet packet figure 23 illustrates the different fiel ds in an ethernet packet. a packet consists of a preamble, a start-of-frame delimiter and an ethernet frame. fig 23. ethernet packet fields optional vlan source address desa oct6 desa oct1 desa oct2 desa oct3 desa oct4 desa oct5 srca oct6 srca oct5 srca oct4 srca oct3 srca oct2 srca oct1 lsb oct(0) oct(1) oct(2) oct(3) oct(4) oct(5) oct(6) msb oct(7) destination address payload fcs ethernet frame preamble 7 bytes ethernet packet start-of-frame delimiter 1 byte time len type
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 205 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet the ethernet frame consists of the destinat ion address, the source address, an optional vlan field, the length/type field, the payload and the frame check sequence. each address consists of 6 bytes where each by te consists of 8 bits. bits are transferred starting with the least significant bit. 10.8 overview 10.8.1 partitioning the ethernet block and associated device driver software offer the functionality of the media access control (mac) sublayer of the data link layer in the osi reference model (see ieee std 802.3). the mac sublayer offe rs the service of transmitting and receiving frames to the next higher protocol level, the mac client layer, typically the logical link control sublayer. the device driver software implements the interface to the mac client layer. it sets up registers in the ethernet bl ock, maintains descriptor arrays pointing to frames in memory and receives results back from the ethernet block through interrupts. when a frame is transmitted, the software partially sets up the ethernet frames by providing pointers to the destination address field, source address field, the length/type field, the mac client data field and optionally the crc in the frame check sequence field. preferably concatenation of frame fields s hould be done by using the scatter/gather functionality of the ethernet core to avoid unnecessary copying of data. the hardware adds the preamble and start frame delimiter fields and can optionally add the crc, if requested by software. when a packet is re ceived the hardware strips the preamble and start frame delimiter and passes the rest of th e packet - the ethernet frame - to the device driver, including destination address, source a ddress, length/type field, mac client data and frame check sequence (fcs). apart from the mac, the ethernet block contai ns receive and transmit dma managers that control receive and transmit data stream s between the mac and the ahb interface. frames are passed via descriptor arrays locat ed in host memory, so that the hardware can process many frames without software/cpu support. frames can consist of multiple fragments that are accessed with scatter/gather dma. the dma managers optimize memory bandwidth using prefetching and buffering. a receive filter block is used to identify rece ived frames that are not addressed to this ethernet station, so that they can be discar ded. the rx filters include a perfect address filter and a hash filter. wake-on-lan power management support makes it possible to wake the system up from a power-down state -a state in which some of the clocks are switched off -when wake-up frames are received over the lan. wake-up fr ames are recognized by the receive filtering modules or by a magic frame detection technology. system wake-up occurs by triggering an interrupt. an interrupt logic block raises and masks interrupts and keeps track of the cause of interrupts. the interrupt block sends an inte rrupt request signal to the host system. interrupts can be enabled, cleared and set by software.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 206 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet support for ieee 802.3/clause 31 flow control is implemented in the flow control block. receive flow control frames are automatically handled by the mac. transmit flow control frames can be initiated by software. in half duplex mode, the flow control module will generate back pressure by sending out continuous preamble only, interrupted by pauses to prevent the jabber limit from being exceeded. the ethernet block has both a standard media independent interface (mii) bus and a reduced media independent interface (rmii) to connect to an external ethernet phy chip. mii or rmii mode can be selected by the rmii bit in the command register. the standard nibble-wide mii interface allows a low speed data connection to the phy chip: 2.5 mhz at 10 mbps or 25 mhz at 100 mbps. the rmii interface allows a low pin count double clock data connection to the phy. registers in the phy chip are accessed via the ahb interface through the serial management connection of the miim bus, typically operating at 2.5 mhz. 10.8.2 example phy devices some examples of compatible phy devices are shown in ta b l e 1 4 4 . table 144. example phy devices manufacturer part numbers broadcom bcm5221 ics ics1893 intel lxt971a lsi logic l80223, l80225, l80227 micrel ks8721 national dp83847, dp83846, dp83843 smsc lan83c185
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 207 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.9 pin description table 145 shows the signals used for connecting the media independent interface (mii), and table 146 shows the signals used for connecting the reduced media independent interface (rmii) to the external phy. table 147 shows the signals used for media independent interface management (miim) to the external phy. table 145. ethernet mii pin descriptions pin name type pin description enet_tx_en output transmit data enable, active low. enet_txd3:0 output transmit data, 4 bits. enet_tx_er output transmit error. enet_tx_clk input transmitter clock. enet_rx_dv input receive data valid. enet_rxd3:0 input receive data, 4 bits. enet_rx_er input receive error. enet_rx_clk input receive clock. enet_col input collision detect. enet_crs input carrier sense. table 146. ethernet rmii pin descriptions pin name type pin description enet_tx_en output transmit data enable, active low. enet_txd1:0 output transmit data, 2 bits enet_rxd1:0 input receive data, 2 bits. enet_rx_er input receive error. enet_crs input enet_crs_dv. carrier sense/data valid. enet_rx_clk input enet_ref_clk. reference clock. table 147. ethernet miim pin descriptions pin name type pin description enet_mdc output miim clock. enet_mdio input/output mi data input and output
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 208 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.10 register description the software interface of the ethernet block c onsists of a register view and the format definitions for the transmit and receive descri ptors. these two aspects are addressed in the next two subsections. the total ahb address space required for the ethernet is 4 kilobytes. after a hard reset or a soft reset via the regreset bit of the command register all bits in all registers are reset to 0 unless stated othe rwise in the following register descriptions. some registers will have unused bi ts which will return a 0 on a read via the ahb interface. writing to unused register bits of an otherwise writable regist er will not have side effects. the register map consists of registers in t he ethernet mac and registers around the core for controlling dma transfers, flow control and filtering. reading from reserved addresses or reserved bits leads to unpredictable data. writing to reserved addresses or reserved bits has no effect. reading of write-only register s will return a read error on the ahb interface. writing of read-only registers will return a write error on the ahb interface. table 148. register overview: ethernet (base address 0x2008 4000) name access address offset description reset value table mac registers mac1 r/w 0x000 mac configuration register 1. 0x8000 149 mac2 r/w 0x004 mac configuration register 2. 0 150 ipgt r/w 0x008 back-to-back in ter-packet-gap register. 0 152 ipgr r/w 0x00c non back-to-back inter-packet-gap register. 0 153 clrt r/w 0x010 collision window / retry register. 0x370f 154 maxf r/w 0x014 maximum frame register. 0x0600 155 supp r/w 0x018 phy support register. 0 156 test r/w 0x01c test register. 0 157 mcfg r/w 0x020 mii mgmt configuration register. 0 158 mcmd r/w 0x024 mii mgmt command register. 0 160 madr r/w 0x028 mii mgmt address register. 0 161 mwtd wo 0x02c mii mgmt write data register. - 162 mrdd ro 0x030 mii mgmt read data register. 0 163 mind ro 0x034 mii mgmt indicators register. 0 164 sa0 r/w 0x040 station address 0 register. 0 165 sa1 r/w 0x044 station address 1 register. 0 166 sa2 r/w 0x048 station address 2 register. 0 167 control registers command r/w 0x100 command register. 0 168 status ro 0x104 status register. 0 169 rxdescriptor r/w 0x108 receive descriptor base address register. 0 170
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 209 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet the third column in the table lists the accessibility of the re gister: read-only , write-only, read/write. all ahb register write transactions except for accesses to the interrupt registers are posted i.e. the ahb tran saction will complete be fore write data is act ually committed to the register. accesses to the inte rrupt registers will only be co mpleted by accepting the write data when the data has been committed to the register. rxstatus r/w 0x10c receive status base address register. 0 171 rxdescriptornumber r/w 0x110 receive number of descriptors register. 0 172 rxproduceindex ro 0x114 receive produce index register. 0 173 rxconsumeindex r/w 0x118 receive consume index register. 0 174 txdescriptor r/w 0x11c transmit descriptor base address register. 0 175 txstatus r/w 0x120 transmit status base address register. 0 176 txdescriptornumber r/w 0x124 transmit number of descriptors register. 0 177 txproduceindex r/w 0x128 transmi t produce index register. 0 178 txconsumeindex ro 0x12c transmit consume index register. 0 179 tsv0 ro 0x158 transmit status vector 0 register. 0 180 tsv1 ro 0x15c transmit status vector 1 register. 0 181 rsv ro 0x160 receive status vector register. 0 182 flowcontrolcounter r/w 0x170 flow control coun ter register. 0 183 flowcontrolstatus ro 0x174 flow control status register. 0 184 rx filter registers rxfilterctrl r/w 0x200 receive filter control register. 0 185 rxfilterwolstatus ro 0x204 receive filter wol status register. 0 186 rxfilterwolclear wo 0x208 receive filter wol clear register. - 187 hashfilterl r/w 0x210 hash filter table lsbs register. 0 188 hashfilterh r/w 0x214 hash filter table msbs register. 0 189 module control registers intstatus ro 0xfe0 interrupt status register. 0 190 intenable r/w 0xfe4 interrupt enable register. 0 191 intclear wo 0xfe8 interrupt clear register. - 192 intset wo 0xfec interrupt set register. - 193 powerdown r/w 0xff4 power-down register. 0 194 table 148. register overview: ethernet (base address 0x2008 4000) name access address offset description reset value table
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 210 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.10.1 ethernet mac register definitions this section defines the bits in the individual registers of the ethernet block register map. 10.10.1.1 mac configuration register 1 the mac configuration register 1 (mac1) has an address of 0x2008 4000. its bit definition is shown in table 149 . table 149. mac configuration register 1 (mac1 - address 0x2008 4000) bit description bit symbol function reset value 0 rxenable receive enable. set this to allow receive frames to be received. internally the mac synchronizes this control bit to the incoming receive stream. 0 1 parf pass all receive frames. when enabled (set to 1), t he mac will pass all frames regardless of type (normal vs. control). when disabled, the mac does not pass valid control frames. 0 2 rxflowctrl rx flow control. when enabled (set to 1), the mac acts upon received pause flow control frames. when disabled, received pause flow control frames are ignored. 0 3 txflowctrl tx flow control. when enabled (set to 1), pause flow control frames are allowed to be transmitted. when disabled, flow control frames are blocked. 0 4 loopback setting this bit will cause the mac transmit interface to be looped back to the mac receive interface. clearing this bit results in normal operation. 0 7:5 - unused 0 8 resettx setting this bit will put the transmit function logic in reset. 0 9 resetmcstx setting this bit resets the mac cont rol sublayer / transmit logic. the mcs logic implements flow control. 0 10 resetrx setting this bit will put t he ethernet receive logic in reset. 0 11 resetmcsrx setting this bit resets the mac cont rol sublayer / receive logic. the mcs logic implements flow control. 0 13:12 - reserved. read value is undefined, only zero should be written. 0 14 simreset simulation reset. settin g this bit will cause a reset to the random nu mber generator within the transmit function. 0 15 softreset soft reset. setting this bit will put all modules within the mac in reset except the host interface. 1 31:16 - reserved. read value is undefined, only zero should be written. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 211 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.10.1.2 mac configuration register 2 table 150. mac configuration register 2 (mac2 - address 0x2008 4004) bit description bit symbol function reset value 0 fullduplex when enabled (set to 1), the mac operates in full-duplex mode. when disabled, the mac operates in half-duplex mode. 0 1 flc framelength checking. when enabled (set to 1), both transmit and receive frame lengths are compared to the length/type field. if the length/type field represents a length then the check is per formed. mismatches are reported in the statusinfo word for each received frame. 0 2 hfen huge frame enable. when enabled (set to 1), frames of any length are transmitted and received. 0 3 delayedcrc delayed crc. this bit determines the number of bytes, if any, of proprietary header information that exist on the front of ieee 802.3 frames. when 1, four bytes of header (ignored by the crc function) are added. when 0, there is no proprietary header. 0 4 crcen crc enable. set this bit to append a crc to every frame whether padding was required or not. must be set if pad/crc en able is set. clear this bit if frames presented to the mac contain a crc. 0 5 padcrcen pad crc enable. set this bit to have the mac pad all short frames. clear this bit if frames presented to the mac have a valid length. this bit is used in conjunction with auto pad enable and vlan pad enable. see table 152 - pad operation for details on the pad function. 0 6 vlanpaden vlan pad enable. set this bit to caus e the mac to pad all short frames to 64 bytes and append a valid crc. consult table 152 - pad operation for more information on the various padding features. note: this bit is ignored if pad / crc enable is cleared. 0 7 autodetpaden autodetectpad enable. set this bit to cause the mac to automatically detect the type of frame, either tagged or un-tagged, by comparing the two octets following the source address with 0x8100 (vlan protocol id) and pad accordingly. table 152 - pad operation provides a description of the pad f unction based on the configuration of this register. note: this bit is ignored if pad / crc enable is cleared. 0 8 ppenf pure preamble enforcement . when enabled (set to 1) , the mac will verify the content of the preamble to ensure it contains 0x55 and is error-free. a packet with an incorrect preamble is discarded. when disabled, no preamble checking is performed. 0 9 lpenf long preamble enforcement. when enabled (set to 1), the mac only allows receive packets which contain preamble fields less than 12 bytes in length. when disabled, the mac allows any length preamble as per the standard. 0 11:10 - reserved. read value is undefined, only zero should be written. 0 12 nobackoff when enabled (set to 1), the mac will immediately retransmit following a collision rather than using the binary exponential backoff algorithm as specified in the standard. 0 13 bp_nobackoff back pressure / no backoff. when enabled (set to 1), after the mac incidentally causes a collision during back pressure, it will immediately retransmit without backoff, reducing the chance of further collisions and ensuring transmit packets get sent. 0 14 excessdefer when enabled (set to 1) the mac will defer to carrier indefinitely as per the standard. when disabled, the mac will abort when the excessive deferral limit is reached. 0 31:15 - reserved. read value is undefined, only zero should be written. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 212 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.10.1.3 back-to-back inter-packet-gap register 10.10.1.4 non back-to-back inter-packet-gap register table 151. pad operation type auto detect pad enable mac2 [7] vlan pad enable mac2 [6] pad/crc enable mac2 [5] action any x x 0 no pad or crc check any 0 0 1 pad to 60 bytes, append crc any x 1 1 pad to 64 bytes, append crc any 1 0 1 if untagged, pad to 60 bytes and append crc. if vlan tagged: pad to 64 bytes and append crc. table 152. back-to-back inter-packet-gap register (ipgt - address 0x2008 4008) bit description bit symbol function reset value 6:0 btobintegap back-to-back inter-packet-gap.this is a programmable field representing the nibble time offset of the minimum possible period between the end of any transmitted packet to the beginning of the next. in full-duplex mode, the register value should be the desired period in nibble times minus 3. in half-duplex mode, the register value should be the desired period in nibble times minus 6. in full-duplex the recommended setting is 0x15 (21d), which represents the minimum ip g of 960 ns (in 100 mbps mode) or 9.6 s (in 10 mbps mode). in half-duplex the recommended setting is 0x12 (18d), which also represents the minimum ipg of 960 ns (in 100 mbps mode) or 9.6 s (in 10 mbps mode). 0 31:7 - reserved. read value is undefined, only zero should be written. 0 table 153. non back-to-back inter-packet-gap register (ipgr - address 0x2008 400c) bit description bit symbol function reset value 6:0 nbtobintegap2 non-back-to-back inter-packet -gap part2. this is a programmable field representing the non-back-to-back inter-packet-gap. the recommended value is 0x12 (18d), which represents the minimum ipg of 960 ns (in 100 mbps mode) or 9.6 s (in 10 mbps mode). 0 7 - reserved. read value is undefined, only zero should be written. 0 14:8 nbtobintegap1 non-back-to-back inter-packet -gap part1. this is a programmable field representing the optional carriersense wind ow referenced in ieee 802.3/4. 2.3.2.1 'carrier deference'. if carrier is detected during the timing of ipgr1, the mac defers to carrier. if, however, carrier becomes active after ipgr1, the mac continues timing ipgr2 and transmits, knowingly causing a collision, thus ensuring fair access to medium. its range of values is 0x0 to ipgr2. the recommended value is 0xc (12d) 0 31:15 - reserved. read value is undefined, only zero should be written. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 213 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.10.1.5 collision window / retry register 10.10.1.6 maximum frame register 10.10.1.7 phy support register the supp register provides additional control over the rmii interface. unused bits in the phy support register should be left as zeroes. table 154. collision window / retry register (clrt - address 0x2008 4010) bit description bit symbol function reset value 3:0 retransmax retransmission maximum.this is a programmable field specifying the number of retransmission attempts following a collision before aborting the packet due to excessive collisions. the standard specifies the attemptlimit to be 0xf (15d). see ieee 802.3/4.2.3.2.5. 0xf 7:4 - reserved. read value is undefined, only zero should be written. 0 13:8 collwin collision window. this is a progra mmable field representing the slot time or collision window during which collisions occur in properly configured networks. the default value of 0x37 (55d) represents a 56 byte window following the preamble and sfd. 0x37 31:14 - reserved. read value is undefined, only zero should be written. na table 155. maximum frame register (maxf - address 0x2008 4014) bit description bit symbol function reset value 15:0 maxflen maximum frame length. this field resets to the value 0x0600, which represents a maximum receive frame of 1536 octets. an untagged maximum size ethernet frame is 1518 octets. a tagged frame adds four octets for a total of 1522 octets. if a shorter maximum length restriction is desired, program this 16-bit field. 0x0600 31:16 - unused 0 table 156. phy support register (supp - address 0x2008 4018) bit description bit symbol function reset value 7:0 - unused 0 8 speed this bit configures the reduced mii logi c for the current operating speed. when set, 100 mbps mode is selected. when cleared, 10 mbps mode is selected. 0 31:9 - unused 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 214 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.10.1.8 test register 10.10.1.9 mii mgmt configuration register table 157. test register (test - address 0x2008 401c) bit description bit symbol function reset value 0 scpq shortcut pause quanta. this bit reduces the effective pause quanta from 64 byte-times to 1 byte-time. 0 1 testpause this bit causes the mac control sublayer to inhibit transmissions, just as if a pause receive control frame with a nonzero pause time parameter was received. 0 2 testbp test backpressure. setting this bit will c ause the mac to assert backpressure on the link. backpressure causes preamble to be transmitted, raising carrier sense. a transmit packet from the system will be sent during backpressure. 0 31:3 - unused 0 table 158. mii mgmt configuration register (mcfg - address 0x2008 4020) bit description bit symbol function reset value 0 scaninc scan increment. set this bit to c ause the mii management hardware to perform read cycles across a range of phys. when set, the mii management hardware will perform read cycles from address 1 through the value set in phy address[4:0]. clear this bit to allow continuous reads of the same phy. 0 1 supppreamble suppress preamble. set this bit to cause the mii manage ment hardware to perform read/write cycles with out the 32-bit preamble field. clear this bit to cause normal cycles to be performed. some phys support suppressed preamble. 0 5:2 clocksel clock select. this field is used by the clock divide logic in creating the mii management clock (mdc) which ieee 802.3u defines to be no faster than 2.5 mhz. some phys support clock rates up to 12 .5 mhz, however. the ahb bus clock (hclk) is divided by the specified amount. refer to table 159 below for the definition of values for this field. 0 14:6 - unused 0 15 resetmiimgmt reset mii mgmt. this bit resets the mii m anagement hardware. 0 31:16 - unused 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 215 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet [1] the maximum ahb clock rate allowed is limited to the maximum cpu clock rate for the device. 10.10.1.10 mii mgmt command register 10.10.1.11 mii mgmt address register table 159. clock select encoding clock select bit 5 bit 4 bit 3 bit 2 maximum ahb clock supported host clock divided by 4 0 0 0 x 10 host clock divided by 6 0 0 1 0 15 host clock divided by 8 0 0 1 1 20 host clock divided by 10 0 1 0 0 25 host clock divided by 14 0 1 0 1 35 host clock divided by 20 0 1 1 0 50 host clock divided by 28 0 1 1 1 70 host clock divided by 36 1 0 0 0 80 [1] host clock divided by 40 1 0 0 1 90 [1] host clock divided by 44 1 0 1 0 100 [1] host clock divided by 48 1 0 1 1 120 [1] host clock divided by 52 1 1 0 0 130 [1] host clock divided by 56 1 1 0 1 140 [1] host clock divided by 60 1 1 1 0 150 [1] host clock divided by 64 1 1 1 1 160 [1] table 160. mii mgmt command register (mcmd - address 0x2008 4024) bit description bit symbol function reset value 0 read this bit causes the mii management hardware to perform a single read cycle. the read data is returned in register mrdd (mii mgmt read data). 0 1 scan this bit causes the mii ma nagement hardware to perform read cycles continuously. this is useful for monitoring link fail for example. 0 31:2 - unused 0 table 161. mii mgmt address register (madr - address 0x2008 4028) bit description bit symbol function reset value 4:0 regaddr register address. this field represents the 5-bit register address field of mgmt cycles. up to 32 registers can be accessed. 0 7:5 - unused 0 12:8 phyaddr phy address. this field represents the 5-bit phy address field of mgmt cycles. up to 31 phys can be addressed (0 is reserved). 0 31:13 - unused 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 216 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.10.1.12 mii mgmt write data register 10.10.1.13 mii mgmt read data register 10.10.1.14 mii mgmt indicators register here are two examples to access phy via the mii management controller. for phy write if scan is not used: 1. write 0 to mcmd 2. write phy address and register address to madr 3. write data to mwtd 4. wait for busy bit to be cleared in mind for phy read if scan is not used: 1. write 1 to mcmd 2. write phy address and register address to madr 3. wait for busy bit to be cleared in mind 4. write 0 to mcmd 5. read data from mrdd table 162. mii mgmt write data register (mwtd - address 0x2008 402c) bit description bit symbol function 15:0 writedata write data. when written, an mii mgmt write cycle is performed using the 16-bit data and the pre-configured phy and register addresses from the mii mgmt address register (madr). 31:16 - unused table 163. mii mgmt read data register (mrdd - address 0x2008 4030) bit description bit symbol function reset value 15:0 readdata read data. following an mii mgmt read cycle, the 16-bit data can be read from this location. 0 31:16 - unused 0 table 164. mii mgmt indicators register (mind - address 0x2008 4034) bit description bit symbol function reset value 0 busy when 1 is returned - indicates mii mgmt is currently performing an mii mgmt read or write cycle. 0 1 scanning when 1 is returned - indicates a scan operation (continuous mii mgmt read cycles) is in progress. 0 2 notvalid when 1 is returned - indicates mii mg mt read cycle ha s not completed and the read data is not yet valid. 0 3 miilinkfail when 1 is returned - indicates that an mii mgmt link fail has occurred. 0 31:4 - unused 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 217 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.10.1.15 station address 0 register the station address is used for perfect addr ess filtering and for sending pause control frames. for the ordering of the octets in the packet please refer to figure 23 . 10.10.1.16 station address 1 register the station address is used for perfect addr ess filtering and for sending pause control frames. for the ordering of the octets in the packet please refer to figure 23 . 10.10.1.17 station address 2 register the station address is used for perfect addr ess filtering and for sending pause control frames. for the ordering of the octets in the packet please refer to figure 23 . table 165. station address register (sa0 - address 0x2008 4040) bit description bit symbol function reset value 7:0 saddr2 station address, 2nd octet. this field hol ds the second octet of the station address. 0 15:8 saddr1 station address, 1st octet. this field holds the first octet of the station address. 0 31:16 - unused 0 table 166. station address register (sa1 - address 0x2008 4044) bit description bit symbol function reset value 7:0 saddr4 station address, 4th octet. this field holds the fourth octet of the station address. 0 15:8 saddr3 station address, 3rd octet. this field ho lds the third octet of the station address. 0 31:16 - unused 0 table 167. station address register (sa2 - address 0x2008 4048) bit description bit symbol function reset value 7:0 saddr6 station address, 6th octet. this field holds the sixth octet of the station address. 0 15:8 saddr5 station address, 5th octet. this field holds the fifth octet of the station address. 0 31:16 - unused 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 218 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.10.2 control re gister definitions 10.10.2.1 command register all bits can be written and read . the tx/rxreset bits are writ e-only, reading will return a 0. 10.10.2.2 status register the status register (status) is a read-only register. the values represent the status of the two ch annels/data paths. when the status is 1, the channel is active, meaning: ? it is enabled and the rx/txenable bit is se t in the command register or it just got disabled while still transmit ting or receiving a frame. ? also, for the transmit channel, the transmit queue is not empty i.e. produceindex != consumeindex. ? also, for the receive channel, the receive queue is not full i.e. produceindex != consumeindex - 1. table 168. command register (command - address 0x2008 4100) bit description bit symbol function reset value 0 rxenable enable receive. 0 1 txenable enable transmit. 0 2 - unused 0 3 regreset when a 1 is written, all datapaths and the host registers ar e reset. the mac needs to be reset separately. 0 4 txreset when a 1 is written, the transmit datapath is reset. - 5 rxreset when a 1 is written, the receive datapath is reset. - 6 passruntframe when set to 1 , passes runt frames s1maller than 64 bytes to memory unless they have a crc error. if 0 runt frames are filtered out. 0 7 passrxfilter when set to 1 , disables receive filtering i.e. all frames received are written to memory. 0 8 txflowcontrol enable ieee 802.3 / clause 31 flow control sending pause frames in full duplex and continuous preamble in half duplex. 0 9 rmii when set to 1 , rmii mode is selected; if 0, mii mode is selected. 0 10 fullduplex when set to 1 , indicates full duplex operation. 0 31:11 - unused 0 table 169. status register (status - address 0x2008 4104) bit description bit symbol function reset value 0 rxstatus if 1, the receive channel is active. if 0, the receive channel is inactive. 0 1 txstatus if 1, the transmit channel is active. if 0, the transmit channel is inactive. 0 31:2 - unused 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 219 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet the status transitions from active to inactive if the channel is disabled by a software reset of the rx/txenable bit in the command regist er and the channel has committed the status and data of the current frame to memory. the status also transitions to inactive if the transmit queue is empty or if the receive queue is full and status and data have been committed to memory. 10.10.2.3 receive descriptor base address register the receive descriptor base address is a byte address aligned to a word boundary i.e. lsb 1:0 are fixed to ?00?. the register contains the lowest address in the array of descriptors. 10.10.2.4 receive status base address register the receive descriptor base address is a byte address aligned to a word boundary i.e. lsb 1:0 are fixed to ?00?. the register contains the lowest address in the array of descriptors. the receive status base address is a byte ad dress aligned to a double word boundary i.e. lsb 2:0 are fixed to ?000?. 10.10.2.5 receive number of descriptors register the receive number of descriptors register defines the number of descriptors in the descriptor array for which rxdescriptor is the base address. the number of descriptors should match the number of statuses. the r egister uses minus one encoding i.e. if the array has 8 elements, the value in the register should be 7. 10.10.2.6 receive produce index register table 170. receive descriptor base address register (rxdescriptor - address 0x2008 4108) bit description bit symbol function reset value 1:0 - fixed to 00 - 31:2 rxdescriptor msbs of receive descriptor base address. 0 table 171. receive status base address register (rxstatus - address 0x2008 410c) bit description bit symbol function reset value 2:0 - fixed to 000 - 31:3 rxstatus msbs of receive status base address. 0 table 172. receive number of desc riptors register (rxdescriptornumber - address 0x2008 4110) bit description bit symbol function reset value 15:0 rxdescriptorn rxdescriptornumber. number of descriptors in the descriptor array for which rxdescriptor is the base address. the number of descriptors is minus one encoded. 0 31:16 - unused 0 table 173. receive produce index register (rxproduceindex - address 0x2008 4114) bit description bit symbol function reset value 15:0 rxproduceix index of the descriptor that is going to be filled next by the receive datapath. 0 31:16 - unused 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 220 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet the receive produ ce index regist er defines the descriptor that is going to be filled next by the hardware receive process. after a frame ha s been received, hardware increments the index. the value is wrapped to 0 once the value of rxdescriptornumber has been reached. if the rxproduceindex equals rxco nsumeindex - 1, the array is full and any further frames being received will cause a buffer overrun error. 10.10.2.7 receive consume index register the receive consume register defines the descr iptor that is going to be processed next by the software receive driver. the receive array is empty as long as rxproduceindex equals rxconsumeindex. as soon as the array is not empty, software can process the frame pointed to by rxconsumeindex. after a frame has been processed by software, software should increment the rxconsumeindex. the value must be wrapped to 0 once the value of rxdescriptornumber has been reache d. if the rxproduceindex equals rxconsumeindex - 1, t he array is full and any further frames being received will cause a buffer overrun error. 10.10.2.8 transmit descriptor base address register the transmit descriptor base address is a by te address aligned to a word boundary i.e. lsb 1:0 are fixed to ?00?. the register contains the lowest address in the array of descriptors. 10.10.2.9 transmit status base address register the transmit status base address is a byte address aligned to a word boundary i.e. lsb 1:0 are fixed to ?00?. the register contains the lowest address in the array of statuses. 10.10.2.10 transmit number of descriptors register table 174. receive consume index register (rxconsumeindex - address 0x2008 4118) bit description bit symbol function reset value 15:0 rxconsumeix index of the descriptor that is going to be processed next by the receive 31:16 - unused 0 table 175. transmit descriptor base address register (txdescriptor - address 0x2008 411c) bit description bit symbol function reset value 1:0 - fixed to ?00? - 31:2 txd txdescriptor. msbs of transmit descriptor base address. 0 table 176. transmit status base address register (txstatus - address 0x2008 4120) bit description bit symbol function reset value 1:0 - fixed to ?00? - 31:2 txstat txstatus. msbs of transmit status base address. 0 table 177. transmit number of descriptors register (txdescriptornumber - address 0x2008 4124) bit description bit symbol function reset value 15:0 txdn txdescriptornumber. number of descriptors in the descriptor array for which txdescriptor is the base address. the register is minus one encoded. 0 31:16 - unused 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 221 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet the transmit number of descriptors register defines the number of descriptors in the descriptor array for which txdescriptor is the base address. the number of descriptors should match the number of statuses. the r egister uses minus one encoding i.e. if the array has 8 elements, the value in the register should be 7. 10.10.2.11 transmit produce index register the transmit produce index register defines the descriptor that is going to be filled next by the software transmit driver. the transmit descriptor array is empty as long as txproduceindex eq uals txconsumeindex. if th e transmit hardware is enabled, it will start transmitting frames as soon as the descriptor array is not empty. after a frame has been processed by software, it should increment the txproduceindex. the value must be wrapped to 0 once the value of txdescriptornumber has been reached. if the txproduceindex equals txconsumeindex - 1 the descriptor array is full and software should stop producing new descriptors unt il hardware has transmitted some frames and updated the txconsumeindex. 10.10.2.12 transmit consume index register the transmit consume index register defines the descriptor that is going to be transmitted next by the hardware transmi t process. after a frame ha s been transmitted hardware increments the index, wrapping the value to 0 once the value of txdescriptornumber has been reached. if the txconsumeindex equa ls txproduceindex the descriptor array is empty and the transmit channel will stop transmitting until so ftware produces new descriptors. 10.10.2.13 transmit status vector 0 register the transmit status vector registers store the most recent transmit status returned by the mac. since the status vector consists of more than 4 bytes, status is distributed over two registers tsv0 and tsv1. these registers ar e provided for debug purposes, because the communication between driver software and the ethernet block takes place primarily through the frame descriptors. the status r egister contents are valid as long as the internal status of the mac is valid and shou ld typically only be read when the transmit and receive processes are halted. table 178. transmit produce index register (txproduceindex - address 0x2008 4128) bit description bit symbol function reset value 15:0 txpi txproduceindex. index of the descriptor that is going to be filled next by the transmit software driver. 0 31:16 - unused 0 table 179. transmit consume index register (txconsumeindex - address 0x2008 412c) bit description bit symbol function reset value 15:0 txci txconsumeindex. index of the descriptor that is going to be transmitted next by the transmit datapath. 0 31:16 - unused 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 222 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet [1] the emac doesn't distinguish the frame type and frame length, so, e.g. when the ip(0x8000) or arp(0x0806) packets are received, it compares the frame type with the max length and gives the "length out of range" error. in fact, this bit is not an error i ndication, but simply a statem ent by the chip regarding the status of the received frame. table 180. transmit status vector 0 register (tsv0 - address 0x2008 4158) bit description bit symbol function reset value 0 crcerr crc error. the attached crc in the packet did not match the internally generated crc. 0 1 lce length check error. indicates the frame length field does not match the actual number of data items and is not a type field. 0 2 lor length out of range. indicates that frame type/length field was larger than 1500 bytes. the emac doesn't distinguish the frame type and frame length, so, e.g. when the ip(0x8000) or arp(0x0806) packets are receiv ed, it compares the frame type with the max length and gives the "length out of range" error. in fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame. 0 3 done transmission of packet was completed. 0 4 multicast packet?s destination was a multicast address. 0 5 broadcast packet?s destination was a broadcast address. 0 6 packetdefer packet was deferred for at least one attempt, but less than an excessive defer. 0 7 exdf excessive defer. packet was deferred in excess of 6071 nibble times in 100 mbps or 24287 bit times in 10 mbps mode. 0 8 excol excessive collision. packet was aborted due to exceeding of maximum allowed number of collisions. 0 9 lcol late collision. collision occurred beyond collision window, 512 bit times. 0 10 giant byte count in frame was greater than ca n be represented in the transmit byte count field in tsv1. 0 11 underrun host side caused buffer underrun. 0 27:12 totalbytes the total number of bytes transferred including collided attempts. 0 28 controlframe the frame was a control frame. 0 29 pause the frame was a control frame with a valid pause opcode. 0 30 backpressure carrier-sense method backpressure was previously applied. 0 31 vlan frame?s length/type field contained 0x8100 which is the vlan protocol identifier. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 223 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.10.2.14 transmit status vector 1 register the transmit status vector 1 register (tsv1) is a read-only register. the transmit status vector registers store the most recent transm it status returned by the mac. since the status vector consists of more than 4 bytes, status is distributed over two registers tsv0 and tsv1. these registers are provided for debug purposes, because the communication between driver software and the ethernet block takes place primarily through the frame descriptors. the status register contents are valid as long as the internal status of the mac is valid and should typically only be r ead when the transmit and receive processes are halted. table 181. transmit status vector 1 register (tsv1 - address 0x2008 415c) bit description bit symbol function reset value 15:0 tbc transmit byte count. the total number of by tes in the frame, not counting the collided bytes. 0 19:16 tcc transmit collision count. number of collisions the current packet incurred during transmission attempts. the maximum number of collisions (16) cannot be represented. 0 31:20 - unused 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 224 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.10.2.15 receive status vector register the receive status vector register (rsv) is a read-only register. the receive status vector register stores the most recent receive stat us returned by the mac. this register is provided for debug purposes, because the communication between driver software and the ethernet block takes place primarily throug h the frame descriptors. the status register contents are valid as long as the internal status of the mac is valid and should typically only be read when the transmit and receive processes are halted. table 182. receive status vector register (rsv - address 0x2008 4160) bit description bit symbol function reset value 15:0 rbc received byte count. indicates length of received frame. 0 16 ppi packet previously ignored. indicates that a packet was dropped. 0 17 rxdvseen rxdv event previously seen. indicates that the last receive event seen was not long enough to be a valid packet. 0 18 ceseen carrier event previously seen. indicates that at some time since the last receive statistics, a carrier event was detected. 0 19 rcv receive code violation. indicates that received phy data does not represent a valid receive code. 0 20 crcerr crc error. the attached crc in the packet did not match the internally generated crc. 0 21 lcerr length check error. indicates the frame length field does not match the actual number of data items and is not a type field. 0 22 lor length out of range. indicates that frame type/length field was larger than 1518 bytes. the emac doesn't distinguish the frame type and frame length, so, e.g. when the ip(0x8000) or arp(0x0806) packets are receiv ed, it compares the frame type with the max length and gives the "length out of range" error. in fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame. 0 23 rok receive ok. the packet had valid crc and no symbol errors. 0 24 multicast the packet destination was a multicast address. 0 25 broadcast the packet destination was a broadcast address. 0 26 dribblenibble indicates that after the end of packet another 1-7 bits were received. a single nibble, called dribble nibble, is formed but not sent out. 0 27 controlframe the frame was a control frame. 0 28 pause the frame was a control frame with a valid pause opcode. 0 29 uo unsupported opcode. the current frame was recognized as a control frame but contains an unknown opcode. 0 30 vlan frame?s length/type field contained 0x8100 which is the vlan protocol identifier. 0 31 - unused 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 225 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.10.2.16 flow control counter register 10.10.2.17 flow control status register table 183. flow control counter register (flowcontrolcounter - address 0x2008 4170) bit description bit symbol function reset value 15:0 mc mirrorcounter. in full duplex mode the mirro rcounter specifies the nu mber of cycles before re-issuing the pause control frame. 0 31:16 pt pausetimer. in full-duplex mode the pausetimer specifies the value that is inserted into the pause timer field of a pause flow control frame. in half duplex mode the pausetimer specifies the number of backpressure cycles. 0 table 184. flow control status register (flowcontrolstatus - address 0x2008 4174) bit description bit symbol function reset value 15:0 mcc mirrorcountercurrent. in full duplex mode this register represents the current value of the datapath?s mirror counter which counts up to the value specified by the mirrorcounter field in the flowcontrolcounter register. in half duplex mode the register counts until it reaches the value of the pausetimer bits in the flowcontrolcounter register. 0 31:16 - unused 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 226 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.10.3 receive filter register definitions 10.10.3.1 receive filter control register 10.10.3.2 receive filter wol status register the receive filter wake-up on lan status re gister (rxfilterwolstatus) is a read-only register. the bits in this register record the cause for a wol. bits in rxfilterwolstatus can be cleared by writing the rxfilterwolclear register. table 185. receive filter control register (rxfilterctrl - address 0x2008 4200) bit description bit symbol function reset value 0 aue acceptunicasten. when set to 1, all unicast frames are accepted. 0 1 abe acceptbroadcasten. when set to 1, all broadcast frames are accepted. 0 2 ame acceptmulticasten. when set to 1, all multicast frames are accepted. 0 3 auhe acceptunicasthashen. when set to 1, unicast frames that pass the imperfect hash filter are accepted. 0 4 amhe acceptmulticasthashen. when set to 1, multicast frames that pass the imperfect hash filter are accepted. 0 5 ape acceptperfecten. when set to 1, the frames with a destination address identical to the station address are accepted. 0 11:6 - reserved. read value is undefined, only zero should be written. na 12 mpew magicpacketenwol. when set to 1, the result of the magic packet filter will generate a wol interrupt when there is a match. 0 13 rfew rxfilterenwol. when set to 1, the result of the perfect address matching filter and the imperfect hash filter will generate a wol interrupt when there is a match. 0 31:14 - unused 0 table 186. receive filter wol status register (rxfilterwolstatus - address 0x2008 4204) bit description bit symbol function reset value 0 auw acceptunicastwol. when the value is 1, a unicast frames caused wol. 0 1 abw acceptbroadcastwol. when the value is 1, a broadcast frame caused wol. 0 2 amw acceptmulticastwol. when the value is 1, a multicast frame caused wol. 0 3 auhw acceptunicasthashwol. when the value is 1, a unicast frame that passes the imperfect hash filter caused wol. 0 4 amhw acceptmulticasthashwol. when the value is 1, a multicast frame that passes the imperfect hash filter caused wol. 0 5 apw acceptperfectwol. when the value is 1, the perfect address matching filter caused wol. 0 6 - unused 0 7 rfw rxfilterwol. when the value is 1, the receive filter caused wol. 0 8 mpw magicpacketwol. when the value is 1, the magic packet filter caused wol. 0 31:9 - unused 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 227 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.10.3.3 receive filter wol clear register the receive filter wake-up on lan clear regi ster (rxfilterwolclear ) is a write-only register. the bits in this register are write-only; writing resets the corresponding bits in the rxfilterwolstatus register. 10.10.3.4 hash filter table lsbs register details of hash filter table use can be found in section 10.13.10 ? receive filtering ? on page 259 . 10.10.3.5 hash filter table msbs register details of hash filter table use can be found in section 10.13.10 ? receive filtering ? on page 259 . table 187. receive filter wol clear register (rxfilterwolclear - address 0x2008 4208) bit description bit symbol function 0 auwclr acceptunicastwolclr. when a 1 is written, the corresponding status bit in the rxfilterwolstatus register is cleared. 1 abwclr acceptbroadcastwolclr. when a 1 is written, the corresponding status bit in the rxfilterwolstatus register is cleared. 2 amwclr acceptmulticastwolclr. when a 1 is written, the corresponding status bit in the rxfilterwolstatus register is cleared. 3 auhwclr acceptunicasthashwolclr. when a 1 is written, the corresponding status bit in the rxfilterwolstatus register is cleared. 4 amhwclr acceptmulticasthashwolclr. when a 1 is written, the corresponding status bit in the rxfilterwolstatus register is cleared. 5 apwclr acceptperfectwolclr. when a 1 is written, the corresponding status bit in the rxfilterwolstatus register is cleared. 6 - unused 7 rfwclr rxfilterwolclr. when a 1 is written, the corresponding status bit in the rxfilterwolstatus register is cleared. 8 mpwclr magicpacketwolclr. when a 1 is written, the corresponding status bit in the rxfilterwolstatus register is cleared. 31:9 - unused table 188. hash filter table lsbs register (hashfilterl - address 0x2008 4210) bit description bit symbol function reset value 31:0 hfl hashfilterl. bits 31:0 of the imperfect filter hash table for receive filtering. 0 table 189. hash filter msbs register (hashfilterh - address 0x2008 4214) bit description bit symbol function reset value 31:0 hfh bits 63:32 of the imperfect filter hash table for receive filtering. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 228 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.10.4 module control register definitions 10.10.4.1 interrupt status register the interrupt status register (intstatus) is a read-only register.note that all bits are flip-flops with an asynchronous set in order to be able to generate interrupts if there are wake-up events while clocks are disabled. the interrupt status register is read-only. setting can be done via the intset register. reset can be accomplished via the intclear register. table 190. interrupt status register (intstatus - address 0x2008 4fe0) bit description bit symbol function reset value 0 rxoverrunint interrupt set on a fatal overrun error in the receive queue. the fatal interrupt should be resolved by a rx soft-reset. the bit is not set when there is a nonfatal overrun error. 0 1 rxerrorint interrupt trigger on receive errors: alignmenterror, rangeerror, lengtherror, symbolerror, crcerror or nodescriptor or overrun. 0 2 rxfinishedint interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where produceindex == consumeindex. 0 3 rxdoneint interrupt triggered when a receive descriptor has been processed while the interrupt bit in the control field of the descriptor was set. 0 4 txunderrunint interrupt set on a fatal underrun error in the transmit queue. the fatal interrupt should be resolved by a tx soft-reset. the bit is not set when there is a nonfatal underrun error. 0 5 txerrorint interrupt trigger on transmit erro rs: latecollision, excessivecollision and excessivedefer, nodesc riptor or underrun. 0 6 txfinishedint interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where produceindex == consumeindex. 0 7 txdoneint interrupt triggered when a descriptor has been transmitted while the interrupt bit in the control field of the descriptor was set. 0 11:8 - unused 0 12 softint interrupt triggered by software writing a 1 to the softintset bit in the intset register. 0 13 wakeupint interrupt triggered by a wake-u p event detected by the receive filter. 0 31:14 - unused 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 229 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.10.4.2 interrupt enable register 10.10.4.3 interrupt clear register the interrupt clear register is write-only. writin g a 1 to a bit of the intclear register clears the corresponding bit in the stat us register. writing a 0 will not affect the interrupt status. table 191. interrupt enable register (int enable - address 0x2008 4f e4) bit description bit symbol function reset value 0 rxoverruninten enable for interrupt trigger on receive buffer overrun or descriptor underrun situations. 0 1 rxerrorinten enable for interrupt trigger on receive errors. 0 2 rxfinishedinten enable for interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where produceindex == consumeindex. 0 3 rxdoneinten enable for interrupt triggered when a receive descriptor has been processed while the interrupt bit in the control field of the descriptor was set. 0 4 txunderruninten enable for interrupt trigger on transmit buffer or descriptor underrun situations. 0 5 txerrorinten enable for interrupt trigger on transmit errors. 0 6 txfinishedinten enable for interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where produceindex == consumeindex. 0 7 txdoneinten enable for interrupt triggered when a descriptor has been transmitted while the interrupt bit in the control field of the descriptor was set. 0 11:8 - unused 0 12 softinten enable for interrupt triggered by the softint bit in the intstatus register, caused by software writing a 1 to the softintset bit in the intset register. 0 13 wakeupinten enable for interrupt triggered by a wake-up event detected by the receive filter. 0 31:14 - unused 0 table 192. interrupt clear register (intclear - address 0x2008 4fe8) bit description bit symbol function 0 rxoverrunintclr writing a 1 clears the corresponding stat us bit in interrupt status register intstatus. 1 rxerrorintclr writing a 1 clears the corresponding status bit in interrupt status register intstatus. 2 rxfinishedintclr writing a 1 clears the corresponding status bit in interrupt status register intstatus. 3 rxdoneintclr writing a 1 clears the corresponding status bit in interrupt status register intstatus. 4 txunderrunintclr writing a 1 clears the corresponding status bit in inte rrupt status register intstatus. 5 txerrorintclr writing a 1 clears the corresponding status bit in interrupt status register intstatus. 6 txfinishedintclr writing a 1 clears the corresponding status bit in interrupt status register intstatus. 7 txdoneintclr writing a 1 clears the corresponding status bit in interrupt status register intstatus. 11:8 - unused 12 softintclr writing a 1 clears the corresponding status bit in interrupt status register intstatus. 13 wakeupintclr writing a 1 clears the corresponding stat us bit in interrupt stat us register intstatus. 31:14 - unused
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 230 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.10.4.4 interrupt set register the interrupt set register is write-only. writing a 1 to a bit of the intset register sets the corresponding bit in the status register. writing a 0 will not affect the interrupt status. 10.10.4.5 power-down register the power-down register (powerdown) is used to block all ahb accesses except accesses to the power-down register. setting the bit will return an error on all re ad and write accesses on the macahb interface except for accesses to the power-down register. table 193. interrupt set register (intset - address 0x2008 4fec) bit description bit symbol function 0 rxoverrunintset writing a 1 to one sets the corresponding status bit in interrupt status register intstatus. 1 rxerrorintset writing a 1 to one sets the corresponding status bit in interrupt status register intstatus. 2 rxfinishedintset writing a 1 to one sets the corresponding status bit in interrupt status register intstatus. 3 rxdoneintset writing a 1 to one sets the corresponding status bit in interrupt status register intstatus. 4 txunderrunintset writing a 1 to one sets the corresponding status bit in interrupt status register intstatus. 5 txerrorintset writing a 1 to one sets the corresponding status bit in interrupt status register intstatus. 6 txfinishedintset writing a 1 to one sets the corresponding status bit in interrupt status register intstatus. 7 txdoneintset writing a 1 to one sets the corresponding status bit in interrupt status register intstatus. 11:8 - unused 12 softintset writing a 1 to one sets the corresponding status bit in interrupt status register intstatus. 13 wakeupintset writing a 1 to one sets the corresponding status bit in in terrupt status register intstatus. 31:14 - unused table 194. power-down register (powerdown - address 0x2008 4ff4) bit description bit symbol function reset value 30:0 - unused 0 31 pd powerdownmacahb. if true, all ahb accesses will return a read/write error, except accesses to the power-down register. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 231 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.11 descriptor an d status formats this section defines th e descriptor format for the transm it and receive scatter/gather dma engines. each ethernet frame can consist of one or more fragments. each fragment corresponds to a single descriptor. the dma managers in the ethernet block scatter (for receive) and gather (for transmit) multip le fragments for a single ethernet frame. 10.11.1 receive descri ptors and statuses figure 24 depicts the layout of the receive descriptors in memory. receive descriptors are stored in an array in memory. the base address of the array is stored in the rxdescriptor register, and shou ld be aligned on a 4 byte address boundary. the number of descriptors in the array is stor ed in the rxdescriptornumber register using a minus one encoding style e.g. if the array has 8 elements the register value should be 7. parallel to the descriptors there is an array of statuses. for each element of the descriptor array there is an associated status field in the status array. the base address of the status array is stored in the rxstatus register , and must be aligned on an 8 byte address boundary. during operation (when the receiv e data path is enabled) the rxdescriptor, rxstatus and rxdescriptornumber r egisters should not be modified. two registers, rxconsumeindex and rxprodu ceindex, define the descriptor locations that will be used next by hard ware and software. both register s act as counters starting at 0 and wrapping when they reach the value of rxdescriptornumber . the rxproduceindex contains the index of the descriptor that is going to be filled with the next frame being fig 24. receive descriptor memory layout 1 2 3 4 5 statusinfo statushashcrc statusinfo statushashcrc statusinfo statushashcrc statusinfo statushashcrc statusinfo statushashcrc statusinfo statushashcrc packet control packet control packet control packet control packet control packet control rxstatus rxdescriptornumber rxdescriptor data buffer data buffer data buffer data buffer data buffer data buffer
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 232 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet received. the rxconsumeindex is programmed by software and is the index of the next descriptor that the software receive driver is going to process. when rxproduceindex == rxconsumeindex, the receive buffer is empty. when rxproduceindex == rxconsumeindex -1 (taking wraparound into ac count), the receive buffer is full and newly received data would generate an overflow unless the software driver frees up one or more descriptors. each receive descriptor takes two word loca tions (8 bytes) in memory. likewise each status field takes two words (8 bytes) in me mory. each receive descriptor consists of a pointer to the data buffer for storing receive data (packet) and a control word (control). the packet field has a zero address offset, the control field has a 4 byte address offset with respect to the descriptor address as defined in table 195 . the data buffer pointer (packet) is a 32-bit, byte aligned address value containing the base address of the data buffer. the definiti on of the control word bits is listed in table 196 . table 197 lists the fields in the receive stat us elements from the status array. each receive status consists of two wo rds. the statushashcrc word contains a concatenation of the two 9-bit hash crcs ca lculated from the de stination and source addresses contained in the received frame. after detecting the destination and source addresses, statushashcrc is calculated once, then held for every fragment of the same frame. the concatenation of the two crcs is shown in table 198 : table 195. receive descriptor fields symbol address offset bytes description packet 0x0 4 base address of the data buffer for storing receive data. control 0x4 4 control information, see table 196 . table 196. receive descriptor control word bit symbol description 10:0 size size in bytes of the data buffer. this is the size of the buffer reserved by the device driver for a frame or frame fragment i.e. the byte size of the buffer pointed to by the packet field. the size is -1 encoded e.g. if the buffer is 8 bytes the size field should be equal to 7. 30:11 - unused 31 interrupt if true generate an rxdone interrupt when the dat a in this frame or frame fragment and the associated status information has been committed to memory. table 197. receive status fields symbol address offset bytes description statusinfo 0x0 4 receive status return flags, see table 199 . statushashcrc 0x4 4 the concatenation of the destination address hash crc and the source address hash crc.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 233 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet the statusinfo word contains flags returned by the mac and flags generated by the receive data path reflecting the status of the reception. ta b l e 1 9 9 lists the bit definitions in the statusinfo word. [1] the emac doesn't distinguish the frame type and frame length, so, e.g. when the ip(0x8000) or arp(0x0806) packets are received, it compares the frame type with the max length and gives the "range" error. in fact, this bit is not an erro r indication, but simply a statement by the chip regarding the status of the received frame. table 198. receive status hashcrc word bit symbol description 8:0 sahashcrc hash crc calculated from the source address. 15:9 - unused 24:16 dahashcrc hash crc calculated from the destination address. 31:25 - unused table 199. receive status information word bit symbol description 10:0 rxsize the size in bytes of the actual data transferred into one fragment buffer. in other words, this is the size of the frame or fragment as actually writt en by the dma manager for one descriptor. this may be different from the size bits of the control field in the descriptor that indicate the size of the buffer allocated by the device driver. size is -1 encoded e. g. if the buffer has 8 bytes the rxsize value will be 7. 17:11 - unused 18 controlframe indicates this is a control frame for flow control, either a pause frame or a frame with an unsupported opcode. 19 vlan indicates a vlan frame. 20 failfilter indicates this frame has failed the rx filter. these frames will not normally pass to memory. but due to the limitation of the size of the buffer, part of this frame may already be passed to memory. once the frame is found to have failed the rx filter, the remainder of the frame will be discarded without being passed to the memory. however, if the passrxfilter bit in the command register is set, the whole frame will be passed to memory. 21 multicast set when a multicast frame is received. 22 broadcast set when a broadcast frame is received. 23 crcerror the received frame had a crc error. 24 symbolerror the phy reports a bit error over the phy interface during reception. 25 lengtherror the frame length field value in the frame specifies a valid length, but does not match the actual data length. 26 rangeerror [1] the received packet exceeds the maximum packet size. 27 alignmenterror an alignment error is flagged when dribble bits are detected and also a crc error is detected. this is in accordance with ieee std. 802.3/clause 4.3.2. 28 overrun receive overrun. the adapter can not accept the data stream. 29 nodescriptor no new rx descriptor is available and the frame is too long for the buffer size in the current receive descriptor. 30 lastflag when set to 1, indicates this descriptor is for the last fragment of a frame. if the frame consists of a single fragment, this bit is also set to 1. 31 error an error occurred during reception of this frame. this is a logical or of alignmenterror, rangeerror, lengtherror, symbolerror, crcerror, and overrun.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 234 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet for multi-fragment frames, the value of t he alignmenterror, rangeerror, lengtherror, symbolerror and crcerror bits in all but the la st fragment in the frame will be 0; likewise the value of the failfilter, multicast, broadcast, vlan and controlframe bits is undefined. the status of the last fragme nt in the frame will copy the value for these bits from the mac. all fragment statuses will have valid lastfrag, rxsize, error, overrun and nodescriptor bits. 10.11.2 transmit descriptors and statuses figure 25 depicts the layout of the transmit descriptors in memory. transmit descriptors are stored in an array in memory. the lowest address of the transmit descriptor array is stored in the txdescriptor register, and must be aligned on a 4 byte address boundary. the number of descriptors in the array is stored in the txdescriptornumber register using a minus on e encoding style i.e. if the array has 8 elements the register value should be 7. parallel to the descriptors there is an array of statuses. for each element of the descriptor arra y there is an associated status field in the status array. the base address of the status ar ray is stored in the txstatus register, and must be aligned on a 4 byte address boundary. during operation (when the transmit data path is enabled) the txdescr iptor, txstatus, and txdescri ptornumber registers should not be modified. two registers, txconsumeindex and txproducei ndex, define the descriptor locations that will be used next by hardware an d software. both register act as counters star ting at 0 and wrapping when they reach the value of txdescriptornumber. the txproduceindex fig 25. transmit descriptor memory layout 1 2 3 4 5 statusinfo statusinfo statusinfo statusinfo statusinfo statusinfo packet control packet control packet control packet control packet control packet control txstatus txdescriptornumber txdescriptor data buffer data buffer data buffer data buffer data buffer data buffer
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 235 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet contains the index of the next descriptor that is going to be filled by the software driver. the txconsumeindex contains the index of t he next descriptor going to be transmitted by the hardware. when txproduceindex == txcons umeindex, the transmit buffer is empty. when txproduceindex == txconsumeindex -1 (taking wraparound into account), the transmit buffer is full and the software dr iver cannot add new descriptors until the hardware has transmitted one or more frames to free up descriptors. each transmit descriptor takes two word locations (8 bytes) in memory. likewise each status field takes one word (4 bytes) in memory. each transmit descriptor consists of a pointer to the data buffer containing transmit data (packet) and a control word (control). the packet field has a zero address offset, whereas the control field has a 4 byte address offset, see table 200 . the data buffer pointer (packet) is a 32-bit, byte aligned address value containing the base address of the data buffer. the definiti on of the control word bits is listed in table 201 . table 202 shows the one field transmit status. the transmit status consists of one word whic h is the statusinfo word. it contains flags returned by the mac and flags generated by the transmit data path reflecting the status of the transmission. table 203 lists the bit definitions in the statusinfo word. table 200. transmit descriptor fields symbol address offset bytes description packet 0x0 4 base address of the data buffer containing transmit data. control 0x4 4 control information, see table 201 . table 201. transmit descriptor control word bit symbol description 10:0 size size in bytes of the data buffer. this is the size of the frame or fragment as it needs to be fetched by the dma manager. in most cases it will be equal to the byte size of the data buffer pointed to by the packet field of the descriptor. size is -1 encoded e.g. a buffer of 8 bytes is encoded as the size value 7. 25:11 - unused 26 override per frame override. if true, bits 30:27 will override the defaults from the mac inte rnal registers. if false, bits 30:27 will be ignored and the defau lt values from the mac will be used. 27 huge if true, enables huge frame, allowing unlimited frame sizes. when false, prevents transmission of more than the maximum frame length (maxf[15:0]). 28 pad if true, pad short frames to 64 bytes. 29 crc if true, append a hardware crc to the frame. 30 last if true, indicates that this is the descriptor for the last fragment in the transmit frame. if false, the fragment from the next descriptor should be appended. 31 interrupt if true, a txdone interrupt will be generated when the data in this frame or frame fragment has been sent and the associated status information has been committed to memory. table 202. transmit status fields symbol address offset bytes description statusinfo 0x0 4 transmit status return flags, see table 203 .
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 236 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet for multi-fragment frames, the value of the latecollis ion, excessivecollision, excessivedefer, defer and collissi oncount bits in all but the la st fragment in the frame will be 0. the status of the last fragment in the frame will copy th e value for these bits from the mac. all fragment statuses will have valid error, nodescriptor and underrun bits. table 203. transmit status information word bit symbol description 20:0 - unused 24:21 collisioncount the number of collisions this packet incurred, up to the retransmission maximum. 25 defer this packet incurred deferral, because the medium was occupied. this is not an error unless excessive deferral occurs. 26 excessivedefer this packet incurred deferral beyond the maximum deferral limit and was aborted. 27 excessivecollision indica tes this packet exceeded the maximum collision limit and was aborted. 28 latecollision an out of window collision was seen, causing packet abort. 29 underrun a tx underrun occurred due to the adapter not producing transmit data. 30 nodescriptor the transmit stream was interrupted because a descriptor was not available. 31 error an error occurred during transmission. this is a logical or of underrun, latecollision, excessivecollision, and excessivedefer.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 237 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.12 ethernet block functional description this section defines the functions of the dma capable 10/100 ethernet mac. after introducing the dma concepts of the etherne t block, and a description of the basic transmit and receive functions, this section el aborates on advanced features such as flow control, receive filtering, etc. 10.12.1 overview the ethernet block can transmit and receive ethernet packets from an off-chip ethernet phy connected through the mii/rmii interface. mii or rmii mode is selected by software. typically during system start-up, the et hernet block will be in itialized. software initialization of the ethernet block should include initializ ation of the descriptor and status arrays as well as the receiver fragment buffers. remark: when initializing the ethernet block, it is important to first configure the phy and insure that reference clocks (enet_ref_clk signal in rmii mode, or both enet_rx_clk and enet_tx_clk signals in mii mode) are present at the external pins and connected to the emac m odule (selecting the appropriate pins using the iocon registers) prior to continuing with ethernet configuration. otherwise the cpu can become locked and no furthe r functionality will be possible. this w ill cause jtag lose communication with the target, if debug mode is being used. to transmit a packet the software driver has to set up the appropriate control registers and a descriptor to point to the packet data buffer before transferring the packet to hardware by incrementin g the txproduceindex register. after transmission, hardware will increment txconsumeindex and opt ionally generate an interrupt. the hardware w ill receive packets from the phy and ap ply filtering as configured by the software driver. while receivin g a packet the hardware will read a descri ptor from memory to find the location of the associated receiver data buffer. receive data is written in the data buffer and receive status is returned in the receive descriptor status word. optionally an interrupt can be generated to notify software that a packet has been received. note that the dma manager will prefetch and buffer up to three descriptors. 10.12.2 ahb interface the registers of the ethernet block connect to an ahb slave interface to allow access to the registers from the cpu. the ahb interface has a 32-bit data path, which supports only word accesses and has an address aperture of 4 kb. ta b l e 1 4 8 lists the registers of the ethernet block. all ahb write accesses to registers are posted except for accesses to the intset, intclear and intenable registers. ahb write operations are executed in order. if the powerdown bit of the powerdown regist er is set, all ahb read and write accesses will return a read or write error except for accesses to the powerdown register. bus errors the ethernet block generates errors for several conditions:
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 238 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet ? the ahb interface will return a read error when there is an ah b read access to a write-only register; likewise a write error is returned when there is an ahb write access to the read-only regist er. an ahb read or write er ror will be returned on ahb read or write accesses to reserved register s. these errors are pr opagated back to the cpu. registers defined as read-only and write-only are identified in ta b l e 1 4 8 . ? if the powerdown bit is set all accesses to ahb registers will re sult in an error response except for accesses to the powerdown register.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 239 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.13 interrupts the ethernet block has a single interrupt r equest output to the cpu (via the nvic). the interrupt service routine must read the intstatus register to determine the origin of the interrupt. all interrupt statuses can be set by software writing to the intset register; statuses can be cleared by software writing to the intclear register. the transmit and receive data paths can only set interrupt statuses, they cannot clear statuses. the softint interrupt cannot be set by hardware and can be used by software for test purposes. 10.13.1 direct memory access (dma) descriptor arrays the ethernet block includes two dma managers . the dma managers make it possible to transfer frames directly to and from memory with little support from the processor and without the need to trigger an interrupt for each frame. the dma managers work with arrays of frame de scriptors and statuses that are stored in memory. the descriptors and statuses act as an interface between the ethernet hardware and the device driver software. there is one descriptor array for receive frames and one descriptor array for transmit frames. using buffering for frame descriptors, the memory traffic and memory bandwid th utilization of descrip tors can be kept small. each frame descriptor contains two 32-bit fields: the first field is a pointer to a data buffer containing a frame or a fragment, whereas the second field is a control word related to that frame or fragment. the software driver must write the base addres ses of the descriptor and status arrays in the txdescriptor/rxdescriptor and txstat us/rxstatus registers. the number of descriptors/statuses in each array must be written in the txdescriptornumber/rxdescriptornumber regi sters. the number of descriptors in an array corresponds to the number of statuses in the associated status array. transmit descriptor arrays, receive descriptor arrays and transmit status arrays must be aligned on a 4 byte (32bit)address boundary, while the receive status array must be aligned on a 8 byte (64bit) address boundary. ownership of descriptors both device driver software and ethernet ha rdware can read and write the descriptor arrays at the same time in order to produce and consume descriptors. a descriptor is "owned" either by the device driver or by the ethernet hardware. only the owner of a descriptor reads or writes its value. typi cally, the sequence of use and ownership of descriptors and statuses is as follows: a de scriptor is owned and set up by the device driver; ownership of the descripto r/status is passed by the de vice driver to the ethernet block, which reads the descript or and writes information to the status field; the ethernet block passes ownership of the descriptor back to the device driver, which uses the status information and then recycles the descriptor to be used for another frame. software must pre-allocate the memory used to hold the descriptor arrays.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 240 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet software can hand over ownership of desc riptors and statuses to the hardware by incrementing (and wrapping if on the array boundary) the txproduceindex/rxconsumeindex registers. hardware hands over descriptors and status to software by updating the tx consumeindex/ rxprodu ceindex registers. after handing over a descriptor to the receive and transmit dma hardware, device driver software should not modify the descriptor or reclaim the descriptor by decrementing the txproduceindex/ rxconsumeindex registers because descriptors may have been prefetched by the hardwar e. in this case the de vice driver software will have to wait until the frame has been transmitted or the device driver has to soft-reset the transmit and/or receive data paths which will al so reset the descriptor arrays. sequential order with wrap-around when descriptors are read from and statuses are written to the arrays, this is done in sequential order with wrap-around. sequent ial order means that when the ethernet block has finished reading/writing a descriptor/status, the next descriptor/status it reads/writes is the one at the next higher, adjacent memory address. wrap around means that when the ethernet block has finished reading/writing the last descriptor/status of the array (with the highest memory address), the next descri ptor/status it reads/writes is the first descriptor/status of the array at the base address of the array. full and empty state of descriptor arrays the descriptor arrays can be empty, partially full or full. a descriptor array is empty when all descriptors are owned by the producer. a descriptor array is partially full if both producer and consumer own part of the desc riptors and both are busy processing those descriptors. a descriptor array is full when all descriptors (except one) are owned by the consumer, so that the producer has no more room to process frames. ownership of descriptors is indicated with the use of a consume index and a produce index. the produce index is the first element of the array owned by the producer. it is also the index of the array element that is next going to be used by the producer of frames (it may already be busy using it and subsequent elements). the consume index is the first element of the array that is owned by the co nsumer. it is also the number of the array element next to be consumed by the consumer of frames (it and subsequent elements may already be in the process of being cons umed). if the consume index and the produce index are equal, the descriptor array is empt y and all array elements are owned by the producer. if the consume index equals the prod uce index plus one, then the array is full and all array elements (except the one at the produce index) are owned by the consumer. with a full descriptor array, st ill one array element is kept empty, to be able to easily distinguish the full or empty state by look ing at the value of the produce index and consume index. an array must have at least 2 elements to be able to indicate a full descriptor array with a produce index of va lue 0 and a consume index of value 1. the wrap around of the arrays is taken into accoun t when determining if a descriptor array is full, so a produce index that indicates the last element in the array and a consume index that indicates the first element in the array, also means the descriptor array is full. when the produce index and the consume index are unequal and the consume index is not the produce index plus one (with wrap around taken in to account), then the descriptor array is partially full and both the consumer and producer own enough descriptors to be able to operate actively on the descriptor array. interrupt bit
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 241 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet the descriptors have an interrupt bit, which is programmed by software. when the ethernet block is processing a de scriptor and finds this bit set, it will allow triggering an interrupt (after committing status to memory ) by passing the rxdoneint or txdoneint bits in the intstatus register to the interrupt output pin. if the interrupt bit is not set in the descriptor, then the rxdoneint or txdoneint ar e not set and no interrupt is triggered (note that the corresponding bits in intenable must al so be set to trigger interrupts). this offers flexible ways of managing the descriptor arra ys. for instance, the device driver could add 10 frames to the tx descriptor array, and set the interrupt bit in descriptor number 5 in the descriptor array. this would invoke the in terrupt service routine before the transmit descriptor array is completely exhausted. th e device driver could add another batch of frames to the descriptor array, without interr upting continuous transmission of frames. frame fragments for maximum flexibility in fram e storage, frames can be split up into multiple frame fragments with fragments located in different places in memory. in this case one descriptor is used for each frame fragment. so, a descriptor can point to a single frame or to a fragment of a frame. by using fragment s, scatter/gather dma can be done: transmit frames are gathered from multiple fragments in memory and receive frames can be scattered to multiple fragments in memory. by stringing together fragments it is possible to create large frames from small memory areas. another use of fragments is to be able to locate a frame header and frame payload in different places and to concatenate them wi thout copy operations in the device driver. for transmissions, the last bit in the descriptor control field indicates if the fragment is the last in a frame; for receive frames, the lastfr ag bit in the statusinfo field of the status words indicates if the fragment is the last in the frame. if the last(f rag) bit is 0 the next descriptor belongs to the same ethernet frame, if the last(frag) bit is 1 the next descriptor is a new ethernet frame. 10.13.2 initialization after reset, the ethernet software driver n eeds to initialize the ethernet block. during initialization the so ftware needs to: ? remove the soft reset condition from the mac. ? configure the phy via the miim interface of the mac. remark: it is important to configure the ph y and insure that reference clocks (enet_ref_clk signal in rmii mode, or both enet_rx_clk and enet_tx_clk signals in mii mode) are present at the external pins and connected to the emac module (selecting the appropriate pins using the iocon registers) prior to continuing with ethernet configuration. otherwise the cpu can become locked and no further functionality will be possible. this will cause jtag lose communication with the target, if debug mode is being used. ? select mii or rmii mode ? configure the transmit and receive dma e ngines, including the descriptor arrays. ? configure the host registers (mac1,mac2 etc.) in the mac. ? enable the receive and transmit data paths.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 242 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet depending on the phy, the software needs to initialize registers in the phy via the mii management interface. the software can read and write phy regist ers by programming the mcfg, mcmd, madr registers of the mac. write data should be written to the mwtd register; read data and status information can be read from the mrdd and mind registers. the ethernet block supports mii and rmii phys. du ring initialization software must select mii or rmii mode by programming the command register. before switching to rmii mode the default soft reset (mac1 register bit 15) has to be de-asserted. the clock(s) from the phy must be running and internally connected during this operation. transmit and receive dma engines should be in itialized by the device driver by allocating the descriptor and status arrays in memory. transmit and receive functions have their own dedicated descriptor and status arrays. the base addresses of these arrays need to be programmed in the txdescriptor/txstatus a nd rxdescriptor/rxstatus registers. the number of descriptors in an array matc hes the number of statuses in an array. please note that the transmit descriptors, re ceive descriptors and re ceive statuses are 8 bytes each while the transmit statuses are 4 b ytes each. all descriptor arrays and transmit statuses need to be aligned on 4 byte boun daries; receive status arrays need to be aligned on 8 byte boundaries. the number of de scriptors in the descriptor arrays needs to be written to the txdescriptornumber/rxdescr iptornumber registers using a -1 encoding i.e. the value in the registers is the number of descriptors minus one e.g. if the descriptor array has 4 descriptors the value of the nu mber of descriptors register should be 3. after setting up the descriptor arrays, frame buffers need to be allocated for the receive descriptors before enabling the receive data path. the packet field of the receive descriptors needs to be filled with the base address of the frame buffer of that descriptor. amongst others the control field in the receiv e descriptor needs to contain the size of the data buffer using -1 encoding. the receive data path has a configurable filter ing function for discardi ng/ignoring specific ethernet frames. the filtering function should also be configured during initialization. after an assertion of the hardwa re reset, the soft reset bit in the mac will be asserted. the soft reset condition must be removed before the ethernet block can be enabled. enabling of the receive function is located in two places. the receive dma manager needs to be enabled and the receive data path of the mac needs to be enabled. to prevent overflow in the receive dma engine the receive dma engine should be enabled by setting the rxenable bit in the command register before enabling the receive data path in the mac by setting the receive enable bit in the mac1 register. the transmit dma engine can be enabled at any time by setting the txenable bit in the command register. before enabling the data paths, several options can be programmed in the mac, such as automatic flow control, transmit to receiv e loop-back for verification, full/half duplex modes, etc. base addresses of descriptor arrays and descriptor array sizes cannot be modified without a (soft) reset of the receive and transmit data paths.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 243 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.13.3 transmit process overview this section outlines the transmission process. device driver sets up descriptors and data if the descriptor array is full th e device driver should wait for the descriptor arrays to become not full before writing to a descriptor in the descriptor array. if the descriptor array is not full, the device driver should use t he descriptor numbered txproduceindex of the array pointed to by txdescriptor. the packet pointer in the descriptor is set to po int to a data frame or frame fragment to be transmitted. the size field in the command fi eld of the descriptor should be set to the number of bytes in the fragment buffer, -1 encoded. additional control information can be indicated in the control field in the descriptor (bits interrupt, last, crc, pad). after writing the descriptor the descriptor needs to be handed over to the hardware by incrementing (and possibly wrappi ng) the txproduceindex register. if the transmit data path is disabled, the devi ce driver should not forget to enable the transmit data path by setting the tx enable bit in the command register. when there is a multi-fragment transmission for fragments other than the last, the last bit in the descriptor must be set to 0; for the last fragment the last bit must be set to 1. to trigger an interrupt when the frame has bee n transmitted and transmission status has been committed to memory, set the interrupt bit in the descriptor control field to 1. to have the hardware add a crc in the frame sequence control field of this ethernet frame, set the crc bit in the descriptor. this should be done if the crc has not already been added by software. to enable automatic padding of small frames to the minimum required frame size, set the pad bit in the control field of the descriptor to 1. in typical applications bits crc and pad are both set to 1. the device driver can set up interrupts using the intenable register to wait for a signal of completion from the hardware or can periodically inspect (poll) the progress of transmission. it can also add new frames at the end of the descriptor array, while hardware consumes descriptor s at the start of the array. the device driver can stop the transmit proc ess by resetting the txenable bit in the command register to 0. the transmission will not stop immediately; frames already being transmitted will be transmitte d completely and th e status will be committed to memory before deactivating the data path. the status of the transmit data path can be monitored by the device driver reading the tx status bit in the status register. as soon as the transmit data path is enabled and the corresponding txconsumeindex and txproduceindex are not equal i.e. th e hardware still needs to process frames from the descriptor array, the txstatus bit in th e status register will return to 1 (active). tx dma manager reads the tx descriptor array
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 244 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet when the txenable bit is set, the tx dma manager reads the descriptors from memory at the address determined by txdescriptor and txconsumeindex. the number of descriptors requested is determined by the total number of descriptors owned by the hardware: txproduceindex - txconsumeindex. block transferring descriptors minimizes memory loading. read data returned from memory is buffered and consumed as needed. tx dma manager transmits data after reading the descriptor the transmit dma engine reads the associated frame data from memory and transmits the frame. afte r transfer completion, the tx dma manager writes status information back to the status info and statushashcrc words of the status field. the value of the txcons umeindex is only updated after status information has been committed to memory, which is checked by an internal tag protocol in the memory interface. the tx dma manager continues to transmit frames until th e descriptor array is empty. if the transmit descriptor array is empty the txstatus bit in the status register will return to 0 (inactive). if the descriptor array is em pty the ethernet hardware will set the txfinishedint bit of th e intstatus register. the transmit data path will still be enabled. the tx dma manager inspects the last bit of the descriptor control field when loading the descriptor. if the last bit is 0, this indicates th at the frame consists of multiple fragments. the tx dma manager gathers all the fragments fr om the host memory, visiting a string of frame descriptors, and sends th em out as one ethernet frame on the ethernet connection. when the tx dma manager finds a descriptor with the last bit in the control field set to 1, this indicates the last fragment of the fr ame and thus the end of the frame is found. update consumeindex each time the tx dma manager commits a st atus word to memory it completes the transmission of a descriptor and it increm ents the txconsumeindex (taking wrap around into account) to hand the descriptor back to the device driver software. software can re-use the descriptor for new transmissi ons after hardware has handed it back. the device driver software can keep track of the progress of the dma manager by reading the txconsumeindex register to see how far along the transmit process is. when the tx descriptor array is emptied completely, the tx consumeindex register retains its last value. write transmission status after the frame has been transmitted over th e mii/rmii bus, the statusinfo word of the frame descriptor is updated by the dma manager. if the descriptor is for the last fragment of a frame (or for the whole frame if there are no fragments), then depending on the success or failure of the frame transmission, error flags (error, latecollision, excessivecollision, underrun, exce ssivedefer, defer) are set in the status. the collisioncount field is set to the number of collisio ns the frame incurred, up to the retransmissi on maximum programmed in the collis ion window/retry register of the mac. statuses for all but the last fragment in the frame will be writte n as soon as the data in the frame has been accepted by the tx dma manager . even if the descriptor is for a frame fragment other than the last fragment, the error flags are returned via the ahb interface. if the ethernet block detects a transmission error during transmission of a (multi-fragment) frame, all remaining fragments of the frame are still read via the ahb interfac e. after an error, the remaining transmit data is discarde d by the ethernet block. if there are errors
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 245 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet during transmission of a multi-fragment frame the error statuses will be repeated until the last fragment of the frame. st atuses for all bu t the last fragment in the frame will be written as soon as the data in the frame has been accepted by the tx dma manager. these may include error information if the error is detected early enough. the status for the last fragment in the frame will only be written after the transmission has completed on the ethernet connecti on. thus, the status for the last fragment w ill always refl ect any error that occurred anywhere in the frame. the status of the last frame transmission can also be inspected by reading the tsv0 and tsv1 registers. these registers do not report statuses on a fragment basis and do not store information of previously sent fram es. they are provided primarily for debug purposes, because the communication between driver software and the ethernet block takes place through the frame descriptors. the status registers are valid as long as the internal status of the mac is valid and shou ld typically only be read when the transmit and receive processes are halted. transmission error handling if an error occurs during the transmit process, the tx dma manager will report the error via the transmission statusinfo word written in the status array and the intstatus interrupt status register. the transmission can generate several types of errors: late collision, excessivecollision, excessivedefer, underrun, and nodescriptor. all have corresponding bits in the transmission statusinfo word. in addition to the separate bits in the statusinfo word, latecollision, excessivecollisio n, and excessiv edefer are ored together into the error bit of the status. errors are also propagated to the intstatus register; the txerror bit in the intstatus register is set in th e case of a latecollis ion, excessivecollisio n, excessivedefer, or nodescriptor error; underrun errors are re ported in the txunderrun bit of the intstatus register. underrun errors can have three causes: ? the next fragment in a multi-fragment transmissi on is not available. this is a nonfatal error. a nodescriptor status will be returned on the previous fragme nt and the txerror bit in intstatus will be set. ? the transmission fragment data is not available when the ethernet block has already started sending the frame. this is a nonfatal error. an u nderrun status will be returned on transfer and the txerror bit in intstatus will be set. ? the flow of transmission statuses stalls and a new status has to be written while a previous status still waits to be transferred across the memory interface. this is a fatal error which can only be resolved by a soft reset of the hardware. the first and second situations are nonfatal and the device driver has to re-send the frame or have upper software layers re-send the frame. in the third case the hardware is in an undefined state and needs to be soft reset by setting the txreset bit in the command register. after reporting a latecollision, e xcessivecollision, ex cessivedefer or u nderrun error, the transmission of the erroneous frame will be aborted, re maining transmission data and frame fragments will be discar ded and transmission will cont inue with the next frame in the descriptor array.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 246 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet device drivers should catch the transmission errors and take action. transmit triggers interrupts the transmit data path can generate four different interrupt types: ? if the interrupt bit in the de scriptor control field is se t, the tx dma will set the txdoneint bit in the intstatus register after sending the fragment and committing the associated transmission status to memory . even if a descriptor (fragment) is not the last in a multi-fragment frame the interrupt bit in the descriptor can be used to generate an interrupt. ? if the descriptor array is empty while the ethernet hardware is enabled the hardware will set the txfinish edint bit of the in tstatus register. ? if the ahb interface does not consume the tr ansmission statuses at a sufficiently high bandwidth the transmission ma y underrun in which case th e txunderrun bi t will be set in the intstatus register. this is a fatal error which requires a soft reset of the transmission queue. ? in the case of a transmission error (latecollision, exce ssivecollision, or excessivedefer) or a multi-fragment frame where the device driver did provide the initial fragments but did not provide the rest of the fragments (nodescriptor) or in the case of a nonfatal overrun, the hardware will set the txer rorint bit of the intstatus register. all of the above interrupts can be enabled and disabled by setting or resetting the corresponding bits in the intenable register. enabling or disabling does not affect the intstatus register contents, only the propagatio n of the interrupt status to the cpu (via the nvic). the interrupts, either of individual frames or of the whole list, are a good means of communication between the dma manager and the device driver, triggering the device driver to inspect the status words of descriptors that ha ve been processed. transmit example figure 26 illustrates the transmit pr ocess in an example transmi tting uses a frame header of 8 bytes and a frame payload of 12 bytes.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 247 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet after reset the values of the dma registers will be zero. du ring initialization the device driver will allocate the descriptor and status array in memory. in this example, an array of four descriptors is allocated; the array is 4x2x4 bytes and aligned on a 4 byte address boundary. since the number of descriptors matches the number of statuses the status array consists of four elements; the array is 4x1x4 bytes and aligned on a 4 byte address boundary. the device driver writes the base address of the descriptor array (0x2008 10ec) to the txdescriptor register and the base address of the status array (0x2008 11f8) to the txstatus register. the device driver writes the number of descriptors and statuses minus 1(3) to the txdescri ptornumber register. the descriptors and statuses in the arrays need not be initialized, yet. at this point, the transmit data path may be enabled by setting the txenable bit in the command register. if the transmit data path is enabled while there are no further frames to send the txfinishedint interrupt flag will be set. to reduce the processor interrupt load only the desired interrupts can be enabled by setting the relevant bits in the intenable register. now suppose application software wants to tr ansmit a frame of 12 bytes using a tcp/ip protocol (in real applications frames will be larger than 12 bytes). the tcp/ ip stack will add a header to the frame. the frame header need not be immediately in front of the payload data in memory. the device driver c an program the tx dma to collect header and payload data. to do so, the devi ce driver will progra m the first descriptor to point at the fig 26. transmit example memory and registers statusinfo statusinfo statusinfo statusinfo packet 0x20081314 txstatus 0x200811f8 txdescriptor 0x200810ec 0x200810ec 0x200810f0 0x200810f4 0x200810f8 0x200810fc 0x20081100 0x20081104 0x20081108 0x200811f8 0x200811fc 0x20081200 0x20081204 packet 0x20081411 packet 0x20081419 packet 0x20081324 descriptor array descriptor 0 de s cr i p t o r 1 de scriptor 2 d escriptor 3 descriptor array fragment buffers txproduceindex txconsumeindex txdescriptornumber = 3 status 1 status 0 st atu s 3 st atu s 2 status array status array packet 1 header (8 bytes) packet 0 payload (12 bytes) packet 0 header (8 bytes) 00 7 control control 00 7 control control 11 3 control control 00 7 control control 0x20081314 0x2008131b 0x20081411 0x20081419 0x2008141c 0x20081324 0x2008132b
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 248 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet frame header; the last flag in the descriptor will be set to false/0 to indicate a multi-fragment tran smission. the device driver will progra m the next descriptor to point at the actual payload data. the maximum size of a payload buffer is 2 kb so a single descriptor suffices to describe the payload buffer. for the sake of the example though the payload is distributed across two descriptor s. after the first descriptor in the array describing the header, the second descriptor in the array describes the initial 8 bytes of the payload; the third descriptor in the array de scribes the remaining 4 bytes of the frame. in the third descriptor the last bit in the control word is set to true /1 to indicate it is the last descriptor in the frame. in this example the in terrupt bit in the descriptor control field is set in the last fragment of the frame in order to trigger an interrup t after the transmission completed. the size field in the descriptor?s c ontrol word is set to the number of bytes in the fragment buffer, -1 encoded. note that in real device driv ers, the payload will typically only be split across multiple descriptors if it is more than 2 kb. also note that transmission payload data is forwarded to the hardware without the device driver copying it (zero copy device driver). after setting up the descriptors for the trans action the device driver increments the txproduceindex register by 3 since three descriptors have been programmed. if the transmit data path was not enabled during in itialization the device driver needs to enable the data path now. if the transmit data path is enabled the ethernet block will start transmitting the frame as soon as it detects the txproduceindex is no t equal to txconsumeindex - both were zero after reset. the tx dma will start readin g the descriptors from memory. the memory system will return the descripto rs and the ethernet block w ill accept them one by one while reading the transmit data fragments. as soon as transmission read da ta is returned from memory, the ethernet block will try to start transmission on the ethernet co nnection via the mii/rmii interface. after transmitting each fragment of the fram e the tx dma will writ e the status of the fragment?s transmission. statuses for all but the last fragment in the frame will be written as soon as the data in the frame has been accepted by the tx dma manager. the status for the last fragment in the frame will only be written after the transmission has completed on the ethernet connection. since the interrupt bit in the descriptor of t he last fragment is set, after committing the status of the last fragment to memory the ethernet block will trigger a txdoneint interrupt, which triggers the device driver to inspect the status information. in this example the device driv er cannot add new descriptor s as long as the ethernet block has not incremented the txconsumeindex because the descriptor array is full (even though one descriptor is not programmed yet). only after the hardwar e commits the status for the first fragment to memory and the txconsumeindex is set to 1 by the dma manager can the device driver program the next (the fo urth) descriptor. the fo urth descriptor can already be programmed before completely transmitting the first frame. in this example the hardware adds the crc to the frame. if the device driver software adds the crc, the crc trailer can be consid ered another frame fragment which can be added by doing another gather dma.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 249 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet each data byte is transmitted across the mii interface as two 4-bit values or the rmii interface as four 2-bit values. the ether net block adds the preamble, frame delimiter leader, and the crc trailer if hardware crc is enabled. once transmission on the mii/rmii interface commences the transmission cannot be interrupted without generating an underrun error, which is why descriptors and data read commands are issued as soon as possible and pipelined. using an mii phy, the data communication between the ethernet block and the phy is done at a 25 mhz rate. with an rmii phy, the data communication between the ethernet block and the phy is at a 50 mhz rate. in 10 mbps mode data will only be transmitted once every 10 clock cycles. 10.13.4 receive process this section outlines the receive process incl uding the activities in the device driver software. device driver sets up descriptors after initializing the receive descriptor and status arrays to receive frames from the ethernet connection, the receive data path should be enabled in the mac1 register and the control register. during initialization, each packet pointer in the descriptors is set to point to a data fragment buffer. the size of the buffer is stor ed in the size bits of the control field of the descriptor. additionally, the control field in th e descriptor has an inte rrupt bit. the interrupt bit allows generation of an interrupt after a fr agment buffer has been filled and its status has been committed to memory. after the initialization and enabling of the receive data path, all descriptors are owned by the receive hardware and should not be modified by the software unless hardware hands over the descriptor by incrementing the rxproduceindex, indicating that a frame has been received. the device driver is allowed to modify the descriptors after a (soft) reset of the receive data path. rx dma manager reads rx descriptor arrays when the rxenable bit in the command register is set, the rx dma manager reads the descriptors from memory at the addr ess determined by rxdescriptor and rxproduceindex. the ethernet block will st art reading descriptors even before actual receive data arrives on the mii/rmii interface (descriptor prefetching). the block size of the descriptors to be read is determined by the total number of descriptors owned by the hardware: rxconsumeindex - rxproduceindex - 1. block transferring of descriptors minimizes memory load. read data returned from memory is buffered and consumed as needed. rx dma manager receives data after reading the descriptor, the receive dma engine waits for the mac to return receive data from the mii/rmii interface that passes the receive filter. receive frames that do not match the filtering criteria are not passed to memory. once a frame passes the receive filter, the data is written in the fragment buff er associated with the descriptor. the rx dma does not write beyond the size of the buffer. wh en a frame is received that is larger than a descriptor?s fragment buffer, the frame will be written to multiple fragment buffers of
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 250 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet consecutive descriptors. in the case of a multi- fragment reception, all but the last fragment in the frame will return a status where the la stfrag bit is set to 0. only on the last fragment of a frame the lastfrag bit in the status will be set to 1. if a fragment buffer is the last of a frame, the buffer ma y not be filled comple tely. the first receive data of the next frame will be written to the fragment buffer of the next descriptor. after receiving a fragment, the rx dma manager writes status information back to the statusinfo and statushashcrc words of the stat us. the ethernet block writes the size in bytes of a descriptor?s fragment buffer in the rxsize field of the status word. the value of the rxproduceindex is only updated after th e fragment data and the fragment status information has been committed to memory, which is checked by an internal tag protocol in the memory interface. the rx dma manager continues to receive frames until the descriptor array is full. if th e descriptor array is full, th e ethernet hardware will set the rxfinishedint bit of the intstatus register. the receive data path will still be enabled. if the receive descriptor array is full any new receiv e data will generate an overflow error and interrupt. update produceindex each time the rx dma manager commits a data fragment and the associated status word to memory, it completes the reception of a descriptor and increments the rxproduceindex (taking wrap around into account) in order to h and the descriptor back to the device driver software. software can re-use the descriptor for new receptions by handing it back to hardware when the receive data has been processed. the device driver software can keep track of the progress of the dma manager by reading the rxproduceindex register to see how far along the receive process is. when the rx descriptor array is emptied completely, t he rxproduceindex retains its last value. write reception status after the frame has been received from the mii/rmii bus, the statusinfo and statushashcrc words of the frame descrip tor are updated by the dma manager. if the descriptor is for the last fragment of a frame (or for the whole frame if there are no fragments), then depending on the success or failure of the frame reception, error flags (error, nodescriptor, overrun, alignmenterror, rangeerror, lengtherror, symbolerror, or crcerror) are set in statusinfo . the rxsize field is set to the number of bytes actually written to the fragment buffer, -1 encoded. for fragments not being the last in the frame the rxsize will match the size of the buffer. the hash crcs of the destination and source addresses of a packet are calculated once for all the fragments belonging to the same packet and then stored in every statushashcrc wo rd of the statuses associated with the corresponding fragments. if the reception reports an error, any remaining data in the receive frame is discarded and the lastfrag bit will be set in the receive status field, so the error flags in all bu t the last fragment of a frame will always be 0. the status of the last received frame can also be inspected by reading the rsv register. the register does not report statuses on a fragment basis and does not store information of previously received frames. rsv is provi ded primarily for debug purposes, because the communication between driver software and the ethernet block takes place through the frame descriptors. reception error handling
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 251 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet when an error occurs during th e receive process, the rx dma manager w ill report the error via the receive statusinfo written in the status array and the intstatus interrupt status register. the receive process can generate several ty pes of errors: alignmenterror, rangeerror, lengtherror, symbolerror, crcerror, overrun, and nodescriptor. all have corresponding bits in the receive statusinfo. in addition to the separate bits in the statusinfo, alignmenterror, rangeerror, lengtherror, sym bolerror, and crcerror are ored together into the error bit of the statusinfo. errors ar e also propagated to the intstatus register; the rxerror bit in the intstatus register is se t if there is an alignmenterror, rangeerror, lengtherror, symbolerror, crcer ror, or nodescriptor error; nonfatal overrun errors are reported in the rxerror bit of the intstatus re gister; fatal overrun errors are report in the rxoverrun bit of the intstatus register. on fata l overrun errors, the rx data path needs to be soft reset by setting the rxre set bit in the command register. overrun errors can have three causes: ? in the case of a multi-fragment reception, the next descriptor may be missing. in this case the nodescriptor field is set in the stat us word of the previ ous descriptor and the rxerror in the intstatus register is set. this error is nonfatal. ? the data flow on the receiver data interfac e stalls, corrupting the packet. in this case the overrun bit in the status word is set and the rxerror bit in the intstatus register is set. this error is nonfatal. ? the flow of reception statuses stalls an d a new status has to be written while a previous status still waits to be transferred across the memory inte rface. this error will corrupt the hardware state and requires the hardware to be soft reset. the error is detected and sets the overrun bit in the intstatus register. the first overrun situation will result in an incomplete fram e with a nodescriptor status and the rxerror bit in intstatus set. software should discard the partially received frame. in the second over run situation the frame data will be corrupt which results in the overrun status bit being set in the status word while the interror interrupt bit is set. in the third case receive errors cannot be reported in the receiver status arrays which corrupts the hardware state; the er rors will still be reported in the intsta tus register?s overrun bit. the rxreset bit in the command register should be used to soft reset the hardware. device drivers should catch the above receive errors and take action. receive triggers interrupts the receive data path can generate four different interrupt types: ? if the interrupt bit in the de scriptor control field is se t, the rx dma will set the rxdoneint bit in the intstatus register after receiving a fragment and committing the associated data and status to memory. even if a descriptor (fragment) is not the last in a multi-fragment frame, the interrupt bit in the descriptor can be used to generate an interrupt. ? if the descriptor array is full while the ethe rnet hardware is enabled, the hardware will set the rxfinishedint bit of the intstatus register. ? if the ahb interface does not consume receive statuses at a sufficiently high bandwidth, the receive status process may overrun, in which case the rxoverrun bit will be set in the intstatus register.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 252 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet ? if there is a receive error (alignmenterror, rangeerror, lengtherror, symbolerror, or crcerror), or a multi-fragment frame where the device driver did provide descriptors for the initial fragments but did not prov ide the descriptors for the rest of the fragments, or if a nonfatal data overrun oc curred, the hardware w ill set the rxerrorint bit of the intstatus register. all of the above interrupts can be enabled and disabled by setting or resetting the corresponding bits in the intenable register. enabling or disabling does not affect the intstatus register contents, only the propagatio n of the interrupt status to the cpu (via the nvic). the interrupts, either of individual frames or of the whole list, are a good means of communication between the dma manager and the device driver, triggering the device driver to inspect the status words of descriptors that ha ve been processed. device driver processes receive data as a response to status (e.g. rxdoneint) in terrupts or polling of th e rxproduceindex, the device driver can read the descriptors that ha ve been handed over to it by the hardware (rxproduceindex - rxconsumeindex). the device driver should inspect the status words in the status array to check for multi- fragment receptions and receive errors. the device driver can forwar d receive data and status to upper software layers. after processing of data and status, the descriptors, statuses and data buffers may be recycled and handed back to hardware by in crementing the rxconsumeindex. receive example figure 27 illustrates the receive pr ocess in an example rece iving a frame of 19 bytes.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 253 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet after reset, the values of the dma registers w ill be zero. during init ialization, the device driver will allocate the descriptor and status array in memory. in this example, an array of four descriptors is allocated; the array is 4x2x4 bytes and aligned on a 4 byte address boundary. since the number of descriptors ma tches the number of statuses, the status array consists of four elements; the array is 4x2x4 bytes and aligned on a 8 byte address boundary. the device driver writes the base address of the descriptor array (0x2008 10ec) in the rxdescriptor register, and the base address of the status array (0x2008 11f8) in the rxstatus register. the de vice driver writes th e number of descriptors and statuses minus 1 (3) in the rxdescri ptornumber register. the descriptors and statuses in the arrays need not be initialized yet. after allocating the descriptors, a fragment buffer needs to be allocated for each of the descriptors. each fragment buffer can be between 1 byte and 2 k bytes. the base address of the fragment buffer is stored in the packet field of the descriptors. the number of bytes in the fragment buffer is stored in the size field of the descriptor control word. the interrupt field in the control word of the descriptor can be set to generate an interrupt as soon as the descriptor ha s been filled by the receive pr ocess. in this example the fragment buffers are 8 bytes, so the value of the size field in the control word of the descriptor is set to 7. note that in this example, the fragment buffers are actually a fig 27. receive example memory and registers packet 0x20081409 rxstatus 0x200811f8 rxdescriptor 0x200810ec 0x200810ec 0x200810f0 0x200810f4 0x200810f8 0x200810fc 0x20081100 0x20081104 0x20081108 0x 2008 11f8 0x 2008 1200 0x 2008 1208 0x 2008 1210 packet 0x20081411 packet 0x20081419 packet 0x20081325 descriptor array de sc ript or 0 descriptor 1 descriptor 2 de scriptor 3 descriptor array fragment buffers rxproduceindex rxconsumeindex rxdescriptornumber = 3 status 1 status 0 status 3 status 2 status array status array fragment 1 buffer (8 bytes) fragment 0 buffer (8 bytes) fragment 2 buffer (3 bytes) fragment 3 buffer (8 bytes) 17 control 17 control 17 control 17 control statusinfo 7 statushashcrc statusinfo 7 statushashcrc statusinfo 7 statushashcrc statusinfo 2 statushashcrc 0x20081409 0x20081410 0x20081411 0x20081418 0x20081325 0x2008132c 0x20081419 0x2008141b
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 254 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet continuous memory space; even when a frame is distributed over mult iple fragments it will typically be in a linear, continuous memory sp ace; when the descriptors wrap at the end of the descriptor array the frame will not be in a continuous memory space. the device driver should enable the receive pr ocess by writing a 1 to the rxenable bit of the command register, after which the mac needs to be enabled by writing a 1 to the ?receive enable? bit of the ma c1 configuration register. the ethernet block will now start receiving ethernet frames. to reduce the processor interrupt load, some interrupts can be disabled by setting the relevant bits in the intenable register. after the rx dma manager is enabled, it will start issuing descript or read commands. in this example the number of descriptors is 4. initially the rxproduceindex and rxconsumeindex are 0. since t he descriptor array is consid ered full if rxproduceindex == rxconsumeindex - 1, the rx dma manag er can only read (rxconsumeindex - rxproduceindex - 1 =) 3 de scriptors; note the wrapping. after enabling the receiv e function in the mac, data re ception will begin starting at the next frame i.e. if the receive function is en abled while the mii/rmii interface is halfway through receiving a frame, the frame will be di scarded and reception w ill start at the next frame. the ethernet block will strip the preamble and start of frame delimiter from the frame. if the frame passes the receive filterin g, the rx dma manager will start writing the frame to the first fragment buffer. suppose the frame is 19 bytes long. due to the buffer sizes specified in this example, the frame will be distributed over thr ee fragment buffers. after writ ing the initial 8 bytes in the first fragment buffer, the status for the first fragment buffer will be written and the rx dma will continue filling the second fragment buffer. since this is a multi-fragment receive, the status of the first fragment w ill have a 0 for the la stfrag bit in the statusinfo word; the rxsize field will be set to 7 (8, -1 encod ed). after writing the 8 bytes in the second fragment the rx dma will continue writing th e third fragment. the status of the second fragment will be like the status of the first frag ment: lastfrag = 0, rxsi ze = 7. after writing the three bytes in the third fragment buffer, the end of the frame has been reached and the status of the third fragment is written. the third fr agment?s status will have the lastfrag bit set to 1 and the rxsize equal to 2 (3, -1 encoded). the next frame received from the mii/rmii interface will be written to the fourth fragment buffer i.e. five bytes of the third buffer will be unused. the rx dma manager uses an internal tag protocol in the memory interface to check that the receive data and status have been committed to memory. after the status of the fragments are committed to memory, an rxdo neint interrupt will be triggered, which activates the device driver to inspect the status information. in this example, all descriptors have the inte rrupt bit set in the co ntrol word i.e. all de scriptors will generate an interrupt after committing data and status to memory. in this example the receive function cannot read new descriptors as long as the device driver does not increment the rxconsumeindex, because the de scriptor array is full (even though one descriptor is not programmed yet). only after the device driver has forwarded the receive data to application software, and after the device driver has updated the rxconsumeindex by incremen ting it, will the ethernet bl ock can continue reading descriptors and receive data. the device driver will probably increment the rxconsumeindex by 3, since the driver will forward the co mplete frame consisting of three fragments to the application, and hence free up three descriptors at the same time.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 255 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet each pair of nibbles transferred on the mii in terface (or four pairs of bits for rmii) are transferred as a byte on the data write interface after being delayed by 128 or 136 cycles for filtering by the receive filter and bu ffer modules. the ethernet block removes preamble, frame start delimiter, and crc from the data and checks the crc. to limit the buffer nodescriptor error proba bility, three descriptors are buffered. the value of the rxproduceindex is only updated after status information has been committed to memory, which is checked by an internal tag protocol in the memory interface. the software device driver will process the receive data, afte r which the device driver will update the rxconsumeindex. for an rmii phy the data between the ethernet block and the phy is communicated at half the data-width and twice the clock frequency (50 mhz). 10.13.5 transmission retry if a collision on the ethernet occurs, it usua lly takes place during the collision window spanning the first 64 bytes of a frame. if collision is detected , the ethernet block will retry the transmission. for this purpose, the first 64 bytes of a frame are buffered, so that this data can be used during the retry. a transmission retry within the first 64 bytes in a frame is fully transparent to the application and device driver software. when a collision occurs outside of the 64 byte collision wi ndow, a latecollision error is triggered, and the transmission is aborted. after a latecollision error, the remaining data in the transmit frame will be discarded. the ethernet block will set the error and latecollision bits in the frame?s status fields. the txerror bit in the intstatus register will be set. if the corresponding bit in the intena ble register is set, the txerror bit in the intstatus register will be propagated to the cpu (via the nvic). the device driver software should catch the interrupt and take appropriate actions. the ?retransmission maximum? field of the clrt register can be used to configure the maximum number of retries before aborting the transmission. 10.13.6 status hash crc calculations for each received frame, the ethernet block is able to detect the destination address and source address and from them calculate the corresponding hash crcs. to perform the computation, the ethernet block features two internal blocks: one is a controller synchronized with the beginning and the end of each frame, the second block is the crc calculator. when a new frame is detected, internal signaling notifies the controller.the controller starts counting the incoming bytes of the frame, which correspond to the destination address bytes. when the sixth (and last) by te is counted, the controller notifies the calculator to store the corresponding 32-bit crc into a first inner register. then the controller repeats counting the next incoming bytes, in order to get synchronized with the source address. when the last byte of the source address is encountered, the controller again notifies the crc calculator, which fr eezes until the next new frame. when the calculator receives this second notification, it stores the present 32-bit crc into a second inner register. then the crcs remain frozen in their own registers until new notifications arise.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 256 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet the destination address an d source address hash crcs being written in the statushashcrc word are the nine most significant bits of the 32-bit crcs as calculated by the crc calculator. 10.13.7 duplex modes the ethernet block can operate in full duplex and half duplex mode. half or full duplex mode needs to be configured by the device driver software during initialization. for a full duplex connection the fullduplex bit of the command register needs to be set to 1 and the full-duplex bit of the mac2 configuration register needs to be set to 1; for half duplex the same bits need to be set to 0. 10.13.8 iee 802.3/clause 31 flow control overview for full duplex connections, the ethernet block supports ieee 8 02.3/clause 31 flow control using pause frames. this type of flow control may be used in full-duplex point-to-point connections. flow control allows a receiver to stall a transmitter e.g. when the receive buffers are (almost) full. for this purpose, th e receiving side sends a pause frame to the transmitting side. pause frames use units of 512 bit times corresponding to 128 rx_clk/tx_clk cycles. receive flow control in full-duplex mode, th e ethernet block will su spend its transmissions when the it receives a pause frame. rx flow control is initiated by the receiving side of the transmission. it is enabled by setting the ?rx flow control? bit in the mac1 configuration register. if the rx flow control? bit is zero, then the et hernet block ignores received pause control frames. when a pause frame is received on the rx side of the ethernet block, transmission on the tx side w ill be interrup ted after the currently transmitting frame has completed, for an amount of time as indicated in the received pause frame. the transmit data path will stop transmitting data for the nu mber of 512 bit slot times encoded in the pause-timer field of the received pause control frame. by default the received pause control frames are not forwarded to the device driver. to forward the receive flow control frames to the device driver, set the ?pass all receive frames? bit in the mac1 configuration register. transmit flow control if case device drivers need to stall the receive data e.g. because software buffers are full, the ethernet block can transmit pause control frames. transmit flow control needs to be initiated by the device driver software; there is no ieee 802.3/31 flow control initiated by hardware, such as the dma managers. with software flow control, the device driver can detect a situation in which the process of receiving frames needs to be interrupted by sending out tx pause frames. note that due to ethernet delays, a few frames can still be received be fore the flow control takes effect and the receive stream stops.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 257 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet transmit flow control is acti vated by writing 1 to the txfl owcontrol bit of the command register. when the ethernet bl ock operates in fu ll duplex mode, this will result in transmission of ieee 802.3/31 pause frames. the flow control continues until a 0 is written to txflowcontrol bit of the command register. if the mac is operating in full-duplex mode, then setting the txflowcontrol bit of the command register will start a pause frame tr ansmission. the value inserted into the pause-timer value field of transmitted pause frames is programmed via the pausetimer[15:0] bits in the flowcontrolcoun ter register. when the txflowcontrol bit is de-asserted, another pause frame having a p ause-timer value of 0x0000 is automatically sent to abort flow control and resume transmission. when flow control be in force for an extend ed time, a sequence of pause frames must be transmitted. this is supported with a mirr or counter mechanism. to enable mirror counting, a nonzero value is written to the mirrorcounter[15:0] bits in the flowcontrolcounter register. when the txflo wcontrol bit is asserted, a pause frame is transmitted. after sending the pause frame, an in ternal mirror counter is initialized to zero. the internal mirror counter starts incrementing one every 512 bit-slot times. when the internal mirror counter re aches the mirrorcounter value, another pause frame is transmitted with pause-timer value equal to the pausetimer field from the flowcontrolcounter register, the internal mirr or counter is reset to zero and restarts counting. the register mirrorcounter[15:0] is usually set to a smaller value than register pausetimer[15:0] to ensure an early expiration of the mirror counter, allowing time to send a new pause frame before the transmission on the other side can resume. by continuing to send pause frames before the transmitting side finishes counting the pause timer, the pause can be extended as long as txflowco ntrol is asserted. this continues until txflowcontrol is de-asserted when a final pause frame having a pause-timer value of 0x0000 is automatically sent to abort flow c ontrol and resume transmission. to disable the mirror counter mechanism, write the value 0 to mirrorcounter field in the flowcontrolcounter register. when using the mirror counter mechanism, account for time-of-flight delays, frame transmission time, queuing delays, crystal frequency tolerances, and response time delays by pr ogramming the mirrorcounter conservatively, typically about 80% of the pausetimer value. if the software device driver sets the mirrorcounter field of the flowcontrolcounter register to zero, the ethernet block will only send one paus e control frame. after sending the pause frame an internal pause counter is in itialized at zero; the internal pause counter is incremented by one every 512 bit-slot time s. once the internal pause counter reaches the value of the pausetimer re gister, the txflowcontrol bit in the command register will be reset. the software device driver can po ll the txflowcontrol bit to detect when the pause completes. the value of the internal counter in the flow control module can be read out via the flowcontrolstatus register. if the mirrorcounter is nonzero, the flowcontrolstatus register will return the value of the internal mirror counter; if the mirrorcounte r is zero the flowcontrolstatus register will return the value of the internal pause counter value. the device driver is allowed to dynamically modify the mirrorcounter register value and switch between zero mirrorcounter and nonzero mirrorcounter modes.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 258 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet transmit flow control is enabled via the ?tx flow control? bit in the mac1 configuration register. if the ?tx flow cont rol? bit is zero, then the mac will not transmit pause control frames, software must not initiate pause frame transmissions, and the txflowcontrol bit in the command register should be zero. transmit flow control example figure 28 illustrates the transmit flow control. in this example, a frame is received while transmitting another frame (full duplex.) the device driver detects that some buffer migh t overrun and enables the transmit flow control by programming the pausetimer and mirrorcounter fields of the flowcontrolcounter register, after which it enables the transmit flow control by setting the txflowcontrol bit in the command register. as a response to the enabling of the flow control a pause co ntrol frame will be sent after the currently transmitting frame has been transmitted. when the pause frame transmission completes the internal mirror counter will start counting bit slots; as soon as the counter reaches the value in the mirrorcounter field another pause frame is transmitted. while counting the transmit da ta path will continue normal transmissions. as soon as software disables transmit fl ow control a zero pause control frame is transmitted to resume the receive process. 10.13.9 half-duplex mode backpressure when in half-duplex mode, backpressure can be generated to stall receive packets by sending continuous preamble that basically ja ms any other transmissions on the ethernet medium. when the ethernet block operates in half duplex mode, asserting the txflowcontrol bit in the comman d register will result in applying cont inuous preamble on the ethernet wire, effectively blocking traffic from any other ethernet station on the same segment. fig 28. transmit flow control mirrorcounter (1/515 bit slots) 400 0 150 300 200 450 350 250 50 100 500 pausetimer mirrorcounter txflowctl clear txflowctl pause control frame transmission pause control frame transmission pause control frame transmission normal transimisson normal receive normal transmission normal receive rmii receive rmii transmit device driver register writes pause in effect
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 259 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet in half duplex mode, when the txflowcontrol bit goes high, continuous preamble is sent until txflowcontrol is de-asserted. if the me dium is idle, the ethernet block begins transmitting preamble, which rais es carrier sense causing all ot her stations to defer. in the event the transmitting of preamble causes a co llision, the backp ressure ?rides through? the collision. the colliding station ba cks off and then defers to the backpressure. if during backpressure, the user wishes to send a frame, the backpressure is interrupted, the frame sent and then the backpressure resumed. if txflowcontrol is asserted for longer than 3.3 ms in 10 mbps mode or 0.33 ms in 100 m bps mode, backpressure will cease sending preamble for several byte times to avoid the jabber limit. 10.13.10 receive filtering features of receive filtering the ethernet mac has several receive packet filtering functions that can be configured from the software driver: ? perfect address filter: allows packets with a perfectly matching station address to be identified and passed to the software driver. ? hash table filter: allows imperfect filteri ng of packets based on the station address. ? unicast/multicast/broadcast filt ering: allows passing of a ll unicast, mult icast, and/or broadcast packets. ? magic packet filter: detection of magic packets to generate a wake-on-lan interrupt. the filtering functions can be logically comb ined to create complex filtering functions. furthermore, the ethernet block can pass or reject runt packets smaller than 64 bytes; a promiscuous mode allows all pack ets to be passed to software. overview the ethernet block has the capab ility to filter out receive fram es by analyzing the ethernet destination address in the frame. this capab ility greatly reduces t he load on the host system, because ethernet frames that are ad dressed to other stations would otherwise need to be inspected and rejected by the device driver software, using up bandwidth, memory space, and host cpu time. address filtering can be implemented using the perfect address filter or the (imperfect) hash filter. the latter produces a 6-bit hash code which can be used as an index into a 64 entry programmable hash table. figure 29 depicts a functional view of the receive filter. at the top of the diagram the ethernet receiv e frame enters the filters. each filter is controlled by signals from control registers; each filter produces a ?ready? output and a ?match? output. if ?ready? is 0 then the match value is ?don?t care?; if a filter finishes filtering then it will assert its ready ou tput; if the filter finds a ma tching frame it will assert the match output along with the ready output. the results of the filters are combined by logic functions into a single rxabor t output. if the rxabor t output is asserted, the frame does not need to be received. in order to reduce memory tr affic, the receive data path has a buffer of 68 bytes. the ethernet mac will only start writ ing a frame to memory after 68 byte delays. if the rxabort signal is asserted during the initial 68 bytes of the frame, the frame can be discarded and removed from the buffer and not stored to memory at all, not using up receive descriptors, etc. if the rxabort signal is asserted after the initial 68 bytes in a frame (probably due to reception of a magic packet), part of the frame is already written to memory and the
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 260 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet ethernet mac will stop writing furt her data in the fram e to memory; the failfilter bit in the status word of the frame will be set to indicate that the soft ware device driver can discard the frame immediately. unicast, broadcast and multicast generic filtering based on the type of fr ame (unicast, multicast or broadcast) can be programmed using the acceptunic asten, acceptmulticasten, or acceptbroadcasten bits of the rxfilterctrl register. setting th e acceptunicast, acceptmulticast, and acceptbroadcast bits causes all frames of types unicast, multicast and broadcast, respectively, to be accepted, ignoring the ethernet destination address in the frame. to program promiscuous mode, i.e. to accept all frames, set all 3 bits to 1. perfect address match when a frame with a unicast destination addres s is received, a perfect filter compares the destination address with the 6 byte station address programmed in the station address registers sa0, sa1, sa2. if the acceptperfecten bi t in the rxfilterctrl register is set to 1, and the address matches, the frame is accepted. imperfect hash filtering fig 29. receive filter block diagram imperfect hash filter acceptunicasten acceptmulticasten acceptmulticasthashen acceptunicasthashen hashfilter perfect address filter packet crc ok? hfready hfmatch pare ady pamatch rxabort fready fmatch rxfilterenwol rxfilterwol stationaddress acceptperfecten
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 261 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet an imperfect filter is available, based on a hash mechanism. this filter applies a hash function to the destination address and uses the hash to access a table that indicates if the frame should be accepted. the advantage of th is type of filter is that a small table can cover any possible address. the disadvantage is that the filtering is imperfect, i.e. sometimes frames are accepted that should have been discarded. ? hash function: ? the standard ethernet cyclic redundancy c heck (crc) function is calculated from the 6 byte destination address in the ethernet frame (this crc is calculated anyway as part of calculating the crc of the whole frame), then bits [28:23] out of the 32-bit crc result are taken to form the hash. the 6-bit hash is used to access the hash table: it is used as an index in t he 64-bit hashfilter register that has been programmed with accept values. if the selected accept value is 1, the frame is accepted. ? the device driver can initialize the hash filter table by writing to the registers hashfilterl and hashfilterh. hashfilterl contains bits 0 through 31 of the table and hashfilterh contains bit 32 through 63 of the table. so, hash value 0 corresponds to bit 0 of the hashfilterl register and hash value 63 corresponds to bit 31 of the hashfilterh register. ? multicast and unicast ? the imperfect hash filter can be applied to multicast addresse s, by setting the acceptmulticasthashen bit in the rxfilter register to 1. ? the same imperfect hash filter that is ava ilable for multicast addresses can also be used for unicast addresses. this is useful to be able to respond to a multitude of unicast addresses without enabling all unicast addresses. the hash filter can be applied to unicast addresses by settin g the acceptunicasth ashen bit in the rxfilter register to 1. enabling and disabling filtering the filters as defined in the sections above can be bypassed by setting the passrxfilter bit in the command register. wh en the passrxfilter bit is se t, all receive frames will be passed to memory. in this case the device driver software has to implement all filtering functionality in software. setting the passrxfilter bit does not affect the runt frame filtering as defined in the next section. runt frames a frame with less than 64 bytes (or 68 byte s for vlan frames) is shorter than the minimum ethernet frame size and therefore c onsidered erroneous; they might be collision fragments. the receive data path automatically filters and discards these runt frames without writing them to memory and using a receive descriptor. when a runt frame has a correct crc there is a po ssibility that it is intended to be useful. the device driver can receive the runt frames with correct crc by setting the passruntframe bit of the command register to 1. 10.13.11 power management the ethernet block supports power management by means of clock switching. all clocks in the ethernet core can be switched off. if wake-up on lan is needed, the rx_clk should not be switched off.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 262 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.13.12 wake-up on lan overview the ethernet block supports power management with remote wake-up over lan. the host system can be powered down, even including part of the ethernet block itself, while the ethernet block continues to listen to packets on the lan. appropriately formed packets can be received and recognized by th e ethernet block and used to trigger the host system to wake up from its power-down state. wake-up of the system takes effect through an interrupt. when a wake-up event is detected, the wakeupint bit in th e intstatus register is set. th e interrupt stat us will trigger an interrupt if the corresponding wakeupinten bit in the intenable register is set. this interrupt should be used by system power management logic to wake up the system. while in a power-down state the packet that generates a wake-up on lan event is lost. there are two ways in which ethernet pack ets can trigger wake-up events: generic wake-up on lan and magic packet. magic packet filtering uses an additional filter for magic packet detection. in both cases a wa ke-up on lan event is only triggered if the triggering packet has a valid crc. figure 29 shows the generation of the wake-up signal. the rxfilterwolstatus register can be read by the software to inspect the reason for a wake-up event. before going to power-down the power management software should clear the register by writing the rxfilterwolclear register. note: when entering in power-down mode, a receive frame might be not entirely stored into the rx buffer. in this situation, afte r turning exiting power-down mode, the next receive frame is corrupted due to the data of the previous frame being added in front of the last received frame. software drivers have to reset the receive data path just after exiting power-down mode. the following subsections describe the two wake-up on lan mechanisms. filtering for wol the receive filter functionality can be used to generate wake-up on lan events. if the rxfilterenwol bit of the rxfilter ctrl register is set, the receiv e filter will set the wakeupint bit of the intstatus register if a frame is received that passes the f ilter. the interrupt will only be generated if the crc of the frame is correct. magic packet wol the ethernet block supports wake-up using magic packet technology (see ?magic packet technology?, advanced micro devices). a magic packet is a specially formed packet solely intended for wake-up purposes. this packet ca n be received, analyzed and recognized by the ethernet block and used to trigger a wake-up event. a magic packet is a packet that contains in it s data portion the station address repeated 16 times with no breaks or interruptions, preceded by 6 magic packet synchronization bytes with the value 0xff. other data may be surrounding the magic packet pattern in the data portion of the packet. the whole pa cket must be a well-formed ethernet frame.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 263 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet the magic packet detection unit analyzes th e ethernet packets, extracts the packet address and checks the payload for the magic packet pattern. the address from the packet is used for matching the pattern (not the address in the sa0/1/2 registers.) a magic packet only sets the wake-up in terrupt status bit if the packet passes the receive filter as illustrated in figure 29 : the result of the receive filter is anded with the magic packet filter result to produce the result. magic packet filtering is enabled by setting the magicpac ketenwol bit of the rxfilterctrl register. note that when doing magic packet wol, the rxfilterenwol bit in the rxfilterctrl register should be 0. setting the rxfilterenwol bit to 1 would accept all packets for a matching address, not just the magic packets i.e. wol using magic packets is more strict. when a magic packet is detected, apart from the wakeupint bit in the intstatus register, the magicpacketwol bit is set in the rxfilter wolstatus register. software can reset the bit writing a 1 to the corresponding bit of the rxfilterwolclear register. example: an example of a magic packet with station address 0x11 0x22 0x33 0x44 0x55 0x66 is the following (misc indicates miscellaneous additional data bytes in the packet):
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