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this document is a general product description and is subject to change without notice. hynix do es not assume any responsibilit y for use of circuits described. no patent licenses are implied. rev. 0.1 / feb. 2004 1 preliminary HY5Y7A2DLM-hf 4banks x 4m x 32bits synchronous dram document title 4bank x 4m x 32bits synchronous dram revision history revision no. history draft date remark 0.1 initial draft feb. 2004 preliminary
this document is a general product description and is subject to change without notice. hynix do es not assume any responsibilit y for use of circuits described. no patent licenses are implied. rev. 0.1 / feb. 2004 2 preliminary HY5Y7A2DLM-hf 4banks x 4m x 32bits synchronous dram description the hynix mobile sdr is suited for non-pc application which use the batteries such as pdas, 2.5g and 3g cellular phones with internet access and multimedia capabilities, mini-notebook, handheld pcs. the hynix HY5Y7A2DLM-hf is a 536,870, 912bit cmos synchronous dynamic random access memory. it is organized as 4banks of 4,194,304x32. the mobile sdr provides for programmable options including cas latency of 1, 2, or 3, read or write burst length of 1, 2, 4, 8, or full page, and the burst count sequence(seque ntial or interleave). and the mobile sdr also provides for special programmable options including partial array self refresh of a quarter bank, a half bank, 1bank, 2banks, or all banks, temperature compensated self refresh of 15, 45, 70, or 85 degrees o c. a burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle(this pipelined design is not restricted by a 2n rule). deep power down mode is a additional operating mode fo r mobile sdr. this mode can achieve maximum power re- duction by removing power to the memory array within each sdr. by using this feature, the system can cut off alomost all dram power without adding the cost of a power switch and giving up mother-board power-line layout flexibility. features standard sdr protocol internal 4bank operation voltage : vdd = 3.0v, vddq = 3.0v lvcmos compatible i/o interface low voltage interface to reduce i/o power low power features - pasr(partial array self refresh) -tcsr (temperature compensated self refresh) - ds (drive strength) - deep power down mode programmable cas latency of 1, 2 or 3 90 ball fbga package - HY5Y7A2DLM-hf : lead - HY5Y7A2DLMp-hf : lead free ordering information part number clock frequency cas latency organization interface HY5Y7A2DLM(p)-hf 133mhz 3 4banks x 4mb x 32 lvcmos
rev. 0.1 / feb. 2004 3 preliminary HY5Y7A2DLM-hf 4banks x 4m x 32bits synchronous dram ball configuralation dq26 dq28 vssq vssq vddq vss a4 a7 clk dqm1 vddq vssq vssq dq11 dq13 dq24 vddq dq27 dq29 dq31 dqm3 a5 a8 cke nc dqs dq10 dq12 vddq dq15 vss vssq dq25 dq30 nc a3 a6 a12 a9 nc vss dq9 dq14 vssq vss vdd vddq dq22 dq17 nc a2 a10 nc ba0 /cas vdd dq6 dq1 vddq vdd dq23 vssq dq20 dq18 dq16 dqm2 a0 ba1 /cs /we dq7 dq5 dq3 vssq dq0 dq21 dq19 vddq vddq vssq vdd a1 a11 /ras dqm0 vssq vddq vddq dq4 dq2 1 1 2 2 3 3 7 7 8 8 9 9 4 4 5 5 6 6 a a b b c c d d e e f f g g h h j j k k l l m m n n p p r r top view dq26 dq28 vssq vssq vddq vss a4 a7 clk dqm1 vddq vssq vssq dq11 dq13 dq24 vddq dq27 dq29 dq31 dqm3 a5 a8 cke nc dqs dq10 dq12 vddq dq15 vss vssq dq25 dq30 nc a3 a6 a12 a9 nc vss dq9 dq14 vssq vss vdd vddq dq22 dq17 nc a2 a10 nc ba0 /cas vdd dq6 dq1 vddq vdd dq23 vssq dq20 dq18 dq16 dqm2 a0 ba1 /cs /we dq7 dq5 dq3 vssq dq0 dq21 dq19 vddq vddq vssq vdd a1 a11 /ras dqm0 vssq vddq vddq dq4 dq2 1 1 2 2 3 3 7 7 8 8 9 9 4 4 5 5 6 6 a a b b c c d d e e f f g g h h j j k k l l m m n n p p r r top view
rev. 0.1 / feb. 2004 4 preliminary HY5Y7A2DLM-hf 4banks x 4m x 32bits synchronous dram pad function descriptions symbol type description clk input clock : the system clock input. all other inputs are registered to the sdr on the rising edge of clk cke input clock enable : controls internal clock sign al and when deactivated, the sdr will be one of the states among power down, suspend or self refresh cs input chip select : enables or disables al l inputs except clk, cke, udqm and ldqm ba0, ba1 input bank address : selects bank to be activated during ras activity selects bank to be read/written during cas activity a0 ~ a12 input row address : ra0 ~ ra12, column address : ca0 ~ ca8 auto-precharge flag : a10 ras , cas , we input command inputs : ras , cas and we define the operation refer function truth table for details udqm, ldqm input data mask:controls output buffers in read mode and masks input data in write mode dq0 ~ dq31 i/o data input/output:mul tiplexed data input/output pin vdd/vss supply power supply for internal circuits vddq/vssq supply power supply for output buffers nc - no connection : these pads should be left unconnected
rev. 0.1 / feb. 2004 5 preliminary HY5Y7A2DLM-hf 4banks x 4m x 32bits synchronous dram functional block diagram 4mbit x 4banks x 32 i/o low power synchronous dram internal row counter column pre decoder column add counter self refresh logic & timer extended mode register sense amp & i/o gate i/o buffer & logic address register burst counter mode register state machine address buffers bank select column active row active cas latency clk cke cs ras cas we u/ldqm a0 a1 ba1 ba0 a12 pasr, tcsr row pre decoder refresh dq0 dq31 row decoders row decoders row decoders row decoders column decoders 4mx32 bank 0 4mx32 bank 1 4mx32 bank 2 4mx32 bank 3 memory cell array data out control burst length
rev. 0.1 / feb. 2004 6 preliminary HY5Y7A2DLM-hf 4banks x 4m x 32bits synchronous dram basic functional description mode register ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0000 op code 00 cas latency bt burst length op code a9 write mode 0burst read and burst write 1 burst read and single write burst type a3 burst type 0sequential 1interleave burst length a2 a1 a0 burst length a3 = 0 a3=1 00 0 1 1 00 1 2 2 01 0 4 4 01 1 8 8 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 full page reserved cas latency a6 a5 a4 cas latency 0 0 0 r e s e r v e d 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 reserved 1 0 1 r e s e r v e d 1 1 0 r e s e r v e d 1 1 1 reserved
rev. 0.1 / feb. 2004 7 preliminary HY5Y7A2DLM-hf 4banks x 4m x 32bits synchronous dram basic functional description (continued) extended mode register note 1) just guarantee for extended and indus trial part ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 1000000 ds tcsr pasr ds (driver strength) a6 a5 driver strength 00full 0 1 1/2 strength 1 0 1/4 strength 11reserved pasr (partial array self refresh) a2 a1 a0 self refresh coverage 000all banks 001half of total bank (ba1=0) 0 1 0 quarter of total bank (ba1=ba0=0) 0 1 1 reserved 1 0 0 reserved 101 one eighth of total bank (row address msb=0) 110 one sixteenth of total bank (row address 2 msbs=0) 1 1 1 reserved tcsr (temperature compensated self refresh) a4 a3 temperature ( o c ) 0 0 45 ~ 70 0 1 15 ~ 45 1 0 -25 ~ 15 1 1 70 ~ 85 1)
rev. 0.1 / feb. 2004 8 preliminary HY5Y7A2DLM-hf 4banks x 4m x 32bits synchronous dram power up and initialization like a synchronous dram, mobile sdr must be powered up and initialized in a predefin ed manner. power must be applied to vdd and vddq(simultaneously). the clock signal must be started at the same time. after power up, an initial pause of 200 usec is required. an d a precharge all command will be issued to the mobile sdr. then, 8 or more auto refresh cycles will be provided. after the auto refr esh cycles are completed, a mode register set(mrs) command will be issued to program the specific mode of operation (c as latency, burst length, etc.) and a extended mode register set command will be issued to progra m specific mode of self refresh operat ion(pasr & tcsr). the following these cycles, the mobile sdr is ready for normal opeartion. programming the registers mode register the mode register contains the specific mode of operation of the mobile sdr. this register includes the selection of a burst length(1, 2, 4, 8, full page), a cas latency(1, 2, or 3), a burst type. the mode register set must be done before any activate command after the power up sequence. any contents of the mode register be altered by re-programming the mode register through the execution of mode register set command. extended mode register the extended mode register contains the specific features of self refresh opeartion of the mobile sdr. this register includes the selection of part ial arrays to be refreshed(half array, quarte r array, etc.), tempearture range of the de- vice(85, 70, 45, 15 o c) for reducing current consumption during self refresh. the extended mode register set must be done before any activate command after the power up sequence. any contents of the mode register be altered by re- programming the mode register through the exec ution of extended mode register set command. bank(row) active the bank active command is used to ac tivate a row in a specified bank of th e device. this command is initiated by activating cs , ras and deasserting cas , we at the positive edge of the clock. the value on the ba1 and ba0 selects the bank, and the value on the a0-a12 selects the row. this row remain s active for column access until a precharge command is issued to that bank. read and write opeartions can only be initiated on this activated bank after the min- imum trcd time is passed from the activate command. read the read command is used to initia te the burst read of data. this co mmand is initiated by activating cs , cas , and deasserting we , ras at the positive edge of the clock. ba1 and ba0 inputs select the bank, a8-a0 address inputs select the sarting column location. the value on input a10 determines whether or not auto precharge is used. if auto pre- charge is selected the row being accessed will be precharged at the end of the read burs t; if auto precharge is not selected, the row will remain active for subsequent accesse s.the length of burst and the cas latency will be determined by the values programmed during the mrs command. write the write command is used to initia te the burst write of data. this co mmand is initiated by activating cs , cas , we and deasserting ras at the positive edge of the clock. ba1 and ba0 inputs select the bank, a8-a0 address inputs select the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto pre- charge is selected the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain ac tive for subsequent accesses.
rev. 0.1 / feb. 2004 9 preliminary HY5Y7A2DLM-hf 4banks x 4m x 32bits synchronous dram precharge the precharge command is used to close the open row in a particular bank or the open row in all banks. when the precharge command is issued with address a10, high, then al l banks will be precharged, and if a10 is low, the open row in a particular bank will be precharged. the bank(s) wi ll be available when the mini mum trp time is met after the precharge command is issued. auto precharge the auto precharge command is issued to close the open ro w in a particular bank after read or write operation. if a10 is high when a read or write co mmand is issued, the read or write with auto precharge is initiated. burst termination the burst termination is used to terminate the burst operatio n. this function can be acco mplished by asserting a burst stop command or a precharge command during a burst read or write operation. the precharge command interrupts a burst cycle and close the active bank, and the burst stop command terminates the existing burst operation leave the bank open. data mask the data mask comamnd is used to mask read or write data. during a read operation, when this command is issued, data ouputs are disabled and become high impeda nce after two clock delay. during a write operation, when this command is issued, data inputs ca n?t be written with no clock delay. clock suspend the clock suspend command is used to suspend the internal clock of dram. during normal access mode, cke is keeping high. when cke is low, it freeze s the internal clock and extends data read and write operations. power down the power down command is used to re duce standby current. before this command is issued , all banks must be pre- charged and trp must be passed after a precharge command. once the power down comman d is initiated by keeping cke low, all of the input buffer except cke are gated off. auto refresh the auto refresh command is used during normal operation and is similar to cbr refresh in coventional drams. this command must be issued each time a refresh is required. when an auto refresh command is issued , the address bits is ?don?t care?, because the specific address bits is generated by internal refresh address counter. self refresh the self refresh command is used to re tain cell data in the mobile sdr. in the self refresh mode, the mobile sdr operates refresh cycle asynchronously. the self refresh co mmand is initiated like an auto refresh command except cke is disabled(low). the mob ile sdr can accomplish an special self refr esh operation by the specific modes(tcsr, pasr) programmed in extended mode registers. the mobile sdr can control the refresh rate by the temperature value of tcsr (temperature compensated self refresh) and se lect the memory array to be refreshed by the value of pasr(partial array self refresh). the mobile sdr can reduce the self refresh current(idd6) by using these two modes. deep power down the deep power down mode is used to achieve maximum power reduction by cutting the power of the whole memory array of the devices. for more information, see the specia l operation for low power consumption of this data sheet.
rev. 0.1 / feb. 2004 10 preliminary HY5Y7A2DLM-hf 4banks x 4m x 32bits synchronous dram command truth table note : 1. exiting self refresh occurs by asynch ronously bringing cke from low to high. 2. ba1/ba0 must be issued 0/0 in the mode register set, and 1/0 in the extended mode register set. function cken-1 cken cs ras cas we dqm addr a10 /ap ba note mode register set h x l l l l x op code 2 extended mode register set h x l l l l x op code 2 no operation h x l h h h x x device deselect h x h x x x x x bank active h x l l h h x row address v read h x lh lh columnl v read with autoprecharge h x lh lh xcolumnh v write h x l h l l x column l v write with autoprecharge h x l h l l x column h v precharge all banks h x l l h l x x h x precharge selected bank h x l l h l x x l v burst stop h x l h h l x x data write/output enable h x x x x data mask/output disable h x x v x auto refresh h h l l l h x x self refresh entry h l l l l h x x self refresh exit l h hx xx xx1 lhhh precharge power down entry h l hx xx xx lhhh precharge power down exit l h hx xx xx lhhh clock suspend entry h l hx xx xx lv vv clock suspend exit l h x x x deep power down entry h l l h h l x x deep power down exit l h x x x
rev. 0.1 / feb. 2004 11 preliminary HY5Y7A2DLM-hf 4banks x 4m x 32bits synchronous dram current state truth table (sheet 1 of 4) current state command action notes cs ras cas we ba0/ ba1 a11-a0 description idle l l l l op code mode register set set the mode register 14 l l l h x x auto or self refresh start auto or self refresh 5 l l h l ba x precharge no operation l l h h ba row add. bank activate activate the specified bank and row lh l l ba col add. a10 write/writeap illegal 4 lh l h ba col add. a10 read/readap illegal 4 l h h h x x no operation no operation 3 h x x x x x device deselect no operation or power down 3 row active l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge precharge 7 l l h h ba row add. bank activate illegal 4 lh l l ba col add. a10 write/writeap start write : optional ap(a10=h) 6 lh l h ba col add. a10 read/readap start read : optional ap(a10=h) 6 l h h h x x no operation no operation h x x x x x device deselect no operation read l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 llhl ba x precharge termination burst: start the precharge l l h h ba row add. bank activate illegal 4 lh l l ba col add. a10 write/writeap termination burst: start write(optional ap) 8,9 lh l h ba col add. a10 read/readap termination burst: start read(optional ap) 8 l h h h x x no operation continue the burst
rev. 0.1 / feb. 2004 12 preliminary HY5Y7A2DLM-hf 4banks x 4m x 32bits synchronous dram current state truth table (sheet 2 of 4) current state command action notes cs ras cas we ba0/ ba1 a11-a0 description read h x x x x x device deselect continue the burst write l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 llh l ba x precharge termination burst: start the precharge 10 l l h h ba row add. bank activate illegal 4 lh l l ba col add. a10 write/writeap termination burst: start write(optional ap) 8 lh l h ba col add. a10 read/readap termination burst: start read(optional ap) 8,9 l h h h x x no operation continue the burst h x x x x x device deselect continue the burst read with auto precharge l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge illegal 4,12 l l h h ba row add. bank activate illegal 4,12 l h l l ba col add. a10 write/writeap illegal 12 l h l h ba col add. a10 read/readap illegal 12 l h h h x x no operation continue the burst h x x x x x device deselect continue the burst write with auto precharge l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge illegal 4,12 l l h h ba row add. bank activate illegal 4,12 l h l l ba col add. a10 write/writeap illegal 12 l h l h ba col add. a10 read/readap illegal 12 l h h h x x no operation continue the burst h x x x x x device deselect continue the burst
rev. 0.1 / feb. 2004 13 preliminary HY5Y7A2DLM-hf 4banks x 4m x 32bits synchronous dram current state truth table (sheet 3 of 4) current state command action notes cs ras cas we ba0/ ba1 a11-a0 description precharging l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 llh l ba x precharge no operation: bank(s) idle after t rp l l h h ba row add. bank activate illegal 4,12 l h l l ba col add. a10 write/writeap illegal 4,12 l h l h ba col add. a10 read/readap illegal 4,12 lhh h x x no operation no operation: bank(s) idle after t rp h x x x x x device deselect no operation: bank(s) idle after t rp row activating l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge illegal 4,12 l l h h ba row add. bank activate illegal 4,11,1 2 l h l l ba col add. a10 write/writeap illegal 4,12 l h l h ba col add. a10 read/readap illegal 4,12 lhh h x x no operation no operation: row active after t rcd h x x x x x device deselect no operation: row active after t rcd write recovering l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge illegal 4,13 l l h h ba row add. bank activate illegal 4,12 l h l l ba col add. a10 write/writeap start write: optional ap(a10=h) l h l h ba col add. a10 read/readap start read: optional ap(a10=h) 9 lhh h x x no operation no operation: row active after t dpl
rev. 0.1 / feb. 2004 14 preliminary HY5Y7A2DLM-hf 4banks x 4m x 32bits synchronous dram urrent state truth table (sheet 4 of 4) current state command action notes cs ras cas we ba0/ ba1 a11-a0 description write recovering h x x x x x device deselect no operation: row active after t dpl write recovering with auto precharge l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge illegal 4,13 l l h h ba row add. bank activate illegal 4,12 l h l l ba col add. a10 write/writeap illegal 4,12 l h l h ba col add. a10 read/readap illegal 4,9,12 lhh h x x no operation no operation: precharge after t dpl h x x x x x device deselect no operation: precharge after t dpl refreshing l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge illegal 13 l l h h ba row add. bank activate illegal 13 l h l l ba col add. a10 write/writeap illegal 13 l h l h ba col add. a10 read/readap illegal 13 lhh h x x no operation no operation: idle after t rc h x x x x x device deselect no operation: idle after t rc mode register accessing l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge illegal 13 l l h h ba row add. bank activate illegal 13 l h l l ba col add. a10 write/writeap illegal 13 l h l h ba col add. a10 read/readap illegal 13 lhh h x x no operation no operation: idle after 2 clock cycles h x x x x x device deselect no operation: idle after 2 clock cycles
rev. 0.1 / feb. 2004 15 preliminary HY5Y7A2DLM-hf 4banks x 4m x 32bits synchronous dram note : 1. h: logic high, l: logic low, x: don ' t care, ba: bank address, ap: auto precharge. 2. all entries assume that cke was active during the preceding clock cycle. 3. if both banks are idle and cke is inactive, then in power down cycle 4. illegal to bank in specified states. function may be legal in the bank indicated by bank address, depending on the state of that bank. 5. if both banks are idle and cke is inactive, then self refresh mode. 6. illegal if t rcd is not satisfied. 7. illegal if t ras is not satisfied. 8. must satisfy burst interrupt condition. 9. must satisfy bus contention, bus turn around, and/or write recovery requirements. 10. must mask preceding data which don ' t satisfy t dpl . 11. illegal if t rrd is not satisfied 12. illegal for single bank, but legal for other banks in multi-bank devices. 13. illegal for all banks. 14. mode register set and extended mode regist er set is same command truth table except ba1.
rev. 0.1 / feb. 2004 16 preliminary HY5Y7A2DLM-hf 4banks x 4m x 32bits synchronous dram cke enable(cke) truth table (sheet 1 of 2) current state cke command action notes previous cycle current cycle cs ras cas we ba0, ba1 a11- a0 self refresh h x xx xxx x invalid 1 lhhxxxxx exit self refresh with device deselect 2 lhlhhhxx exit self refresh with no operation 2 lhlhhlxx illegal 2 lhlhlxxx illegal 2 lhllxxxx illegal 2 l l xx xxx x maintain self refresh power down h x xx xxx x invalid 1 lh hx xxx x power down mode exit, all banks idle 2 lhhhx x lhl lxxx x illegal 2 xlxx x xxlx x l l xx xxx x maintain power down mode deep power down h x xx xxx x invalid 1 l h xx xxx x deep power down mode exit 5 l l xx xxx x maintain deep power down mode
rev. 0.1 / feb. 2004 17 preliminary HY5Y7A2DLM-hf 4banks x 4m x 32bits synchronous dram cke enable(cke) truth table (sheet 2 of 2) note : 1. for the given current state cke must be low in the previous cycle. 2. when cke has a low to high transition, the clock and other in puts are re-enabled asynchronously. when exiting power down mod e, a nop (or device deselect) command is required on the first positive edge of clock after cke goes high. 3. the address inputs depend on the command that is issued. 4. the precharge power down mode, the self refresh mode, and the mode register set can only be entered from the all banks idle state. 5. when cke has a low to high transition, the cloc k and other inputs are re -enabled asynchronously. when exiting deep power down mode, a nop (or device de select) command is required on the first positive edge of clock after cke goes high and is maintained for a minimum 200usec. current state cke command action notes previous cycle current cycle cs ras cas we ba0, ba1 a11- a0 all banks idle hhhxxx refer to the idle state section of the current state truth table 3 hhlhxx 3 hhllhx 3 hhlllhxx auto refresh h h l l l l op code mode register set 4 hlhxxx refer to the idle state section of the current state truth table 3 hllhxx 3 hlllhx 3 hllllhxx entry self refresh 4 h l l l l l op code mode register set l x xx xxx x power down 4 h l l h h l x x deep power down 4 any state other than listed above h h xx xxx x refer to operations of the current state truth table h l xx xxx x begin clock suspend next cycle l h xx xxx x exit clock suspend next cycle l l xx xxx x maintain clock suspend
rev. 0.1 / feb. 2004 18 preliminary HY5Y7A2DLM-hf 4banks x 4m x 32bits synchronous dram absolute maximum rating dc operating condition (t a = -25 to 70 o c ) note : 1. all voltages are referenced to v ss = 0v 2. v ddq must not exceed the level of v dd ac operating test condition (t a = -25 to 70 o c , v dd = 2.7 ~ 3.6v, v ss = 0v) parameter symbol rating unit ambient temperature t a -25 ~ 70 o c storage temperature t stg -55 ~ 125 o c voltage on any pin relative to v ss v in , v out -1.0 ~ 4.6 v voltage on v dd relative to v ss v dd -1.0 ~ 4.6 v voltage on v ddq relative to v ss v ddq -1.0 ~ 4.6 v short circuit output current i os 50 ma power dissipation pd 1 w soldering temperature . time t solder 260 . 10 o c . sec parameter symbol min typ max unit note power supply voltage v dd 2.7 3.0 3.6 v 1 power supply voltage v ddq 2.7 3.0 3.6 v 1, 2 input high voltage v ih 2.2 - v ddq+ 0.3 v 1, 2 input low voltage v il -0.3 - 0.5 v 1, 2 parameter symbol value unit note ac input high/low level voltage v ih / v il 2.4/0.4 v input timing measurement reference level voltage v trip 0.5*v ddq v input rise/fall time t r / t f 1ns output timing measurement reference level voltage v outref 0.5*v ddq v output load capacitance for access time measurement cl pf 1
rev. 0.1 / feb. 2004 19 preliminary HY5Y7A2DLM-hf 4banks x 4m x 32bits synchronous dram capacitance (t a = 25 o c , f=1mhz, v dd =3.3v) note 1. dc characterristics i (t a = -25 to 70 o c ) note : 1. v in = 0 to 3.0v. all other pi ns are not tested under v in =0v. 2. d out is disabled. v out = 0 to 3.6v. 3. i out = - 0.1ma 4. i out = + 0.1ma parameter pin symbol min max unit input capacitance clk ci1 tbd tbd pf a0 ~ a12, ba0, ba1, cke, cs , ras , cas , we , dqm0~3 ci2 tbd tbd pf data input / output capaci- tance dq0 ~ dq31 ci/o tbd tbd pf parameter symbol min max unit note input leakage current i li -1 1 ua 1 output leakage current i lo -1 1 ua 2 output high voltage v oh 2.4 - v 3 output low voltage v ol -0.4v4 zo=50? output vtt=0.5xvddq 50? 30pf
rev. 0.1 / feb. 2004 20 preliminary HY5Y7A2DLM-hf 4banks x 4m x 32bits synchronous dram dc characteristics ii (t a = -25 to 70 o c ) note : 1. i dd1 and i dd4 depend on output loading and cycle rates. spec ified values are measured with the output open 2. see the tables of next page for more specific i dd6 current values. parameter symbol test condition speed unit note h operating current i dd1 burst length=1, one bank active t rc t rc (min), i ol =0ma 180 ma 1 precharge standby current in power down mode i dd2p cke v il (max), t ck = 15ns 1.0 ma i dd2ps cke v il (max), t ck = 0.7 ma precharge standby current in non power down mode i dd2n cke v ih (min), cs v ih (min), t ck = 15ns input signals are changed one time during 2clks. all other pins v dd -0.2v or 0.2v 30 ma i dd2ns cke v ih (min), t ck = input signals are stable. 14 active standby current in power down mode i dd3p cke v il (max), t ck = 15ns 10 ma i dd3ps cke v il (max), t ck = 10 active standby current in non power down mode i dd3n cke v ih (min), cs v ih (min), t ck = 15ns input signals are changed one time during 2clks. all other pins v dd -0.2v or 0.2v 50 ma i dd3ns cke v ih (min), t ck = input signals are stable. 50 burst mode operating current i dd4 t ck t ck (min), i ol =0ma all banks active 240 ma 1 auto refresh current i dd5 t rc t rc (min), all banks active 360 ma self refresh current i dd6 cke 0.2v see next page ma 2 standby current in deep power down mode i dd7 see p.24~25 140 ua
rev. 0.1 / feb. 2004 21 preliminary HY5Y7A2DLM-hf 4banks x 4m x 32bits synchronous dram dc characteristic s iii - low power i dd6 temp. ( o c) memory array unit 4 banks 2 banks 1 bank 70 1260 860 620 ua 45 820 620 500 ua 15 660 500 400 ua
rev. 0.1 / feb. 2004 22 preliminary HY5Y7A2DLM-hf 4banks x 4m x 32bits synchronous dram ac characteristics i (ac operating conditions unless otherwise noted) note : 1. assume t r / t f (input rise and fall time) is 1ns. if t r & t f > 1ns, then [(t r +t f )/2-1]ns should be added to the parameter. 2. access time to be measured with input signal s of 1v/ns edge rate, from 0.8v to 0.2v. if t r > 1ns, then (t r /2-0.5)ns should be added to the parameter. parameter symbol b unit note min max system clock cycle time cas latency=3 t ck3 7.5 1000 ns cas latency=2 t ck2 9.5 ns clock high pulse width t chw 2.5 - ns 1 clock low pulse width t clw 2.5 - ns 1 access time from clock cas latency=3 t ac3 -5.4 ns 2 cas latency=2 t ac2 -7 ns data-out hold time t oh 2.5 - ns data-input setup time t ds 2- ns 1 data-input hold time t dh 1- ns 1 address setup time t as 2- ns 1 address hold time t ah 1- ns 1 cke setup time t cks 2- ns 1 cke hold time t ckh 1- ns 1 command setup time t cs 2- ns 1 command hold time t ch 1- ns 1 clk to data output in low-z time t olz 1- ns clk to data output in high-z time cas latency=3 t ohz3 5.4 ns cas latency=2 t ohz2 7ns
rev. 0.1 / feb. 2004 23 preliminary HY5Y7A2DLM-hf 4banks x 4m x 32bits synchronous dram ac characteristics ii (ac operating conditions unless otherwise noted) note : 1. a new command can be given t rc after self refresh exit. parameter symbol b unit note min max ras cycle time t rc 65 - ns ras to cas delay t rcd 19 - ns ras active time t ras 45 100k ns ras precharge time t rp 19 - ns ras to ras bank active delay t rrd 15 - ns cas to cas delay t ccd 1-clk write command to data-in delay t wtl 0 - clk data-in to precharge command t dpl 2-clk data-in to active command t dal t dpl +t rp dqm to data-out hi-z t dqz 2-clk dqm to data-in mask t dqm 0-clk mrs to new command t mrd 2-clk precharge to data output high-z cas latency=3 t proz3 3- clk cas latency=2 t proz2 2clk power down exit time t dpe 1-clk power down exit time t dpe 1-clk self refresh exit time t sre 1-clk1 refresh time t ref -64ms
rev. 0.1 / feb. 2004 24 preliminary HY5Y7A2DLM-hf 4banks x 4m x 32bits synchronous dram special operation for low power consumption deep power down mode deep power down mode is an operating mode to achieve ma ximum power reduction by cutting the power of the whole memory array of the devices. data will not be retained once the device enters deep power down mode. full initialization is required when the device exits from deep power down mode. truth table deep power down mode entry the deep power down mode is entered by having cs and we held low with ras and cas high at the rising edge of the clock, while cke is low. the following di agram illustrates deep power down mode entry. current state command cke n-1 cke n cs ras cas we idle deep power down entry h l l h h l deep power downdeep power down exitl h xxxx clk cke cs ras cas we t rp precharge if needed deep power down entry
rev. 0.1 / feb. 2004 25 preliminary HY5Y7A2DLM-hf 4banks x 4m x 32bits synchronous dram deep power down mode (continued) deep power down mode exit sequence the deep power down mode is exited by asserting cke high. after the exit, the following sequence is needed to enter a new command. 1. maintain nop input conditions for a minimum of 200usec 2. issue precharge commands for all banks of the device 3. issue 8 or more auto refresh commands 4. issue a mode register set command to initialize the mode register 5. issue an extended mode register set command to initialize the extended mode register the following timing diagra m illustrates deep power down mode exit sequence. clk cke cs ras cas we deep power down exit all banks precharge auto refresh auto refresh mode register set extended mode register set new command accepted here 200 s trp trc
rev. 0.1 / feb. 2004 26 preliminary HY5Y7A2DLM-hf 4banks x 4m x 32bits synchronous dram package information 90 ball 0.8mm pitch, 11mm x 13mm fbga unit [mm] 1.40 max 0.340 0.05 0.450 0.05 11.0 6.40 bsc 0.80( typ) a1 index mark 13.0 0.10 11.20 bsc 0.80( typ) 6.50 0.05 3.20 0.05 5.50 0.05 bottom bottom view view 2.30 0.10 0.80( 6.50 0.05 bottom view

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