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  HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew 2.4ghz transceiver 8-bit otp mcu rev. 1.00 1 march 15, 2010 general description the device is an 8-bit high performance, risc architec- ture microcontroller devices specifically designed for multiple i/o, mouse/keyboard appliances and spi con- trol product applications. the advantages of low power consumption, i/o flexibility, timer functions, watchdog timer, power down, wake-up functions together with the optional peripherals such as eeprom memory and rf transceiver provide the devices with versatility for indus- trial control, consumer products, subsystem controllers, rf module control, etc. features  operating voltage: f sys = 6mhz: 1.8v~3.3v  internal 6mhz rc oscillator for f sys  power down and wake-up functions to reduce power consumption  two bit to define microcontroller system clock (f sys /1, f sys /2, f sys /4)  all instructions executed in one or two machine cycles  table read instructions  63 powerful instructions  6-level subroutine nesting  bit manipulation instruction  program memory: 4k 15  data memory: 128 8~1608  watchdog timer function  up to 40 bidirectional i/o lines with pull-high options  all i/o pins have falling and rising edge wake-up function  single 16-bit internal timer with overflow interrupt and timer input  spi interface shared with i/o lines  low voltage reset function (lvr) for dc_dc output controlled by configuration option  built-in dc/dc to provide stable 2.8v, 3.0v, 3.3v with error  5% selected by configuration options  low voltage detector (lvd) with levels 1.8v/2.0v/2.2v/2.5v/2.8v  5% for battery input (bat_in) selected by application program  wide range of available package types  optional peripheral -- eeprom memory with 128 8 capacity  optional peripheral -- rf transceiver with 2.4ghz rf frequency
selection table part no. program memory data memory data eeprom i/o timer dc/dc converter spi interface rf transceiver built-in osc stack package HT82M75R 4k  15 1288  24 16-bit 1   6 20/28sop/ssop 32qfn ht82k75r 4k  15 1608  40 16-bit 1   6 48ssop HT82M75Re (1) 4k 15 128 8 128 8 22 16-bit1   6 32qfn ht82k75re (1) 4k 15 160 8 128 8 38 16-bit1   6 48ssop HT82M75Rew (2) 4k 15 128 8 128 8 15 16-bit1   6 40qfn (660.85mm) ht82k75rew (2) 4k 15 160 8 128 8 31 16-bit1    6 64lqfp note: (1) there is an additional peripheral known as the data eeprom with capacity of 128 bytes in HT82M75Re and ht82k75re devices. all information related to the data eeprom will be described in the following eeprom data memory section. (2) there are additional peripherals named rf transceiver with rf frequency of 2.4ghz and data eeprom with capacity of 128 bytes in HT82M75Rew and ht82k75rew devices. all information related to the rf transceiver and eeprom data memory will be described in the corresponding section respectively. (3) as devices exist in more than one package format, the table reflects the situation for the package with the most pins. block diagram HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 2 march 15, 2010        
   
  
            
          
              
  
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pin description the following table only includes the pins which are directly related to the mcu. the pin descriptions of the additional peripheral functions are located at the corresponding section of the datasheet along with the relevant peripheral func - tion functional description. pin name i/o options description pa0~pa1 pa2/tmr pa3~pa7 i/o pull-high wake-up bidirectional 8-bit input/output port. each pin can be configured as a wake-up input (both falling and rising edge) by a configuration option. soft - ware instructions determine if the pin is a cmos output or schmitt trigger input. configuration options determine if the pins have pull-high resistors. pa2 is shared with the external timer input pin tmr. pb0/scs pb1~pb7 i/o pull-high or wake-up cmos/nmo s bidirectional 8-bit input/output port. each pin can be configured as a wake-up input (both falling and rising edge) by a configuration option. soft - ware instructions determine if the pin is a cmos output or schmitt trigger input. configuration options determine if the pins have pull-high resistors. also a configuration option determines if the pb0 is a cmos output type or nmos output type. pb0 is shared with scs of the spi interface. pc0~pc1 pc2/int pc3~pc4 pc5/sdi pc6/sdo pc7/sck i/o pull-high or wake-up cmos/nmo s bidirectional 8-bit input/output port. each pin can be configured as a wake-up input (both falling and rising edge) by a configuration option. soft - ware instructions determine if the pin is a cmos output or schmitt trigger input. configuration options determine if the pins have pull-high resistors. also a configuration option determines if the pc pins are cmos output type or nmos output type. the int is shared with pc2, pc5~pc7 are shared with the spi interface. pd0~pd7 (ht82k75r only) i/o pull-high or wake-up bidirectional 8-bit input/output port. each nibble can be configured as wake-up inputs (both falling and rising edge) by a configuration option. soft- ware instructions determine if the pin is a cmos output or schmitt trigger input. configuration options determine if the pins have pull-high resistors. pe0~pe7 (ht82k75r only) i/o pull-high or wake-up bidirectional 8-bit input/output port. each nibble can be configured as wake-up inputs (both falling and rising edge) by a configuration option. soft- ware instructions determine if the pin is a cmos output or schmitt trigger input. configuration options determine if the pins have pull-high resistors. vss  negative power supply, ground res i  schmitt trigger reset input. active low vdd  positive power supply bat_in i  battery input lx i  dc/dc lx switch vsslx i  dc/dc ground absolute maximum ratings supply voltage ...........................v ss  0.3v to v ss +6.0v storage temperature ............................ 50 cto125 c input voltage..............................v ss  0.3v to v dd +0.3v operating temperature........................... 40 cto85 c i ol total ..............................................................150ma i oh total............................................................ 100ma total power dissipation .....................................500mw note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 4 march 15, 2010
d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v bat bat_in operating voltage  1.8 2.2 3.3 v i dd operating current (crystal osc) 3v no load, f sys = 6mhz  36ma i stb standby current  no load, system halt wdt disable, lvr disable  20
a v il1 input low voltage for i/o (schmitt trigger)  0  0.3v dd v v ih1 input high voltage for i/o (schmitt trigger)  0.7v dd  v dd v v il2 input low voltage (res )  0  0.3v dd v v ih2 input high voltage (res )  0.9v dd  v dd v i ol1 other i/o pins sink current 3v v ol =0.1v dd 4  ma i oh1 other i/o pins source current 3v v oh =0.9v dd 2.5 4.5  ma r ph1 other pins internal pull-high resistance 3v  10 30 50 k a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys system clock 3v  5.7 6 6.3 mhz t rcsys watchdog osc period 3v  71 
s t wdt1 watchdog time-out period with 6-stage prescaler 3v wdts=1  4.57  ms t res external reset low pulse width  1  ms t sst system start-up timer   512  1/f sys t lvr low voltage width to reset  0.25 1 2 ms t wake-up mcu wake-up timer   1ms t configure watchdog time-out period   1024  t rcsys HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 5 march 15, 2010
power-on reset characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions i por operating current 1.8v~ 3.3v  1.0 
a rr vdd v dd rise rate to ensure power-on reset  without 0.1
f between v dd and v ss 0.05  v/ms v por maximum v dd start voltage to ensure power-on reset  without 0.1
f between v dd and v ss ,ta=25c 0.9  1.5 v t por power-on reset low pulse width  without 0.1
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HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 7 march 15, 2010 system architecture a key factor in the high-performance features of the holtek range of microcontrollers is attributed to the inter - nal system architecture. the devices take advantage of the usual features found within risc microcontrollers providing increased speed of operation and enhanced performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction exe - cution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. an 8-bit wide alu is used in practically all operations of the instruction set. it carries out arith - metic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplified by moving data through the accumula - tor and the alu. certain internal registers are imple - mented in the data memory and can be directly or indirectly addressed. the simple addressing methods of these registers along with additional architectural fea - tures ensure that a minimum of external components is required to provide a functional i/o control system with maximum reliability and flexibility. clocking and pipelining the main system clock, derived from either a crys - tal/resonator or rc oscillator is subdivided into four in- ternally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way, one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructions takes place in consecutive in - struction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. for instructions involving branches, such as jump or call instructions, two machine cycles are required to com - plete instruction execution. an extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications program counter during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as jmp or call that demand a jump to a non-consecutive program memory address. it must be noted that only the lower 8 bits, known as the program counter low register, are directly addressable by user. (
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HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 8 march 15, 2010 when executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the program counter. for condi - tional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is dis - carded and a dummy cycle takes its place while the cor - rect instruction is obtained. the lower byte of the program counter, known as the program counter low register or pcl, is available for program control and is a readable and writeable regis - ter. by transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be in - serted. the lower byte of the program counter is fully accessi - ble under program control. manipulating the pcl might cause program branching, so an extra cycle is needed to pre-fetch. further information on the pcl register can be found in the special function register section. stack this is a special part of the memory which is used to save the contents of the program counter only. the stack has 6 levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer, sp, and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the con - tents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, sig - naled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the ac - knowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overflow al - lowing the programmer to use the structure more easily. however, when the stack is full, a call subroutine in - struction can still be executed which will result in a stack overflow. precautions should be taken to avoid such cases which might cause unpredictable program branching. mode program counter bits b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 initial reset 0 00000000000 spi interrupt 0 00000000100 timer/event counter overflow 0 00000001000 external interrupt 0 00000001100 skip program counter + 2 loading pcl pc11 pc10 pc9 pc8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: pc11~pc8: current program counter bits @7~@0: pcl bits #11~#0: instruction code address bits s11~s0: stack register bits      !  
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HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 9 march 15, 2010 arithmetic and logic unit  alu the arithmetic-logic unit or alu is a critical area of the microcontroller that carries out arithmetic and logic op - erations of the instruction set. connected to the main microcontroller data bus, the alu receives related in - struction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. as these alu calculation or oper - ations may result in carry, borrow or other status changes, the status register will be correspondingly up - dated to reflect these changes. the alu supports the following functions:  arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa  logic operations: and, or, xor, andm, orm, xorm, cpl, cpla  rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc  increment and decrement inca, inc, deca, dec  branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti program memory the program memory is the location where the user code or program is stored. the device is supplied with one-time programmable, otp, memory where users can program their application code into the device. by using the appropriate programming tools, otp devices offer users the flexibility to freely develop their applica - tions which may be useful during debug or for products requiring frequent upgrades or program changes. otp devices are also applicable for use in applications that require low or medium volume production runs. structure the program memory has a capacity of 4k  15 bits. the program memory is addressed by the program counter and also contains data, table information and interrupt entries. table data, which can be setup in any location within the program memory, is addressed by separate table pointer registers. special vectors within the program memory, certain locations are re - served for special usage such as reset and interrupts.  location 000h this vector is reserved for use by the device reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execu - tion.  location 004h this vector is used by serial interface. when 8-bits of data have been received or transmitted success-fully from serial interface. the program will jump to this lo - cation and begin execution if the interrupt is enable and the stack is not full.  location 008h this vector is used by the timer/event counter. if a counter overflow occurs, the program will jump to this location and begin execution if the timer interrupt is enabled and the stack is not full.  location 00ch this vector is used by the external interrupt. if the int external input pin on the device receives a high to low transition, the program will jump to this location and begin execution, if the interrupt is enabled and the stack is not full.  table location any location in the program memory can be used as look-up tables. there are three method to read the rom data by two table read instructions: tabrdc and tabrdl , transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to tblh (08h). ( ( ( @  ,         
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   program memory structure instruction table location bits b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 tabrdc[m] pc11 pc10 pc9 pc8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl[m] 1 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0 table location note: pc11~pc8: current program counter bits when tbhp is disabled tbhp register bit3~bit0 when tbhp is enabled @7~@0: table pointer tblp bits
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 10 march 15, 2010 the three methods are shown as follows: the in - structions tabrdc [m] (the current page, one page=256words), where the table location is de - fined by tblp (07h) in the current page. and the configuration option tbhp is disabled (default). the instructions tabrdc [m] , where the table lo - cation is defined by registers tblp (07h) and tbhp (01fh). and the configuration option tbhp is enabled. the instructions tabrdl [m] , where the table lo - cation is defined by register tblp (07h) in the last page (f00h~fffh). only the destination of the lower-order byte in the ta - ble is well-defined, the other bits of the table word are transferred to the lower portion of tblh, and the re - maining 1-bit words are read as 0 . the table higher-order byte register (tblh) is read only. the ta - ble pointer (tblp, tbhp) is a read/write register (07h, 1fh), which indicates the table location. before ac - cessing the table, the location must be placed in the tblp and tbhp (if the configuration option tbhp is disabled, the value in tbhp has no effect). the tblh is read only and cannot be restored. if the main rou - tine and the isr (interrupt service routine) both em - ploy the table read instruction, the contents of the tblh in the main routine are likely to be changed by the table read instruction used in the isr. errors can occur. in other words, using the table read instruction in the main rou- tine and the isr simultaneously should be avoided. however, if the table read instruction has to be applied in both the main routine and the isr, the interrupt should be disabled prior to the table read instruction. it will not be enabled until the tblh has been backed up. all table related instructions require two cycles to complete the operation. these areas may function as normal program memory depending on the require - ments. once tbhp is enabled, the instruction tabrdc [m] reads the rom data as defined by tblp and tbhp value. otherwise, the configuration option tbhp is disabled, the instruction tabrdc [m] reads the rom data as defined by tblp and the current pro - gram counter bits. table program example the following example shows how the table pointer and table data is defined and retrieved from the microcontroller. this example uses raw table data lo - cated in the last page which is stored there using the org statement. the value at this org statement is f00h which refers to the start address of the last page within the 4k program memory of device. the table pointer is setup here to have an initial value of 06h . this will ensure that the first data read from the data ta - ble will be at the program memory address f06h or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the first ad - dress of the present page if the tabrdc [m] instruc - tion is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the tabrdl [m] in- struction is executed.     
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HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 11 march 15, 2010 tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise table pointer - note that this address ; is referenced mov tblp,a ; to the last page or present page : : tabrdl tempreg1 ; transfers value in table referenced by table pointer ; to tempregl ; data at prog. memory address f06h transferred to ; tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrdl tempreg2 ; transfers value in table referenced by table pointer ; to tempreg2 ; data at prog.memory address f05h transferred to ; tempreg2 and tblh ; in this example the data 1ah is transferred to ; tempreg1 and data 0fh to register tempreg2 ; the value 00h will be transferred to the high byte ; register tblh : : org f00h ; sets initial address of last page dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : : because the tblh register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and interrupt service routine use the table read instructions. if using the table read instructions, the interrupt service routines may change the value of tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation.
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 12 march 15, 2010 data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary in - formation is stored. divided into two sections, the first of these is an area of ram where special function registers are located. these registers have fixed locations and are necessary for correct operation of the device. many of these registers can be read from and written to di - rectly under program control, however, some remain protected from user manipulation. the second area of data memory is reserved for general purpose use. all locations within this area are read and write accessible under program control. structure the two sections of data memory, the special purpose and general purpose data memory are located at con - secutive locations. all are implemented in ram and are 8-bit wide. the start address of the data memory for all devices is the address 00h . registers which are com - mon to all microcontrollers, such as acc, pcl, etc., have the same data memory address. general purpose data memory all microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. it is this area of ram memory that is known as general purpose data memory. this area of data memory is fully accessible by the user pro - gram for both read and write operations. by using the set [m].i and clr [m].i instructions, individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the data memory. special purpose data memory this area of data memory is where registers, necessary for the correct operation of the microcontroller, are stored. most of the registers are both readable and writeable but some are protected and are readable only, the details of which are located under the relevant spe - cial function register section. note that for locations that are unused, any read instruction to these addresses will return the value 00h . d

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HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 14 march 15, 2010 special function registers to ensure successful operation of the microcontroller, certain internal registers are implemented in the data memory area. these registers ensure correct operation of internal functions such as timers, interrupts, etc., as well as external functions such as i/o data control. the location of these registers within the data memory be - gins at the address 00h. any unused data memory lo - cations between these special function registers and the point where the general purpose memory begins is re - served and attempting to read data from these locations will return a value of 00h. indirect addressing register  iar0, iar1 the indirect addressing registers, iar0 and iar1, al - though having their locations in normal ram register space, do not actually physically exist as normal regis - ters. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory ad - dressing, where the actual memory address is speci - fied. actions on the iar0 and iar1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corre - sponding memory pointer, mp0 or mp1. acting as a pair, iar0 and mp0 can together only access data from bank 0, while the iar1 and mp1 register pair can ac - cess data from all of the data banks if the data memory is divided into 2 or more banks. as the indirect ad - dressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of 00h and writing to the registers indi - rectly will result in no operation. memory pointer  mp0, mp1 for all devices, two memory pointers, known as mp0 and mp1 are provided. these memory pointers are physically implemented in the data memory and can be manipulated in the same way as normal registers pro - viding a convenient way with which to address and track data. when any operation to the relevant indirect ad - dressing registers is carried out, the actual address that the microcontroller is directed to, is the address speci - fied by the related memory pointer. mp0 can only ac - cess data in bank 0 while mp1 can access all data banks if the data memory is divided into 2 or more banks. data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1; accumulator loaded with first ram address mov mp,a ; setup memory pointer with first ram address loop: clr iar0 ; clear the data at address defined by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: the important point to note here is that in the example shown above, no reference is made to specific data memory ad - dresses.
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 15 march 15, 2010 accumulator  acc the accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. without the accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the data memory resulting in higher programming and timing overheads. data transfer operations usually involve the temporary storage function of the accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register  pcl to provide additional program control functions, the low byte of the program counter is made accessible to pro - grammers by locating it within the special purpose area of the data memory. by manipulating this register, direct jumps to other program locations are easily imple - mented. loading a value directly into this pcl register will cause a jump to the specified program memory lo - cation, however, as the register is only 8-bit wide, only jumps within the current program memory page are per- mitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers  tblp, tblh, tbhp these two special function registers are used to control operation of the look-up table which is stored in the pro- gram memory. tblp is the table pointer and indicates the location where the table data is located. its value must be setup before any table read commands are ex - ecuted. its value can be changed, for example using the inc or dec instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored after a table read data instruction has been executed. note that the lower order table data byte is transferred to a user de - fined location. once tbhp is enabled, the instruction tabrdc [m] reads the rom data as defined by tblp and tbhp value. otherwise, the configuration option tbhp is disabled, the instruction tabrdc [m] reads the rom data as defined by tblp and the current program counter bits. status register  status this 8-bit register contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pdf), and watchdog time-out flag (to). these arithmetic/logical operation and system manage - ment flags are used to record the status and operation of the microcontroller. with the exception of the to and pdf flags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf flag. in addition, opera - tions related to the status register may give different re - sults due to the different instruction operations. the to flag can be affected only by a system power-up, a wdt time-out or by executing the clr wdt or halt in - struction. the pdf flag is affected only by executing the halt or clr wdt instruction or during a system power-up. the z, ov, ac and c flags generally reflect the status of the latest operations.  c is set if an operation results in a carry during an ad- dition operation or if a borrow does not take place dur- ing a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction.  ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nib- ble into the low nibble in subtraction; otherwise ac is cleared.  z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared.  ov is set if an operation results in a carry into the high - est-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared.  pdf is cleared by a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction.  to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out.    (  ' g     
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HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 16 march 15, 2010 in addition, on entering an interrupt sequence or execut - ing a subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status registers are important and if the interrupt rou - tine can change the status register, precautions must be taken to correctly save it. interrupt control registers  intc the microcontroller provides an internal timer/event counter overflow interrupt. by setting various bits within this register using standard bit manipulation instruc - tions, the enable/disable function of each interrupt can be independently controlled. a master interrupt bit within this register, the emi bit, acts like a global enable/dis - able and is used to set all of the interrupt enable bits on or off. this bit is cleared when an interrupt routine is en - tered to disable further interrupt and is set by executing the reti instruction. timer/event counter registers  tmrh, tmrl, tmrc all devices possess a single internal 16-bit count-up timer. an associated register pair known as tmrl/tmrh is the location where the timer 16-bit value is located. this register can also be preloaded with fixed data to allow different time intervals to be setup. an as- sociated control register, known as tmrc, contains the setup information for this timer, which determines in what mode the timer is to be used as well as containing the timer on/off control function. watchdog timer register  wdts the watchdog function in the microcontroller provides an automatic reset function giving the microcontroller a means of protection against spurious jumps to incorrect program memory addresses. to implement this, a timer is provided within the microcontroller which will issue a reset command when its value overflows.to provide variable watchdog timer reset times, the watchdog timer clock source can be divided by various division ra - tios, the value of which is set using the wdts register. by writing directly to this register, the appropriate divi - sion ratio for the watchdog timer clock source can be setup. note that only the lower 3 bits are used to set divi - sion ratios between 1 and 128. input/output ports and control registers within the area of special function registers, the i/o registers and their associated control registers play a prominent role. all i/o ports have correspondingly des - ignated registers known as pa, pb, etc. these labeled i/o registers are mapped to specific addresses within the data memory as shown in the data memory table, which are used to transfer the appropriate output or in - put data on that port. with each i/o port there is an asso - ciated control register known as pac, pbc, etc., also mapped to specific addresses with the data memory. input/output ports holtek microcontrollers offer considerable flexibility on their i/o ports. with the input or output designation of ev - ery pin fully under user program control, pull-high op - tions for all ports and wake-up option for all i/o pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the microcontroller provides 24 or 40 bit bidirectional in - put/output lines labeled with port names known as pa, pb, etc. these i/o ports are mapped to the data mem - ory with addresses as shown in the special purpose data memory table. all of these i/o lines can be used for input and output operations and one line as an input only. for input operation, these ports are non-latching, which means the inputs must be ready at the t2 rising edge of instruction mov a,[m] , where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an exter - nal resistor. to eliminate the need for these external re- sistors, i/o pins, when configured as an input have the capability of being connected to an internal pull-high re- sistor. the pull-high resistors are selectable via configu- ration options and are implemented using weak pmos transistors. the individual pull-high resistor is selected to be connected to each pin on port a by a configuration option. a configuration option can determine if the pull-high resistors are connected to the lower significant four pins or higher significant four pins on each i/o port except port a. port pin wake-up if the halt instruction is executed, the device will enter the power down mode, where the system clock will stop resulting in power being conserved, a feature that is im - portant for battery and other low-power applications. various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port pins from high to low. after a halt instruction forces the microcontroller into entering the power down mode, the processor will remain in a low-power state un - til the logic condition of the selected wake-up pin on the port pin changes from high to low. this function is espe - cially suitable for applications that can be woken up via external switches. all of the i/o pins can be configured to have the capability to wake-up the device by high to low and low to high edges using different configuring ways. it means once the i/o pin is configured to have the
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 17 march 15, 2010 wake-up capability, the device can be woken up by any i/o transition. for more details, refer to the configura - tion option section later. i/o port control registers each i/o port has its own control register known as pac, pbc, etc., to control the input/output configuration. with this control register, each cmos/nmos output or input with or without pull-high resistor structures can be re- configured dynamically under software control. each of the i/o ports is directly mapped to a bit in its associated port control register. pc and pb can be set cmos or nmos output for option. for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 1 . this will then allow the logic state of the input pin to be di - rectly read by instructions. when the corresponding bit of the control register is written as a 0 , the i/o pin will be setup as a cmos/nmos output. if the pin is currently setup as an output, instructions can still be used to read the output register. however, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pin-shared functions the flexibility of the microcontroller range is greatly en - hanced by the use of pins that have more than one func - tion. limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be over - come. for some pins, the chosen function of the multi-function i/o pins is set by configuration options while for others the function is set by application pro - gram control.  external timer clock input the external timer pin tmr is pin-shared with the i/o pin pa2. to configure this pin to operate as timer input, the corresponding control bits in the timer control reg- ister must be correctly set. for applications that do not require an external timer input, this pin can be used as a normal i/o pin. note that if used as a normal i/o pin the timer mode control bits in the timer control register must select the timer mode, which has an internal clock source, to prevent the input pin from interfering with the timer operation.  external interrupt input the external interrupt pin int is pin-shared with the i/o pin pc2. for applications not requiring an external interrupt input, the pin-shared external interrupt pin can be used as a normal i/o pin, however to do this, the external interrupt enable bits in the intc register must be disabled. i/o pin structures the diagrams illustrate the i/o pin internal structures. as the exact logical construction of the i/o pin may differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. programming considerations within the user program, one of the first things to con - sider is port initialisation. after a reset, all of the data and port control register will be set high. this means that all i/o pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high options have been selected. if the control reg - isters, known as pac, pbc, etc., are programmed to setup some pins as outputs, these output pins will have '    e 6     #  1        1 !  $  
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HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 18 march 15, 2010 an initial high output value unless the associated data registers are first programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct value into the port control register or by programming individual bits in the port control reg - ister using the set [m].i and clr [m].i instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must first read in the data on the entire port, modify it to the required new bit values and then re - write this data back to the output ports. all i/o have the additional capability of providing wake-up functions. when the device is in the power down mode, various methods are available to wake the device up. one of these is a high to low and low to high transition of any of the selected wake-up pins. timer/event counters the provision of timers form an important part of any microcontroller giving the designer a means of carrying out time related functions. the device contains an inter - nal 16-bit count-up timer which has three operating modes. the timer can be configured to operate as a general timer, external event counter or as a pulse width measurement device. there are three registers related to the timer/event counter, tmrl, tmrh and tmrc. the tmrl/tmrh register pair are the registers that contains the actual timing value. writing to this register pair places an initial starting value in the timer/event counter preload regis - ter while reading retrieves the contents of the timer/event counter. the tmrc register is a timer/event counter control register, which defines the timer options, and determines how the timer is to be used. the timer clock source can be configured to come from the internal system clock divided by 4 or from an external clock on shared pin pa2/tmr. configuring the timer/event counter input clock source the timer clock source can originate from either the sys - tem clock divided by 4 or from an external clock source. the system clock divided by 4 is used when the timer is in the timer mode or in the pulse width measurement mode. an external clock source is used when the timer is in the event counting mode, the clock source being provided on shared pin pa2/tmr. depending upon the condition of the te bit, each high to low, or low to high transition on the pa2/tmr pin will increment the counter by one. timer registers  tmrh, tmrl the tmrh and tmrl registers are two 8-bit special function register locations within the special purpose data memory where the actual timer value is stored. the value in the timer registers increases by one each time an internal clock pulse is received or an external transition occurs on the pa2/tmr pin. the timer will count from the initial value loaded by the preload regis - ter to the full count value of ffffh at which point the timer overflows and an internal interrupt signal gener - ated. the timer value will then be reset with the initial preload register value and continue counting. for a maximum full range count of 0000h to ffffh the preload registers must first be cleared to 0000h. it should be noted that after power-on the preload regis - ters will be in an unknown condition. note that if the timer/event counter is not running and data is written to its preload registers, this data will be immediately written into the actual counter. however, if the counter is en - abled and counting, any new data written into the preload registers during this period will remain in the preload registers and will only be written into the actual counter the next time an overflow occurs. accessing these registers is carried out in a specific way. it must be noted that when using instructions to preload data into the low byte register, namely tmrl, the data will only be placed in a low byte buffer and not directly into the low byte register. the actual transfer of the data into the low byte register is only carried out when a write to its associated high byte register, namely tmrh, is executed. on the other hand, using instruc- tions to preload data into the high byte timer register will result in the data being directly written to the high byte register. at the same time the data in the low byte buffer will be transferred into its associated low byte register. for this reason, when preloading data into the 16-bit timer registers, the low byte should be written first. it must also be noted that to read the contents of the low byte register, a read to the high byte register must first be executed to latch the contents of the low byte buffer from its associated low byte register. after this has been done, the low byte register can be read in the normal way. note that reading the low byte timer register di - rectly will only result in reading the previously latched contents of the low byte buffer and not the actual con - tents of the low byte timer register. timer control register  tmrc the flexible features of the holtek microcontroller timer/event counters enable them to operate in three different modes, the options of which are determined by the contents of the timer control register tmrc. to - gether with the tmrl and tmrh registers, these three    *  .  -    *  .  - $  
      
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HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 19 march 15, 2010 registers control the full operation of the timer/event counter. before the timer can be used, it is essential that the tmrc register is fully programmed with the right data to ensure its correct operation, a process that is normally carried out during program initialisation. to choose which of the three modes the timer is to oper - ate in, the timer mode, the event counting mode or the pulse width measurement mode, bits tm0 and tm1 must be set to the required logic levels. the timer-on bit ton or bit 4 of the tmrc register provides the basic on/off control of the timer, setting the bit high allows the counter to run, clearing the bit stops the counter. if the timer is in the event count or pulse width measurement mode the active transition edge level type is selected by the logic level of the te or bit 3 of the tmrc register. configuring the timer mode in this mode, the timer can be utilised to measure fixed time intervals, providing an internal interrupt signal each time the counter overflows. to operate in this mode, bits tm1 and tm0 of the tmrc register must be set to 1 and 0 respectively. in this mode, the internal clock is used as the timer clock. the timer-on bit, ton, must be set high to enable the timer to run. each time an internal clock high to low transition occurs, the timer increments by one. when the timer is full and overflows, the timer will be reset to the value already loaded into the preload reg - ister and continue counting. if the timer interrupt is en - abled, an interrupt signal will also be generated. the timer interrupt can be disabled by ensuring that the eti bit in the intc register is cleared to zero.      ) *  & 
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HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 20 march 15, 2010 configuring the event counter mode in this mode, a number of externally changing logic events, occurring on external pin pa2/tmr, can be re - corded by the internal timer. for the timer to operate in the event counting mode, bits tm1 and tm0 of the tmrc register must be set to 0 and 1 respectively. the timer-on bit, ton must be set high to enable the timer to count. with te low, the counter will increment each time the pa2/tmr pin receives a low to high transition. if the te bit is high, the counter will increment each time pa2/tmr receives a high to low transition. as in the case of the other two modes, when the counter is full and overflows, the timer will be reset to the value al - ready loaded into the preload register and continue counting. if the timer interrupt is enabled, an interrupt signal will also be generated. the timer interrupt can be disabled by ensuring that the eti bit in the intc register is cleared to zero. to ensure that the external pin pa2/tmr is configured to operate as an event counter input pin, two things have to happen. the first is to en - sure that the tm0 and tm1 bits place the timer/event counter in the event counting mode, the second is to en - sure that the port control register configures the pin as an input. in the event counting mode, the timer/event counter will continue to record externally changing logic events on the timer input pin, even if the microcontroller is in the power down mode. configuring the pulse width measurement mode in this mode, the width of external pulses applied to the pin-shared external pin pa2/tmr can be measured. in the pulse width measurement mode, the timer clock source is supplied by the internal clock. for the timer to operate in this mode, bits tm0 and tm1 must both be set high. if the te bit is low, once a high to low transition has been received on the pa2/tmr pin, the timer will start counting until the pa2/tmr pin returns to its origi - nal high level. at this point the ton bit will be automati - cally reset to zero and the timer will stop counting. if the te bit is high, the timer will begin counting once a low to high transition has been received on the pa2/tmr pin and stop counting when the pa2/tmr pin returns to its original low level. as before, the ton bit will be automat - ically reset to zero and the timer will stop counting. it is important to note that in the pulse width measurement mode, the ton bit is automatically reset to zero when the external control signal on the external timer pin re - turns to its original level, whereas in the other two modes the ton bit can only be reset to zero under pro - gram control. the residual value in the timer, which can now be read by the program, therefore represents the length of the pulse received on pin pa2/tmr. as the ton bit has now been reset any further transitions on the pa2/tmr pin will be ignored. not until the ton bit is again set high by the program can the timer begin fur - ther pulse width measurements. in this way single shot pulse measurements can be easily made. it should be noted that in this mode the counter is controlled by logi - cal transitions on the pa2/tmr pin and not by the logic level. as in the case of the other two modes, when the counter is full and overflows, the timer will be reset to the value already loaded into the preload register. if the timer in- terrupt is enabled, an interrupt signal will also be gener- ated. to ensure that the external pin pa2/tmr is configured to operate as a pulse width measuring input pin, two things have to happen. the first is to ensure that the tm0 and tm1 bits place the timer/event counter in the pulse width measuring mode, the second is to en- sure that the port control register configures the pin as an input.  
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HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 21 march 15, 2010 i/o interfacing the timer/event counter, when configured to run in the event counter or pulse width measurement mode, re - quire the use of the external pa2 pin for correct opera - tion. as this pin is a shared pin it must be configured correctly to ensure it is setup for use as a timer/event counter input and not as a normal i/o pin. this is imple - mented by ensuring that the mode select bits in the timer/event counter control register, select either the event counter or pulse width measurement mode. addi - tionally the port control register pac bit 2 must be set high to ensure that the pin is setup as an input. any pull-high resistor configuration option on this pin will re - main valid even if the pin is used as a timer/event counter input. programming considerations when configured to run in the timer mode, the internal system clock is used as the timer clock source and is therefore synchronised with the overall operation of the microcontroller. in this mode when the appropriate timer register is full, the microcontroller will generate an inter - nal interrupt signal directing the program flow to the re - spective internal interrupt vector. for the pulse width measurement mode, the internal system clock is also used as the timer clock source but the timer will only run when the correct logic condition appears on the external timer input pin. as this is an external event and not syn- chronised with the internal timer clock, the microcontroller will only see this external event when the next timer clock pulse arrives. as a result, there may be small differences in measured values requiring pro- grammers to take this into account during programming. the same applies if the timer is configured to be in the event counting mode, which again is an external event and not synchronised with the internal system or timer clock. when the timer/event counter is read, or if data is writ - ten to the preload register, the clock is inhibited to avoid errors, however as this may result in a counting error, this should be taken into account by the programmer. care must be taken to ensure that the timers are prop - erly initialised before using them for the first time. the associated timer interrupt enable bits in the interrupt control register must be properly set otherwise the inter - nal interrupt associated with the timer will remain inac - tive. the edge select, timer mode and clock source control bits in timer control register must also be cor - rectly set to ensure the timer is properly configured for the required application. it is also important to ensure that an initial value is first loaded into the timer registers before the timer is switched on; this is because after power-on the initial values of the timer registers are un - known. after the timer has been initialised the timer can be turned on and off by controlling the enable bit in the timer control register. note that setting the timer enable bit high to turn the timer on, should only be executed af - ter the timer mode bits have been properly setup. set - ting the timer enable bit high together with a mode bit modification, may lead to improper timer operation if ex - ecuted as a single timer control register byte write in - struction. when the timer/event counter overflows, its corre- sponding interrupt request flag in the interrupt control register will be set. if the timer interrupt is enabled this will in turn generate an interrupt signal. but the timer for internal clock overflow can t wake up the mcu if mcu is in a power down condition.
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 22 march 15, 2010 timer program example this program example shows how the timer/event counter registers are setup, along with how the interrupts are en - abled and managed. note how the timer/event counter is turned on, by setting bit 4 of the timer control register. the timer/event counter can be turned off in a similar way by clearing the same bit. this example program sets the timer/event counter to be in the timer mode, which uses the internal system clock as the clock source. org 04h reti org 08h ; timer/event counter interrupt vector jmp tmrint ; jump here when timer overflows : org 20h ; main program ;internal timer/event counter interrupt routine tmrint: : ; timer/event counter main program placed here : reti : : begin: ;setup timer registers mov a,09bh ; setup timer low register mov tmrl,a; ; load low register first mov a, 0aah ; setup timer high register mov tmrh,a mov a,080h ; setup timer control register mov tmrc,a ; timer mode is used ; setup interrupt register mov a,005h ; enable master interrupt and timer interrupt mov intc,a set tmrc.4 ; start timer/event counter - note mode bits must be previously setup interrupts interrupts are an important part of any microcontroller system. when an internal function such as a timer/event counter overflow, their corresponding in- terrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. these devices contain sev - eral interrupts generated by internal interrupts events and external interrupt. interrupt register overall interrupt control, which means interrupt enabling and request flag setting, is controlled by a single inter - rupt control register, which is located in the data mem - ory. by controlling the appropriate enable bits in this register the interrupt can be enabled or disabled. also when an interrupt occurs, the request flag will be set by the microcontroller. the global enable bit if cleared to zero will disable all interrupts. interrupt operation a timer/event counter overflow, will generate an inter - rupt request by setting its corresponding request flag, if its interrupt enable bit is set. when this happens, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the correspond- ing interrupt vector. the microcontroller will then fetch its next instruction from this interrupt vector. the instruc- tion at this vector will usually be a jmp statement which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated with a reti statement, which retrieves the original program counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. once an interrupt subroutine is serviced, other inter - rupts will be blocked, as the emi bit will be cleared auto - matically. this will prevent any further interrupt nesting from occurring. however, if other interrupt requests oc - cur during this interval, although the interrupt will not be immediately serviced, the request flag will still be re - corded. if an interrupt requires immediate servicing while the program is already in another interrupt service routine, the emi bit should be set after entering the rou - tine, to allow interrupt nesting. if the stack is full, the in - terrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full.
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 23 march 15, 2010 timer/event counter interrupt for a timer/event counter interrupt to occur, the global interrupt enable bit, emi, and its corresponding timer in - terrupt enable bit, eti, must first be set. an actual timer/event counter interrupt will take place when the timer/event counter request flag, tf, is set, a situation that will occur when the timer/event counter overflows. when the interrupt is enabled, the stack is not full and a timer/event counter overflow occurs, a subroutine call to the timer interrupt vector at location 08h, will take place. when the interrupt is serviced, the timer interrupt request flag, tf, will be automatically reset and the emi bit will be automatically cleared to disable other inter - rupts. programming considerations by disabling the interrupt enable bit, the requested inter - rupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt control register until the corre - sponding interrupt is serviced or until the request flag is cleared by a software instruction. it is recommended that programs do not use the call subroutine instruction within the interrupt subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. if only one stack is left and the interrupt is not well con - trolled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. all of these interrupts have the capability of waking up the processor when in the power down mode. only the program counter is pushed onto the stack. if the contents of the accumulator or status register are al - tered by the interrupt service program, which may cor - rupt the desired control sequence, then the contents should be saved in advance.  !        # #   #

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HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 24 march 15, 2010 reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is first applied to the microcontroller. in this case, internal circuitry will ensure that the microcontroller, af - ter a short delay, will be in a well defined state and ready to execute the first program instruction. after this power-on reset, certain important internal registers will be set to defined states before the program com - mences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. in addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. one example of this is where after power has been applied and the microcontroller is already running, the res line is force - fully pulled low. in such a case, known as a normal oper - ation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. another type of reset is when the watchdog timer overflows and resets the microcontroller. all types of re- set operations result in different register conditions be- ing setup. another reset exists in the form of a low voltage reset, lvr, where a full reset, similar to the res reset is imple- mented in situations where the power supply voltage falls below a certain threshold. reset functions there are five ways in which a microcontroller reset can occur, through events occurring both internally and ex - ternally:  power-on reset the most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. as well as ensuring that the program memory begins execution from the first memory ad - dress, a power-on reset also ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. although the microcontroller has an internal rc reset function, if the vdd power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. for this reason it is recom - mended that an external rc network is connected to the res pin, whose additional time delay will ensure that the res pin remains low for an extended period to allow the power supply to stabilise. during this time delay, normal operation of the microcontroller will be inhibited. after the res line reaches a certain voltage value, the reset delay time t rstd is invoked to provide an extra delay time after which the microcontroller will begin normal operation. the abbreviation sst in the figures stands for system start-up timer. for most applications a resistor connected between vdd and the res pin and a capacitor connected be - tween vss and the res pin will provide a suitable ex - ternal reset circuit. any wiring connected to the res pin should be kept as short as possible to minimise any stray noise interference. for applications that operate within an environment where more noise is present the enhanced reset cir- cuit shown is recommended. more information regarding external reset circuits is located in application note ha0075e on the holtek website.  res pin reset this type of reset occurs when the microcontroller is already running and the res pin is forcefully pulled low by external hardware such as an external switch. in this case as in the case of other reset, the program counter will reset to zero and program execution initi - ated from this point.  ) '      
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HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 25 march 15, 2010  low voltage reset  lvr the microcontroller contains a low voltage reset cir - cuit in order to monitor the supply voltage of the de - vice. the lvr function is selected via a configuration option. if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the battery, the lvr will automatically reset the device internally. for a valid lvr signal, a low sup - ply voltage, i.e., a voltage in the range between 0.9v~v lvr must exist for a time greater than that spec - ified by t lvr in the a.c. characteristics. if the low sup - ply voltage state does not exceed this value, the lvr will ignore the low supply voltage and will not perform a reset function. the actual v lvr value can be se - lected via configuration options.  watchdog time-out reset during normal operation the watchdog time-out reset during normal opera - tion is the same as a hardware res pin reset except that the watchdog time-out flag to will be set to 1 .  watchdog time-out reset during power down the watchdog time-out reset during power down is a little different from other kinds of reset. most of the conditions remain unchanged except that the pro - gram counter and the stack pointer will be cleared to 0 and the to flag will be set to 1 . refer to the a.c. characteristics for t sst details. reset initial conditions the different types of reset described affect the reset flags in different ways. these flags, known as pdf and to are located in the status register and are controlled by various microcontroller operations, such as the power down function or watchdog timer. the reset flags are shown in the table: to pdf reset conditions 0 0 res reset during power-on 0 1 res wake-up halt u u res or lvr reset during normal operation 1 u wdt time-out reset during normal operation 1 1 wdt time-out reset during power down note: u stands for unchanged the following table indicates the way in which the vari - ous components of the microcontroller are affected after a power-on reset occurs. item condition after reset program counter reset to zero interrupts all interrupts will be disabled wdt clear after reset, wdt begins counting timer/event counter timer counter will be turned off input/output ports i/o ports will be setup as inputs stack pointer stack pointer will point to the top of the stack 5 '     
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HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 26 march 15, 2010 the different kinds of resets all affect the internal registers of the microcontroller in different ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. register reset (power-on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* pcl 000h 000h 000h 000h 000h acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu status --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu intc -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu tmrl xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmrh xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmrc 00-0 1---- 00-0 1---- 00-0 1---- 00-0 1---- uu-u u--- pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pcc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pd ** 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pdc ** 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pe ** 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pec ** 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu wdts ---- -111 ---- -111 ---- -111 ---- -111 ---- -uuu mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ctlr 0100 0x00 0100 0x00 0100 0x00 0100 0x00 uuuu uxuu ptr 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tbhp ----- 0000 ----- 0000 ----- 0000 ----- 0000 0000 uuuu spir 0000 0000 0000 0000 0000 0000 0000 0000 0000 uuuu sbcr 0110 0000 0110 0000 0110 0000 0110 0000 uuuu uuuu sbdr xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu note: ** for the ht82k75r only - not implemented u means unchanged x means unknown
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 27 march 15, 2010 oscillator the clock source for these devices is provided by an in - tegrated oscillator requiring no external components. this oscillator has one fixed frequencies of 6mhz. watchdog timer oscillator the wdt oscillator is a fully self-contained free running on-chip rc oscillator with a typical period of 71
sat3v requiring no external components. when the device en - ters the power down mode, the system clock will stop running but the wdt oscillator continues to free-run and to keep the watchdog active. however, to preserve power in certain applications the wdt oscillator can be disabled via a configuration option. power down mode and wake-up power down mode all of the holtek microcontrollers have the ability to enter a power down mode. when the device enters this mode, the normal operating current, will be reduced to an extremely low standby current level. this occurs be - cause when the device enters the power down mode, the system oscillator is stopped which reduces the power consumption to extremely low levels, however, as the device maintains its present internal condition, it can be woken up at a later stage and continue running, without requiring a full reset. this feature is extremely important in application areas where the microcontroller must have its power supply constantly maintained to keep the device in a known condition but where the power supply capacity is limited such as in battery appli- cations. entering the power down mode there is only one way for the device to enter the power down mode and that is to execute the halt instruc - tion in the application program. when this instruction is executed, the following will occur:  the system oscillator will stop running and the appli - cation program will stop at the halt instruction.  the data memory contents and registers will maintain their present condition.  the wdt will be cleared and resume counting if the wdt function is enabled.  the i/o ports will maintain their present condition.  in the status register, the power down flag, will be set and the watchdog time-out flag, to, will be cleared. standby current considerations as the main reason for entering the power down mode is to keep the current consumption of the microcontroller to as low a value as possible, perhaps only in the order of several micro-amps, there are other considerations which must also be taken into account by the circuit de - signer if the power consumption is to be minimised. special attention must be made to the i/o pins on the device. all high-impedance input pins must be con - nected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or con - nected only to external circuits that do not draw current, such as other cmos inputs. if the configuration option has enabled the watchdog timer internal oscillator, then the watchdog timer will continue to run when in the power down mode and will thus consume some power. wake-up after the system enters the power down mode, it can be woken up from one of various sources listed as follows:  an external reset  an external falling or rising edge on any of the i/o pins  a system interrupt  a wdt overflow (if the contents of the ptr are zeros)  a ptr overflow occurs (if the contents of the ptr are not equal to zeros) if the system is woken up by an external reset, the de- vice will experience a full system reset, however, if the device is woken up by a wdt overflow, a watchdog timer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the ac- tual source of the wake-up can be determined by exam- ining the to and pdf flags. the pdf flag is cleared by a system power-up or executing the clear watchdog timer instructions and is set when executing the halt instruction. the to flag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other flags remain in their original status. note that the wdt time-out will not occur if the contents of the period timer register (ptr) are not equal to zeros. each pin on port a or any nibble on other ports can be setup via configuration options to permit a negative or positive transition on the pin to wake-up the system. when a port pin wake-up occurs, the program will re - sume execution at the instruction following the halt instruction. if the system is woken up by an interrupt, then two possi - ble situations may occur. the first is where the interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the halt instruction. in this situa - tion, the interrupt will not be immediately serviced, but will rather be serviced later when the related interrupt is
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 28 march 15, 2010 finally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular inter - rupt response takes place. if an interrupt request flag is set to 1 before entering the power down mode, the wake-up function of the related interrupt will be disabled. no matter what the source of the wake-up event is, once a wake-up situation occurs, a time period equal to 512 system clock periods will be required before normal sys - tem operation resumes. however, if the wake-up has originated due to an interrupt, the actual interrupt sub - routine execution will be delayed by additional one or more cycles. if the wake-up results in the execution of the next instruction following the halt instruction, this will be executed immediately after the 512 system clock period delay has ended. watchdog timer the watchdog timer is provided to prevent program malfunctions or sequences from jumping to unknown lo - cations, due to certain uncontrollable external events such as electrical noise. it operates by providing a de - vice reset when the wdt counter overflows. the wdt clock is supplied by its own internal dedicated internal wdt oscillator. note that if the wdt configuration op - tion has been disabled, then any instruction relating to its operation will result in no operation. the wdt function is selected by a configuration option. there is also an internal register associated with the wdt named wdts to disable the watchdog timer function and select various wdt time-out periods in the device. the clock source of the wdt comes from the in- ternal wdt oscillator and its clock period may vary with vdd, temperature and process variation. the wdt clock is further divided by an internal 6-stage counter followed by a 7-stage prescaler to obtain longer wdt time-out period selected by the wdt prescaler rate se - lection bits, ws2~ws0, in the associated wdt register known as wdts. there is only one instruction to clear the watchdog timer known as clr wdt . as the instruction clr wdt is executed, all contents of the 6-stage counter and 7-stage prescaler will be clear. it makes the wdt time-out period more accurate relatively. under normal program operation, a wdt time-out will initialise a device reset and set the status bit to. how - ever, if the system is in the power down mode, when a wdt time-out occurs, the to bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the wdt. the first is an external hardware reset, which means a low level on the res pin, the second is using the watchdog software instruc - tions and the third is via a halt instruction. although the wdt overflow is a source to wake up the mcu from the power down mode, there are some limi - tations on the conditions at which the wdt overflow oc- curs. if the wdt function is enabled and the ptr contents are equal to zeros, the wdt overflow will occur to wake up the mcu from the power down mode. if the ptr contents are not equal to zeros, the wdt overflow will not occur in power down mode even if the wdt function has been enabled.        !  
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HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 29 march 15, 2010 bit no. func. name r/w description 0 cnt_wk r 0: mcu wakeup not by period counter 1: mcu wakeup by period counter overflow (read only) 1 dc_ctrl r/w this bit is used to decide whether the dc block is in operation 0: enable dc_dc output (default) 1: disable dc_dc output 2 2.2 low battery r flag for 2.2v battery low signal coming from dc/dc block (error 5%) 0: battery voltage > 2.2 or 2.0v 1: battery voltage  2.2 or 2.0 v 3 4 clock_div r/w 00: clk/1=6mhz (default) 01: clk/2=3mhz 10: clk/4=1.5mhz 11: clk/4=1.5mhz 5 6 7 lvd_set r/w lvd detect voltage select 000: 1.8v 001: 2.0v 010: 2.2v (default) 011: 2.5v 100: 2.8v control register ctlr period timer register  ptr this register is used to define the period of the timer which always counts in the power down mode. once the timer is reached, the mcu will be woken-up by period timer register overflow. once the mcu is woken-up by the period timer, the cnt_wk bit of the wake-up register is set to 1 . bit no. function name r/w description 0~7 period timer r/w the period timer is the time interval generator with one second as a unit. if the bits [7:0] are equal to 00h, the mcu will be woken up by one of the wake-up source mentioned in wake-up section except the ptr overflow event. if the bits [7:0] are not equal to 00h, the mcu will be woken up from the power down mode by the following events except wdt overflow event:  i/o port wake-up  int wake-up  reset  the period timer is reached to the values specified by the ptr. period timer register  ptr $ * . / 
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HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 30 march 15, 2010 dc-to-dc converter (dc/dc) section this circuit is used to generate a stable 2.8v or 3.0v or 3.3v (error  5%) power voltage for whole ic and output to the irpt. the clock of dc/dc is 140khz. also it can detect the battery voltage. if the battery voltage drops to 2.2v or 2.0v determined by a configuration option (er - ror 5%), the dc/dc circuit will output a low voltage de - tect signal lvd (2.2v/2.0v low battery flag stored in as - sociated flag bit of the control register ctlr.2) to mcu. also there is a low voltage reset (lvr) circuit to check the dc/dc output voltage. when the dc/dc out - put voltage drops to 2.4v, the mcu will be reset. the lvr function is controlled by a configuration together with a software control bit named dc_ctrl in the control register ctlr. to enable the lvr function, the configu - ration option of lvr function has to be enabled and the control bit dc_ctrl must be set to 0 to enable the dc/dc circuit. if the configuration option is selected to disable the lvr function or the dc_ctrl bit is set to 1 to disable the dc/dc circuit, then the lvr function will be dis - abled. if the lvr function is enabled by appropriate set - ting of the configuration option and software control bit as mentioned above, then the lvr still works even if the mcu enters into the power down mode. it is recom - mended that the lvr function is enabled when the mcu is in the power down mode. when the dc/dc output voltage drops to 2.2v, the dc/dc can still work properly and is capable of output - ting driving current with 100ma typically. as the voltage of the battery-in pin drops to 1.8v, the dc/dc still has the capability of outputting current with 40ma at least. the dc/dc output signal 1.8v/2.0v/2.2v/2.5v/2.8v lvd is connected to the associated flag in control reg - ister (i.e. bit 2 in ctlr). test_dc is the internal test pin of the dc_dc.     c   % '  #   
 

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HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 31 march 15, 2010 spi serial interface the device includes one spi serial interfaces. the spi interface is a full duplex serial data link, originally de - signed by motorola, which allows multiple devices con - nected to the same spi bus to communicate with each other. the devices communicate using a master/slave technique where only the single master device can initi - ate a data transfer. a simple four line signal bus is used for all communication. spi interface communication four lines are used for each function. these are, sdi - serial data input, sdo - serial data output, sck - se - rial clock and scs - slave select. note that the condi - tion of the slave select line is conditioned by the csen bit in the sbcr control register. if the csen bit is high then the scs line is active while if the bit is low then the scs line will be i/o mode. the accompanying timing di - agram depicts the basic timing protocol of the spi bus. spi registers there are three registers for control of the spi interface. these are the sbcr register which is the control regis - ter and the sbdr which is the data register and spir register which is the spi mode control register. the sbcr register is used to setup the required setup pa- rameters for the spi bus and also used to store associ- ated operating flags, while the sbdr register is used for data storage. the spir register is used to select spi mode, clock po - larity edge selection and spi enable or disable selec - tion. after power on, the contents of the sbdr register will be in an unknown condition while the sbcr register will default to the condition below: cks m1 m0 sben mls csen wcol trf 01100000 note that data written to the sbdr register will only be written to the txrx buffer, whereas data read from the sbdr register will actual be read from the register. spi bus enable/disable to enable the bus, the sben bit should be set high, then wait for data to be written to the sbdr (txrx buffer) register. for the master mode, after data has been written to the sbdr (txrx buffer) register then transmission or reception will start automatically. when all the data has been transferred, the trf bit should be set. for the slave mode, when clock pulses are re - ceived on sck, data in the txrx buffer will be shifted out or data on sdi will be shifted in. to disable the spi bus sck, sdi, sdo, scs should be i/o mode. bit no. label r/w function 0 spi_cpol r/w 0: clock polarity falling (default falling) 1: clock polarity rising 1 spi_mode r/w 0: spi output the data in the rising edge(polarity=1) or falling edge (polarity=0); spi read data in the in the falling edge(polarity=1) or rising edge (polarity=0); (default) 1: spi first output the data immediately after the spi is enable. and spi output the data in the falling edge(polarity=1) or rising edge (polarity=0); spi read data in the in the rising edge(polarity=1) or falling edge (polarity=0) 2 spi_csen r/w 0: spi_csen disable, scs define as gpio (default disable) 1: spi_csen enable , this bit is used to enable/disable software csen function 3 spi_en r/w this bit control the shared pin (scs , sdi, sdo and sck) is spi or gpio mode 0: i/o mode (default) 1: spi mode 7~4 reserved bit r/w always 0 spir register
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HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 33 march 15, 2010 spi operation all communication is carried out using the 4-line inter - face for both master or slave mode. the timing diagram shows the basic operation of the bus. the csen bit in the sbcr register controls the scs line of the spi interface. setting this bit high, will enable the spi interface by allowing the scs line to be active, which can then be used to control the spi inteface. if the csen bit is low, the scs line will be in a floating condi - tion and can therefore not be used for control of the spi interface. the sben bit in the sbcr register must also be high which will place the sdi line in a floating condi - tion and the sdo line high. if in the master mode the sck line will be either high or low depending upon the clock polarity control bit in spir register. if in the slave mode the sck line will be in a floating condition. if sben is low then the bus will be disabled and scs , sdi, sdo and sck will all be i/o mode. in the master mode, the master will always generate the clock signal. the clock and data transmission will be ini - tiated after data has been written to the sbdr register. in the slave mode, the clock signal will be received from an external master device for both data transmission or reception. the following sequences show the order to be followed for data transfer in both master and slave mode:  master mode step 1. select the clock source using the cks bit in the sbcr control register step 2. setup the m0 and m1 bits in the sbcr control register to select the master mode and the required baud rate. values of 00, 01 or 10 can be selected. step 3. setup the csen bit and setup the mls bit to choose if the data is msb or lsb first, this must be same as the slave device. step 4. setup the sben bit in the sbcr control register to enable the spi interface. step 5. for write operations: write the data to the sbdr register, which will actually place the data into the txrx buffer. then use the sck and scs lines to output the data. goto to step 6.for read operations: the data transferred in on the sdi line will be stored in the txrx buffer until all the data has been received at which point it will be latched into the sbdr register. step 6. check the wcol bit, if set high then a collision error has occurred so return to step5. if equal to zero then go to the following step. step 7. check the trf bit or wait for an spi serial bus interrupt. step 8. read data from the sbdr register. step 9. clear trf. step10. goto step 5.  slave mode: step 1. the cks bit has a don t care value in the slave mode. step 2. setup the m0 and m1 bits to 11 to select the slave mode. the cks bit is don t care. step 3. setup the csen bit and setup the mls bit to choose if the data is msb or lsb first, this must be same as the master device. step 4. setup the sben bit in the sbcr control register to enable the spi interface. step 5. for write operations: write data to the sbdr register, which will actually place the data into the txrx register, then wait for the master clock and scs signal. after this goto step 6. for read operations: the data transferred in on the sdi line will be stored in the txrx buffer until all the data has been received at which point it will be latched into the sbdr register. step 6. check the wcol bit, if set high then a collision error has occurred so return to step5. if equal to zero then goto the following step. step 7. check the trf bit or wait for an spi serial bus interrupt. step 8. read data from the sbdr register. step 9. clear trf step10. step 5
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 34 march 15, 2010 spi configuration options and status control one option is to enable the operation of the wcol, write collision bit, in the sbcr register. some control in spir register. the spi_cpol select the clock polarity of the sck line . the spi_mode select spi data output mode. spi include four pins , can share i/o mode status . the status control combine with four bits for spir and sbcr regis - ter. include spi_csen , spi_en for spir register and csen ,sben for sbcr register. spir(22h) sbcr(23h) i/o status note spi_en spi_csen sben csen spi scs 0 x x x i/o mode i/o mode 1 x 0 x i/o mode i/o mode 1 0 1 x spi mode i/o mode scs not floating 1 1 1 0 spi mode i/o mode scs not floating 1 1 1 1 spi mode scs mode the spi enable, scs , sdi, sdo, sck the internal pull-high function is invalid. note: x: don t care error detection the wcol bit in the sbcr register is provided to indi - cate errors during data transfer. the bit is set by the se - rial interface but must be cleared by the application program. this bit indicates a data collision has occurred which happens if a write to the sbdr register takes place during a data transfer operation and will prevent the write operation from continuing. the bit will be set high by the serial interface but has to be cleared by the user application program. the overall function of the wcol bit can be disabled or enabled by a configuration option. programming considerations when the device is placed into the power down mode note that data reception and transmission will continue. the trf bit is used to generate an interrupt when the data has been transferred or received. 0 +
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configuration options no. options 1 pa0~7 pull-high by bit: pull-high or non-pull-high 2 pa wake-up by bit, :wake-up or non-wake-up 3 pb pull-high by nibble : pull-high or non-pull-high 4 pc pull-high by nibble : pull-high or non-pull-high 5 spi_wcol enable/disable (default) 6 output slew enable 100ns or 200ns 7 tbhp function (enable /disable) 8 dc_dc output option:2.8v,3.0v,3.3v 9 lvr enable/disable (default disable) 10 wdt clock source : enable, disable for normal mode 11 pb wake-up by bit, wake-up or non-wake-up 12 pc wake-up by bit, wake-up or non-wake-up 13 pc output type cmos/nmos 14 pb0 output type cmos/nmos 15 pd pull-high by nibble: pull-high or non-pull-high (*) 16 pe pull-high by nibble: pull-high or non-pull-high (*) 17 pd wake-up by nibble: wake-up or non-wake-up (*) 18 pe wake-up by nibble: wake-up or non-wake-up (*) note: for ht82k75r, there are additional configuration options as the asterisk marks shown. HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 37 march 15, 2010
application circuits HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 38 march 15, 2010 *  * + *  * , * - * . * * *  * /  0    +    ,  * . - ,  +  0  /    *  .  -        1 , 1  1 +  /    *      .  -  ,    +  ) 5 6 ' '   / 7   ( '   / 7   (  / /   - +  ( 1 - 1 . 1 * 1  1 / +  , - . * ' '   1   4  3 -  - + -  - , - - - . - * -  - / . 0 .  . + .  . , . - . . . * .  . / * 0 *  * + *  * ,  * . - ,  +  0  /    *  .  -  ,    +    0 * / *  * * * . * -        '   3 1   4  3 ' 5 6 5 6 1 + 1  1 , 1 - 1 . 1 * 1  1 / )  ) * ) . ) - ) , )  ) + /  * . 3 '  )  /    *      .  -  ,    +  /    *  .  -  ,    + 1 / +  , - '   / 7   (    ( '   / 7   (  / /   - +  (
eeprom data memory block diagram HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 39 march 15, 2010 eeprom memory features  1k capacity organized into 128 8  accessible using two i 2 c lines  device address: 0  1010000b followed with a read/write operation selection bit  device operations:  byte write operation  current address read operation  random address read operation  sequential address read operation eeprom memory overview an area of eeprom, which stands for electrically eras - able programmable read only memory, is contained within the device. this type of memory is non-volatile with data retention even after power is removed and is useful for storing information such as product identifica - tion numbers, calibration values, user data, system setup data, etc.        # 5     
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pin assignment eeprom memory pin description pin name type description vddp  external positive power supply for eeprom memory vssp  external negative power supply for eeprom memory, ground sda i/o internal serial data input/output signal internal connected with mcu i/o line. scl i serial clock input signal internal connected with mcu i/o line. nc  implies that the pin is not connected and can therefore not be used. note: the pin descriptions for all external pins with the exception of the eeprom vddp and vssp pins are described in the preceding mcu section. vddp and vssp should be externally connected to the mcu power supply named vdd and vss respectively. the sda and scl lines here are internal connected to the mcu i/o pins pc0 and pc1 respectively for these devices. HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 40 march 15, 2010 -  - + -  - , - - - . - * -  - / . 0 .  . + .  . , . - . . . * .  . / * 0 *  * + *  * ,  * . - ,  +  0  /    *  .  -  ,    +    0 * / *  * * * . * -        )  
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absolute maximum ratings supply voltage ..........................v ss  0.3v to v ss +6.0v storage temperature ............................ 50 cto125 c input voltage .............................v ss  0.3v to v cc +0.3v operating temperature........................... 40 cto85 c note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. d.c. characteristics ta = 40c~85c symbol parameter test conditions min. typ. max. unit v cc conditions i cc1 * operating current 3v read at 100khz  1ma i cc2 * operating current 3v write at 100khz  3ma i stb* standby current 3v v in =0 or v cc  3
a note: * the operating current icc1 and icc2 listed here are the additional currents consumed when the eeprom memory operates in read operation and write operation respectively. if the eeprom is operating, the icc1 or icc2 should be added to calculate the relevant operating current of the device for different conditions. to calculate the standby current for the whole device, the standby current shown above should also be taken into account. a.c. characteristics ta = 40c~85c symbol parameter remark standard mode* unit min. max. f sk scl clock frequency  100 khz t high clock high time  4000  ns t low clock low time  4700  ns t r sda and scl rise time note  1000 ns t f sda and scl fall time note  300 ns t hd:sta start condition hold time after this period the first clock pulse is generated 4000  ns t su:sta start condition setup time only relevant for repeated start condition 4000  ns t hd:dat data input hold time  0  ns t su:dat data input setup time  200  ns t su:sto stop condition setup time  4000  ns t aa output valid from clock  3500 ns t buf bus free time time in which the bus must be free before a new transmission can start 4700  ns t sp input filter time constant (sda and scl pins) noise suppression time  100 ns t wr write cycle time  5ms note: these parameters are periodically sampled but not 100% tested * the standard mode means v cc =2.2v to 3.6v for relative timing, refer to timing diagrams HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 41 march 15, 2010
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 42 march 15, 2010 eeprom data memory functional description the embedded eeprom data memory is an i2c type device and therefore operates using a two wire serial bus. it has a capacity is 1k organized into a structure of 128 8-bit words and contains the information or data im - portant for user. eeprom data memory internal connection in addition to the pins described above there are other mcu to eeprom data memory interconnecting lines that are described in the above eeprom pin descrip - tion table. note that the sda and scl lines are internal connected to the mcu i/o pins respectively and are not bonded to external pins. accessing the eeprom data memory the two i2c lines are the serial clock line, scl, and the serial data line sda. the sda and scl pins are inter - nal connected to the host mcu i/o pins. normal i/o con - trol software instructions are used to control the reading and writing operations on the eeprom data memory.  serial data - sda the sda line is the bidirectional eeprom serial data line which is controlled by the host mcu i/o pin. the host mcu should configure this i/o pin as input or out - put dynamically opposite to the data direction of the eeprom. the sda line is an internal line and not connected to an output pin.  serial clock - scl the scl line is the eeprom serial clock input line which is controlled by the host mcu i/o pin. the host mcu should configure this i/o pin connected to the scl line as output pin. the scl line is an internal line and not connected to an output pin. the scl input clocks data into the eeprom on its positive edge and clocks data out of the eeprom on its negative edge.  clock and data transition data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition.  start condition a high-to-low transition of sda with scl high will be interpreted as a start condition which must precede any other command - refer to the start and stop defi - nition timing diagram.  stop condition a low-to-high transition of sda with scl high will be interpreted as a stop condition. after a read sequence the stop command will place the eeprom in a standby power mode - refer to start and stop defini - tion timing diagram.  acknowledge all addresses and data words are serially transmitted to and from the eeprom in 8-bit words. the eeprom sends a zero to acknowledge that it has re- ceived each word. this happens during the ninth clock cycle. device addressing all eeprom devices require an 8-bit device address word following a start condition to enable the eeprom for read or write operations. the device address word consist of a mandatory one, zero sequence for the first four most significant bits. refer to the diagram showing the device address. this is common to all the eeprom devices. the next three bits are all zero bits. the 8th bit of device address is the read/write operation select bit. a read operation is initiated if this bit is high and a write operation is initiated if this bit is low. sda scl eeprom vddp vssp i/o.x i/o.y vdd vss mcu vdd vdd dual vdd/single vss power supply mcu to eeprom internal connection sda scl eeprom vddp vssp i/o.x i/o.y vdd vss mcu vdd vdd dual vdd / dual vss power supply mcu to eeprom internal connection 5         # #  c
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HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 43 march 15, 2010 if the comparison of the device address is successful then the eeprom will output a zero as an ack bit. if not, the eeprom will return to a standby state. device operations  byte write a write operation requires an 8-bit data word address following the device address word and acknowledg - ment. upon receipt of this address, the eeprom will again respond with a zero and then clock in the first 8-bit data word. after receiving the 8-bit data word, the eeprom will output a zero and the addressing device must terminate the write sequence with a stop condi - tion. at this time the eeprom enters an inter - nally-timed write cycle to the non-volatile memory. all inputs are disabled during this write cycle and eeprom will not respond until the write cycle is com - pleted.  acknowledge polling to maximize bus throughput, one technique is to allow the master to poll for an acknowledge signal after the start condition and the control byte for a write com - mand have been sent. if the device is still busy imple - menting its write cycle, then no ack will be returned. the master can send the next read/write command when the ack signal has finally been received.  read operations the data eeprom supports three read operations, namely, current address read, random address read and sequential read. during read operation execution, the read/write select bit should be set to 1.  current address read the internal data word address counter maintains the last address accessed during the last read or write op - eration, incremented by one. this address stays valid between operations as long as the eeprom power is maintained. the address will roll over during a read from the last byte of the last memory page to the first byte of the first page. once the device address with the read/write select bit set to one is clocked in and ac - knowledged by the eeprom, the current address data word is serially clocked out. the microcontroller should respond a no ack - high - signal and a follow - ing stop condition.  random read a random read requires a dummy byte write sequence to load in the data word address which is then clocked in and acknowledged by the eeprom. the microcontroller must then generate another start con - dition. the microcontroller now initiates a current ad - dress read by sending a device address with the read/write select bit high. the eeprom acknowl - edges the device address and serially clocks out the data word. the microcontroller should respond with a no ack signal - high - followed by a stop condition.  sequential read sequential reads are initiated by either a current ad- dress read or a random address read. after the microcontroller receives a data word, it responds with an acknowledgment. as long as the eeprom re- ceives an acknowledgment, it will continue to incre- ment the data word address and serially clock out sequential data words. when the memory address limit is reached, the data word address will roll over and the sequential read continues. the sequential read operation is terminated when the microcontroller responds with a no ack signal - high - followed by a stop condition.   $  / 
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rf transceiver block diagram HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 46 march 15, 2010 rf transceiver rf transceiver features rf/analog circuit features  ism band 2.400ghz~2.495ghz operation  -90dbm/-80dbm sensitivity @ 250k/1m bps (packet error rate under 0.1%)  3dbm maximum input level  -3dbm~0dbm typical output power  differential rf input/output and integrated tx/rx switch  integrated low phase noise vco, frequency synthesizer and pll loop filter  integrated 32mhz oscillator drive  digital vco and filter calibration  18ma in rx and 15ma in tx mode  2.4
a deep sleep mode, 0.1
a power down  1m bps turbo mode supported  pll lock-on time less than 130
s mac/baseband features  automatic ack response and fcs check  62-byte tx fifo  dual 64-byte rx fifos  various power saving modes  simple four-wire spi interface rf transceiver applications  home/building/factory automation  pc peripheral  rf remote controller  consumer electronics  2-way medium-data-rate applications rf transceiver overview the device contains a 2.4 ghz rf transceiver with a baseband/mac block. the rf transceiver can be con- trolled by the mcu for low data rate applications such as consumer electronics, pc peripherals, toys, industrial automations, etc. for medium data rate applications like wireless voice and image transmission, the rf trans- ceiver provides 1m bps turbo mode. interfacing lower mac si so sclk sen int rf_p rf transceiver memory power management phy rf_n vdd gpio0~gpio2 xtal_p xtal_n rst gnd
pin assignment rf transceiver pin description pin name type description rf_p i/o external differential rf input/output (+) rf_n i/o external differential rf input/output (-) vdd_rf1 i external rf transceiver power supply (1) vdd_rf2 i external rf transceiver power supply (1) gpio0 gpio1 i/o external general purpose digital i/o it is also used as an external tx/rx switch control gpio2 i/o external general purpose digital i/o it is also used as an external power amplifier (p.a.) enable control. vdd_d i external rf transceiver digital circuit power supply (+) gnd_d i external rf transceiver digital circuit power supply (-) vdd_2v2 o external rf transceiver dc-dc output voltage it cannot be used. vdd_3v i external rf transceiver 3v input for a dc-dc regulator gnd_gr  external rf transceiver guard-ring ground vdd_a i external rf transceiver power supply for analog circuits (1) xtal_p i external rf transceiver 32mhz crystal input (+) xtal_n i external rf transceiver 32mhz crystal input (-) vdd_pll i external rf transceiver pll power supply (1) vdd_cp i external rf transceiver charge pump power supply (1) vdd_vco i external rf transceiver voltage-controlled oscillator power supply (1) loop_c i/o external rf transceiver pll loop filter external capacitor it is connected to the external 47pf capacitor. HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 47 march 15, 2010 - + -  - , - - - . - * -  *  * * * . * - * , *  * + *  * 0 . / .  . * . . . - . , .  . + .  . 0 - /  -  .  *    / , 0 ,  , + ,  , , , - , . , * ,  , / - 0 -   * . - ,  +  0  /    *  .  -  ,    +    0 * /        ) .
5 
"        +  /    *  .  -  ,    + d   * d 3  4  d    d   / '   4  '   4 * ' * 1 . 1 * 1  ) / )  ) * ) . ) - ) , )  ) + ' '   '   4  ( * 3  ( 4 3 1 - 1 , 1  1 + 5 6 ' 5 6 1   4  3 '   '  )  /    *  .  -  ,  ( 4 3 '   4  (   1 , 5   4  1 , '   4 '  '   4 '   4 5 5 d  3 4 5 5 6   5 4 6   5 4 3  1 - '   4  '   4 d   '   4 1 d '   4 . '        ) .  
      ( 4 3 '   4  ( * 3 '   ' '   1   4  3 ' 5 6 5 6  ) '   4 . '  '   4 d   '   4 1 d '   4  6   5 4 3 6   5 4 '   4 5 5 '   4 '   4 '  5   4 '   4  (   ( 4 1  1 +  /    *      .   -  ,    +  * . - ,  +  0  /    *  .  -  ,    +    0 * / *  * * * . * - * , *  * + *  * 0 . / . . *. .. -. ,. . +. . 0- / '   4 * ' * '   4  d   / d    d   * 1  1 * 1 . 1 - 1 ,
pin name type description vdd_gr i external rf transceiver guard-ring power supply (1) vdd_bg o external rf transceiver bandgap power supply (1) db4 i external test pin it is connected to ground. db5 i external test pin it is connected to ground. si i internal rf transceiver slave spi serial data input signal internally connected to the mcu master spi sdo output signal so o internal rf transceiver slave spi serial data output signal internally connected to the mcu master spi sdi input signal sclk i internal rf transceiver slave spi serial clock input signal internally connected to the mcu master spi sck output signal sen i internal rf transceiver slave spi serial interface enable input signal internally connected to the mcu master spi scs output signal int i internal rf transceiver interrupt output signal internally connected to the mcu int input signal rst i internal rf transceiver global hardware reset input signal, active low. internally connected to the mcu i/o pin configured as output type. nc  implies that the pin is not connected and can therefore not be used. notes: (1) connecting bypass capacitor(s) as close to the pin as possible. (2) the pin descriptions for all external pins except the rf transceiver pins listed in the above table are de- scribed in the preceding mcu section. (3) the int and rst lines are internally connected to the mcu i/o pins pc2 and pc3 respectively for the HT82M75Rew and ht82k75rew devices. rf transceiver d.c. characteristics v dd =3v, ta=25 c symbol test conditions min. typ. max. unit i tx rf transceiver tx active. at 0 dbm output power dc-dc off*  21 30 ma i rx rf transceiver rx active in normal mode (250 kbps) dc-dc off*  19 28 ma rf transceiver rx active in turbo mode (1m bps) dc-dc off*  21 30 ma i stb rf transceiver in standby mode. partial 32mhz clock and sleep clock remains active. rf/mac/bb, system clock shutdown.  60 80
a i ds rf transceiver in deep_sleep mode. power to digital circuit re - mains active to retain registers and fifos. all the other power is shutdown.  3.2 10.0
a i pd rf transceiver in power_down mode. minimum wake-up cir - cuit remains active. all power is shutdown. register and fifo data are not retained.  0.6 2.0
a note: * the operating current i tx or i rx listed here is the additional current consumed when the rf transceiver op - erates in active tx mode or active rx mode. if the rf transceiver is active, either i tx or i rx should be added to calculate the relevant operating current of the device for different operating mode. to calculate the standby current for the whole device, the standby current shown above including i stb ,i ds and i pd should be taken into account for different power saving mode. HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 48 march 15, 2010
rf transceiver a.c. characteristics v dd =3v, ta=25  c, lo frequency=2.445ghz, dc-dc off receiver parameters test conditions min. typ. max. unit rf input frequency  2.400  2.495 ghz rf sensitivity at antenna input with o-qpsk signal, per  0.1% 250kbps  -90  dbm 1 mbps  -80  dbm maximum rf input  5  dbm adjacent channel rejection @  5mhz, 250kbps (-82dbm + 20 db = -62dbm)  20 -62  dbc dbm alternative channel rejection @  10 mhz, 250kbps (-82dbm + 40 db = -42dbm)  40 -42  dbc dbm lo leakage measured at the balun matching the network with the input frequency at 2.4~2.5ghz  -60  dbm noise figure (including matching)  8  db transmitter v dd =3v, ta=25  c, lo frequency=2.445ghz, 250 kbps, dc-dc off parameters test conditions min. typ. max. unit rf carrier frequency  2.400  2.495 ghz maximum rf output power at 0 dbm output power setting -3 0  dbm rf output power accuracy    4 dbm rf output power control range  36  db tx gain control resolution  0.1  0.5 db carrier suppression  -30  dbc tx spectrum mask for o-qpsk signal offset frequency > 3.5 mhz at 0 dbm output power  -30 dbm  -20 dbc tx evm  30  % synthesizer v dd =3v, ta=25  c, lo frequency=2.445ghz, 250 kbps, dc-dc off parameters test conditions min. typ. max. unit pll stable time  130 
s pll programming resolution  1  mhz HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 49 march 15, 2010
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 50 march 15, 2010 rf transceiver power-on and reset characteristics the rf transceiver has built-in power-on reset (por) circuit which automatically resets all digital registers when the power is turned on. the 32mhz oscillator cir - cuit starts to lock frequency of the right clock after power-on. the whole process takes 3ms for a clock cir - cuit to become stable and completes the power-on re - set. it is highly recommended that the user waits at least 3ms before starting to access the rf transceiver. the rf transceiver hardware reset signal (warm start) named rst is controlled by mcu i/o pin and internally pulled high with 33k resistor connected to vcc within the rf transceiver. the rf transceiver will hold in re - set state around 20
s after rst signal is released from the low state. rf transceiver crystal parameter specifications the rf transceiver utilizes external 32mhz crystal to generate the oscillation for rf transceiver input clock. the associated pins are xtal_p and xtal_n. the ta - ble below lists the parameters of the crystal oscillator used in the rf transceiver. to operate the rf trans - ceiver properly, user has to select the crystal which meets the following requirements. parameters min. typ. max. unit crystal frequency 32  mhz frequency offset -40  40 ppm load capacitance  10 pf recovery time  180
s 32 mhz crystal oscillator recovery time highly depends on the shunt capacitance of 32 mhz crystal. the lower shunt capacitance value makes the recovery time shorter. this recovery time 180
s is measured with 32 mhz crystal by ndk nx3225sa. rf transceiver functional description the rf transceiver integrates receiver, transmitter, volt - age-controlled oscillator (vco), and phase-locked loop (pll). it uses advanced radio architecture to minimize the external component count and the power consump - tion. the baseband/mac block provides the hardware architecture for both mac and phy layers. it mainly consists of tx/rx control and digital signal processing module. interconnection between the mcu and the rf transceiver is implemented by internally connecting the mcu master spi interface to the rf transceiver slave spi interface. all data transmissions and receptions be - tween mcu and rf transceiver including rf trans - ceiver commands are conducted along this interconnected spi interface. the rf transceiver func - tion control is executed by the mcu using its spi master serial interface. the rf transceiver contains its own in - dependent interrupt which can be used to indicate when a wake-up event occurs, an available packet reception occurs or when a packet transmission has successfully terminated or retransmission is timed out. rf transceiver internal connection in addition to the rf transceiver external pins de - scribed above there are other mcu to rf transceiver interconnecting lines that are described in the above rf transceiver pin description table. note that these lines are internal to the device and are not bonded to external pins. the rf transceiver is composed of several functional blocks named interfacing block, lower mac block, memory block, power management block and phy block. the detailed functions of the functional blocks are described in the following sections. '   ' '   4  ( 5 2   ) 3  3    2      3     '   ' d 3  d   / d    d   *  ( 4  ( 4 3 6   5 4 6   5 4 3    % &  !   *    +  mcu to rf transceiver internal connection
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 51 march 15, 2010 rf transceiver phy block the key features and the block diagram of the phy layer in rf transceiver are listed as below. operating frequency range is from 2400mhz to 2495mhz. it uses offset qpsk (oqpsk) modulation to transmit data at 250k/1m bps. direct sequence spreading spectrum (dsss) is used in baseband algorithm to increase the snr. the rf transceiver uses a fractional-n phase-locked loop (pll) as frequency synthesizer. therefore, 1mhz channel spacing is supported and any integer carrier frequency between 2400mhz to 2495mhz can be used. the loop filters of pll are integrated into the rf trans - ceiver except one external capacitor which should be connected between the pll loop filter external pin and the ground. in order to keep the pll stable, the board layout around the pll loop filter external capacitor pin should be carefully designed to avoid emi. the recom - mended value of this external capacitor is 47pf. under 1m bps turbo mode, user can use the same pro - gram settings of mac and all mac functions are re - mained the same. compare with 250k bps mode, in 1m bps mode, signal bandwidth is extended to 8mhz. the packet includes a 6 bytes phy header and a 7~63 bytes phy payload. the 6 bytes phy header includes 4 bytes of preamble, 1 byte of start-of-frame delimiter (sfd) and 1 byte of payload length. preamble and sfd are used for receiver packet detection and synchroniza - tion. the frame length field specifies the length of the phy payload field. the valid length can be from 7 to 63 bytes. the frame format is shown as below:        5  c    1 #       5  c
   1 #    1  
   &   !           5 5 5 3     :
 #  " %  
(  # 
5        " #   
 (    phy block architecture
  #
    @ <    #   & -    
     
    
+ k  .    
        ( 
 
#   
( 
5
   % @ <  @
 &
phy layer frame format
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 52 march 15, 2010 rf transceiver low mac block the rf transceiver mac provides plenty of hard - ware-assisted features to relieve the host mcu power requirement. besides providing reliable wireless packet transactions between two nodes, it also handles data and command transfer between the network and the physical layers phy. mac frame format  data frame the address field contains the broadcast address (0xffff-ffffh) or destination address. the bit 0 of frame control (fc) field is used for ack-request which specifies whether an acknowledgement is required from the recipient device. if the bit is 1 , the recipient device shall send an acknowledgement frame back after determining that the received frame is valid. the bit 1 of fc field is 0 for data frame. the length of payload field is variable from 0 to 56 bytes. the frame check sequence (fcs) is calculated over the address field, fc field and the payload. the polynomial is de - gree 16:  acknowledgement frame the length of acknowledgement frame is always 5 bytes. bit 1 of fc field is 1 for ack frame. the payload field, containing user information of acknowledge - ment frame, can be configured by sreg0x03 and sreg0x04. the fcs is calculated over the fcs of the received packet, fc field and the payload field. the polynomial is degree 16: data frame d    8 : 9  i  :    ;  :    ;  :   ;         * , acknowledgement frame d    8 : 9  i  :    ;  :    ;  :   ;         * , @ < 5  c
    6    6   
    
      lower mac block diagram d    8 : 9  i  :    ;  :    ;  :   ;         * ,
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 53 march 15, 2010 txmac when the txfifo is triggered, the txmac gets the data from txfifo to generate a 16-bit fcs and sends the packet to the phy layer of the tx immediately. if necessary, txmac handles the retransmission, when the acknowledgement packet is not received. the block diagram of a txmac is shown below. rxmac the rx phy of the rf transceiver filters signals and tracks the synchronization symbols. if a packet passes the filtering, rxmac performs frame type parsing, ad - dress recognition and fcs checking. if the destination address is broadcast address or matches its own iden - tity, configured by sreg0x05 to sreg0x08, and the fcs check is passed, an interrupt is issued at sreg0x31 [3] to indicate a valid packet is received. meanwhile, the frame length field of phy header and phy payload will be stored in rxfifo. unqualified packets are skipped. rxfifo0 and rxfifo1 are mapped into the 64-byte memory space from 0x300h to 0x33fh as ping-pong fifos. if ping-pong rx mode is enabled by sreg0x34 [0], rxmac automatically switches between rxfifo0 and rxfifo1 to store incoming frame whenever a new packet comes. when the mcu host reads the long ad - dress memory 0x300h, the rxmac will change the flag of sreg0x34 [1] automatically. for manually controlled rx operation, if the value of the flag sreg0x34 [1] is 0 , the rxfifo0 shall be read. otherwise, the rxfifo1 shall be read. in the above diagram, the current status of each frame is represented in sreg0x30. sreg0x30 [7] means rxfifo full indicating the two rxfifos are occupied. if the mcu host cannot read the rxfifo in time, the value of sreg0x30 [7] will be set to 1 . once the mcu host read the rxfifo, the value of the sreg0x30 [7] will be set to 0 automatically. the contents of the rxfifo can be flushed only by the following three ways: (1) the mcu host reads length field of rxfifo and the last byte of the packet, (2) the host issues an rx flush, and (3) the software reset by sreg0x2a [0]. note that rxfifo is ready to receive next packet and all the data in rfifo will be overwritten after rxfifo flushed. txmac block diagram rxmac block diagram
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 54 march 15, 2010 auto acknowledgement the rxmac supports automatically acknowledgement. if and only if the packet is successfully received and an ack-request bit, bit 0, in the fc field of the received packet is set, rxmac informs txmac to send an ac - knowledgement packet automatically. user should write the fc field correctly into the tx fifo. if an acknowledgement is requested and the replied ack frame is not received, the transmitter automatically resends the packet until the maximum retransmission times, specified in sreg0x1b [7:4], are reached. to uti - lize the function properly, the corresponding registers of both transmitting and receiving sides need to be set cor - rectly.  auto-retransmission on tx side to automatically retransmit a packet when an ack is not received, sreg0x1b [2] is required to be set to 1 .  auto-acknowledgement on rx side to automatically reply an ack packet when ack-request bit is set to 1 , sreg0x00 [5] should be set to 0 .
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 55 march 15, 2010 rf transceiver memory block the memory block of the rf transceiver is imple - mented by the sram. as the following memory block diagram shown, the rf transceiver memory is com - posed of registers and fifos, which can be accessed by the spi interface. they are categorized into two kinds of address spaces. one is the short address space; the other is the long address space. registers registers provide control bits and status flags for the rf transceiver operations, including transmission, recep - tion, interrupt control, mac/baseband/rf parameter settings, etc. the registers are divided into two types ac - cording to addressing mode as listed below.  short address register (6-bit short addressing mode register, total 64 registers)  long address register (10-bit long addressing mode register, total 128 registers) short address registers are accessed by short address - ing mode with valid addresses ranging from 0x00h to 0x3fh. long address registers are accessed by long addressing mode with valid addresses ranging from 0x200h to 0x27fh. short registers are accessed faster than long registers. please refer to the following spi in - terface section for detailed addressing rules via spi in - terface. memory space diagram memory block diagram
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 56 march 15, 2010 short address registers legend: r=reserved addr. file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por 0x00 rxmcr r r noackrsp rrrrr 0000 0000 0x03 auinfl auinf7 auinf6 auinf5 auinf4 auinf3 auinf2 auinf1 auinf0 0000 0000 0x04 auinfh auinf15 auinf14 auinf13 auinf12 auinf11 auinf10 auinf9 auinf8 0000 0000 0x05 dadr_0 dadr[7:0] 0000 0000 0x06 dadr_1 dadr[15:8] 0000 0000 0x07 dadr_2 dadr[23:16] 0000 0000 0x08 dadr_3 dadr[31:24] 0000 0000 0x0d rxflush r wakepol wakepad r r ptx r rxflush 0110 0000 0x12 ackto r matop6 matop5 matop4 matop3 matop2 matop1 matop0 0011 1001 0x17 pacon r r r paonts3 paonts2 paonts1 paonts0 r 0000 0010 0x18 txcon r r txonts3 txonts2 txonts1 txonts0 r r 1000 1000 0x1b txtrig txrtyn3 txrtyn2 txrtyn1 txrtyn0 r txackreq r txtrig 0011 0000 0x22 wakectl immwake regwake rrrrrr 0100 0000 0x24 txsr txretry3 txretry2 txretry1 txretry0 r r r txns 0000 0000 0x26 gateclk r r spisync r r entxm r r 0000 0000 0x2a softrst rrrrrr rstbb rstmac 0000 0000 0x2e txpemisp txpet3 txpet2 txpet1 txpet0 rrrr 0111 0101 0x30 rxsr rxfffull wrff1 r rxffovfl rxcrcerr r r r 0000 0000 0x31 isrsts r wakeif r r rxif r r txnif 0000 0000 0x32 intmsk r wakemsk r r rxmsk r r txnmsk 1111 1111 0x34 batrxf r r batind r r r rdff1 rxfifo2 0000 0000 0x35 slpack slpack wakecnt6 wakecnt5 wakecnt4 wakecnt3 wakecnt2 wakecnt1 wakecnt0 0000 0000 0x36 rfctl r r r wakecnt8 wakecnt7 rfrst r r 0000 0000 0x38 bbreg0 rrrrrrr turbo 1000 0001 short address registers list
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 57 march 15, 2010 long address registers legend: r=reserved addr. file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por 0x200 rfctrl0 channel3 channel2 channel1 channel0 r r r r 0000 0001 0x201 rfctrl1 r r r r r r vcorx1 vcorx0 0000 0001 0x202 rfctrl2 r rxfc0-1 rxfc0-0 r r r r r 1000 0100 0x203 rfctrl3 txgb4 txgb3 txgb2 txgb1 txgb0 r r r 0000 0000 0x204 rfctrl4 r r r r r rxfco rxd2co1 rxd2co0 0000 0000 0x205 rfctrl5 batth3 batth2 batth1 batth0 r r r r 0000 0000 0x206 rfctrl6 txfbw1 txfbw0 32mxco1 32mxco0 baten r r r 1111 0000 0x207 rfctrl7 r r r rxfc2 r r r r 0000 0000 0x208 rfctrl8 r txd2co0 r r r r r r 0000 1100 0x209 slpcal_0 slpcal7 slpcal6 slpcal5 slpcal4 slpcal3 slpcal2 slpcal1 slpcal0 0000 0000 0x20a slpcal_1 slpcal15 slpcal14 slpcal13 slpcal12 slpcal11 slpcal10 slpcal9 slpcal8 0000 0000 0x20b slpcal_2 slpcalrdy r r slpcalen slpcal19 slpcal18 slpcal17 slpcal16 0000 0000 0x211 irqctrl r r r r r r irqctrl r 0000 0000 0x22f testmode mpspi r r r r testmode2 testmode1 testmode0 0010 1000 0x23d gpiodir r r gdirctrl2 gdirctrl1 gdirctrl0 gpio2dir gpio1dir gpio0dir 0011 1111 0x23e gpio r r r r r gpio2 gpio1 gpio0 0000 0000 0x250 rfctrl50 r r r dcpoc dcopc3 dcopc2 dcopc1 dcopc0 0000 0000 0x251 rfctrl51 dcopc5 dcopc4 r r r r r r 0000 0000 0x252 rfctrl52 slctrl6 slctrl5 slctrl4 slctrl3 slctrl2 slctrl1 slctrl0 32mxctrl 1111 1111 0x253 rfctrl53 r fifops digitalps p32mxe pacen2 pactrl2-2 pactrl2-1 pactrl2-0 0000 0000 0x254 rfctrl54 1mcsen 1mfrch6 1mfrch5 1mfrch4 1mfrch3 1mfrch2 1mfrch1 1mfrch0 0000 0000 0x259 rfctrl59 r r r r r r r pllopt3 0000 0001 0x273 rfctrl73 vcotxopt1 vcotxopt0 r r pllopt2 pllopt1 pllopt0 r 0000 0000 0x274 rfctrl74 pacen0 pactrl0-2 pactrl0-1 pactrl0-0 pacen1 pactrl1-2 pactrl1-1 pactrl1-0 1100 1010 0x275 rfctrl75 r r r r sclkopt3 sclkopt2 sclkopt1 sclkopt0 0001 0101 0x276 rfctrl76 r r r r r sclkopt6 sclkopt5 sclkopt4 0000 0001 0x277 rfctrl77 r r slpsel1 slpsel0 slpvctrl1 slpvctrl0 slpvsel1 slpvsel0 0000 1000
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 58 march 15, 2010 fifos serve as the temporary data buffers for data transmission and reception. each fifo holds only one packet at a time. txfifo, the transmission fifo, is composed of 62-byte fifo. rx fifo, the receiving fifo, is composed of two 64-byte fifos.  tx fifo - (62 bytes) the txmac gets the to-be transmitted data from the 62-byte txfifo. the memory space of txfifo is from 0x001 to 0x03e and contains a fl field, ad - dress field, fc field and payload field. the fl field in - dicates the length of the address field, fc field and the payload field. the valid value of frame length is from 5 to 61 bytes.  rx fifo - rxfifo0 (64 bytes) and rxfifo1 (64 bytes) a rxfifo is composed of two 64-byte fifos (rxfifo0 and rxfifo1) to store the incoming packet. each of them is designed to store one packet at a time. rxfifo contains a fl field, address field, fc field, payload field and fcs field. the memory space of rxfifo is from 0x300 to 0x33f . the fl field, which is extracted from the phy header, indi - cates the length of the address field, fc field, the pay - load field and fcs field. the valid value of frame length is from 7 to 63 bytes. the value of the fl field of phy header is calculated by adding 2, the length of fcs field of mac frame, and the above mentioned value up. rf transceiver power management block almost all wireless sensor network applications require low-power consumption to lengthen battery life. typical battery-powered device is required to be operated over years without replacing its battery. the rf transceiver achieves low active current consumption of both the dig - ital and the rf/analog circuits by controlling the supply voltage and using low-power architecture. the rf transceiver has four power saving modes that will be further described in power saving modes sec - tion. for ultra low-power operation, power-down mode is available which consumes around 0.1
a while the rf transceiver is powered down. all data stored in regis - ters and fifos will be lost under power-down mode. in this mode, the rf transceiver is able to wake up by a wake-up input signal. except power down mode, the data in the registers/fifos are retained during the other power saving modes. power supply scheme the table below lists the recommended values of the ex - ternal bypass capacitors for each power pin of the rf transceiver. for the power pins vdd_rf1 and vdd_3v, an extra bypass capacitor is needed for the decoupling purpose while the rest of the power pins re - quire only one bypass capacitor. the path length be - tween the bypass capacitors to each pin should be made as short as possible. pin name bypass capacitor 1 bypass capacitor 2 vdd_rf1 47pf 10nf vdd_rf2 47pf vdd_d 10nf vdd_3v 10
f 10nf vdd_a 47pf vdd_pll 47pf vdd_cp 10nf recommended external bypass capacitors txfifo format rxfifo format
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 59 march 15, 2010 dc-dc converter there are two ways to supply power to the rf trans - ceiver. one is through the on-chip dc-dc converter and the other is without the dc-dc converter. with dc-dc converter, the rf transceiver consumes lower current. with the dc-dc converter, power pins including vdd_rf1, vdd_rf2, vdd_d, vdd_a, vdd_pll and vdd_cp should be hardwired to the dc-dc converter output, pin vdd_2v2 of the rf transceiver. without dc-dc converter, all the power pins should be directly hardwired to the external supplied voltage. for this device the on-chip dc-dc converter is not used. user can set lreg0x250 [4] to 0 and lreg0x273 to 0x4e to bypass the dc-dc converter. when the dc-dc converter is bypassed, pins vdd_2v2 and vdd_3v are shorted internally. battery monitor the rf transceiver provides a function to monitor the rf transceiver supplied voltage. a 4-bit voltage thresh - old can be configured so that when the supplied voltage is lower than the threshold, the system will be notified. for battery monitor function, please refer to the section named battery monitor operations. power saving modes the rf transceiver power modes are classified into the following four modes:  idle: rf circuit off. the regulator, oscillator, and digi- tal circuits are on.  standby: rf/mac/bb shutdown with sleep and 32mhz clocks remain active  deep_sleep: all power is shutdown except the power to the digital circuits and registers and fifos data are retained.  power_down: all power is shutdown. registers and fifos data are not retained, a wake-up input sig - nal can wake up the rf transceiver. idle mode is rarely used because the device should at least always turns on its rx circuit to capture the on-air rf signals. the only difference between standby mode and deep_sleep mode is the power status of the sleep clock. to wake the rf transceiver up, the mcu host has to control the time of sleep process. the power management control is used for the low power operation of mac and baseband modules. it manages to turn on and off the 32 mhz clock when the rf transceiver goes into power saving mode. by turn - ing off the 32 mhz clock, the mac and baseband circuits become inactive regardless whether their power sup - plies exist or not. all the digital modules are clock-gated automatically. that means only when a module is func - tioning, its clock would then be turned on. this approach efficiently decreases certain amount of the current con - sumption. rf transceiver interfacing block the interfacing block mainly includes three parts named spi interface, gpio and interrupt signal. each of them is described as followings. spi interface the mcu communicates with the rf transceiver via an internal spi interface to read/write the control registers and fifos. the spi interface connected to the mcu spi master in the rf transceiver has the following fea- tures:  a 4-line slave spi interface composed of: sen (spi enable), sclk (spi clock), si (serial data input) and so (serial data output).  most significant bit (msb) of all addresses and data transfers on the spi interface is done first. block diagram of voltage regulators with dc-dc converter on/bypass
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 60 march 15, 2010 spi addressing format msb of addressing frame indicates the addressing mode of the packet. the length of address field is 6 or 10 bits for short and long addressing mode respectively. bit 0 is a one-bit read/write indicator. spi characteristics parameter symbol min. max. unit conditions sclk, clock frequency f sclk  5 mhz sclk low pulse duration t cl 100  ns the minimum time sclk must be low. sclk high pulse duration t ch 100  ns the minimum time sclk must be high. sen setup time t sp 100  ns the minimum time sen must be low before the first positive edge of sclk. sen hold time t ns 100  ns the minimum time sen must be held low after the last negative edge of sclk. si setup t sd 25  ns the minimum time data must be ready at si, before the positive edge of sclk si hold time t hd 25  ns the minimum time data must be held at si, after the positive edge of sclk. rise time t rise  25 ns the maximum rise time for sclk and sen. fall time t fall  25 ns the maximum fall time for sclk and sen. spi timing diagram the following figures show the timing diagrams for the short and long addressing mode respectively. the mcu spi master will initiate a read or write operation by asserting the interface enable signal sen to low, toggling sclk and sent the address field by si. the interface enable signal sen should be high when a transaction is completed. spi addressing format a6 a5 a3 a4 a2 a1 0 0 d r 7d r 6 d r 4 d r 5 d r 3d r 2 d r 0d r 1 0 a6 x a6 a5 a3 a4 a2 a1 1 0 d w 6 d w 4d w 5 d w 3d w 2 d w 0d w 1 0 d w 7 sclk sen si so si so t sp t sd t hd t ch t cl t ns read short address data write short address data a5 a4 a3 a2 a1 0 x d r 7 d r 5d r 6 a6 a5 a3a4 a2 a1 1 d w 6 d w 5 d w 7 timing diagram of short addressing mode
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 61 march 15, 2010 the spi burst mode is provided for the access of long address memory space on a continuous basis. if sen does not go high after the 8-bit write data and the sclk continuously toggles, the followed 8-bit write data is written to the next address field. same for the read access, the data of the next address will be read. the spi burst mode is only available for the long-address mode. a9 a8 a6 a7 a5 a4 a3 a10 d r 7d r 6 d r 4 d r 5 d r 3d r 2 d r 0d r 1 x a9 a8 a6 a7 a5 a4 a3 a10 a1 d w 7 1 d w 6d w 5 d w 3d w 4 d w 2 a2 sclk sen si so si so t sp t sd t hd t ch t cl t ns read long address data write long address data d r 7 d r 5 d r 6 d w 1d w 0 d w 6d w 7 d w 5 d w 4 a2 a1 0 d r 4 1 1 xx x x xx x x timing diagram of long addressing mode gpio the rf transceiver has 3 digital gpio pins. each gpio pins can be configured as input or output by lreg0x23d respectively. when being configured as an output pad, the driving capability is 4ma for gpio0 and 1ma for gpio1 and gpio2. the status of these pins can be configured or read by lreg0x23e. to benefit wide rang applications, gpio0, gpio1 and gpio2 can be configured to control the external power amplifier (p.a.) and rf switch according to the current rf state automatically. please refer to the following sec - tion named external power amplifier configuration for details. interrupt signal the rf transceiver provides an interrupt output pin named int and the polarity of the interrupt signal is selectable. the rf transceiver issues interrupts to the mcu host on three possible events. if one of the three events happens, the rf transceiver sets the corre - sponding status bit in sreg0x31. if the corresponding interrupt mask in sreg0x32 is clear (i.e. equals 0), an interrupt will be issued on the interrupt output pin int. if the corresponding interrupt mask is set to 1 (masked), no interrupt will be issued, but the status is still present. whenever the sreg0x31 register is read, the interrupt and the status are cleared. the three interrupt events are described as below:  wake-up alert interrupt (wakeif): each time a wake-up event happens the rf transceiver issues the interrupt event.  packet received interrupt (rxif): this interrupt is is - sued when an available packet is received in the rxfifo. an available packet means that it passes a rxmac filter, which includes frame type identifying, address filtering and fcs check.  tx fifo release interrupt (txnif): this interrupt can be issued in two possible conditions. the two condi - tions are when a packet in txfifo is triggered and sent successfully, or when a packet is triggered and the retransmission is timed out.
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 62 march 15, 2010 rf transceiver application guide some typical applications are described in this section to help user gains more understanding of the operation of the rf transceiver. rf transceiver hardware connection a typical application connection is shown in application circuit section. the mcu host serves as a master role, and the rf transceiver serves as a slave role. for more information, refer to the application circuit section. rf transceiver initialization after the rf transceiver is powered up, some registers need to be configured before the data transmission or recep - tion. the procedure is described as below.  procedure list parameter symbol min. max. unit conditions sreg 0x26 gateclk enable spi sync function 20 sreg 0x17 pacon1 increase paon time 08 sreg 0x18 fifoen increase txon time 94 sreg 0x2e txpemisp vco calibration period 95 lreg 0x200 rfctl0 rf optimized control 01 lreg 0x201 rfctl1 rf optimized control 02 lreg 0x202 rfctl2 rf optimized control e0 lreg 0x204 rfctl4 rf optimized control 06 lreg 0x206 rfctl6 rf optimized control c0 1m bps lreg 0x207 rfctl7 rf optimized control f0 1m bps lreg 0x208 rfctl8 rf optimized control 8c lreg 0x23d gpiodir for setting gpio to output 00 lreg 0x250 rfctl50 rf optimized control 07 dc-dc off lreg 0x251 rfctl51 rf optimized control c0 lreg 0x252 rfctl52 rf optimized control 01 lreg 0x259 rfctl59 rf optimized control 00 lreg 0x273 rfctl73 rf optimized control 40 lreg 0x274 rfctl74 rf optimized control c6 dc-dc off lreg 0x275 rfctl75 rf optimized control 13 lreg 0x276 rfctl76 rf optimized control 07 sreg 0x32 intmsk enable all interrupt 00 sreg 0x2a softrst baseband reset 02 sreg 0x36 rfctl rf reset 04 reset rf state machine sreg 0x36 rfctl rf reset 00 release rf state machine
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 63 march 15, 2010  registers associated with initialization addr. file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por 0x17 pacon r r r paonts3 paonts2 paonts1 paonts0 r 0000 0010 0x18 txcon r r txonts3 txonts2 txonts1 txonts0 r r 1000 1000 0x26 gateclk r r spisync r r entxm r r 0000 0000 0x2a softrst r r rrrr rstbb rstmac 0000 0000 0x2e txpemisp txpet3 txpet2 txpet1 txpet0 rrrr 0111 0101 0x32 intmsk r wakemsk r r rxmsk r r txnmsk 1111 1111 0x36 rfctl r r r wakecnt8 wakecnt7 rfrst r r 0000 0000 0x200 rfctrl0 channel3 channel2 channel1 channel0 rrrr 0000 0001 0x201 rfctrl1 r r rrrr vcorx1 vcorx0 0000 0001 0x202 rfctrl2 r rxfc0-1 rxfc0-0 rrrrr 1000 0100 0x204 rfctrl4 r r r r r rxfco rxd2co1 rxd2co0 0000 0000 0x206 rfctrl6 txfbw1 txfbw0 32mxco1 32mxco0 baten r r r 1111 0000 0x207 rfctrl7 r r r rxfc2 rrrr 0000 0000 0x208 rfctrl8 r txd2co0 rrrrrr 0000 1100 0x23d gpiodir r r gdirctrl2 gdirctrl1 gdirctrl0 gpio2dir gpio1dir gpio0dir 0011 1111 0x250 rfctrl50 r r r dcpoc dcopc3 dcopc2 dcopc1 dcopc0 0000 0000 0x251 rfctrl51 dcopc5 dcopc4 rrrrrr 0000 0000 0x252 rfctrl52 slctrl6 slctrl5 slctrl4 slctrl3 slctrl2 slctrl1 slctrl0 32mxctrl 1111 1111 0x259 rfctrl59 r r rrrrr pllopt3 0000 0001 0x273 rfctrl73 vcotxopt1 vcotxopt0 r r pllopt2 pllopt1 pllopt0 r 0000 0000 0x274 rfctrl74 pacen0 pactrl0-2 pactrl0-1 pactrl0-0 pacen1 pactrl1-2 pactrl1-1 pactrl1-0 1100 1010 0x275 rfctrl75 r r r r sclkopt3 sclkopt2 sclkopt1 sclkopt0 0001 0101 0x276 rfctrl76 r r r r r sclkopt6 sclkopt5 sclkopt4 0000 0001 change rf channel procedure the rf transceiver operates in 2.4ghz ism band. the operating frequency is divided into 16 channels. the proce - dure to change the channels is described as below.  set the rf channel. users can select one of the channels by configuring either lreg0x200 or lreg0x254.  turn on the tx mac gated clock by setting sreg0x26 [2] to 1. to avoid an incomplete acknowledgment frame transmission happen during rf state machine reset period.  reset rf transceiver state machine by setting sreg0x36 [2] to 1 and then set sreg0x36 [2] back to 0.  after rf transceiver reset, delay for a while to ensure the acknowledgment frame, if any, is successfully transmitted. 250 kbps mode: delay 550
s 1m bps mode: delay 300
s  to disable the tx mac gated clock by setting sreg26 [2] to 0. registers associated with change channel procedure. addr. file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por 0x26 gateclk r r spisync r r entxm r r 0000 0000 0x36 rfctl r r r wakecnt8 wakecnt7 rfrst r r 0000 0000 0x200 rfctrl0 channel3 channel2 channel1 channel0 r r r r 0000 0001 0x254 rfctrl54 1mcsen 1mfrch6 1mfrch5 1mfrch4 1mfrch3 1mfrch2 1mfrch1 1mfrch0 0000 0000
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 64 march 15, 2010 rf transceiver interrupt configuration the rf transceiver issues a hardware interrupt at the internally connected interrupt signal line named int to the mcu host. there are two related registers that need to be set correctly. all the interrupts are masked (disabled) by default. the interrupt mask should be removed by setting sreg0x32 in advance. the interrupt is by default sent to the mcu host as a falling edge signal after mask removed. the polarity can be configured by lreg0x211. the interrupt status can be read from sreg0x31 when it is triggered. registers associated with interrupt configuration addr. file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por 0x31 isrsts r wakeif r r rxif r r txnif 0000 0000 0x32 intmsk r wakemsk r r rxmsk r r txnmsk 1111 1111 0x211 irqctrl r r r r r r irqpol r 0000 0000 rf transceiver external power amplifier configuration to enable the power amplifier (p.a.), users can set lreg0x22f [2:0] value to 0x001b. this register setting integrates the p.a. enable and the rf switch control (tx branch, rx branch) by utilizing gpio0, gpio1 and gpio2. if the rf transceiver is in tx mode, the gpio0 (external p.a. enable) and gpio1 (tx branch enable) will be pulled high, and gpio2 (rx branch enable) will be pulled low. if the rf transceiver is in rx mode, the gpio0 and gpio1 will be pulled low, and gpio2 will be pulled high. the status of gpio pins are automatically changed corresponding to tx/rx mode of the rf transceiver.  tx mode: [gpio0, gpio1, gpio2] = [high, high, low]  rx mode: [gpio0, gpio1, gpio2] = [low, high, high] registers associated with external power amplifier configuration addr. file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por 0x22f testmode mspi r r r r testmode2 testmode1 testmode0 0010 1000 rf transceiver turbo mode configuration the rf transceiver provides 1m bps turbo mode to transmit and receive data at a higher data rate. turbo mode pro- vides an added capability for applications which require more bandwidth. the application circuits need not any modifi - cation for turbo mode. to use the rf transceiver in 250k and 1m bps, the following registers need to be configured as below. address mode addr. register name descriptions value (hex) 250k 1m lreg 0x206 rfctl6 rf optimized control 0x00 0xc0 lreg 0x207 rfctl7 rf optimized control 0xe0 0xf0 sreg 0x38 bbreg0 enable normal/turbo mode 0x80 0x81 sreg 0x2a softrst baseband reset 0x02 registers associated with external power amplifier configuration addr. file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por 0x2a softrst r r r r r r rstbb rstmac 0000 0000 0x38 bbreg0 r r r r r r r turbo 1000 0001 0x206 rfctrl6 txfbw1 txfbw0 32mxco1 32mxco0 baten r r r 1111 0000 0x207 rfctrl7 r r r rxfc2 r r r r 0000 0000
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 65 march 15, 2010 typical rf transceiver tx operation the txmac inside the rf transceiver will automatically generate the preamble, start-of-frame delimiter and the fcs when transmitting. the mcu host must write all other frame fields into txfifo for tx operation. to send a packet in tx fifo, there are several steps to follow: fill necessary data in txfifo. the format of txfifo is as follows: txfifo address 0x001 0x0+n 1 byte 4 bytes 1 byte n bytes frame length destination address frame control payload  set ackreq by sreg0x1b [2], if an acknowledgement / retransmission is required. the rf transceiver automatically retransmits the packet till the number of the max trial times specified in sreg1b [7:4] is reached, if there is no ac - knowledgement received.  by triggering sreg0x1b [0], the txmac will send the packet immediately. this bit will be automatically cleared.  wait for the interrupt status shown in sreg0x31 [0]. if retransmission is not required, sreg0x31 [0] indicates the packet is successfully transmitted.  check sreg0x24 [0] to see if transmission is successful. if sreg0x24 [0] is equal to 0, it means that the transmis - sion is successful and the ack was received. the number of times of the retransmission can be read at sreg0x24 [7:4]. if sreg0x24 [0] is equal to 1, it means that the transmission failed and ack was not received. registers associated with typical tx operation addr. file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por 0x1b txtrig txrtyn3 txrtyn2 txrtyn1 txrtyn0 r txackreq r txtrig 0011 0000 0x24 txsr txretry3 txretry2 txretry1 txretry0 r r r txns 0000 0000 0x31 isrsts r wakeif r r rxif r r txnif 0000 0000 typical rf transceiver rx operation when a valid packet is received, an interrupt is issued at sreg0x31 [3]. the mcu host can read the whole packet in- side the rxfifo. the rxfifo is flushed when the frame length field and the last byte of rxfifo are read, or when the mcu host triggers a rx flush by sreg0x0d [0]. the format of rxfifo is as follows:  rxfifo address 0x300 0x307+n 1 byte 4 bytes 1 byte n byte 1 bytes frame length destination address frame control payload frame control  registers associated with typical rx operation addr. file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por 0x0d rxflush rrrrrptxr rxflush 0110 0000 0x31 isrsts r wakeif r r rxif r r txnif 0000 0000
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 66 march 15, 2010 rf transceiver power saving operation standby, deep-sleep and power-down modes are designed for the rf transceiver. it is only allowed to switch be - tween power saving modes and active mode. the following settings are effective in active mode only. standby mode shutdown rf/mac/bb, while the voltage regulator, partial 32mhz clock and sleep clock remains active.  set lreg0x277 [5:4] to 00 to select for standby mode.  set lreg0x277 [3:2] to 10 for enable sleep voltage automatically controlled by internal circuit.  set lreg0x253 [4] to 1 to enable partial 32mhz clock. deep_sleep mode all power is shutdown except the power to the digital circuits and sleep clock. registers and fifos are retained.  set lreg0x277 [5:4] to 00 to select for deep_sleep mode.  set lreg0x277 [3:2] to 10 for enable sleep voltage automatically controlled by internal circuit. power down mode all power is shutdown. registers and fifos data are not retained. initialization is needed after the rf transceiver back to active mode. only the internal connected interrupt line named wake can wake the rf transceiver up.  set lreg0x277 [5:4] to 11 to select for power down mode.  set lreg0x277 [3:2] to 10 for enable sleep voltage automatically controlled by internal circuit.  set lreg0x253 [6:5] to 11 to connect the fifo power and digital circuit power to ground. if the internal connected interrupt line named wake is going to be used to wake the rf transceiver up, the configura - tion for wake line should be included. refer to the following wake line wake-up section for details. the on-chip dc-dc converter is not used for this device and then bypasses it by setting the dcpoc bit in lreg0x250 register to 0. after the necessary settings mentioned above are configured, user can execute the following procedures to disable spisync and place the rf transceiver to the desired power saving mode.  set sreg0x26 [5] to 0 to disable spisync.  set sreg0x35 [7] to 1 to place the rf transceiver to power saving mode. registers associated with power saving operation: addr. file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por 0x26 gateclk r r spisync r r entxm r r 0000 0000 0x35 slpack slpack wakecnt6 wakecnt5 wakecnt4 wakecnt3 wakecnt2 wakecnt1 wakecnt0 0000 0000 0x250 rfctrl50 r r r dcpoc dcopc3 dcopc2 dcopc1 dcopc0 0000 0000 0x253 rfctrl53 r fifops digitalps p32mxe pacen2 pactrl2-2 pactrl2-1 pactrl2-0 0000 0000 0x277 rfctrl77 r r slpsel1 slpsel0 slpvctrl1 slpvctrl0 slpvsel1 slpvsel0 0000 1000
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 67 march 15, 2010 rf transceiver wake-up operation after entering into power saving mode, the rf transceiver could be waked up by the internal register trigger. one and only one method should be used for wake-up operation.  configure clock recovery time wakecnt, used to calculate for recovery time of 32mhz clock of the rf transceiver, should be set in advance. user shall follow the following two steps to configure wakecnt. calculate the period of sleep clock set lreg0x20b [4] to 1 and then keep polling lreg0x20b [7] until the value becomes 1. after the value of lreg0x20b [7] becomes 1, lreg0x20b [3:0], lreg0x20a, lreg0x209 form a 20-bit value c. then the period of the sleep clock (p sleepclock ) can be calculated by the following equation: p sleepclock = 62 5 16 . () xc ns if the sleep clock frequency is higher than the expected value, user can configure lreg0x220 [4:0] to slow down the clock rate. the new clock period p sleepclock_new is obtained by the following equation: p sleepclock_new =p sleepclock_ori  2 lreg0x220[4:0] (ns) configure wakecnt to set the recovery time of 32mhz clock to 180
s set wakecnt, i.e. sreg0x36 [4:3] and sreg0x35 [6:0], to (1000*180) / p sleepclock . for example, the period of the sleep clock, p sleepclock , is 10000ns. set sreg0x36 [4:3] and sreg0x35 [6:0]} to 0x12. register trigger wake-up user can wake the rf transceiver up from standby and deep_sleep modes by simply setting sreg0x22 [7:6] to 11 . when the rf transceiver is woken up by register trigger, the following steps shall be executed to complete the opera - tion:  wait the rf transceiver issues a wake-up interrupt. the related wake-up interrupt flag is stored in sreg0x31 [6].  turn on spisync function by setting sreg0x26 [5] to 1.  setting the lreg0x250 [4] to 1 to turn off the on-chip dc-dc converter. registers associated with power saving operation: addr. file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por 0x0d rxflush rrrrrptxr rxflush 0110 0000 0x22 wakectl immwake regwake rrrrrr 0100 0000 0x26 gateclk r r spisync r r entxm r r 0000 0000 0x31 isrsts r wakeif r r rxif r r txnif 0000 0000 0x35 slpack slpack wakecnt6 wakecnt5 wakecnt4 wakecnt3 wakecnt2 wakecnt1 wakecnt0 0000 0000 0x36 rfctl r r r wakecnt8 wakecnt7 rfrst r r 0000 0000 0x209 slpcal_0 slpcal7 slpcal6 slpcal5 slpcal4 slpcal3 slpcal2 slpcal1 slpcal0 0000 0000 0x20a slpcal_1 slpcal15 slpcal14 slpcal13 slpcal12 slpcal11 slpcal10 slpcal9 slpcal8 0000 0000 0x20b slpcal_2 slpcalrd y r r slpcalen slpcal19 slpcal18 slpcal17 slpcal16 0000 0000 0x250 rfctrl50 r r r dcpoc dcopc3 dcopc2 dcopc1 dcopc0 -0000 0000
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 68 march 15, 2010 primary rf transceiver tx operation users activate the primary tx mode by setting sreg0x0d [2] to 1. after changing the sreg0x0d [2] value, users have to reset the rf and let rf state machine go to primary tx mode correctly. if primary tx mode is enabled, the rf transceiver will enter power waving mode after ant packet transmits. if primary tx mode is not enabled, the rf trans - ceiver will switch to rx mode after any packet transmits. if ack response is needed and primary tx mode is enabled, the rf transceiver will enter the power saving mode after ack frame received. if no ack frame received, the rf transceiver will not enter the power saving mode until the max time to wait for an acknowledgement frame by setting sreg0x12 [6:0]. registers associated with power saving operation: addr. file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por 0x0d rxflush rrrrrptxr rxflush 0110 0000 0x12 ackto r matop6 matop5 matop4 matop3 matop2 matop1 matop0 0011 1001 rf transceiver battery monitor operation the rf transceiver has battery monitor function and the procedure to enable the battery monitor function is described as below.  set the battery monitor threshold value at lreg0x205 [7:4].  enable the battery monitor by setting the lreg0x206 [3] to the value 1.  read the battery-low indicator at sreg0x34 [5]. if this bit is set, it means that the supply voltage is lower than the bat - tery monitor threshold specified by lreg0x205 [7:4]. registers associated with power saving operation: addr. file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por 0x34 batrxf r r batind r r r rdff1 rxfifo2 0000 0000 0x205 rfctrl5 batth3 batth2 batth1 batth0 rrrr 0000 0000 0x206 rfctrl6 txfbw1 txfbw0 32mxco1 32mxco0 baten r r r 1111 0000 rf transceiver register definitions the memory of the rf transceiver is categorized into two kinds of addressing mode, known as short addressing reg - isters and long addressing registers. each of the register definition is described in the following sections. legends of rf transceiver register types register type description r/w read/write register wt write 1 to trigger register, automatically cleared by hardware rc read to clear register r read-only register r/w1c read/write 1 to clear register
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 69 march 15, 2010 rf transceiver short addressing registers (sreg0x00~sreg0x3f) 0x00 rxmcr 0x12 ackto 0x22 wakectl 0x30 rxsr 0x03 auinfl 0x17 pacon 0x24 txsr 0x31 isrsts 0x04 auinfh 0x18 txcon 0x26 gateclk 0x32 intmsk 0x05 dadr_0 0x1b txtrig 0x2a softrst 0x34 batrxf 0x06 dadr_1  0x2e txpemisp 0x35 slpack 0x07 dadr_2  0x36 rfctl 0x08 dadr_3  0x38 bbreg0 0x0d rxflush   sreg0x00 - rxmcr: receive mac control register bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name  noackrsp  type r r r/w rrrrr por00 0 00000 bit 7~6 reserved: maintain as 0b00 bit 5 noackrsp : automatic acknowledgement response 0: (default) enables automatic acknowledgement response 1: disables automatic acknowledgement response bit 4~0 reserved: maintain as 0b00000  sreg0x03 - auinfl: acknowledgement user information low byte bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name auinf7 auinf6 auinf5 auinf4 auinf3 auinf2 auinf1 auinf0 type r/w r/w r/w r/w r/w r/w r/w r/w p o r00000000 bit 7~0 auinf [7:0 ]: 16-bit user information of acknowledgement frame low byte.  sreg0x04 - auinfh: acknowledgement user information high byte bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name auinf15 auinf14 auinf13 auinf12 auinf11 auinf10 auinf9 auinf8 type r/w r/w r/w r/w r/w r/w r/w r/w p o r00000000 bit 7~0 auinf [15:8] : 16-bit user information of acknowledgement frame high byte.  sreg0x05 - dadr_0: device address 0 bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name dadr7 dadr6 dadr5 dadr4 dadr3 dadr2 dadr1 dadr0 type r/w r/w r/w r/w r/w r/w r/w r/w p o r00000000 bit 7~0 dadr [7:0] : 32-bit address of the rf transceiver.
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 70 march 15, 2010  sreg0x06 - dadr_1: device address 1 bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name dadr15 dadr14 dadr13 dadr12 dadr11 dadr10 dadr9 dadr8 type r/w r/w r/w r/w r/w r/w r/w r/w p o r00000000 bit 7~0 dadr [15:8] : 32-bit address of the rf transceiver  sreg0x07 - dadr_2: device address 2 bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name dadr23 dadr22 dadr21 dadr20 dadr19 dadr18 dadr17 dadr16 type r/w r/w r/w r/w r/w r/w r/w r/w p o r00000000 bit 7~0 dadr [23:16] : 32-bit address of the rf transceiver.  sreg0x08 - dadr_3: device address 3 bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name dadr31 dadr30 dadr29 dadr28 dadr27 dadr26 dadr25 dadr24 type r/w r/w r/w r/w r/w r/w r/w r/w p o r00000000 bit 7~0 dadr [31:24] : 32-bit address of the rf transceiver  sreg0x0d - rxflush: receive fifo flush bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name  ptx  rxflush type rrrrrr/wrwt por01100000 bit 7 reserved: maintain as 0b0 bit 6-5 reserved: maintain as 0b11 bit 4-3 reserved: maintain as 0b00 bit 2 ptx : primary tx mode enable (1) 1: primary tx mode 0: primary rx mode (default) note: rf reset, sreg0x36 [2], is needed after switching between ptx and prx modes bit 1 reserved: maintain as 0b0 bit 0 rxflush : flush the rx fifo 1: flush rx fifo. rx fifo data is not modified. if ping-pong fifo is enabled (sreg0x34 [0] =1), both fifos are flushed at the same time. bit is automatically cleared to 0 by hardware.
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 71 march 15, 2010  sreg0x12 - ackto: acknowledgement timeout period bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name  matop6 matop5 matop4 matop3 matop2 matop1 matop0 type r r/w r/w r/w r/w r/w r/w r/w por00111001 bit 7 reserved: maintain as 0b0 bit 6~0 matop [6:0] : maximum acknowledgement timeout period 0000000: 0 (default) 0000001: 1 0000010: 2 : 0111001: 57 : 1111111: 127  sreg0x17 - pacon: power amplifier control register bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name  paonts3 paonts2 paonts1 paonts0  type r r r r/w r/w r/w r/w r por00000010 bit 7~5 reserved: maintain as 0b000 bit 4~1 paonts [3:0] : power amplifier settling time to begin packet transmission. 0001: (default) 0100: (optimized - do not change) bit 0 reserved: maintain as 0b0  sreg0x18 - txcon: transmitter control register bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name  txonts3 txonts2 txonts1 txonts0  type r r r/w r/w r/w r/w r r por00001000 bit 7~6 reserved: maintain as 0b00 bit 5~2 txonts [3:0] : transmitter settling time to begin packet transmission 0010: (default) 0101: (optimized - do not change) bit 1~0 reserved: maintain as 0b00
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 72 march 15, 2010  sreg0x1b - txtrig: transmit fifo control register bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name txrtyn3 txrtyn2 txrtyn1 txrtyn0  txackreq  txtrig type r/w r/w r/w r/w r r/w r wt por00110 0 00 bit 7-4 txrtyn [3:0 ]: maximum tx retry times 0000: 0 : 0011: 3 (default) : 0101: 15 bit 3 reserved: maintain as 0b0 bit 2 txackreq : tx fifo acknowledge request bit 1: acknowledgement packet requested 0: no acknowledgement packet requested (default) transmit a packet with acknowledgement request. if acknowledgement is not received, the rf transceiver retransmits up to xx times. bit 1 reserved: maintain as 0b0 bit 0 txtrig : transmit trigger bit 1: transmit frame in tx fifo. bit is automatically cleared to 0 by hardware.  sreg0x22 - wakectl: wake-up control register bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name immwake regwake  type r/w wt rrrrrr por01000000 bit 7 immwake : immediate wake-up mode enable bit 1: enable immediate wake-up mode 0: disable immediate wake-up mode (default) bit 6 regwake : register triggered wake-up bit 1: to wake the rf transceiver up. bit is automatically to 0 by hardware. bit 5~0 reserved: maintain as 0b000000  sreg0x24 - txsr: tx status register bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name txretry3 txretry2 txretry1 txretry0  txnx type rrrrrrrr por00000000 bit 7-4 txretry [3:0] : txfifo retry times 0000: 0 (default) : 0101: 15 txretry indicates the maximum number of retries of the most recent txfifo transmission. bit 3-1 reserved: maintain as 0b000 bit 0 txnx : txfifo normal release status 1: fail, retry count exceed 0: succeeded (default)
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 73 march 15, 2010  sreg0x26 - gateclk: gated clock control register bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name  spisync  entrm  type r r r/w r r r/w r r por00000000 bit 7~6 reserved: maintain as 0b00 bit 5 spisync : spi interface synchronization 1: enable (optimized - do not change) 0: disable (default) bit 4~3 reserved: maintain as 0b00 bit 2 entrm : tx mac clock enable control 1: enable 0: disable (default) bit 1~0 reserved: maintain as 0b00  sreg0x2a - softrst: software reset control register bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name  rstbb rstmac type rrrrrrwtwt por00000000 bit 7-2 reserved: maintain as 0b000000 bit 1 rstbb : baseband reset 1: reset baseband circuitry. initialization is not needed after rstbb reset. bit is automatically cleared to 0 by hardware. bit 0 rstmac : mac and short/long addressing registers reset. 1: reset mac circuitry and short/long addressing registers. initialization is needed after rstmac reset. bit is automatically cleared to 0 by hardware.  sreg0x2e - txpemisp: transmit parameters register bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name txpet3 txpet2 txpet1 txpet0  type r/w r/w r/w r/w rrrr por01110101 bit 7~4 txpet [3:0] : txfifo retry times. 0111: (default) 1001: (optimized - do not change) bit 3~0 reserved: maintain as 0b0101
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 74 march 15, 2010  sreg0x30 - rxsr: rx mac status register bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name rxfffull wrff1  rxffovfl rxcrcerr  type r r r r r r r r por000 0 0 000 bit 7 rxfffull : rx fifo full 1: rx fifo is not available for data receiving 0: rx fifo is available for data receiving (default) bit 6 wrff1 : rx fifo status 1: packet is ready in rx fifo 1 0: packet is ready in rx fifo 0 (default) bit 5 reserved: maintain as 0b0 bit 4 rxffovfl : rx fifo overflow 1: rx fifo overflows 0: (default) rx fifo not overflow bit 3 rxcrcerr : rx crc error 1: rx crc error 0: rx crc is correct (default) bit 2~0 reserved: maintain as 0b000  sreg0x31 - isrsts: interrupt status register bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name  wakeif  rxif  txnif type r rc r r rc r r rc por00000000 bit 7 reserved: maintain as 0b0 bit 6 wakeif : wake-up alert interrupt 1: a wake-up interrupt occurred 0: no wake-up alert interrupt occurred (default) this bit is cleared to 0 when the register is read. bit 5-4 reserved: maintain as 0b00 bit 3 rxif : rx fifo reception interrupt 1: a rx fifo reception interrupt occurred 0: no rx fifo reception interrupt occurred (default) this bit is cleared to 0 when the register is read. bit 2-1 reserved: maintain as 0b00 bit 0 txnif : tx fifo normal transmission interrupt 1: tx fifo normal transmission interrupt occurred 0: no tx fifo normal transmission interrupt occurred (default) this bit is cleared to 0 when the register is read.
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 75 march 15, 2010  sreg0x32 - intmsk: interrupt mask control register bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name  wakemsk  rxmsk  txnmsk type r r/w r r r/w r r r/w por11111111 bit 7 reserved: maintain as 0b1 bit 6 wakemsk : wake-up alert interrupt mask 1: disable the wake-up interrupt (default) 0: enable the wake-up alert interrupt bit 5~4 reserved: maintain as 0b11 bit 3 rxmsk : rx fifo reception interrupt mask 1: disable the rx fifo reception interrupt (default) 0: enable the rx fifo reception interrupt bit 2~1 reserved: maintain as 0b11 bit 0 txnmsk : tx fifo normal transmission interrupt mask 1: disable the tx fifo normal transmission interrupt (default) 0: enable the tx fifo normal transmission interrupt  sreg0x34 - batrxf: battery and rx fifo control register bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name  batind  rdff1 rxfifo2 type rrrrrrrr/w por00000000 bit 7~6 reserved: maintain as 0b00 bit 5 batind : battery low indicator 1: battery voltage is lower than the threshold voltage specified by the lreg0x205 [7:4]. 0: battery voltage is higher than the threshold voltage specified by the lreg0x205 [7:4] (default) bit 4~2 reserved: maintain as 0b000 bit 1 rdff1 : rx fifo selected to read 1: read data from rx fifo 1 0: read data from rx fifo 0 (default) bit 0 rxfifo2 : rx ping-pong fifo enable control 1: enable the rx ping-pong fifos 0: disable the rx ping-pong fifos (default)  sreg0x35 - slpack: sleep acknowledgement and wake-up counter register bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name slpack wakecnt6 wakecnt5 wakecnt4 wakecnt3 wakecnt2 wakecnt1 wakecnt0 type wt r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7 slpack : sleep acknowledgement place the rf transceiver to power saving mode. bit is automatically cleared to 0 by hardware. bit 6~0 wakecnt [6:0] : system clock recovery time 0000000: (default). wakecnt is a 9-bit value. the wakecnt [8:7] bits are located in sreg0x36 [4:3].
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 76 march 15, 2010  sreg0x36 - rfctl: rf mode control register bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name  wakecnt8 wakecnt7 rfrst  type r r r r/w r/w r/w r r por00000000 bit 7~5 reserved: maintain as 0b000 bit 4~3 wakecnt [8:7] : system clock recovery time 00: (default). wakecnt is a 9-bit value. the wakecnt [6:0] bits are located in sreg0x35 [6:0]. bit 2 rfrst : rf state machine reset. 1: hold rf state machine in reset state 0: normal operation of rf state machine (default) perform rf reset by setting rfrst to 1 and then setting rfrst to 0 . delay at least 192
s after performing to allow rf circuitry to calibrate. bit 1~0 reserved: maintain as 0b00  sreg0x38 - bbreg0: baseband register bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name  turbo type rrrrrrrr/w por10000001 bit 7~1 reserved: maintain as 0b1000000 bit 0 turbo : turbo mode select 1: 1m bps turbo mode (default) 0: 250k bps normal mode rf transceiver long addressing registers (lreg0x200~lreg0x27f) 0x200 rfctrl0 0x211 irqctl 0x250 rfctrl50 0x273 rfctrl73 0x201 rfctrl1 0x22f testmode 0x251 rfctrl51 0x274 rfctrl74 0x202 rfctrl2 0x23c  0x252 rfctrl52 0x275 rfctrl75 0x203 _rfctrl3 0x23d gpiodir 0x253 rfctrl53 0x276 rfctrl76 0x204 rfctrl4 0x23e gpio 0x254 rfctrl54 0x277 rfctrl77 0x205 rfctrl5  0x259 rfctrl59  0x206 rfctrl6  0x207 rfctrl7  0x208 rfctrl8  0x209 slpcal_0  0x20a slpcal_1  0x20b slpcal_2 
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 77 march 15, 2010  lreg0x200 - rfctrl0: rf control register 0 bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name channel 3 channel 2 channel 1 channel 0  type r/w r/w r/w r/w rrrr por00000001 bit 7~4 channel [3:0] : channel number. ieee 802.15.4 2.4ghz band channels (11~26) 0000: channel 11, 2405mhz (default) 0001: channel 12, 2410mhz 0010: channel 13, 2415mhz 0011: channel 14, 2420mhz 0100: channel 15, 2425mhz 0101: channel 16, 2430mhz 0110: channel 17, 2435mhz 0111: channel 18, 2440mhz 1000: channel 19, 2445mhz 1001: channel 20, 2450mhz 1010: channel 21, 2455mhz 1011: channel 22, 2460mhz 1100: channel 23, 2465mhz 1101: channel 24, 2470mhz 1110: channel 25, 2475mhz 1111: channel 26, 2480mhz bit 3~0 reserved: maintain as 0b0001  lreg0x201 - rfctrl1: rf control register 1 bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name  vcorx1 vcorx0 type rrrrrrr/wr/w por00000001 bit 7~2 reserved: maintain as 0b000000 bit 1~0 vcorx [1:0] :rxvc 01: (default) 10: (optimized - do not change)  lreg0x202 - rfctrl2: rf control register 2 bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name  rxfc0-1 rxfc0-0  type r r/w r/w rrrrr por10000000 bit 7 reserved: maintain as 0b1 bit 6~5 rxfc0 [1:0] : rx filter control 0. 00: (default) 11: (optimized - do not change) bit 4~0 reserved: maintain as 0b00000
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 78 march 15, 2010  lreg0x203 - rfctrl3: rf control register 3 bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name txgb4 txgb3 txgb2 txgb1 txgb0  type r/w r/w r/w r/w r/w r r r por00000000 bit 7-3 txgb [4:0] : tx gain control in db. gain step is monotonic and nonlinear with gain resolution of 0.1 ~ 0.5 db. gain resolution is variable between chips. 00000: 0 dbm (default) 00001: -0.1 dbm 00010: -0.3 dbm 00011: -0.6 dbm 00100: -0.9 dbm 00101: -1.1 dbm 00110: -1.2 dbm 00111: -1.3 dbm 01000: -1.4 dbm 01001: -1.5 dbm 01010: -1.7 dbm 01011: -2.0 dbm 01100: -2.2 dbm 01101: -2.4 dbm 01110: -2.6 dbm 01111: -2.8 dbm 10000: -3.1 dbm 10001: -3.3 dbm 10010: -3.6 dbm 10011: -3.8 dbm 10100: -4.2 dbm 10101: -4.4 dbm 10110: -4.7 dbm 10111: -5.0 dbm 11000: -5.3 dbm 11001: -5.7 dbm 11010: -6.2 dbm 11011: -6.5 dbm 11100: -6.9 dbm 11101: -7.4 dbm 11110: -7.9 dbm 11111: -8.3 dbm tx output power configuration summary table: tx output power register control lreg0x253 [3:0] lreg0x274 [7:0] lreg0x203 [7:3] tx output power 00 c6 for dc-dc off 00000 0 dbm 00001 -0.1 dbm 00010 -0.3 dbm 00011 -0.6 dbm 00100 -0.9 dbm 00101 -1.1 dbm 00110 -1.2 dbm 00111 -1.3 dbm 01000 -1.4 dbm 01001 -1.5 dbm 01010 -1.7 dbm 01011 -2.0 dbm 01100 -2.2 dbm 01101 -2.4 dbm 01110 -2.6 dbm 01111 -2.8 dbm 10000 -3.1 dbm 10001 -3.3 dbm 10010 -3.6 dbm 10011 -3.8 dbm 10100 -4.2 dbm 10101 -4.4 dbm 10110 -4.7 dbm 10111 -5.0 dbm
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 79 march 15, 2010 tx output power register control lreg0x253 [3:0] lreg0x274 [7:0] lreg0x203 [7:3] tx output power 00 c6 for dc-dc off 11000 -5.3 dbm 11001 -5.7 dbm 11010 -6.2 dbm 11011 -6.5 dbm 11100 -6.9 dbm 11101 -7.4 dbm 11110 -7.9 dbm 11111 -8.3 dbm 0c 81 11111 -16 dbm 0c 09 11111 -24 dbm 09 01 11111 -32 dbm 08 01 11111 -40 dbm bit 2~0 reserved: maintain as 0b000  lreg0x204 - rfctrl4: rf control register 4 bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name  rxfco rxd2o1 rxd2o0 type rrrrrr/wr/w r\/w por00000000 bit 7~3 reserved: maintain as 0b00000 bit 2 rxfco : rx filter calibration output 1: (optimized - do not change) 0: (default) bit 1~0 rxd2o [1:0] : rx divide-by-2 option 00: (default) 10: (optimized - do not change)  lreg0x205 - rfctrl5: rf control register 5 bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name batth3 batth2 batth1 batth0  type r/w r/w r/w r/w rrrr por00000000 bit 7~4 batth [3:0 ]: battery monitor threshold. 0000: 1.8v (default) 0001: 1.9v 0010: 2.0v 0011: 2.1v 0100: 2.2v 0101: 2.3v 0110: 2.4v 0111: 2.5v 1000: 2.6v 1001: 2.7v 1010: 2.8v 1011: 2.9v 1100: 3.0v 1101: 3.3v 1110: 3.4v 1111: 3.6v bit 3~0 reserved: maintain as 0b0000
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 80 march 15, 2010  lreg0x206 - rfctrl6: rf control register 6 bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name txfbw1 txfbw0 32mxco1 32mxco0 baten  type r/w r/w r/w r/w r/w r r r por11110000 bit 7~6 txfbw [1:0 ]: tx filter 00: optimized for 250k bps normal mode 11: optimized for 1m bps turbo mode bit 5~4 32mxco [1:0] : 32mhz crystal oscillator 00: (optimized - do not change) 11: (default) bit 3 baten : battery monitor enable 1: enable 0: disable (default) bit 2~0 reserved: maintain as 0b000  lreg0x207 - rfctrl7: rf control register 7 bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name  rxfc2  type r r r r/w rrrr por00000000 bit 7~5 reserved: maintain as 0b000 bit 4 rxfc2 : rx filter control 2 1: for 1m bps turbo mode 0: for 250k bps normal mode (default) bit 3~0 reserved: maintain as 0b0000  lreg0x208 - rfctrl8: rf control register 8 bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name txd2co1 txd2co0  type r/w r/w rrrrrr por00001100 bit 7~6 txd2co [1:0 ]: tx divide-by-2 option 00: (default) 10: (optimized - do not change) bit 5~0 reserved: maintain as 0b001100  lreg0x209 - slpcal_0: sleep clock calibration 0 bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name slpcal7 slpcal6 slpcal5 slpcal4 slpcal3 slpcal2 slpcal1 slpcal0 type r/w r/w r/w r/w r/w r/w r/w r/w p o r00000000 bit 7~0 slpcal [7:0] : sleep clock calibration counter bit 7~0 a 20-bit calibration counter which calibrates the sleep clock. slpcal [19:0] indicates the time period of 16 sleep clock cycles. the unit is 62.5ns, counted by the 16mhz.
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 81 march 15, 2010  lreg0x20a - slpcal_1: sleep clock calibration 1 bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name slpcal15 slpcal14 slpcal13 slpcal12 slpcal11 slpcal10 slpcal9 slpcal8 type r/w r/w r/w r/w r/w r/w r/w r/w p o r00000000 bit 7-0 slpcal [15:8] : sleep clock calibration counter bit 15~8 a 20-bit calibration counter which calibrates the sleep clock. slpcal [19:0] indicates the time period of 16 sleep clock cycles. the unit is 62.5ns, counted by the 16mhz.  lreg0x20b - slpcal_2: sleep clock calibration 2 bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name slpcalrdy  slpcalen slpcal19 slpcal18 slpcal17 slpcal16 type r r r wt r/w r/w r/w r/w por00000000 bit 7 slpcalrdy : sleep clock calibration ready 1: sleep clock calibration counter is ready to be read. 0: not ready (default) bit 6-5 reserved: maintain as 0b00 bit 4 slpcalen : sleep clock calibration enable 1: starts the sleep clock calibration counter. bit is automatically cleared to 0 by hardware bit 3-0 slpcal [19:16 ]: sleep clock calibration counter bit 19~16 a 20-bit calibration counter which calibrates the sleep clock. slpcal [19:0] indicates the time period of 16 sleep clock cycles. the unit is 62.5ns, counted by the 16mhz.  lreg0x211 - irqctrl: interrupt control register bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name  irqpol  type rrrrrrr/wr por00000000 bit 7~2 reserved: maintain as 0b000000 bit 1 irqpol : interrupt edge polarity 1: rising edge 0: falling edge (default) bit 0 reserved: maintain as 0b0
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 82 march 15, 2010  lreg0x22f - testmode: test mode register bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name mspi  testmode2 testmode1 testmode0 type r/w rrrr r/w r/w r/w por 0 0101 0 0 0 bit 7 mspi : multiple spi operation 1: enable multiple spi operation, so will be high-z state when spi inactive 0: single spi operation, so will be low when spi inactive (default) bit 6-3 reserved: maintain as 0b0101 bit 2-0 testmode [2:0 ]: special operation 000: (default) normal operation 001: gpio0, gpio1 and gpio2 are configured to control the external p.a., lna and rf switch 101: single-tone test mode others: undefined.  lreg0x23d - gpiodir: gpio pin direction bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name  gdirctrl2 gdirctrl1 gdirctrl0 gpio2dir gpio1dir gpio0dir type r r r/w r/w r/w r/w r/w r/w por00111111 bit 7-6 reserved: maintain as 0b00 bit 5-3 gdirctrl [2:0 ]: gpio direction control 000: (optimized - do not change) 111: (default) bit 2 gpio2dir : general purpose i/o gpio2 direction 1: input (default) 0: output bit 1 gpio1dir : general purpose i/o gpio1 direction 1: input (default) 0: output bit 0 gpio0dir : general purpose i/o gpio0 direction 1: input (default) 0: output  lreg0x23e - gpio: gpio bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name  gpio2 gpio1 gpio0 type r r r r r r/w r/w r/w por00000 0 0 0 bit 7~3 reserved: maintain as 0b00000 bit 2 gpio2 : setting for output/status for input of general purpose i/o pin gpio2 0: (default) bit 1 gpio1 : setting for output/status for input of general purpose i/o pin gpio1 0: (default) bit 0 gpio0 : setting for output/status for input of general purpose i/o pin gpio0 0: (default)
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 83 march 15, 2010  lreg0x250 - rfctrl50: rf control register 50 bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name  dcpoc dcopc3 dcopc2 dcopc1 dcopc0 type r r r r/w r/w r/w r/w r/w por00000000 bit 7~5 reserved: maintain as 0b000 bit 4 dcpoc : dc-dc converter power control 1: enable 0: bypass (default) bit 3~0 dcopc [3:0] : dc-dc converter optimization control 0000: (default) 0111: (optimized - do not change)  lreg0x251 - rfctrl51: rf control register 51 bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name dcopc5 dcopc4  type r/w r/w r/w r/w rrrr por00000000 bit 7~6 dcopc [5:4 ]: dc-dc converter optimization control 00: (default) 11: (optimized - do not change) bit 5~0 reserved: maintain as 0b000000  lreg0x252 - rfctrl52: rf control register 52 bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name slctrl6 slctrl5 slctrl4 slctrl3 slctrl2 slctrl1 slctrl0 32mxctrl type r/w r/w r/w r/w r/w r/w r/w r/w p o r11111111 bit 7~1 slctrl [6:0 ]: sleep clock control 0000000: (optimized - do not change) 1111111: (default) bit 0 32mxctrl : start-up circuit in 32mhz crystal oscillator control 1: enable (default) 0: disable
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 84 march 15, 2010  lreg0x253 - rfctrl53: rf control register 53 bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name  fifops digitalps p32mxe pacen2 pactrl2-2 pactrl2-1 pactrl2-0 type r/w r/w r/w r/w rrrr por00000000 bit 7 reserved: maintain as 0b0 bit 6 fifops : fifo power while the rf transceiver is in power saving mode 1: gnd 0: vdd (default) bit 5 digitalps : digital power while sleep 1: gnd 0: vdd (default) bit 4 p32mxe : partial 32mhz clock enable 1: enable 0: disable (default) bit 3 pacen2 : power amplifier control 2 enable 1: enable 0: disable (default) bit 2~0 pactrl2-[2:0 ]: power amplifier control 2 000: (default) pactrl2 [2:0] is for 1st stage power amplifier current fine tuning. please follow the tx output power configuration summary table in lreg0x203 register definition.
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 85 march 15, 2010  lreg0x254 - rfctrl54: rf control register 54 bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name 1mcsen 1mcsch6 1mcsch5 1mcsch4 1mcsch3 1mcsch2 1mcsch1 1mcsch0 type r/w r/w r/w r/w r/w r/w r/w r/w p o r00000000 bit 7 1mcsen : 1 mhz channel spacing enable 1: enable. when lreg0x254 [7] = 1, rf channel can only be selected by lreg0x254 [6:0] and the setting of lreg0x200 [7:4] will not change the channel number at all. 0: disable (default) bit 6~0 1mcsch [6:0 ]: 1 mhz channel spacing channel number lreg0x254 [6:0] only works when lreg0x254 [7] = 1. 0000000: 2400 mhz 0000001: 2401 mhz 0000010: 2402 mhz 0000011: 2403 mhz 0000100: 2404 mhz 0000101: 2405 mhz 0000110: 2406 mhz 0000111: 2407 mhz 0001000: 2408 mhz 0001001: 2409 mhz 0001010: 2410 mhz 0001011: 2411 mhz 0001100: 2412 mhz 0001101: 2413 mhz 0001110: 2414 mhz 0001111: 2415 mhz 0010000: 2416 mhz 0010001: 2417 mhz 0010010: 2418 mhz 0010011: 2419 mhz 0010100: 2420 mhz 0010101: 2421 mhz 0010110: 2422 mhz 0010111: 2423 mhz 0011000: 2424 mhz 0011001: 2425 mhz 0011010: 2426 mhz 0011011: 2427 mhz 0011100: 2428 mhz 0011101: 2429 mhz 0011110: 2430 mhz 0011111: 2431 mhz 0100000: 2432 mhz 0100001: 2433 mhz 0100010: 2434 mhz 0100011: 2435 mhz 0100100: 2436 mhz 0100101: 2437 mhz 0100110: 2438 mhz 0100111: 2439 mhz 0101000: 2440 mhz 0101001: 2441 mhz 0101010: 2442 mhz 0101011: 2443 mhz 0101100: 2444 mhz 0101101: 2445 mhz 0101110: 2446 mhz 0101111: 2447 mhz 0110000: 2448 mhz 0110001: 2449 mhz 0110010: 2450 mhz 0110011: 2451 mhz 0110100: 2452 mhz 0110101: 2453 mhz 0110110: 2454 mhz 0110111: 2455 mhz 0111000: 2456 mhz 0111001: 2457 mhz 0111010: 2458 mhz 0111011: 2459 mhz 0111100: 2460 mhz 0111101: 2461 mhz 0111110: 2462 mhz 0111111: 2463 mhz 1000000: 2464 mhz 1000001: 2465 mhz 1000010: 2466 mhz 1000011: 2467 mhz 1000100: 2468 mhz 1000101: 2469 mhz 1000110: 2470 mhz 1000111: 2471 mhz 1001000: 2472 mhz 1001001: 2473 mhz 1001010: 2474 mhz 1001011: 2475 mhz 1001100: 2476 mhz 1001101: 2477 mhz 1001110: 2478 mhz 1001111: 2479 mhz 1010000: 2480 mhz 1010001: 2481 mhz 1010010: 2482 mhz 1010011: 2483 mhz 1010100: 2484 mhz 1010101: 2485 mhz 1010110: 2486 mhz 1010111: 2487 mhz 1011000: 2488 mhz 1011001: 2489 mhz 1011010: 2490 mhz 1011011: 2491 mhz 1011100: 2492 mhz 1011101: 2493 mhz 1011110: 2494 mhz 1011111: 2495 mhz 1100000: undefined : 1111111: undefined
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 86 march 15, 2010  lreg0x259 - rfctrl59: rf control register 59 bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name  pllopt3 type rrrrrrrr por00000000 bit 7~1 reserved: maintain as 0b0000000 bit 0 pllopt3 : pll performance optimization 1: (default) 0: (optimized - do not change)  lreg0x273 - rfctrl73: rf control register 73 bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name vcotxopt1 vcotxopt0  pllopt2 pllopt1 pllopt0  type r/w r/w r r r/w r/w r/w r por0 0 000000 bit 7~6 vcotxopt [1:0 ]: vco for tx optimization 00: (default) 01: (optimized - do not change) bit 5~4 reserved: maintain as 0b00 bit 3~1 pllopt [2:0 ]: pll performance optimization 000: (default) 111: optimized for dc-dc converter bypass bit 0 reserved: maintain as 0b0  lreg0x274 - rfctrl74: rf control register 74 bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name pac0en pactrl0-2 pactrl0-1 pactrl0-0 pac1en pactrl1-2 pactrl1-1 pactrl1-0 type r/w r/w r/w r/w r/w r/w r/w r/w p o r11001010 bit 7 pac0en : power amplifier control 0 enable 1: enable (default) 0: disable bit 6~4 pactrl0 [2:0 ]: power amplifier control 0 100: (default) pactrl0 [2:0] is for 1st stage power amplifier current large scale control. bit 3 pac1en : power amplifier control 1 enable 1: enable (default) 0: disable bit 2-0 pactrl1 [2:0 ]: power amplifier control 1 100: optimized for dc-dc on 110: optimized for dc-dc off 010: (default) pactrl1 [2:0] is for 2nd stage power amplifier current control. please follow the tx output power configuration summary table in lreg0x203 register definition.
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 87 march 15, 2010  lreg0x275 - rfctrl75: rf control register 75 bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name  sclkopt3 sclkopt2 sclkopt1 sclkopt0 type r r r r r/w r/w r/w r/w por00010101 bit 7~4 reserved: maintain as 0b0001 bit 3~0 sclkopt [3:0 ]: sleep clock optimization 0011: (optimized - do not change) 0101: (default)  lreg0x276 - rfctrl76: rf control register 76 bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name  sclkopt6 sclkopt5 sclkopt4 type r r r r r r/w r/w r/w por00000 0 0 1 bit 7~3 reserved: maintain as 0b00000 bit 2~0 sclkopt [6:4 ]: sleep clock optimization 111: (optimized - do not change) 001: (default)  lreg0x277 - rfctrl77: rf control register 77 bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name  slpsel1 slpsel0 slpvctrl1 slpvctrl0 slpvsel1 slpvsel0 type r r r/w r/w r/w r/w r/w r/w por0000 1 0 00 bit 7~6 reserved: maintain as 0b00 bit 5~4 slpsel [1:0 ]: power saving mode selection 00: (default) standby / deep sleep mode 01: undefined 10: undefined 11: power down mode bit 3~2 slpvctrl [1:0 ]: sleep voltage control 00: undefined 01: controlled by lreg0x27 [1:0] 10: (default) automatically controlled by internal circuit 11: undefined bit 1~0 slpvsel [1:0 ]: sleep voltage selection 00: (default - no not change)
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 88 march 15, 2010 rf transceiver power-down and wake-up the mcu and rf transceiver are powered down independently of each other. the method of powering down the mcu is covered in the previous mcu section of the datasheet. the rf transceiver must be powered down before the mcu is powered down. the method of powering down the rf transceiver is mentioned in the previous power saving mode section of this datasheet. for a rf transceiver interrupt to occur, in addition to the bits for the related enable and interrupt polarity control de - scribed in rf transceiver interrupt configuration section being set, the global interrupt enable control and the related interrupt enable control bits in host mcu must also be set. if the bits related to the interrupt function are configured properly, the rf transceiver will generate an interrupt signal on int pin connected to the mcu i/o pin to get the atten - tions from mcu and then the interrupt subroutine will be serviced. if the related interrupt control bits in host mcu are not set properly, then the interrupt signal on rf transceiver int line will be a wake-up signal and no interrupt will be serviced. using the rf transceiver function to use the rf transceiver function, several important steps must be implemented to ensure that the rf transceiver operates normally:  the host mcu must be configured as the master spi. therefore, the mcu spi mode selection bits [m1, m0] in spi interface control register can not be set to [1, 1] as slave mode.  although the spi mode selection bits [m1, m0] can be set to [0, 0], [0, 1] and [1, 0], along with the spi clock source selection bit cks, to force the host mcu spi interface to operate as master spi with different baud rate, there are some limitations on the maximum spi clock speed that can be selected to be suitable for the rf transceiver slave spi clock speed. as the maximum rf transceiver slave spi clock frequency is 5mhz, care must be taken for the combinations of the spi clock source selection cks and mode selection [m1, m0] when the system clock fre - quency is greater than 5mhz. for example, if the system clock operates at a frequency of 6mhz, the spi mode se - lection [m1, m0] and clock source selection cks should not be set to [0, 0] and 0. doing so will obtain a master spi baud rate of 6mhz that is greater than the maximum clock frequency of the slave spi which may result in spi inter- face malfunction. spi master/slave/baud rate selection bits in sbcr register bit bit 6 bit 5 name m1 m0 value 00, 01, 10 00: spi master mode; baud rate is f spi 01: spi master mode; baud rate is f spi /4 10: spi master mode; baud rate is f spi /16 11: spi slave mode  can not be used spi clock source selection bit in sbcr register bit bit 7 name cks value 0, 1 0: f spi =f sys /2 1: f spi =f sys  since the msb is first shifted in on si line and shifted out on so line for the rf transceiver slave spi read/write oper - ations, the msb/lsb selection bit mls in mcu master spi sbcr register should be set to 1 for msb shift first on sdi/sdo lines. spi msb/lsb first selection bit in sbcr register bit bit 5 name mls setting value 1
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 89 march 15, 2010  as the rf transceiver slave spi timing diagram shows, the spi data output mode selection spi_mode and the clock polarity selection spi_cpol of the master spi should be correctly set to fit the slave spi protocol requirement. to successfully communicate with the rf transceiver slave spi, the spi_mode and spi_cpol of the mcu master spi should be set to [1, 1]. spi_mode and spi_cpol setup in spir register bit bit 1 bit 0 name spi_mode spi_cpol setting value 1 1 the relevant timing diagram for the above setting is shown in the preceding spi bus timing diagram in spi serial interface section.  for the mcu master spi to completely control the slave spi sen line, the mcu master spi uses a general purpose i/o line via application program instead of the spi scs line with hardware mechanism. to achieve this requirement, the software csen enable control bit spi_csen of the master spi should be set to 0, then the master spi scs line will lose the scs line characteristics and be configured as a general purpose i/o line. spi_csen software csen enable control bit in spir register bit bit 5 name spi_csen setting value 0 0: the software csen function is disabled and the scs line is configured as an i/o line  finally set the spi_en bit to 1 to ensure that the pin-shared function for other three spi lines known as sck, sdi and sdo are surely selected. spi_en software spi interface lines enable control bit in spir register bit bit 5 name spi_en setting value 1 1: the pin-shared function of the spi interface lines is enabled. after the above setup conditions have been implemented, the mcu can enable the spi interface by setting the sben bit high. the mcu can then begin communication with the rf transceiver using the spi interface. the de- tailed mcu master spi functional description is provided within the spi serial interface section of the mcu datasheet.
application circuits with rf transceiver HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 90 march 15, 2010 HT82M75Rew 1 2 3 4 5 6 7 8 9 10 14 15 16 17 18 19 20 36 37 38 39 40 31 32 33 34 35 26 27 28 29 30 21 22 23 24 25 11 12 13 vdd_3v vdd_3v 100k 0.1uf 0.1uf 47uf 47uf vdd_3v 0.1uf 100uh 0.1uf vb vdd_3v vdd_bg vdd_gr xtal_n xtal_p vdd_pll vdd_cp vdd_vco loop_c vdd_rf1 rf_n nc vdd_rf2 pb1 pb2 pb3 pb4 pa0 pa1 pa2 pa3 pa4 pa5 vss vdd vdd bat_in lx res pa7 pa6 pb7 pb6 pb5 gpio2 gpio1 gpio0 vdd_d vdd_2v2 vdd_a vsslx 10nf vcc_3v 47uf bead 15pf 32m 15pf vcc_3v 4.7uf 47pf 10nf 10nf 1uf 47pf vcc_3v 47pf 47pf 10nf 6.8nh 4.7nh 5.6nh 0.47pf 0.47pf ant 1pf 1.2nh rf_p
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 91 march 15, 2010 ht82k75rew 1 2 3 4 5 6 7 8 9 10 11 12 13 20 21 22 23 24 25 26 27 28 60 61 62 63 64 29 30 31 32 52 53 54 55 56 57 58 59 14 15 16 43 44 45 46 47 48 36 37 38 39 40 41 42 33 34 35 17 18 19 49 50 51 pa6 pa7 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 gpio2 gnd_d gpio1 gpio0 vdd_d vdd_2v2 vdd_3v vdd_gr / vdd_bg vdd_a db4 xtal_n xtal_p gnd_pll vdd_pll vdd_cp vdd_vco db5 db5 loop_c vdd_rf1 n.c. rf_p rf_n n.c. vdd_rf2 pc1 pc0 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 lx vsslx bat_in vss vdd res pa0 pa1 pa2 / tmr pa3 pa4 pa5 vdd_3v vdd_3v 100k 0.1uf 0.1uf 47uf 220uf vdd_3v vcc_3v 10nf 0.1uf vcc_3v 0.1uf vcc_3v 4.7uf vcc_3v 0.1uf vcc_3v 47pf 10nf 47pf 15pf 15pf 10nf 1uf 47pf vcc_3v vcc_3v 47pf 10nf 6.8nh 5.6nh 6.8nh 0.5pf 0.5pf 100uh 0.1uf ant 32m 0.5pf 1.8pf 1.2nh vdd_3v bead vb
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 92 march 15, 2010 instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of pro - gram instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of pro - gramming overheads. for easier understanding of the various instruction codes, they have been subdivided into several func - tional groupings. instruction timing most instructions are implemented within one instruc - tion cycle. the exceptions to this are branch, call, or ta - ble read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5
s and branch or call instructions would be im - plemented within 1
s. although instructions which re - quire one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instruc- tions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to imple- ment. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instruc- tions would be clr pcl or mov pcl, a . for the case of skip instructions, it must be noted that if the re- sult of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specific imme - diate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to en - sure correct handling of carry and borrow data when re - sults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on pro - gram requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specified locations using the jmp instruction or to a sub- routine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the sub - routine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made re - garding the condition of a certain data memory or indi - vidual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the pro - gram perhaps determined by the condition of certain in - put switches or by the condition of internal data bits.
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 93 march 15, 2010 bit operations the ability to provide single bit operations on data mem - ory is an extremely flexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively. the fea - ture removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write pro - cess is taken care of automatically when these bit oper - ation instructions are used. table read operations data storage is normally implemented by using regis - ters. however, when working with large amounts of fixed data, the volume involved often makes it inconve - nient to store the fixed data in the data memory. to over - come this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instruc - tions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the halt in - struction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electro - magnetic environments. for their relevant operations, refer to the functional related sections. instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be con - sulted as a basic instruction reference using the follow - ing listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from the acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry, result in data memory decimal adjust acc for addition with result in data memory 1 1 note 1 1 1 note 1 1 1 note 1 1 note 1 note z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] logical and data memory to acc logical or data memory to acc logical xor data memory to acc logical and acc to data memory logical or acc to data memory logical xor acc to data memory logical and immediate data to acc logical or immediate data to acc logical xor immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 note 1 note 1 note 1 1 1 1 note 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 note 1 1 note z z z z
HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 94 march 15, 2010 mnemonic description cycles flag affected rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 note 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 note 1 note none none branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read table (current page) to tblh and data memory read table (last page) to tblh and data memory 2 note 2 note none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 note 1 note 1 1 1 1 note 1 1 none none none to, pdf to, pdf to, pdf none none to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both clr wdt1 and clr wdt2 instructions are consecutively executed. otherwise the to and pdf flags remain unchanged.
instruction definition adc a,[m] add data memory to acc with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the accumulator. operation acc  acc+[m]+c affected flag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the specified data memory. operation [m]  acc+[m]+c affected flag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc  acc + [m] affected flag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specified immediate data are added. the result is stored in the accumulator. operation acc  acc+x affected flag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the specified data memory. operation [m]  acc + [m] affected flag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical and op - eration. the result is stored in the accumulator. operation acc  acc and [m] affected flag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical and operation. the result is stored in the accumulator. operation acc  acc and x affected flag(s) z andm a,[m] logical and acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical and op - eration. the result is stored in the data memory. operation [m]  acc and [m] affected flag(s) z HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 95 march 15, 2010
call addr subroutine call description unconditionally calls a subroutine at the specified address. the program counter then in - crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specified address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cycle instruc - tion. operation stack  program counter + 1 program counter  addr affected flag(s) none clr [m] clear data memory description each bit of the specified data memory is cleared to 0. operation [m]  00h affected flag(s) none clr [m].i clear bit of data memory description bit i of the specified data memory is cleared to 0. operation [m].i  0 affected flag(s) none clr wdt clear watchdog timer description the to, pdf flags and the wdt are all cleared. operation wdt cleared to  0 pdf  0 affected flag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc- tion with clr wdt2 and must be executed alternately with clr wdt2 to have effect. re- petitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to  0 pdf  0 affected flag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc - tion with clr wdt1 and must be executed alternately with clr wdt1 to have effect. re - petitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to  0 pdf  0 affected flag(s) to, pdf HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 96 march 15, 2010
cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. operation [m]  [m] affected flag(s) z cpla [m] complement data memory with result in acc description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc  [m] affected flag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd ( binary coded decimal) value re - sulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac flag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c flag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by add - ing 00h, 06h, 60h or 66h depending on the accumulator and flag conditions. only the c flag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m]  acc + 00h or [m]  acc + 06h or [m]  acc + 60h or [m]  acc + 66h affected flag(s) c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m]  [m]  1 affected flag(s) z deca [m] decrement data memory with result in acc description data in the specified data memory is decremented by 1. the result is stored in the accu - mulator. the contents of the data memory remain unchanged. operation acc  [m]  1 affected flag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the contents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down flag pdf is set and the wdt time-out flag to is cleared. operation to  0 pdf  1 affected flag(s) to, pdf HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 97 march 15, 2010
inc [m] increment data memory description data in the specified data memory is incremented by 1. operation [m]  [m]+1 affected flag(s) z inca [m] increment data memory with result in acc description data in the specified data memory is incremented by 1. the result is stored in the accumu - lator. the contents of the data memory remain unchanged. operation acc  [m]+1 affected flag(s) z jmp addr jump unconditionally description the contents of the program counter are replaced with the specified address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter  addr affected flag(s) none mov a,[m] move data memory to acc description the contents of the specified data memory are copied to the accumulator. operation acc  [m] affected flag(s) none mov a,x move immediate data to acc description the immediate data specified is loaded into the accumulator. operation acc  x affected flag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specified data memory. operation [m]  acc affected flag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected flag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical or oper - ation. the result is stored in the accumulator. operation acc  acc or [m] affected flag(s) z HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 98 march 15, 2010
or a,x logical or immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical or op - eration. the result is stored in the accumulator. operation acc  acc or x affected flag(s) z orm a,[m] logical or acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical or oper - ation. the result is stored in the data memory. operation [m]  acc or [m] affected flag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the re - stored address. operation program counter  stack affected flag(s) none ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specified immediate data. program execution continues at the restored address. operation program counter  stack acc  x affected flag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by set- ting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pending when the reti instruction is executed, the pending interrupt routine will be processed be- fore returning to the main program. operation program counter  stack emi  1 affected flag(s) none rl [m] rotate data memory left description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1)  [m].i; (i = 0~6) [m].0  [m].7 affected flag(s) none rla [m] rotate data memory left with result in acc description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory re - main unchanged. operation acc.(i+1)  [m].i; (i = 0~6) acc.0  [m].7 affected flag(s) none HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 99 march 15, 2010
rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0. operation [m].(i+1)  [m].i; (i = 0~6) [m].0  c c  [m].7 affected flag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1)  [m].i; (i = 0~6) acc.0  c c  [m].7 affected flag(s) c rr [m] rotate data memory right description the contents of the specified data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i  [m].(i+1); (i = 0~6) [m].7  [m].0 affected flag(s) none rra [m] rotate data memory right with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit with bit 0 ro- tated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i  [m].(i+1); (i = 0~6) acc.7  [m].0 affected flag(s) none rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry flag is rotated into bit 7. operation [m].i  [m].(i+1); (i = 0~6) [m].7  c c  [m].0 affected flag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit. bit 0 re - places the carry bit and the original carry flag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i  [m].(i+1); (i = 0~6) acc.7  c c  [m].0 affected flag(s) c HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 100 march 15, 2010
sbc a,[m] subtract data memory from acc with carry description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc  acc  [m]  c affected flag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the data memory. note that if the re - sult of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m]  acc  [m]  c affected flag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are first decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m]  [m]  1 skip if [m] = 0 affected flag(s) none sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specified data memory are first decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in- struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc  [m]  1 skip if acc = 0 affected flag(s) none set [m] set data memory description each bit of the specified data memory is set to 1. operation [m]  ffh affected flag(s) none set [m].i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i  1 affected flag(s) none HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 101 march 15, 2010
siz [m] skip if increment data memory is 0 description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m]  [m]+1 skip if [m] = 0 affected flag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in - struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc  [m]+1 skip if acc = 0 affected flag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specified data memory is not 0, the following instruction is skipped. as this re - quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i  0 affected flag(s) none sub a,[m] subtract data memory from acc description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc  acc  [m] affected flag(s) ov, z, ac, c subm a,[m] subtract data memory from acc with result in data memory description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m]  acc  [m] affected flag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specified by the code is subtracted from the contents of the accumu - lator. the result is stored in the accumulator. note that if the result of subtraction is nega - tive, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc  acc  x affected flag(s) ov, z, ac, c HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 102 march 15, 2010
swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specified data memory are interchanged. operation [m].3~[m].0  [m].7 ~ [m].4 affected flag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specified data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3 ~ acc.0  [m].7 ~ [m].4 acc.7 ~ acc.4  [m].3 ~ [m].0 affected flag(s) none sz [m] skip if data memory is 0 description if the contents of the specified data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruc - tion. operation skip if [m] = 0 affected flag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specified data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruc - tion while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc  [m] skip if [m] = 0 affected flag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specified data memory is 0, the following instruction is skipped. as this re- quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i = 0 affected flag(s) none tabrdc [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m]  program code (low byte) tblh  program code (high byte) affected flag(s) none tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m]  program code (low byte) tblh  program code (high byte) affected flag(s) none HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 103 march 15, 2010
xor a,[m] logical xor data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical xor op - eration. the result is stored in the accumulator. operation acc  acc xor [m] affected flag(s) z xorm a,[m] logical xor acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical xor op - eration. the result is stored in the data memory. operation [m]  acc xor [m] affected flag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc  acc xor x affected flag(s) z HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 104 march 15, 2010
package information 20-pin sop (300mil) outline dimensions  ms-013 symbol dimensions in inch min. nom. max. a 0.393  0.419 b 0.256  0.300 c 0.012  0.020 c 0.496  0.512 d  0.104 e  0.050  f 0.004  0.012 g 0.016  0.050 h 0.008  0.013  08 symbol dimensions in mm min. nom. max. a 9.98  10.64 b 6.50  7.62 c 0.30  0.51 c 12.60  13.00 d  2.64 e  1.27  f 0.10  0.30 g 0.41  1.27 h 0.20  0.33  08 HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 105 march 15, 2010 * /     /  1  ) ( m d @ 
20-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.228  0.244 b 0.150  0.158 c 0.008  0.012 c 0.335  0.347 d 0.049  0.065 e  0.025  f 0.004  0.010 g 0.015  0.050 h 0.007  0.010  08 symbol dimensions in mm min. nom. max. a 5.79  6.20 b 3.81  4.01 c 0.20  0.30 c 8.51  8.81 d 1.24  1.65 e  0.64  f 0.10  0.25 g 0.38  1.27 h 0.18  0.25  08 HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 106 march 15, 2010 * /     /  1  ) ( m d @ 
28-pin sop (300mil) outline dimensions  ms-013 symbol dimensions in inch min. nom. max. a 0.393  0.419 b 0.256  0.300 c 0.012  0.020 c 0.697  0.713 d  0.104 e  0.050  f 0.004  0.012 g 0.016  0.050 h 0.008  0.013  08 symbol dimensions in mm min. nom. max. a 9.98  10.64 b 6.50  7.62 c 0.30  0.51 c 17.70  18.11 d  2.64 e  1.27  f 0.10  0.30 g 0.41  1.27 h 0.20  0.33  08 HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 107 march 15, 2010 *    ,  -  1  ( m d @  )
28-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.228  0.244 b 0.150  0.157 c 0.008  0.012 c 0.386  0.394 d 0.054  0.060 e  0.025  f 0.004  0.010 g 0.022  0.028 h 0.007  0.010  08 symbol dimensions in mm min. nom. max. a 5.79  6.20 b 3.81  3.99 c 0.20  0.30 c 9.80  10.01 d 1.37  1.52 e  0.64  f 0.10  0.25 g 0.56  0.71 h 0.18  0.25  08 HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 108 march 15, 2010 *    ,  -  1  ( m d @  )
saw type 32-pin (5mm 5mm) qfn outline dimensions symbol dimensions in inch min. nom. max. a 0.028  0.031 a1 0.000  0.002 a3  0.008  b 0.007  0.012 d  0.197  e  0.197  e  0.020  d2 0.049  0.128 e2 0.049  0.128 l 0.012  0.020 k  symbol dimensions in mm min. nom. max. a 0.70  0.80 a1 0.00  0.05 a3  0.20  b 0.18  0.30 d  5.00  e  5.00  e  0.50  d2 1.25  3.25 e2 1.25  3.25 l 0.30  0.50 k  HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 109 march 15, 2010  )
    .   * 5 ) * 2   0    + * - * , . *
saw type 40-pin (6mm  6mm for 0.85mm) qfn outline dimensions  gtk symbol dimensions in inch min. nom. max. a 0.031 0.033 0.035 a1 0.000 0.001 0.002 a3  0.008  b 0.007 0.010 0.012 d  0.236  e  0.236  e  0.020  d2 0.173 0.177 0.179 e2 0.173 0.177 0.179 l 0.014 0.016 0.018 k 0.008  symbol dimensions in mm min. nom. max. a 0.80 0.85 0.90 a1 0.00 0.02 0.05 a3  0.20  b 0.18 0.25 0.30 d  6.00  e  6.00  e  0.50  d2 4.40 4.50 4.55 e2 4.40 4.50 4.55 l 0.35 0.40 0.45 k 0.20  HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 110 march 15, 2010  )
    .   * 5 ) * 2   /   * / *  . / .  - /
48-pin ssop (300mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.395  0.420 b 0.291  0.299 c 0.008  0.012 c 0.613  0.637 d 0.085  0.099 e  0.025  f 0.004  0.010 g 0.025  0.035 h 0.004  0.012  08 symbol dimensions in mm min. nom. max. a 10.03  10.67 b 7.39  7.59 c 0.20  0.30 c 15.57  16.18 d 2.16  2.51 e  0.64  f 0.10  0.25 g 0.64  0.89 h 0.10  0.30  08 HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 111 march 15, 2010 -   * , * -  1  ( m d @  )
64-pin lqfp (7mm  7mm) outline dimensions symbol dimensions in mm min. nom. max. a 8.90  9.10 b 6.90  7.10 c 8.90  9.10 d 6.90  7.10 e  0.40  f 0.13  0.23 g 1.35  1.45 h  1.60 i 0.05  0.15 j 0.45  0.75 k 0.09  0.20  07 symbol dimensions in inch min. nom. max. a 0.350  0.358 b 0.272  0.280 c 0.350  0.358 d 0.272  0.280 e  0.016  f 0.005  0.009 g 0.053  0.057 h  0.063 i 0.002  0.006 j 0.018  0.030 k 0.004  0.008  07 HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 112 march 15, 2010 -  - 0 . . . *  -     +  1  ) ( d @  n 2 
product tape and reel specifications reel dimensions sop 20w symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 24.8 +0.3/-0.2 t2 reel thickness 30.20.2 ssop 20s (150mil) symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 16.8 +0.3/-0.2 t2 reel thickness 22.20.2 HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 113 march 15, 2010  1    * 
sop 28w (300mil) symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 24.8 +0.3/-0.2 t2 reel thickness 30.20.2 ssop 28s (150mil) symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 16.8 +0.3/-0.2 t2 reel thickness 22.20.2 ssop 48w symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.00.1 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 32.2 +0.3/-0.2 t2 reel thickness 38.20.2 HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 114 march 15, 2010
carrier tape dimensions sop 20w symbol description dimensions in mm w carrier tape width 24.0 +0.3/-0.1 p cavity pitch 12.00.1 e perforation position 1.750.10 f cavity to perforation (width direction) 11.50.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 10.80.1 b0 cavity width 13.30.1 k0 cavity depth 3.20.1 t carrier tape thickness 0.300.05 c cover tape width 21.30.1 ssop 20s (150mil) symbol description dimensions in mm w carrier tape width 16.0 +0.3/-0.1 p cavity pitch 8.00.1 e perforation position 1.750.10 f cavity to perforation (width direction) 7.50.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 6.50.1 b0 cavity width 9.00.1 k0 cavity depth 2.30.1 t carrier tape thickness 0.300.05 c cover tape width 13.30.1 HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 115 march 15, 2010   $  /  ) (  2 / 1 /  /   "     
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sop 28w (300mil) symbol description dimensions in mm w carrier tape width 24.00.3 p cavity pitch 12.00.1 e perforation position 1.750.10 f cavity to perforation (width direction) 11.50.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 10.850.10 b0 cavity width 18.340.10 k0 cavity depth 2.970.10 t carrier tape thickness 0.350.01 c cover tape width 21.30.1 ssop 28s (150mil) symbol description dimensions in mm w carrier tape width 16.00.3 p cavity pitch 8.00.1 e perforation position 1.750.1 f cavity to perforation (width direction) 7.50.1 d perforation diameter 1.55 +0.10/-0.00 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 6.50.1 b0 cavity width 10.30.1 k0 cavity depth 2.10.1 t carrier tape thickness 0.300.05 c cover tape width 13.30.1 HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 116 march 15, 2010
carrier tape dimensions ssop 48w symbol description dimensions in mm w carrier tape width 32.00.3 p cavity pitch 16.00.1 e perforation position 1.750.10 f cavity to perforation (width direction) 14.20.1 d perforation diameter 2 min. d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 12.00.1 b0 cavity width 16.20.1 k1 cavity depth 2.40.1 k2 cavity depth 3.20.1 t carrier tape thickness 0.350.05 c cover tape width 25.50.1 HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 117 march 15, 2010    /  ) (  2 * 1 /  / $ 2    "     
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HT82M75R/HT82M75Re/HT82M75Rew ht82k75r/ht82k75re/ht82k75rew rev. 1.00 118 march 15, 2010 holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shenzhen sales office) 5f, unit a, productivity building, no.5 gaoxin m 2nd road, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538 tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com copyright  2010 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw.


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