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rev. 1.00 1 january 18, 2012 rev. 1.00 pb january 18, 2012 ht16523 5x7 dot character vfd controller & driver feature ? logic voltage: 2.7v~5.5v ? high voltage: 40v (max.) ? 3-line serial interface ? alphanumeric and symbolic display using integrated rom ? 16 x 8-bit display data ram (ddram) ? integrated 5x7 dot rom containing 248 character set ? 8 user-defned characters stored in character generator ram (cgram) ? additional s ymbol display data stored in 16 x 8-bit ram (adram) ? display content: 16 columns by 1 row + 32 symbols - each column has 1 digit character with 2 symbols ? supports display output: 35-segment & 16-grid ? supports symbol output: 2-symbol & 16-grid ? supports 2 -pin g eneral o utput p ort - static o peration ? fully integrated oscillator circuit ? 64-pin lqfp package applications ? consumer products panel function control ? industrial measuring instrument panel function control ? other similar application panel function control ? suitable for pos terminals or message display s general description the ht16523 device is a dot matrix v acuum fluorescent display , vfd, controller/driver which displays c haracters, num eric s a nd sym bols. dot matrix vfd driving signals are received via a 3-line serial interface driven by an externally connected microcontroller. the display data is stored in the internal rom and ram for character and symbol display. ordering information part number information ht16523-002 64-pin lqfp package with rom code 002 HT16523-003 64-pin lqfp package with rom code 003
rev. 1.00 2 january 18, 2012 ht16523 block diagram 8 bit shift register command decoder control circuit timing generator 1 oscillator timing generator 2 write address counter read address counter address selector duty control digit control ddram 16 w x 8b cgrom 248 w x 35 b cgram 8 w x 35 b adram 16 w x 2b segment driver ad driver port driver grid driver vdd vh vss rst cs sck si osci test g1 g 16 p1 p2 ad 1 ad 2 s1 s 35
rev. 1.00 3 january 18, 2012 ht16523 pin assignment ht16523 64 lqfp-a 1 2 3 4 5 6 7 8 9 10 11 12 13 202122232425 262728 6061626364 29303132 5253545556575859 14 15 16 43 44 45 46 47 48 36 37 38 39 40 41 42 33 34 35 17 1819 495051 g1 s35 s34 s33 s32 s31 s30 s29 s28 s27 s26 s25 s24 s23 s22 s21 vss osci test rst cs sck si vdd p1 p2 ad2 ad1 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 s16 s17 s18 s19 s20 vh g16 g15 g14 g13 g12 g11 g10 g9 g8 g7 g6 g5 g4 g3 g2 pin description pin name i/o description power supply pins vdd positive power supply for logic circuits. vh power supply for vfd driver circuits. vss vss - ground pin. microcontroller interface pins cs i chip select pin when low, the device is active. sck i serial clock input shift clock input with data written on the sck rising edge. si i serial data input. the serial data is frst shifted from lsb. rst i initialize all the internal registers and commands. all segments and digits are fxed at low level. test i when low or open, the device is in normal mode. when high, the device is in test mode. output pins s1~s35 o high-voltage segment output pins. g1~g16 o high-voltage grid output pins. ad1,ad2 o high-voltage additional data segment output pins. p1,p2 o general port output. static operation output - can drive leds oscillator pin osci i oscillator input pin connected to an external resistor and capacitor to generate the oscillation frequency.
rev. 1.00 4 january 18, 2012 ht16523 note: these are stress ratings only . stresses exceeding the range specifed under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those l isted i n t he sp ecifcation i s n ot i mplied a nd p rolonged e xposure t o e xtreme c onditions m ay a ffect device reliability. approximate internal connections s1~s35, g1~g16, ad1, ad2 test vdd vss cs, sck, si, rst (for schmit trigger type) vh vss vdd vss p1, p2 vdd vss absolute maximum ratings logic supply v oltage ............... vss-0.3v to vss+6.0v driver supply v oltage ............... vss-0.3v to vss+45v input v oltage . . . vss-0.3v to v dd +0.3v output v oltage ......................... vss-0.3v to v dd +0.3v grid output current ............................... -20ma to 4ma segment output current ........................ -10ma to 4ma ad output current ................................ -15ma to 4ma general port output current ................ -20ma to 40ma storage t emperature ........................... -55c to 125 c operation t emperature ......................... -40c to 85 c
rev. 1.00 5 january 18, 2012 ht16523 d.c. characteristics v h =40v, v ss =0v, ta=-40c ~ 85c symbol parameter test condition min. typ. max. unit v dd condition v dd logic supply voltage 2.7 5.0 5.5 v v h vfd supply voltage 10 40 v i dd1 vdd operating current 5v f osc =2mhz, no load, duty=15/16, digit=1 to 16. all output lights on, mcu no write data or command, p2 and p1=high 2 ma 3v 1 i dd2 vdd operating current 5v f osc =2mhz, no load, duty=15/16, digit=1 to 16. stop scan mcu no write data or command, p2 and p1=high 2 ma 3v 1 i stb vdd standby current 5v standby mode 2 10 a 3v 1 5 a i h1 vh operating current f osc =2mhz, no load, duty=15/16, digit=1 to 16, all output lights on, mcu no write data or command, p2 and p1=high 1 ma i h2 vh operating current f osc =2mhz, no load, duty=15/16, digit=1 to 16, stop scan mcu no write data or command, p2 and p1=high 20 a i h_stb vh standby current standby mode 20 a v ih high level input voltage 5v cs, sck, si, rst 0.8v dd v dd v 3v v il low level input voltage 5v cs, sck, si, rst 0 0.2v dd v 3v i ih high level input current 5v v ih =v dd , cs, sck, si, rst 1 a 3v i il low level input current 5v v il =0v, cs, sck, si, rst -1 a 3v v oh1 high level output voltage 5v g1~g16, i oh1 =-15ma 37 v 3v v oh2 5v ad1, ad2, i oh2 =-7ma 38 v 3v v oh3 5v s1~s35, i oh3 =-1ma 38 v 3v v oh4 5v p1, p2 i oh4 =-2ma 0.9v dd v 3v i oh4 =-1ma 0.9v dd v ol1 low level output voltage 5v g1~g16, i ol1 =1ma 2 v 3v v ol2 5v ad1, ad2, i ol2 =1ma 2 v 3v v ol3 5v s1~s35, i ol3 =1ma 2 v 3v v ol4 5v p1, p2 i ol4 =20ma 1 v 3v i ol4 =10ma 1 r pd pull down resistor 5v test pin 50 100 k 3v 100 200 k
rev. 1.00 6 january 18, 2012 ht16523 a.c. characteristics serial interface timing t cyc t l- sc k t h- sc k t start t stop t setup t hold t csh b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 1 st byte 1 st byte 2 nd byte b0 b1 b2 b3 b4 b5 b6 b7 3 rd byte cs sck si t dec t dec sck si cs
rev. 1.00 7 january 18, 2012 ht16523 output timing 0.8 vh 0.2 vh all outputs t r t f v h =40v, v ss =0v, ta =-40 o c ~ 85 o c symbol parameter test condition min. typ. max. unit v dd condition f osc oscillation frequency 5v r1=120 k, c1=0.1f 1.5 2 2.5 mhz 3v f fr frame frequency 5v digit=1 to 16, r1=120 k , c1=0.1f 183 244 305 hz 3v t cyc write cycle time 5v sck 2 mhz 3v 2 t l-sck low pulse of sck 5v sck 250 ns 3v 250 t h-sck high pulse of sck 5v sck 250 ns 3v 250 t setup data setup time 5v sck, si 250 ns 3v 250 t hold data hold time 5v sck, si 250 ns 3v 250 t start command start wait time 5v sck, si 250 ns 3v 250 t stop command stop wait time 5v sck, cs 16 s 3v 16 t csh cs off time 5v 250 ns 3v 250 t dec command/data decode time 5v 8 s 3v 8 t r all output slew rate 5v ci=100 pf, t r =20 to 80% 2 s 3v t f 5v ci=100 pf, t f =80 to 20% 2 s 3v
rev. 1.00 8 january 18, 2012 ht16523 reset and wake-up timing hardware reset vdd rst si t rson t rsoff t pof v ih v il v ih v il 0.8v dd 0v 0.5v dd t rw ta=-40 o c ~ 85 o c symbol parameter test condition min. typ. max. unit v dd condition t rson oscillator stable time 5v rst signal is an external input from a microcontroller etc. 250 ns 3v 250 5v r2=1k , c2=0.1f 1000 s 3v 1000 t pof vdd off time 5v vdd drop down to 0v 40 s 3v 10 ms t rw rst pulse width 5v rst signal is an external input from a microcontroller etc. 400 ns 3v 400 t rsoff si wait time 5v 3 s 3v 3 wake-up timing t wu t os sck si cs ta=-40 o c ~ 85 o c symbol parameter test condition min. typ. max. unit v dd condition t wu wake-up time 5v 200 ns 3v t os oscillation stable time 5v 1000 s 3v
rev. 1.00 9 january 18, 2012 ht16523 digit output timing for 16-digits display, at a duty of 15/16 blank timing t 3 =4 t (t 3 = 16 us when f osc =2 mhz ) display timing t 2 = 60 t (t 2 = 240 us when f osc =2 mhz ) frame cycle t 1 = 1024 t (t 1 = 4096 us when f osc =2 mhz ) g1 g2 g3 g4 g5 g6 g7 g8 g9 g 10 g 11 g 12 g 13 g 14 g 15 g 16 ad 1,2 s1~ 35 t=8/f osc
rev. 1.00 10 january 18, 2012 ht16523 segment and ad position positional relationship between s1~s35 and ad1 ~ ad2 - single digit c5 s6 cgram written data . corresponds to 2 nd byte (1 st column ) cgram written data . corresponds to 3 rd byte (2 nd column ) cgram written data . corresponds to 4 th byte (3 rd column ) cgram written data . corresponds to 5 th byte (4 th column ) cgram written data . corresponds to 6 th byte (5 th column ) c 10 s 11 c 15 s 16 c 20 s 21 c 30 s 31 c 25 s 26 c0 s1 c6 s7 c 11 s 12 c 16 s 17 c 21 s 22 c 31 s 32 c 26 s 27 c1 s2 c7 s8 c 12 s 13 c 17 s 18 c 22 s 23 c 32 s 33 c 27 s 28 c2 s3 c8 s9 c 13 s 14 c 18 s 19 c 23 s 24 c 33 s 34 c 28 s 29 c3 s4 c9 s 10 c 14 s 15 c 19 s 20 c 24 s 25 c 34 s 35 c 29 s 30 c4 s5 c 1 ad 2 c 0 ad 1 adram written data . corresponds to 2 nd byte .
rev. 1.00 11 january 18, 2012 ht16523 command table function byte r/w bit7 (msb) bit6 bit5 bit4 bit3 bit2 bit1 bit0 (lsb) note default ddram data write 1st w 0 0 0 * x3 x2 x1 x0 xn: address specifcation for each ram 00h ddram data 2nd w c7 c6 c5 c4 c3 c2 c1 c0 cn: character code specifcation for each ram cgram data write 1st w 0 0 1 * * x2 x1 x0 xn: address specifcation for each ram 20h cgram data 2nd w * c30 c25 c20 c15 c10 c5 c0 cn: character code specifcation for each ram cgram data 3rd w * c31 c26 c21 c16 c11 c6 c1 cgram data 4th w * c32 c27 c22 c17 c12 c7 c2 cgram data 5th w * c33 c28 c23 c18 c13 c8 c3 cgram data 6th w * c34 c29 c24 c19 c14 c9 c4 adram data write 1st w 0 1 0 * x3 x2 x1 x0 xn: address specifcation for each ram 40h adram data 2nd w * * * * * * c1 c0 cn: character code specifcation for each ram general output port set 1st w 0 1 1 * * * p2 p1 pn: general output port status specifcation 63h display duty set 1st w 1 0 0 * * d2 d1 d0 dn: display duty specifcation 80h number of digits set 1st w 1 0 1 * * k2 k1 k0 kn: number of digits specifcation a0h all lights on/off 1st w 1 1 0 * d s h l d: display on/off instruction s: standby mode instruction h: all lights on instruction l: all lights off instruction c0h test mode 1st w 1 1 1 0 0 0 0 0 for holtek internal testing e0h
rev. 1.00 12 january 18, 2012 ht16523 command and data transfer methods c omplete access to the vfd driver consist s of display command s and the display data. the number of transmitted data byte s for a complete access depends upon the command and memory type as the command table shows. the display control command s and data are t ransmitted using a 3 -wire se rial i nterface f rom the host mcu . the following steps show how the operation of the serial interface circuitry. ? setting the cs pin to a low level will enable a data transfer. ? data is 8-bit s wide and is sequential ly shifted-in on the si pin from lsb to msb (lsb frst) ? data s hifted into the regis ter is ready at the ris ing edge of the serial shift clock , sck. if the 8-bit data i s t o be wri tten i n, t he n i nternal si gnals a re automatically g enerated a nd t he d ata wi ll b e wr itten into the corresponding register and ram. ? setting the cs pin to high will disable the command and data transfer ? when data is written into the ram area includ ing ddram, adram and cgram continuously , the comma nd used to specify the ram area is contained in the first shifted-in command byte together with the start address. then the ram address will be internally incremented by 1 automatically. therefore, it is not necessary to specify the start address of the data to be written after the command byte. reset function when t he rst pi n i s se t t o low, t he m odule i s initialized to the following conditions: ? address will be reset to 00h for each ram includ ing ddram, adram and cgram ? the contents of the ram includ ing ddram, adram and cgram are undefned. ? all general output ports go high. ? display d uty se tting wi ll b e r eset t o 8 /16 d uty (register value d2, d1, d0=0, 0, 0). ? number of di gits se tting wi ll be re set t o 16 di gits (register value k2, k1, k0=0, 0, 0). ? all display lights on/off setting s will be switched to the display of f mode (register value d,s,h,l=0,0,0,0) ? all segment outputs go low. ? all ad outputs go low. ? all grid outputs go low. note: after a power on reset, all the ram, including ddram, adram and cgram, will be cleared. function al description timing generation circuit a t iming generation circuit generates timing signals for the operation of internal circuit s such as the ddram, cgram, cgrom and adram. vfd driver circuit the vfd driver circuit consists of 16 grid signal drivers and 35 segment signal drivers. when the number of di gits a re se lected by a corresponding command, the required grid signal drivers automatically o utput d rive wa veforms, wh ile t he o ther grid signal driver s continue to output non-selection waveforms. sending serial data is latched when the display data character pattern corresponds to the last address of the display data ram (ddram). data display ram - ddram the display data ram (ddram) stores the display data in 8-bit character codes. its extended capacity is 16x8 bits or 16 characters. ddram data write command byte r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 1st w 0 0 0 * x3 x2 x1 x0 2nd w c7 c6 c5 c4 c3 c2 c1 c0 3rd w c7 c6 c5 c4 c3 c2 c1 c0 4th w c7 c6 c5 c4 c3 c2 c1 c0 : : : : : : : : : : *: dont care the ddr am d ata wr ite c ommand d escriptions are shown in the following: ? x3~x0: ddram address is for 16 digits addressed from 00h to 0fh ? c7~c0: cha racter code of the cgrom ( internal 248 c haracters) or cgram (use r-defined 8 characters) ? to specify the character code of the cgrom or cgram continuously , only the character code needs to be specifed ? the addres ses of the d dram are automatically incremented by 1. ? the address will be wrapped around to the start address w hen the d dram data w rite function is successively executed and the ddram address is greater than the maximum available address
rev. 1.00 13 january 18, 2012 ht16523 ? grid positions and set ddram addresses hex x3 x2 x1 x0 grid position 0 0 0 0 0 g1 1 0 0 0 1 g2 2 0 0 1 0 g3 3 0 0 1 1 g4 4 0 1 0 0 g5 5 0 1 0 1 g6 6 0 1 1 0 g7 7 0 1 1 1 g8 8 1 0 0 0 g9 9 1 0 0 1 g10 a 1 0 1 0 g11 b 1 0 1 1 g12 c 1 1 0 0 g13 d 1 1 0 1 g14 e 1 1 1 0 g15 f 1 1 1 1 g16
rev. 1.00 14 january 18, 2012 ht16523 character generator rom (cgrom) ? the cgrom for generating character patterns of 5x7 dots from 8-bit character codes generates 248 types of character patterns ? the character codes are shown on the following page ? character codes 00h to 07h are allocated to the cgram character code table for rom code 002
rev. 1.00 15 january 18, 2012 ht16523 ram0 (cgram) ram1 (cgram) ram2 (cgram) ram3 (cgram) ram4 (cgram) ram5 (cgram) ram6 (cgram) ram7 (cgram) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 msb lsb character code table for rom code 003
rev. 1.00 16 january 18, 2012 ht16523 character generator ram (cgram) the cgram stores the pixel information (1=pixel on, 0=pixel of f) for the eight user -defined 5x7 characters. v alid cgram addresses are 00h to 07h. character codes 00h ~07h are as signed to the us er- defned characters. cgram data write command byte r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 1st w 0 0 1 * * x2 x1 x0 2nd w * c30 c25 c20 c15 c10 c5 c0 3rd w * c31 c26 c21 c16 c11 c6 c1 4th w * c32 c27 c22 c17 c12 c7 c2 5th w * c33 c28 c23 c18 c13 c8 c3 6th w * c34 c29 c24 c19 c14 c9 c4 *: dont care the cgram data write command descriptions are described by the following: ? x2~x0: cgram a ddresses for 8 use r-defined characters ? c34~c0: character pattern data, 35-bit outputs per digit. the relation ship between the 35-bit character pattern d ata a nd t he d ot p ositions f or e ach d igit is shown in the accompanying diagram ? a character pattern stored in the cgram can be displayed and addressed by the character code specifed in the ddram ? to specify character pattern data continuously, only the character pattern data needs to be specifed ? the a ddresses of the cgram a re a utomatically incremented by 1 ? the address will be wrapped around to the start address whe n t he cgram da ta wri te func tion i s successively e xecuted a nd t he c gram a ddress i s greater than the maximum available address ? cgrom addresses and set cgram addresses hex x2 x1 x0 cgram mapping to cgrom address 00 0 0 0 ram00 00000000b 01 0 0 1 ram01 00000001b 02 0 1 0 ram02 00000010b 03 0 1 1 ram03 00000011b 04 1 0 0 ram04 00000100b 05 1 0 1 ram05 00000101b 06 1 1 0 ram06 00000110b 07 1 1 1 ram07 00000111b ? relationship between the cgram output data and the character dot position c0 c5 c10 c15 c20 c25 c30 c1 c6 c11 c16 c21 c26 c31 c2 c7 c12 c17 c22 c27 c32 c3 c8 c13 c18 c23 c28 c33 c4 c9 c14 c19 c24 c29 c34 area that corresponds to 2nd byte (1st column) area that corresponds to 3rd byte (2nd column) area that corresponds to 4th byte (3rd column) area that corresponds to 5th byte (4th column) area that corresponds to 6th byte (5th column)
rev. 1.00 17 january 18, 2012 ht16523 additional symbol display ram (adram) the adram stores the additional symbol information (1=symbol on, 0=symbol of f) for the 16 digits. for each 5x7 digit there are two symbols displayed together with the character . the positional relationship is shown in the accompanying diagram. adram data write command byte r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 1st w 0 1 0 * x3 x2 x1 x0 2nd w * * * * * * c1 c0 3rd w * * * * * * c1 c0 4th w * * * * * * c1 c0 : : : : : : : : : : *: dont care the adram data write command descriptions are described by the following: ? x3~x0: adram addresses for 16 digits ? c1~c0: 2 bits symbol data for each digit ? symbol data specifed by the adram is directly output re gardless of t he cgram da ta a nd t he cgrom code ? the adram can store 2 types of symbol pattern for each digit ? the a dram contents output to the terminal can be used as a cursor for each digit ? the address of the adram is automatically incremented by 1 ? the address will be wrapped around to the start address whe n t he adram da ta wri te func tion i s successively e xecuted a nd t he adr am a ddress i s greater than the maximum available address ? grid positions and adram addresses hex x3 x2 x1 x0 grid position 0 0 0 0 0 g1 1 0 0 0 1 g2 2 0 0 1 0 g3 3 0 0 1 1 g4 4 0 1 0 0 g5 5 0 1 0 1 g6 6 0 1 1 0 g7 7 0 1 1 1 g8 8 1 0 0 0 g9 9 1 0 0 1 g10 a 1 0 1 0 g11 b 1 0 1 1 g12 c 1 1 0 0 g13 d 1 1 0 1 g14 e 1 1 1 0 g15 f 1 1 1 1 g16 general output port command byte r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 1st w 0 1 1 * * * p2 p1 *: dont care the ge neral out put port c ommand de scriptions are described by the following: ? p2, p1: general output port data ? the general output port supports 2-bit static output operation ? u sed to control other i/o devices or control leds ? when t he ge neral out put port da ta i s se t t o a hi gh level, the related pin will output a vdd voltage level while the related pin will output a gnd voltage level when the general output port data is cleared to a low level ? relationship between the general output port data and the output pin status p2 p1 display state of general output port comment 0 0 sets p2 to low; sets p1 to low 0 1 sets p2 to low; sets p1 to high 1 0 sets p2 to high; sets p1 to low 1 1 sets p2 to high; sets p1 to high default state when power is applied or when the rst input is at a low level. display duty set command byte r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 1st w 1 0 0 * * d2 d1 d0 *: dont care the display duty set command des criptions are described by the following: ? d2~d0: display duty selections ? the d isplay duty adjusts the contrast in 8 stages using 3 selection bits to adjust the pulse width of the segment output. ? the relationship between the setup data and the grid duty is shown in the table. hex d2 d1 d0 grid duty comment 0 0 0 0 8/16 default state when power is applied or when rst input is at a low level. 1 0 0 1 9/16 2 0 1 0 10/16 3 0 1 1 11/16 4 1 0 0 12/16 5 1 0 1 13/16 6 1 1 0 14/16 7 1 1 1 15/16
rev. 1.00 18 january 18, 2012 ht16523 number of digits set command byte r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 1st w 1 0 1 * * k2 k1 k0 *: dont care the number of digits set command descriptions is are described by the following: ? k2~k0: number of digit selections ? the number of display digits can be from 9 to 16 digits using the 3 selection bits. ? the relationship between setup data and the displayed grid is shown in the table. hex k2 k1 k0 number of digits of grid comment 0 0 0 0 g1 to g16 default state when power is applied or when the rst input is at a low level. 1 0 0 1 g1 to g9 2 0 1 0 g1 to g10 3 0 1 1 g1 to g11 4 1 0 0 g1 to g12 5 1 0 1 g1 to g13 6 1 1 0 g1 to g14 7 1 1 1 g1 to g15 all display lights on/off set command byte r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 1st w 1 1 0 * d s h l *: dont care the display on/off set command des criptions are described by the following: ? s bit: s=1 is standby mode; s=0 is normal mode ? d bit: d=1 is display on; d=0 is display off ? h bit: set all lights on ? l bit: set all lights off ? when s bit = 1, the internal oscillator stops and all outputs are set to low and the general port is set to high (p2 and p1 are all at high levels) ? when s bit = 1, all registers will keep their original value ? after being woken up, the device will set the s and d bits to 0 ? the all display lights on command is used primarily for display testing ? the all display lights off command is primarily used for display fashing ? the command bits , including d, h and l bits , cannot control the general output port ? the relationship between the control bits and display state of g1~g16, s1~s35 and ad1~ad2 pins is shown in the table. d s h l driver output status comment 1 0 0 0 normal display 1 0 0 1 sets all segments and sets all segments and ad to low. all grids maintain scan general ports active ad to low 1 0 1 * sets all segments and ad to high all grids maintain scan general ports active 0 0 * * sets all segments and ad to low sets all grids to low general ports active display off mode (default state when power is applied or when the rst input is at a low level.) * 1 * * sets all segments and ad to low. sets all grids to low. set general ports to high. standby mode *: dont care wake-up setting the wake-up behavior is described by the following: ? the device is woken up when a cs low pulse is asserted i.e. when a cs signal falling edge occurs. ? the d and s control bits described in the preceding section will be set to 0 - display off mode ? the oscillator starts to oscillate after wake-up ? the vfd driver does not display until the host mcu transmits commands to it. wake - up cs sck si test command byte r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 1st w 1 1 1 0 0 0 0 0 the test command is described by the following: ? only when the test pin is high is the test command e0h is valid ? this command is used by holtek for internal testing.
rev. 1.00 19 january 18, 2012 ht16523 setting flowchart power applied included apply vdd apply vh all display lights off general output port setting number of digits setting display duty setting cgram data write mode (with address setting) cgram character code cgram is character code write ended? address is automatically incremented no adram data write mode (with address setting) adram character code adram is character code write ended? address is automatically incremented no ddram data write mode (with address setting) ddram character code ddram is character code write ended? address is automatically incremented no another ram to be set? yes yes yes yes select a ram to be used status of all outputs by rst signal input releases all display lights off mode end no display operation mode
rev. 1.00 20 january 18, 2012 ht16523 power-off flowchart display operation mode turn off vh turn off vdd
rev. 1.00 21 january 18, 2012 ht16523 application circuit rst pin is connected to a mcu micro- controller ad1-2 s1-35 g1-16 vh p1-2 vdd led 2 test osci vss gnd r1 c1 2 35 16 r4 r3 c4 vh rst vdd csb sck si vddvss vdd c3 zd 5x7 dot matrix fluorescent display tube vdd rst pin is connected to external resistor and capacitor micro- controller ad1-2 s1-35 g1-16 vh p1-2 vdd led 2 test osci vss gnd r1 c1 2 35 16 r4 r3 c4 vh rst vdd csb sck si vddvss vdd c3 c2 r2 zd 5x7 dot matrix fluorescent display tube vdd note: 1. the vdd value depends on the power supply voltage of the microcontroller used. adjust the values of the components r2 , r4 , c2 , c3 and c4 according to the power supply voltage used. 2. the vh value depends on the fuorescent display tube used. adjust the value s of the components r3 and zd according to the power supply voltage used. 3. r1=120k, c1=0.1f.
rev. 1.00 22 january 18, 2012 ht16523 package information 64-pin lqfp (7mm x 7mm) outline dimensions lqfp outline dimensions 64-pin lqfp (7mm 7mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.350 0.358 b 0.272 0.280 c 0.350 0.358 d 0.272 0.280 e 0.016 f 0.005 0.009 g 0.053 0.057 h 0.063 i 0.002 0.006 j 0.018 0.030 k 0.004 0.008 07 symbol dimensions in mm min. nom. max. a 8.90 9.10 b 6.90 7.10 c 8.90 9.10 d 6.90 7.10 e 0.40 f 0.13 0.23 g 1.35 1.45 h 1.60 i 0.05 0.15 j 0.45 0.75 k 0.09 0.20 07 package information 1 february 8, 2010 symbol dimensions in inch min. nom. max. a 0.350 D 0.358 b 0.272 D 0.280 c 0.350 D 0.358 d 0.272 D 0.280 e D 0.016 D f 0.005 D 0.009 g 0.053 D 0.057 h D D 0.063 i 0.002 D 0.006 j 0.018 D 0.030 k 0.004 D 0.008 0 D 7 symbol dimensions in mm min. nom. max. a 8.90 D 9.10 b 6.90 D 7.10 c 8.90 D 9.10 d 6.90 D 7.10 e D 0.40 D f 0.13 D 0.23 g 1.35 D 1.45 h D D 1.60 i 0.05 D 0.15 j 0.45 D 0.75 k 0.09 D 0.20 0 D 7
rev. 1.00 23 january 18, 2012 ht16523 holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales offce) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shenzhen sales offce) 5f, unit a, productivity building, no.5 gaoxin m 2nd road, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor (usa), inc. (north america sales offce) 46729 fremont blvd., fremont, ca 94538, usa tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com copyright ? 2012 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek assumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek's products are not authorized for use as critical components in life vxssruwghylfhvruvvwhpvrowhnuhvhuyhvwkhuljkwwrdowhulwvsurgxfwvzlwkrxwsulruqrwlfdwlrq)ru the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

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