1/4 status of this document the japanese version of this doc ument is the formal specification. a customer may use this translation version only for a reference to help reading the formal version. if there are any differences in tr anslation version of this document, for mal version takes priority. rev. a structure silicon monolithic integrated circuit product name irda controller lsi built-in ir remote control model name BU92747GUW outer dimension figure 1 outer dimensions features ~ data transfer speed (bps) irda sir: 2.4kbps, 9.6kbps, 19.2 kbps, 38.4kbps, 57.6kbps and 115.2kbps irda mir: 0.576mbps, 1.152mbps irda fir: 4mbps irsimple ~ interface 16-bit data bus , address a 0-3 ~ built-in 2560 2byte fifo buffer (for transmission and reception) ~ accessible as a memory device connected to the bus ~ power down mode setting possible for transmission and reception ~ input clock of 48mhz for external input clock and crystal input clock ~ ir remote control function serial 2-lines sda, and scl *this lsi chip is not subject to radiation-proof design. ? absolute maximum rating ta = 2 5 c unless otherwise stated item symbol minimum maximum unit supply voltage *1 v dd -0.3 2.5 v interface supply voltage1 *1 v io1 -0.3 4.5 v interface supply voltage2 *1 v io2 -0.3 4.5 v input voltage *1 v in -0.3 v io1, 2 +0.3 v power dissipation *2 pd - 800 mw operating temperature range t opr -40 85 c storage temperature range t stg -55 125 c *1 it applies to all pins based on the gnd pin. *2 measured value with conformity substrate to semi (114.3mm 76.2mm 1.6mm z 4layer) 8.0mw/ ? decrease over ta=25 ? use ? operation range item symbol minimum st andard maximum unit supply voltage v dd 1.62 1.8 1.98 v interface supply voltage1 v io1 1.62 1.8 3.6 v interface supply voltage2 *3 v io2 1.62 1.8 3.6 v *3 v io2 is connected with xin/clk48m, xout, pwdn, nirq and reset.
2/4 rev. a ? electrical characterist ics (dc characteristics) ta = 2 5 c, v dd =1.8v, v io1 =1.8v, v io2 =1.8v and gnd=0v unless otherwise stated standard value item symbol min typ max unit remarks dissipation current 1 i dd 1 - 0.1 10 a for input with no output load = 0v dissipation current 2 i dd 2 - 10 30 ma for xin = 48mhz digital high-level input voltage v ih 0.75 v io - - v digital low-level input voltage v il - - 0.25 v io v - - 10 a input voltage level 1.8v digital high-level input current i ih - - 100 a input voltage level 1.8v test1-3 digital low-level input current i il - - 10 a input voltage level gnd digital high-level output voltage v oh v io -0.6 - - v intr, d 0-15 , irdapwdown, irtx, irrc, nirq, ctla ioh=-1ma digital low-level output voltage v ol - - 0.6 v intr, d 0-15 , irdapwdown, irtx, irrc, sda, nirq, ctla iol=1ma ? pin description pin name i / o condition of after reset pin function circuit diagram irrx i - irda receive input pin b extir i - signal input pin in sm2="h" (input signal is outputted to irtx or irrc) b irtx o l irda and remote control transmission output pin transmission irda when rc_en= "l" transmission remote control when rc_en="h", rc_mode="h" a d 0-15 i / o input data i/o pin c a 0-3 i - address input pin b cs i - chip select pin. low (l) active the read/write signal goes ?active? in a low period. b rd i - read signal input pin. low (l) active b wr i - write signal input pin. low (l) active b intr o h cpu interrupt request output pin (irda controller) the signal goes ?low? when an interrupt condition takes place. a reset i - reset input pin. low (l) active the signal causes the internal regist er settings, etc. to be initialized. b pwdn i - power down mode setting. low (l) active when set to low (l), this signal causes the wait status and sets the low dissipation current mode. after the power down mode is removed, reset=l must set to low until crysta l clock oscillatio n becomes stable (about 2 or 3 ms). after that reset must set to high. take it into consideration that this period depends on the crystal in use. b irrc o l remote control transmission output pin transmission remote control when rc_en= "h", rc_mode= "l" a ctla o l control signal output pin a scl i - serial clock f sda i/o input serial data i/o pin g nirq o h cpu interrupt request output pin (ir remote control) the signal goes ?low? when an interrupt condition takes place. a xin/clk48m i - crystal in / external clk input e xout o - crystal out (n.c when external input clock is used) e test1-3 i - test pins (these pins must be gnd during normal operation.) d irda pwdown o h irda module control signal output pin these pins must be open for irda modules having no power-down pin. a v dd - - power supply pin - v io1 - - interface power supply voltage1 - v io2 - - interface power supply voltage2 - gnd - - ground pin -
3/4 rev. a ? equivalent circuit diagram ? outer dimensions figure1 outer dimensions(vbga048w040) vbga048w040 land matrix table land matrix no. pin name land matrix no. pin name land matrix no. pin name land matrix no. pin name a1 pwdn c1 v io2 e1 a 2 g1 gnd a2 xout c2 nirq e2 a 1 g2 d 5 a3 scl c3 reset e3 a 0 g3 d 4 a4 irrc c4 (nc) e4 d 15 g4 d 3 a5 irtx c5 extir e5 d 14 g5 d 2 a6 irrx c6 v io1 e6 d 13 g6 d 1 a7 gnd c7 rd e7 d 12 g7 d 0 (nc) (nc) d1 v io1 f1 d 11 b2 xin d2 a 3 f2 v dd b3 sda d3 test1 f3 d 10 b4 ctla d4 test2 f4 d 9 b5 irdapwdn d5 test3 f5 d 8 b6 v dd d6 intr f6 d 7 b7 wr d7 cs f7 d 6 " 9 * / 9 0 6 5 1 8 % / # $ % & |