View IR2010S_4587176.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

features ? floating channel designed for bootstrap operation fully operational to 200v tolerant to negative transient voltage, dv/dt immune ? gate drive supply range from 10 to 20v ? undervoltage lockout for both channels ? 3.3v logic compatible separate logic supply range from 3.3v to 20v logic and power ground 5v of fset ? cmos schmitt-triggered inputs with pull-down ? shut down input turns off both channels ? matched propagation delay for both channels ? outputs in phase with inputs packages high and low side driver product summary v offset 200v max. i o +/- 3.0a / 3.0a typ. v out 10 - 20v t on/off 95 & 65 ns typ. delay matching 15 ns max. description the ir2010 is a high power, high voltage, high speed power mosfet and igbt drivers with independent high and low side referenced output channels, ideal for audio class d and dc-dc converter applications. logic inputs are compatible with standard cmos or lsttl output, down to 3.0v logic. the output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. propagation de- lays are matched to simplify use in high frequency applications. the floating channel can be used to drive an n-channel power mosfet or igbt in the high side configura- tion which operates up to 200 volts. proprietary hvic and latch immune cmos tech- nologies enable ruggedized monolithic construction. ir2010 ( s ) 14-lead pdip 16-lead soic www.irf.com 1 typical connection hin 200v to load v dd v b v s ho lo com hin lin v ss sd v cc lin v dd sd v ss v cc (refer to lead assignments for correct configuration). this/these diagram(s) show electrical connections only. please refer to our application notes and designtips for proper circuit board layout. data sheet no. pd60195-c applications ? audio class d amplifiers ? high power dc-dc smps converters ? other high frequency applications
2 www.irf.com ir2010 ( s ) (please refer to the design tip dt97-3 for more details). note 1: logic operational for v s of -4 to +200v. logic state held for v s of -4v to -v bs . note 2: when v dd < 5v, the minimum v ss offset is limited to -v dd. symbol definition min. max. units v b high side floating supply absolute voltage v s + 10 v s + 20 v s high side floating supply offset voltage note 1 200 v ho high side floating output voltage v s v b v cc low side fixed supply voltage 10 20 v lo low side output voltage 0 v cc v dd logic supply voltage v ss + 3 v ss + 20 v ss logic supply offset voltage -5 (note 2) 5 v in logic input voltage (hin, lin & sd) v ss v dd t a ambient temperature -40 125 c recommended operating conditions the input/output logic timing diagram is shown in figure 1. for proper operation the device should be used within the recommended conditions. the v s and v ss offset ratings are tested with all supplies biased at 15v differential. typical ratings at other bias conditions are shown in figures 24 and 25. v absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. all voltage param- eters are absolute voltages referenced to com. the thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. symbol definition min. max. units v b high side floating supply voltage -0.3 225 v s high side floating supply offset voltage v b - 25 v b + 0.3 v ho high side floating output voltage v s - 0.3 v b + 0.3 v cc low side fixed supply voltage -0.3 25 v lo low side output voltage -0.3 v cc + 0.3 v dd logic supply voltage -0.3 v ss + 25 v ss logic supply offset voltage v cc - 25 v cc + 0.3 v in logic input voltage (hin, lin & sd) v ss - 0.3 v dd + 0.3 dv s /dt allowable offset supply voltage transient (figure 2) ? 50 v/ns p d package power dissipation @ t a +25 c (14 lead dip) ? 1.6 (16 lead soic) ? 1.25 r thja thermal resistance, junction to ambient (14 lead dip) ? 75 (16 lead soic) ? 100 t j junction temperature ? 150 t s storage temperature -55 150 t l lead temperature (soldering, 10 seconds) ? 300 c/w w v c
www.irf.com 3 ir2010 ( s ) symbol definition figure min. typ. max. units test conditions t on turn-on propagation delay 7 50 95 135 v s = 0v t off turn-off propagation delay 8 30 65 105 v s = 200v t sd shutdown propagation delay 9 35 70 105 v s = 200v t r turn-on rise time 10 ? 10 20 t f turn-off fall time 11 ? 15 25 mt delay matching, hs & ls turn-on/off 6 ? ? 15 ns dynamic electrical characteristics v bias (v cc , v bs , v dd ) = 15v, c l = 1000 pf, t a = 25 c and v ss = com unless otherwise specified. the dynamic electrical characteristics are measured using the test circuit shown in figure 3. symbol definition figure min. typ. max. units test conditions v ih logic ?1? input voltage 12 9.5 ? ? v il logic ?0? input voltage 13 ? ? 6.0 v ih logic ?1? input voltage 12 2 ? ? v il logic ?0? input voltage 13 ? ? 1 v oh high level output voltage, v bias - v o 14 ? ? 1.0 i o = 0a v ol low level output voltage, v o 15 ? ? 0.1 i o = 0a i lk offset supply leakage current 16 ? ? 50 v b =v s = 200v i qbs quiescent v bs supply current 17 ? 70 210 v in = 0v or v dd i qcc quiescent v cc supply current 18 ? 100 230 v in = 0v or v dd i qdd quiescent v dd supply current 19 ? 1 5 v in = 0v or v dd i in+ logic ?1? input bias current 20 ? 20 40 v in = v dd i in- logic ?0? input bias current 21 ? ? 1.0 v in = 0v v bsuv+ v bs supply undervoltage positive going 22 7.5 8.6 9.7 threshold v bsuv- v bs supply undervoltage negative going 23 7.0 8.2 9.4 threshold v ccuv+ v cc supply undervoltage positive going 24 7.5 8.6 9.7 threshold v ccuv- v cc supply undervoltage negative going 25 7.0 8.2 9.4 threshold i o+ output high short circuit pulsed current 26 2.5 3.0 ? v o = 0v, v in = v dd pw 10 s i o- output low short circuit pulsed current 27 2.5 3.0 ? v o = 15v, v in = 0v pw 10 s v a v a static electrical characteristics v bias (v cc , v bs , v dd ) = 15v, t a = 25 c and v ss = com unless otherwise specified. the v in , v th and i in parameters are referenced to v ss and are applicable to all three logic input leads: hin, lin and sd. the v o and i o parameters are referenced to com and are applicable to the respective output leads: ho or lo. v dd = 15v v dd = 3.3v
4 www.irf.com ir2010 ( s ) functional block diagram lead definitions symbol description 14 lead pdip 16 lead soic (wide body) ir2010 IR2010S part number lead assignments v dd logic supply hin logic input for high side gate driver output (ho), in phase sd logic input for shutdown lin logic input for low side gate driver output (lo), in phase v ss logic ground v b high side floating supply ho high side gate drive output v s high side floating supply return v cc low side supply lo low side gate drive output com low side return v b sd lin v dd v ss uv detect delay v cc uv detect lo v s com s r uv q hin ho level shift circuit v ss /com level shift level shift v ss /com
www.irf.com 5 ir2010 ( s ) figure 1. input/output timing diagram figure 2. floating supply voltage transient test circuit figure 3. switching time test circuit figure 4. switching time waveform definition figure 6. delay matching waveform definitions figure 5. shutdown waveform definitions hin lin t r t on t f t off ho lo 50% 50% 90% 90% 10% 10% hin lin ho 50% 50% 10% lo 90% mt ho lo mt (0 to 200v) hin lin sd ho lo sd t sd ho lo 50% 90% hv =10 to 200v <50 v/ns
6 www.irf.com ir2010 ( s ) figure 8a. turn-off time vs. temperature figure 8b. turn-off time vs. v cc /v bs voltage figure 7a. turn-on time vs. temperature figure 7b. turn-on time vs. v cc /v bs voltage figure 7c. turn-on time vs v dd voltage figure 8c. turn-off time vs. v dd voltage 0 50 100 150 200 250 -50 -25 0 25 50 75 100 125 temperature (c) turn-on time (ns ) 0 50 100 150 200 250 10 12 14 16 18 20 v cc /v bs supply voltage (v) turn-on time (ns ) 0 50 100 150 200 250 300 0 2 4 6 8 101214161820 v dd supply voltage (v) turn-on time (ns ) 0 50 100 150 200 250 -50 -25 0 25 50 75 100 125 temperature (c) turn-off time (ns ) max typ max ty p max ty p max ty p max ty p 0 50 100 150 200 250 300 0 2 4 6 8 101214161820 vdd supply voltage (v) turn-off time (ns) max typ 0 50 100 150 200 250 10 12 14 16 18 20 v cc /v bs supply voltage (v) turn-off time (ns)
www.irf.com 7 ir2010 ( s ) figure 9a. shutdown time vs. temperature figure 9c. shutdown time vs v dd voltage figure 9b. shutdown time vs. v cc /v bs voltage figure 10a. turn-on rise time vs. temperature figure 10b. turn-on rise time vs. v bias voltage figure 11a. turn-off fall time vs. temperature 0 10 20 30 40 10 12 14 16 18 20 v bia s supply voltage (v) turn-on rise time (ns) max typ 0 10 20 30 40 -50 -25 0 25 50 75 100 125 temperature (c) turn-on rise time (ns ) max typ 0 50 100 150 200 250 -50 -25 0 25 50 75 100 125 temperature (c) shutdown time (ns ) max typ 0 50 100 150 200 250 300 0 2 4 6 8 10 12 14 16 18 20 v dd supply voltage (v) shutdown time (ns ) 0 10 20 30 40 -50 -25 0 25 50 75 100 125 temperature (c) turn-off fall time (ns ) max typ s) 0 50 100 150 200 250 10 12 14 16 18 20 max ty p shutdown t ime (ns) v cc /v bs supply voltage (v)
8 www.irf.com ir2010 ( s ) figure 11b. turn-off fall time vs. v bias voltage figure 12b. logic ?1? input threshold vs. v dd voltage figure 12a. logic ?1? input threshold vs. temperature figure 13a. logic ?0? input threshold vs. temperature figure 13b. logic ?0? input threshold vs. v dd voltage figure 14a. high level output vs. temperature 0 3 6 9 12 15 -50 -25 0 25 50 75 100 125 temperature (c) logic '0' input threshold (v ) max 0 1 2 3 4 5 -50 -25 0 25 50 75 100 125 temperature (c) high level output (v) max 0 10 20 30 40 10 12 14 16 18 20 v bi as supply voltage (v) turn-off fall time (ns ) max typ 0 3 6 9 12 15 -50 -25 0 25 50 75 100 125 temperature (c) logic '1' input threshold (v ) min 0 3 6 9 12 15 0 2 4 6 8 101214161820 v dd logic supply voltage (v) logic '1' input threshold (v min ) 0 3 6 9 12 15 02468101214161820 v dd logic supply voltage (v) logic '0' input threshold (v ) max
www.irf.com 9 ir2010 ( s ) figure 15b. low level output vs. v bias voltage figure 16a. offset supply current vs. temperature figure 16b. offset supply current vs. offset voltage figure 14b. high level output vs. v bias voltage figure 15a. low level output vs. temperature figure 17a. vbs supply current vs. temperature 0.0 0.2 0.4 0.6 0.8 1.0 -50 -25 0 25 50 75 100 125 max 0.0 0.2 0.4 0.6 0.8 1.0 10 12 14 16 18 20 v bias supply voltage (v) low level output (v) max 0 100 200 300 -50 -25 0 25 50 75 100 125 max 0 1 2 3 4 5 10 12 14 16 18 20 v bias supply voltage (v) high level output (v ) max 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 temperature (c) v bs supply current (ua) max typ 0 20 40 60 80 100 0 20 40 60 80 100 120 140 160 180 200 max low level output (v) temperature (c) temperature (c) offset supply current (ua) offset supply voltage (v) offset supply current (ua)
10 www.irf.com ir2010 ( s ) figure 17b. vbs supply current vs. v bs voltage figure 19b. vdd supply current vs. v dd voltage figure 20a. logic ?1? input current vs. temperature figure 18a. vcc supply current vs. temperature figure 18b. vcc supply current vs. v cc voltage figure 19a. vdd supply current vs. temperature 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 temperature (c) v cc supply current (ua) max typ 0 100 200 300 400 500 10 12 14 16 18 20 v bs floating supply voltage (v) v bs supply current (ua) max typ 0 100 200 300 400 500 10 12 14 16 18 20 v cc voltage (v) v cc supply current (ua) typ max 0 5 10 15 20 -50 -25 0 25 50 75 100 125 temperature (c) v dd supply current (ua) typ max 0 2 4 6 8 10 2 4 6 8 10 12 14 16 18 20 v dd voltage (v) v dd supply current (ua) typ max 0 20 40 60 80 100 -50 -25 0 25 50 75 100 125 temperature (c) logic '1' input current (ua) typ max
www.irf.com 11 ir2010 ( s ) figure 22. v bs undervoltage (+) vs. temperature figure 23. v bs undervoltage (-) vs. temperature figure 24. v cc undervoltage (+) vs. temperature figure 20b. logic ?1? input current vs. v dd voltage figure 21a. logic ?0? input current vs. temperature figure 21b. logic ?0? input current vs. v dd voltage 6.0 7.0 8.0 9.0 10.0 11.0 -50 -25 0 25 50 75 100 125 temperature (c) v bs undervoltage lockout + (v) max. typ. min. 6.0 7.0 8.0 9.0 10.0 11.0 -50 -25 0 25 50 75 100 125 temperature (c) v bs undervoltage lockout - (v) max. typ. min. 6.0 7.0 8.0 9.0 10.0 11.0 -50 -25 0 25 50 75 100 125 temperature (c) v cc undervoltage lockout + (v) max. typ. min. 0.0 1.0 2.0 3.0 4.0 5.0 -50-25 0 25 50 75100125 temperature (c) logic '0' input current (ua) max 0 20 40 60 80 100 2 4 6 8 101214161820 v dd voltage (v) typ max 0.0 1.0 2.0 3.0 4.0 5.0 2 4 6 8 101214161820 max v dd voltage (v) logic ?0? input current (ua) logic ?1? input current (ua)
12 www.irf.com ir2010 ( s ) 6.0 7.0 8.0 9.0 10.0 11.0 -50-25 0 255075100125 temperature (c) max. typ. min. figure 26a. output source current vs. temperature figure 26b. output source current vs. v bias voltage figure 27a. output sink current vs. temperature figure 25. v cc undervoltage (-) vs. temperature figure 27b. output sink current vs. v bias voltage figure 28. ir2010 tj vs frequency r gate = 10 ohm, vcc = 15v with irfpe50 0.0 1.0 2.0 3.0 4.0 5.0 -50 -25 0 25 50 75 100 125 temperature (c) output sink current (ua) typ min 0.0 1.0 2.0 3.0 4.0 5.0 10 12 14 16 18 20 vbias supply voltage (v) output sink current (ua) typ min 0.00 25.00 50.00 75.00 100.00 125.00 150.00 1.e + 03 1.e + 04 1.e + 05 1.e + 06 frequency (h z ) 200v 10v 100v 0.0 1.0 2.0 3.0 4.0 5.0 -50-25 0 25 50 75100125 temperature (c) output source current (ua) min typ 0.0 1.0 2.0 3.0 4.0 5.0 10 12 14 16 18 20 vbias supply voltage (v) output source current (ua) typ min vcc undervoltage lockout - (v) junction t emperature (c)
www.irf.com 13 ir2010 ( s ) figure 29. ir2010 tj vs frequency r gate = 16 ohm, vcc = 15v with irfbc40 figure 30. ir2010 tj vs frequency r gate = 22 ohm, vcc = 15v with irfbc30 0.00 25.00 50.00 75.00 100.00 125.00 150.00 1.e + 03 1.e + 04 1.e + 05 1.e + 06 frequ ency (h z) ju ncti on tem perature (c ) 200v 100v 10v 0.00 25.00 50.00 75.00 100.00 125.00 150.00 1.e + 03 1.e + 04 1.e + 05 1.e + 06 frequency (h z) ju ncti on tem perature (c ) 200v 100v 10v 0.00 25.00 50.00 75.00 100.00 125.00 150.00 1.e + 03 1.e + 04 1.e + 05 1.e + 06 frequ ency (h z) ju ncti on tem perature (c ) 200v 100v 10v figure 31. ir2010 tj vs frequency r gate = 33 ohm, vcc = 15v with irfbc20 0.00 25.00 50.00 75.00 100.00 125.00 150.00 1.e + 03 1.e + 04 1.e + 05 1.e + 06 freq uen cy (h z) ju ncti on tem perature (c ) 200v 100v 10v figure 32. IR2010S tj vs frequency r gate = 10 ohm, vcc = 15v with irfpe50
14 www.irf.com ir2010 ( s ) figure 33. IR2010S tj vs frequency r gate = 16 ohm, vcc = 15v with irfbc40 0.00 25. 00 50. 00 75. 00 100.00 125.00 150.00 1.e + 03 1.e + 04 1.e + 05 1.e + 06 200v 100v 10v 0.00 25.00 50.00 75.00 100.00 125.00 150.00 1.e + 03 1.e + 04 1.e + 05 1.e + 06 200v 100v 10v figure 34. IR2010S tj vs frequency r gate = 22 ohm, vcc = 15v with irfbc30 figure 35. IR2010S tj vs frequency r gate = 33 ohm, vcc = 15v with irfbc20 0.00 25.00 50.00 75.00 100.00 125.00 150.00 1.e +03 1.e +04 1.e +05 1.e +06 200v 100v 10v junction t emperature (c) junction temperature (c) junction t emperature (c) frequency (hz) frequency (hz) frequency (hz)
www.irf.com 15 ir2010 ( s ) 16 lead soic (wide body) 01 6012 01-3014 03 (ms-013aa) ir world headquarters: 233 kansas st., el segundo, california 90245 tel: (310) 252-7105 data and specifications subject to change without notice. 2/7/2003 01-6010 01-3002 03 (ms-001ac) 14 lead pdip case outlines

▲Up To Search▲

Price & Availability of IR2010S

	To Download IR2010S Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .